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[SCSI] qla2xxx: Clear mailbox busy flag during premature mailbox completion for ISP82xx.
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_mbx.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/delay.h>
5a0e3ad6 10#include <linux/gfp.h>
1da177e4 11
1da177e4
LT		 12
13/*
14 * qla2x00_mailbox_command
15 * Issue mailbox command and waits for completion.
16 *
17 * Input:
18 * ha = adapter block pointer.
19 * mcp = driver internal mbx struct pointer.
20 *
21 * Output:
22 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
23 *
24 * Returns:
25 * 0 : QLA_SUCCESS = cmd performed success
26 * 1 : QLA_FUNCTION_FAILED (error encountered)
27 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
28 *
29 * Context:
30 * Kernel context.
31 */
32static int
7b867cf7 33qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
1da177e4
LT		 34{
35 int rval;
36 unsigned long flags = 0;
2c3dfe3f 37 device_reg_t __iomem *reg;
1c7c6357 38 uint8_t abort_active;
2c3dfe3f 39 uint8_t io_lock_on;
cdbb0a4f 40 uint16_t command = 0;
1da177e4
LT		 41 uint16_t *iptr;
42 uint16_t __iomem *optr;
43 uint32_t cnt;
44 uint32_t mboxes;
1da177e4 45 unsigned long wait_time;
7b867cf7
AC		 46 struct qla_hw_data *ha = vha->hw;
47 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 48
7c3df132
SK		 49 ql_dbg(ql_dbg_mbx, base_vha, 0x1000, "Entered %s.\n", __func__);
50
51 if (ha->pdev->error_state > pci_channel_io_frozen) {
52 ql_log(ql_log_warn, base_vha, 0x1001,
53 "error_state is greater than pci_channel_io_frozen, "
54 "exiting.\n");
b9b12f73 55 return QLA_FUNCTION_TIMEOUT;
7c3df132 56 }
b9b12f73 57
a9083016 58 if (vha->device_flags & DFLG_DEV_FAILED) {
7c3df132
SK		 59 ql_log(ql_log_warn, base_vha, 0x1002,
60 "Device in failed state, exiting.\n");
a9083016
GM		 61 return QLA_FUNCTION_TIMEOUT;
62 }
63
2c3dfe3f 64 reg = ha->iobase;
7b867cf7 65 io_lock_on = base_vha->flags.init_done;
1da177e4
LT		 66
67 rval = QLA_SUCCESS;
7b867cf7 68 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1c7c6357 69
1da177e4 70
85880801 71 if (ha->flags.pci_channel_io_perm_failure) {
7c3df132
SK		 72 ql_log(ql_log_warn, base_vha, 0x1003,
73 "Perm failure on EEH timeout MBX, exiting.\n");
85880801
AV		 74 return QLA_FUNCTION_TIMEOUT;
75 }
76
862cd01e
GM		 77 if (ha->flags.isp82xx_fw_hung) {
78 /* Setting Link-Down error */
79 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
7c3df132
SK		 80 ql_log(ql_log_warn, base_vha, 0x1004,
81 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
1806fcd5 82 return QLA_FUNCTION_TIMEOUT;
862cd01e
GM		 83 }
84
1da177e4 85 /*
1c7c6357
AV		 86 * Wait for active mailbox commands to finish by waiting at most tov
87 * seconds. This is to serialize actual issuing of mailbox cmds during
88 * non ISP abort time.
1da177e4 89 */
8eca3f39
AV		 90 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
91 /* Timeout occurred. Return error. */
7c3df132
SK		 92 ql_log(ql_log_warn, base_vha, 0x1005,
93 "Cmd access timeout, Exiting.\n");
8eca3f39 94 return QLA_FUNCTION_TIMEOUT;
1da177e4
LT		 95 }
96
97 ha->flags.mbox_busy = 1;
98 /* Save mailbox command for debug */
99 ha->mcp = mcp;
100
7c3df132
SK		 101 ql_dbg(ql_dbg_mbx, base_vha, 0x1006,
102 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
1da177e4
LT		 103
104 spin_lock_irqsave(&ha->hardware_lock, flags);
105
106 /* Load mailbox registers. */
a9083016
GM		 107 if (IS_QLA82XX(ha))
108 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
109 else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha))
1c7c6357
AV		 110 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
111 else
112 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
1da177e4
LT		 113
114 iptr = mcp->mb;
115 command = mcp->mb[0];
116 mboxes = mcp->out_mb;
117
118 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
119 if (IS_QLA2200(ha) && cnt == 8)
1c7c6357
AV		 120 optr =
121 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
1da177e4
LT		 122 if (mboxes & BIT_0)
123 WRT_REG_WORD(optr, *iptr);
124
125 mboxes >>= 1;
126 optr++;
127 iptr++;
128 }
129
7c3df132
SK		 130 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1111,
131 "Loaded MBX registers (displayed in bytes) =.\n");
132 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1112,
133 (uint8_t *)mcp->mb, 16);
134 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1113,
135 ".\n");
136 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1114,
137 ((uint8_t *)mcp->mb + 0x10), 16);
138 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1115,
139 ".\n");
140 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1116,
141 ((uint8_t *)mcp->mb + 0x20), 8);
142 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1117,
143 "I/O Address = %p.\n", optr);
144 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x100e);
1da177e4
LT		 145
146 /* Issue set host interrupt command to send cmd out. */
147 ha->flags.mbox_int = 0;
148 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
149
150 /* Unlock mbx registers and wait for interrupt */
7c3df132
SK		 151 ql_dbg(ql_dbg_mbx, base_vha, 0x100f,
152 "Going to unlock irq & waiting for interrupts. "
153 "jiffies=%lx.\n", jiffies);
1da177e4
LT		 154
155 /* Wait for mbx cmd completion until timeout */
156
124f85e6 157 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
1da177e4
LT		 158 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
159
a9083016
GM		 160 if (IS_QLA82XX(ha)) {
161 if (RD_REG_DWORD(&reg->isp82.hint) &
162 HINT_MBX_INT_PENDING) {
163 spin_unlock_irqrestore(&ha->hardware_lock,
164 flags);
8937f2f1 165 ha->flags.mbox_busy = 0;
7c3df132
SK		 166 ql_dbg(ql_dbg_mbx, base_vha, 0x1010,
167 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 168 rval = QLA_FUNCTION_TIMEOUT;
169 goto premature_exit;
a9083016
GM		 170 }
171 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
172 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 173 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
174 else
175 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4
LT		 176 spin_unlock_irqrestore(&ha->hardware_lock, flags);
177
0b05a1f0 178 wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
1da177e4 179
1da177e4
LT		 180 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
181
1da177e4 182 } else {
7c3df132
SK		 183 ql_dbg(ql_dbg_mbx, base_vha, 0x1011,
184 "Cmd=%x Polling Mode.\n", command);
1da177e4 185
a9083016
GM		 186 if (IS_QLA82XX(ha)) {
187 if (RD_REG_DWORD(&reg->isp82.hint) &
188 HINT_MBX_INT_PENDING) {
189 spin_unlock_irqrestore(&ha->hardware_lock,
190 flags);
8937f2f1 191 ha->flags.mbox_busy = 0;
7c3df132
SK		 192 ql_dbg(ql_dbg_mbx, base_vha, 0x1012,
193 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 194 rval = QLA_FUNCTION_TIMEOUT;
195 goto premature_exit;
a9083016
GM		 196 }
197 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
198 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 199 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
200 else
201 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4 202 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 203
204 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
205 while (!ha->flags.mbox_int) {
206 if (time_after(jiffies, wait_time))
207 break;
208
209 /* Check for pending interrupts. */
73208dfd 210 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4 211
85880801
AV		 212 if (!ha->flags.mbox_int &&
213 !(IS_QLA2200(ha) &&
214 command == MBC_LOAD_RISC_RAM_EXTENDED))
59989831 215 msleep(10);
1da177e4 216 } /* while */
7c3df132
SK		 217 ql_dbg(ql_dbg_mbx, base_vha, 0x1013,
218 "Waited %d sec.\n",
219 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
1da177e4
LT		 220 }
221
1da177e4
LT		 222 /* Check whether we timed out */
223 if (ha->flags.mbox_int) {
224 uint16_t *iptr2;
225
7c3df132
SK		 226 ql_dbg(ql_dbg_mbx, base_vha, 0x1014,
227 "Cmd=%x completed.\n", command);
1da177e4
LT		 228
229 /* Got interrupt. Clear the flag. */
230 ha->flags.mbox_int = 0;
231 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
232
7190575f 233 if (ha->flags.isp82xx_fw_hung) {
cdbb0a4f
SV		 234 ha->flags.mbox_busy = 0;
235 /* Setting Link-Down error */
236 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
237 ha->mcp = NULL;
238 rval = QLA_FUNCTION_FAILED;
7c3df132
SK		 239 ql_log(ql_log_warn, base_vha, 0x1015,
240 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
cdbb0a4f
SV		 241 goto premature_exit;
242 }
243
354d6b21 244 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
1da177e4 245 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 246
247 /* Load return mailbox registers. */
248 iptr2 = mcp->mb;
249 iptr = (uint16_t *)&ha->mailbox_out[0];
250 mboxes = mcp->in_mb;
251 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
252 if (mboxes & BIT_0)
253 *iptr2 = *iptr;
254
255 mboxes >>= 1;
256 iptr2++;
257 iptr++;
258 }
259 } else {
260
1c7c6357
AV		 261 uint16_t mb0;
262 uint32_t ictrl;
263
e428924c 264 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 265 mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
266 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
267 } else {
cca5335c 268 mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
1c7c6357
AV		 269 ictrl = RD_REG_WORD(&reg->isp.ictrl);
270 }
7c3df132
SK		 271 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1119,
272 "MBX Command timeout for cmd %x.\n", command);
273 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x111a,
274 "iocontrol=%x jiffies=%lx.\n", ictrl, jiffies);
275 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x111b,
276 "mb[0] = 0x%x.\n", mb0);
277 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1019);
1da177e4 278
1da177e4
LT		 279 rval = QLA_FUNCTION_TIMEOUT;
280 }
281
1da177e4
LT		 282 ha->flags.mbox_busy = 0;
283
284 /* Clean up */
285 ha->mcp = NULL;
286
124f85e6 287 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
7c3df132
SK		 288 ql_dbg(ql_dbg_mbx, base_vha, 0x101a,
289 "Checking for additional resp interrupt.\n");
1da177e4
LT		 290
291 /* polling mode for non isp_abort commands. */
73208dfd 292 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4
LT		 293 }
294
1c7c6357
AV		 295 if (rval == QLA_FUNCTION_TIMEOUT &&
296 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
85880801
AV		 297 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
298 ha->flags.eeh_busy) {
1da177e4 299 /* not in dpc. schedule it for dpc to take over. */
7c3df132
SK		 300 ql_dbg(ql_dbg_mbx, base_vha, 0x101b,
301 "Timeout, schedule isp_abort_needed.\n");
cdbb0a4f
SV		 302
303 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
304 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
305 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
306
7c3df132
SK		 307 ql_log(ql_log_info, base_vha, 0x101c,
308 "Mailbox cmd timeout occured. "
309 "Scheduling ISP abort eeh_busy=0x%x.\n",
310 ha->flags.eeh_busy);
cdbb0a4f
SV		 311 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
312 qla2xxx_wake_dpc(vha);
313 }
1da177e4 314 } else if (!abort_active) {
1da177e4 315 /* call abort directly since we are in the DPC thread */
7c3df132
SK		 316 ql_dbg(ql_dbg_mbx, base_vha, 0x101d,
317 "Timeout, calling abort_isp.\n");
cdbb0a4f
SV		 318
319 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
320 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
321 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
322
7c3df132
SK		 323 ql_log(ql_log_info, base_vha, 0x101e,
324 "Mailbox cmd timeout occured. "
325 "Scheduling ISP abort.\n");
cdbb0a4f
SV		 326
327 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
328 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
329 if (ha->isp_ops->abort_isp(vha)) {
330 /* Failed. retry later. */
331 set_bit(ISP_ABORT_NEEDED,
332 &vha->dpc_flags);
333 }
334 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
7c3df132
SK		 335 ql_dbg(ql_dbg_mbx, base_vha, 0x101f,
336 "Finished abort_isp.\n");
1da177e4 337 }
1da177e4
LT		 338 }
339 }
340
cdbb0a4f 341premature_exit:
1da177e4 342 /* Allow next mbx cmd to come in. */
8eca3f39 343 complete(&ha->mbx_cmd_comp);
1da177e4
LT		 344
345 if (rval) {
7c3df132
SK		 346 ql_dbg(ql_dbg_mbx, base_vha, 0x1020,
347 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, cmd=%x ****.\n",
348 mcp->mb[0], mcp->mb[1], mcp->mb[2], command);
1da177e4 349 } else {
7c3df132 350 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
1da177e4
LT		 351 }
352
1da177e4
LT		 353 return rval;
354}
355
1da177e4 356int
7b867cf7 357qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
590f98e5 358 uint32_t risc_code_size)
1da177e4
LT		 359{
360 int rval;
7b867cf7 361 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 362 mbx_cmd_t mc;
363 mbx_cmd_t *mcp = &mc;
1da177e4 364
7c3df132 365 ql_dbg(ql_dbg_mbx, vha, 0x1022, "Entered %s.\n", __func__);
1da177e4 366
e428924c 367 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
590f98e5 368 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
369 mcp->mb[8] = MSW(risc_addr);
370 mcp->out_mb = MBX_8|MBX_0;
1da177e4 371 } else {
590f98e5 372 mcp->mb[0] = MBC_LOAD_RISC_RAM;
373 mcp->out_mb = MBX_0;
1da177e4 374 }
1da177e4
LT		 375 mcp->mb[1] = LSW(risc_addr);
376 mcp->mb[2] = MSW(req_dma);
377 mcp->mb[3] = LSW(req_dma);
1da177e4
LT		 378 mcp->mb[6] = MSW(MSD(req_dma));
379 mcp->mb[7] = LSW(MSD(req_dma));
590f98e5 380 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
e428924c 381 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 382 mcp->mb[4] = MSW(risc_code_size);
383 mcp->mb[5] = LSW(risc_code_size);
384 mcp->out_mb |= MBX_5|MBX_4;
385 } else {
386 mcp->mb[4] = LSW(risc_code_size);
387 mcp->out_mb |= MBX_4;
388 }
389
1da177e4 390 mcp->in_mb = MBX_0;
b93480e3 391 mcp->tov = MBX_TOV_SECONDS;
1da177e4 392 mcp->flags = 0;
7b867cf7 393 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 394
1da177e4 395 if (rval != QLA_SUCCESS) {
7c3df132
SK		 396 ql_dbg(ql_dbg_mbx, vha, 0x1023,
397 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4 398 } else {
7c3df132 399 ql_dbg(ql_dbg_mbx, vha, 0x1024, "Done %s.\n", __func__);
1da177e4
LT		 400 }
401
402 return rval;
403}
404
cad454b1 405#define EXTENDED_BB_CREDITS BIT_0
1da177e4
LT		 406/*
407 * qla2x00_execute_fw
1c7c6357 408 * Start adapter firmware.
1da177e4
LT		 409 *
410 * Input:
1c7c6357
AV		 411 * ha = adapter block pointer.
412 * TARGET_QUEUE_LOCK must be released.
413 * ADAPTER_STATE_LOCK must be released.
1da177e4
LT		 414 *
415 * Returns:
1c7c6357 416 * qla2x00 local function return status code.
1da177e4
LT		 417 *
418 * Context:
1c7c6357 419 * Kernel context.
1da177e4
LT		 420 */
421int
7b867cf7 422qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 423{
424 int rval;
7b867cf7 425 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 426 mbx_cmd_t mc;
427 mbx_cmd_t *mcp = &mc;
428
7c3df132 429 ql_dbg(ql_dbg_mbx, vha, 0x1025, "Entered %s.\n", __func__);
1da177e4
LT		 430
431 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
1c7c6357
AV		 432 mcp->out_mb = MBX_0;
433 mcp->in_mb = MBX_0;
e428924c 434 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 435 mcp->mb[1] = MSW(risc_addr);
436 mcp->mb[2] = LSW(risc_addr);
437 mcp->mb[3] = 0;
cad454b1
SV		 438 if (IS_QLA81XX(ha)) {
439 struct nvram_81xx *nv = ha->nvram;
440 mcp->mb[4] = (nv->enhanced_features &
441 EXTENDED_BB_CREDITS);
442 } else
443 mcp->mb[4] = 0;
8b3253d1 444 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
1c7c6357
AV		 445 mcp->in_mb |= MBX_1;
446 } else {
447 mcp->mb[1] = LSW(risc_addr);
448 mcp->out_mb |= MBX_1;
449 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
450 mcp->mb[2] = 0;
451 mcp->out_mb |= MBX_2;
452 }
1da177e4
LT		 453 }
454
b93480e3 455 mcp->tov = MBX_TOV_SECONDS;
1da177e4 456 mcp->flags = 0;
7b867cf7 457 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 458
1c7c6357 459 if (rval != QLA_SUCCESS) {
7c3df132
SK		 460 ql_dbg(ql_dbg_mbx, vha, 0x1026,
461 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357 462 } else {
e428924c 463 if (IS_FWI2_CAPABLE(ha)) {
7c3df132
SK		 464 ql_dbg(ql_dbg_mbx, vha, 0x1027,
465 "Done exchanges=%x.\n", mcp->mb[1]);
1c7c6357 466 } else {
7c3df132 467 ql_dbg(ql_dbg_mbx, vha, 0x1028, "Done %s.\n", __func__);
1c7c6357
AV		 468 }
469 }
1da177e4
LT		 470
471 return rval;
472}
473
474/*
475 * qla2x00_get_fw_version
476 * Get firmware version.
477 *
478 * Input:
479 * ha: adapter state pointer.
480 * major: pointer for major number.
481 * minor: pointer for minor number.
482 * subminor: pointer for subminor number.
483 *
484 * Returns:
485 * qla2x00 local function return status code.
486 *
487 * Context:
488 * Kernel context.
489 */
ca9e9c3e 490int
7b867cf7 491qla2x00_get_fw_version(scsi_qla_host_t *vha, uint16_t *major, uint16_t *minor,
3a03eb79 492 uint16_t *subminor, uint16_t *attributes, uint32_t *memory, uint8_t *mpi,
55a96158 493 uint32_t *mpi_caps, uint8_t *phy)
1da177e4
LT		 494{
495 int rval;
496 mbx_cmd_t mc;
497 mbx_cmd_t *mcp = &mc;
498
7c3df132 499 ql_dbg(ql_dbg_mbx, vha, 0x1029, "Entered %s.\n", __func__);
1da177e4
LT		 500
501 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
502 mcp->out_mb = MBX_0;
503 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3a03eb79 504 if (IS_QLA81XX(vha->hw))
55a96158 505 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
1da177e4 506 mcp->flags = 0;
b93480e3 507 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 508 rval = qla2x00_mailbox_command(vha, mcp);
ca9e9c3e
AV		 509 if (rval != QLA_SUCCESS)
510 goto failed;
1da177e4
LT		 511
512 /* Return mailbox data. */
513 *major = mcp->mb[1];
514 *minor = mcp->mb[2];
515 *subminor = mcp->mb[3];
516 *attributes = mcp->mb[6];
7b867cf7 517 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
1da177e4
LT		 518 *memory = 0x1FFFF; /* Defaults to 128KB. */
519 else
520 *memory = (mcp->mb[5] << 16) | mcp->mb[4];
3a03eb79 521 if (IS_QLA81XX(vha->hw)) {
55a96158
AV		 522 mpi[0] = mcp->mb[10] & 0xff;
523 mpi[1] = mcp->mb[11] >> 8;
524 mpi[2] = mcp->mb[11] & 0xff;
3a03eb79 525 *mpi_caps = (mcp->mb[12] << 16) | mcp->mb[13];
55a96158
AV		 526 phy[0] = mcp->mb[8] & 0xff;
527 phy[1] = mcp->mb[9] >> 8;
528 phy[2] = mcp->mb[9] & 0xff;
3a03eb79 529 }
ca9e9c3e 530failed:
1da177e4
LT		 531 if (rval != QLA_SUCCESS) {
532 /*EMPTY*/
7c3df132 533 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1da177e4
LT		 534 } else {
535 /*EMPTY*/
7c3df132 536 ql_dbg(ql_dbg_mbx, vha, 0x102b, "Done %s.\n", __func__);
1da177e4 537 }
ca9e9c3e 538 return rval;
1da177e4
LT		 539}
540
541/*
542 * qla2x00_get_fw_options
543 * Set firmware options.
544 *
545 * Input:
546 * ha = adapter block pointer.
547 * fwopt = pointer for firmware options.
548 *
549 * Returns:
550 * qla2x00 local function return status code.
551 *
552 * Context:
553 * Kernel context.
554 */
555int
7b867cf7 556qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 557{
558 int rval;
559 mbx_cmd_t mc;
560 mbx_cmd_t *mcp = &mc;
561
7c3df132 562 ql_dbg(ql_dbg_mbx, vha, 0x102c, "Entered %s.\n", __func__);
1da177e4
LT		 563
564 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
565 mcp->out_mb = MBX_0;
566 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 567 mcp->tov = MBX_TOV_SECONDS;
1da177e4 568 mcp->flags = 0;
7b867cf7 569 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 570
571 if (rval != QLA_SUCCESS) {
572 /*EMPTY*/
7c3df132 573 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1da177e4 574 } else {
1c7c6357 575 fwopts[0] = mcp->mb[0];
1da177e4
LT		 576 fwopts[1] = mcp->mb[1];
577 fwopts[2] = mcp->mb[2];
578 fwopts[3] = mcp->mb[3];
579
7c3df132 580 ql_dbg(ql_dbg_mbx, vha, 0x102e, "Done %s.\n", __func__);
1da177e4
LT		 581 }
582
583 return rval;
584}
585
586
587/*
588 * qla2x00_set_fw_options
589 * Set firmware options.
590 *
591 * Input:
592 * ha = adapter block pointer.
593 * fwopt = pointer for firmware options.
594 *
595 * Returns:
596 * qla2x00 local function return status code.
597 *
598 * Context:
599 * Kernel context.
600 */
601int
7b867cf7 602qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 603{
604 int rval;
605 mbx_cmd_t mc;
606 mbx_cmd_t *mcp = &mc;
607
7c3df132 608 ql_dbg(ql_dbg_mbx, vha, 0x102f, "Entered %s.\n", __func__);
1da177e4
LT		 609
610 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
611 mcp->mb[1] = fwopts[1];
612 mcp->mb[2] = fwopts[2];
613 mcp->mb[3] = fwopts[3];
1c7c6357 614 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 615 mcp->in_mb = MBX_0;
7b867cf7 616 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 617 mcp->in_mb |= MBX_1;
618 } else {
619 mcp->mb[10] = fwopts[10];
620 mcp->mb[11] = fwopts[11];
621 mcp->mb[12] = 0; /* Undocumented, but used */
622 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
623 }
b93480e3 624 mcp->tov = MBX_TOV_SECONDS;
1da177e4 625 mcp->flags = 0;
7b867cf7 626 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 627
1c7c6357
AV		 628 fwopts[0] = mcp->mb[0];
629
1da177e4
LT		 630 if (rval != QLA_SUCCESS) {
631 /*EMPTY*/
7c3df132
SK		 632 ql_dbg(ql_dbg_mbx, vha, 0x1030,
633 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 634 } else {
635 /*EMPTY*/
7c3df132 636 ql_dbg(ql_dbg_mbx, vha, 0x1031, "Done %s.\n", __func__);
1da177e4
LT		 637 }
638
639 return rval;
640}
641
642/*
643 * qla2x00_mbx_reg_test
644 * Mailbox register wrap test.
645 *
646 * Input:
647 * ha = adapter block pointer.
648 * TARGET_QUEUE_LOCK must be released.
649 * ADAPTER_STATE_LOCK must be released.
650 *
651 * Returns:
652 * qla2x00 local function return status code.
653 *
654 * Context:
655 * Kernel context.
656 */
657int
7b867cf7 658qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1da177e4
LT		 659{
660 int rval;
661 mbx_cmd_t mc;
662 mbx_cmd_t *mcp = &mc;
663
7c3df132 664 ql_dbg(ql_dbg_mbx, vha, 0x1032, "Entered %s.\n", __func__);
1da177e4
LT		 665
666 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
667 mcp->mb[1] = 0xAAAA;
668 mcp->mb[2] = 0x5555;
669 mcp->mb[3] = 0xAA55;
670 mcp->mb[4] = 0x55AA;
671 mcp->mb[5] = 0xA5A5;
672 mcp->mb[6] = 0x5A5A;
673 mcp->mb[7] = 0x2525;
674 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
675 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 676 mcp->tov = MBX_TOV_SECONDS;
1da177e4 677 mcp->flags = 0;
7b867cf7 678 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 679
680 if (rval == QLA_SUCCESS) {
681 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
682 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
683 rval = QLA_FUNCTION_FAILED;
684 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
685 mcp->mb[7] != 0x2525)
686 rval = QLA_FUNCTION_FAILED;
687 }
688
689 if (rval != QLA_SUCCESS) {
690 /*EMPTY*/
7c3df132 691 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1da177e4
LT		 692 } else {
693 /*EMPTY*/
7c3df132 694 ql_dbg(ql_dbg_mbx, vha, 0x1034, "Done %s.\n", __func__);
1da177e4
LT		 695 }
696
697 return rval;
698}
699
700/*
701 * qla2x00_verify_checksum
702 * Verify firmware checksum.
703 *
704 * Input:
705 * ha = adapter block pointer.
706 * TARGET_QUEUE_LOCK must be released.
707 * ADAPTER_STATE_LOCK must be released.
708 *
709 * Returns:
710 * qla2x00 local function return status code.
711 *
712 * Context:
713 * Kernel context.
714 */
715int
7b867cf7 716qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 717{
718 int rval;
719 mbx_cmd_t mc;
720 mbx_cmd_t *mcp = &mc;
721
7c3df132 722 ql_dbg(ql_dbg_mbx, vha, 0x1035, "Entered %s.\n", __func__);
1da177e4
LT		 723
724 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1c7c6357
AV		 725 mcp->out_mb = MBX_0;
726 mcp->in_mb = MBX_0;
7b867cf7 727 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 728 mcp->mb[1] = MSW(risc_addr);
729 mcp->mb[2] = LSW(risc_addr);
730 mcp->out_mb |= MBX_2|MBX_1;
731 mcp->in_mb |= MBX_2|MBX_1;
732 } else {
733 mcp->mb[1] = LSW(risc_addr);
734 mcp->out_mb |= MBX_1;
735 mcp->in_mb |= MBX_1;
736 }
737
b93480e3 738 mcp->tov = MBX_TOV_SECONDS;
1da177e4 739 mcp->flags = 0;
7b867cf7 740 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 741
742 if (rval != QLA_SUCCESS) {
7c3df132
SK		 743 ql_dbg(ql_dbg_mbx, vha, 0x1036,
744 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
745 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1da177e4 746 } else {
7c3df132 747 ql_dbg(ql_dbg_mbx, vha, 0x1037, "Done %s.\n", __func__);
1da177e4
LT		 748 }
749
750 return rval;
751}
752
753/*
754 * qla2x00_issue_iocb
755 * Issue IOCB using mailbox command
756 *
757 * Input:
758 * ha = adapter state pointer.
759 * buffer = buffer pointer.
760 * phys_addr = physical address of buffer.
761 * size = size of buffer.
762 * TARGET_QUEUE_LOCK must be released.
763 * ADAPTER_STATE_LOCK must be released.
764 *
765 * Returns:
766 * qla2x00 local function return status code.
767 *
768 * Context:
769 * Kernel context.
770 */
6e98016c 771int
7b867cf7 772qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
4d4df193 773 dma_addr_t phys_addr, size_t size, uint32_t tov)
1da177e4
LT		 774{
775 int rval;
776 mbx_cmd_t mc;
777 mbx_cmd_t *mcp = &mc;
778
7c3df132
SK		 779 ql_dbg(ql_dbg_mbx, vha, 0x1038, "Entered %s.\n", __func__);
780
1da177e4
LT		 781 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
782 mcp->mb[1] = 0;
783 mcp->mb[2] = MSW(phys_addr);
784 mcp->mb[3] = LSW(phys_addr);
785 mcp->mb[6] = MSW(MSD(phys_addr));
786 mcp->mb[7] = LSW(MSD(phys_addr));
787 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
788 mcp->in_mb = MBX_2|MBX_0;
4d4df193 789 mcp->tov = tov;
1da177e4 790 mcp->flags = 0;
7b867cf7 791 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 792
793 if (rval != QLA_SUCCESS) {
794 /*EMPTY*/
7c3df132 795 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1da177e4 796 } else {
8c958a99
AV		 797 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
798
799 /* Mask reserved bits. */
800 sts_entry->entry_status &=
7b867cf7 801 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
7c3df132 802 ql_dbg(ql_dbg_mbx, vha, 0x103a, "Done %s.\n", __func__);
1da177e4
LT		 803 }
804
805 return rval;
806}
807
4d4df193 808int
7b867cf7 809qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
4d4df193
HK		 810 size_t size)
811{
7b867cf7 812 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
4d4df193
HK		 813 MBX_TOV_SECONDS);
814}
815
1da177e4
LT		 816/*
817 * qla2x00_abort_command
818 * Abort command aborts a specified IOCB.
819 *
820 * Input:
821 * ha = adapter block pointer.
822 * sp = SB structure pointer.
823 *
824 * Returns:
825 * qla2x00 local function return status code.
826 *
827 * Context:
828 * Kernel context.
829 */
830int
2afa19a9 831qla2x00_abort_command(srb_t *sp)
1da177e4
LT		 832{
833 unsigned long flags = 0;
1da177e4 834 int rval;
73208dfd 835 uint32_t handle = 0;
1da177e4
LT		 836 mbx_cmd_t mc;
837 mbx_cmd_t *mcp = &mc;
2afa19a9
AC		 838 fc_port_t *fcport = sp->fcport;
839 scsi_qla_host_t *vha = fcport->vha;
7b867cf7 840 struct qla_hw_data *ha = vha->hw;
2afa19a9 841 struct req_que *req = vha->req;
1da177e4 842
7c3df132 843 ql_dbg(ql_dbg_mbx, vha, 0x103b, "Entered %s.\n", __func__);
1da177e4 844
c9c5ced9 845 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 846 for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
7b867cf7 847 if (req->outstanding_cmds[handle] == sp)
1da177e4
LT		 848 break;
849 }
c9c5ced9 850 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 851
852 if (handle == MAX_OUTSTANDING_COMMANDS) {
853 /* command not found */
854 return QLA_FUNCTION_FAILED;
855 }
856
857 mcp->mb[0] = MBC_ABORT_COMMAND;
858 if (HAS_EXTENDED_IDS(ha))
859 mcp->mb[1] = fcport->loop_id;
860 else
861 mcp->mb[1] = fcport->loop_id << 8;
862 mcp->mb[2] = (uint16_t)handle;
863 mcp->mb[3] = (uint16_t)(handle >> 16);
bdf79621 864 mcp->mb[6] = (uint16_t)sp->cmd->device->lun;
1da177e4
LT		 865 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
866 mcp->in_mb = MBX_0;
b93480e3 867 mcp->tov = MBX_TOV_SECONDS;
1da177e4 868 mcp->flags = 0;
7b867cf7 869 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 870
871 if (rval != QLA_SUCCESS) {
7c3df132 872 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1da177e4 873 } else {
7c3df132 874 ql_dbg(ql_dbg_mbx, vha, 0x103d, "Done %s.\n", __func__);
1da177e4
LT		 875 }
876
877 return rval;
878}
879
1da177e4 880int
2afa19a9 881qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
1da177e4 882{
523ec773 883 int rval, rval2;
1da177e4
LT		 884 mbx_cmd_t mc;
885 mbx_cmd_t *mcp = &mc;
7b867cf7 886 scsi_qla_host_t *vha;
73208dfd
AC		 887 struct req_que *req;
888 struct rsp_que *rsp;
1da177e4 889
523ec773 890 l = l;
7b867cf7 891 vha = fcport->vha;
7c3df132
SK		 892
893 ql_dbg(ql_dbg_mbx, vha, 0x103e, "Entered %s.\n", __func__);
894
7e2b895b
GM		 895 req = vha->hw->req_q_map[0];
896 rsp = req->rsp;
1da177e4 897 mcp->mb[0] = MBC_ABORT_TARGET;
523ec773 898 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
7b867cf7 899 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 900 mcp->mb[1] = fcport->loop_id;
901 mcp->mb[10] = 0;
902 mcp->out_mb |= MBX_10;
903 } else {
904 mcp->mb[1] = fcport->loop_id << 8;
905 }
7b867cf7
AC		 906 mcp->mb[2] = vha->hw->loop_reset_delay;
907 mcp->mb[9] = vha->vp_idx;
1da177e4
LT		 908
909 mcp->in_mb = MBX_0;
b93480e3 910 mcp->tov = MBX_TOV_SECONDS;
1da177e4 911 mcp->flags = 0;
7b867cf7 912 rval = qla2x00_mailbox_command(vha, mcp);
523ec773 913 if (rval != QLA_SUCCESS) {
7c3df132 914 ql_dbg(ql_dbg_mbx, vha, 0x103f, "Failed=%x.\n", rval);
523ec773
AV		 915 }
916
917 /* Issue marker IOCB. */
73208dfd
AC		 918 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
919 MK_SYNC_ID);
523ec773 920 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 921 ql_dbg(ql_dbg_mbx, vha, 0x1040,
922 "Failed to issue marker IOCB (%x).\n", rval2);
523ec773 923 } else {
7c3df132 924 ql_dbg(ql_dbg_mbx, vha, 0x1041, "Done %s.\n", __func__);
523ec773
AV		 925 }
926
927 return rval;
928}
929
930int
2afa19a9 931qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
523ec773
AV		 932{
933 int rval, rval2;
934 mbx_cmd_t mc;
935 mbx_cmd_t *mcp = &mc;
7b867cf7 936 scsi_qla_host_t *vha;
73208dfd
AC		 937 struct req_que *req;
938 struct rsp_que *rsp;
523ec773 939
7b867cf7 940 vha = fcport->vha;
7c3df132
SK		 941
942 ql_dbg(ql_dbg_mbx, vha, 0x1042, "Entered %s.\n", __func__);
943
7e2b895b
GM		 944 req = vha->hw->req_q_map[0];
945 rsp = req->rsp;
523ec773
AV		 946 mcp->mb[0] = MBC_LUN_RESET;
947 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 948 if (HAS_EXTENDED_IDS(vha->hw))
523ec773
AV		 949 mcp->mb[1] = fcport->loop_id;
950 else
951 mcp->mb[1] = fcport->loop_id << 8;
952 mcp->mb[2] = l;
953 mcp->mb[3] = 0;
7b867cf7 954 mcp->mb[9] = vha->vp_idx;
1da177e4 955
523ec773 956 mcp->in_mb = MBX_0;
b93480e3 957 mcp->tov = MBX_TOV_SECONDS;
523ec773 958 mcp->flags = 0;
7b867cf7 959 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 960 if (rval != QLA_SUCCESS) {
7c3df132 961 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
523ec773
AV		 962 }
963
964 /* Issue marker IOCB. */
73208dfd
AC		 965 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
966 MK_SYNC_ID_LUN);
523ec773 967 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 968 ql_dbg(ql_dbg_mbx, vha, 0x1044,
969 "Failed to issue marker IOCB (%x).\n", rval2);
1da177e4 970 } else {
7c3df132 971 ql_dbg(ql_dbg_mbx, vha, 0x1045, "Done %s.\n", __func__);
1da177e4
LT		 972 }
973
974 return rval;
975}
1da177e4 976
1da177e4
LT		 977/*
978 * qla2x00_get_adapter_id
979 * Get adapter ID and topology.
980 *
981 * Input:
982 * ha = adapter block pointer.
983 * id = pointer for loop ID.
984 * al_pa = pointer for AL_PA.
985 * area = pointer for area.
986 * domain = pointer for domain.
987 * top = pointer for topology.
988 * TARGET_QUEUE_LOCK must be released.
989 * ADAPTER_STATE_LOCK must be released.
990 *
991 * Returns:
992 * qla2x00 local function return status code.
993 *
994 * Context:
995 * Kernel context.
996 */
997int
7b867cf7 998qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
2c3dfe3f 999 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1da177e4
LT		 1000{
1001 int rval;
1002 mbx_cmd_t mc;
1003 mbx_cmd_t *mcp = &mc;
1004
7c3df132 1005 ql_dbg(ql_dbg_mbx, vha, 0x1046, "Entered %s.\n", __func__);
1da177e4
LT		 1006
1007 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
7b867cf7 1008 mcp->mb[9] = vha->vp_idx;
eb66dc60 1009 mcp->out_mb = MBX_9|MBX_0;
2c3dfe3f 1010 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
a9083016 1011 if (IS_QLA8XXX_TYPE(vha->hw))
bad7001c 1012 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
b93480e3 1013 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1014 mcp->flags = 0;
7b867cf7 1015 rval = qla2x00_mailbox_command(vha, mcp);
33135aa2
RA		 1016 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1017 rval = QLA_COMMAND_ERROR;
42e421b1
AV		 1018 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1019 rval = QLA_INVALID_COMMAND;
1da177e4
LT		 1020
1021 /* Return data. */
1022 *id = mcp->mb[1];
1023 *al_pa = LSB(mcp->mb[2]);
1024 *area = MSB(mcp->mb[2]);
1025 *domain = LSB(mcp->mb[3]);
1026 *top = mcp->mb[6];
2c3dfe3f 1027 *sw_cap = mcp->mb[7];
1da177e4
LT		 1028
1029 if (rval != QLA_SUCCESS) {
1030 /*EMPTY*/
7c3df132 1031 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1da177e4 1032 } else {
7c3df132 1033 ql_dbg(ql_dbg_mbx, vha, 0x1048, "Done %s.\n", __func__);
bad7001c 1034
a9083016 1035 if (IS_QLA8XXX_TYPE(vha->hw)) {
bad7001c
AV		 1036 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1037 vha->fcoe_fcf_idx = mcp->mb[10];
1038 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1039 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1040 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1041 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1042 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1043 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1044 }
1da177e4
LT		 1045 }
1046
1047 return rval;
1048}
1049
1050/*
1051 * qla2x00_get_retry_cnt
1052 * Get current firmware login retry count and delay.
1053 *
1054 * Input:
1055 * ha = adapter block pointer.
1056 * retry_cnt = pointer to login retry count.
1057 * tov = pointer to login timeout value.
1058 *
1059 * Returns:
1060 * qla2x00 local function return status code.
1061 *
1062 * Context:
1063 * Kernel context.
1064 */
1065int
7b867cf7 1066qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1da177e4
LT		 1067 uint16_t *r_a_tov)
1068{
1069 int rval;
1070 uint16_t ratov;
1071 mbx_cmd_t mc;
1072 mbx_cmd_t *mcp = &mc;
1073
7c3df132 1074 ql_dbg(ql_dbg_mbx, vha, 0x1049, "Entered %s.\n", __func__);
1da177e4
LT		 1075
1076 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1077 mcp->out_mb = MBX_0;
1078 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1079 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1080 mcp->flags = 0;
7b867cf7 1081 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1082
1083 if (rval != QLA_SUCCESS) {
1084 /*EMPTY*/
7c3df132
SK		 1085 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1086 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1087 } else {
1088 /* Convert returned data and check our values. */
1089 *r_a_tov = mcp->mb[3] / 2;
1090 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1091 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1092 /* Update to the larger values */
1093 *retry_cnt = (uint8_t)mcp->mb[1];
1094 *tov = ratov;
1095 }
1096
7c3df132
SK		 1097 ql_dbg(ql_dbg_mbx, vha, 0x104b,
1098 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1da177e4
LT		 1099 }
1100
1101 return rval;
1102}
1103
1104/*
1105 * qla2x00_init_firmware
1106 * Initialize adapter firmware.
1107 *
1108 * Input:
1109 * ha = adapter block pointer.
1110 * dptr = Initialization control block pointer.
1111 * size = size of initialization control block.
1112 * TARGET_QUEUE_LOCK must be released.
1113 * ADAPTER_STATE_LOCK must be released.
1114 *
1115 * Returns:
1116 * qla2x00 local function return status code.
1117 *
1118 * Context:
1119 * Kernel context.
1120 */
1121int
7b867cf7 1122qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1da177e4
LT		 1123{
1124 int rval;
1125 mbx_cmd_t mc;
1126 mbx_cmd_t *mcp = &mc;
7b867cf7 1127 struct qla_hw_data *ha = vha->hw;
1da177e4 1128
7c3df132 1129 ql_dbg(ql_dbg_mbx, vha, 0x104c, "Entered %s.\n", __func__);
1da177e4 1130
a9083016
GM		 1131 if (IS_QLA82XX(ha) && ql2xdbwr)
1132 qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
1133 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1134
e6e074f1 1135 if (ha->flags.npiv_supported)
2c3dfe3f
SJ		 1136 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1137 else
1138 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1139
b64b0e8f 1140 mcp->mb[1] = 0;
1da177e4
LT		 1141 mcp->mb[2] = MSW(ha->init_cb_dma);
1142 mcp->mb[3] = LSW(ha->init_cb_dma);
1da177e4
LT		 1143 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1144 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
b64b0e8f
AV		 1145 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1146 if (IS_QLA81XX(ha) && ha->ex_init_cb->ex_version) {
1147 mcp->mb[1] = BIT_0;
1148 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1149 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1150 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1151 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1152 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1153 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1154 }
1155 mcp->in_mb = MBX_0;
1da177e4
LT		 1156 mcp->buf_size = size;
1157 mcp->flags = MBX_DMA_OUT;
b93480e3 1158 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1159 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1160
1161 if (rval != QLA_SUCCESS) {
1162 /*EMPTY*/
7c3df132
SK		 1163 ql_dbg(ql_dbg_mbx, vha, 0x104d,
1164 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1165 } else {
1166 /*EMPTY*/
7c3df132 1167 ql_dbg(ql_dbg_mbx, vha, 0x104e, "Done %s.\n", __func__);
1da177e4
LT		 1168 }
1169
1170 return rval;
1171}
1172
1173/*
1174 * qla2x00_get_port_database
1175 * Issue normal/enhanced get port database mailbox command
1176 * and copy device name as necessary.
1177 *
1178 * Input:
1179 * ha = adapter state pointer.
1180 * dev = structure pointer.
1181 * opt = enhanced cmd option byte.
1182 *
1183 * Returns:
1184 * qla2x00 local function return status code.
1185 *
1186 * Context:
1187 * Kernel context.
1188 */
1189int
7b867cf7 1190qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1da177e4
LT		 1191{
1192 int rval;
1193 mbx_cmd_t mc;
1194 mbx_cmd_t *mcp = &mc;
1195 port_database_t *pd;
1c7c6357 1196 struct port_database_24xx *pd24;
1da177e4 1197 dma_addr_t pd_dma;
7b867cf7 1198 struct qla_hw_data *ha = vha->hw;
1da177e4 1199
7c3df132 1200 ql_dbg(ql_dbg_mbx, vha, 0x104f, "Entered %s.\n", __func__);
1da177e4 1201
1c7c6357
AV		 1202 pd24 = NULL;
1203 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1da177e4 1204 if (pd == NULL) {
7c3df132
SK		 1205 ql_log(ql_log_warn, vha, 0x1050,
1206 "Failed to allocate port database structure.\n");
1da177e4
LT		 1207 return QLA_MEMORY_ALLOC_FAILED;
1208 }
1c7c6357 1209 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1da177e4 1210
1c7c6357 1211 mcp->mb[0] = MBC_GET_PORT_DATABASE;
e428924c 1212 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1da177e4 1213 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1da177e4
LT		 1214 mcp->mb[2] = MSW(pd_dma);
1215 mcp->mb[3] = LSW(pd_dma);
1216 mcp->mb[6] = MSW(MSD(pd_dma));
1217 mcp->mb[7] = LSW(MSD(pd_dma));
7b867cf7 1218 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1219 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1da177e4 1220 mcp->in_mb = MBX_0;
e428924c 1221 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1222 mcp->mb[1] = fcport->loop_id;
1223 mcp->mb[10] = opt;
1224 mcp->out_mb |= MBX_10|MBX_1;
1225 mcp->in_mb |= MBX_1;
1226 } else if (HAS_EXTENDED_IDS(ha)) {
1227 mcp->mb[1] = fcport->loop_id;
1228 mcp->mb[10] = opt;
1229 mcp->out_mb |= MBX_10|MBX_1;
1230 } else {
1231 mcp->mb[1] = fcport->loop_id << 8 | opt;
1232 mcp->out_mb |= MBX_1;
1233 }
e428924c
AV		 1234 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1235 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1da177e4
LT		 1236 mcp->flags = MBX_DMA_IN;
1237 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 1238 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1239 if (rval != QLA_SUCCESS)
1240 goto gpd_error_out;
1241
e428924c 1242 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1243 pd24 = (struct port_database_24xx *) pd;
1244
1245 /* Check for logged in state. */
1246 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1247 pd24->last_login_state != PDS_PRLI_COMPLETE) {
7c3df132
SK		 1248 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1249 "Unable to verify login-state (%x/%x) for "
1250 "loop_id %x.\n", pd24->current_login_state,
1251 pd24->last_login_state, fcport->loop_id);
1c7c6357
AV		 1252 rval = QLA_FUNCTION_FAILED;
1253 goto gpd_error_out;
1254 }
1da177e4 1255
1c7c6357
AV		 1256 /* Names are little-endian. */
1257 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1258 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1259
1260 /* Get port_id of device. */
1261 fcport->d_id.b.domain = pd24->port_id[0];
1262 fcport->d_id.b.area = pd24->port_id[1];
1263 fcport->d_id.b.al_pa = pd24->port_id[2];
1264 fcport->d_id.b.rsvd_1 = 0;
1265
1266 /* If not target must be initiator or unknown type. */
1267 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1268 fcport->port_type = FCT_INITIATOR;
1269 else
1270 fcport->port_type = FCT_TARGET;
1271 } else {
1272 /* Check for logged in state. */
1273 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1274 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
7c3df132
SK		 1275 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1276 "Unable to verify login-state (%x/%x) - "
1277 "portid=%02x%02x%02x.\n", pd->master_state,
1278 pd->slave_state, fcport->d_id.b.domain,
1279 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1c7c6357
AV		 1280 rval = QLA_FUNCTION_FAILED;
1281 goto gpd_error_out;
1282 }
1da177e4 1283
1c7c6357
AV		 1284 /* Names are little-endian. */
1285 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1286 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1287
1288 /* Get port_id of device. */
1289 fcport->d_id.b.domain = pd->port_id[0];
1290 fcport->d_id.b.area = pd->port_id[3];
1291 fcport->d_id.b.al_pa = pd->port_id[2];
1292 fcport->d_id.b.rsvd_1 = 0;
1293
1c7c6357
AV		 1294 /* If not target must be initiator or unknown type. */
1295 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1296 fcport->port_type = FCT_INITIATOR;
1297 else
1298 fcport->port_type = FCT_TARGET;
ad3e0eda
AV		 1299
1300 /* Passback COS information. */
1301 fcport->supported_classes = (pd->options & BIT_4) ?
1302 FC_COS_CLASS2: FC_COS_CLASS3;
1c7c6357 1303 }
1da177e4
LT		 1304
1305gpd_error_out:
1306 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1307
1308 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1309 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1310 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1311 mcp->mb[0], mcp->mb[1]);
1da177e4 1312 } else {
7c3df132 1313 ql_dbg(ql_dbg_mbx, vha, 0x1053, "Done %s.\n", __func__);
1da177e4
LT		 1314 }
1315
1316 return rval;
1317}
1318
1319/*
1320 * qla2x00_get_firmware_state
1321 * Get adapter firmware state.
1322 *
1323 * Input:
1324 * ha = adapter block pointer.
1325 * dptr = pointer for firmware state.
1326 * TARGET_QUEUE_LOCK must be released.
1327 * ADAPTER_STATE_LOCK must be released.
1328 *
1329 * Returns:
1330 * qla2x00 local function return status code.
1331 *
1332 * Context:
1333 * Kernel context.
1334 */
1335int
7b867cf7 1336qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1da177e4
LT		 1337{
1338 int rval;
1339 mbx_cmd_t mc;
1340 mbx_cmd_t *mcp = &mc;
1341
7c3df132 1342 ql_dbg(ql_dbg_mbx, vha, 0x1054, "Entered %s.\n", __func__);
1da177e4
LT		 1343
1344 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1345 mcp->out_mb = MBX_0;
9d2683c0
AV		 1346 if (IS_FWI2_CAPABLE(vha->hw))
1347 mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1348 else
1349 mcp->in_mb = MBX_1|MBX_0;
b93480e3 1350 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1351 mcp->flags = 0;
7b867cf7 1352 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1353
4d4df193
HK		 1354 /* Return firmware states. */
1355 states[0] = mcp->mb[1];
9d2683c0
AV		 1356 if (IS_FWI2_CAPABLE(vha->hw)) {
1357 states[1] = mcp->mb[2];
1358 states[2] = mcp->mb[3];
1359 states[3] = mcp->mb[4];
1360 states[4] = mcp->mb[5];
1361 }
1da177e4
LT		 1362
1363 if (rval != QLA_SUCCESS) {
1364 /*EMPTY*/
7c3df132 1365 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1da177e4
LT		 1366 } else {
1367 /*EMPTY*/
7c3df132 1368 ql_dbg(ql_dbg_mbx, vha, 0x1056, "Done %s.\n", __func__);
1da177e4
LT		 1369 }
1370
1371 return rval;
1372}
1373
1374/*
1375 * qla2x00_get_port_name
1376 * Issue get port name mailbox command.
1377 * Returned name is in big endian format.
1378 *
1379 * Input:
1380 * ha = adapter block pointer.
1381 * loop_id = loop ID of device.
1382 * name = pointer for name.
1383 * TARGET_QUEUE_LOCK must be released.
1384 * ADAPTER_STATE_LOCK must be released.
1385 *
1386 * Returns:
1387 * qla2x00 local function return status code.
1388 *
1389 * Context:
1390 * Kernel context.
1391 */
1392int
7b867cf7 1393qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1da177e4
LT		 1394 uint8_t opt)
1395{
1396 int rval;
1397 mbx_cmd_t mc;
1398 mbx_cmd_t *mcp = &mc;
1399
7c3df132 1400 ql_dbg(ql_dbg_mbx, vha, 0x1057, "Entered %s.\n", __func__);
1da177e4
LT		 1401
1402 mcp->mb[0] = MBC_GET_PORT_NAME;
7b867cf7 1403 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1404 mcp->out_mb = MBX_9|MBX_1|MBX_0;
7b867cf7 1405 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1406 mcp->mb[1] = loop_id;
1407 mcp->mb[10] = opt;
1408 mcp->out_mb |= MBX_10;
1409 } else {
1410 mcp->mb[1] = loop_id << 8 | opt;
1411 }
1412
1413 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1414 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1415 mcp->flags = 0;
7b867cf7 1416 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1417
1418 if (rval != QLA_SUCCESS) {
1419 /*EMPTY*/
7c3df132 1420 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1da177e4
LT		 1421 } else {
1422 if (name != NULL) {
1423 /* This function returns name in big endian. */
1196ae02
RL		 1424 name[0] = MSB(mcp->mb[2]);
1425 name[1] = LSB(mcp->mb[2]);
1426 name[2] = MSB(mcp->mb[3]);
1427 name[3] = LSB(mcp->mb[3]);
1428 name[4] = MSB(mcp->mb[6]);
1429 name[5] = LSB(mcp->mb[6]);
1430 name[6] = MSB(mcp->mb[7]);
1431 name[7] = LSB(mcp->mb[7]);
1da177e4
LT		 1432 }
1433
7c3df132 1434 ql_dbg(ql_dbg_mbx, vha, 0x1059, "Done %s.\n", __func__);
1da177e4
LT		 1435 }
1436
1437 return rval;
1438}
1439
1440/*
1441 * qla2x00_lip_reset
1442 * Issue LIP reset mailbox command.
1443 *
1444 * Input:
1445 * ha = adapter block pointer.
1446 * TARGET_QUEUE_LOCK must be released.
1447 * ADAPTER_STATE_LOCK must be released.
1448 *
1449 * Returns:
1450 * qla2x00 local function return status code.
1451 *
1452 * Context:
1453 * Kernel context.
1454 */
1455int
7b867cf7 1456qla2x00_lip_reset(scsi_qla_host_t *vha)
1da177e4
LT		 1457{
1458 int rval;
1459 mbx_cmd_t mc;
1460 mbx_cmd_t *mcp = &mc;
1461
7c3df132 1462 ql_dbg(ql_dbg_mbx, vha, 0x105a, "Entered %s.\n", __func__);
1da177e4 1463
a9083016 1464 if (IS_QLA8XXX_TYPE(vha->hw)) {
3a03eb79
AV		 1465 /* Logout across all FCFs. */
1466 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1467 mcp->mb[1] = BIT_1;
1468 mcp->mb[2] = 0;
1469 mcp->out_mb = MBX_2|MBX_1|MBX_0;
1470 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 1471 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
0c8c39af
AV		 1472 mcp->mb[1] = BIT_6;
1473 mcp->mb[2] = 0;
7b867cf7 1474 mcp->mb[3] = vha->hw->loop_reset_delay;
1c7c6357 1475 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 1476 } else {
1c7c6357
AV		 1477 mcp->mb[0] = MBC_LIP_RESET;
1478 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1479 if (HAS_EXTENDED_IDS(vha->hw)) {
1c7c6357
AV		 1480 mcp->mb[1] = 0x00ff;
1481 mcp->mb[10] = 0;
1482 mcp->out_mb |= MBX_10;
1483 } else {
1484 mcp->mb[1] = 0xff00;
1485 }
7b867cf7 1486 mcp->mb[2] = vha->hw->loop_reset_delay;
1c7c6357 1487 mcp->mb[3] = 0;
1da177e4 1488 }
1da177e4 1489 mcp->in_mb = MBX_0;
b93480e3 1490 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1491 mcp->flags = 0;
7b867cf7 1492 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1493
1494 if (rval != QLA_SUCCESS) {
1495 /*EMPTY*/
7c3df132 1496 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1da177e4
LT		 1497 } else {
1498 /*EMPTY*/
7c3df132 1499 ql_dbg(ql_dbg_mbx, vha, 0x105c, "Done %s.\n", __func__);
1da177e4
LT		 1500 }
1501
1502 return rval;
1503}
1504
1505/*
1506 * qla2x00_send_sns
1507 * Send SNS command.
1508 *
1509 * Input:
1510 * ha = adapter block pointer.
1511 * sns = pointer for command.
1512 * cmd_size = command size.
1513 * buf_size = response/command size.
1514 * TARGET_QUEUE_LOCK must be released.
1515 * ADAPTER_STATE_LOCK must be released.
1516 *
1517 * Returns:
1518 * qla2x00 local function return status code.
1519 *
1520 * Context:
1521 * Kernel context.
1522 */
1523int
7b867cf7 1524qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1da177e4
LT		 1525 uint16_t cmd_size, size_t buf_size)
1526{
1527 int rval;
1528 mbx_cmd_t mc;
1529 mbx_cmd_t *mcp = &mc;
1530
7c3df132 1531 ql_dbg(ql_dbg_mbx, vha, 0x105d, "Entered %s.\n", __func__);
1da177e4 1532
7c3df132
SK		 1533 ql_dbg(ql_dbg_mbx, vha, 0x105e,
1534 "Retry cnt=%d ratov=%d total tov=%d.\n",
1535 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1da177e4
LT		 1536
1537 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
1538 mcp->mb[1] = cmd_size;
1539 mcp->mb[2] = MSW(sns_phys_address);
1540 mcp->mb[3] = LSW(sns_phys_address);
1541 mcp->mb[6] = MSW(MSD(sns_phys_address));
1542 mcp->mb[7] = LSW(MSD(sns_phys_address));
1543 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1544 mcp->in_mb = MBX_0|MBX_1;
1545 mcp->buf_size = buf_size;
1546 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
7b867cf7
AC		 1547 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
1548 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1549
1550 if (rval != QLA_SUCCESS) {
1551 /*EMPTY*/
7c3df132
SK		 1552 ql_dbg(ql_dbg_mbx, vha, 0x105f,
1553 "Failed=%x mb[0]=%x mb[1]=%x.\n",
1554 rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 1555 } else {
1556 /*EMPTY*/
7c3df132 1557 ql_dbg(ql_dbg_mbx, vha, 0x1060, "Done %s.\n", __func__);
1da177e4
LT		 1558 }
1559
1560 return rval;
1561}
1562
1c7c6357 1563int
7b867cf7 1564qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 1565 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1566{
1567 int rval;
1568
1569 struct logio_entry_24xx *lg;
1570 dma_addr_t lg_dma;
1571 uint32_t iop[2];
7b867cf7 1572 struct qla_hw_data *ha = vha->hw;
2afa19a9
AC		 1573 struct req_que *req;
1574 struct rsp_que *rsp;
1c7c6357 1575
7c3df132 1576 ql_dbg(ql_dbg_mbx, vha, 0x1061, "Entered %s.\n", __func__);
1c7c6357 1577
7163ea81 1578 if (ha->flags.cpu_affinity_enabled)
68ca949c
AC		 1579 req = ha->req_q_map[0];
1580 else
1581 req = vha->req;
2afa19a9
AC		 1582 rsp = req->rsp;
1583
1c7c6357
AV		 1584 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1585 if (lg == NULL) {
7c3df132
SK		 1586 ql_log(ql_log_warn, vha, 0x1062,
1587 "Failed to allocate login IOCB.\n");
1c7c6357
AV		 1588 return QLA_MEMORY_ALLOC_FAILED;
1589 }
1590 memset(lg, 0, sizeof(struct logio_entry_24xx));
1591
1592 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
1593 lg->entry_count = 1;
2afa19a9 1594 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 1595 lg->nport_handle = cpu_to_le16(loop_id);
1596 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
1597 if (opt & BIT_0)
1598 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
8baa51a6
AV		 1599 if (opt & BIT_1)
1600 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
1c7c6357
AV		 1601 lg->port_id[0] = al_pa;
1602 lg->port_id[1] = area;
1603 lg->port_id[2] = domain;
7b867cf7
AC		 1604 lg->vp_index = vha->vp_idx;
1605 rval = qla2x00_issue_iocb(vha, lg, lg_dma, 0);
1c7c6357 1606 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1607 ql_dbg(ql_dbg_mbx, vha, 0x1063,
1608 "Failed to issue login IOCB (%x).\n", rval);
1c7c6357 1609 } else if (lg->entry_status != 0) {
7c3df132
SK		 1610 ql_dbg(ql_dbg_mbx, vha, 0x1064,
1611 "Failed to complete IOCB -- error status (%x).\n",
1612 lg->entry_status);
1c7c6357
AV		 1613 rval = QLA_FUNCTION_FAILED;
1614 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
1615 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1616 iop[1] = le32_to_cpu(lg->io_parameter[1]);
1617
7c3df132
SK		 1618 ql_dbg(ql_dbg_mbx, vha, 0x1065,
1619 "Failed to complete IOCB -- completion status (%x) "
1620 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1621 iop[0], iop[1]);
1c7c6357
AV		 1622
1623 switch (iop[0]) {
1624 case LSC_SCODE_PORTID_USED:
1625 mb[0] = MBS_PORT_ID_USED;
1626 mb[1] = LSW(iop[1]);
1627 break;
1628 case LSC_SCODE_NPORT_USED:
1629 mb[0] = MBS_LOOP_ID_USED;
1630 break;
1631 case LSC_SCODE_NOLINK:
1632 case LSC_SCODE_NOIOCB:
1633 case LSC_SCODE_NOXCB:
1634 case LSC_SCODE_CMD_FAILED:
1635 case LSC_SCODE_NOFABRIC:
1636 case LSC_SCODE_FW_NOT_READY:
1637 case LSC_SCODE_NOT_LOGGED_IN:
1638 case LSC_SCODE_NOPCB:
1639 case LSC_SCODE_ELS_REJECT:
1640 case LSC_SCODE_CMD_PARAM_ERR:
1641 case LSC_SCODE_NONPORT:
1642 case LSC_SCODE_LOGGED_IN:
1643 case LSC_SCODE_NOFLOGI_ACC:
1644 default:
1645 mb[0] = MBS_COMMAND_ERROR;
1646 break;
1647 }
1648 } else {
7c3df132 1649 ql_dbg(ql_dbg_mbx, vha, 0x1066, "Done %s.\n", __func__);
1c7c6357
AV		 1650
1651 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1652
1653 mb[0] = MBS_COMMAND_COMPLETE;
1654 mb[1] = 0;
1655 if (iop[0] & BIT_4) {
1656 if (iop[0] & BIT_8)
1657 mb[1] |= BIT_1;
1658 } else
1659 mb[1] = BIT_0;
ad3e0eda
AV		 1660
1661 /* Passback COS information. */
1662 mb[10] = 0;
1663 if (lg->io_parameter[7] || lg->io_parameter[8])
1664 mb[10] |= BIT_0; /* Class 2. */
1665 if (lg->io_parameter[9] || lg->io_parameter[10])
1666 mb[10] |= BIT_1; /* Class 3. */
1c7c6357
AV		 1667 }
1668
1669 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
1670
1671 return rval;
1672}
1673
1da177e4
LT		 1674/*
1675 * qla2x00_login_fabric
1676 * Issue login fabric port mailbox command.
1677 *
1678 * Input:
1679 * ha = adapter block pointer.
1680 * loop_id = device loop ID.
1681 * domain = device domain.
1682 * area = device area.
1683 * al_pa = device AL_PA.
1684 * status = pointer for return status.
1685 * opt = command options.
1686 * TARGET_QUEUE_LOCK must be released.
1687 * ADAPTER_STATE_LOCK must be released.
1688 *
1689 * Returns:
1690 * qla2x00 local function return status code.
1691 *
1692 * Context:
1693 * Kernel context.
1694 */
1695int
7b867cf7 1696qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1da177e4
LT		 1697 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1698{
1699 int rval;
1700 mbx_cmd_t mc;
1701 mbx_cmd_t *mcp = &mc;
7b867cf7 1702 struct qla_hw_data *ha = vha->hw;
1da177e4 1703
7c3df132 1704 ql_dbg(ql_dbg_mbx, vha, 0x1067, "Entered %s.\n", __func__);
1da177e4
LT		 1705
1706 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
1707 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1708 if (HAS_EXTENDED_IDS(ha)) {
1709 mcp->mb[1] = loop_id;
1710 mcp->mb[10] = opt;
1711 mcp->out_mb |= MBX_10;
1712 } else {
1713 mcp->mb[1] = (loop_id << 8) | opt;
1714 }
1715 mcp->mb[2] = domain;
1716 mcp->mb[3] = area << 8 | al_pa;
1717
1718 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
1719 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1720 mcp->flags = 0;
7b867cf7 1721 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1722
1723 /* Return mailbox statuses. */
1724 if (mb != NULL) {
1725 mb[0] = mcp->mb[0];
1726 mb[1] = mcp->mb[1];
1727 mb[2] = mcp->mb[2];
1728 mb[6] = mcp->mb[6];
1729 mb[7] = mcp->mb[7];
ad3e0eda
AV		 1730 /* COS retrieved from Get-Port-Database mailbox command. */
1731 mb[10] = 0;
1da177e4
LT		 1732 }
1733
1734 if (rval != QLA_SUCCESS) {
1735 /* RLU tmp code: need to change main mailbox_command function to
1736 * return ok even when the mailbox completion value is not
1737 * SUCCESS. The caller needs to be responsible to interpret
1738 * the return values of this mailbox command if we're not
1739 * to change too much of the existing code.
1740 */
1741 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
1742 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
1743 mcp->mb[0] == 0x4006)
1744 rval = QLA_SUCCESS;
1745
1746 /*EMPTY*/
7c3df132
SK		 1747 ql_dbg(ql_dbg_mbx, vha, 0x1068,
1748 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
1749 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1da177e4
LT		 1750 } else {
1751 /*EMPTY*/
7c3df132 1752 ql_dbg(ql_dbg_mbx, vha, 0x1069, "Done %s.\n", __func__);
1da177e4
LT		 1753 }
1754
1755 return rval;
1756}
1757
1758/*
1759 * qla2x00_login_local_device
1760 * Issue login loop port mailbox command.
fa2a1ce5 1761 *
1da177e4
LT		 1762 * Input:
1763 * ha = adapter block pointer.
1764 * loop_id = device loop ID.
1765 * opt = command options.
fa2a1ce5 1766 *
1da177e4
LT		 1767 * Returns:
1768 * Return status code.
fa2a1ce5 1769 *
1da177e4
LT		 1770 * Context:
1771 * Kernel context.
fa2a1ce5 1772 *
1da177e4
LT		 1773 */
1774int
7b867cf7 1775qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 1776 uint16_t *mb_ret, uint8_t opt)
1777{
1778 int rval;
1779 mbx_cmd_t mc;
1780 mbx_cmd_t *mcp = &mc;
7b867cf7 1781 struct qla_hw_data *ha = vha->hw;
1da177e4 1782
7c3df132
SK		 1783 ql_dbg(ql_dbg_mbx, vha, 0x106a, "Entered %s.\n", __func__);
1784
e428924c 1785 if (IS_FWI2_CAPABLE(ha))
7b867cf7 1786 return qla24xx_login_fabric(vha, fcport->loop_id,
9a52a57c 1787 fcport->d_id.b.domain, fcport->d_id.b.area,
1788 fcport->d_id.b.al_pa, mb_ret, opt);
1789
1da177e4
LT		 1790 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
1791 if (HAS_EXTENDED_IDS(ha))
9a52a57c 1792 mcp->mb[1] = fcport->loop_id;
1da177e4 1793 else
9a52a57c 1794 mcp->mb[1] = fcport->loop_id << 8;
1da177e4
LT		 1795 mcp->mb[2] = opt;
1796 mcp->out_mb = MBX_2|MBX_1|MBX_0;
1797 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
1798 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1799 mcp->flags = 0;
7b867cf7 1800 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1801
1802 /* Return mailbox statuses. */
1803 if (mb_ret != NULL) {
1804 mb_ret[0] = mcp->mb[0];
1805 mb_ret[1] = mcp->mb[1];
1806 mb_ret[6] = mcp->mb[6];
1807 mb_ret[7] = mcp->mb[7];
1808 }
1809
1810 if (rval != QLA_SUCCESS) {
1811 /* AV tmp code: need to change main mailbox_command function to
1812 * return ok even when the mailbox completion value is not
1813 * SUCCESS. The caller needs to be responsible to interpret
1814 * the return values of this mailbox command if we're not
1815 * to change too much of the existing code.
1816 */
1817 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
1818 rval = QLA_SUCCESS;
1819
7c3df132
SK		 1820 ql_dbg(ql_dbg_mbx, vha, 0x106b,
1821 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
1822 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1da177e4
LT		 1823 } else {
1824 /*EMPTY*/
7c3df132 1825 ql_dbg(ql_dbg_mbx, vha, 0x106c, "Done %s.\n", __func__);
1da177e4
LT		 1826 }
1827
1828 return (rval);
1829}
1830
1c7c6357 1831int
7b867cf7 1832qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 1833 uint8_t area, uint8_t al_pa)
1834{
1835 int rval;
1836 struct logio_entry_24xx *lg;
1837 dma_addr_t lg_dma;
7b867cf7 1838 struct qla_hw_data *ha = vha->hw;
2afa19a9
AC		 1839 struct req_que *req;
1840 struct rsp_que *rsp;
1c7c6357 1841
7c3df132 1842 ql_dbg(ql_dbg_mbx, vha, 0x106d, "Entered %s.\n", __func__);
1c7c6357
AV		 1843
1844 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1845 if (lg == NULL) {
7c3df132
SK		 1846 ql_log(ql_log_warn, vha, 0x106e,
1847 "Failed to allocate logout IOCB.\n");
1c7c6357
AV		 1848 return QLA_MEMORY_ALLOC_FAILED;
1849 }
1850 memset(lg, 0, sizeof(struct logio_entry_24xx));
1851
2afa19a9
AC		 1852 if (ql2xmaxqueues > 1)
1853 req = ha->req_q_map[0];
1854 else
1855 req = vha->req;
1856 rsp = req->rsp;
1c7c6357
AV		 1857 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
1858 lg->entry_count = 1;
2afa19a9 1859 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 1860 lg->nport_handle = cpu_to_le16(loop_id);
1861 lg->control_flags =
c8d6691b
AV		 1862 __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
1863 LCF_FREE_NPORT);
1c7c6357
AV		 1864 lg->port_id[0] = al_pa;
1865 lg->port_id[1] = area;
1866 lg->port_id[2] = domain;
7b867cf7 1867 lg->vp_index = vha->vp_idx;
73208dfd 1868
7b867cf7 1869 rval = qla2x00_issue_iocb(vha, lg, lg_dma, 0);
1c7c6357 1870 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1871 ql_dbg(ql_dbg_mbx, vha, 0x106f,
1872 "Failed to issue logout IOCB (%x).\n", rval);
1c7c6357 1873 } else if (lg->entry_status != 0) {
7c3df132
SK		 1874 ql_dbg(ql_dbg_mbx, vha, 0x1070,
1875 "Failed to complete IOCB -- error status (%x).\n",
1876 lg->entry_status);
1c7c6357
AV		 1877 rval = QLA_FUNCTION_FAILED;
1878 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 1879 ql_dbg(ql_dbg_mbx, vha, 0x1071,
1880 "Failed to complete IOCB -- completion status (%x) "
1881 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1c7c6357 1882 le32_to_cpu(lg->io_parameter[0]),
7c3df132 1883 le32_to_cpu(lg->io_parameter[1]));
1c7c6357
AV		 1884 } else {
1885 /*EMPTY*/
7c3df132 1886 ql_dbg(ql_dbg_mbx, vha, 0x1072, "Done %s.\n", __func__);
1c7c6357
AV		 1887 }
1888
1889 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
1890
1891 return rval;
1892}
1893
1da177e4
LT		 1894/*
1895 * qla2x00_fabric_logout
1896 * Issue logout fabric port mailbox command.
1897 *
1898 * Input:
1899 * ha = adapter block pointer.
1900 * loop_id = device loop ID.
1901 * TARGET_QUEUE_LOCK must be released.
1902 * ADAPTER_STATE_LOCK must be released.
1903 *
1904 * Returns:
1905 * qla2x00 local function return status code.
1906 *
1907 * Context:
1908 * Kernel context.
1909 */
1910int
7b867cf7 1911qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357 1912 uint8_t area, uint8_t al_pa)
1da177e4
LT		 1913{
1914 int rval;
1915 mbx_cmd_t mc;
1916 mbx_cmd_t *mcp = &mc;
1917
7c3df132 1918 ql_dbg(ql_dbg_mbx, vha, 0x1073, "Entered %s.\n", __func__);
1da177e4
LT		 1919
1920 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
1921 mcp->out_mb = MBX_1|MBX_0;
7b867cf7 1922 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1923 mcp->mb[1] = loop_id;
1924 mcp->mb[10] = 0;
1925 mcp->out_mb |= MBX_10;
1926 } else {
1927 mcp->mb[1] = loop_id << 8;
1928 }
1929
1930 mcp->in_mb = MBX_1|MBX_0;
b93480e3 1931 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1932 mcp->flags = 0;
7b867cf7 1933 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1934
1935 if (rval != QLA_SUCCESS) {
1936 /*EMPTY*/
7c3df132
SK		 1937 ql_dbg(ql_dbg_mbx, vha, 0x1074,
1938 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1da177e4
LT		 1939 } else {
1940 /*EMPTY*/
7c3df132 1941 ql_dbg(ql_dbg_mbx, vha, 0x1075, "Done %s.\n", __func__);
1da177e4
LT		 1942 }
1943
1944 return rval;
1945}
1946
1947/*
1948 * qla2x00_full_login_lip
1949 * Issue full login LIP mailbox command.
1950 *
1951 * Input:
1952 * ha = adapter block pointer.
1953 * TARGET_QUEUE_LOCK must be released.
1954 * ADAPTER_STATE_LOCK must be released.
1955 *
1956 * Returns:
1957 * qla2x00 local function return status code.
1958 *
1959 * Context:
1960 * Kernel context.
1961 */
1962int
7b867cf7 1963qla2x00_full_login_lip(scsi_qla_host_t *vha)
1da177e4
LT		 1964{
1965 int rval;
1966 mbx_cmd_t mc;
1967 mbx_cmd_t *mcp = &mc;
1968
7c3df132 1969 ql_dbg(ql_dbg_mbx, vha, 0x1076, "Entered %s.\n", __func__);
1da177e4
LT		 1970
1971 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
7b867cf7 1972 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
0c8c39af 1973 mcp->mb[2] = 0;
1da177e4
LT		 1974 mcp->mb[3] = 0;
1975 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1976 mcp->in_mb = MBX_0;
b93480e3 1977 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1978 mcp->flags = 0;
7b867cf7 1979 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1980
1981 if (rval != QLA_SUCCESS) {
1982 /*EMPTY*/
7c3df132 1983 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
1da177e4
LT		 1984 } else {
1985 /*EMPTY*/
7c3df132 1986 ql_dbg(ql_dbg_mbx, vha, 0x1078, "Done %s.\n", __func__);
1da177e4
LT		 1987 }
1988
1989 return rval;
1990}
1991
1992/*
1993 * qla2x00_get_id_list
1994 *
1995 * Input:
1996 * ha = adapter block pointer.
1997 *
1998 * Returns:
1999 * qla2x00 local function return status code.
2000 *
2001 * Context:
2002 * Kernel context.
2003 */
2004int
7b867cf7 2005qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
1da177e4
LT		 2006 uint16_t *entries)
2007{
2008 int rval;
2009 mbx_cmd_t mc;
2010 mbx_cmd_t *mcp = &mc;
2011
7c3df132 2012 ql_dbg(ql_dbg_mbx, vha, 0x1079, "Entered %s.\n", __func__);
1da177e4
LT		 2013
2014 if (id_list == NULL)
2015 return QLA_FUNCTION_FAILED;
2016
2017 mcp->mb[0] = MBC_GET_ID_LIST;
1c7c6357 2018 mcp->out_mb = MBX_0;
7b867cf7 2019 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 2020 mcp->mb[2] = MSW(id_list_dma);
2021 mcp->mb[3] = LSW(id_list_dma);
2022 mcp->mb[6] = MSW(MSD(id_list_dma));
2023 mcp->mb[7] = LSW(MSD(id_list_dma));
247ec457 2024 mcp->mb[8] = 0;
7b867cf7 2025 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2026 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
1c7c6357
AV		 2027 } else {
2028 mcp->mb[1] = MSW(id_list_dma);
2029 mcp->mb[2] = LSW(id_list_dma);
2030 mcp->mb[3] = MSW(MSD(id_list_dma));
2031 mcp->mb[6] = LSW(MSD(id_list_dma));
2032 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2033 }
1da177e4 2034 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2035 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2036 mcp->flags = 0;
7b867cf7 2037 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2038
2039 if (rval != QLA_SUCCESS) {
2040 /*EMPTY*/
7c3df132 2041 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
1da177e4
LT		 2042 } else {
2043 *entries = mcp->mb[1];
7c3df132 2044 ql_dbg(ql_dbg_mbx, vha, 0x107b, "Done %s.\n", __func__);
1da177e4
LT		 2045 }
2046
2047 return rval;
2048}
2049
2050/*
2051 * qla2x00_get_resource_cnts
2052 * Get current firmware resource counts.
2053 *
2054 * Input:
2055 * ha = adapter block pointer.
2056 *
2057 * Returns:
2058 * qla2x00 local function return status code.
2059 *
2060 * Context:
2061 * Kernel context.
2062 */
2063int
7b867cf7 2064qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
4d0ea247 2065 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
f3a0a77e 2066 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
1da177e4
LT		 2067{
2068 int rval;
2069 mbx_cmd_t mc;
2070 mbx_cmd_t *mcp = &mc;
2071
7c3df132 2072 ql_dbg(ql_dbg_mbx, vha, 0x107c, "Entered %s.\n", __func__);
1da177e4
LT		 2073
2074 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2075 mcp->out_mb = MBX_0;
4d0ea247 2076 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
f3a0a77e
AV		 2077 if (IS_QLA81XX(vha->hw))
2078 mcp->in_mb |= MBX_12;
b93480e3 2079 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2080 mcp->flags = 0;
7b867cf7 2081 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2082
2083 if (rval != QLA_SUCCESS) {
2084 /*EMPTY*/
7c3df132
SK		 2085 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2086 "Failed mb[0]=%x.\n", mcp->mb[0]);
1da177e4 2087 } else {
7c3df132
SK		 2088 ql_dbg(ql_dbg_mbx, vha, 0x107e,
2089 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2090 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2091 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2092 mcp->mb[11], mcp->mb[12]);
1da177e4
LT		 2093
2094 if (cur_xchg_cnt)
2095 *cur_xchg_cnt = mcp->mb[3];
2096 if (orig_xchg_cnt)
2097 *orig_xchg_cnt = mcp->mb[6];
2098 if (cur_iocb_cnt)
2099 *cur_iocb_cnt = mcp->mb[7];
2100 if (orig_iocb_cnt)
2101 *orig_iocb_cnt = mcp->mb[10];
7b867cf7 2102 if (vha->hw->flags.npiv_supported && max_npiv_vports)
4d0ea247 2103 *max_npiv_vports = mcp->mb[11];
f3a0a77e
AV		 2104 if (IS_QLA81XX(vha->hw) && max_fcfs)
2105 *max_fcfs = mcp->mb[12];
1da177e4
LT		 2106 }
2107
2108 return (rval);
2109}
2110
1da177e4
LT		 2111/*
2112 * qla2x00_get_fcal_position_map
2113 * Get FCAL (LILP) position map using mailbox command
2114 *
2115 * Input:
2116 * ha = adapter state pointer.
2117 * pos_map = buffer pointer (can be NULL).
2118 *
2119 * Returns:
2120 * qla2x00 local function return status code.
2121 *
2122 * Context:
2123 * Kernel context.
2124 */
2125int
7b867cf7 2126qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
1da177e4
LT		 2127{
2128 int rval;
2129 mbx_cmd_t mc;
2130 mbx_cmd_t *mcp = &mc;
2131 char *pmap;
2132 dma_addr_t pmap_dma;
7b867cf7 2133 struct qla_hw_data *ha = vha->hw;
1da177e4 2134
7c3df132
SK		 2135 ql_dbg(ql_dbg_mbx, vha, 0x107f, "Entered %s.\n", __func__);
2136
4b89258c 2137 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
1da177e4 2138 if (pmap == NULL) {
7c3df132
SK		 2139 ql_log(ql_log_warn, vha, 0x1080,
2140 "Memory alloc failed.\n");
1da177e4
LT		 2141 return QLA_MEMORY_ALLOC_FAILED;
2142 }
2143 memset(pmap, 0, FCAL_MAP_SIZE);
2144
2145 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2146 mcp->mb[2] = MSW(pmap_dma);
2147 mcp->mb[3] = LSW(pmap_dma);
2148 mcp->mb[6] = MSW(MSD(pmap_dma));
2149 mcp->mb[7] = LSW(MSD(pmap_dma));
2150 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2151 mcp->in_mb = MBX_1|MBX_0;
2152 mcp->buf_size = FCAL_MAP_SIZE;
2153 mcp->flags = MBX_DMA_IN;
2154 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 2155 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2156
2157 if (rval == QLA_SUCCESS) {
7c3df132
SK		 2158 ql_dbg(ql_dbg_mbx, vha, 0x1081,
2159 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2160 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2161 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2162 pmap, pmap[0] + 1);
1da177e4
LT		 2163
2164 if (pos_map)
2165 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2166 }
2167 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2168
2169 if (rval != QLA_SUCCESS) {
7c3df132 2170 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
1da177e4 2171 } else {
7c3df132 2172 ql_dbg(ql_dbg_mbx, vha, 0x1083, "Done %s.\n", __func__);
1da177e4
LT		 2173 }
2174
2175 return rval;
2176}
392e2f65 2177
2178/*
2179 * qla2x00_get_link_status
2180 *
2181 * Input:
2182 * ha = adapter block pointer.
2183 * loop_id = device loop ID.
2184 * ret_buf = pointer to link status return buffer.
2185 *
2186 * Returns:
2187 * 0 = success.
2188 * BIT_0 = mem alloc error.
2189 * BIT_1 = mailbox error.
2190 */
2191int
7b867cf7 2192qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
43ef0580 2193 struct link_statistics *stats, dma_addr_t stats_dma)
392e2f65 2194{
2195 int rval;
2196 mbx_cmd_t mc;
2197 mbx_cmd_t *mcp = &mc;
43ef0580 2198 uint32_t *siter, *diter, dwords;
7b867cf7 2199 struct qla_hw_data *ha = vha->hw;
392e2f65 2200
7c3df132 2201 ql_dbg(ql_dbg_mbx, vha, 0x1084, "Entered %s.\n", __func__);
392e2f65 2202
392e2f65 2203 mcp->mb[0] = MBC_GET_LINK_STATUS;
43ef0580
AV		 2204 mcp->mb[2] = MSW(stats_dma);
2205 mcp->mb[3] = LSW(stats_dma);
2206 mcp->mb[6] = MSW(MSD(stats_dma));
2207 mcp->mb[7] = LSW(MSD(stats_dma));
392e2f65 2208 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2209 mcp->in_mb = MBX_0;
e428924c 2210 if (IS_FWI2_CAPABLE(ha)) {
392e2f65 2211 mcp->mb[1] = loop_id;
2212 mcp->mb[4] = 0;
2213 mcp->mb[10] = 0;
2214 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2215 mcp->in_mb |= MBX_1;
2216 } else if (HAS_EXTENDED_IDS(ha)) {
2217 mcp->mb[1] = loop_id;
2218 mcp->mb[10] = 0;
2219 mcp->out_mb |= MBX_10|MBX_1;
2220 } else {
2221 mcp->mb[1] = loop_id << 8;
2222 mcp->out_mb |= MBX_1;
2223 }
b93480e3 2224 mcp->tov = MBX_TOV_SECONDS;
392e2f65 2225 mcp->flags = IOCTL_CMD;
7b867cf7 2226 rval = qla2x00_mailbox_command(vha, mcp);
392e2f65 2227
2228 if (rval == QLA_SUCCESS) {
2229 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2230 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2231 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
43ef0580 2232 rval = QLA_FUNCTION_FAILED;
392e2f65 2233 } else {
43ef0580 2234 /* Copy over data -- firmware data is LE. */
7c3df132 2235 ql_dbg(ql_dbg_mbx, vha, 0x1086, "Done %s.\n", __func__);
43ef0580
AV		 2236 dwords = offsetof(struct link_statistics, unused1) / 4;
2237 siter = diter = &stats->link_fail_cnt;
2238 while (dwords--)
2239 *diter++ = le32_to_cpu(*siter++);
392e2f65 2240 }
2241 } else {
2242 /* Failed. */
7c3df132 2243 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
392e2f65 2244 }
2245
392e2f65 2246 return rval;
2247}
2248
2249int
7b867cf7 2250qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
43ef0580 2251 dma_addr_t stats_dma)
1c7c6357
AV		 2252{
2253 int rval;
2254 mbx_cmd_t mc;
2255 mbx_cmd_t *mcp = &mc;
43ef0580 2256 uint32_t *siter, *diter, dwords;
1c7c6357 2257
7c3df132 2258 ql_dbg(ql_dbg_mbx, vha, 0x1088, "Entered %s.\n", __func__);
1c7c6357 2259
1c7c6357 2260 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
43ef0580
AV		 2261 mcp->mb[2] = MSW(stats_dma);
2262 mcp->mb[3] = LSW(stats_dma);
2263 mcp->mb[6] = MSW(MSD(stats_dma));
2264 mcp->mb[7] = LSW(MSD(stats_dma));
2265 mcp->mb[8] = sizeof(struct link_statistics) / 4;
7b867cf7 2266 mcp->mb[9] = vha->vp_idx;
1c7c6357 2267 mcp->mb[10] = 0;
43ef0580 2268 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1c7c6357 2269 mcp->in_mb = MBX_2|MBX_1|MBX_0;
b93480e3 2270 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 2271 mcp->flags = IOCTL_CMD;
7b867cf7 2272 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 2273
2274 if (rval == QLA_SUCCESS) {
2275 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2276 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2277 "Failed mb[0]=%x.\n", mcp->mb[0]);
43ef0580 2278 rval = QLA_FUNCTION_FAILED;
1c7c6357 2279 } else {
7c3df132 2280 ql_dbg(ql_dbg_mbx, vha, 0x108a, "Done %s.\n", __func__);
1c7c6357 2281 /* Copy over data -- firmware data is LE. */
43ef0580
AV		 2282 dwords = sizeof(struct link_statistics) / 4;
2283 siter = diter = &stats->link_fail_cnt;
1c7c6357 2284 while (dwords--)
43ef0580 2285 *diter++ = le32_to_cpu(*siter++);
1c7c6357
AV		 2286 }
2287 } else {
2288 /* Failed. */
7c3df132 2289 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
1c7c6357
AV		 2290 }
2291
1c7c6357
AV		 2292 return rval;
2293}
1c7c6357
AV		 2294
2295int
2afa19a9 2296qla24xx_abort_command(srb_t *sp)
1c7c6357
AV		 2297{
2298 int rval;
1c7c6357
AV		 2299 unsigned long flags = 0;
2300
2301 struct abort_entry_24xx *abt;
2302 dma_addr_t abt_dma;
2303 uint32_t handle;
2afa19a9
AC		 2304 fc_port_t *fcport = sp->fcport;
2305 struct scsi_qla_host *vha = fcport->vha;
7b867cf7 2306 struct qla_hw_data *ha = vha->hw;
67c2e93a 2307 struct req_que *req = vha->req;
1c7c6357 2308
7c3df132 2309 ql_dbg(ql_dbg_mbx, vha, 0x108c, "Entered %s.\n", __func__);
1c7c6357 2310
7b867cf7 2311 spin_lock_irqsave(&ha->hardware_lock, flags);
1c7c6357 2312 for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
7b867cf7 2313 if (req->outstanding_cmds[handle] == sp)
1c7c6357
AV		 2314 break;
2315 }
7b867cf7 2316 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1c7c6357
AV		 2317 if (handle == MAX_OUTSTANDING_COMMANDS) {
2318 /* Command not found. */
2319 return QLA_FUNCTION_FAILED;
2320 }
2321
2322 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2323 if (abt == NULL) {
7c3df132
SK		 2324 ql_log(ql_log_warn, vha, 0x108d,
2325 "Failed to allocate abort IOCB.\n");
1c7c6357
AV		 2326 return QLA_MEMORY_ALLOC_FAILED;
2327 }
2328 memset(abt, 0, sizeof(struct abort_entry_24xx));
2329
2330 abt->entry_type = ABORT_IOCB_TYPE;
2331 abt->entry_count = 1;
2afa19a9 2332 abt->handle = MAKE_HANDLE(req->id, abt->handle);
1c7c6357 2333 abt->nport_handle = cpu_to_le16(fcport->loop_id);
a74ec14f 2334 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
1c7c6357
AV		 2335 abt->port_id[0] = fcport->d_id.b.al_pa;
2336 abt->port_id[1] = fcport->d_id.b.area;
2337 abt->port_id[2] = fcport->d_id.b.domain;
2c3dfe3f 2338 abt->vp_index = fcport->vp_idx;
73208dfd
AC		 2339
2340 abt->req_que_no = cpu_to_le16(req->id);
2341
7b867cf7 2342 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
1c7c6357 2343 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2344 ql_dbg(ql_dbg_mbx, vha, 0x108e,
2345 "Failed to issue IOCB (%x).\n", rval);
1c7c6357 2346 } else if (abt->entry_status != 0) {
7c3df132
SK		 2347 ql_dbg(ql_dbg_mbx, vha, 0x108f,
2348 "Failed to complete IOCB -- error status (%x).\n",
2349 abt->entry_status);
1c7c6357
AV		 2350 rval = QLA_FUNCTION_FAILED;
2351 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
7c3df132
SK		 2352 ql_dbg(ql_dbg_mbx, vha, 0x1090,
2353 "Failed to complete IOCB -- completion status (%x).\n",
2354 le16_to_cpu(abt->nport_handle));
1c7c6357
AV		 2355 rval = QLA_FUNCTION_FAILED;
2356 } else {
7c3df132 2357 ql_dbg(ql_dbg_mbx, vha, 0x1091, "Done %s.\n", __func__);
1c7c6357
AV		 2358 }
2359
2360 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
2361
2362 return rval;
2363}
2364
2365struct tsk_mgmt_cmd {
2366 union {
2367 struct tsk_mgmt_entry tsk;
2368 struct sts_entry_24xx sts;
2369 } p;
2370};
2371
523ec773
AV		 2372static int
2373__qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
2afa19a9 2374 unsigned int l, int tag)
1c7c6357 2375{
523ec773 2376 int rval, rval2;
1c7c6357 2377 struct tsk_mgmt_cmd *tsk;
9ca1d01f 2378 struct sts_entry_24xx *sts;
1c7c6357 2379 dma_addr_t tsk_dma;
7b867cf7
AC		 2380 scsi_qla_host_t *vha;
2381 struct qla_hw_data *ha;
73208dfd
AC		 2382 struct req_que *req;
2383 struct rsp_que *rsp;
1c7c6357 2384
7b867cf7
AC		 2385 vha = fcport->vha;
2386 ha = vha->hw;
2afa19a9 2387 req = vha->req;
7c3df132
SK		 2388
2389 ql_dbg(ql_dbg_mbx, vha, 0x1092, "Entered %s.\n", __func__);
2390
7163ea81 2391 if (ha->flags.cpu_affinity_enabled)
68ca949c
AC		 2392 rsp = ha->rsp_q_map[tag + 1];
2393 else
2394 rsp = req->rsp;
7b867cf7 2395 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
1c7c6357 2396 if (tsk == NULL) {
7c3df132
SK		 2397 ql_log(ql_log_warn, vha, 0x1093,
2398 "Failed to allocate task management IOCB.\n");
1c7c6357
AV		 2399 return QLA_MEMORY_ALLOC_FAILED;
2400 }
2401 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
2402
2403 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
2404 tsk->p.tsk.entry_count = 1;
2afa19a9 2405 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
1c7c6357 2406 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
00a537b8 2407 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
523ec773 2408 tsk->p.tsk.control_flags = cpu_to_le32(type);
1c7c6357
AV		 2409 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
2410 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
2411 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
2c3dfe3f 2412 tsk->p.tsk.vp_index = fcport->vp_idx;
523ec773
AV		 2413 if (type == TCF_LUN_RESET) {
2414 int_to_scsilun(l, &tsk->p.tsk.lun);
2415 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
2416 sizeof(tsk->p.tsk.lun));
2417 }
2c3dfe3f 2418
9ca1d01f 2419 sts = &tsk->p.sts;
7b867cf7 2420 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
1c7c6357 2421 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2422 ql_dbg(ql_dbg_mbx, vha, 0x1094,
2423 "Failed to issue %s reset IOCB (%x).\n", name, rval);
9ca1d01f 2424 } else if (sts->entry_status != 0) {
7c3df132
SK		 2425 ql_dbg(ql_dbg_mbx, vha, 0x1095,
2426 "Failed to complete IOCB -- error status (%x).\n",
2427 sts->entry_status);
1c7c6357 2428 rval = QLA_FUNCTION_FAILED;
9ca1d01f 2429 } else if (sts->comp_status !=
1c7c6357 2430 __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2431 ql_dbg(ql_dbg_mbx, vha, 0x1096,
2432 "Failed to complete IOCB -- completion status (%x).\n",
2433 le16_to_cpu(sts->comp_status));
9ca1d01f 2434 rval = QLA_FUNCTION_FAILED;
97dec564
AV		 2435 } else if (le16_to_cpu(sts->scsi_status) &
2436 SS_RESPONSE_INFO_LEN_VALID) {
2437 if (le32_to_cpu(sts->rsp_data_len) < 4) {
7c3df132
SK		 2438 ql_dbg(ql_dbg_mbx, vha, 0x1097,
2439 "Ignoring inconsistent data length -- not enough "
2440 "response info (%d).\n",
2441 le32_to_cpu(sts->rsp_data_len));
97dec564 2442 } else if (sts->data[3]) {
7c3df132
SK		 2443 ql_dbg(ql_dbg_mbx, vha, 0x1098,
2444 "Failed to complete IOCB -- response (%x).\n",
2445 sts->data[3]);
97dec564
AV		 2446 rval = QLA_FUNCTION_FAILED;
2447 }
1c7c6357
AV		 2448 }
2449
2450 /* Issue marker IOCB. */
73208dfd 2451 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
523ec773
AV		 2452 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
2453 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2454 ql_dbg(ql_dbg_mbx, vha, 0x1099,
2455 "Failed to issue marker IOCB (%x).\n", rval2);
1c7c6357 2456 } else {
7c3df132 2457 ql_dbg(ql_dbg_mbx, vha, 0x109a, "Done %s.\n", __func__);
1c7c6357
AV		 2458 }
2459
7b867cf7 2460 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
1c7c6357
AV		 2461
2462 return rval;
2463}
2464
523ec773 2465int
2afa19a9 2466qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
523ec773 2467{
3822263e
MI		 2468 struct qla_hw_data *ha = fcport->vha->hw;
2469
2470 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2471 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
2472
2afa19a9 2473 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
523ec773
AV		 2474}
2475
2476int
2afa19a9 2477qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
523ec773 2478{
3822263e
MI		 2479 struct qla_hw_data *ha = fcport->vha->hw;
2480
2481 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2482 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
2483
2afa19a9 2484 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
523ec773
AV		 2485}
2486
1c7c6357 2487int
7b867cf7 2488qla2x00_system_error(scsi_qla_host_t *vha)
1c7c6357
AV		 2489{
2490 int rval;
2491 mbx_cmd_t mc;
2492 mbx_cmd_t *mcp = &mc;
7b867cf7 2493 struct qla_hw_data *ha = vha->hw;
1c7c6357 2494
68af0811 2495 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 2496 return QLA_FUNCTION_FAILED;
2497
7c3df132 2498 ql_dbg(ql_dbg_mbx, vha, 0x109b, "Entered %s.\n", __func__);
1c7c6357
AV		 2499
2500 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
2501 mcp->out_mb = MBX_0;
2502 mcp->in_mb = MBX_0;
2503 mcp->tov = 5;
2504 mcp->flags = 0;
7b867cf7 2505 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 2506
2507 if (rval != QLA_SUCCESS) {
7c3df132 2508 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
1c7c6357 2509 } else {
7c3df132 2510 ql_dbg(ql_dbg_mbx, vha, 0x109d, "Done %s.\n", __func__);
1c7c6357
AV		 2511 }
2512
2513 return rval;
2514}
2515
1c7c6357
AV		 2516/**
2517 * qla2x00_set_serdes_params() -
2518 * @ha: HA context
2519 *
2520 * Returns
2521 */
2522int
7b867cf7 2523qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
1c7c6357
AV		 2524 uint16_t sw_em_2g, uint16_t sw_em_4g)
2525{
2526 int rval;
2527 mbx_cmd_t mc;
2528 mbx_cmd_t *mcp = &mc;
2529
7c3df132 2530 ql_dbg(ql_dbg_mbx, vha, 0x109e, "Entered %s.\n", __func__);
1c7c6357
AV		 2531
2532 mcp->mb[0] = MBC_SERDES_PARAMS;
2533 mcp->mb[1] = BIT_0;
fdbc6833 2534 mcp->mb[2] = sw_em_1g | BIT_15;
2535 mcp->mb[3] = sw_em_2g | BIT_15;
2536 mcp->mb[4] = sw_em_4g | BIT_15;
1c7c6357
AV		 2537 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2538 mcp->in_mb = MBX_0;
b93480e3 2539 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 2540 mcp->flags = 0;
7b867cf7 2541 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 2542
2543 if (rval != QLA_SUCCESS) {
2544 /*EMPTY*/
7c3df132
SK		 2545 ql_dbg(ql_dbg_mbx, vha, 0x109f,
2546 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357
AV		 2547 } else {
2548 /*EMPTY*/
7c3df132 2549 ql_dbg(ql_dbg_mbx, vha, 0x10a0, "Done %s.\n", __func__);
1c7c6357
AV		 2550 }
2551
2552 return rval;
2553}
f6ef3b18
AV		 2554
2555int
7b867cf7 2556qla2x00_stop_firmware(scsi_qla_host_t *vha)
f6ef3b18
AV		 2557{
2558 int rval;
2559 mbx_cmd_t mc;
2560 mbx_cmd_t *mcp = &mc;
2561
7b867cf7 2562 if (!IS_FWI2_CAPABLE(vha->hw))
f6ef3b18
AV		 2563 return QLA_FUNCTION_FAILED;
2564
7c3df132 2565 ql_dbg(ql_dbg_mbx, vha, 0x10a1, "Entered %s.\n", __func__);
f6ef3b18
AV		 2566
2567 mcp->mb[0] = MBC_STOP_FIRMWARE;
2568 mcp->out_mb = MBX_0;
2569 mcp->in_mb = MBX_0;
2570 mcp->tov = 5;
2571 mcp->flags = 0;
7b867cf7 2572 rval = qla2x00_mailbox_command(vha, mcp);
f6ef3b18
AV		 2573
2574 if (rval != QLA_SUCCESS) {
7c3df132 2575 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
b469a7cb
AV		 2576 if (mcp->mb[0] == MBS_INVALID_COMMAND)
2577 rval = QLA_INVALID_COMMAND;
f6ef3b18 2578 } else {
7c3df132 2579 ql_dbg(ql_dbg_mbx, vha, 0x10a3, "Done %s.\n", __func__);
f6ef3b18
AV		 2580 }
2581
2582 return rval;
2583}
a7a167bf
AV		 2584
2585int
7b867cf7 2586qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
a7a167bf
AV		 2587 uint16_t buffers)
2588{
2589 int rval;
2590 mbx_cmd_t mc;
2591 mbx_cmd_t *mcp = &mc;
2592
7c3df132
SK		 2593 ql_dbg(ql_dbg_mbx, vha, 0x10a4, "Entered %s.\n", __func__);
2594
7b867cf7 2595 if (!IS_FWI2_CAPABLE(vha->hw))
a7a167bf
AV		 2596 return QLA_FUNCTION_FAILED;
2597
85880801
AV		 2598 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2599 return QLA_FUNCTION_FAILED;
2600
a7a167bf 2601 mcp->mb[0] = MBC_TRACE_CONTROL;
00b6bd25
AV		 2602 mcp->mb[1] = TC_EFT_ENABLE;
2603 mcp->mb[2] = LSW(eft_dma);
2604 mcp->mb[3] = MSW(eft_dma);
2605 mcp->mb[4] = LSW(MSD(eft_dma));
2606 mcp->mb[5] = MSW(MSD(eft_dma));
2607 mcp->mb[6] = buffers;
2608 mcp->mb[7] = TC_AEN_DISABLE;
2609 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
a7a167bf 2610 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2611 mcp->tov = MBX_TOV_SECONDS;
a7a167bf 2612 mcp->flags = 0;
7b867cf7 2613 rval = qla2x00_mailbox_command(vha, mcp);
00b6bd25 2614 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2615 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
2616 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2617 rval, mcp->mb[0], mcp->mb[1]);
00b6bd25 2618 } else {
7c3df132 2619 ql_dbg(ql_dbg_mbx, vha, 0x10a6, "Done %s.\n", __func__);
00b6bd25
AV		 2620 }
2621
2622 return rval;
2623}
a7a167bf 2624
00b6bd25 2625int
7b867cf7 2626qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
00b6bd25
AV		 2627{
2628 int rval;
2629 mbx_cmd_t mc;
2630 mbx_cmd_t *mcp = &mc;
2631
7c3df132
SK		 2632 ql_dbg(ql_dbg_mbx, vha, 0x10a7, "Entered %s.\n", __func__);
2633
7b867cf7 2634 if (!IS_FWI2_CAPABLE(vha->hw))
00b6bd25
AV		 2635 return QLA_FUNCTION_FAILED;
2636
85880801
AV		 2637 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2638 return QLA_FUNCTION_FAILED;
2639
00b6bd25
AV		 2640 mcp->mb[0] = MBC_TRACE_CONTROL;
2641 mcp->mb[1] = TC_EFT_DISABLE;
2642 mcp->out_mb = MBX_1|MBX_0;
2643 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2644 mcp->tov = MBX_TOV_SECONDS;
00b6bd25 2645 mcp->flags = 0;
7b867cf7 2646 rval = qla2x00_mailbox_command(vha, mcp);
a7a167bf 2647 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2648 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
2649 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2650 rval, mcp->mb[0], mcp->mb[1]);
a7a167bf 2651 } else {
7c3df132 2652 ql_dbg(ql_dbg_mbx, vha, 0x10a9, "Done %s.\n", __func__);
a7a167bf
AV		 2653 }
2654
2655 return rval;
2656}
2657
df613b96 2658int
7b867cf7 2659qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
df613b96
AV		 2660 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
2661{
2662 int rval;
2663 mbx_cmd_t mc;
2664 mbx_cmd_t *mcp = &mc;
2665
7c3df132
SK		 2666 ql_dbg(ql_dbg_mbx, vha, 0x10aa, "Entered %s.\n", __func__);
2667
3a03eb79 2668 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw))
df613b96
AV		 2669 return QLA_FUNCTION_FAILED;
2670
85880801
AV		 2671 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2672 return QLA_FUNCTION_FAILED;
2673
df613b96
AV		 2674 mcp->mb[0] = MBC_TRACE_CONTROL;
2675 mcp->mb[1] = TC_FCE_ENABLE;
2676 mcp->mb[2] = LSW(fce_dma);
2677 mcp->mb[3] = MSW(fce_dma);
2678 mcp->mb[4] = LSW(MSD(fce_dma));
2679 mcp->mb[5] = MSW(MSD(fce_dma));
2680 mcp->mb[6] = buffers;
2681 mcp->mb[7] = TC_AEN_DISABLE;
2682 mcp->mb[8] = 0;
2683 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
2684 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
2685 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
2686 MBX_1|MBX_0;
2687 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 2688 mcp->tov = MBX_TOV_SECONDS;
df613b96 2689 mcp->flags = 0;
7b867cf7 2690 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 2691 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2692 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
2693 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2694 rval, mcp->mb[0], mcp->mb[1]);
df613b96 2695 } else {
7c3df132 2696 ql_dbg(ql_dbg_mbx, vha, 0x10ac, "Done %s.\n", __func__);
df613b96
AV		 2697
2698 if (mb)
2699 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
2700 if (dwords)
fa0926df 2701 *dwords = buffers;
df613b96
AV		 2702 }
2703
2704 return rval;
2705}
2706
2707int
7b867cf7 2708qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
df613b96
AV		 2709{
2710 int rval;
2711 mbx_cmd_t mc;
2712 mbx_cmd_t *mcp = &mc;
2713
7c3df132
SK		 2714 ql_dbg(ql_dbg_mbx, vha, 0x10ad, "Entered %s.\n", __func__);
2715
7b867cf7 2716 if (!IS_FWI2_CAPABLE(vha->hw))
df613b96
AV		 2717 return QLA_FUNCTION_FAILED;
2718
85880801
AV		 2719 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2720 return QLA_FUNCTION_FAILED;
2721
df613b96
AV		 2722 mcp->mb[0] = MBC_TRACE_CONTROL;
2723 mcp->mb[1] = TC_FCE_DISABLE;
2724 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
2725 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2726 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
2727 MBX_1|MBX_0;
b93480e3 2728 mcp->tov = MBX_TOV_SECONDS;
df613b96 2729 mcp->flags = 0;
7b867cf7 2730 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 2731 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2732 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
2733 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2734 rval, mcp->mb[0], mcp->mb[1]);
df613b96 2735 } else {
7c3df132 2736 ql_dbg(ql_dbg_mbx, vha, 0x10af, "Done %s.\n", __func__);
df613b96
AV		 2737
2738 if (wr)
2739 *wr = (uint64_t) mcp->mb[5] << 48 |
2740 (uint64_t) mcp->mb[4] << 32 |
2741 (uint64_t) mcp->mb[3] << 16 |
2742 (uint64_t) mcp->mb[2];
2743 if (rd)
2744 *rd = (uint64_t) mcp->mb[9] << 48 |
2745 (uint64_t) mcp->mb[8] << 32 |
2746 (uint64_t) mcp->mb[7] << 16 |
2747 (uint64_t) mcp->mb[6];
2748 }
2749
2750 return rval;
2751}
2752
6e98016c
GM		 2753int
2754qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
2755 uint16_t *port_speed, uint16_t *mb)
2756{
2757 int rval;
2758 mbx_cmd_t mc;
2759 mbx_cmd_t *mcp = &mc;
2760
7c3df132
SK		 2761 ql_dbg(ql_dbg_mbx, vha, 0x10b0, "Entered %s.\n", __func__);
2762
6e98016c
GM		 2763 if (!IS_IIDMA_CAPABLE(vha->hw))
2764 return QLA_FUNCTION_FAILED;
2765
6e98016c
GM		 2766 mcp->mb[0] = MBC_PORT_PARAMS;
2767 mcp->mb[1] = loop_id;
2768 mcp->mb[2] = mcp->mb[3] = 0;
2769 mcp->mb[9] = vha->vp_idx;
2770 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
2771 mcp->in_mb = MBX_3|MBX_1|MBX_0;
2772 mcp->tov = MBX_TOV_SECONDS;
2773 mcp->flags = 0;
2774 rval = qla2x00_mailbox_command(vha, mcp);
2775
2776 /* Return mailbox statuses. */
2777 if (mb != NULL) {
2778 mb[0] = mcp->mb[0];
2779 mb[1] = mcp->mb[1];
2780 mb[3] = mcp->mb[3];
2781 }
2782
2783 if (rval != QLA_SUCCESS) {
7c3df132 2784 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
6e98016c 2785 } else {
7c3df132 2786 ql_dbg(ql_dbg_mbx, vha, 0x10b2, "Done %s.\n", __func__);
6e98016c
GM		 2787 if (port_speed)
2788 *port_speed = mcp->mb[3];
2789 }
2790
2791 return rval;
2792}
2793
d8b45213 2794int
7b867cf7 2795qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
d8b45213
AV		 2796 uint16_t port_speed, uint16_t *mb)
2797{
2798 int rval;
2799 mbx_cmd_t mc;
2800 mbx_cmd_t *mcp = &mc;
2801
7c3df132
SK		 2802 ql_dbg(ql_dbg_mbx, vha, 0x10b3, "Entered %s.\n", __func__);
2803
7b867cf7 2804 if (!IS_IIDMA_CAPABLE(vha->hw))
d8b45213
AV		 2805 return QLA_FUNCTION_FAILED;
2806
d8b45213
AV		 2807 mcp->mb[0] = MBC_PORT_PARAMS;
2808 mcp->mb[1] = loop_id;
2809 mcp->mb[2] = BIT_0;
a9083016 2810 if (IS_QLA8XXX_TYPE(vha->hw))
1bb39548
HZ		 2811 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
2812 else
2813 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
2814 mcp->mb[9] = vha->vp_idx;
2815 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
2816 mcp->in_mb = MBX_3|MBX_1|MBX_0;
b93480e3 2817 mcp->tov = MBX_TOV_SECONDS;
d8b45213 2818 mcp->flags = 0;
7b867cf7 2819 rval = qla2x00_mailbox_command(vha, mcp);
d8b45213
AV		 2820
2821 /* Return mailbox statuses. */
2822 if (mb != NULL) {
2823 mb[0] = mcp->mb[0];
2824 mb[1] = mcp->mb[1];
2825 mb[3] = mcp->mb[3];
d8b45213
AV		 2826 }
2827
2828 if (rval != QLA_SUCCESS) {
7c3df132 2829 ql_dbg(ql_dbg_mbx, vha, 0x10b4, "Failed=%x.\n", rval);
d8b45213 2830 } else {
7c3df132 2831 ql_dbg(ql_dbg_mbx, vha, 0x10b5, "Done %s.\n", __func__);
d8b45213
AV		 2832 }
2833
2834 return rval;
2835}
2c3dfe3f 2836
2c3dfe3f 2837void
7b867cf7 2838qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2c3dfe3f
SJ		 2839 struct vp_rpt_id_entry_24xx *rptid_entry)
2840{
2841 uint8_t vp_idx;
c6852c4c 2842 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
7b867cf7
AC		 2843 struct qla_hw_data *ha = vha->hw;
2844 scsi_qla_host_t *vp;
feafb7b1 2845 unsigned long flags;
2c3dfe3f 2846
7c3df132
SK		 2847 ql_dbg(ql_dbg_mbx, vha, 0x10b6, "Entered %s.\n", __func__);
2848
2c3dfe3f
SJ		 2849 if (rptid_entry->entry_status != 0)
2850 return;
2c3dfe3f
SJ		 2851
2852 if (rptid_entry->format == 0) {
7c3df132
SK		 2853 ql_dbg(ql_dbg_mbx, vha, 0x10b7,
2854 "Format 0 : Number of VPs setup %d, number of "
2855 "VPs acquired %d.\n",
2856 MSB(le16_to_cpu(rptid_entry->vp_count)),
2857 LSB(le16_to_cpu(rptid_entry->vp_count)));
2858 ql_dbg(ql_dbg_mbx, vha, 0x10b8,
2859 "Primary port id %02x%02x%02x.\n",
2860 rptid_entry->port_id[2], rptid_entry->port_id[1],
2861 rptid_entry->port_id[0]);
2c3dfe3f 2862 } else if (rptid_entry->format == 1) {
c6852c4c 2863 vp_idx = LSB(stat);
7c3df132
SK		 2864 ql_dbg(ql_dbg_mbx, vha, 0x10b9,
2865 "Format 1: VP[%d] enabled - status %d - with "
2866 "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
2c3dfe3f 2867 rptid_entry->port_id[2], rptid_entry->port_id[1],
7c3df132 2868 rptid_entry->port_id[0]);
531a82d1
AV		 2869
2870 vp = vha;
2871 if (vp_idx == 0 && (MSB(stat) != 1))
2872 goto reg_needed;
2c3dfe3f 2873
81eb9b49 2874 if (MSB(stat) == 1) {
7c3df132
SK		 2875 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
2876 "Could not acquire ID for VP[%d].\n", vp_idx);
2c3dfe3f 2877 return;
81eb9b49 2878 }
2c3dfe3f 2879
feafb7b1
AE		 2880 spin_lock_irqsave(&ha->vport_slock, flags);
2881 list_for_each_entry(vp, &ha->vp_list, list)
7b867cf7 2882 if (vp_idx == vp->vp_idx)
2c3dfe3f 2883 break;
feafb7b1
AE		 2884 spin_unlock_irqrestore(&ha->vport_slock, flags);
2885
7b867cf7 2886 if (!vp)
2c3dfe3f
SJ		 2887 return;
2888
7b867cf7
AC		 2889 vp->d_id.b.domain = rptid_entry->port_id[2];
2890 vp->d_id.b.area = rptid_entry->port_id[1];
2891 vp->d_id.b.al_pa = rptid_entry->port_id[0];
2c3dfe3f
SJ		 2892
2893 /*
2894 * Cannot configure here as we are still sitting on the
2895 * response queue. Handle it in dpc context.
2896 */
7b867cf7 2897 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
2c3dfe3f 2898
531a82d1
AV		 2899reg_needed:
2900 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
2901 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
2902 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
7b867cf7 2903 qla2xxx_wake_dpc(vha);
2c3dfe3f
SJ		 2904 }
2905}
2906
2907/*
2908 * qla24xx_modify_vp_config
2909 * Change VP configuration for vha
2910 *
2911 * Input:
2912 * vha = adapter block pointer.
2913 *
2914 * Returns:
2915 * qla2xxx local function return status code.
2916 *
2917 * Context:
2918 * Kernel context.
2919 */
2920int
2921qla24xx_modify_vp_config(scsi_qla_host_t *vha)
2922{
2923 int rval;
2924 struct vp_config_entry_24xx *vpmod;
2925 dma_addr_t vpmod_dma;
7b867cf7
AC		 2926 struct qla_hw_data *ha = vha->hw;
2927 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f
SJ		 2928
2929 /* This can be called by the parent */
2c3dfe3f 2930
7c3df132
SK		 2931 ql_dbg(ql_dbg_mbx, vha, 0x10bb, "Entered %s.\n", __func__);
2932
7b867cf7 2933 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2c3dfe3f 2934 if (!vpmod) {
7c3df132
SK		 2935 ql_log(ql_log_warn, vha, 0x10bc,
2936 "Failed to allocate modify VP IOCB.\n");
2c3dfe3f
SJ		 2937 return QLA_MEMORY_ALLOC_FAILED;
2938 }
2939
2940 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
2941 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
2942 vpmod->entry_count = 1;
2943 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
2944 vpmod->vp_count = 1;
2945 vpmod->vp_index1 = vha->vp_idx;
2946 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2947 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
2948 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
2949 vpmod->entry_count = 1;
2950
7b867cf7 2951 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2c3dfe3f 2952 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2953 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
2954 "Failed to issue VP config IOCB (%x).\n", rval);
2c3dfe3f 2955 } else if (vpmod->comp_status != 0) {
7c3df132
SK		 2956 ql_dbg(ql_dbg_mbx, vha, 0x10be,
2957 "Failed to complete IOCB -- error status (%x).\n",
2958 vpmod->comp_status);
2c3dfe3f
SJ		 2959 rval = QLA_FUNCTION_FAILED;
2960 } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2961 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
2962 "Failed to complete IOCB -- completion status (%x).\n",
2963 le16_to_cpu(vpmod->comp_status));
2c3dfe3f
SJ		 2964 rval = QLA_FUNCTION_FAILED;
2965 } else {
2966 /* EMPTY */
7c3df132 2967 ql_dbg(ql_dbg_mbx, vha, 0x10c0, "Done %s.\n", __func__);
2c3dfe3f
SJ		 2968 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
2969 }
7b867cf7 2970 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2c3dfe3f
SJ		 2971
2972 return rval;
2973}
2974
2975/*
2976 * qla24xx_control_vp
2977 * Enable a virtual port for given host
2978 *
2979 * Input:
2980 * ha = adapter block pointer.
2981 * vhba = virtual adapter (unused)
2982 * index = index number for enabled VP
2983 *
2984 * Returns:
2985 * qla2xxx local function return status code.
2986 *
2987 * Context:
2988 * Kernel context.
2989 */
2990int
2991qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
2992{
2993 int rval;
2994 int map, pos;
2995 struct vp_ctrl_entry_24xx *vce;
2996 dma_addr_t vce_dma;
7b867cf7 2997 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 2998 int vp_index = vha->vp_idx;
7b867cf7 2999 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 3000
7c3df132
SK		 3001 ql_dbg(ql_dbg_mbx, vha, 0x10c1,
3002 "Entered %s enabling index %d.\n", __func__, vp_index);
2c3dfe3f 3003
eb66dc60 3004 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
2c3dfe3f
SJ		 3005 return QLA_PARAMETER_ERROR;
3006
3007 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3008 if (!vce) {
7c3df132
SK		 3009 ql_log(ql_log_warn, vha, 0x10c2,
3010 "Failed to allocate VP control IOCB.\n");
2c3dfe3f
SJ		 3011 return QLA_MEMORY_ALLOC_FAILED;
3012 }
3013 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3014
3015 vce->entry_type = VP_CTRL_IOCB_TYPE;
3016 vce->entry_count = 1;
3017 vce->command = cpu_to_le16(cmd);
3018 vce->vp_count = __constant_cpu_to_le16(1);
3019
3020 /* index map in firmware starts with 1; decrement index
3021 * this is ok as we never use index 0
3022 */
3023 map = (vp_index - 1) / 8;
3024 pos = (vp_index - 1) & 7;
6c2f527c 3025 mutex_lock(&ha->vport_lock);
2c3dfe3f 3026 vce->vp_idx_map[map] |= 1 << pos;
6c2f527c 3027 mutex_unlock(&ha->vport_lock);
2c3dfe3f 3028
7b867cf7 3029 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
2c3dfe3f 3030 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3031 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3032 "Failed to issue VP control IOCB (%x).\n", rval);
2c3dfe3f 3033 } else if (vce->entry_status != 0) {
7c3df132
SK		 3034 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3035 "Failed to complete IOCB -- error status (%x).\n",
2c3dfe3f
SJ		 3036 vce->entry_status);
3037 rval = QLA_FUNCTION_FAILED;
3038 } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3039 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
3040 "Failed to complet IOCB -- completion status (%x).\n",
2c3dfe3f
SJ		 3041 le16_to_cpu(vce->comp_status));
3042 rval = QLA_FUNCTION_FAILED;
3043 } else {
7c3df132 3044 ql_dbg(ql_dbg_mbx, vha, 0x10c6, "Done %s.\n", __func__);
2c3dfe3f
SJ		 3045 }
3046
3047 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3048
3049 return rval;
3050}
3051
3052/*
3053 * qla2x00_send_change_request
3054 * Receive or disable RSCN request from fabric controller
3055 *
3056 * Input:
3057 * ha = adapter block pointer
3058 * format = registration format:
3059 * 0 - Reserved
3060 * 1 - Fabric detected registration
3061 * 2 - N_port detected registration
3062 * 3 - Full registration
3063 * FF - clear registration
3064 * vp_idx = Virtual port index
3065 *
3066 * Returns:
3067 * qla2x00 local function return status code.
3068 *
3069 * Context:
3070 * Kernel Context
3071 */
3072
3073int
7b867cf7 3074qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
2c3dfe3f
SJ		 3075 uint16_t vp_idx)
3076{
3077 int rval;
3078 mbx_cmd_t mc;
3079 mbx_cmd_t *mcp = &mc;
3080
7c3df132
SK		 3081 ql_dbg(ql_dbg_mbx, vha, 0x10c7, "Entered %s.\n", __func__);
3082
2c3dfe3f
SJ		 3083 /*
3084 * This command is implicitly executed by firmware during login for the
3085 * physical hosts
3086 */
3087 if (vp_idx == 0)
3088 return QLA_FUNCTION_FAILED;
3089
3090 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3091 mcp->mb[1] = format;
3092 mcp->mb[9] = vp_idx;
3093 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3094 mcp->in_mb = MBX_0|MBX_1;
3095 mcp->tov = MBX_TOV_SECONDS;
3096 mcp->flags = 0;
7b867cf7 3097 rval = qla2x00_mailbox_command(vha, mcp);
2c3dfe3f
SJ		 3098
3099 if (rval == QLA_SUCCESS) {
3100 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3101 rval = BIT_1;
3102 }
3103 } else
3104 rval = BIT_1;
3105
3106 return rval;
3107}
338c9161
AV		 3108
3109int
7b867cf7 3110qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
338c9161
AV		 3111 uint32_t size)
3112{
3113 int rval;
3114 mbx_cmd_t mc;
3115 mbx_cmd_t *mcp = &mc;
3116
7c3df132 3117 ql_dbg(ql_dbg_mbx, vha, 0x1009, "Entered %s.\n", __func__);
338c9161 3118
7b867cf7 3119 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3120 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3121 mcp->mb[8] = MSW(addr);
3122 mcp->out_mb = MBX_8|MBX_0;
3123 } else {
3124 mcp->mb[0] = MBC_DUMP_RISC_RAM;
3125 mcp->out_mb = MBX_0;
3126 }
3127 mcp->mb[1] = LSW(addr);
3128 mcp->mb[2] = MSW(req_dma);
3129 mcp->mb[3] = LSW(req_dma);
3130 mcp->mb[6] = MSW(MSD(req_dma));
3131 mcp->mb[7] = LSW(MSD(req_dma));
3132 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
7b867cf7 3133 if (IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3134 mcp->mb[4] = MSW(size);
3135 mcp->mb[5] = LSW(size);
3136 mcp->out_mb |= MBX_5|MBX_4;
3137 } else {
3138 mcp->mb[4] = LSW(size);
3139 mcp->out_mb |= MBX_4;
3140 }
3141
3142 mcp->in_mb = MBX_0;
b93480e3 3143 mcp->tov = MBX_TOV_SECONDS;
338c9161 3144 mcp->flags = 0;
7b867cf7 3145 rval = qla2x00_mailbox_command(vha, mcp);
338c9161
AV		 3146
3147 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3148 ql_dbg(ql_dbg_mbx, vha, 0x1008,
3149 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
338c9161 3150 } else {
7c3df132 3151 ql_dbg(ql_dbg_mbx, vha, 0x1007, "Done %s.\n", __func__);
338c9161
AV		 3152 }
3153
3154 return rval;
3155}
4d4df193
HK		 3156
3157/* 84XX Support **************************************************************/
3158
3159struct cs84xx_mgmt_cmd {
3160 union {
3161 struct verify_chip_entry_84xx req;
3162 struct verify_chip_rsp_84xx rsp;
3163 } p;
3164};
3165
3166int
7b867cf7 3167qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4d4df193
HK		 3168{
3169 int rval, retry;
3170 struct cs84xx_mgmt_cmd *mn;
3171 dma_addr_t mn_dma;
3172 uint16_t options;
3173 unsigned long flags;
7b867cf7 3174 struct qla_hw_data *ha = vha->hw;
4d4df193 3175
7c3df132 3176 ql_dbg(ql_dbg_mbx, vha, 0x10c8, "Entered %s.\n", __func__);
4d4df193
HK		 3177
3178 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
3179 if (mn == NULL) {
4d4df193
HK		 3180 return QLA_MEMORY_ALLOC_FAILED;
3181 }
3182
3183 /* Force Update? */
3184 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
3185 /* Diagnostic firmware? */
3186 /* options |= MENLO_DIAG_FW; */
3187 /* We update the firmware with only one data sequence. */
3188 options |= VCO_END_OF_DATA;
3189
4d4df193 3190 do {
c1ec1f1b 3191 retry = 0;
4d4df193
HK		 3192 memset(mn, 0, sizeof(*mn));
3193 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
3194 mn->p.req.entry_count = 1;
3195 mn->p.req.options = cpu_to_le16(options);
3196
7c3df132
SK		 3197 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
3198 "Dump of Verify Request.\n");
3199 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
3200 (uint8_t *)mn, sizeof(*mn));
4d4df193 3201
7b867cf7 3202 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4d4df193 3203 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3204 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
3205 "Failed to issue verify IOCB (%x).\n", rval);
4d4df193
HK		 3206 goto verify_done;
3207 }
3208
7c3df132
SK		 3209 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
3210 "Dump of Verify Response.\n");
3211 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
3212 (uint8_t *)mn, sizeof(*mn));
4d4df193
HK		 3213
3214 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
3215 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
3216 le16_to_cpu(mn->p.rsp.failure_code) : 0;
7c3df132
SK		 3217 ql_dbg(ql_dbg_mbx, vha, 0x10ce,
3218 "cs=%x fc=%x.\n", status[0], status[1]);
4d4df193
HK		 3219
3220 if (status[0] != CS_COMPLETE) {
3221 rval = QLA_FUNCTION_FAILED;
3222 if (!(options & VCO_DONT_UPDATE_FW)) {
7c3df132
SK		 3223 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
3224 "Firmware update failed. Retrying "
3225 "without update firmware.\n");
4d4df193
HK		 3226 options |= VCO_DONT_UPDATE_FW;
3227 options &= ~VCO_FORCE_UPDATE;
3228 retry = 1;
3229 }
3230 } else {
7c3df132
SK		 3231 ql_dbg(ql_dbg_mbx, vha, 0x10d0,
3232 "Firmware updated to %x.\n",
3233 le32_to_cpu(mn->p.rsp.fw_ver));
4d4df193
HK		 3234
3235 /* NOTE: we only update OP firmware. */
3236 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
3237 ha->cs84xx->op_fw_version =
3238 le32_to_cpu(mn->p.rsp.fw_ver);
3239 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
3240 flags);
3241 }
3242 } while (retry);
3243
3244verify_done:
3245 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
3246
3247 if (rval != QLA_SUCCESS) {
7c3df132 3248 ql_dbg(ql_dbg_mbx, vha, 0x10d1, "Failed=%x.\n", rval);
4d4df193 3249 } else {
7c3df132 3250 ql_dbg(ql_dbg_mbx, vha, 0x10d2, "Done %s.\n", __func__);
4d4df193
HK		 3251 }
3252
3253 return rval;
3254}
73208dfd
AC		 3255
3256int
618a7523 3257qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
73208dfd
AC		 3258{
3259 int rval;
3260 unsigned long flags;
3261 mbx_cmd_t mc;
3262 mbx_cmd_t *mcp = &mc;
3263 struct device_reg_25xxmq __iomem *reg;
3264 struct qla_hw_data *ha = vha->hw;
3265
7c3df132
SK		 3266 ql_dbg(ql_dbg_mbx, vha, 0x10d3, "Entered %s.\n", __func__);
3267
73208dfd 3268 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 3269 mcp->mb[1] = req->options;
73208dfd
AC		 3270 mcp->mb[2] = MSW(LSD(req->dma));
3271 mcp->mb[3] = LSW(LSD(req->dma));
3272 mcp->mb[6] = MSW(MSD(req->dma));
3273 mcp->mb[7] = LSW(MSD(req->dma));
3274 mcp->mb[5] = req->length;
3275 if (req->rsp)
3276 mcp->mb[10] = req->rsp->id;
3277 mcp->mb[12] = req->qos;
3278 mcp->mb[11] = req->vp_idx;
3279 mcp->mb[13] = req->rid;
3280
3281 reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
3282 QLA_QUE_PAGE * req->id);
3283
3284 mcp->mb[4] = req->id;
3285 /* que in ptr index */
3286 mcp->mb[8] = 0;
3287 /* que out ptr index */
3288 mcp->mb[9] = 0;
3289 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
3290 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3291 mcp->in_mb = MBX_0;
3292 mcp->flags = MBX_DMA_OUT;
3293 mcp->tov = 60;
3294
3295 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 3296 if (!(req->options & BIT_0)) {
73208dfd
AC		 3297 WRT_REG_DWORD(&reg->req_q_in, 0);
3298 WRT_REG_DWORD(&reg->req_q_out, 0);
3299 }
2afa19a9
AC		 3300 req->req_q_in = &reg->req_q_in;
3301 req->req_q_out = &reg->req_q_out;
73208dfd
AC		 3302 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3303
17d98630 3304 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 3305 if (rval != QLA_SUCCESS) {
3306 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
3307 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3308 } else {
3309 ql_dbg(ql_dbg_mbx, vha, 0x10d5, "Done %s.\n", __func__);
3310 }
3311
73208dfd
AC		 3312 return rval;
3313}
3314
3315int
618a7523 3316qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
73208dfd
AC		 3317{
3318 int rval;
3319 unsigned long flags;
3320 mbx_cmd_t mc;
3321 mbx_cmd_t *mcp = &mc;
3322 struct device_reg_25xxmq __iomem *reg;
3323 struct qla_hw_data *ha = vha->hw;
3324
7c3df132
SK		 3325 ql_dbg(ql_dbg_mbx, vha, 0x10d6, "Entered %s.\n", __func__);
3326
73208dfd 3327 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 3328 mcp->mb[1] = rsp->options;
73208dfd
AC		 3329 mcp->mb[2] = MSW(LSD(rsp->dma));
3330 mcp->mb[3] = LSW(LSD(rsp->dma));
3331 mcp->mb[6] = MSW(MSD(rsp->dma));
3332 mcp->mb[7] = LSW(MSD(rsp->dma));
3333 mcp->mb[5] = rsp->length;
444786d7 3334 mcp->mb[14] = rsp->msix->entry;
73208dfd
AC		 3335 mcp->mb[13] = rsp->rid;
3336
3337 reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
3338 QLA_QUE_PAGE * rsp->id);
3339
3340 mcp->mb[4] = rsp->id;
3341 /* que in ptr index */
3342 mcp->mb[8] = 0;
3343 /* que out ptr index */
3344 mcp->mb[9] = 0;
2afa19a9 3345 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
73208dfd
AC		 3346 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3347 mcp->in_mb = MBX_0;
3348 mcp->flags = MBX_DMA_OUT;
3349 mcp->tov = 60;
3350
3351 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 3352 if (!(rsp->options & BIT_0)) {
73208dfd
AC		 3353 WRT_REG_DWORD(&reg->rsp_q_out, 0);
3354 WRT_REG_DWORD(&reg->rsp_q_in, 0);
3355 }
3356
3357 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3358
17d98630 3359 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 3360 if (rval != QLA_SUCCESS) {
3361 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
3362 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3363 } else {
3364 ql_dbg(ql_dbg_mbx, vha, 0x10d8, "Done %s.\n", __func__);
3365 }
3366
73208dfd
AC		 3367 return rval;
3368}
3369
8a659571
AV		 3370int
3371qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
3372{
3373 int rval;
3374 mbx_cmd_t mc;
3375 mbx_cmd_t *mcp = &mc;
3376
7c3df132 3377 ql_dbg(ql_dbg_mbx, vha, 0x10d9, "Entered %s.\n", __func__);
8a659571
AV		 3378
3379 mcp->mb[0] = MBC_IDC_ACK;
3380 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3381 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3382 mcp->in_mb = MBX_0;
3383 mcp->tov = MBX_TOV_SECONDS;
3384 mcp->flags = 0;
3385 rval = qla2x00_mailbox_command(vha, mcp);
3386
3387 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3388 ql_dbg(ql_dbg_mbx, vha, 0x10da,
3389 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
8a659571 3390 } else {
7c3df132 3391 ql_dbg(ql_dbg_mbx, vha, 0x10db, "Done %s.\n", __func__);
8a659571
AV		 3392 }
3393
3394 return rval;
3395}
1d2874de
JC		 3396
3397int
3398qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
3399{
3400 int rval;
3401 mbx_cmd_t mc;
3402 mbx_cmd_t *mcp = &mc;
3403
7c3df132
SK		 3404 ql_dbg(ql_dbg_mbx, vha, 0x10dc, "Entered %s.\n", __func__);
3405
1d2874de
JC		 3406 if (!IS_QLA81XX(vha->hw))
3407 return QLA_FUNCTION_FAILED;
3408
1d2874de
JC		 3409 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3410 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
3411 mcp->out_mb = MBX_1|MBX_0;
3412 mcp->in_mb = MBX_1|MBX_0;
3413 mcp->tov = MBX_TOV_SECONDS;
3414 mcp->flags = 0;
3415 rval = qla2x00_mailbox_command(vha, mcp);
3416
3417 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3418 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
3419 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3420 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 3421 } else {
7c3df132 3422 ql_dbg(ql_dbg_mbx, vha, 0x10de, "Done %s.\n", __func__);
1d2874de
JC		 3423 *sector_size = mcp->mb[1];
3424 }
3425
3426 return rval;
3427}
3428
3429int
3430qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
3431{
3432 int rval;
3433 mbx_cmd_t mc;
3434 mbx_cmd_t *mcp = &mc;
3435
3436 if (!IS_QLA81XX(vha->hw))
3437 return QLA_FUNCTION_FAILED;
3438
7c3df132 3439 ql_dbg(ql_dbg_mbx, vha, 0x10df, "Entered %s.\n", __func__);
1d2874de
JC		 3440
3441 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3442 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
3443 FAC_OPT_CMD_WRITE_PROTECT;
3444 mcp->out_mb = MBX_1|MBX_0;
3445 mcp->in_mb = MBX_1|MBX_0;
3446 mcp->tov = MBX_TOV_SECONDS;
3447 mcp->flags = 0;
3448 rval = qla2x00_mailbox_command(vha, mcp);
3449
3450 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3451 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
3452 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3453 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 3454 } else {
7c3df132 3455 ql_dbg(ql_dbg_mbx, vha, 0x10e1, "Done %s.\n", __func__);
1d2874de
JC		 3456 }
3457
3458 return rval;
3459}
3460
3461int
3462qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
3463{
3464 int rval;
3465 mbx_cmd_t mc;
3466 mbx_cmd_t *mcp = &mc;
3467
3468 if (!IS_QLA81XX(vha->hw))
3469 return QLA_FUNCTION_FAILED;
3470
7c3df132 3471 ql_dbg(ql_dbg_mbx, vha, 0x10e2, "Entered %s.\n", __func__);
1d2874de
JC		 3472
3473 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3474 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
3475 mcp->mb[2] = LSW(start);
3476 mcp->mb[3] = MSW(start);
3477 mcp->mb[4] = LSW(finish);
3478 mcp->mb[5] = MSW(finish);
3479 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3480 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3481 mcp->tov = MBX_TOV_SECONDS;
3482 mcp->flags = 0;
3483 rval = qla2x00_mailbox_command(vha, mcp);
3484
3485 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3486 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
3487 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3488 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1d2874de 3489 } else {
7c3df132 3490 ql_dbg(ql_dbg_mbx, vha, 0x10e4, "Done %s.\n", __func__);
1d2874de
JC		 3491 }
3492
3493 return rval;
3494}
6e181be5
LC		 3495
3496int
3497qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
3498{
3499 int rval = 0;
3500 mbx_cmd_t mc;
3501 mbx_cmd_t *mcp = &mc;
3502
7c3df132 3503 ql_dbg(ql_dbg_mbx, vha, 0x10e5, "Entered %s.\n", __func__);
6e181be5
LC		 3504
3505 mcp->mb[0] = MBC_RESTART_MPI_FW;
3506 mcp->out_mb = MBX_0;
3507 mcp->in_mb = MBX_0|MBX_1;
3508 mcp->tov = MBX_TOV_SECONDS;
3509 mcp->flags = 0;
3510 rval = qla2x00_mailbox_command(vha, mcp);
3511
3512 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3513 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
3514 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3515 rval, mcp->mb[0], mcp->mb[1]);
6e181be5 3516 } else {
7c3df132 3517 ql_dbg(ql_dbg_mbx, vha, 0x10e7, "Done %s.\n", __func__);
6e181be5
LC		 3518 }
3519
3520 return rval;
3521}
ad0ecd61
JC		 3522
3523int
6766df9e
JC		 3524qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
3525 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 3526{
3527 int rval;
3528 mbx_cmd_t mc;
3529 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 3530 struct qla_hw_data *ha = vha->hw;
3531
7c3df132
SK		 3532 ql_dbg(ql_dbg_mbx, vha, 0x10e8, "Entered %s.\n", __func__);
3533
6766df9e
JC		 3534 if (!IS_FWI2_CAPABLE(ha))
3535 return QLA_FUNCTION_FAILED;
ad0ecd61 3536
6766df9e
JC		 3537 if (len == 1)
3538 opt |= BIT_0;
3539
ad0ecd61
JC		 3540 mcp->mb[0] = MBC_READ_SFP;
3541 mcp->mb[1] = dev;
3542 mcp->mb[2] = MSW(sfp_dma);
3543 mcp->mb[3] = LSW(sfp_dma);
3544 mcp->mb[6] = MSW(MSD(sfp_dma));
3545 mcp->mb[7] = LSW(MSD(sfp_dma));
3546 mcp->mb[8] = len;
6766df9e 3547 mcp->mb[9] = off;
ad0ecd61
JC		 3548 mcp->mb[10] = opt;
3549 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1bff6cc8 3550 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 3551 mcp->tov = MBX_TOV_SECONDS;
3552 mcp->flags = 0;
3553 rval = qla2x00_mailbox_command(vha, mcp);
3554
3555 if (opt & BIT_0)
6766df9e 3556 *sfp = mcp->mb[1];
ad0ecd61
JC		 3557
3558 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3559 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
3560 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 3561 } else {
7c3df132 3562 ql_dbg(ql_dbg_mbx, vha, 0x10ea, "Done %s.\n", __func__);
ad0ecd61
JC		 3563 }
3564
3565 return rval;
3566}
3567
3568int
6766df9e
JC		 3569qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
3570 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 3571{
3572 int rval;
3573 mbx_cmd_t mc;
3574 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 3575 struct qla_hw_data *ha = vha->hw;
3576
7c3df132
SK		 3577 ql_dbg(ql_dbg_mbx, vha, 0x10eb, "Entered %s.\n", __func__);
3578
6766df9e
JC		 3579 if (!IS_FWI2_CAPABLE(ha))
3580 return QLA_FUNCTION_FAILED;
ad0ecd61 3581
6766df9e
JC		 3582 if (len == 1)
3583 opt |= BIT_0;
3584
ad0ecd61 3585 if (opt & BIT_0)
6766df9e 3586 len = *sfp;
ad0ecd61
JC		 3587
3588 mcp->mb[0] = MBC_WRITE_SFP;
3589 mcp->mb[1] = dev;
3590 mcp->mb[2] = MSW(sfp_dma);
3591 mcp->mb[3] = LSW(sfp_dma);
3592 mcp->mb[6] = MSW(MSD(sfp_dma));
3593 mcp->mb[7] = LSW(MSD(sfp_dma));
3594 mcp->mb[8] = len;
6766df9e 3595 mcp->mb[9] = off;
ad0ecd61
JC		 3596 mcp->mb[10] = opt;
3597 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6766df9e 3598 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 3599 mcp->tov = MBX_TOV_SECONDS;
3600 mcp->flags = 0;
3601 rval = qla2x00_mailbox_command(vha, mcp);
3602
3603 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3604 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
3605 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 3606 } else {
7c3df132 3607 ql_dbg(ql_dbg_mbx, vha, 0x10ed, "Done %s.\n", __func__);
ad0ecd61
JC		 3608 }
3609
3610 return rval;
3611}
ce0423f4
AV		 3612
3613int
3614qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
3615 uint16_t size_in_bytes, uint16_t *actual_size)
3616{
3617 int rval;
3618 mbx_cmd_t mc;
3619 mbx_cmd_t *mcp = &mc;
3620
7c3df132
SK		 3621 ql_dbg(ql_dbg_mbx, vha, 0x10ee, "Entered %s.\n", __func__);
3622
a9083016 3623 if (!IS_QLA8XXX_TYPE(vha->hw))
ce0423f4
AV		 3624 return QLA_FUNCTION_FAILED;
3625
ce0423f4
AV		 3626 mcp->mb[0] = MBC_GET_XGMAC_STATS;
3627 mcp->mb[2] = MSW(stats_dma);
3628 mcp->mb[3] = LSW(stats_dma);
3629 mcp->mb[6] = MSW(MSD(stats_dma));
3630 mcp->mb[7] = LSW(MSD(stats_dma));
3631 mcp->mb[8] = size_in_bytes >> 2;
3632 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3633 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3634 mcp->tov = MBX_TOV_SECONDS;
3635 mcp->flags = 0;
3636 rval = qla2x00_mailbox_command(vha, mcp);
3637
3638 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3639 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
3640 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3641 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
ce0423f4 3642 } else {
7c3df132
SK		 3643 ql_dbg(ql_dbg_mbx, vha, 0x10f0, "Done %s.\n", __func__);
3644
ce0423f4
AV		 3645
3646 *actual_size = mcp->mb[2] << 2;
3647 }
3648
3649 return rval;
3650}
11bbc1d8
AV		 3651
3652int
3653qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
3654 uint16_t size)
3655{
3656 int rval;
3657 mbx_cmd_t mc;
3658 mbx_cmd_t *mcp = &mc;
3659
7c3df132
SK		 3660 ql_dbg(ql_dbg_mbx, vha, 0x10f1, "Entered %s.\n", __func__);
3661
a9083016 3662 if (!IS_QLA8XXX_TYPE(vha->hw))
11bbc1d8
AV		 3663 return QLA_FUNCTION_FAILED;
3664
11bbc1d8
AV		 3665 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
3666 mcp->mb[1] = 0;
3667 mcp->mb[2] = MSW(tlv_dma);
3668 mcp->mb[3] = LSW(tlv_dma);
3669 mcp->mb[6] = MSW(MSD(tlv_dma));
3670 mcp->mb[7] = LSW(MSD(tlv_dma));
3671 mcp->mb[8] = size;
3672 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
3673 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3674 mcp->tov = MBX_TOV_SECONDS;
3675 mcp->flags = 0;
3676 rval = qla2x00_mailbox_command(vha, mcp);
3677
3678 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3679 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
3680 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3681 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
11bbc1d8 3682 } else {
7c3df132 3683 ql_dbg(ql_dbg_mbx, vha, 0x10f3, "Done %s.\n", __func__);
11bbc1d8
AV		 3684 }
3685
3686 return rval;
3687}
18e7555a
AV		 3688
3689int
3690qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
3691{
3692 int rval;
3693 mbx_cmd_t mc;
3694 mbx_cmd_t *mcp = &mc;
3695
7c3df132
SK		 3696 ql_dbg(ql_dbg_mbx, vha, 0x10f4, "Entered %s.\n", __func__);
3697
18e7555a
AV		 3698 if (!IS_FWI2_CAPABLE(vha->hw))
3699 return QLA_FUNCTION_FAILED;
3700
18e7555a
AV		 3701 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
3702 mcp->mb[1] = LSW(risc_addr);
3703 mcp->mb[8] = MSW(risc_addr);
3704 mcp->out_mb = MBX_8|MBX_1|MBX_0;
3705 mcp->in_mb = MBX_3|MBX_2|MBX_0;
3706 mcp->tov = 30;
3707 mcp->flags = 0;
3708 rval = qla2x00_mailbox_command(vha, mcp);
3709 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3710 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
3711 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 3712 } else {
7c3df132 3713 ql_dbg(ql_dbg_mbx, vha, 0x10f6, "Done %s.\n", __func__);
18e7555a
AV		 3714 *data = mcp->mb[3] << 16 | mcp->mb[2];
3715 }
3716
3717 return rval;
3718}
3719
9a069e19 3720int
a9083016
GM		 3721qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
3722 uint16_t *mresp)
9a069e19
GM		 3723{
3724 int rval;
3725 mbx_cmd_t mc;
3726 mbx_cmd_t *mcp = &mc;
3727 uint32_t iter_cnt = 0x1;
3728
7c3df132 3729 ql_dbg(ql_dbg_mbx, vha, 0x10f7, "Entered %s.\n", __func__);
9a069e19
GM		 3730
3731 memset(mcp->mb, 0 , sizeof(mcp->mb));
3732 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
3733 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
3734
3735 /* transfer count */
3736 mcp->mb[10] = LSW(mreq->transfer_size);
3737 mcp->mb[11] = MSW(mreq->transfer_size);
3738
3739 /* send data address */
3740 mcp->mb[14] = LSW(mreq->send_dma);
3741 mcp->mb[15] = MSW(mreq->send_dma);
3742 mcp->mb[20] = LSW(MSD(mreq->send_dma));
3743 mcp->mb[21] = MSW(MSD(mreq->send_dma));
3744
25985edc 3745 /* receive data address */
9a069e19
GM		 3746 mcp->mb[16] = LSW(mreq->rcv_dma);
3747 mcp->mb[17] = MSW(mreq->rcv_dma);
3748 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
3749 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
3750
3751 /* Iteration count */
3752 mcp->mb[18] = LSW(iter_cnt);
3753 mcp->mb[19] = MSW(iter_cnt);
3754
3755 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
3756 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
a9083016 3757 if (IS_QLA8XXX_TYPE(vha->hw))
9a069e19
GM		 3758 mcp->out_mb |= MBX_2;
3759 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
3760
3761 mcp->buf_size = mreq->transfer_size;
3762 mcp->tov = MBX_TOV_SECONDS;
3763 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
3764
3765 rval = qla2x00_mailbox_command(vha, mcp);
3766
3767 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3768 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
3769 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
3770 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
3771 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
9a069e19 3772 } else {
7c3df132 3773 ql_dbg(ql_dbg_mbx, vha, 0x10f9, "Done %s.\n", __func__);
9a069e19
GM		 3774 }
3775
3776 /* Copy mailbox information */
3777 memcpy( mresp, mcp->mb, 64);
9a069e19
GM		 3778 return rval;
3779}
3780
3781int
a9083016
GM		 3782qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
3783 uint16_t *mresp)
9a069e19
GM		 3784{
3785 int rval;
3786 mbx_cmd_t mc;
3787 mbx_cmd_t *mcp = &mc;
3788 struct qla_hw_data *ha = vha->hw;
3789
7c3df132 3790 ql_dbg(ql_dbg_mbx, vha, 0x10fa, "Entered %s.\n", __func__);
9a069e19
GM		 3791
3792 memset(mcp->mb, 0 , sizeof(mcp->mb));
3793 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
3794 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
a9083016 3795 if (IS_QLA8XXX_TYPE(ha)) {
9a069e19 3796 mcp->mb[1] |= BIT_15;
a9083016
GM		 3797 mcp->mb[2] = vha->fcoe_fcf_idx;
3798 }
9a069e19
GM		 3799 mcp->mb[16] = LSW(mreq->rcv_dma);
3800 mcp->mb[17] = MSW(mreq->rcv_dma);
3801 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
3802 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
3803
3804 mcp->mb[10] = LSW(mreq->transfer_size);
3805
3806 mcp->mb[14] = LSW(mreq->send_dma);
3807 mcp->mb[15] = MSW(mreq->send_dma);
3808 mcp->mb[20] = LSW(MSD(mreq->send_dma));
3809 mcp->mb[21] = MSW(MSD(mreq->send_dma));
3810
3811 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
3812 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
a9083016 3813 if (IS_QLA8XXX_TYPE(ha))
9a069e19
GM		 3814 mcp->out_mb |= MBX_2;
3815
3816 mcp->in_mb = MBX_0;
a9083016 3817 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || IS_QLA8XXX_TYPE(ha))
9a069e19 3818 mcp->in_mb |= MBX_1;
a9083016 3819 if (IS_QLA8XXX_TYPE(ha))
9a069e19
GM		 3820 mcp->in_mb |= MBX_3;
3821
3822 mcp->tov = MBX_TOV_SECONDS;
3823 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
3824 mcp->buf_size = mreq->transfer_size;
3825
3826 rval = qla2x00_mailbox_command(vha, mcp);
3827
3828 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3829 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
3830 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3831 rval, mcp->mb[0], mcp->mb[1]);
9a069e19 3832 } else {
7c3df132 3833 ql_dbg(ql_dbg_mbx, vha, 0x10fc, "Done %s.\n", __func__);
9a069e19
GM		 3834 }
3835
3836 /* Copy mailbox information */
6dbdda4d 3837 memcpy(mresp, mcp->mb, 64);
9a069e19
GM		 3838 return rval;
3839}
6dbdda4d 3840
9a069e19 3841int
7c3df132 3842qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
9a069e19
GM		 3843{
3844 int rval;
3845 mbx_cmd_t mc;
3846 mbx_cmd_t *mcp = &mc;
3847
7c3df132
SK		 3848 ql_dbg(ql_dbg_mbx, vha, 0x10fd,
3849 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
9a069e19
GM		 3850
3851 mcp->mb[0] = MBC_ISP84XX_RESET;
3852 mcp->mb[1] = enable_diagnostic;
3853 mcp->out_mb = MBX_1|MBX_0;
3854 mcp->in_mb = MBX_1|MBX_0;
3855 mcp->tov = MBX_TOV_SECONDS;
3856 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
7c3df132 3857 rval = qla2x00_mailbox_command(vha, mcp);
9a069e19 3858
9a069e19 3859 if (rval != QLA_SUCCESS)
7c3df132 3860 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
9a069e19 3861 else
7c3df132 3862 ql_dbg(ql_dbg_mbx, vha, 0x10ff, "Done %s.\n", __func__);
9a069e19
GM		 3863
3864 return rval;
3865}
3866
18e7555a
AV		 3867int
3868qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
3869{
3870 int rval;
3871 mbx_cmd_t mc;
3872 mbx_cmd_t *mcp = &mc;
3873
7c3df132
SK		 3874 ql_dbg(ql_dbg_mbx, vha, 0x1100, "Entered %s.\n", __func__);
3875
18e7555a 3876 if (!IS_FWI2_CAPABLE(vha->hw))
6c452a45 3877 return QLA_FUNCTION_FAILED;
18e7555a 3878
18e7555a
AV		 3879 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
3880 mcp->mb[1] = LSW(risc_addr);
3881 mcp->mb[2] = LSW(data);
3882 mcp->mb[3] = MSW(data);
3883 mcp->mb[8] = MSW(risc_addr);
3884 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
3885 mcp->in_mb = MBX_0;
3886 mcp->tov = 30;
3887 mcp->flags = 0;
3888 rval = qla2x00_mailbox_command(vha, mcp);
3889 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3890 ql_dbg(ql_dbg_mbx, vha, 0x1101,
3891 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 3892 } else {
7c3df132 3893 ql_dbg(ql_dbg_mbx, vha, 0x1102, "Done %s.\n", __func__);
18e7555a
AV		 3894 }
3895
3896 return rval;
3897}
3064ff39 3898
b1d46989
MI		 3899int
3900qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
3901{
3902 int rval;
3903 uint32_t stat, timer;
3904 uint16_t mb0 = 0;
3905 struct qla_hw_data *ha = vha->hw;
3906 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
3907
3908 rval = QLA_SUCCESS;
3909
7c3df132 3910 ql_dbg(ql_dbg_mbx, vha, 0x1103, "Entered %s.\n", __func__);
b1d46989
MI		 3911
3912 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
3913
3914 /* Write the MBC data to the registers */
3915 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
3916 WRT_REG_WORD(&reg->mailbox1, mb[0]);
3917 WRT_REG_WORD(&reg->mailbox2, mb[1]);
3918 WRT_REG_WORD(&reg->mailbox3, mb[2]);
3919 WRT_REG_WORD(&reg->mailbox4, mb[3]);
3920
3921 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
3922
3923 /* Poll for MBC interrupt */
3924 for (timer = 6000000; timer; timer--) {
3925 /* Check for pending interrupts. */
3926 stat = RD_REG_DWORD(&reg->host_status);
3927 if (stat & HSRX_RISC_INT) {
3928 stat &= 0xff;
3929
3930 if (stat == 0x1 || stat == 0x2 ||
3931 stat == 0x10 || stat == 0x11) {
3932 set_bit(MBX_INTERRUPT,
3933 &ha->mbx_cmd_flags);
3934 mb0 = RD_REG_WORD(&reg->mailbox0);
3935 WRT_REG_DWORD(&reg->hccr,
3936 HCCRX_CLR_RISC_INT);
3937 RD_REG_DWORD(&reg->hccr);
3938 break;
3939 }
3940 }
3941 udelay(5);
3942 }
3943
3944 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
3945 rval = mb0 & MBS_MASK;
3946 else
3947 rval = QLA_FUNCTION_FAILED;
3948
3949 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3950 ql_dbg(ql_dbg_mbx, vha, 0x1104,
3951 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
b1d46989 3952 } else {
7c3df132 3953 ql_dbg(ql_dbg_mbx, vha, 0x1105, "Done %s.\n", __func__);
b1d46989
MI		 3954 }
3955
3956 return rval;
3957}
3064ff39
MH		 3958int
3959qla2x00_get_data_rate(scsi_qla_host_t *vha)
3960{
3961 int rval;
3962 mbx_cmd_t mc;
3963 mbx_cmd_t *mcp = &mc;
3964 struct qla_hw_data *ha = vha->hw;
3965
7c3df132
SK		 3966 ql_dbg(ql_dbg_mbx, vha, 0x1106, "Entered %s.\n", __func__);
3967
3064ff39
MH		 3968 if (!IS_FWI2_CAPABLE(ha))
3969 return QLA_FUNCTION_FAILED;
3970
3064ff39
MH		 3971 mcp->mb[0] = MBC_DATA_RATE;
3972 mcp->mb[1] = 0;
3973 mcp->out_mb = MBX_1|MBX_0;
3974 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3975 mcp->tov = MBX_TOV_SECONDS;
3976 mcp->flags = 0;
3977 rval = qla2x00_mailbox_command(vha, mcp);
3978 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3979 ql_dbg(ql_dbg_mbx, vha, 0x1107,
3980 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3064ff39 3981 } else {
7c3df132 3982 ql_dbg(ql_dbg_mbx, vha, 0x1108, "Done %s.\n", __func__);
3064ff39
MH		 3983 if (mcp->mb[1] != 0x7)
3984 ha->link_data_rate = mcp->mb[1];
3985 }
3986
3987 return rval;
3988}
09ff701a 3989
23f2ebd1
SR		 3990int
3991qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
3992{
3993 int rval;
3994 mbx_cmd_t mc;
3995 mbx_cmd_t *mcp = &mc;
3996 struct qla_hw_data *ha = vha->hw;
3997
7c3df132 3998 ql_dbg(ql_dbg_mbx, vha, 0x1109, "Entered %s.\n", __func__);
23f2ebd1
SR		 3999
4000 if (!IS_QLA81XX(ha))
4001 return QLA_FUNCTION_FAILED;
4002 mcp->mb[0] = MBC_GET_PORT_CONFIG;
4003 mcp->out_mb = MBX_0;
4004 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4005 mcp->tov = MBX_TOV_SECONDS;
4006 mcp->flags = 0;
4007
4008 rval = qla2x00_mailbox_command(vha, mcp);
4009
4010 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4011 ql_dbg(ql_dbg_mbx, vha, 0x110a,
4012 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1
SR		 4013 } else {
4014 /* Copy all bits to preserve original value */
4015 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
4016
7c3df132 4017 ql_dbg(ql_dbg_mbx, vha, 0x110b, "Done %s.\n", __func__);
23f2ebd1
SR		 4018 }
4019 return rval;
4020}
4021
4022int
4023qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4024{
4025 int rval;
4026 mbx_cmd_t mc;
4027 mbx_cmd_t *mcp = &mc;
4028
7c3df132 4029 ql_dbg(ql_dbg_mbx, vha, 0x110c, "Entered %s.\n", __func__);
23f2ebd1
SR		 4030
4031 mcp->mb[0] = MBC_SET_PORT_CONFIG;
4032 /* Copy all bits to preserve original setting */
4033 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
4034 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4035 mcp->in_mb = MBX_0;
4036 mcp->tov = MBX_TOV_SECONDS;
4037 mcp->flags = 0;
4038 rval = qla2x00_mailbox_command(vha, mcp);
4039
4040 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4041 ql_dbg(ql_dbg_mbx, vha, 0x110d,
4042 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1 4043 } else
7c3df132 4044 ql_dbg(ql_dbg_mbx, vha, 0x110e, "Done %s.\n", __func__);
23f2ebd1
SR		 4045
4046 return rval;
4047}
4048
4049
09ff701a
SR		 4050int
4051qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
4052 uint16_t *mb)
4053{
4054 int rval;
4055 mbx_cmd_t mc;
4056 mbx_cmd_t *mcp = &mc;
4057 struct qla_hw_data *ha = vha->hw;
4058
7c3df132
SK		 4059 ql_dbg(ql_dbg_mbx, vha, 0x110f, "Entered %s.\n", __func__);
4060
09ff701a
SR		 4061 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
4062 return QLA_FUNCTION_FAILED;
4063
09ff701a
SR		 4064 mcp->mb[0] = MBC_PORT_PARAMS;
4065 mcp->mb[1] = loop_id;
4066 if (ha->flags.fcp_prio_enabled)
4067 mcp->mb[2] = BIT_1;
4068 else
4069 mcp->mb[2] = BIT_2;
4070 mcp->mb[4] = priority & 0xf;
4071 mcp->mb[9] = vha->vp_idx;
4072 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4073 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
4074 mcp->tov = 30;
4075 mcp->flags = 0;
4076 rval = qla2x00_mailbox_command(vha, mcp);
4077 if (mb != NULL) {
4078 mb[0] = mcp->mb[0];
4079 mb[1] = mcp->mb[1];
4080 mb[3] = mcp->mb[3];
4081 mb[4] = mcp->mb[4];
4082 }
4083
4084 if (rval != QLA_SUCCESS) {
7c3df132 4085 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
09ff701a 4086 } else {
7c3df132 4087 ql_dbg(ql_dbg_mbx, vha, 0x10cc, "Done %s.\n", __func__);
09ff701a
SR		 4088 }
4089
4090 return rval;
4091}
a9083016 4092
794a5691
AV		 4093int
4094qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp, uint16_t *frac)
4095{
4096 int rval;
6ad11eaa 4097 uint8_t byte;
794a5691
AV		 4098 struct qla_hw_data *ha = vha->hw;
4099
7c3df132 4100 ql_dbg(ql_dbg_mbx, vha, 0x10ca, "Entered %s.\n", __func__);
794a5691 4101
6ad11eaa
JC		 4102 /* Integer part */
4103 rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x01, 1, BIT_13|BIT_0);
794a5691 4104 if (rval != QLA_SUCCESS) {
7c3df132 4105 ql_dbg(ql_dbg_mbx, vha, 0x10c9, "Failed=%x.\n", rval);
794a5691
AV		 4106 ha->flags.thermal_supported = 0;
4107 goto fail;
4108 }
6ad11eaa 4109 *temp = byte;
794a5691 4110
6ad11eaa
JC		 4111 /* Fraction part */
4112 rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x10, 1, BIT_13|BIT_0);
794a5691 4113 if (rval != QLA_SUCCESS) {
7c3df132 4114 ql_dbg(ql_dbg_mbx, vha, 0x1019, "Failed=%x.\n", rval);
794a5691
AV		 4115 ha->flags.thermal_supported = 0;
4116 goto fail;
4117 }
6ad11eaa 4118 *frac = (byte >> 6) * 25;
794a5691 4119
7c3df132 4120 ql_dbg(ql_dbg_mbx, vha, 0x1018, "Done %s.\n", __func__);
794a5691
AV		 4121fail:
4122 return rval;
4123}
4124
a9083016
GM		 4125int
4126qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
4127{
4128 int rval;
4129 struct qla_hw_data *ha = vha->hw;
4130 mbx_cmd_t mc;
4131 mbx_cmd_t *mcp = &mc;
4132
7c3df132
SK		 4133 ql_dbg(ql_dbg_mbx, vha, 0x1017, "Entered %s.\n", __func__);
4134
a9083016
GM		 4135 if (!IS_FWI2_CAPABLE(ha))
4136 return QLA_FUNCTION_FAILED;
4137
a9083016 4138 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 4139 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 4140 mcp->mb[1] = 1;
4141
4142 mcp->out_mb = MBX_1|MBX_0;
4143 mcp->in_mb = MBX_0;
4144 mcp->tov = 30;
4145 mcp->flags = 0;
4146
4147 rval = qla2x00_mailbox_command(vha, mcp);
4148 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4149 ql_dbg(ql_dbg_mbx, vha, 0x1016,
4150 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 4151 } else {
7c3df132 4152 ql_dbg(ql_dbg_mbx, vha, 0x100e, "Done %s.\n", __func__);
a9083016
GM		 4153 }
4154
4155 return rval;
4156}
4157
4158int
4159qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
4160{
4161 int rval;
4162 struct qla_hw_data *ha = vha->hw;
4163 mbx_cmd_t mc;
4164 mbx_cmd_t *mcp = &mc;
4165
7c3df132
SK		 4166 ql_dbg(ql_dbg_mbx, vha, 0x100d, "Entered %s.\n", __func__);
4167
a9083016
GM		 4168 if (!IS_QLA82XX(ha))
4169 return QLA_FUNCTION_FAILED;
4170
a9083016 4171 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 4172 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 4173 mcp->mb[1] = 0;
4174
4175 mcp->out_mb = MBX_1|MBX_0;
4176 mcp->in_mb = MBX_0;
4177 mcp->tov = 30;
4178 mcp->flags = 0;
4179
4180 rval = qla2x00_mailbox_command(vha, mcp);
4181 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4182 ql_dbg(ql_dbg_mbx, vha, 0x100c,
4183 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 4184 } else {
7c3df132 4185 ql_dbg(ql_dbg_mbx, vha, 0x100b, "Done %s.\n", __func__);
a9083016
GM		 4186 }
4187
4188 return rval;
4189}
08de2844
GM		 4190
4191int
4192qla82xx_md_get_template_size(scsi_qla_host_t *vha)
4193{
4194 struct qla_hw_data *ha = vha->hw;
4195 mbx_cmd_t mc;
4196 mbx_cmd_t *mcp = &mc;
4197 int rval = QLA_FUNCTION_FAILED;
4198
4199 ql_dbg(ql_dbg_mbx, vha, 0x111f, "Entered %s.\n", __func__);
4200
4201 memset(mcp->mb, 0 , sizeof(mcp->mb));
4202 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4203 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4204 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
4205 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
4206
4207 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4208 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
4209 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4210
4211 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4212 mcp->tov = MBX_TOV_SECONDS;
4213 rval = qla2x00_mailbox_command(vha, mcp);
4214
4215 /* Always copy back return mailbox values. */
4216 if (rval != QLA_SUCCESS) {
4217 ql_dbg(ql_dbg_mbx, vha, 0x1120,
4218 "mailbox command FAILED=0x%x, subcode=%x.\n",
4219 (mcp->mb[1] << 16) | mcp->mb[0],
4220 (mcp->mb[3] << 16) | mcp->mb[2]);
4221 } else {
4222 ql_dbg(ql_dbg_mbx, vha, 0x1121, "Done %s.\n", __func__);
4223 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
4224 if (!ha->md_template_size) {
4225 ql_dbg(ql_dbg_mbx, vha, 0x1122,
4226 "Null template size obtained.\n");
4227 rval = QLA_FUNCTION_FAILED;
4228 }
4229 }
4230 return rval;
4231}
4232
4233int
4234qla82xx_md_get_template(scsi_qla_host_t *vha)
4235{
4236 struct qla_hw_data *ha = vha->hw;
4237 mbx_cmd_t mc;
4238 mbx_cmd_t *mcp = &mc;
4239 int rval = QLA_FUNCTION_FAILED;
4240
4241 ql_dbg(ql_dbg_mbx, vha, 0x1123, "Entered %s.\n", __func__);
4242
4243 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
4244 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
4245 if (!ha->md_tmplt_hdr) {
4246 ql_log(ql_log_warn, vha, 0x1124,
4247 "Unable to allocate memory for Minidump template.\n");
4248 return rval;
4249 }
4250
4251 memset(mcp->mb, 0 , sizeof(mcp->mb));
4252 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4253 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4254 mcp->mb[2] = LSW(RQST_TMPLT);
4255 mcp->mb[3] = MSW(RQST_TMPLT);
4256 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
4257 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
4258 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
4259 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
4260 mcp->mb[8] = LSW(ha->md_template_size);
4261 mcp->mb[9] = MSW(ha->md_template_size);
4262
4263 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4264 mcp->tov = MBX_TOV_SECONDS;
4265 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
4266 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4267 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4268 rval = qla2x00_mailbox_command(vha, mcp);
4269
4270 if (rval != QLA_SUCCESS) {
4271 ql_dbg(ql_dbg_mbx, vha, 0x1125,
4272 "mailbox command FAILED=0x%x, subcode=%x.\n",
4273 ((mcp->mb[1] << 16) | mcp->mb[0]),
4274 ((mcp->mb[3] << 16) | mcp->mb[2]));
4275 } else
4276 ql_dbg(ql_dbg_mbx, vha, 0x1126, "Done %s.\n", __func__);
4277 return rval;
4278}
999916dc
SK		 4279
4280int
4281qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
4282{
4283 int rval;
4284 struct qla_hw_data *ha = vha->hw;
4285 mbx_cmd_t mc;
4286 mbx_cmd_t *mcp = &mc;
4287
4288 if (!IS_QLA82XX(ha))
4289 return QLA_FUNCTION_FAILED;
4290
4291 ql_dbg(ql_dbg_mbx, vha, 0x1127,
4292 "Entered %s.\n", __func__);
4293
4294 memset(mcp, 0, sizeof(mbx_cmd_t));
4295 mcp->mb[0] = MBC_SET_LED_CONFIG;
4296 if (enable)
4297 mcp->mb[7] = 0xE;
4298 else
4299 mcp->mb[7] = 0xD;
4300
4301 mcp->out_mb = MBX_7|MBX_0;
4302 mcp->in_mb = MBX_0;
4303 mcp->tov = 30;
4304 mcp->flags = 0;
4305
4306 rval = qla2x00_mailbox_command(vha, mcp);
4307 if (rval != QLA_SUCCESS) {
4308 ql_dbg(ql_dbg_mbx, vha, 0x1128,
4309 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4310 } else {
4311 ql_dbg(ql_dbg_mbx, vha, 0x1129,
4312 "Done %s.\n", __func__);
4313 }
4314
4315 return rval;
4316}
Linux 6.x block layer and io_uring tree(s)