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scsi: qla2xxx: Update driver version to 9.01.00.00-k
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_mbx.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
2d70c103 8#include "qla_target.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/gfp.h>
1da177e4 12
15f30a57
QT		 13static struct mb_cmd_name {
14 uint16_t cmd;
15 const char *str;
16} mb_str[] = {
17 {MBC_GET_PORT_DATABASE, "GPDB"},
18 {MBC_GET_ID_LIST, "GIDList"},
19 {MBC_GET_LINK_PRIV_STATS, "Stats"},
20};
21
22static const char *mb_to_str(uint16_t cmd)
23{
24 int i;
25 struct mb_cmd_name *e;
26
27 for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
28 e = mb_str + i;
29 if (cmd == e->cmd)
30 return e->str;
31 }
32 return "unknown";
33}
34
ca825828 35static struct rom_cmd {
77ddb94a 36 uint16_t cmd;
37} rom_cmds[] = {
38 { MBC_LOAD_RAM },
39 { MBC_EXECUTE_FIRMWARE },
40 { MBC_READ_RAM_WORD },
41 { MBC_MAILBOX_REGISTER_TEST },
42 { MBC_VERIFY_CHECKSUM },
43 { MBC_GET_FIRMWARE_VERSION },
44 { MBC_LOAD_RISC_RAM },
45 { MBC_DUMP_RISC_RAM },
46 { MBC_LOAD_RISC_RAM_EXTENDED },
47 { MBC_DUMP_RISC_RAM_EXTENDED },
48 { MBC_WRITE_RAM_WORD_EXTENDED },
49 { MBC_READ_RAM_EXTENDED },
50 { MBC_GET_RESOURCE_COUNTS },
51 { MBC_SET_FIRMWARE_OPTION },
52 { MBC_MID_INITIALIZE_FIRMWARE },
53 { MBC_GET_FIRMWARE_STATE },
54 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
55 { MBC_GET_RETRY_COUNT },
56 { MBC_TRACE_CONTROL },
57};
58
59static int is_rom_cmd(uint16_t cmd)
60{
61 int i;
62 struct rom_cmd *wc;
63
64 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
65 wc = rom_cmds + i;
66 if (wc->cmd == cmd)
67 return 1;
68 }
69
70 return 0;
71}
1da177e4
LT		 72
73/*
74 * qla2x00_mailbox_command
75 * Issue mailbox command and waits for completion.
76 *
77 * Input:
78 * ha = adapter block pointer.
79 * mcp = driver internal mbx struct pointer.
80 *
81 * Output:
82 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
83 *
84 * Returns:
85 * 0 : QLA_SUCCESS = cmd performed success
86 * 1 : QLA_FUNCTION_FAILED (error encountered)
87 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
88 *
89 * Context:
90 * Kernel context.
91 */
92static int
7b867cf7 93qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
1da177e4 94{
d14e72fb 95 int rval, i;
1da177e4 96 unsigned long flags = 0;
f73cb695 97 device_reg_t *reg;
1c7c6357 98 uint8_t abort_active;
2c3dfe3f 99 uint8_t io_lock_on;
cdbb0a4f 100 uint16_t command = 0;
1da177e4
LT		 101 uint16_t *iptr;
102 uint16_t __iomem *optr;
103 uint32_t cnt;
104 uint32_t mboxes;
d14e72fb 105 uint16_t __iomem *mbx_reg;
1da177e4 106 unsigned long wait_time;
7b867cf7
AC		 107 struct qla_hw_data *ha = vha->hw;
108 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 109
d14e72fb 110
5e19ed90 111 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
7c3df132
SK		 112
113 if (ha->pdev->error_state > pci_channel_io_frozen) {
5e19ed90 114 ql_log(ql_log_warn, vha, 0x1001,
7c3df132
SK		 115 "error_state is greater than pci_channel_io_frozen, "
116 "exiting.\n");
b9b12f73 117 return QLA_FUNCTION_TIMEOUT;
7c3df132 118 }
b9b12f73 119
a9083016 120 if (vha->device_flags & DFLG_DEV_FAILED) {
5e19ed90 121 ql_log(ql_log_warn, vha, 0x1002,
7c3df132 122 "Device in failed state, exiting.\n");
a9083016
GM		 123 return QLA_FUNCTION_TIMEOUT;
124 }
125
c2a5d94f 126 /* if PCI error, then avoid mbx processing.*/
ba175891
SC		 127 if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) &&
128 test_bit(UNLOADING, &base_vha->dpc_flags)) {
83548fe2 129 ql_log(ql_log_warn, vha, 0xd04e,
783e0dc4
SC		 130 "PCI error, exiting.\n");
131 return QLA_FUNCTION_TIMEOUT;
c2a5d94f 132 }
783e0dc4 133
2c3dfe3f 134 reg = ha->iobase;
7b867cf7 135 io_lock_on = base_vha->flags.init_done;
1da177e4
LT		 136
137 rval = QLA_SUCCESS;
7b867cf7 138 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1c7c6357 139
1da177e4 140
85880801 141 if (ha->flags.pci_channel_io_perm_failure) {
5e19ed90 142 ql_log(ql_log_warn, vha, 0x1003,
7c3df132 143 "Perm failure on EEH timeout MBX, exiting.\n");
85880801
AV		 144 return QLA_FUNCTION_TIMEOUT;
145 }
146
7ec0effd 147 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
862cd01e
GM		 148 /* Setting Link-Down error */
149 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
5e19ed90 150 ql_log(ql_log_warn, vha, 0x1004,
7c3df132 151 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
1806fcd5 152 return QLA_FUNCTION_TIMEOUT;
862cd01e
GM		 153 }
154
77ddb94a 155 /* check if ISP abort is active and return cmd with timeout */
156 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
157 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
158 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
159 !is_rom_cmd(mcp->mb[0])) {
160 ql_log(ql_log_info, vha, 0x1005,
161 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
162 mcp->mb[0]);
163 return QLA_FUNCTION_TIMEOUT;
164 }
165
1da177e4 166 /*
1c7c6357
AV		 167 * Wait for active mailbox commands to finish by waiting at most tov
168 * seconds. This is to serialize actual issuing of mailbox cmds during
169 * non ISP abort time.
1da177e4 170 */
8eca3f39
AV		 171 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
172 /* Timeout occurred. Return error. */
83548fe2 173 ql_log(ql_log_warn, vha, 0xd035,
d8c0d546
CD		 174 "Cmd access timeout, cmd=0x%x, Exiting.\n",
175 mcp->mb[0]);
8eca3f39 176 return QLA_FUNCTION_TIMEOUT;
1da177e4
LT		 177 }
178
179 ha->flags.mbox_busy = 1;
180 /* Save mailbox command for debug */
181 ha->mcp = mcp;
182
5e19ed90 183 ql_dbg(ql_dbg_mbx, vha, 0x1006,
7c3df132 184 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
1da177e4
LT		 185
186 spin_lock_irqsave(&ha->hardware_lock, flags);
187
188 /* Load mailbox registers. */
7ec0effd 189 if (IS_P3P_TYPE(ha))
a9083016 190 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
7ec0effd 191 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
1c7c6357
AV		 192 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
193 else
194 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
1da177e4
LT		 195
196 iptr = mcp->mb;
197 command = mcp->mb[0];
198 mboxes = mcp->out_mb;
199
7b711623 200 ql_dbg(ql_dbg_mbx, vha, 0x1111,
0e31a2c8 201 "Mailbox registers (OUT):\n");
1da177e4
LT		 202 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
203 if (IS_QLA2200(ha) && cnt == 8)
1c7c6357
AV		 204 optr =
205 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
0e31a2c8
JC		 206 if (mboxes & BIT_0) {
207 ql_dbg(ql_dbg_mbx, vha, 0x1112,
208 "mbox[%d]<-0x%04x\n", cnt, *iptr);
1da177e4 209 WRT_REG_WORD(optr, *iptr);
0e31a2c8 210 }
1da177e4
LT		 211
212 mboxes >>= 1;
213 optr++;
214 iptr++;
215 }
216
5e19ed90 217 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
7c3df132 218 "I/O Address = %p.\n", optr);
1da177e4
LT		 219
220 /* Issue set host interrupt command to send cmd out. */
221 ha->flags.mbox_int = 0;
222 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
223
224 /* Unlock mbx registers and wait for interrupt */
5e19ed90 225 ql_dbg(ql_dbg_mbx, vha, 0x100f,
7c3df132
SK		 226 "Going to unlock irq & waiting for interrupts. "
227 "jiffies=%lx.\n", jiffies);
1da177e4
LT		 228
229 /* Wait for mbx cmd completion until timeout */
230
124f85e6 231 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
1da177e4
LT		 232 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
233
7ec0effd 234 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 235 if (RD_REG_DWORD(&reg->isp82.hint) &
236 HINT_MBX_INT_PENDING) {
237 spin_unlock_irqrestore(&ha->hardware_lock,
238 flags);
8937f2f1 239 ha->flags.mbox_busy = 0;
5e19ed90 240 ql_dbg(ql_dbg_mbx, vha, 0x1010,
7c3df132 241 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 242 rval = QLA_FUNCTION_TIMEOUT;
243 goto premature_exit;
a9083016
GM		 244 }
245 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
246 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 247 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
248 else
249 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4
LT		 250 spin_unlock_irqrestore(&ha->hardware_lock, flags);
251
77ddb94a 252 wait_time = jiffies;
754d1243
GM		 253 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
254 mcp->tov * HZ)) {
255 ql_dbg(ql_dbg_mbx, vha, 0x117a,
256 "cmd=%x Timeout.\n", command);
257 spin_lock_irqsave(&ha->hardware_lock, flags);
258 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
259 spin_unlock_irqrestore(&ha->hardware_lock, flags);
260 }
77ddb94a 261 if (time_after(jiffies, wait_time + 5 * HZ))
262 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
263 command, jiffies_to_msecs(jiffies - wait_time));
1da177e4 264 } else {
5e19ed90 265 ql_dbg(ql_dbg_mbx, vha, 0x1011,
7c3df132 266 "Cmd=%x Polling Mode.\n", command);
1da177e4 267
7ec0effd 268 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 269 if (RD_REG_DWORD(&reg->isp82.hint) &
270 HINT_MBX_INT_PENDING) {
271 spin_unlock_irqrestore(&ha->hardware_lock,
272 flags);
8937f2f1 273 ha->flags.mbox_busy = 0;
5e19ed90 274 ql_dbg(ql_dbg_mbx, vha, 0x1012,
7c3df132 275 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 276 rval = QLA_FUNCTION_TIMEOUT;
277 goto premature_exit;
a9083016
GM		 278 }
279 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
280 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 281 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
282 else
283 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4 284 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 285
286 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
287 while (!ha->flags.mbox_int) {
288 if (time_after(jiffies, wait_time))
289 break;
290
291 /* Check for pending interrupts. */
73208dfd 292 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4 293
85880801
AV		 294 if (!ha->flags.mbox_int &&
295 !(IS_QLA2200(ha) &&
296 command == MBC_LOAD_RISC_RAM_EXTENDED))
59989831 297 msleep(10);
1da177e4 298 } /* while */
5e19ed90 299 ql_dbg(ql_dbg_mbx, vha, 0x1013,
7c3df132
SK		 300 "Waited %d sec.\n",
301 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
1da177e4
LT		 302 }
303
1da177e4
LT		 304 /* Check whether we timed out */
305 if (ha->flags.mbox_int) {
306 uint16_t *iptr2;
307
5e19ed90 308 ql_dbg(ql_dbg_mbx, vha, 0x1014,
7c3df132 309 "Cmd=%x completed.\n", command);
1da177e4
LT		 310
311 /* Got interrupt. Clear the flag. */
312 ha->flags.mbox_int = 0;
313 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
314
7ec0effd 315 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
cdbb0a4f
SV		 316 ha->flags.mbox_busy = 0;
317 /* Setting Link-Down error */
318 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
319 ha->mcp = NULL;
320 rval = QLA_FUNCTION_FAILED;
83548fe2 321 ql_log(ql_log_warn, vha, 0xd048,
7c3df132 322 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
cdbb0a4f
SV		 323 goto premature_exit;
324 }
325
354d6b21 326 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
1da177e4 327 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 328
329 /* Load return mailbox registers. */
330 iptr2 = mcp->mb;
331 iptr = (uint16_t *)&ha->mailbox_out[0];
332 mboxes = mcp->in_mb;
0e31a2c8
JC		 333
334 ql_dbg(ql_dbg_mbx, vha, 0x1113,
335 "Mailbox registers (IN):\n");
1da177e4 336 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
0e31a2c8 337 if (mboxes & BIT_0) {
1da177e4 338 *iptr2 = *iptr;
0e31a2c8
JC		 339 ql_dbg(ql_dbg_mbx, vha, 0x1114,
340 "mbox[%d]->0x%04x\n", cnt, *iptr2);
341 }
1da177e4
LT		 342
343 mboxes >>= 1;
344 iptr2++;
345 iptr++;
346 }
347 } else {
348
8d3c9c23
QT		 349 uint16_t mb[8];
350 uint32_t ictrl, host_status, hccr;
783e0dc4 351 uint16_t w;
1c7c6357 352
e428924c 353 if (IS_FWI2_CAPABLE(ha)) {
8d3c9c23
QT		 354 mb[0] = RD_REG_WORD(&reg->isp24.mailbox0);
355 mb[1] = RD_REG_WORD(&reg->isp24.mailbox1);
356 mb[2] = RD_REG_WORD(&reg->isp24.mailbox2);
357 mb[3] = RD_REG_WORD(&reg->isp24.mailbox3);
358 mb[7] = RD_REG_WORD(&reg->isp24.mailbox7);
1c7c6357 359 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
8d3c9c23
QT		 360 host_status = RD_REG_DWORD(&reg->isp24.host_status);
361 hccr = RD_REG_DWORD(&reg->isp24.hccr);
362
83548fe2 363 ql_log(ql_log_warn, vha, 0xd04c,
8d3c9c23
QT		 364 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
365 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
366 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
367 mb[7], host_status, hccr);
368
1c7c6357 369 } else {
8d3c9c23 370 mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
1c7c6357 371 ictrl = RD_REG_WORD(&reg->isp.ictrl);
8d3c9c23
QT		 372 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
373 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
374 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
1c7c6357 375 }
5e19ed90 376 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
1da177e4 377
783e0dc4
SC		 378 /* Capture FW dump only, if PCI device active */
379 if (!pci_channel_offline(vha->hw->pdev)) {
380 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
381 if (w == 0xffff || ictrl == 0xffffffff) {
382 /* This is special case if there is unload
383 * of driver happening and if PCI device go
384 * into bad state due to PCI error condition
385 * then only PCI ERR flag would be set.
386 * we will do premature exit for above case.
387 */
783e0dc4
SC		 388 ha->flags.mbox_busy = 0;
389 rval = QLA_FUNCTION_TIMEOUT;
390 goto premature_exit;
391 }
f55bfc88 392
783e0dc4
SC		 393 /* Attempt to capture firmware dump for further
394 * anallysis of the current formware state. we do not
395 * need to do this if we are intentionally generating
396 * a dump
397 */
398 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
399 ha->isp_ops->fw_dump(vha, 0);
400 rval = QLA_FUNCTION_TIMEOUT;
401 }
1da177e4
LT		 402 }
403
1da177e4
LT		 404 ha->flags.mbox_busy = 0;
405
406 /* Clean up */
407 ha->mcp = NULL;
408
124f85e6 409 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
5e19ed90 410 ql_dbg(ql_dbg_mbx, vha, 0x101a,
7c3df132 411 "Checking for additional resp interrupt.\n");
1da177e4
LT		 412
413 /* polling mode for non isp_abort commands. */
73208dfd 414 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4
LT		 415 }
416
1c7c6357
AV		 417 if (rval == QLA_FUNCTION_TIMEOUT &&
418 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
85880801
AV		 419 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
420 ha->flags.eeh_busy) {
1da177e4 421 /* not in dpc. schedule it for dpc to take over. */
5e19ed90 422 ql_dbg(ql_dbg_mbx, vha, 0x101b,
7c3df132 423 "Timeout, schedule isp_abort_needed.\n");
cdbb0a4f
SV		 424
425 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
426 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
427 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 428 if (IS_QLA82XX(ha)) {
429 ql_dbg(ql_dbg_mbx, vha, 0x112a,
430 "disabling pause transmit on port "
431 "0 & 1.\n");
432 qla82xx_wr_32(ha,
433 QLA82XX_CRB_NIU + 0x98,
434 CRB_NIU_XG_PAUSE_CTL_P0|
435 CRB_NIU_XG_PAUSE_CTL_P1);
436 }
7c3df132 437 ql_log(ql_log_info, base_vha, 0x101c,
24d9ee85 438 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 439 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
440 "abort.\n", command, mcp->mb[0],
441 ha->flags.eeh_busy);
cdbb0a4f
SV		 442 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
443 qla2xxx_wake_dpc(vha);
444 }
1da177e4 445 } else if (!abort_active) {
1da177e4 446 /* call abort directly since we are in the DPC thread */
5e19ed90 447 ql_dbg(ql_dbg_mbx, vha, 0x101d,
7c3df132 448 "Timeout, calling abort_isp.\n");
cdbb0a4f
SV		 449
450 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
451 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
452 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 453 if (IS_QLA82XX(ha)) {
454 ql_dbg(ql_dbg_mbx, vha, 0x112b,
455 "disabling pause transmit on port "
456 "0 & 1.\n");
457 qla82xx_wr_32(ha,
458 QLA82XX_CRB_NIU + 0x98,
459 CRB_NIU_XG_PAUSE_CTL_P0|
460 CRB_NIU_XG_PAUSE_CTL_P1);
461 }
7c3df132 462 ql_log(ql_log_info, base_vha, 0x101e,
24d9ee85 463 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 464 "mb[0]=0x%x. Scheduling ISP abort ",
465 command, mcp->mb[0]);
cdbb0a4f
SV		 466 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
467 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
d3360960
GM		 468 /* Allow next mbx cmd to come in. */
469 complete(&ha->mbx_cmd_comp);
cdbb0a4f
SV		 470 if (ha->isp_ops->abort_isp(vha)) {
471 /* Failed. retry later. */
472 set_bit(ISP_ABORT_NEEDED,
473 &vha->dpc_flags);
474 }
475 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
5e19ed90 476 ql_dbg(ql_dbg_mbx, vha, 0x101f,
7c3df132 477 "Finished abort_isp.\n");
d3360960 478 goto mbx_done;
1da177e4 479 }
1da177e4
LT		 480 }
481 }
482
cdbb0a4f 483premature_exit:
1da177e4 484 /* Allow next mbx cmd to come in. */
8eca3f39 485 complete(&ha->mbx_cmd_comp);
1da177e4 486
d3360960 487mbx_done:
1da177e4 488 if (rval) {
34c5801d 489 ql_dbg(ql_dbg_disc, base_vha, 0x1020,
6246b8a1
GM		 490 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
491 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
d14e72fb 492
75d560e0 493 ql_dbg(ql_dbg_mbx, vha, 0x1198,
d14e72fb
HM		 494 "host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n",
495 RD_REG_DWORD(&reg->isp24.host_status),
496 ha->fw_dump_cap_flags,
497 RD_REG_DWORD(&reg->isp24.ictrl),
498 RD_REG_DWORD(&reg->isp24.istatus));
499
500 mbx_reg = &reg->isp24.mailbox0;
501 for (i = 0; i < 6; i++)
75d560e0 502 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1199,
d14e72fb 503 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
1da177e4 504 } else {
7c3df132 505 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
1da177e4
LT		 506 }
507
1da177e4
LT		 508 return rval;
509}
510
1da177e4 511int
7b867cf7 512qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
590f98e5 513 uint32_t risc_code_size)
1da177e4
LT		 514{
515 int rval;
7b867cf7 516 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 517 mbx_cmd_t mc;
518 mbx_cmd_t *mcp = &mc;
1da177e4 519
5f28d2d7
SK		 520 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
521 "Entered %s.\n", __func__);
1da177e4 522
e428924c 523 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
590f98e5 524 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
525 mcp->mb[8] = MSW(risc_addr);
526 mcp->out_mb = MBX_8|MBX_0;
1da177e4 527 } else {
590f98e5 528 mcp->mb[0] = MBC_LOAD_RISC_RAM;
529 mcp->out_mb = MBX_0;
1da177e4 530 }
1da177e4
LT		 531 mcp->mb[1] = LSW(risc_addr);
532 mcp->mb[2] = MSW(req_dma);
533 mcp->mb[3] = LSW(req_dma);
1da177e4
LT		 534 mcp->mb[6] = MSW(MSD(req_dma));
535 mcp->mb[7] = LSW(MSD(req_dma));
590f98e5 536 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
e428924c 537 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 538 mcp->mb[4] = MSW(risc_code_size);
539 mcp->mb[5] = LSW(risc_code_size);
540 mcp->out_mb |= MBX_5|MBX_4;
541 } else {
542 mcp->mb[4] = LSW(risc_code_size);
543 mcp->out_mb |= MBX_4;
544 }
545
1da177e4 546 mcp->in_mb = MBX_0;
b93480e3 547 mcp->tov = MBX_TOV_SECONDS;
1da177e4 548 mcp->flags = 0;
7b867cf7 549 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 550
1da177e4 551 if (rval != QLA_SUCCESS) {
7c3df132
SK		 552 ql_dbg(ql_dbg_mbx, vha, 0x1023,
553 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4 554 } else {
5f28d2d7
SK		 555 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
556 "Done %s.\n", __func__);
1da177e4
LT		 557 }
558
559 return rval;
560}
561
cad454b1 562#define EXTENDED_BB_CREDITS BIT_0
1da177e4
LT		 563/*
564 * qla2x00_execute_fw
1c7c6357 565 * Start adapter firmware.
1da177e4
LT		 566 *
567 * Input:
1c7c6357
AV		 568 * ha = adapter block pointer.
569 * TARGET_QUEUE_LOCK must be released.
570 * ADAPTER_STATE_LOCK must be released.
1da177e4
LT		 571 *
572 * Returns:
1c7c6357 573 * qla2x00 local function return status code.
1da177e4
LT		 574 *
575 * Context:
1c7c6357 576 * Kernel context.
1da177e4
LT		 577 */
578int
7b867cf7 579qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 580{
581 int rval;
7b867cf7 582 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 583 mbx_cmd_t mc;
584 mbx_cmd_t *mcp = &mc;
585
5f28d2d7
SK		 586 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
587 "Entered %s.\n", __func__);
1da177e4
LT		 588
589 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
1c7c6357
AV		 590 mcp->out_mb = MBX_0;
591 mcp->in_mb = MBX_0;
e428924c 592 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 593 mcp->mb[1] = MSW(risc_addr);
594 mcp->mb[2] = LSW(risc_addr);
595 mcp->mb[3] = 0;
f73cb695
CD		 596 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
597 IS_QLA27XX(ha)) {
cad454b1
SV		 598 struct nvram_81xx *nv = ha->nvram;
599 mcp->mb[4] = (nv->enhanced_features &
600 EXTENDED_BB_CREDITS);
601 } else
602 mcp->mb[4] = 0;
b0d6cabd
HM		 603
604 if (ha->flags.exlogins_enabled)
605 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
606
2f56a7f1
HM		 607 if (ha->flags.exchoffld_enabled)
608 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
609
8b3253d1 610 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
1c7c6357
AV		 611 mcp->in_mb |= MBX_1;
612 } else {
613 mcp->mb[1] = LSW(risc_addr);
614 mcp->out_mb |= MBX_1;
615 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
616 mcp->mb[2] = 0;
617 mcp->out_mb |= MBX_2;
618 }
1da177e4
LT		 619 }
620
b93480e3 621 mcp->tov = MBX_TOV_SECONDS;
1da177e4 622 mcp->flags = 0;
7b867cf7 623 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 624
1c7c6357 625 if (rval != QLA_SUCCESS) {
7c3df132
SK		 626 ql_dbg(ql_dbg_mbx, vha, 0x1026,
627 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357 628 } else {
e428924c 629 if (IS_FWI2_CAPABLE(ha)) {
5f28d2d7 630 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
7c3df132 631 "Done exchanges=%x.\n", mcp->mb[1]);
1c7c6357 632 } else {
5f28d2d7
SK		 633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
634 "Done %s.\n", __func__);
1c7c6357
AV		 635 }
636 }
1da177e4
LT		 637
638 return rval;
639}
640
b0d6cabd
HM		 641/*
642 * qla_get_exlogin_status
643 * Get extended login status
644 * uses the memory offload control/status Mailbox
645 *
646 * Input:
647 * ha: adapter state pointer.
648 * fwopt: firmware options
649 *
650 * Returns:
651 * qla2x00 local function status
652 *
653 * Context:
654 * Kernel context.
655 */
656#define FETCH_XLOGINS_STAT 0x8
657int
658qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
659 uint16_t *ex_logins_cnt)
660{
661 int rval;
662 mbx_cmd_t mc;
663 mbx_cmd_t *mcp = &mc;
664
665 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
666 "Entered %s\n", __func__);
667
668 memset(mcp->mb, 0 , sizeof(mcp->mb));
669 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
670 mcp->mb[1] = FETCH_XLOGINS_STAT;
671 mcp->out_mb = MBX_1|MBX_0;
672 mcp->in_mb = MBX_10|MBX_4|MBX_0;
673 mcp->tov = MBX_TOV_SECONDS;
674 mcp->flags = 0;
675
676 rval = qla2x00_mailbox_command(vha, mcp);
677 if (rval != QLA_SUCCESS) {
678 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
679 } else {
680 *buf_sz = mcp->mb[4];
681 *ex_logins_cnt = mcp->mb[10];
682
683 ql_log(ql_log_info, vha, 0x1190,
684 "buffer size 0x%x, exchange login count=%d\n",
685 mcp->mb[4], mcp->mb[10]);
686
687 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
688 "Done %s.\n", __func__);
689 }
690
691 return rval;
692}
693
694/*
695 * qla_set_exlogin_mem_cfg
696 * set extended login memory configuration
697 * Mbx needs to be issues before init_cb is set
698 *
699 * Input:
700 * ha: adapter state pointer.
701 * buffer: buffer pointer
702 * phys_addr: physical address of buffer
703 * size: size of buffer
704 * TARGET_QUEUE_LOCK must be released
705 * ADAPTER_STATE_LOCK must be release
706 *
707 * Returns:
708 * qla2x00 local funxtion status code.
709 *
710 * Context:
711 * Kernel context.
712 */
713#define CONFIG_XLOGINS_MEM 0x3
714int
715qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
716{
717 int rval;
718 mbx_cmd_t mc;
719 mbx_cmd_t *mcp = &mc;
720 struct qla_hw_data *ha = vha->hw;
b0d6cabd
HM		 721
722 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
723 "Entered %s.\n", __func__);
724
725 memset(mcp->mb, 0 , sizeof(mcp->mb));
726 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
727 mcp->mb[1] = CONFIG_XLOGINS_MEM;
728 mcp->mb[2] = MSW(phys_addr);
729 mcp->mb[3] = LSW(phys_addr);
730 mcp->mb[6] = MSW(MSD(phys_addr));
731 mcp->mb[7] = LSW(MSD(phys_addr));
732 mcp->mb[8] = MSW(ha->exlogin_size);
733 mcp->mb[9] = LSW(ha->exlogin_size);
734 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
735 mcp->in_mb = MBX_11|MBX_0;
736 mcp->tov = MBX_TOV_SECONDS;
737 mcp->flags = 0;
738 rval = qla2x00_mailbox_command(vha, mcp);
739 if (rval != QLA_SUCCESS) {
740 /*EMPTY*/
741 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval);
742 } else {
b0d6cabd
HM		 743 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
744 "Done %s.\n", __func__);
745 }
746
747 return rval;
748}
749
2f56a7f1
HM		 750/*
751 * qla_get_exchoffld_status
752 * Get exchange offload status
753 * uses the memory offload control/status Mailbox
754 *
755 * Input:
756 * ha: adapter state pointer.
757 * fwopt: firmware options
758 *
759 * Returns:
760 * qla2x00 local function status
761 *
762 * Context:
763 * Kernel context.
764 */
765#define FETCH_XCHOFFLD_STAT 0x2
766int
767qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
768 uint16_t *ex_logins_cnt)
769{
770 int rval;
771 mbx_cmd_t mc;
772 mbx_cmd_t *mcp = &mc;
773
774 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
775 "Entered %s\n", __func__);
776
777 memset(mcp->mb, 0 , sizeof(mcp->mb));
778 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
779 mcp->mb[1] = FETCH_XCHOFFLD_STAT;
780 mcp->out_mb = MBX_1|MBX_0;
781 mcp->in_mb = MBX_10|MBX_4|MBX_0;
782 mcp->tov = MBX_TOV_SECONDS;
783 mcp->flags = 0;
784
785 rval = qla2x00_mailbox_command(vha, mcp);
786 if (rval != QLA_SUCCESS) {
787 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
788 } else {
789 *buf_sz = mcp->mb[4];
790 *ex_logins_cnt = mcp->mb[10];
791
792 ql_log(ql_log_info, vha, 0x118e,
793 "buffer size 0x%x, exchange offload count=%d\n",
794 mcp->mb[4], mcp->mb[10]);
795
796 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
797 "Done %s.\n", __func__);
798 }
799
800 return rval;
801}
802
803/*
804 * qla_set_exchoffld_mem_cfg
805 * Set exchange offload memory configuration
806 * Mbx needs to be issues before init_cb is set
807 *
808 * Input:
809 * ha: adapter state pointer.
810 * buffer: buffer pointer
811 * phys_addr: physical address of buffer
812 * size: size of buffer
813 * TARGET_QUEUE_LOCK must be released
814 * ADAPTER_STATE_LOCK must be release
815 *
816 * Returns:
817 * qla2x00 local funxtion status code.
818 *
819 * Context:
820 * Kernel context.
821 */
822#define CONFIG_XCHOFFLD_MEM 0x3
823int
99e1b683 824qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha)
2f56a7f1
HM		 825{
826 int rval;
827 mbx_cmd_t mc;
828 mbx_cmd_t *mcp = &mc;
829 struct qla_hw_data *ha = vha->hw;
830
831 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
832 "Entered %s.\n", __func__);
833
834 memset(mcp->mb, 0 , sizeof(mcp->mb));
835 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
836 mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
99e1b683
QT		 837 mcp->mb[2] = MSW(ha->exchoffld_buf_dma);
838 mcp->mb[3] = LSW(ha->exchoffld_buf_dma);
839 mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma));
840 mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma));
841 mcp->mb[8] = MSW(ha->exchoffld_size);
842 mcp->mb[9] = LSW(ha->exchoffld_size);
2f56a7f1
HM		 843 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
844 mcp->in_mb = MBX_11|MBX_0;
845 mcp->tov = MBX_TOV_SECONDS;
846 mcp->flags = 0;
847 rval = qla2x00_mailbox_command(vha, mcp);
848 if (rval != QLA_SUCCESS) {
849 /*EMPTY*/
850 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
851 } else {
852 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
853 "Done %s.\n", __func__);
854 }
855
856 return rval;
857}
858
1da177e4
LT		 859/*
860 * qla2x00_get_fw_version
861 * Get firmware version.
862 *
863 * Input:
864 * ha: adapter state pointer.
865 * major: pointer for major number.
866 * minor: pointer for minor number.
867 * subminor: pointer for subminor number.
868 *
869 * Returns:
870 * qla2x00 local function return status code.
871 *
872 * Context:
873 * Kernel context.
874 */
ca9e9c3e 875int
6246b8a1 876qla2x00_get_fw_version(scsi_qla_host_t *vha)
1da177e4
LT		 877{
878 int rval;
879 mbx_cmd_t mc;
880 mbx_cmd_t *mcp = &mc;
6246b8a1 881 struct qla_hw_data *ha = vha->hw;
1da177e4 882
5f28d2d7
SK		 883 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
884 "Entered %s.\n", __func__);
1da177e4
LT		 885
886 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
887 mcp->out_mb = MBX_0;
888 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
7ec0effd 889 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
55a96158 890 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
fb0effee 891 if (IS_FWI2_CAPABLE(ha))
6246b8a1 892 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
f73cb695 893 if (IS_QLA27XX(ha))
ad1ef177
JC		 894 mcp->in_mb |=
895 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
896 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8;
03aa868c 897
1da177e4 898 mcp->flags = 0;
b93480e3 899 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 900 rval = qla2x00_mailbox_command(vha, mcp);
ca9e9c3e
AV		 901 if (rval != QLA_SUCCESS)
902 goto failed;
1da177e4
LT		 903
904 /* Return mailbox data. */
6246b8a1
GM		 905 ha->fw_major_version = mcp->mb[1];
906 ha->fw_minor_version = mcp->mb[2];
907 ha->fw_subminor_version = mcp->mb[3];
908 ha->fw_attributes = mcp->mb[6];
7b867cf7 909 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
6246b8a1 910 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1da177e4 911 else
6246b8a1 912 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
03aa868c 913
7ec0effd 914 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
6246b8a1
GM		 915 ha->mpi_version[0] = mcp->mb[10] & 0xff;
916 ha->mpi_version[1] = mcp->mb[11] >> 8;
917 ha->mpi_version[2] = mcp->mb[11] & 0xff;
918 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
919 ha->phy_version[0] = mcp->mb[8] & 0xff;
920 ha->phy_version[1] = mcp->mb[9] >> 8;
921 ha->phy_version[2] = mcp->mb[9] & 0xff;
922 }
03aa868c 923
81178772
SK		 924 if (IS_FWI2_CAPABLE(ha)) {
925 ha->fw_attributes_h = mcp->mb[15];
926 ha->fw_attributes_ext[0] = mcp->mb[16];
927 ha->fw_attributes_ext[1] = mcp->mb[17];
928 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
929 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
930 __func__, mcp->mb[15], mcp->mb[6]);
931 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
932 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
933 __func__, mcp->mb[17], mcp->mb[16]);
2f56a7f1 934
b0d6cabd
HM		 935 if (ha->fw_attributes_h & 0x4)
936 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
937 "%s: Firmware supports Extended Login 0x%x\n",
938 __func__, ha->fw_attributes_h);
2f56a7f1
HM		 939
940 if (ha->fw_attributes_h & 0x8)
941 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
942 "%s: Firmware supports Exchange Offload 0x%x\n",
943 __func__, ha->fw_attributes_h);
3a03eb79 944 }
03aa868c 945
f73cb695 946 if (IS_QLA27XX(ha)) {
03aa868c
SC		 947 ha->mpi_version[0] = mcp->mb[10] & 0xff;
948 ha->mpi_version[1] = mcp->mb[11] >> 8;
949 ha->mpi_version[2] = mcp->mb[11] & 0xff;
950 ha->pep_version[0] = mcp->mb[13] & 0xff;
951 ha->pep_version[1] = mcp->mb[14] >> 8;
952 ha->pep_version[2] = mcp->mb[14] & 0xff;
f73cb695
CD		 953 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
954 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
ad1ef177
JC		 955 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
956 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
f73cb695 957 }
6246b8a1 958
ca9e9c3e 959failed:
1da177e4
LT		 960 if (rval != QLA_SUCCESS) {
961 /*EMPTY*/
7c3df132 962 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1da177e4
LT		 963 } else {
964 /*EMPTY*/
5f28d2d7
SK		 965 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
966 "Done %s.\n", __func__);
1da177e4 967 }
ca9e9c3e 968 return rval;
1da177e4
LT		 969}
970
971/*
972 * qla2x00_get_fw_options
973 * Set firmware options.
974 *
975 * Input:
976 * ha = adapter block pointer.
977 * fwopt = pointer for firmware options.
978 *
979 * Returns:
980 * qla2x00 local function return status code.
981 *
982 * Context:
983 * Kernel context.
984 */
985int
7b867cf7 986qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 987{
988 int rval;
989 mbx_cmd_t mc;
990 mbx_cmd_t *mcp = &mc;
991
5f28d2d7
SK		 992 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
993 "Entered %s.\n", __func__);
1da177e4
LT		 994
995 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
996 mcp->out_mb = MBX_0;
997 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 998 mcp->tov = MBX_TOV_SECONDS;
1da177e4 999 mcp->flags = 0;
7b867cf7 1000 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1001
1002 if (rval != QLA_SUCCESS) {
1003 /*EMPTY*/
7c3df132 1004 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1da177e4 1005 } else {
1c7c6357 1006 fwopts[0] = mcp->mb[0];
1da177e4
LT		 1007 fwopts[1] = mcp->mb[1];
1008 fwopts[2] = mcp->mb[2];
1009 fwopts[3] = mcp->mb[3];
1010
5f28d2d7
SK		 1011 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
1012 "Done %s.\n", __func__);
1da177e4
LT		 1013 }
1014
1015 return rval;
1016}
1017
1018
1019/*
1020 * qla2x00_set_fw_options
1021 * Set firmware options.
1022 *
1023 * Input:
1024 * ha = adapter block pointer.
1025 * fwopt = pointer for firmware options.
1026 *
1027 * Returns:
1028 * qla2x00 local function return status code.
1029 *
1030 * Context:
1031 * Kernel context.
1032 */
1033int
7b867cf7 1034qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1035{
1036 int rval;
1037 mbx_cmd_t mc;
1038 mbx_cmd_t *mcp = &mc;
1039
5f28d2d7
SK		 1040 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
1041 "Entered %s.\n", __func__);
1da177e4
LT		 1042
1043 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
1044 mcp->mb[1] = fwopts[1];
1045 mcp->mb[2] = fwopts[2];
1046 mcp->mb[3] = fwopts[3];
1c7c6357 1047 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 1048 mcp->in_mb = MBX_0;
7b867cf7 1049 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 1050 mcp->in_mb |= MBX_1;
2da52737
QT		 1051 mcp->mb[10] = fwopts[10];
1052 mcp->out_mb |= MBX_10;
1c7c6357
AV		 1053 } else {
1054 mcp->mb[10] = fwopts[10];
1055 mcp->mb[11] = fwopts[11];
1056 mcp->mb[12] = 0; /* Undocumented, but used */
1057 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
1058 }
b93480e3 1059 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1060 mcp->flags = 0;
7b867cf7 1061 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1062
1c7c6357
AV		 1063 fwopts[0] = mcp->mb[0];
1064
1da177e4
LT		 1065 if (rval != QLA_SUCCESS) {
1066 /*EMPTY*/
7c3df132
SK		 1067 ql_dbg(ql_dbg_mbx, vha, 0x1030,
1068 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 1069 } else {
1070 /*EMPTY*/
5f28d2d7
SK		 1071 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
1072 "Done %s.\n", __func__);
1da177e4
LT		 1073 }
1074
1075 return rval;
1076}
1077
1078/*
1079 * qla2x00_mbx_reg_test
1080 * Mailbox register wrap test.
1081 *
1082 * Input:
1083 * ha = adapter block pointer.
1084 * TARGET_QUEUE_LOCK must be released.
1085 * ADAPTER_STATE_LOCK must be released.
1086 *
1087 * Returns:
1088 * qla2x00 local function return status code.
1089 *
1090 * Context:
1091 * Kernel context.
1092 */
1093int
7b867cf7 1094qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1da177e4
LT		 1095{
1096 int rval;
1097 mbx_cmd_t mc;
1098 mbx_cmd_t *mcp = &mc;
1099
5f28d2d7
SK		 1100 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
1101 "Entered %s.\n", __func__);
1da177e4
LT		 1102
1103 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
1104 mcp->mb[1] = 0xAAAA;
1105 mcp->mb[2] = 0x5555;
1106 mcp->mb[3] = 0xAA55;
1107 mcp->mb[4] = 0x55AA;
1108 mcp->mb[5] = 0xA5A5;
1109 mcp->mb[6] = 0x5A5A;
1110 mcp->mb[7] = 0x2525;
1111 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1112 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1113 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1114 mcp->flags = 0;
7b867cf7 1115 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1116
1117 if (rval == QLA_SUCCESS) {
1118 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
1119 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
1120 rval = QLA_FUNCTION_FAILED;
1121 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
1122 mcp->mb[7] != 0x2525)
1123 rval = QLA_FUNCTION_FAILED;
1124 }
1125
1126 if (rval != QLA_SUCCESS) {
1127 /*EMPTY*/
7c3df132 1128 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1da177e4
LT		 1129 } else {
1130 /*EMPTY*/
5f28d2d7
SK		 1131 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
1132 "Done %s.\n", __func__);
1da177e4
LT		 1133 }
1134
1135 return rval;
1136}
1137
1138/*
1139 * qla2x00_verify_checksum
1140 * Verify firmware checksum.
1141 *
1142 * Input:
1143 * ha = adapter block pointer.
1144 * TARGET_QUEUE_LOCK must be released.
1145 * ADAPTER_STATE_LOCK must be released.
1146 *
1147 * Returns:
1148 * qla2x00 local function return status code.
1149 *
1150 * Context:
1151 * Kernel context.
1152 */
1153int
7b867cf7 1154qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 1155{
1156 int rval;
1157 mbx_cmd_t mc;
1158 mbx_cmd_t *mcp = &mc;
1159
5f28d2d7
SK		 1160 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
1161 "Entered %s.\n", __func__);
1da177e4
LT		 1162
1163 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1c7c6357
AV		 1164 mcp->out_mb = MBX_0;
1165 mcp->in_mb = MBX_0;
7b867cf7 1166 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 1167 mcp->mb[1] = MSW(risc_addr);
1168 mcp->mb[2] = LSW(risc_addr);
1169 mcp->out_mb |= MBX_2|MBX_1;
1170 mcp->in_mb |= MBX_2|MBX_1;
1171 } else {
1172 mcp->mb[1] = LSW(risc_addr);
1173 mcp->out_mb |= MBX_1;
1174 mcp->in_mb |= MBX_1;
1175 }
1176
b93480e3 1177 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1178 mcp->flags = 0;
7b867cf7 1179 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1180
1181 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1182 ql_dbg(ql_dbg_mbx, vha, 0x1036,
1183 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
1184 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1da177e4 1185 } else {
5f28d2d7
SK		 1186 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
1187 "Done %s.\n", __func__);
1da177e4
LT		 1188 }
1189
1190 return rval;
1191}
1192
1193/*
1194 * qla2x00_issue_iocb
1195 * Issue IOCB using mailbox command
1196 *
1197 * Input:
1198 * ha = adapter state pointer.
1199 * buffer = buffer pointer.
1200 * phys_addr = physical address of buffer.
1201 * size = size of buffer.
1202 * TARGET_QUEUE_LOCK must be released.
1203 * ADAPTER_STATE_LOCK must be released.
1204 *
1205 * Returns:
1206 * qla2x00 local function return status code.
1207 *
1208 * Context:
1209 * Kernel context.
1210 */
6e98016c 1211int
7b867cf7 1212qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
4d4df193 1213 dma_addr_t phys_addr, size_t size, uint32_t tov)
1da177e4
LT		 1214{
1215 int rval;
1216 mbx_cmd_t mc;
1217 mbx_cmd_t *mcp = &mc;
1218
5f28d2d7
SK		 1219 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1220 "Entered %s.\n", __func__);
7c3df132 1221
1da177e4
LT		 1222 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1223 mcp->mb[1] = 0;
1224 mcp->mb[2] = MSW(phys_addr);
1225 mcp->mb[3] = LSW(phys_addr);
1226 mcp->mb[6] = MSW(MSD(phys_addr));
1227 mcp->mb[7] = LSW(MSD(phys_addr));
1228 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1229 mcp->in_mb = MBX_2|MBX_0;
4d4df193 1230 mcp->tov = tov;
1da177e4 1231 mcp->flags = 0;
7b867cf7 1232 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1233
1234 if (rval != QLA_SUCCESS) {
1235 /*EMPTY*/
7c3df132 1236 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1da177e4 1237 } else {
8c958a99
AV		 1238 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
1239
1240 /* Mask reserved bits. */
1241 sts_entry->entry_status &=
7b867cf7 1242 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
5f28d2d7
SK		 1243 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1244 "Done %s.\n", __func__);
1da177e4
LT		 1245 }
1246
1247 return rval;
1248}
1249
4d4df193 1250int
7b867cf7 1251qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
4d4df193
HK		 1252 size_t size)
1253{
7b867cf7 1254 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
4d4df193
HK		 1255 MBX_TOV_SECONDS);
1256}
1257
1da177e4
LT		 1258/*
1259 * qla2x00_abort_command
1260 * Abort command aborts a specified IOCB.
1261 *
1262 * Input:
1263 * ha = adapter block pointer.
1264 * sp = SB structure pointer.
1265 *
1266 * Returns:
1267 * qla2x00 local function return status code.
1268 *
1269 * Context:
1270 * Kernel context.
1271 */
1272int
2afa19a9 1273qla2x00_abort_command(srb_t *sp)
1da177e4
LT		 1274{
1275 unsigned long flags = 0;
1da177e4 1276 int rval;
73208dfd 1277 uint32_t handle = 0;
1da177e4
LT		 1278 mbx_cmd_t mc;
1279 mbx_cmd_t *mcp = &mc;
2afa19a9
AC		 1280 fc_port_t *fcport = sp->fcport;
1281 scsi_qla_host_t *vha = fcport->vha;
7b867cf7 1282 struct qla_hw_data *ha = vha->hw;
d7459527 1283 struct req_que *req;
9ba56b95 1284 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1da177e4 1285
5f28d2d7
SK		 1286 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1287 "Entered %s.\n", __func__);
1da177e4 1288
d7459527
MH		 1289 if (vha->flags.qpairs_available && sp->qpair)
1290 req = sp->qpair->req;
1291 else
1292 req = vha->req;
1293
c9c5ced9 1294 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 1295 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 1296 if (req->outstanding_cmds[handle] == sp)
1da177e4
LT		 1297 break;
1298 }
c9c5ced9 1299 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1300
8d93f550 1301 if (handle == req->num_outstanding_cmds) {
1da177e4
LT		 1302 /* command not found */
1303 return QLA_FUNCTION_FAILED;
1304 }
1305
1306 mcp->mb[0] = MBC_ABORT_COMMAND;
1307 if (HAS_EXTENDED_IDS(ha))
1308 mcp->mb[1] = fcport->loop_id;
1309 else
1310 mcp->mb[1] = fcport->loop_id << 8;
1311 mcp->mb[2] = (uint16_t)handle;
1312 mcp->mb[3] = (uint16_t)(handle >> 16);
9ba56b95 1313 mcp->mb[6] = (uint16_t)cmd->device->lun;
1da177e4
LT		 1314 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1315 mcp->in_mb = MBX_0;
b93480e3 1316 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1317 mcp->flags = 0;
7b867cf7 1318 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1319
1320 if (rval != QLA_SUCCESS) {
7c3df132 1321 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1da177e4 1322 } else {
5f28d2d7
SK		 1323 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
1324 "Done %s.\n", __func__);
1da177e4
LT		 1325 }
1326
1327 return rval;
1328}
1329
1da177e4 1330int
9cb78c16 1331qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
1da177e4 1332{
523ec773 1333 int rval, rval2;
1da177e4
LT		 1334 mbx_cmd_t mc;
1335 mbx_cmd_t *mcp = &mc;
7b867cf7 1336 scsi_qla_host_t *vha;
73208dfd
AC		 1337 struct req_que *req;
1338 struct rsp_que *rsp;
1da177e4 1339
523ec773 1340 l = l;
7b867cf7 1341 vha = fcport->vha;
7c3df132 1342
5f28d2d7
SK		 1343 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1344 "Entered %s.\n", __func__);
7c3df132 1345
7e2b895b
GM		 1346 req = vha->hw->req_q_map[0];
1347 rsp = req->rsp;
1da177e4 1348 mcp->mb[0] = MBC_ABORT_TARGET;
523ec773 1349 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
7b867cf7 1350 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1351 mcp->mb[1] = fcport->loop_id;
1352 mcp->mb[10] = 0;
1353 mcp->out_mb |= MBX_10;
1354 } else {
1355 mcp->mb[1] = fcport->loop_id << 8;
1356 }
7b867cf7
AC		 1357 mcp->mb[2] = vha->hw->loop_reset_delay;
1358 mcp->mb[9] = vha->vp_idx;
1da177e4
LT		 1359
1360 mcp->in_mb = MBX_0;
b93480e3 1361 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1362 mcp->flags = 0;
7b867cf7 1363 rval = qla2x00_mailbox_command(vha, mcp);
523ec773 1364 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 1365 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
1366 "Failed=%x.\n", rval);
523ec773
AV		 1367 }
1368
1369 /* Issue marker IOCB. */
73208dfd
AC		 1370 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
1371 MK_SYNC_ID);
523ec773 1372 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1373 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1374 "Failed to issue marker IOCB (%x).\n", rval2);
523ec773 1375 } else {
5f28d2d7
SK		 1376 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1377 "Done %s.\n", __func__);
523ec773
AV		 1378 }
1379
1380 return rval;
1381}
1382
1383int
9cb78c16 1384qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773
AV		 1385{
1386 int rval, rval2;
1387 mbx_cmd_t mc;
1388 mbx_cmd_t *mcp = &mc;
7b867cf7 1389 scsi_qla_host_t *vha;
73208dfd
AC		 1390 struct req_que *req;
1391 struct rsp_que *rsp;
523ec773 1392
7b867cf7 1393 vha = fcport->vha;
7c3df132 1394
5f28d2d7
SK		 1395 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1396 "Entered %s.\n", __func__);
7c3df132 1397
7e2b895b
GM		 1398 req = vha->hw->req_q_map[0];
1399 rsp = req->rsp;
523ec773
AV		 1400 mcp->mb[0] = MBC_LUN_RESET;
1401 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1402 if (HAS_EXTENDED_IDS(vha->hw))
523ec773
AV		 1403 mcp->mb[1] = fcport->loop_id;
1404 else
1405 mcp->mb[1] = fcport->loop_id << 8;
9cb78c16 1406 mcp->mb[2] = (u32)l;
523ec773 1407 mcp->mb[3] = 0;
7b867cf7 1408 mcp->mb[9] = vha->vp_idx;
1da177e4 1409
523ec773 1410 mcp->in_mb = MBX_0;
b93480e3 1411 mcp->tov = MBX_TOV_SECONDS;
523ec773 1412 mcp->flags = 0;
7b867cf7 1413 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1414 if (rval != QLA_SUCCESS) {
7c3df132 1415 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
523ec773
AV		 1416 }
1417
1418 /* Issue marker IOCB. */
73208dfd
AC		 1419 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1420 MK_SYNC_ID_LUN);
523ec773 1421 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1422 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1423 "Failed to issue marker IOCB (%x).\n", rval2);
1da177e4 1424 } else {
5f28d2d7
SK		 1425 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1426 "Done %s.\n", __func__);
1da177e4
LT		 1427 }
1428
1429 return rval;
1430}
1da177e4 1431
1da177e4
LT		 1432/*
1433 * qla2x00_get_adapter_id
1434 * Get adapter ID and topology.
1435 *
1436 * Input:
1437 * ha = adapter block pointer.
1438 * id = pointer for loop ID.
1439 * al_pa = pointer for AL_PA.
1440 * area = pointer for area.
1441 * domain = pointer for domain.
1442 * top = pointer for topology.
1443 * TARGET_QUEUE_LOCK must be released.
1444 * ADAPTER_STATE_LOCK must be released.
1445 *
1446 * Returns:
1447 * qla2x00 local function return status code.
1448 *
1449 * Context:
1450 * Kernel context.
1451 */
1452int
7b867cf7 1453qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
2c3dfe3f 1454 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1da177e4
LT		 1455{
1456 int rval;
1457 mbx_cmd_t mc;
1458 mbx_cmd_t *mcp = &mc;
1459
5f28d2d7
SK		 1460 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1461 "Entered %s.\n", __func__);
1da177e4
LT		 1462
1463 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
7b867cf7 1464 mcp->mb[9] = vha->vp_idx;
eb66dc60 1465 mcp->out_mb = MBX_9|MBX_0;
2c3dfe3f 1466 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 1467 if (IS_CNA_CAPABLE(vha->hw))
bad7001c 1468 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
7c9c4766
JC		 1469 if (IS_FWI2_CAPABLE(vha->hw))
1470 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
969a6199
SC		 1471 if (IS_QLA27XX(vha->hw))
1472 mcp->in_mb |= MBX_15;
b93480e3 1473 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1474 mcp->flags = 0;
7b867cf7 1475 rval = qla2x00_mailbox_command(vha, mcp);
33135aa2
RA		 1476 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1477 rval = QLA_COMMAND_ERROR;
42e421b1
AV		 1478 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1479 rval = QLA_INVALID_COMMAND;
1da177e4
LT		 1480
1481 /* Return data. */
1482 *id = mcp->mb[1];
1483 *al_pa = LSB(mcp->mb[2]);
1484 *area = MSB(mcp->mb[2]);
1485 *domain = LSB(mcp->mb[3]);
1486 *top = mcp->mb[6];
2c3dfe3f 1487 *sw_cap = mcp->mb[7];
1da177e4
LT		 1488
1489 if (rval != QLA_SUCCESS) {
1490 /*EMPTY*/
7c3df132 1491 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1da177e4 1492 } else {
5f28d2d7
SK		 1493 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1494 "Done %s.\n", __func__);
bad7001c 1495
6246b8a1 1496 if (IS_CNA_CAPABLE(vha->hw)) {
bad7001c
AV		 1497 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1498 vha->fcoe_fcf_idx = mcp->mb[10];
1499 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1500 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1501 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1502 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1503 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1504 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1505 }
7c9c4766 1506 /* If FA-WWN supported */
d6b9b42b
SK		 1507 if (IS_FAWWN_CAPABLE(vha->hw)) {
1508 if (mcp->mb[7] & BIT_14) {
1509 vha->port_name[0] = MSB(mcp->mb[16]);
1510 vha->port_name[1] = LSB(mcp->mb[16]);
1511 vha->port_name[2] = MSB(mcp->mb[17]);
1512 vha->port_name[3] = LSB(mcp->mb[17]);
1513 vha->port_name[4] = MSB(mcp->mb[18]);
1514 vha->port_name[5] = LSB(mcp->mb[18]);
1515 vha->port_name[6] = MSB(mcp->mb[19]);
1516 vha->port_name[7] = LSB(mcp->mb[19]);
1517 fc_host_port_name(vha->host) =
1518 wwn_to_u64(vha->port_name);
1519 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1520 "FA-WWN acquired %016llx\n",
1521 wwn_to_u64(vha->port_name));
1522 }
7c9c4766 1523 }
969a6199
SC		 1524
1525 if (IS_QLA27XX(vha->hw))
1526 vha->bbcr = mcp->mb[15];
1da177e4
LT		 1527 }
1528
1529 return rval;
1530}
1531
1532/*
1533 * qla2x00_get_retry_cnt
1534 * Get current firmware login retry count and delay.
1535 *
1536 * Input:
1537 * ha = adapter block pointer.
1538 * retry_cnt = pointer to login retry count.
1539 * tov = pointer to login timeout value.
1540 *
1541 * Returns:
1542 * qla2x00 local function return status code.
1543 *
1544 * Context:
1545 * Kernel context.
1546 */
1547int
7b867cf7 1548qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1da177e4
LT		 1549 uint16_t *r_a_tov)
1550{
1551 int rval;
1552 uint16_t ratov;
1553 mbx_cmd_t mc;
1554 mbx_cmd_t *mcp = &mc;
1555
5f28d2d7
SK		 1556 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1557 "Entered %s.\n", __func__);
1da177e4
LT		 1558
1559 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1560 mcp->out_mb = MBX_0;
1561 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1562 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1563 mcp->flags = 0;
7b867cf7 1564 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1565
1566 if (rval != QLA_SUCCESS) {
1567 /*EMPTY*/
7c3df132
SK		 1568 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1569 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1570 } else {
1571 /* Convert returned data and check our values. */
1572 *r_a_tov = mcp->mb[3] / 2;
1573 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1574 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1575 /* Update to the larger values */
1576 *retry_cnt = (uint8_t)mcp->mb[1];
1577 *tov = ratov;
1578 }
1579
5f28d2d7 1580 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
7c3df132 1581 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1da177e4
LT		 1582 }
1583
1584 return rval;
1585}
1586
1587/*
1588 * qla2x00_init_firmware
1589 * Initialize adapter firmware.
1590 *
1591 * Input:
1592 * ha = adapter block pointer.
1593 * dptr = Initialization control block pointer.
1594 * size = size of initialization control block.
1595 * TARGET_QUEUE_LOCK must be released.
1596 * ADAPTER_STATE_LOCK must be released.
1597 *
1598 * Returns:
1599 * qla2x00 local function return status code.
1600 *
1601 * Context:
1602 * Kernel context.
1603 */
1604int
7b867cf7 1605qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1da177e4
LT		 1606{
1607 int rval;
1608 mbx_cmd_t mc;
1609 mbx_cmd_t *mcp = &mc;
7b867cf7 1610 struct qla_hw_data *ha = vha->hw;
1da177e4 1611
5f28d2d7
SK		 1612 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1613 "Entered %s.\n", __func__);
1da177e4 1614
7ec0effd 1615 if (IS_P3P_TYPE(ha) && ql2xdbwr)
8dfa4b5a 1616 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
a9083016
GM		 1617 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1618
e6e074f1 1619 if (ha->flags.npiv_supported)
2c3dfe3f
SJ		 1620 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1621 else
1622 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1623
b64b0e8f 1624 mcp->mb[1] = 0;
1da177e4
LT		 1625 mcp->mb[2] = MSW(ha->init_cb_dma);
1626 mcp->mb[3] = LSW(ha->init_cb_dma);
1da177e4
LT		 1627 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1628 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
b64b0e8f 1629 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4ef21bd4 1630 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
b64b0e8f
AV		 1631 mcp->mb[1] = BIT_0;
1632 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1633 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1634 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1635 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1636 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1637 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1638 }
6246b8a1
GM		 1639 /* 1 and 2 should normally be captured. */
1640 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 1641 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 1642 /* mb3 is additional info about the installed SFP. */
1643 mcp->in_mb |= MBX_3;
1da177e4
LT		 1644 mcp->buf_size = size;
1645 mcp->flags = MBX_DMA_OUT;
b93480e3 1646 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1647 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1648
1649 if (rval != QLA_SUCCESS) {
1650 /*EMPTY*/
7c3df132 1651 ql_dbg(ql_dbg_mbx, vha, 0x104d,
6246b8a1
GM		 1652 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1653 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1da177e4
LT		 1654 } else {
1655 /*EMPTY*/
5f28d2d7
SK		 1656 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1657 "Done %s.\n", __func__);
1da177e4
LT		 1658 }
1659
1660 return rval;
1661}
1662
2d70c103 1663
1da177e4
LT		 1664/*
1665 * qla2x00_get_port_database
1666 * Issue normal/enhanced get port database mailbox command
1667 * and copy device name as necessary.
1668 *
1669 * Input:
1670 * ha = adapter state pointer.
1671 * dev = structure pointer.
1672 * opt = enhanced cmd option byte.
1673 *
1674 * Returns:
1675 * qla2x00 local function return status code.
1676 *
1677 * Context:
1678 * Kernel context.
1679 */
1680int
7b867cf7 1681qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1da177e4
LT		 1682{
1683 int rval;
1684 mbx_cmd_t mc;
1685 mbx_cmd_t *mcp = &mc;
1686 port_database_t *pd;
1c7c6357 1687 struct port_database_24xx *pd24;
1da177e4 1688 dma_addr_t pd_dma;
7b867cf7 1689 struct qla_hw_data *ha = vha->hw;
1da177e4 1690
5f28d2d7
SK		 1691 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1692 "Entered %s.\n", __func__);
1da177e4 1693
1c7c6357
AV		 1694 pd24 = NULL;
1695 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1da177e4 1696 if (pd == NULL) {
7c3df132
SK		 1697 ql_log(ql_log_warn, vha, 0x1050,
1698 "Failed to allocate port database structure.\n");
1da177e4
LT		 1699 return QLA_MEMORY_ALLOC_FAILED;
1700 }
1c7c6357 1701 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1da177e4 1702
1c7c6357 1703 mcp->mb[0] = MBC_GET_PORT_DATABASE;
e428924c 1704 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1da177e4 1705 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1da177e4
LT		 1706 mcp->mb[2] = MSW(pd_dma);
1707 mcp->mb[3] = LSW(pd_dma);
1708 mcp->mb[6] = MSW(MSD(pd_dma));
1709 mcp->mb[7] = LSW(MSD(pd_dma));
7b867cf7 1710 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1711 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1da177e4 1712 mcp->in_mb = MBX_0;
e428924c 1713 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1714 mcp->mb[1] = fcport->loop_id;
1715 mcp->mb[10] = opt;
1716 mcp->out_mb |= MBX_10|MBX_1;
1717 mcp->in_mb |= MBX_1;
1718 } else if (HAS_EXTENDED_IDS(ha)) {
1719 mcp->mb[1] = fcport->loop_id;
1720 mcp->mb[10] = opt;
1721 mcp->out_mb |= MBX_10|MBX_1;
1722 } else {
1723 mcp->mb[1] = fcport->loop_id << 8 | opt;
1724 mcp->out_mb |= MBX_1;
1725 }
e428924c
AV		 1726 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1727 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1da177e4
LT		 1728 mcp->flags = MBX_DMA_IN;
1729 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 1730 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1731 if (rval != QLA_SUCCESS)
1732 goto gpd_error_out;
1733
e428924c 1734 if (IS_FWI2_CAPABLE(ha)) {
0eba25df 1735 uint64_t zero = 0;
1c7c6357
AV		 1736 pd24 = (struct port_database_24xx *) pd;
1737
1738 /* Check for logged in state. */
1739 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1740 pd24->last_login_state != PDS_PRLI_COMPLETE) {
7c3df132
SK		 1741 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1742 "Unable to verify login-state (%x/%x) for "
1743 "loop_id %x.\n", pd24->current_login_state,
1744 pd24->last_login_state, fcport->loop_id);
1c7c6357
AV		 1745 rval = QLA_FUNCTION_FAILED;
1746 goto gpd_error_out;
1747 }
1da177e4 1748
0eba25df
AE		 1749 if (fcport->loop_id == FC_NO_LOOP_ID ||
1750 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1751 memcmp(fcport->port_name, pd24->port_name, 8))) {
1752 /* We lost the device mid way. */
1753 rval = QLA_NOT_LOGGED_IN;
1754 goto gpd_error_out;
1755 }
1756
1c7c6357
AV		 1757 /* Names are little-endian. */
1758 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1759 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1760
1761 /* Get port_id of device. */
1762 fcport->d_id.b.domain = pd24->port_id[0];
1763 fcport->d_id.b.area = pd24->port_id[1];
1764 fcport->d_id.b.al_pa = pd24->port_id[2];
1765 fcport->d_id.b.rsvd_1 = 0;
1766
1767 /* If not target must be initiator or unknown type. */
1768 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1769 fcport->port_type = FCT_INITIATOR;
1770 else
1771 fcport->port_type = FCT_TARGET;
2d70c103
NB		 1772
1773 /* Passback COS information. */
1774 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1775 FC_COS_CLASS2 : FC_COS_CLASS3;
1776
1777 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1778 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1c7c6357 1779 } else {
0eba25df
AE		 1780 uint64_t zero = 0;
1781
1c7c6357
AV		 1782 /* Check for logged in state. */
1783 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1784 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
7c3df132
SK		 1785 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1786 "Unable to verify login-state (%x/%x) - "
1787 "portid=%02x%02x%02x.\n", pd->master_state,
1788 pd->slave_state, fcport->d_id.b.domain,
1789 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1c7c6357
AV		 1790 rval = QLA_FUNCTION_FAILED;
1791 goto gpd_error_out;
1792 }
1da177e4 1793
0eba25df
AE		 1794 if (fcport->loop_id == FC_NO_LOOP_ID ||
1795 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1796 memcmp(fcport->port_name, pd->port_name, 8))) {
1797 /* We lost the device mid way. */
1798 rval = QLA_NOT_LOGGED_IN;
1799 goto gpd_error_out;
1800 }
1801
1c7c6357
AV		 1802 /* Names are little-endian. */
1803 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1804 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1805
1806 /* Get port_id of device. */
1807 fcport->d_id.b.domain = pd->port_id[0];
1808 fcport->d_id.b.area = pd->port_id[3];
1809 fcport->d_id.b.al_pa = pd->port_id[2];
1810 fcport->d_id.b.rsvd_1 = 0;
1811
1c7c6357
AV		 1812 /* If not target must be initiator or unknown type. */
1813 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1814 fcport->port_type = FCT_INITIATOR;
1815 else
1816 fcport->port_type = FCT_TARGET;
ad3e0eda
AV		 1817
1818 /* Passback COS information. */
1819 fcport->supported_classes = (pd->options & BIT_4) ?
1820 FC_COS_CLASS2: FC_COS_CLASS3;
1c7c6357 1821 }
1da177e4
LT		 1822
1823gpd_error_out:
1824 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1825
1826 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1827 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1828 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1829 mcp->mb[0], mcp->mb[1]);
1da177e4 1830 } else {
5f28d2d7
SK		 1831 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1832 "Done %s.\n", __func__);
1da177e4
LT		 1833 }
1834
1835 return rval;
1836}
1837
1838/*
1839 * qla2x00_get_firmware_state
1840 * Get adapter firmware state.
1841 *
1842 * Input:
1843 * ha = adapter block pointer.
1844 * dptr = pointer for firmware state.
1845 * TARGET_QUEUE_LOCK must be released.
1846 * ADAPTER_STATE_LOCK must be released.
1847 *
1848 * Returns:
1849 * qla2x00 local function return status code.
1850 *
1851 * Context:
1852 * Kernel context.
1853 */
1854int
7b867cf7 1855qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1da177e4
LT		 1856{
1857 int rval;
1858 mbx_cmd_t mc;
1859 mbx_cmd_t *mcp = &mc;
1860
5f28d2d7
SK		 1861 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
1862 "Entered %s.\n", __func__);
1da177e4
LT		 1863
1864 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1865 mcp->out_mb = MBX_0;
9d2683c0 1866 if (IS_FWI2_CAPABLE(vha->hw))
b5a340dd 1867 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
9d2683c0
AV		 1868 else
1869 mcp->in_mb = MBX_1|MBX_0;
b93480e3 1870 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1871 mcp->flags = 0;
7b867cf7 1872 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1873
4d4df193
HK		 1874 /* Return firmware states. */
1875 states[0] = mcp->mb[1];
9d2683c0
AV		 1876 if (IS_FWI2_CAPABLE(vha->hw)) {
1877 states[1] = mcp->mb[2];
ec891462 1878 states[2] = mcp->mb[3]; /* SFP info */
9d2683c0
AV		 1879 states[3] = mcp->mb[4];
1880 states[4] = mcp->mb[5];
b5a340dd 1881 states[5] = mcp->mb[6]; /* DPORT status */
9d2683c0 1882 }
1da177e4
LT		 1883
1884 if (rval != QLA_SUCCESS) {
1885 /*EMPTY*/
7c3df132 1886 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1da177e4
LT		 1887 } else {
1888 /*EMPTY*/
5f28d2d7
SK		 1889 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
1890 "Done %s.\n", __func__);
1da177e4
LT		 1891 }
1892
1893 return rval;
1894}
1895
1896/*
1897 * qla2x00_get_port_name
1898 * Issue get port name mailbox command.
1899 * Returned name is in big endian format.
1900 *
1901 * Input:
1902 * ha = adapter block pointer.
1903 * loop_id = loop ID of device.
1904 * name = pointer for name.
1905 * TARGET_QUEUE_LOCK must be released.
1906 * ADAPTER_STATE_LOCK must be released.
1907 *
1908 * Returns:
1909 * qla2x00 local function return status code.
1910 *
1911 * Context:
1912 * Kernel context.
1913 */
1914int
7b867cf7 1915qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1da177e4
LT		 1916 uint8_t opt)
1917{
1918 int rval;
1919 mbx_cmd_t mc;
1920 mbx_cmd_t *mcp = &mc;
1921
5f28d2d7
SK		 1922 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
1923 "Entered %s.\n", __func__);
1da177e4
LT		 1924
1925 mcp->mb[0] = MBC_GET_PORT_NAME;
7b867cf7 1926 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1927 mcp->out_mb = MBX_9|MBX_1|MBX_0;
7b867cf7 1928 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1929 mcp->mb[1] = loop_id;
1930 mcp->mb[10] = opt;
1931 mcp->out_mb |= MBX_10;
1932 } else {
1933 mcp->mb[1] = loop_id << 8 | opt;
1934 }
1935
1936 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1937 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1938 mcp->flags = 0;
7b867cf7 1939 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1940
1941 if (rval != QLA_SUCCESS) {
1942 /*EMPTY*/
7c3df132 1943 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1da177e4
LT		 1944 } else {
1945 if (name != NULL) {
1946 /* This function returns name in big endian. */
1196ae02
RL		 1947 name[0] = MSB(mcp->mb[2]);
1948 name[1] = LSB(mcp->mb[2]);
1949 name[2] = MSB(mcp->mb[3]);
1950 name[3] = LSB(mcp->mb[3]);
1951 name[4] = MSB(mcp->mb[6]);
1952 name[5] = LSB(mcp->mb[6]);
1953 name[6] = MSB(mcp->mb[7]);
1954 name[7] = LSB(mcp->mb[7]);
1da177e4
LT		 1955 }
1956
5f28d2d7
SK		 1957 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
1958 "Done %s.\n", __func__);
1da177e4
LT		 1959 }
1960
1961 return rval;
1962}
1963
61e1b269
JC		 1964/*
1965 * qla24xx_link_initialization
1966 * Issue link initialization mailbox command.
1967 *
1968 * Input:
1969 * ha = adapter block pointer.
1970 * TARGET_QUEUE_LOCK must be released.
1971 * ADAPTER_STATE_LOCK must be released.
1972 *
1973 * Returns:
1974 * qla2x00 local function return status code.
1975 *
1976 * Context:
1977 * Kernel context.
1978 */
1979int
1980qla24xx_link_initialize(scsi_qla_host_t *vha)
1981{
1982 int rval;
1983 mbx_cmd_t mc;
1984 mbx_cmd_t *mcp = &mc;
1985
1986 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
1987 "Entered %s.\n", __func__);
1988
1989 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
1990 return QLA_FUNCTION_FAILED;
1991
1992 mcp->mb[0] = MBC_LINK_INITIALIZATION;
5a5c27b6
JC		 1993 mcp->mb[1] = BIT_4;
1994 if (vha->hw->operating_mode == LOOP)
1995 mcp->mb[1] |= BIT_6;
1996 else
1997 mcp->mb[1] |= BIT_5;
61e1b269
JC		 1998 mcp->mb[2] = 0;
1999 mcp->mb[3] = 0;
2000 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2001 mcp->in_mb = MBX_0;
2002 mcp->tov = MBX_TOV_SECONDS;
2003 mcp->flags = 0;
2004 rval = qla2x00_mailbox_command(vha, mcp);
2005
2006 if (rval != QLA_SUCCESS) {
2007 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
2008 } else {
2009 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
2010 "Done %s.\n", __func__);
2011 }
2012
2013 return rval;
2014}
2015
1da177e4
LT		 2016/*
2017 * qla2x00_lip_reset
2018 * Issue LIP reset mailbox command.
2019 *
2020 * Input:
2021 * ha = adapter block pointer.
2022 * TARGET_QUEUE_LOCK must be released.
2023 * ADAPTER_STATE_LOCK must be released.
2024 *
2025 * Returns:
2026 * qla2x00 local function return status code.
2027 *
2028 * Context:
2029 * Kernel context.
2030 */
2031int
7b867cf7 2032qla2x00_lip_reset(scsi_qla_host_t *vha)
1da177e4
LT		 2033{
2034 int rval;
2035 mbx_cmd_t mc;
2036 mbx_cmd_t *mcp = &mc;
2037
5f28d2d7
SK		 2038 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
2039 "Entered %s.\n", __func__);
1da177e4 2040
6246b8a1 2041 if (IS_CNA_CAPABLE(vha->hw)) {
3a03eb79
AV		 2042 /* Logout across all FCFs. */
2043 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2044 mcp->mb[1] = BIT_1;
2045 mcp->mb[2] = 0;
2046 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2047 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 2048 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
0c8c39af
AV		 2049 mcp->mb[1] = BIT_6;
2050 mcp->mb[2] = 0;
7b867cf7 2051 mcp->mb[3] = vha->hw->loop_reset_delay;
1c7c6357 2052 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 2053 } else {
1c7c6357
AV		 2054 mcp->mb[0] = MBC_LIP_RESET;
2055 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 2056 if (HAS_EXTENDED_IDS(vha->hw)) {
1c7c6357
AV		 2057 mcp->mb[1] = 0x00ff;
2058 mcp->mb[10] = 0;
2059 mcp->out_mb |= MBX_10;
2060 } else {
2061 mcp->mb[1] = 0xff00;
2062 }
7b867cf7 2063 mcp->mb[2] = vha->hw->loop_reset_delay;
1c7c6357 2064 mcp->mb[3] = 0;
1da177e4 2065 }
1da177e4 2066 mcp->in_mb = MBX_0;
b93480e3 2067 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2068 mcp->flags = 0;
7b867cf7 2069 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2070
2071 if (rval != QLA_SUCCESS) {
2072 /*EMPTY*/
7c3df132 2073 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1da177e4
LT		 2074 } else {
2075 /*EMPTY*/
5f28d2d7
SK		 2076 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
2077 "Done %s.\n", __func__);
1da177e4
LT		 2078 }
2079
2080 return rval;
2081}
2082
2083/*
2084 * qla2x00_send_sns
2085 * Send SNS command.
2086 *
2087 * Input:
2088 * ha = adapter block pointer.
2089 * sns = pointer for command.
2090 * cmd_size = command size.
2091 * buf_size = response/command size.
2092 * TARGET_QUEUE_LOCK must be released.
2093 * ADAPTER_STATE_LOCK must be released.
2094 *
2095 * Returns:
2096 * qla2x00 local function return status code.
2097 *
2098 * Context:
2099 * Kernel context.
2100 */
2101int
7b867cf7 2102qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1da177e4
LT		 2103 uint16_t cmd_size, size_t buf_size)
2104{
2105 int rval;
2106 mbx_cmd_t mc;
2107 mbx_cmd_t *mcp = &mc;
2108
5f28d2d7
SK		 2109 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
2110 "Entered %s.\n", __func__);
1da177e4 2111
5f28d2d7 2112 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
7c3df132
SK		 2113 "Retry cnt=%d ratov=%d total tov=%d.\n",
2114 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1da177e4
LT		 2115
2116 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
2117 mcp->mb[1] = cmd_size;
2118 mcp->mb[2] = MSW(sns_phys_address);
2119 mcp->mb[3] = LSW(sns_phys_address);
2120 mcp->mb[6] = MSW(MSD(sns_phys_address));
2121 mcp->mb[7] = LSW(MSD(sns_phys_address));
2122 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2123 mcp->in_mb = MBX_0|MBX_1;
2124 mcp->buf_size = buf_size;
2125 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
7b867cf7
AC		 2126 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
2127 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2128
2129 if (rval != QLA_SUCCESS) {
2130 /*EMPTY*/
7c3df132
SK		 2131 ql_dbg(ql_dbg_mbx, vha, 0x105f,
2132 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2133 rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 2134 } else {
2135 /*EMPTY*/
5f28d2d7
SK		 2136 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
2137 "Done %s.\n", __func__);
1da177e4
LT		 2138 }
2139
2140 return rval;
2141}
2142
1c7c6357 2143int
7b867cf7 2144qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2145 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2146{
2147 int rval;
2148
2149 struct logio_entry_24xx *lg;
2150 dma_addr_t lg_dma;
2151 uint32_t iop[2];
7b867cf7 2152 struct qla_hw_data *ha = vha->hw;
2afa19a9 2153 struct req_que *req;
1c7c6357 2154
5f28d2d7
SK		 2155 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
2156 "Entered %s.\n", __func__);
1c7c6357 2157
d7459527
MH		 2158 if (vha->vp_idx && vha->qpair)
2159 req = vha->qpair->req;
68ca949c 2160 else
d7459527 2161 req = ha->req_q_map[0];
2afa19a9 2162
1c7c6357
AV		 2163 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2164 if (lg == NULL) {
7c3df132
SK		 2165 ql_log(ql_log_warn, vha, 0x1062,
2166 "Failed to allocate login IOCB.\n");
1c7c6357
AV		 2167 return QLA_MEMORY_ALLOC_FAILED;
2168 }
2169 memset(lg, 0, sizeof(struct logio_entry_24xx));
2170
2171 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2172 lg->entry_count = 1;
2afa19a9 2173 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357 2174 lg->nport_handle = cpu_to_le16(loop_id);
ad950360 2175 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
1c7c6357 2176 if (opt & BIT_0)
ad950360 2177 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
8baa51a6 2178 if (opt & BIT_1)
ad950360 2179 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
1c7c6357
AV		 2180 lg->port_id[0] = al_pa;
2181 lg->port_id[1] = area;
2182 lg->port_id[2] = domain;
7b867cf7 2183 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2184 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2185 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2186 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2187 ql_dbg(ql_dbg_mbx, vha, 0x1063,
2188 "Failed to issue login IOCB (%x).\n", rval);
1c7c6357 2189 } else if (lg->entry_status != 0) {
7c3df132
SK		 2190 ql_dbg(ql_dbg_mbx, vha, 0x1064,
2191 "Failed to complete IOCB -- error status (%x).\n",
2192 lg->entry_status);
1c7c6357 2193 rval = QLA_FUNCTION_FAILED;
ad950360 2194 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
1c7c6357
AV		 2195 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2196 iop[1] = le32_to_cpu(lg->io_parameter[1]);
2197
7c3df132
SK		 2198 ql_dbg(ql_dbg_mbx, vha, 0x1065,
2199 "Failed to complete IOCB -- completion status (%x) "
2200 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2201 iop[0], iop[1]);
1c7c6357
AV		 2202
2203 switch (iop[0]) {
2204 case LSC_SCODE_PORTID_USED:
2205 mb[0] = MBS_PORT_ID_USED;
2206 mb[1] = LSW(iop[1]);
2207 break;
2208 case LSC_SCODE_NPORT_USED:
2209 mb[0] = MBS_LOOP_ID_USED;
2210 break;
2211 case LSC_SCODE_NOLINK:
2212 case LSC_SCODE_NOIOCB:
2213 case LSC_SCODE_NOXCB:
2214 case LSC_SCODE_CMD_FAILED:
2215 case LSC_SCODE_NOFABRIC:
2216 case LSC_SCODE_FW_NOT_READY:
2217 case LSC_SCODE_NOT_LOGGED_IN:
2218 case LSC_SCODE_NOPCB:
2219 case LSC_SCODE_ELS_REJECT:
2220 case LSC_SCODE_CMD_PARAM_ERR:
2221 case LSC_SCODE_NONPORT:
2222 case LSC_SCODE_LOGGED_IN:
2223 case LSC_SCODE_NOFLOGI_ACC:
2224 default:
2225 mb[0] = MBS_COMMAND_ERROR;
2226 break;
2227 }
2228 } else {
5f28d2d7
SK		 2229 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
2230 "Done %s.\n", __func__);
1c7c6357
AV		 2231
2232 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2233
2234 mb[0] = MBS_COMMAND_COMPLETE;
2235 mb[1] = 0;
2236 if (iop[0] & BIT_4) {
2237 if (iop[0] & BIT_8)
2238 mb[1] |= BIT_1;
2239 } else
2240 mb[1] = BIT_0;
ad3e0eda
AV		 2241
2242 /* Passback COS information. */
2243 mb[10] = 0;
2244 if (lg->io_parameter[7] || lg->io_parameter[8])
2245 mb[10] |= BIT_0; /* Class 2. */
2246 if (lg->io_parameter[9] || lg->io_parameter[10])
2247 mb[10] |= BIT_1; /* Class 3. */
ad950360 2248 if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
2d70c103
NB		 2249 mb[10] |= BIT_7; /* Confirmed Completion
2250 * Allowed
2251 */
1c7c6357
AV		 2252 }
2253
2254 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2255
2256 return rval;
2257}
2258
1da177e4
LT		 2259/*
2260 * qla2x00_login_fabric
2261 * Issue login fabric port mailbox command.
2262 *
2263 * Input:
2264 * ha = adapter block pointer.
2265 * loop_id = device loop ID.
2266 * domain = device domain.
2267 * area = device area.
2268 * al_pa = device AL_PA.
2269 * status = pointer for return status.
2270 * opt = command options.
2271 * TARGET_QUEUE_LOCK must be released.
2272 * ADAPTER_STATE_LOCK must be released.
2273 *
2274 * Returns:
2275 * qla2x00 local function return status code.
2276 *
2277 * Context:
2278 * Kernel context.
2279 */
2280int
7b867cf7 2281qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1da177e4
LT		 2282 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2283{
2284 int rval;
2285 mbx_cmd_t mc;
2286 mbx_cmd_t *mcp = &mc;
7b867cf7 2287 struct qla_hw_data *ha = vha->hw;
1da177e4 2288
5f28d2d7
SK		 2289 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2290 "Entered %s.\n", __func__);
1da177e4
LT		 2291
2292 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2293 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2294 if (HAS_EXTENDED_IDS(ha)) {
2295 mcp->mb[1] = loop_id;
2296 mcp->mb[10] = opt;
2297 mcp->out_mb |= MBX_10;
2298 } else {
2299 mcp->mb[1] = (loop_id << 8) | opt;
2300 }
2301 mcp->mb[2] = domain;
2302 mcp->mb[3] = area << 8 | al_pa;
2303
2304 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2305 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2306 mcp->flags = 0;
7b867cf7 2307 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2308
2309 /* Return mailbox statuses. */
2310 if (mb != NULL) {
2311 mb[0] = mcp->mb[0];
2312 mb[1] = mcp->mb[1];
2313 mb[2] = mcp->mb[2];
2314 mb[6] = mcp->mb[6];
2315 mb[7] = mcp->mb[7];
ad3e0eda
AV		 2316 /* COS retrieved from Get-Port-Database mailbox command. */
2317 mb[10] = 0;
1da177e4
LT		 2318 }
2319
2320 if (rval != QLA_SUCCESS) {
2321 /* RLU tmp code: need to change main mailbox_command function to
2322 * return ok even when the mailbox completion value is not
2323 * SUCCESS. The caller needs to be responsible to interpret
2324 * the return values of this mailbox command if we're not
2325 * to change too much of the existing code.
2326 */
2327 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2328 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2329 mcp->mb[0] == 0x4006)
2330 rval = QLA_SUCCESS;
2331
2332 /*EMPTY*/
7c3df132
SK		 2333 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2334 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2335 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1da177e4
LT		 2336 } else {
2337 /*EMPTY*/
5f28d2d7
SK		 2338 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2339 "Done %s.\n", __func__);
1da177e4
LT		 2340 }
2341
2342 return rval;
2343}
2344
2345/*
2346 * qla2x00_login_local_device
2347 * Issue login loop port mailbox command.
fa2a1ce5 2348 *
1da177e4
LT		 2349 * Input:
2350 * ha = adapter block pointer.
2351 * loop_id = device loop ID.
2352 * opt = command options.
fa2a1ce5 2353 *
1da177e4
LT		 2354 * Returns:
2355 * Return status code.
fa2a1ce5 2356 *
1da177e4
LT		 2357 * Context:
2358 * Kernel context.
fa2a1ce5 2359 *
1da177e4
LT		 2360 */
2361int
7b867cf7 2362qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 2363 uint16_t *mb_ret, uint8_t opt)
2364{
2365 int rval;
2366 mbx_cmd_t mc;
2367 mbx_cmd_t *mcp = &mc;
7b867cf7 2368 struct qla_hw_data *ha = vha->hw;
1da177e4 2369
5f28d2d7
SK		 2370 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2371 "Entered %s.\n", __func__);
7c3df132 2372
e428924c 2373 if (IS_FWI2_CAPABLE(ha))
7b867cf7 2374 return qla24xx_login_fabric(vha, fcport->loop_id,
9a52a57c 2375 fcport->d_id.b.domain, fcport->d_id.b.area,
2376 fcport->d_id.b.al_pa, mb_ret, opt);
2377
1da177e4
LT		 2378 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2379 if (HAS_EXTENDED_IDS(ha))
9a52a57c 2380 mcp->mb[1] = fcport->loop_id;
1da177e4 2381 else
9a52a57c 2382 mcp->mb[1] = fcport->loop_id << 8;
1da177e4
LT		 2383 mcp->mb[2] = opt;
2384 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2385 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2386 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2387 mcp->flags = 0;
7b867cf7 2388 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2389
2390 /* Return mailbox statuses. */
2391 if (mb_ret != NULL) {
2392 mb_ret[0] = mcp->mb[0];
2393 mb_ret[1] = mcp->mb[1];
2394 mb_ret[6] = mcp->mb[6];
2395 mb_ret[7] = mcp->mb[7];
2396 }
2397
2398 if (rval != QLA_SUCCESS) {
2399 /* AV tmp code: need to change main mailbox_command function to
2400 * return ok even when the mailbox completion value is not
2401 * SUCCESS. The caller needs to be responsible to interpret
2402 * the return values of this mailbox command if we're not
2403 * to change too much of the existing code.
2404 */
2405 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2406 rval = QLA_SUCCESS;
2407
7c3df132
SK		 2408 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2409 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2410 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1da177e4
LT		 2411 } else {
2412 /*EMPTY*/
5f28d2d7
SK		 2413 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2414 "Done %s.\n", __func__);
1da177e4
LT		 2415 }
2416
2417 return (rval);
2418}
2419
1c7c6357 2420int
7b867cf7 2421qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2422 uint8_t area, uint8_t al_pa)
2423{
2424 int rval;
2425 struct logio_entry_24xx *lg;
2426 dma_addr_t lg_dma;
7b867cf7 2427 struct qla_hw_data *ha = vha->hw;
2afa19a9 2428 struct req_que *req;
1c7c6357 2429
5f28d2d7
SK		 2430 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2431 "Entered %s.\n", __func__);
1c7c6357
AV		 2432
2433 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2434 if (lg == NULL) {
7c3df132
SK		 2435 ql_log(ql_log_warn, vha, 0x106e,
2436 "Failed to allocate logout IOCB.\n");
1c7c6357
AV		 2437 return QLA_MEMORY_ALLOC_FAILED;
2438 }
2439 memset(lg, 0, sizeof(struct logio_entry_24xx));
2440
d7459527 2441 req = vha->req;
1c7c6357
AV		 2442 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2443 lg->entry_count = 1;
2afa19a9 2444 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 2445 lg->nport_handle = cpu_to_le16(loop_id);
2446 lg->control_flags =
ad950360 2447 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
c8d6691b 2448 LCF_FREE_NPORT);
1c7c6357
AV		 2449 lg->port_id[0] = al_pa;
2450 lg->port_id[1] = area;
2451 lg->port_id[2] = domain;
7b867cf7 2452 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2453 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2454 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2455 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2456 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2457 "Failed to issue logout IOCB (%x).\n", rval);
1c7c6357 2458 } else if (lg->entry_status != 0) {
7c3df132
SK		 2459 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2460 "Failed to complete IOCB -- error status (%x).\n",
2461 lg->entry_status);
1c7c6357 2462 rval = QLA_FUNCTION_FAILED;
ad950360 2463 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2464 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2465 "Failed to complete IOCB -- completion status (%x) "
2466 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1c7c6357 2467 le32_to_cpu(lg->io_parameter[0]),
7c3df132 2468 le32_to_cpu(lg->io_parameter[1]));
1c7c6357
AV		 2469 } else {
2470 /*EMPTY*/
5f28d2d7
SK		 2471 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2472 "Done %s.\n", __func__);
1c7c6357
AV		 2473 }
2474
2475 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2476
2477 return rval;
2478}
2479
1da177e4
LT		 2480/*
2481 * qla2x00_fabric_logout
2482 * Issue logout fabric port mailbox command.
2483 *
2484 * Input:
2485 * ha = adapter block pointer.
2486 * loop_id = device loop ID.
2487 * TARGET_QUEUE_LOCK must be released.
2488 * ADAPTER_STATE_LOCK must be released.
2489 *
2490 * Returns:
2491 * qla2x00 local function return status code.
2492 *
2493 * Context:
2494 * Kernel context.
2495 */
2496int
7b867cf7 2497qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357 2498 uint8_t area, uint8_t al_pa)
1da177e4
LT		 2499{
2500 int rval;
2501 mbx_cmd_t mc;
2502 mbx_cmd_t *mcp = &mc;
2503
5f28d2d7
SK		 2504 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2505 "Entered %s.\n", __func__);
1da177e4
LT		 2506
2507 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2508 mcp->out_mb = MBX_1|MBX_0;
7b867cf7 2509 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2510 mcp->mb[1] = loop_id;
2511 mcp->mb[10] = 0;
2512 mcp->out_mb |= MBX_10;
2513 } else {
2514 mcp->mb[1] = loop_id << 8;
2515 }
2516
2517 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2518 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2519 mcp->flags = 0;
7b867cf7 2520 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2521
2522 if (rval != QLA_SUCCESS) {
2523 /*EMPTY*/
7c3df132
SK		 2524 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2525 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1da177e4
LT		 2526 } else {
2527 /*EMPTY*/
5f28d2d7
SK		 2528 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2529 "Done %s.\n", __func__);
1da177e4
LT		 2530 }
2531
2532 return rval;
2533}
2534
2535/*
2536 * qla2x00_full_login_lip
2537 * Issue full login LIP mailbox command.
2538 *
2539 * Input:
2540 * ha = adapter block pointer.
2541 * TARGET_QUEUE_LOCK must be released.
2542 * ADAPTER_STATE_LOCK must be released.
2543 *
2544 * Returns:
2545 * qla2x00 local function return status code.
2546 *
2547 * Context:
2548 * Kernel context.
2549 */
2550int
7b867cf7 2551qla2x00_full_login_lip(scsi_qla_host_t *vha)
1da177e4
LT		 2552{
2553 int rval;
2554 mbx_cmd_t mc;
2555 mbx_cmd_t *mcp = &mc;
2556
5f28d2d7
SK		 2557 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2558 "Entered %s.\n", __func__);
1da177e4
LT		 2559
2560 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
7b867cf7 2561 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
0c8c39af 2562 mcp->mb[2] = 0;
1da177e4
LT		 2563 mcp->mb[3] = 0;
2564 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2565 mcp->in_mb = MBX_0;
b93480e3 2566 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2567 mcp->flags = 0;
7b867cf7 2568 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2569
2570 if (rval != QLA_SUCCESS) {
2571 /*EMPTY*/
7c3df132 2572 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
1da177e4
LT		 2573 } else {
2574 /*EMPTY*/
5f28d2d7
SK		 2575 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2576 "Done %s.\n", __func__);
1da177e4
LT		 2577 }
2578
2579 return rval;
2580}
2581
2582/*
2583 * qla2x00_get_id_list
2584 *
2585 * Input:
2586 * ha = adapter block pointer.
2587 *
2588 * Returns:
2589 * qla2x00 local function return status code.
2590 *
2591 * Context:
2592 * Kernel context.
2593 */
2594int
7b867cf7 2595qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
1da177e4
LT		 2596 uint16_t *entries)
2597{
2598 int rval;
2599 mbx_cmd_t mc;
2600 mbx_cmd_t *mcp = &mc;
2601
5f28d2d7
SK		 2602 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2603 "Entered %s.\n", __func__);
1da177e4
LT		 2604
2605 if (id_list == NULL)
2606 return QLA_FUNCTION_FAILED;
2607
2608 mcp->mb[0] = MBC_GET_ID_LIST;
1c7c6357 2609 mcp->out_mb = MBX_0;
7b867cf7 2610 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 2611 mcp->mb[2] = MSW(id_list_dma);
2612 mcp->mb[3] = LSW(id_list_dma);
2613 mcp->mb[6] = MSW(MSD(id_list_dma));
2614 mcp->mb[7] = LSW(MSD(id_list_dma));
247ec457 2615 mcp->mb[8] = 0;
7b867cf7 2616 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2617 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
1c7c6357
AV		 2618 } else {
2619 mcp->mb[1] = MSW(id_list_dma);
2620 mcp->mb[2] = LSW(id_list_dma);
2621 mcp->mb[3] = MSW(MSD(id_list_dma));
2622 mcp->mb[6] = LSW(MSD(id_list_dma));
2623 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2624 }
1da177e4 2625 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2626 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2627 mcp->flags = 0;
7b867cf7 2628 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2629
2630 if (rval != QLA_SUCCESS) {
2631 /*EMPTY*/
7c3df132 2632 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
1da177e4
LT		 2633 } else {
2634 *entries = mcp->mb[1];
5f28d2d7
SK		 2635 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2636 "Done %s.\n", __func__);
1da177e4
LT		 2637 }
2638
2639 return rval;
2640}
2641
2642/*
2643 * qla2x00_get_resource_cnts
2644 * Get current firmware resource counts.
2645 *
2646 * Input:
2647 * ha = adapter block pointer.
2648 *
2649 * Returns:
2650 * qla2x00 local function return status code.
2651 *
2652 * Context:
2653 * Kernel context.
2654 */
2655int
03e8c680 2656qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
1da177e4 2657{
03e8c680 2658 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2659 int rval;
2660 mbx_cmd_t mc;
2661 mbx_cmd_t *mcp = &mc;
2662
5f28d2d7
SK		 2663 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2664 "Entered %s.\n", __func__);
1da177e4
LT		 2665
2666 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2667 mcp->out_mb = MBX_0;
4d0ea247 2668 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
f73cb695 2669 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
f3a0a77e 2670 mcp->in_mb |= MBX_12;
b93480e3 2671 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2672 mcp->flags = 0;
7b867cf7 2673 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2674
2675 if (rval != QLA_SUCCESS) {
2676 /*EMPTY*/
7c3df132
SK		 2677 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2678 "Failed mb[0]=%x.\n", mcp->mb[0]);
1da177e4 2679 } else {
5f28d2d7 2680 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
7c3df132
SK		 2681 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2682 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2683 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2684 mcp->mb[11], mcp->mb[12]);
1da177e4 2685
03e8c680
QT		 2686 ha->orig_fw_tgt_xcb_count = mcp->mb[1];
2687 ha->cur_fw_tgt_xcb_count = mcp->mb[2];
2688 ha->cur_fw_xcb_count = mcp->mb[3];
2689 ha->orig_fw_xcb_count = mcp->mb[6];
2690 ha->cur_fw_iocb_count = mcp->mb[7];
2691 ha->orig_fw_iocb_count = mcp->mb[10];
2692 if (ha->flags.npiv_supported)
2693 ha->max_npiv_vports = mcp->mb[11];
2694 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
2695 ha->fw_max_fcf_count = mcp->mb[12];
1da177e4
LT		 2696 }
2697
2698 return (rval);
2699}
2700
1da177e4
LT		 2701/*
2702 * qla2x00_get_fcal_position_map
2703 * Get FCAL (LILP) position map using mailbox command
2704 *
2705 * Input:
2706 * ha = adapter state pointer.
2707 * pos_map = buffer pointer (can be NULL).
2708 *
2709 * Returns:
2710 * qla2x00 local function return status code.
2711 *
2712 * Context:
2713 * Kernel context.
2714 */
2715int
7b867cf7 2716qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
1da177e4
LT		 2717{
2718 int rval;
2719 mbx_cmd_t mc;
2720 mbx_cmd_t *mcp = &mc;
2721 char *pmap;
2722 dma_addr_t pmap_dma;
7b867cf7 2723 struct qla_hw_data *ha = vha->hw;
1da177e4 2724
5f28d2d7
SK		 2725 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2726 "Entered %s.\n", __func__);
7c3df132 2727
4b89258c 2728 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
1da177e4 2729 if (pmap == NULL) {
7c3df132
SK		 2730 ql_log(ql_log_warn, vha, 0x1080,
2731 "Memory alloc failed.\n");
1da177e4
LT		 2732 return QLA_MEMORY_ALLOC_FAILED;
2733 }
2734 memset(pmap, 0, FCAL_MAP_SIZE);
2735
2736 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2737 mcp->mb[2] = MSW(pmap_dma);
2738 mcp->mb[3] = LSW(pmap_dma);
2739 mcp->mb[6] = MSW(MSD(pmap_dma));
2740 mcp->mb[7] = LSW(MSD(pmap_dma));
2741 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2742 mcp->in_mb = MBX_1|MBX_0;
2743 mcp->buf_size = FCAL_MAP_SIZE;
2744 mcp->flags = MBX_DMA_IN;
2745 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 2746 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2747
2748 if (rval == QLA_SUCCESS) {
5f28d2d7 2749 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
7c3df132
SK		 2750 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2751 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2752 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2753 pmap, pmap[0] + 1);
1da177e4
LT		 2754
2755 if (pos_map)
2756 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2757 }
2758 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2759
2760 if (rval != QLA_SUCCESS) {
7c3df132 2761 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
1da177e4 2762 } else {
5f28d2d7
SK		 2763 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2764 "Done %s.\n", __func__);
1da177e4
LT		 2765 }
2766
2767 return rval;
2768}
392e2f65 2769
2770/*
2771 * qla2x00_get_link_status
2772 *
2773 * Input:
2774 * ha = adapter block pointer.
2775 * loop_id = device loop ID.
2776 * ret_buf = pointer to link status return buffer.
2777 *
2778 * Returns:
2779 * 0 = success.
2780 * BIT_0 = mem alloc error.
2781 * BIT_1 = mailbox error.
2782 */
2783int
7b867cf7 2784qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
43ef0580 2785 struct link_statistics *stats, dma_addr_t stats_dma)
392e2f65 2786{
2787 int rval;
2788 mbx_cmd_t mc;
2789 mbx_cmd_t *mcp = &mc;
c6dc9905
JC		 2790 uint32_t *iter = (void *)stats;
2791 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
7b867cf7 2792 struct qla_hw_data *ha = vha->hw;
392e2f65 2793
5f28d2d7
SK		 2794 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2795 "Entered %s.\n", __func__);
392e2f65 2796
392e2f65 2797 mcp->mb[0] = MBC_GET_LINK_STATUS;
c6dc9905
JC		 2798 mcp->mb[2] = MSW(LSD(stats_dma));
2799 mcp->mb[3] = LSW(LSD(stats_dma));
43ef0580
AV		 2800 mcp->mb[6] = MSW(MSD(stats_dma));
2801 mcp->mb[7] = LSW(MSD(stats_dma));
392e2f65 2802 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2803 mcp->in_mb = MBX_0;
e428924c 2804 if (IS_FWI2_CAPABLE(ha)) {
392e2f65 2805 mcp->mb[1] = loop_id;
2806 mcp->mb[4] = 0;
2807 mcp->mb[10] = 0;
2808 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2809 mcp->in_mb |= MBX_1;
2810 } else if (HAS_EXTENDED_IDS(ha)) {
2811 mcp->mb[1] = loop_id;
2812 mcp->mb[10] = 0;
2813 mcp->out_mb |= MBX_10|MBX_1;
2814 } else {
2815 mcp->mb[1] = loop_id << 8;
2816 mcp->out_mb |= MBX_1;
2817 }
b93480e3 2818 mcp->tov = MBX_TOV_SECONDS;
392e2f65 2819 mcp->flags = IOCTL_CMD;
7b867cf7 2820 rval = qla2x00_mailbox_command(vha, mcp);
392e2f65 2821
2822 if (rval == QLA_SUCCESS) {
2823 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2824 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2825 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
43ef0580 2826 rval = QLA_FUNCTION_FAILED;
392e2f65 2827 } else {
c6dc9905 2828 /* Re-endianize - firmware data is le32. */
5f28d2d7
SK		 2829 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
2830 "Done %s.\n", __func__);
da08ef5c
JC		 2831 for ( ; dwords--; iter++)
2832 le32_to_cpus(iter);
392e2f65 2833 }
2834 } else {
2835 /* Failed. */
7c3df132 2836 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
392e2f65 2837 }
2838
392e2f65 2839 return rval;
2840}
2841
2842int
7b867cf7 2843qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
15f30a57 2844 dma_addr_t stats_dma, uint16_t options)
1c7c6357
AV		 2845{
2846 int rval;
2847 mbx_cmd_t mc;
2848 mbx_cmd_t *mcp = &mc;
da08ef5c 2849 uint32_t *iter, dwords;
1c7c6357 2850
5f28d2d7
SK		 2851 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2852 "Entered %s.\n", __func__);
1c7c6357 2853
15f30a57
QT		 2854 memset(&mc, 0, sizeof(mc));
2855 mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
2856 mc.mb[2] = MSW(stats_dma);
2857 mc.mb[3] = LSW(stats_dma);
2858 mc.mb[6] = MSW(MSD(stats_dma));
2859 mc.mb[7] = LSW(MSD(stats_dma));
2860 mc.mb[8] = sizeof(struct link_statistics) / 4;
2861 mc.mb[9] = cpu_to_le16(vha->vp_idx);
2862 mc.mb[10] = cpu_to_le16(options);
2863
2864 rval = qla24xx_send_mb_cmd(vha, &mc);
1c7c6357
AV		 2865
2866 if (rval == QLA_SUCCESS) {
2867 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2868 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2869 "Failed mb[0]=%x.\n", mcp->mb[0]);
43ef0580 2870 rval = QLA_FUNCTION_FAILED;
1c7c6357 2871 } else {
5f28d2d7
SK		 2872 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
2873 "Done %s.\n", __func__);
c6dc9905 2874 /* Re-endianize - firmware data is le32. */
43ef0580 2875 dwords = sizeof(struct link_statistics) / 4;
da08ef5c
JC		 2876 iter = &stats->link_fail_cnt;
2877 for ( ; dwords--; iter++)
2878 le32_to_cpus(iter);
1c7c6357
AV		 2879 }
2880 } else {
2881 /* Failed. */
7c3df132 2882 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
1c7c6357
AV		 2883 }
2884
1c7c6357
AV		 2885 return rval;
2886}
1c7c6357
AV		 2887
2888int
2afa19a9 2889qla24xx_abort_command(srb_t *sp)
1c7c6357
AV		 2890{
2891 int rval;
1c7c6357
AV		 2892 unsigned long flags = 0;
2893
2894 struct abort_entry_24xx *abt;
2895 dma_addr_t abt_dma;
2896 uint32_t handle;
2afa19a9
AC		 2897 fc_port_t *fcport = sp->fcport;
2898 struct scsi_qla_host *vha = fcport->vha;
7b867cf7 2899 struct qla_hw_data *ha = vha->hw;
67c2e93a 2900 struct req_que *req = vha->req;
1c7c6357 2901
5f28d2d7
SK		 2902 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
2903 "Entered %s.\n", __func__);
1c7c6357 2904
d7459527
MH		 2905 if (vha->flags.qpairs_available && sp->qpair)
2906 req = sp->qpair->req;
2907
4440e46d
AB		 2908 if (ql2xasynctmfenable)
2909 return qla24xx_async_abort_command(sp);
2910
7b867cf7 2911 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 2912 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 2913 if (req->outstanding_cmds[handle] == sp)
1c7c6357
AV		 2914 break;
2915 }
7b867cf7 2916 spin_unlock_irqrestore(&ha->hardware_lock, flags);
8d93f550 2917 if (handle == req->num_outstanding_cmds) {
1c7c6357
AV		 2918 /* Command not found. */
2919 return QLA_FUNCTION_FAILED;
2920 }
2921
2922 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2923 if (abt == NULL) {
7c3df132
SK		 2924 ql_log(ql_log_warn, vha, 0x108d,
2925 "Failed to allocate abort IOCB.\n");
1c7c6357
AV		 2926 return QLA_MEMORY_ALLOC_FAILED;
2927 }
2928 memset(abt, 0, sizeof(struct abort_entry_24xx));
2929
2930 abt->entry_type = ABORT_IOCB_TYPE;
2931 abt->entry_count = 1;
2afa19a9 2932 abt->handle = MAKE_HANDLE(req->id, abt->handle);
1c7c6357 2933 abt->nport_handle = cpu_to_le16(fcport->loop_id);
a74ec14f 2934 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
1c7c6357
AV		 2935 abt->port_id[0] = fcport->d_id.b.al_pa;
2936 abt->port_id[1] = fcport->d_id.b.area;
2937 abt->port_id[2] = fcport->d_id.b.domain;
c6d39e23 2938 abt->vp_index = fcport->vha->vp_idx;
73208dfd
AC		 2939
2940 abt->req_que_no = cpu_to_le16(req->id);
2941
7b867cf7 2942 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
1c7c6357 2943 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2944 ql_dbg(ql_dbg_mbx, vha, 0x108e,
2945 "Failed to issue IOCB (%x).\n", rval);
1c7c6357 2946 } else if (abt->entry_status != 0) {
7c3df132
SK		 2947 ql_dbg(ql_dbg_mbx, vha, 0x108f,
2948 "Failed to complete IOCB -- error status (%x).\n",
2949 abt->entry_status);
1c7c6357 2950 rval = QLA_FUNCTION_FAILED;
ad950360 2951 } else if (abt->nport_handle != cpu_to_le16(0)) {
7c3df132
SK		 2952 ql_dbg(ql_dbg_mbx, vha, 0x1090,
2953 "Failed to complete IOCB -- completion status (%x).\n",
2954 le16_to_cpu(abt->nport_handle));
f934c9d0
CD		 2955 if (abt->nport_handle == CS_IOCB_ERROR)
2956 rval = QLA_FUNCTION_PARAMETER_ERROR;
2957 else
2958 rval = QLA_FUNCTION_FAILED;
1c7c6357 2959 } else {
5f28d2d7
SK		 2960 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
2961 "Done %s.\n", __func__);
1c7c6357
AV		 2962 }
2963
2964 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
2965
2966 return rval;
2967}
2968
2969struct tsk_mgmt_cmd {
2970 union {
2971 struct tsk_mgmt_entry tsk;
2972 struct sts_entry_24xx sts;
2973 } p;
2974};
2975
523ec773
AV		 2976static int
2977__qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
9cb78c16 2978 uint64_t l, int tag)
1c7c6357 2979{
523ec773 2980 int rval, rval2;
1c7c6357 2981 struct tsk_mgmt_cmd *tsk;
9ca1d01f 2982 struct sts_entry_24xx *sts;
1c7c6357 2983 dma_addr_t tsk_dma;
7b867cf7
AC		 2984 scsi_qla_host_t *vha;
2985 struct qla_hw_data *ha;
73208dfd
AC		 2986 struct req_que *req;
2987 struct rsp_que *rsp;
d7459527 2988 struct qla_qpair *qpair;
1c7c6357 2989
7b867cf7
AC		 2990 vha = fcport->vha;
2991 ha = vha->hw;
2afa19a9 2992 req = vha->req;
7c3df132 2993
5f28d2d7
SK		 2994 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
2995 "Entered %s.\n", __func__);
7c3df132 2996
d7459527
MH		 2997 if (vha->vp_idx && vha->qpair) {
2998 /* NPIV port */
2999 qpair = vha->qpair;
3000 rsp = qpair->rsp;
3001 req = qpair->req;
3002 } else {
68ca949c 3003 rsp = req->rsp;
d7459527
MH		 3004 }
3005
7b867cf7 3006 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
1c7c6357 3007 if (tsk == NULL) {
7c3df132
SK		 3008 ql_log(ql_log_warn, vha, 0x1093,
3009 "Failed to allocate task management IOCB.\n");
1c7c6357
AV		 3010 return QLA_MEMORY_ALLOC_FAILED;
3011 }
3012 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
3013
3014 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3015 tsk->p.tsk.entry_count = 1;
2afa19a9 3016 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
1c7c6357 3017 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
00a537b8 3018 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
523ec773 3019 tsk->p.tsk.control_flags = cpu_to_le32(type);
1c7c6357
AV		 3020 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
3021 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
3022 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
c6d39e23 3023 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
523ec773
AV		 3024 if (type == TCF_LUN_RESET) {
3025 int_to_scsilun(l, &tsk->p.tsk.lun);
3026 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
3027 sizeof(tsk->p.tsk.lun));
3028 }
2c3dfe3f 3029
9ca1d01f 3030 sts = &tsk->p.sts;
7b867cf7 3031 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
1c7c6357 3032 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3033 ql_dbg(ql_dbg_mbx, vha, 0x1094,
3034 "Failed to issue %s reset IOCB (%x).\n", name, rval);
9ca1d01f 3035 } else if (sts->entry_status != 0) {
7c3df132
SK		 3036 ql_dbg(ql_dbg_mbx, vha, 0x1095,
3037 "Failed to complete IOCB -- error status (%x).\n",
3038 sts->entry_status);
1c7c6357 3039 rval = QLA_FUNCTION_FAILED;
ad950360 3040 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3041 ql_dbg(ql_dbg_mbx, vha, 0x1096,
3042 "Failed to complete IOCB -- completion status (%x).\n",
3043 le16_to_cpu(sts->comp_status));
9ca1d01f 3044 rval = QLA_FUNCTION_FAILED;
97dec564
AV		 3045 } else if (le16_to_cpu(sts->scsi_status) &
3046 SS_RESPONSE_INFO_LEN_VALID) {
3047 if (le32_to_cpu(sts->rsp_data_len) < 4) {
5f28d2d7 3048 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
7c3df132
SK		 3049 "Ignoring inconsistent data length -- not enough "
3050 "response info (%d).\n",
3051 le32_to_cpu(sts->rsp_data_len));
97dec564 3052 } else if (sts->data[3]) {
7c3df132
SK		 3053 ql_dbg(ql_dbg_mbx, vha, 0x1098,
3054 "Failed to complete IOCB -- response (%x).\n",
3055 sts->data[3]);
97dec564
AV		 3056 rval = QLA_FUNCTION_FAILED;
3057 }
1c7c6357
AV		 3058 }
3059
3060 /* Issue marker IOCB. */
73208dfd 3061 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
523ec773
AV		 3062 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
3063 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3064 ql_dbg(ql_dbg_mbx, vha, 0x1099,
3065 "Failed to issue marker IOCB (%x).\n", rval2);
1c7c6357 3066 } else {
5f28d2d7
SK		 3067 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
3068 "Done %s.\n", __func__);
1c7c6357
AV		 3069 }
3070
7b867cf7 3071 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
1c7c6357
AV		 3072
3073 return rval;
3074}
3075
523ec773 3076int
9cb78c16 3077qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3078{
3822263e
MI		 3079 struct qla_hw_data *ha = fcport->vha->hw;
3080
3081 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3082 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
3083
2afa19a9 3084 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
523ec773
AV		 3085}
3086
3087int
9cb78c16 3088qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3089{
3822263e
MI		 3090 struct qla_hw_data *ha = fcport->vha->hw;
3091
3092 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3093 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
3094
2afa19a9 3095 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
523ec773
AV		 3096}
3097
1c7c6357 3098int
7b867cf7 3099qla2x00_system_error(scsi_qla_host_t *vha)
1c7c6357
AV		 3100{
3101 int rval;
3102 mbx_cmd_t mc;
3103 mbx_cmd_t *mcp = &mc;
7b867cf7 3104 struct qla_hw_data *ha = vha->hw;
1c7c6357 3105
68af0811 3106 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 3107 return QLA_FUNCTION_FAILED;
3108
5f28d2d7
SK		 3109 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
3110 "Entered %s.\n", __func__);
1c7c6357
AV		 3111
3112 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
3113 mcp->out_mb = MBX_0;
3114 mcp->in_mb = MBX_0;
3115 mcp->tov = 5;
3116 mcp->flags = 0;
7b867cf7 3117 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3118
3119 if (rval != QLA_SUCCESS) {
7c3df132 3120 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
1c7c6357 3121 } else {
5f28d2d7
SK		 3122 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
3123 "Done %s.\n", __func__);
1c7c6357
AV		 3124 }
3125
3126 return rval;
3127}
3128
db64e930
JC		 3129int
3130qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
3131{
3132 int rval;
3133 mbx_cmd_t mc;
3134 mbx_cmd_t *mcp = &mc;
3135
f299c7c2
JC		 3136 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3137 !IS_QLA27XX(vha->hw))
db64e930
JC		 3138 return QLA_FUNCTION_FAILED;
3139
3140 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
3141 "Entered %s.\n", __func__);
3142
3143 mcp->mb[0] = MBC_WRITE_SERDES;
3144 mcp->mb[1] = addr;
064135e0
AV		 3145 if (IS_QLA2031(vha->hw))
3146 mcp->mb[2] = data & 0xff;
3147 else
3148 mcp->mb[2] = data;
3149
db64e930
JC		 3150 mcp->mb[3] = 0;
3151 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
3152 mcp->in_mb = MBX_0;
3153 mcp->tov = MBX_TOV_SECONDS;
3154 mcp->flags = 0;
3155 rval = qla2x00_mailbox_command(vha, mcp);
3156
3157 if (rval != QLA_SUCCESS) {
3158 ql_dbg(ql_dbg_mbx, vha, 0x1183,
3159 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3160 } else {
3161 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
3162 "Done %s.\n", __func__);
3163 }
3164
3165 return rval;
3166}
3167
3168int
3169qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
3170{
3171 int rval;
3172 mbx_cmd_t mc;
3173 mbx_cmd_t *mcp = &mc;
3174
f299c7c2
JC		 3175 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3176 !IS_QLA27XX(vha->hw))
db64e930
JC		 3177 return QLA_FUNCTION_FAILED;
3178
3179 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
3180 "Entered %s.\n", __func__);
3181
3182 mcp->mb[0] = MBC_READ_SERDES;
3183 mcp->mb[1] = addr;
3184 mcp->mb[3] = 0;
3185 mcp->out_mb = MBX_3|MBX_1|MBX_0;
3186 mcp->in_mb = MBX_1|MBX_0;
3187 mcp->tov = MBX_TOV_SECONDS;
3188 mcp->flags = 0;
3189 rval = qla2x00_mailbox_command(vha, mcp);
3190
064135e0
AV		 3191 if (IS_QLA2031(vha->hw))
3192 *data = mcp->mb[1] & 0xff;
3193 else
3194 *data = mcp->mb[1];
db64e930
JC		 3195
3196 if (rval != QLA_SUCCESS) {
3197 ql_dbg(ql_dbg_mbx, vha, 0x1186,
3198 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3199 } else {
3200 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
3201 "Done %s.\n", __func__);
3202 }
3203
3204 return rval;
3205}
3206
e8887c51
JC		 3207int
3208qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
3209{
3210 int rval;
3211 mbx_cmd_t mc;
3212 mbx_cmd_t *mcp = &mc;
3213
3214 if (!IS_QLA8044(vha->hw))
3215 return QLA_FUNCTION_FAILED;
3216
83548fe2 3217 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0,
e8887c51
JC		 3218 "Entered %s.\n", __func__);
3219
3220 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3221 mcp->mb[1] = HCS_WRITE_SERDES;
3222 mcp->mb[3] = LSW(addr);
3223 mcp->mb[4] = MSW(addr);
3224 mcp->mb[5] = LSW(data);
3225 mcp->mb[6] = MSW(data);
3226 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
3227 mcp->in_mb = MBX_0;
3228 mcp->tov = MBX_TOV_SECONDS;
3229 mcp->flags = 0;
3230 rval = qla2x00_mailbox_command(vha, mcp);
3231
3232 if (rval != QLA_SUCCESS) {
83548fe2 3233 ql_dbg(ql_dbg_mbx, vha, 0x11a1,
e8887c51
JC		 3234 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3235 } else {
3236 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
3237 "Done %s.\n", __func__);
3238 }
3239
3240 return rval;
3241}
3242
3243int
3244qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
3245{
3246 int rval;
3247 mbx_cmd_t mc;
3248 mbx_cmd_t *mcp = &mc;
3249
3250 if (!IS_QLA8044(vha->hw))
3251 return QLA_FUNCTION_FAILED;
3252
3253 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
3254 "Entered %s.\n", __func__);
3255
3256 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3257 mcp->mb[1] = HCS_READ_SERDES;
3258 mcp->mb[3] = LSW(addr);
3259 mcp->mb[4] = MSW(addr);
3260 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
3261 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3262 mcp->tov = MBX_TOV_SECONDS;
3263 mcp->flags = 0;
3264 rval = qla2x00_mailbox_command(vha, mcp);
3265
3266 *data = mcp->mb[2] << 16 | mcp->mb[1];
3267
3268 if (rval != QLA_SUCCESS) {
3269 ql_dbg(ql_dbg_mbx, vha, 0x118a,
3270 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3271 } else {
3272 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
3273 "Done %s.\n", __func__);
3274 }
3275
3276 return rval;
3277}
3278
1c7c6357
AV		 3279/**
3280 * qla2x00_set_serdes_params() -
3281 * @ha: HA context
3282 *
3283 * Returns
3284 */
3285int
7b867cf7 3286qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
1c7c6357
AV		 3287 uint16_t sw_em_2g, uint16_t sw_em_4g)
3288{
3289 int rval;
3290 mbx_cmd_t mc;
3291 mbx_cmd_t *mcp = &mc;
3292
5f28d2d7
SK		 3293 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3294 "Entered %s.\n", __func__);
1c7c6357
AV		 3295
3296 mcp->mb[0] = MBC_SERDES_PARAMS;
3297 mcp->mb[1] = BIT_0;
fdbc6833 3298 mcp->mb[2] = sw_em_1g | BIT_15;
3299 mcp->mb[3] = sw_em_2g | BIT_15;
3300 mcp->mb[4] = sw_em_4g | BIT_15;
1c7c6357
AV		 3301 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3302 mcp->in_mb = MBX_0;
b93480e3 3303 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 3304 mcp->flags = 0;
7b867cf7 3305 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3306
3307 if (rval != QLA_SUCCESS) {
3308 /*EMPTY*/
7c3df132
SK		 3309 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3310 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357
AV		 3311 } else {
3312 /*EMPTY*/
5f28d2d7
SK		 3313 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3314 "Done %s.\n", __func__);
1c7c6357
AV		 3315 }
3316
3317 return rval;
3318}
f6ef3b18
AV		 3319
3320int
7b867cf7 3321qla2x00_stop_firmware(scsi_qla_host_t *vha)
f6ef3b18
AV		 3322{
3323 int rval;
3324 mbx_cmd_t mc;
3325 mbx_cmd_t *mcp = &mc;
3326
7b867cf7 3327 if (!IS_FWI2_CAPABLE(vha->hw))
f6ef3b18
AV		 3328 return QLA_FUNCTION_FAILED;
3329
5f28d2d7
SK		 3330 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3331 "Entered %s.\n", __func__);
f6ef3b18
AV		 3332
3333 mcp->mb[0] = MBC_STOP_FIRMWARE;
4ba988db
AV		 3334 mcp->mb[1] = 0;
3335 mcp->out_mb = MBX_1|MBX_0;
f6ef3b18
AV		 3336 mcp->in_mb = MBX_0;
3337 mcp->tov = 5;
3338 mcp->flags = 0;
7b867cf7 3339 rval = qla2x00_mailbox_command(vha, mcp);
f6ef3b18
AV		 3340
3341 if (rval != QLA_SUCCESS) {
7c3df132 3342 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
b469a7cb
AV		 3343 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3344 rval = QLA_INVALID_COMMAND;
f6ef3b18 3345 } else {
5f28d2d7
SK		 3346 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3347 "Done %s.\n", __func__);
f6ef3b18
AV		 3348 }
3349
3350 return rval;
3351}
a7a167bf
AV		 3352
3353int
7b867cf7 3354qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
a7a167bf
AV		 3355 uint16_t buffers)
3356{
3357 int rval;
3358 mbx_cmd_t mc;
3359 mbx_cmd_t *mcp = &mc;
3360
5f28d2d7
SK		 3361 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3362 "Entered %s.\n", __func__);
7c3df132 3363
7b867cf7 3364 if (!IS_FWI2_CAPABLE(vha->hw))
a7a167bf
AV		 3365 return QLA_FUNCTION_FAILED;
3366
85880801
AV		 3367 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3368 return QLA_FUNCTION_FAILED;
3369
a7a167bf 3370 mcp->mb[0] = MBC_TRACE_CONTROL;
00b6bd25
AV		 3371 mcp->mb[1] = TC_EFT_ENABLE;
3372 mcp->mb[2] = LSW(eft_dma);
3373 mcp->mb[3] = MSW(eft_dma);
3374 mcp->mb[4] = LSW(MSD(eft_dma));
3375 mcp->mb[5] = MSW(MSD(eft_dma));
3376 mcp->mb[6] = buffers;
3377 mcp->mb[7] = TC_AEN_DISABLE;
3378 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
a7a167bf 3379 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3380 mcp->tov = MBX_TOV_SECONDS;
a7a167bf 3381 mcp->flags = 0;
7b867cf7 3382 rval = qla2x00_mailbox_command(vha, mcp);
00b6bd25 3383 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3384 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3385 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3386 rval, mcp->mb[0], mcp->mb[1]);
00b6bd25 3387 } else {
5f28d2d7
SK		 3388 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3389 "Done %s.\n", __func__);
00b6bd25
AV		 3390 }
3391
3392 return rval;
3393}
a7a167bf 3394
00b6bd25 3395int
7b867cf7 3396qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
00b6bd25
AV		 3397{
3398 int rval;
3399 mbx_cmd_t mc;
3400 mbx_cmd_t *mcp = &mc;
3401
5f28d2d7
SK		 3402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3403 "Entered %s.\n", __func__);
7c3df132 3404
7b867cf7 3405 if (!IS_FWI2_CAPABLE(vha->hw))
00b6bd25
AV		 3406 return QLA_FUNCTION_FAILED;
3407
85880801
AV		 3408 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3409 return QLA_FUNCTION_FAILED;
3410
00b6bd25
AV		 3411 mcp->mb[0] = MBC_TRACE_CONTROL;
3412 mcp->mb[1] = TC_EFT_DISABLE;
3413 mcp->out_mb = MBX_1|MBX_0;
3414 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3415 mcp->tov = MBX_TOV_SECONDS;
00b6bd25 3416 mcp->flags = 0;
7b867cf7 3417 rval = qla2x00_mailbox_command(vha, mcp);
a7a167bf 3418 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3419 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3420 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3421 rval, mcp->mb[0], mcp->mb[1]);
a7a167bf 3422 } else {
5f28d2d7
SK		 3423 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3424 "Done %s.\n", __func__);
a7a167bf
AV		 3425 }
3426
3427 return rval;
3428}
3429
df613b96 3430int
7b867cf7 3431qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
df613b96
AV		 3432 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3433{
3434 int rval;
3435 mbx_cmd_t mc;
3436 mbx_cmd_t *mcp = &mc;
3437
5f28d2d7
SK		 3438 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3439 "Entered %s.\n", __func__);
7c3df132 3440
6246b8a1 3441 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
f73cb695 3442 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
df613b96
AV		 3443 return QLA_FUNCTION_FAILED;
3444
85880801
AV		 3445 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3446 return QLA_FUNCTION_FAILED;
3447
df613b96
AV		 3448 mcp->mb[0] = MBC_TRACE_CONTROL;
3449 mcp->mb[1] = TC_FCE_ENABLE;
3450 mcp->mb[2] = LSW(fce_dma);
3451 mcp->mb[3] = MSW(fce_dma);
3452 mcp->mb[4] = LSW(MSD(fce_dma));
3453 mcp->mb[5] = MSW(MSD(fce_dma));
3454 mcp->mb[6] = buffers;
3455 mcp->mb[7] = TC_AEN_DISABLE;
3456 mcp->mb[8] = 0;
3457 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3458 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3459 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3460 MBX_1|MBX_0;
3461 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 3462 mcp->tov = MBX_TOV_SECONDS;
df613b96 3463 mcp->flags = 0;
7b867cf7 3464 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3465 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3466 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3467 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3468 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3469 } else {
5f28d2d7
SK		 3470 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3471 "Done %s.\n", __func__);
df613b96
AV		 3472
3473 if (mb)
3474 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3475 if (dwords)
fa0926df 3476 *dwords = buffers;
df613b96
AV		 3477 }
3478
3479 return rval;
3480}
3481
3482int
7b867cf7 3483qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
df613b96
AV		 3484{
3485 int rval;
3486 mbx_cmd_t mc;
3487 mbx_cmd_t *mcp = &mc;
3488
5f28d2d7
SK		 3489 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3490 "Entered %s.\n", __func__);
7c3df132 3491
7b867cf7 3492 if (!IS_FWI2_CAPABLE(vha->hw))
df613b96
AV		 3493 return QLA_FUNCTION_FAILED;
3494
85880801
AV		 3495 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3496 return QLA_FUNCTION_FAILED;
3497
df613b96
AV		 3498 mcp->mb[0] = MBC_TRACE_CONTROL;
3499 mcp->mb[1] = TC_FCE_DISABLE;
3500 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3501 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3502 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3503 MBX_1|MBX_0;
b93480e3 3504 mcp->tov = MBX_TOV_SECONDS;
df613b96 3505 mcp->flags = 0;
7b867cf7 3506 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3507 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3508 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3509 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3510 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3511 } else {
5f28d2d7
SK		 3512 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3513 "Done %s.\n", __func__);
df613b96
AV		 3514
3515 if (wr)
3516 *wr = (uint64_t) mcp->mb[5] << 48 |
3517 (uint64_t) mcp->mb[4] << 32 |
3518 (uint64_t) mcp->mb[3] << 16 |
3519 (uint64_t) mcp->mb[2];
3520 if (rd)
3521 *rd = (uint64_t) mcp->mb[9] << 48 |
3522 (uint64_t) mcp->mb[8] << 32 |
3523 (uint64_t) mcp->mb[7] << 16 |
3524 (uint64_t) mcp->mb[6];
3525 }
3526
3527 return rval;
3528}
3529
6e98016c
GM		 3530int
3531qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3532 uint16_t *port_speed, uint16_t *mb)
3533{
3534 int rval;
3535 mbx_cmd_t mc;
3536 mbx_cmd_t *mcp = &mc;
3537
5f28d2d7
SK		 3538 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3539 "Entered %s.\n", __func__);
7c3df132 3540
6e98016c
GM		 3541 if (!IS_IIDMA_CAPABLE(vha->hw))
3542 return QLA_FUNCTION_FAILED;
3543
6e98016c
GM		 3544 mcp->mb[0] = MBC_PORT_PARAMS;
3545 mcp->mb[1] = loop_id;
3546 mcp->mb[2] = mcp->mb[3] = 0;
3547 mcp->mb[9] = vha->vp_idx;
3548 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3549 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3550 mcp->tov = MBX_TOV_SECONDS;
3551 mcp->flags = 0;
3552 rval = qla2x00_mailbox_command(vha, mcp);
3553
3554 /* Return mailbox statuses. */
3555 if (mb != NULL) {
3556 mb[0] = mcp->mb[0];
3557 mb[1] = mcp->mb[1];
3558 mb[3] = mcp->mb[3];
3559 }
3560
3561 if (rval != QLA_SUCCESS) {
7c3df132 3562 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
6e98016c 3563 } else {
5f28d2d7
SK		 3564 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3565 "Done %s.\n", __func__);
6e98016c
GM		 3566 if (port_speed)
3567 *port_speed = mcp->mb[3];
3568 }
3569
3570 return rval;
3571}
3572
d8b45213 3573int
7b867cf7 3574qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
d8b45213
AV		 3575 uint16_t port_speed, uint16_t *mb)
3576{
3577 int rval;
3578 mbx_cmd_t mc;
3579 mbx_cmd_t *mcp = &mc;
3580
5f28d2d7
SK		 3581 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3582 "Entered %s.\n", __func__);
7c3df132 3583
7b867cf7 3584 if (!IS_IIDMA_CAPABLE(vha->hw))
d8b45213
AV		 3585 return QLA_FUNCTION_FAILED;
3586
d8b45213
AV		 3587 mcp->mb[0] = MBC_PORT_PARAMS;
3588 mcp->mb[1] = loop_id;
3589 mcp->mb[2] = BIT_0;
6246b8a1 3590 if (IS_CNA_CAPABLE(vha->hw))
1bb39548
HZ		 3591 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
3592 else
3593 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3594 mcp->mb[9] = vha->vp_idx;
3595 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3596 mcp->in_mb = MBX_3|MBX_1|MBX_0;
b93480e3 3597 mcp->tov = MBX_TOV_SECONDS;
d8b45213 3598 mcp->flags = 0;
7b867cf7 3599 rval = qla2x00_mailbox_command(vha, mcp);
d8b45213
AV		 3600
3601 /* Return mailbox statuses. */
3602 if (mb != NULL) {
3603 mb[0] = mcp->mb[0];
3604 mb[1] = mcp->mb[1];
3605 mb[3] = mcp->mb[3];
d8b45213
AV		 3606 }
3607
3608 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3609 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3610 "Failed=%x.\n", rval);
d8b45213 3611 } else {
5f28d2d7
SK		 3612 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3613 "Done %s.\n", __func__);
d8b45213
AV		 3614 }
3615
3616 return rval;
3617}
2c3dfe3f 3618
2c3dfe3f 3619void
7b867cf7 3620qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2c3dfe3f
SJ		 3621 struct vp_rpt_id_entry_24xx *rptid_entry)
3622{
7b867cf7 3623 struct qla_hw_data *ha = vha->hw;
41dc529a 3624 scsi_qla_host_t *vp = NULL;
feafb7b1 3625 unsigned long flags;
4ac8d4ca 3626 int found;
482c9dc7 3627 port_id_t id;
2c3dfe3f 3628
5f28d2d7
SK		 3629 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3630 "Entered %s.\n", __func__);
7c3df132 3631
2c3dfe3f
SJ		 3632 if (rptid_entry->entry_status != 0)
3633 return;
2c3dfe3f 3634
482c9dc7
QT		 3635 id.b.domain = rptid_entry->port_id[2];
3636 id.b.area = rptid_entry->port_id[1];
3637 id.b.al_pa = rptid_entry->port_id[0];
3638 id.b.rsvd_1 = 0;
3639
2c3dfe3f 3640 if (rptid_entry->format == 0) {
41dc529a 3641 /* loop */
ec7193e2 3642 ql_dbg(ql_dbg_async, vha, 0x10b7,
7c3df132 3643 "Format 0 : Number of VPs setup %d, number of "
41dc529a
QT		 3644 "VPs acquired %d.\n", rptid_entry->vp_setup,
3645 rptid_entry->vp_acquired);
ec7193e2 3646 ql_dbg(ql_dbg_async, vha, 0x10b8,
7c3df132
SK		 3647 "Primary port id %02x%02x%02x.\n",
3648 rptid_entry->port_id[2], rptid_entry->port_id[1],
3649 rptid_entry->port_id[0]);
41dc529a 3650
482c9dc7 3651 qlt_update_host_map(vha, id);
41dc529a 3652
2c3dfe3f 3653 } else if (rptid_entry->format == 1) {
41dc529a 3654 /* fabric */
ec7193e2 3655 ql_dbg(ql_dbg_async, vha, 0x10b9,
7c3df132 3656 "Format 1: VP[%d] enabled - status %d - with "
41dc529a
QT		 3657 "port id %02x%02x%02x.\n", rptid_entry->vp_idx,
3658 rptid_entry->vp_status,
2c3dfe3f 3659 rptid_entry->port_id[2], rptid_entry->port_id[1],
7c3df132 3660 rptid_entry->port_id[0]);
531a82d1 3661
969a6199 3662 /* buffer to buffer credit flag */
41dc529a
QT		 3663 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0;
3664
3665 if (rptid_entry->vp_idx == 0) {
3666 if (rptid_entry->vp_status == VP_STAT_COMPL) {
3667 /* FA-WWN is only for physical port */
3668 if (qla_ini_mode_enabled(vha) &&
3669 ha->flags.fawwpn_enabled &&
3670 (rptid_entry->u.f1.flags &
3671 VP_FLAGS_NAME_VALID)) {
3672 memcpy(vha->port_name,
3673 rptid_entry->u.f1.port_name,
3674 WWN_SIZE);
3675 }
7c9c4766 3676
482c9dc7 3677 qlt_update_host_map(vha, id);
7c9c4766 3678 }
41dc529a 3679
41dc529a
QT		 3680 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
3681 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
3682 } else {
3683 if (rptid_entry->vp_status != VP_STAT_COMPL &&
3684 rptid_entry->vp_status != VP_STAT_ID_CHG) {
3685 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3686 "Could not acquire ID for VP[%d].\n",
3687 rptid_entry->vp_idx);
3688 return;
4ac8d4ca 3689 }
feafb7b1 3690
41dc529a
QT		 3691 found = 0;
3692 spin_lock_irqsave(&ha->vport_slock, flags);
3693 list_for_each_entry(vp, &ha->vp_list, list) {
3694 if (rptid_entry->vp_idx == vp->vp_idx) {
3695 found = 1;
3696 break;
3697 }
3698 }
3699 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f 3700
41dc529a
QT		 3701 if (!found)
3702 return;
2c3dfe3f 3703
482c9dc7 3704 qlt_update_host_map(vp, id);
2c3dfe3f 3705
41dc529a
QT		 3706 /*
3707 * Cannot configure here as we are still sitting on the
3708 * response queue. Handle it in dpc context.
3709 */
3710 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
3711 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3712 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3713 }
531a82d1 3714 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
7b867cf7 3715 qla2xxx_wake_dpc(vha);
41dc529a 3716 } else if (rptid_entry->format == 2) {
83548fe2 3717 ql_dbg(ql_dbg_async, vha, 0x505f,
41dc529a
QT		 3718 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n",
3719 rptid_entry->port_id[2], rptid_entry->port_id[1],
3720 rptid_entry->port_id[0]);
3721
83548fe2 3722 ql_dbg(ql_dbg_async, vha, 0x5075,
41dc529a
QT		 3723 "N2N: Remote WWPN %8phC.\n",
3724 rptid_entry->u.f2.port_name);
3725
3726 /* N2N. direct connect */
3727 vha->d_id.b.domain = rptid_entry->port_id[2];
3728 vha->d_id.b.area = rptid_entry->port_id[1];
3729 vha->d_id.b.al_pa = rptid_entry->port_id[0];
3730
3731 spin_lock_irqsave(&ha->vport_slock, flags);
3732 qlt_update_vp_map(vha, SET_AL_PA);
3733 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f
SJ		 3734 }
3735}
3736
3737/*
3738 * qla24xx_modify_vp_config
3739 * Change VP configuration for vha
3740 *
3741 * Input:
3742 * vha = adapter block pointer.
3743 *
3744 * Returns:
3745 * qla2xxx local function return status code.
3746 *
3747 * Context:
3748 * Kernel context.
3749 */
3750int
3751qla24xx_modify_vp_config(scsi_qla_host_t *vha)
3752{
3753 int rval;
3754 struct vp_config_entry_24xx *vpmod;
3755 dma_addr_t vpmod_dma;
7b867cf7
AC		 3756 struct qla_hw_data *ha = vha->hw;
3757 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f
SJ		 3758
3759 /* This can be called by the parent */
2c3dfe3f 3760
5f28d2d7
SK		 3761 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
3762 "Entered %s.\n", __func__);
7c3df132 3763
7b867cf7 3764 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2c3dfe3f 3765 if (!vpmod) {
7c3df132
SK		 3766 ql_log(ql_log_warn, vha, 0x10bc,
3767 "Failed to allocate modify VP IOCB.\n");
2c3dfe3f
SJ		 3768 return QLA_MEMORY_ALLOC_FAILED;
3769 }
3770
3771 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
3772 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
3773 vpmod->entry_count = 1;
3774 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
3775 vpmod->vp_count = 1;
3776 vpmod->vp_index1 = vha->vp_idx;
3777 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2d70c103
NB		 3778
3779 qlt_modify_vp_config(vha, vpmod);
3780
2c3dfe3f
SJ		 3781 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
3782 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
3783 vpmod->entry_count = 1;
3784
7b867cf7 3785 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2c3dfe3f 3786 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3787 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
3788 "Failed to issue VP config IOCB (%x).\n", rval);
2c3dfe3f 3789 } else if (vpmod->comp_status != 0) {
7c3df132
SK		 3790 ql_dbg(ql_dbg_mbx, vha, 0x10be,
3791 "Failed to complete IOCB -- error status (%x).\n",
3792 vpmod->comp_status);
2c3dfe3f 3793 rval = QLA_FUNCTION_FAILED;
ad950360 3794 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3795 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
3796 "Failed to complete IOCB -- completion status (%x).\n",
3797 le16_to_cpu(vpmod->comp_status));
2c3dfe3f
SJ		 3798 rval = QLA_FUNCTION_FAILED;
3799 } else {
3800 /* EMPTY */
5f28d2d7
SK		 3801 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
3802 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3803 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
3804 }
7b867cf7 3805 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2c3dfe3f
SJ		 3806
3807 return rval;
3808}
3809
3810/*
3811 * qla24xx_control_vp
3812 * Enable a virtual port for given host
3813 *
3814 * Input:
3815 * ha = adapter block pointer.
3816 * vhba = virtual adapter (unused)
3817 * index = index number for enabled VP
3818 *
3819 * Returns:
3820 * qla2xxx local function return status code.
3821 *
3822 * Context:
3823 * Kernel context.
3824 */
3825int
3826qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
3827{
3828 int rval;
3829 int map, pos;
3830 struct vp_ctrl_entry_24xx *vce;
3831 dma_addr_t vce_dma;
7b867cf7 3832 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 3833 int vp_index = vha->vp_idx;
7b867cf7 3834 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 3835
5f28d2d7 3836 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
7c3df132 3837 "Entered %s enabling index %d.\n", __func__, vp_index);
2c3dfe3f 3838
eb66dc60 3839 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
2c3dfe3f
SJ		 3840 return QLA_PARAMETER_ERROR;
3841
3842 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3843 if (!vce) {
7c3df132
SK		 3844 ql_log(ql_log_warn, vha, 0x10c2,
3845 "Failed to allocate VP control IOCB.\n");
2c3dfe3f
SJ		 3846 return QLA_MEMORY_ALLOC_FAILED;
3847 }
3848 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3849
3850 vce->entry_type = VP_CTRL_IOCB_TYPE;
3851 vce->entry_count = 1;
3852 vce->command = cpu_to_le16(cmd);
ad950360 3853 vce->vp_count = cpu_to_le16(1);
2c3dfe3f
SJ		 3854
3855 /* index map in firmware starts with 1; decrement index
3856 * this is ok as we never use index 0
3857 */
3858 map = (vp_index - 1) / 8;
3859 pos = (vp_index - 1) & 7;
6c2f527c 3860 mutex_lock(&ha->vport_lock);
2c3dfe3f 3861 vce->vp_idx_map[map] |= 1 << pos;
6c2f527c 3862 mutex_unlock(&ha->vport_lock);
2c3dfe3f 3863
7b867cf7 3864 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
2c3dfe3f 3865 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3866 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3867 "Failed to issue VP control IOCB (%x).\n", rval);
2c3dfe3f 3868 } else if (vce->entry_status != 0) {
7c3df132
SK		 3869 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3870 "Failed to complete IOCB -- error status (%x).\n",
2c3dfe3f
SJ		 3871 vce->entry_status);
3872 rval = QLA_FUNCTION_FAILED;
ad950360 3873 } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3874 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
3875 "Failed to complet IOCB -- completion status (%x).\n",
2c3dfe3f
SJ		 3876 le16_to_cpu(vce->comp_status));
3877 rval = QLA_FUNCTION_FAILED;
3878 } else {
5f28d2d7
SK		 3879 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
3880 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3881 }
3882
3883 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3884
3885 return rval;
3886}
3887
3888/*
3889 * qla2x00_send_change_request
3890 * Receive or disable RSCN request from fabric controller
3891 *
3892 * Input:
3893 * ha = adapter block pointer
3894 * format = registration format:
3895 * 0 - Reserved
3896 * 1 - Fabric detected registration
3897 * 2 - N_port detected registration
3898 * 3 - Full registration
3899 * FF - clear registration
3900 * vp_idx = Virtual port index
3901 *
3902 * Returns:
3903 * qla2x00 local function return status code.
3904 *
3905 * Context:
3906 * Kernel Context
3907 */
3908
3909int
7b867cf7 3910qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
2c3dfe3f
SJ		 3911 uint16_t vp_idx)
3912{
3913 int rval;
3914 mbx_cmd_t mc;
3915 mbx_cmd_t *mcp = &mc;
3916
5f28d2d7
SK		 3917 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
3918 "Entered %s.\n", __func__);
7c3df132 3919
2c3dfe3f
SJ		 3920 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3921 mcp->mb[1] = format;
3922 mcp->mb[9] = vp_idx;
3923 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3924 mcp->in_mb = MBX_0|MBX_1;
3925 mcp->tov = MBX_TOV_SECONDS;
3926 mcp->flags = 0;
7b867cf7 3927 rval = qla2x00_mailbox_command(vha, mcp);
2c3dfe3f
SJ		 3928
3929 if (rval == QLA_SUCCESS) {
3930 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3931 rval = BIT_1;
3932 }
3933 } else
3934 rval = BIT_1;
3935
3936 return rval;
3937}
338c9161
AV		 3938
3939int
7b867cf7 3940qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
338c9161
AV		 3941 uint32_t size)
3942{
3943 int rval;
3944 mbx_cmd_t mc;
3945 mbx_cmd_t *mcp = &mc;
3946
5f28d2d7
SK		 3947 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
3948 "Entered %s.\n", __func__);
338c9161 3949
7b867cf7 3950 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3951 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3952 mcp->mb[8] = MSW(addr);
3953 mcp->out_mb = MBX_8|MBX_0;
3954 } else {
3955 mcp->mb[0] = MBC_DUMP_RISC_RAM;
3956 mcp->out_mb = MBX_0;
3957 }
3958 mcp->mb[1] = LSW(addr);
3959 mcp->mb[2] = MSW(req_dma);
3960 mcp->mb[3] = LSW(req_dma);
3961 mcp->mb[6] = MSW(MSD(req_dma));
3962 mcp->mb[7] = LSW(MSD(req_dma));
3963 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
7b867cf7 3964 if (IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3965 mcp->mb[4] = MSW(size);
3966 mcp->mb[5] = LSW(size);
3967 mcp->out_mb |= MBX_5|MBX_4;
3968 } else {
3969 mcp->mb[4] = LSW(size);
3970 mcp->out_mb |= MBX_4;
3971 }
3972
3973 mcp->in_mb = MBX_0;
b93480e3 3974 mcp->tov = MBX_TOV_SECONDS;
338c9161 3975 mcp->flags = 0;
7b867cf7 3976 rval = qla2x00_mailbox_command(vha, mcp);
338c9161
AV		 3977
3978 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3979 ql_dbg(ql_dbg_mbx, vha, 0x1008,
3980 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
338c9161 3981 } else {
5f28d2d7
SK		 3982 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
3983 "Done %s.\n", __func__);
338c9161
AV		 3984 }
3985
3986 return rval;
3987}
4d4df193
HK		 3988/* 84XX Support **************************************************************/
3989
3990struct cs84xx_mgmt_cmd {
3991 union {
3992 struct verify_chip_entry_84xx req;
3993 struct verify_chip_rsp_84xx rsp;
3994 } p;
3995};
3996
3997int
7b867cf7 3998qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4d4df193
HK		 3999{
4000 int rval, retry;
4001 struct cs84xx_mgmt_cmd *mn;
4002 dma_addr_t mn_dma;
4003 uint16_t options;
4004 unsigned long flags;
7b867cf7 4005 struct qla_hw_data *ha = vha->hw;
4d4df193 4006
5f28d2d7
SK		 4007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
4008 "Entered %s.\n", __func__);
4d4df193
HK		 4009
4010 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
4011 if (mn == NULL) {
4d4df193
HK		 4012 return QLA_MEMORY_ALLOC_FAILED;
4013 }
4014
4015 /* Force Update? */
4016 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
4017 /* Diagnostic firmware? */
4018 /* options |= MENLO_DIAG_FW; */
4019 /* We update the firmware with only one data sequence. */
4020 options |= VCO_END_OF_DATA;
4021
4d4df193 4022 do {
c1ec1f1b 4023 retry = 0;
4d4df193
HK		 4024 memset(mn, 0, sizeof(*mn));
4025 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
4026 mn->p.req.entry_count = 1;
4027 mn->p.req.options = cpu_to_le16(options);
4028
7c3df132
SK		 4029 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4030 "Dump of Verify Request.\n");
4031 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
4032 (uint8_t *)mn, sizeof(*mn));
4d4df193 4033
7b867cf7 4034 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4d4df193 4035 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4036 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
4037 "Failed to issue verify IOCB (%x).\n", rval);
4d4df193
HK		 4038 goto verify_done;
4039 }
4040
7c3df132
SK		 4041 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4042 "Dump of Verify Response.\n");
4043 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
4044 (uint8_t *)mn, sizeof(*mn));
4d4df193
HK		 4045
4046 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4047 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
4048 le16_to_cpu(mn->p.rsp.failure_code) : 0;
5f28d2d7 4049 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
7c3df132 4050 "cs=%x fc=%x.\n", status[0], status[1]);
4d4df193
HK		 4051
4052 if (status[0] != CS_COMPLETE) {
4053 rval = QLA_FUNCTION_FAILED;
4054 if (!(options & VCO_DONT_UPDATE_FW)) {
7c3df132
SK		 4055 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
4056 "Firmware update failed. Retrying "
4057 "without update firmware.\n");
4d4df193
HK		 4058 options |= VCO_DONT_UPDATE_FW;
4059 options &= ~VCO_FORCE_UPDATE;
4060 retry = 1;
4061 }
4062 } else {
5f28d2d7 4063 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
7c3df132
SK		 4064 "Firmware updated to %x.\n",
4065 le32_to_cpu(mn->p.rsp.fw_ver));
4d4df193
HK		 4066
4067 /* NOTE: we only update OP firmware. */
4068 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
4069 ha->cs84xx->op_fw_version =
4070 le32_to_cpu(mn->p.rsp.fw_ver);
4071 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
4072 flags);
4073 }
4074 } while (retry);
4075
4076verify_done:
4077 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
4078
4079 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 4080 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
4081 "Failed=%x.\n", rval);
4d4df193 4082 } else {
5f28d2d7
SK		 4083 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
4084 "Done %s.\n", __func__);
4d4df193
HK		 4085 }
4086
4087 return rval;
4088}
73208dfd
AC		 4089
4090int
618a7523 4091qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
73208dfd
AC		 4092{
4093 int rval;
4094 unsigned long flags;
4095 mbx_cmd_t mc;
4096 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4097 struct qla_hw_data *ha = vha->hw;
4098
5f28d2d7
SK		 4099 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
4100 "Entered %s.\n", __func__);
7c3df132 4101
7c6300e3
JC		 4102 if (IS_SHADOW_REG_CAPABLE(ha))
4103 req->options |= BIT_13;
4104
73208dfd 4105 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4106 mcp->mb[1] = req->options;
73208dfd
AC		 4107 mcp->mb[2] = MSW(LSD(req->dma));
4108 mcp->mb[3] = LSW(LSD(req->dma));
4109 mcp->mb[6] = MSW(MSD(req->dma));
4110 mcp->mb[7] = LSW(MSD(req->dma));
4111 mcp->mb[5] = req->length;
4112 if (req->rsp)
4113 mcp->mb[10] = req->rsp->id;
4114 mcp->mb[12] = req->qos;
4115 mcp->mb[11] = req->vp_idx;
4116 mcp->mb[13] = req->rid;
f73cb695 4117 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4118 mcp->mb[15] = 0;
73208dfd 4119
73208dfd
AC		 4120 mcp->mb[4] = req->id;
4121 /* que in ptr index */
4122 mcp->mb[8] = 0;
4123 /* que out ptr index */
7c6300e3 4124 mcp->mb[9] = *req->out_ptr = 0;
73208dfd
AC		 4125 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
4126 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4127 mcp->in_mb = MBX_0;
4128 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4129 mcp->tov = MBX_TOV_SECONDS * 2;
4130
f73cb695 4131 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4132 mcp->in_mb |= MBX_1;
ba4828b7 4133 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 4134 mcp->out_mb |= MBX_15;
4135 /* debug q create issue in SR-IOV */
4136 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4137 }
73208dfd
AC		 4138
4139 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4140 if (!(req->options & BIT_0)) {
da9b1d5c 4141 WRT_REG_DWORD(req->req_q_in, 0);
29db41c3 4142 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 4143 WRT_REG_DWORD(req->req_q_out, 0);
73208dfd
AC		 4144 }
4145 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4146
17d98630 4147 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4148 if (rval != QLA_SUCCESS) {
4149 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
4150 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4151 } else {
5f28d2d7
SK		 4152 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
4153 "Done %s.\n", __func__);
7c3df132
SK		 4154 }
4155
73208dfd
AC		 4156 return rval;
4157}
4158
4159int
618a7523 4160qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
73208dfd
AC		 4161{
4162 int rval;
4163 unsigned long flags;
4164 mbx_cmd_t mc;
4165 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4166 struct qla_hw_data *ha = vha->hw;
4167
5f28d2d7
SK		 4168 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
4169 "Entered %s.\n", __func__);
7c3df132 4170
7c6300e3
JC		 4171 if (IS_SHADOW_REG_CAPABLE(ha))
4172 rsp->options |= BIT_13;
4173
73208dfd 4174 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4175 mcp->mb[1] = rsp->options;
73208dfd
AC		 4176 mcp->mb[2] = MSW(LSD(rsp->dma));
4177 mcp->mb[3] = LSW(LSD(rsp->dma));
4178 mcp->mb[6] = MSW(MSD(rsp->dma));
4179 mcp->mb[7] = LSW(MSD(rsp->dma));
4180 mcp->mb[5] = rsp->length;
444786d7 4181 mcp->mb[14] = rsp->msix->entry;
73208dfd 4182 mcp->mb[13] = rsp->rid;
f73cb695 4183 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4184 mcp->mb[15] = 0;
73208dfd 4185
73208dfd
AC		 4186 mcp->mb[4] = rsp->id;
4187 /* que in ptr index */
7c6300e3 4188 mcp->mb[8] = *rsp->in_ptr = 0;
73208dfd
AC		 4189 /* que out ptr index */
4190 mcp->mb[9] = 0;
2afa19a9 4191 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
73208dfd
AC		 4192 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4193 mcp->in_mb = MBX_0;
4194 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4195 mcp->tov = MBX_TOV_SECONDS * 2;
4196
4197 if (IS_QLA81XX(ha)) {
4198 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
4199 mcp->in_mb |= MBX_1;
f73cb695 4200 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 4201 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
4202 mcp->in_mb |= MBX_1;
4203 /* debug q create issue in SR-IOV */
4204 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4205 }
73208dfd
AC		 4206
4207 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4208 if (!(rsp->options & BIT_0)) {
da9b1d5c 4209 WRT_REG_DWORD(rsp->rsp_q_out, 0);
b20f02e1 4210 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 4211 WRT_REG_DWORD(rsp->rsp_q_in, 0);
73208dfd
AC		 4212 }
4213
4214 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4215
17d98630 4216 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4217 if (rval != QLA_SUCCESS) {
4218 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
4219 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4220 } else {
5f28d2d7
SK		 4221 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
4222 "Done %s.\n", __func__);
7c3df132
SK		 4223 }
4224
73208dfd
AC		 4225 return rval;
4226}
4227
8a659571
AV		 4228int
4229qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
4230{
4231 int rval;
4232 mbx_cmd_t mc;
4233 mbx_cmd_t *mcp = &mc;
4234
5f28d2d7
SK		 4235 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
4236 "Entered %s.\n", __func__);
8a659571
AV		 4237
4238 mcp->mb[0] = MBC_IDC_ACK;
4239 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4240 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4241 mcp->in_mb = MBX_0;
4242 mcp->tov = MBX_TOV_SECONDS;
4243 mcp->flags = 0;
4244 rval = qla2x00_mailbox_command(vha, mcp);
4245
4246 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4247 ql_dbg(ql_dbg_mbx, vha, 0x10da,
4248 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
8a659571 4249 } else {
5f28d2d7
SK		 4250 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
4251 "Done %s.\n", __func__);
8a659571
AV		 4252 }
4253
4254 return rval;
4255}
1d2874de
JC		 4256
4257int
4258qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
4259{
4260 int rval;
4261 mbx_cmd_t mc;
4262 mbx_cmd_t *mcp = &mc;
4263
5f28d2d7
SK		 4264 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
4265 "Entered %s.\n", __func__);
7c3df132 4266
f73cb695
CD		 4267 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4268 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4269 return QLA_FUNCTION_FAILED;
4270
1d2874de
JC		 4271 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4272 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
4273 mcp->out_mb = MBX_1|MBX_0;
4274 mcp->in_mb = MBX_1|MBX_0;
4275 mcp->tov = MBX_TOV_SECONDS;
4276 mcp->flags = 0;
4277 rval = qla2x00_mailbox_command(vha, mcp);
4278
4279 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4280 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
4281 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4282 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4283 } else {
5f28d2d7
SK		 4284 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
4285 "Done %s.\n", __func__);
1d2874de
JC		 4286 *sector_size = mcp->mb[1];
4287 }
4288
4289 return rval;
4290}
4291
4292int
4293qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
4294{
4295 int rval;
4296 mbx_cmd_t mc;
4297 mbx_cmd_t *mcp = &mc;
4298
f73cb695
CD		 4299 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4300 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4301 return QLA_FUNCTION_FAILED;
4302
5f28d2d7
SK		 4303 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
4304 "Entered %s.\n", __func__);
1d2874de
JC		 4305
4306 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4307 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4308 FAC_OPT_CMD_WRITE_PROTECT;
4309 mcp->out_mb = MBX_1|MBX_0;
4310 mcp->in_mb = MBX_1|MBX_0;
4311 mcp->tov = MBX_TOV_SECONDS;
4312 mcp->flags = 0;
4313 rval = qla2x00_mailbox_command(vha, mcp);
4314
4315 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4316 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4317 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4318 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4319 } else {
5f28d2d7
SK		 4320 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4321 "Done %s.\n", __func__);
1d2874de
JC		 4322 }
4323
4324 return rval;
4325}
4326
4327int
4328qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4329{
4330 int rval;
4331 mbx_cmd_t mc;
4332 mbx_cmd_t *mcp = &mc;
4333
f73cb695
CD		 4334 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4335 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4336 return QLA_FUNCTION_FAILED;
4337
5f28d2d7
SK		 4338 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4339 "Entered %s.\n", __func__);
1d2874de
JC		 4340
4341 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4342 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4343 mcp->mb[2] = LSW(start);
4344 mcp->mb[3] = MSW(start);
4345 mcp->mb[4] = LSW(finish);
4346 mcp->mb[5] = MSW(finish);
4347 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4348 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4349 mcp->tov = MBX_TOV_SECONDS;
4350 mcp->flags = 0;
4351 rval = qla2x00_mailbox_command(vha, mcp);
4352
4353 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4354 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4355 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4356 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1d2874de 4357 } else {
5f28d2d7
SK		 4358 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4359 "Done %s.\n", __func__);
1d2874de
JC		 4360 }
4361
4362 return rval;
4363}
6e181be5
LC		 4364
4365int
4366qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4367{
4368 int rval = 0;
4369 mbx_cmd_t mc;
4370 mbx_cmd_t *mcp = &mc;
4371
5f28d2d7
SK		 4372 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4373 "Entered %s.\n", __func__);
6e181be5
LC		 4374
4375 mcp->mb[0] = MBC_RESTART_MPI_FW;
4376 mcp->out_mb = MBX_0;
4377 mcp->in_mb = MBX_0|MBX_1;
4378 mcp->tov = MBX_TOV_SECONDS;
4379 mcp->flags = 0;
4380 rval = qla2x00_mailbox_command(vha, mcp);
4381
4382 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4383 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4384 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4385 rval, mcp->mb[0], mcp->mb[1]);
6e181be5 4386 } else {
5f28d2d7
SK		 4387 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4388 "Done %s.\n", __func__);
6e181be5
LC		 4389 }
4390
4391 return rval;
4392}
ad0ecd61 4393
c46e65c7
JC		 4394int
4395qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4396{
4397 int rval;
4398 mbx_cmd_t mc;
4399 mbx_cmd_t *mcp = &mc;
4400 int i;
4401 int len;
4402 uint16_t *str;
4403 struct qla_hw_data *ha = vha->hw;
4404
4405 if (!IS_P3P_TYPE(ha))
4406 return QLA_FUNCTION_FAILED;
4407
4408 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4409 "Entered %s.\n", __func__);
4410
4411 str = (void *)version;
4412 len = strlen(version);
4413
4414 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4415 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4416 mcp->out_mb = MBX_1|MBX_0;
4417 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4418 mcp->mb[i] = cpu_to_le16p(str);
4419 mcp->out_mb |= 1<<i;
4420 }
4421 for (; i < 16; i++) {
4422 mcp->mb[i] = 0;
4423 mcp->out_mb |= 1<<i;
4424 }
4425 mcp->in_mb = MBX_1|MBX_0;
4426 mcp->tov = MBX_TOV_SECONDS;
4427 mcp->flags = 0;
4428 rval = qla2x00_mailbox_command(vha, mcp);
4429
4430 if (rval != QLA_SUCCESS) {
4431 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4432 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4433 } else {
4434 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4435 "Done %s.\n", __func__);
4436 }
4437
4438 return rval;
4439}
4440
4441int
4442qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4443{
4444 int rval;
4445 mbx_cmd_t mc;
4446 mbx_cmd_t *mcp = &mc;
4447 int len;
4448 uint16_t dwlen;
4449 uint8_t *str;
4450 dma_addr_t str_dma;
4451 struct qla_hw_data *ha = vha->hw;
4452
4453 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4454 IS_P3P_TYPE(ha))
4455 return QLA_FUNCTION_FAILED;
4456
4457 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4458 "Entered %s.\n", __func__);
4459
4460 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4461 if (!str) {
4462 ql_log(ql_log_warn, vha, 0x117f,
4463 "Failed to allocate driver version param.\n");
4464 return QLA_MEMORY_ALLOC_FAILED;
4465 }
4466
4467 memcpy(str, "\x7\x3\x11\x0", 4);
4468 dwlen = str[0];
4469 len = dwlen * 4 - 4;
4470 memset(str + 4, 0, len);
4471 if (len > strlen(version))
4472 len = strlen(version);
4473 memcpy(str + 4, version, len);
4474
4475 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4476 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4477 mcp->mb[2] = MSW(LSD(str_dma));
4478 mcp->mb[3] = LSW(LSD(str_dma));
4479 mcp->mb[6] = MSW(MSD(str_dma));
4480 mcp->mb[7] = LSW(MSD(str_dma));
4481 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4482 mcp->in_mb = MBX_1|MBX_0;
4483 mcp->tov = MBX_TOV_SECONDS;
4484 mcp->flags = 0;
4485 rval = qla2x00_mailbox_command(vha, mcp);
4486
4487 if (rval != QLA_SUCCESS) {
4488 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4489 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4490 } else {
4491 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4492 "Done %s.\n", __func__);
4493 }
4494
4495 dma_pool_free(ha->s_dma_pool, str, str_dma);
4496
4497 return rval;
4498}
4499
fe52f6e1
JC		 4500static int
4501qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4502{
4503 int rval;
4504 mbx_cmd_t mc;
4505 mbx_cmd_t *mcp = &mc;
4506
4507 if (!IS_FWI2_CAPABLE(vha->hw))
4508 return QLA_FUNCTION_FAILED;
4509
4510 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4511 "Entered %s.\n", __func__);
4512
4513 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4514 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4515 mcp->out_mb = MBX_1|MBX_0;
4516 mcp->in_mb = MBX_1|MBX_0;
4517 mcp->tov = MBX_TOV_SECONDS;
4518 mcp->flags = 0;
4519 rval = qla2x00_mailbox_command(vha, mcp);
4520 *temp = mcp->mb[1];
4521
4522 if (rval != QLA_SUCCESS) {
4523 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4524 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4525 } else {
4526 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4527 "Done %s.\n", __func__);
4528 }
4529
4530 return rval;
4531}
4532
ad0ecd61 4533int
6766df9e
JC		 4534qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4535 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4536{
4537 int rval;
4538 mbx_cmd_t mc;
4539 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4540 struct qla_hw_data *ha = vha->hw;
4541
5f28d2d7
SK		 4542 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4543 "Entered %s.\n", __func__);
7c3df132 4544
6766df9e
JC		 4545 if (!IS_FWI2_CAPABLE(ha))
4546 return QLA_FUNCTION_FAILED;
ad0ecd61 4547
6766df9e
JC		 4548 if (len == 1)
4549 opt |= BIT_0;
4550
ad0ecd61
JC		 4551 mcp->mb[0] = MBC_READ_SFP;
4552 mcp->mb[1] = dev;
4553 mcp->mb[2] = MSW(sfp_dma);
4554 mcp->mb[3] = LSW(sfp_dma);
4555 mcp->mb[6] = MSW(MSD(sfp_dma));
4556 mcp->mb[7] = LSW(MSD(sfp_dma));
4557 mcp->mb[8] = len;
6766df9e 4558 mcp->mb[9] = off;
ad0ecd61
JC		 4559 mcp->mb[10] = opt;
4560 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1bff6cc8 4561 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4562 mcp->tov = MBX_TOV_SECONDS;
4563 mcp->flags = 0;
4564 rval = qla2x00_mailbox_command(vha, mcp);
4565
4566 if (opt & BIT_0)
6766df9e 4567 *sfp = mcp->mb[1];
ad0ecd61
JC		 4568
4569 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4570 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4571 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4572 } else {
5f28d2d7
SK		 4573 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4574 "Done %s.\n", __func__);
ad0ecd61
JC		 4575 }
4576
4577 return rval;
4578}
4579
4580int
6766df9e
JC		 4581qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4582 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4583{
4584 int rval;
4585 mbx_cmd_t mc;
4586 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4587 struct qla_hw_data *ha = vha->hw;
4588
5f28d2d7
SK		 4589 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4590 "Entered %s.\n", __func__);
7c3df132 4591
6766df9e
JC		 4592 if (!IS_FWI2_CAPABLE(ha))
4593 return QLA_FUNCTION_FAILED;
ad0ecd61 4594
6766df9e
JC		 4595 if (len == 1)
4596 opt |= BIT_0;
4597
ad0ecd61 4598 if (opt & BIT_0)
6766df9e 4599 len = *sfp;
ad0ecd61
JC		 4600
4601 mcp->mb[0] = MBC_WRITE_SFP;
4602 mcp->mb[1] = dev;
4603 mcp->mb[2] = MSW(sfp_dma);
4604 mcp->mb[3] = LSW(sfp_dma);
4605 mcp->mb[6] = MSW(MSD(sfp_dma));
4606 mcp->mb[7] = LSW(MSD(sfp_dma));
4607 mcp->mb[8] = len;
6766df9e 4608 mcp->mb[9] = off;
ad0ecd61
JC		 4609 mcp->mb[10] = opt;
4610 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6766df9e 4611 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4612 mcp->tov = MBX_TOV_SECONDS;
4613 mcp->flags = 0;
4614 rval = qla2x00_mailbox_command(vha, mcp);
4615
4616 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4617 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4618 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4619 } else {
5f28d2d7
SK		 4620 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4621 "Done %s.\n", __func__);
ad0ecd61
JC		 4622 }
4623
4624 return rval;
4625}
ce0423f4
AV		 4626
4627int
4628qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4629 uint16_t size_in_bytes, uint16_t *actual_size)
4630{
4631 int rval;
4632 mbx_cmd_t mc;
4633 mbx_cmd_t *mcp = &mc;
4634
5f28d2d7
SK		 4635 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4636 "Entered %s.\n", __func__);
7c3df132 4637
6246b8a1 4638 if (!IS_CNA_CAPABLE(vha->hw))
ce0423f4
AV		 4639 return QLA_FUNCTION_FAILED;
4640
ce0423f4
AV		 4641 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4642 mcp->mb[2] = MSW(stats_dma);
4643 mcp->mb[3] = LSW(stats_dma);
4644 mcp->mb[6] = MSW(MSD(stats_dma));
4645 mcp->mb[7] = LSW(MSD(stats_dma));
4646 mcp->mb[8] = size_in_bytes >> 2;
4647 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4648 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4649 mcp->tov = MBX_TOV_SECONDS;
4650 mcp->flags = 0;
4651 rval = qla2x00_mailbox_command(vha, mcp);
4652
4653 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4654 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4655 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4656 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
ce0423f4 4657 } else {
5f28d2d7
SK		 4658 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4659 "Done %s.\n", __func__);
7c3df132 4660
ce0423f4
AV		 4661
4662 *actual_size = mcp->mb[2] << 2;
4663 }
4664
4665 return rval;
4666}
11bbc1d8
AV		 4667
4668int
4669qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4670 uint16_t size)
4671{
4672 int rval;
4673 mbx_cmd_t mc;
4674 mbx_cmd_t *mcp = &mc;
4675
5f28d2d7
SK		 4676 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4677 "Entered %s.\n", __func__);
7c3df132 4678
6246b8a1 4679 if (!IS_CNA_CAPABLE(vha->hw))
11bbc1d8
AV		 4680 return QLA_FUNCTION_FAILED;
4681
11bbc1d8
AV		 4682 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4683 mcp->mb[1] = 0;
4684 mcp->mb[2] = MSW(tlv_dma);
4685 mcp->mb[3] = LSW(tlv_dma);
4686 mcp->mb[6] = MSW(MSD(tlv_dma));
4687 mcp->mb[7] = LSW(MSD(tlv_dma));
4688 mcp->mb[8] = size;
4689 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4690 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4691 mcp->tov = MBX_TOV_SECONDS;
4692 mcp->flags = 0;
4693 rval = qla2x00_mailbox_command(vha, mcp);
4694
4695 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4696 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4697 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4698 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
11bbc1d8 4699 } else {
5f28d2d7
SK		 4700 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4701 "Done %s.\n", __func__);
11bbc1d8
AV		 4702 }
4703
4704 return rval;
4705}
18e7555a
AV		 4706
4707int
4708qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4709{
4710 int rval;
4711 mbx_cmd_t mc;
4712 mbx_cmd_t *mcp = &mc;
4713
5f28d2d7
SK		 4714 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4715 "Entered %s.\n", __func__);
7c3df132 4716
18e7555a
AV		 4717 if (!IS_FWI2_CAPABLE(vha->hw))
4718 return QLA_FUNCTION_FAILED;
4719
18e7555a
AV		 4720 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4721 mcp->mb[1] = LSW(risc_addr);
4722 mcp->mb[8] = MSW(risc_addr);
4723 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4724 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4725 mcp->tov = 30;
4726 mcp->flags = 0;
4727 rval = qla2x00_mailbox_command(vha, mcp);
4728 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4729 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4730 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4731 } else {
5f28d2d7
SK		 4732 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4733 "Done %s.\n", __func__);
18e7555a
AV		 4734 *data = mcp->mb[3] << 16 | mcp->mb[2];
4735 }
4736
4737 return rval;
4738}
4739
9a069e19 4740int
a9083016
GM		 4741qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4742 uint16_t *mresp)
9a069e19
GM		 4743{
4744 int rval;
4745 mbx_cmd_t mc;
4746 mbx_cmd_t *mcp = &mc;
9a069e19 4747
5f28d2d7
SK		 4748 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
4749 "Entered %s.\n", __func__);
9a069e19
GM		 4750
4751 memset(mcp->mb, 0 , sizeof(mcp->mb));
4752 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
4753 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
4754
4755 /* transfer count */
4756 mcp->mb[10] = LSW(mreq->transfer_size);
4757 mcp->mb[11] = MSW(mreq->transfer_size);
4758
4759 /* send data address */
4760 mcp->mb[14] = LSW(mreq->send_dma);
4761 mcp->mb[15] = MSW(mreq->send_dma);
4762 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4763 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4764
25985edc 4765 /* receive data address */
9a069e19
GM		 4766 mcp->mb[16] = LSW(mreq->rcv_dma);
4767 mcp->mb[17] = MSW(mreq->rcv_dma);
4768 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4769 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4770
4771 /* Iteration count */
1b98b421
JC		 4772 mcp->mb[18] = LSW(mreq->iteration_count);
4773 mcp->mb[19] = MSW(mreq->iteration_count);
9a069e19
GM		 4774
4775 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
4776 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4777 if (IS_CNA_CAPABLE(vha->hw))
9a069e19
GM		 4778 mcp->out_mb |= MBX_2;
4779 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
4780
4781 mcp->buf_size = mreq->transfer_size;
4782 mcp->tov = MBX_TOV_SECONDS;
4783 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4784
4785 rval = qla2x00_mailbox_command(vha, mcp);
4786
4787 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4788 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
4789 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
4790 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
4791 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
9a069e19 4792 } else {
5f28d2d7
SK		 4793 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
4794 "Done %s.\n", __func__);
9a069e19
GM		 4795 }
4796
4797 /* Copy mailbox information */
4798 memcpy( mresp, mcp->mb, 64);
9a069e19
GM		 4799 return rval;
4800}
4801
4802int
a9083016
GM		 4803qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4804 uint16_t *mresp)
9a069e19
GM		 4805{
4806 int rval;
4807 mbx_cmd_t mc;
4808 mbx_cmd_t *mcp = &mc;
4809 struct qla_hw_data *ha = vha->hw;
4810
5f28d2d7
SK		 4811 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
4812 "Entered %s.\n", __func__);
9a069e19
GM		 4813
4814 memset(mcp->mb, 0 , sizeof(mcp->mb));
4815 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
1d634965
JC		 4816 /* BIT_6 specifies 64bit address */
4817 mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
6246b8a1 4818 if (IS_CNA_CAPABLE(ha)) {
a9083016
GM		 4819 mcp->mb[2] = vha->fcoe_fcf_idx;
4820 }
9a069e19
GM		 4821 mcp->mb[16] = LSW(mreq->rcv_dma);
4822 mcp->mb[17] = MSW(mreq->rcv_dma);
4823 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4824 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4825
4826 mcp->mb[10] = LSW(mreq->transfer_size);
4827
4828 mcp->mb[14] = LSW(mreq->send_dma);
4829 mcp->mb[15] = MSW(mreq->send_dma);
4830 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4831 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4832
4833 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
4834 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4835 if (IS_CNA_CAPABLE(ha))
9a069e19
GM		 4836 mcp->out_mb |= MBX_2;
4837
4838 mcp->in_mb = MBX_0;
6246b8a1
GM		 4839 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
4840 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19 4841 mcp->in_mb |= MBX_1;
6246b8a1 4842 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19
GM		 4843 mcp->in_mb |= MBX_3;
4844
4845 mcp->tov = MBX_TOV_SECONDS;
4846 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4847 mcp->buf_size = mreq->transfer_size;
4848
4849 rval = qla2x00_mailbox_command(vha, mcp);
4850
4851 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4852 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
4853 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4854 rval, mcp->mb[0], mcp->mb[1]);
9a069e19 4855 } else {
5f28d2d7
SK		 4856 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
4857 "Done %s.\n", __func__);
9a069e19
GM		 4858 }
4859
4860 /* Copy mailbox information */
6dbdda4d 4861 memcpy(mresp, mcp->mb, 64);
9a069e19
GM		 4862 return rval;
4863}
6dbdda4d 4864
9a069e19 4865int
7c3df132 4866qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
9a069e19
GM		 4867{
4868 int rval;
4869 mbx_cmd_t mc;
4870 mbx_cmd_t *mcp = &mc;
4871
5f28d2d7 4872 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
7c3df132 4873 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
9a069e19
GM		 4874
4875 mcp->mb[0] = MBC_ISP84XX_RESET;
4876 mcp->mb[1] = enable_diagnostic;
4877 mcp->out_mb = MBX_1|MBX_0;
4878 mcp->in_mb = MBX_1|MBX_0;
4879 mcp->tov = MBX_TOV_SECONDS;
4880 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
7c3df132 4881 rval = qla2x00_mailbox_command(vha, mcp);
9a069e19 4882
9a069e19 4883 if (rval != QLA_SUCCESS)
7c3df132 4884 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
9a069e19 4885 else
5f28d2d7
SK		 4886 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
4887 "Done %s.\n", __func__);
9a069e19
GM		 4888
4889 return rval;
4890}
4891
18e7555a
AV		 4892int
4893qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
4894{
4895 int rval;
4896 mbx_cmd_t mc;
4897 mbx_cmd_t *mcp = &mc;
4898
5f28d2d7
SK		 4899 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
4900 "Entered %s.\n", __func__);
7c3df132 4901
18e7555a 4902 if (!IS_FWI2_CAPABLE(vha->hw))
6c452a45 4903 return QLA_FUNCTION_FAILED;
18e7555a 4904
18e7555a
AV		 4905 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
4906 mcp->mb[1] = LSW(risc_addr);
4907 mcp->mb[2] = LSW(data);
4908 mcp->mb[3] = MSW(data);
4909 mcp->mb[8] = MSW(risc_addr);
4910 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
4911 mcp->in_mb = MBX_0;
4912 mcp->tov = 30;
4913 mcp->flags = 0;
4914 rval = qla2x00_mailbox_command(vha, mcp);
4915 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4916 ql_dbg(ql_dbg_mbx, vha, 0x1101,
4917 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4918 } else {
5f28d2d7
SK		 4919 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
4920 "Done %s.\n", __func__);
18e7555a
AV		 4921 }
4922
4923 return rval;
4924}
3064ff39 4925
b1d46989
MI		 4926int
4927qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
4928{
4929 int rval;
4930 uint32_t stat, timer;
4931 uint16_t mb0 = 0;
4932 struct qla_hw_data *ha = vha->hw;
4933 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4934
4935 rval = QLA_SUCCESS;
4936
5f28d2d7
SK		 4937 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
4938 "Entered %s.\n", __func__);
b1d46989
MI		 4939
4940 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
4941
4942 /* Write the MBC data to the registers */
4943 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
4944 WRT_REG_WORD(&reg->mailbox1, mb[0]);
4945 WRT_REG_WORD(&reg->mailbox2, mb[1]);
4946 WRT_REG_WORD(&reg->mailbox3, mb[2]);
4947 WRT_REG_WORD(&reg->mailbox4, mb[3]);
4948
4949 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
4950
4951 /* Poll for MBC interrupt */
4952 for (timer = 6000000; timer; timer--) {
4953 /* Check for pending interrupts. */
4954 stat = RD_REG_DWORD(&reg->host_status);
4955 if (stat & HSRX_RISC_INT) {
4956 stat &= 0xff;
4957
4958 if (stat == 0x1 || stat == 0x2 ||
4959 stat == 0x10 || stat == 0x11) {
4960 set_bit(MBX_INTERRUPT,
4961 &ha->mbx_cmd_flags);
4962 mb0 = RD_REG_WORD(&reg->mailbox0);
4963 WRT_REG_DWORD(&reg->hccr,
4964 HCCRX_CLR_RISC_INT);
4965 RD_REG_DWORD(&reg->hccr);
4966 break;
4967 }
4968 }
4969 udelay(5);
4970 }
4971
4972 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
4973 rval = mb0 & MBS_MASK;
4974 else
4975 rval = QLA_FUNCTION_FAILED;
4976
4977 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4978 ql_dbg(ql_dbg_mbx, vha, 0x1104,
4979 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
b1d46989 4980 } else {
5f28d2d7
SK		 4981 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
4982 "Done %s.\n", __func__);
b1d46989
MI		 4983 }
4984
4985 return rval;
4986}
6246b8a1 4987
3064ff39
MH		 4988int
4989qla2x00_get_data_rate(scsi_qla_host_t *vha)
4990{
4991 int rval;
4992 mbx_cmd_t mc;
4993 mbx_cmd_t *mcp = &mc;
4994 struct qla_hw_data *ha = vha->hw;
4995
5f28d2d7
SK		 4996 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
4997 "Entered %s.\n", __func__);
7c3df132 4998
3064ff39
MH		 4999 if (!IS_FWI2_CAPABLE(ha))
5000 return QLA_FUNCTION_FAILED;
5001
3064ff39
MH		 5002 mcp->mb[0] = MBC_DATA_RATE;
5003 mcp->mb[1] = 0;
5004 mcp->out_mb = MBX_1|MBX_0;
5005 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 5006 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 5007 mcp->in_mb |= MBX_3;
3064ff39
MH		 5008 mcp->tov = MBX_TOV_SECONDS;
5009 mcp->flags = 0;
5010 rval = qla2x00_mailbox_command(vha, mcp);
5011 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5012 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5013 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3064ff39 5014 } else {
5f28d2d7
SK		 5015 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5016 "Done %s.\n", __func__);
3064ff39
MH		 5017 if (mcp->mb[1] != 0x7)
5018 ha->link_data_rate = mcp->mb[1];
5019 }
5020
5021 return rval;
5022}
09ff701a 5023
23f2ebd1
SR		 5024int
5025qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5026{
5027 int rval;
5028 mbx_cmd_t mc;
5029 mbx_cmd_t *mcp = &mc;
5030 struct qla_hw_data *ha = vha->hw;
5031
5f28d2d7
SK		 5032 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
5033 "Entered %s.\n", __func__);
23f2ebd1 5034
f73cb695
CD		 5035 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
5036 !IS_QLA27XX(ha))
23f2ebd1
SR		 5037 return QLA_FUNCTION_FAILED;
5038 mcp->mb[0] = MBC_GET_PORT_CONFIG;
5039 mcp->out_mb = MBX_0;
5040 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5041 mcp->tov = MBX_TOV_SECONDS;
5042 mcp->flags = 0;
5043
5044 rval = qla2x00_mailbox_command(vha, mcp);
5045
5046 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5047 ql_dbg(ql_dbg_mbx, vha, 0x110a,
5048 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1
SR		 5049 } else {
5050 /* Copy all bits to preserve original value */
5051 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
5052
5f28d2d7
SK		 5053 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
5054 "Done %s.\n", __func__);
23f2ebd1
SR		 5055 }
5056 return rval;
5057}
5058
5059int
5060qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5061{
5062 int rval;
5063 mbx_cmd_t mc;
5064 mbx_cmd_t *mcp = &mc;
5065
5f28d2d7
SK		 5066 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
5067 "Entered %s.\n", __func__);
23f2ebd1
SR		 5068
5069 mcp->mb[0] = MBC_SET_PORT_CONFIG;
5070 /* Copy all bits to preserve original setting */
5071 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
5072 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5073 mcp->in_mb = MBX_0;
5074 mcp->tov = MBX_TOV_SECONDS;
5075 mcp->flags = 0;
5076 rval = qla2x00_mailbox_command(vha, mcp);
5077
5078 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5079 ql_dbg(ql_dbg_mbx, vha, 0x110d,
5080 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1 5081 } else
5f28d2d7
SK		 5082 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
5083 "Done %s.\n", __func__);
23f2ebd1
SR		 5084
5085 return rval;
5086}
5087
5088
09ff701a
SR		 5089int
5090qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
5091 uint16_t *mb)
5092{
5093 int rval;
5094 mbx_cmd_t mc;
5095 mbx_cmd_t *mcp = &mc;
5096 struct qla_hw_data *ha = vha->hw;
5097
5f28d2d7
SK		 5098 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
5099 "Entered %s.\n", __func__);
7c3df132 5100
09ff701a
SR		 5101 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
5102 return QLA_FUNCTION_FAILED;
5103
09ff701a
SR		 5104 mcp->mb[0] = MBC_PORT_PARAMS;
5105 mcp->mb[1] = loop_id;
5106 if (ha->flags.fcp_prio_enabled)
5107 mcp->mb[2] = BIT_1;
5108 else
5109 mcp->mb[2] = BIT_2;
5110 mcp->mb[4] = priority & 0xf;
5111 mcp->mb[9] = vha->vp_idx;
5112 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5113 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5114 mcp->tov = 30;
5115 mcp->flags = 0;
5116 rval = qla2x00_mailbox_command(vha, mcp);
5117 if (mb != NULL) {
5118 mb[0] = mcp->mb[0];
5119 mb[1] = mcp->mb[1];
5120 mb[3] = mcp->mb[3];
5121 mb[4] = mcp->mb[4];
5122 }
5123
5124 if (rval != QLA_SUCCESS) {
7c3df132 5125 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
09ff701a 5126 } else {
5f28d2d7
SK		 5127 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
5128 "Done %s.\n", __func__);
09ff701a
SR		 5129 }
5130
5131 return rval;
5132}
a9083016 5133
794a5691 5134int
fe52f6e1 5135qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
794a5691 5136{
fe52f6e1 5137 int rval = QLA_FUNCTION_FAILED;
794a5691 5138 struct qla_hw_data *ha = vha->hw;
fe52f6e1 5139 uint8_t byte;
794a5691 5140
1ae47cf3
JC		 5141 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
5142 ql_dbg(ql_dbg_mbx, vha, 0x1150,
5143 "Thermal not supported by this card.\n");
5144 return rval;
5145 }
5146
5147 if (IS_QLA25XX(ha)) {
5148 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5149 ha->pdev->subsystem_device == 0x0175) {
5150 rval = qla2x00_read_sfp(vha, 0, &byte,
5151 0x98, 0x1, 1, BIT_13|BIT_0);
5152 *temp = byte;
5153 return rval;
5154 }
5155 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
5156 ha->pdev->subsystem_device == 0x338e) {
5157 rval = qla2x00_read_sfp(vha, 0, &byte,
5158 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
5159 *temp = byte;
5160 return rval;
5161 }
5162 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
5163 "Thermal not supported by this card.\n");
5164 return rval;
794a5691 5165 }
794a5691 5166
1ae47cf3
JC		 5167 if (IS_QLA82XX(ha)) {
5168 *temp = qla82xx_read_temperature(vha);
5169 rval = QLA_SUCCESS;
5170 return rval;
5171 } else if (IS_QLA8044(ha)) {
5172 *temp = qla8044_read_temperature(vha);
5173 rval = QLA_SUCCESS;
5174 return rval;
794a5691 5175 }
794a5691 5176
1ae47cf3 5177 rval = qla2x00_read_asic_temperature(vha, temp);
794a5691
AV		 5178 return rval;
5179}
5180
a9083016
GM		 5181int
5182qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
5183{
5184 int rval;
5185 struct qla_hw_data *ha = vha->hw;
5186 mbx_cmd_t mc;
5187 mbx_cmd_t *mcp = &mc;
5188
5f28d2d7
SK		 5189 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
5190 "Entered %s.\n", __func__);
7c3df132 5191
a9083016
GM		 5192 if (!IS_FWI2_CAPABLE(ha))
5193 return QLA_FUNCTION_FAILED;
5194
a9083016 5195 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5196 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5197 mcp->mb[1] = 1;
5198
5199 mcp->out_mb = MBX_1|MBX_0;
5200 mcp->in_mb = MBX_0;
5201 mcp->tov = 30;
5202 mcp->flags = 0;
5203
5204 rval = qla2x00_mailbox_command(vha, mcp);
5205 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5206 ql_dbg(ql_dbg_mbx, vha, 0x1016,
5207 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5208 } else {
5f28d2d7
SK		 5209 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
5210 "Done %s.\n", __func__);
a9083016
GM		 5211 }
5212
5213 return rval;
5214}
5215
5216int
5217qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
5218{
5219 int rval;
5220 struct qla_hw_data *ha = vha->hw;
5221 mbx_cmd_t mc;
5222 mbx_cmd_t *mcp = &mc;
5223
5f28d2d7
SK		 5224 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
5225 "Entered %s.\n", __func__);
7c3df132 5226
7ec0effd 5227 if (!IS_P3P_TYPE(ha))
a9083016
GM		 5228 return QLA_FUNCTION_FAILED;
5229
a9083016 5230 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5231 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5232 mcp->mb[1] = 0;
5233
5234 mcp->out_mb = MBX_1|MBX_0;
5235 mcp->in_mb = MBX_0;
5236 mcp->tov = 30;
5237 mcp->flags = 0;
5238
5239 rval = qla2x00_mailbox_command(vha, mcp);
5240 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5241 ql_dbg(ql_dbg_mbx, vha, 0x100c,
5242 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5243 } else {
5f28d2d7
SK		 5244 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
5245 "Done %s.\n", __func__);
a9083016
GM		 5246 }
5247
5248 return rval;
5249}
08de2844
GM		 5250
5251int
5252qla82xx_md_get_template_size(scsi_qla_host_t *vha)
5253{
5254 struct qla_hw_data *ha = vha->hw;
5255 mbx_cmd_t mc;
5256 mbx_cmd_t *mcp = &mc;
5257 int rval = QLA_FUNCTION_FAILED;
5258
5f28d2d7
SK		 5259 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
5260 "Entered %s.\n", __func__);
08de2844
GM		 5261
5262 memset(mcp->mb, 0 , sizeof(mcp->mb));
5263 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5264 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5265 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
5266 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
5267
5268 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5269 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
5270 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5271
5272 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5273 mcp->tov = MBX_TOV_SECONDS;
5274 rval = qla2x00_mailbox_command(vha, mcp);
5275
5276 /* Always copy back return mailbox values. */
5277 if (rval != QLA_SUCCESS) {
5278 ql_dbg(ql_dbg_mbx, vha, 0x1120,
5279 "mailbox command FAILED=0x%x, subcode=%x.\n",
5280 (mcp->mb[1] << 16) | mcp->mb[0],
5281 (mcp->mb[3] << 16) | mcp->mb[2]);
5282 } else {
5f28d2d7
SK		 5283 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
5284 "Done %s.\n", __func__);
08de2844
GM		 5285 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
5286 if (!ha->md_template_size) {
5287 ql_dbg(ql_dbg_mbx, vha, 0x1122,
5288 "Null template size obtained.\n");
5289 rval = QLA_FUNCTION_FAILED;
5290 }
5291 }
5292 return rval;
5293}
5294
5295int
5296qla82xx_md_get_template(scsi_qla_host_t *vha)
5297{
5298 struct qla_hw_data *ha = vha->hw;
5299 mbx_cmd_t mc;
5300 mbx_cmd_t *mcp = &mc;
5301 int rval = QLA_FUNCTION_FAILED;
5302
5f28d2d7
SK		 5303 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
5304 "Entered %s.\n", __func__);
08de2844
GM		 5305
5306 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5307 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5308 if (!ha->md_tmplt_hdr) {
5309 ql_log(ql_log_warn, vha, 0x1124,
5310 "Unable to allocate memory for Minidump template.\n");
5311 return rval;
5312 }
5313
5314 memset(mcp->mb, 0 , sizeof(mcp->mb));
5315 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5316 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5317 mcp->mb[2] = LSW(RQST_TMPLT);
5318 mcp->mb[3] = MSW(RQST_TMPLT);
5319 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5320 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5321 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5322 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5323 mcp->mb[8] = LSW(ha->md_template_size);
5324 mcp->mb[9] = MSW(ha->md_template_size);
5325
5326 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5327 mcp->tov = MBX_TOV_SECONDS;
5328 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5329 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5330 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5331 rval = qla2x00_mailbox_command(vha, mcp);
5332
5333 if (rval != QLA_SUCCESS) {
5334 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5335 "mailbox command FAILED=0x%x, subcode=%x.\n",
5336 ((mcp->mb[1] << 16) | mcp->mb[0]),
5337 ((mcp->mb[3] << 16) | mcp->mb[2]));
5338 } else
5f28d2d7
SK		 5339 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5340 "Done %s.\n", __func__);
08de2844
GM		 5341 return rval;
5342}
999916dc 5343
7ec0effd
AD		 5344int
5345qla8044_md_get_template(scsi_qla_host_t *vha)
5346{
5347 struct qla_hw_data *ha = vha->hw;
5348 mbx_cmd_t mc;
5349 mbx_cmd_t *mcp = &mc;
5350 int rval = QLA_FUNCTION_FAILED;
5351 int offset = 0, size = MINIDUMP_SIZE_36K;
5352 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5353 "Entered %s.\n", __func__);
5354
5355 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5356 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5357 if (!ha->md_tmplt_hdr) {
5358 ql_log(ql_log_warn, vha, 0xb11b,
5359 "Unable to allocate memory for Minidump template.\n");
5360 return rval;
5361 }
5362
5363 memset(mcp->mb, 0 , sizeof(mcp->mb));
5364 while (offset < ha->md_template_size) {
5365 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5366 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5367 mcp->mb[2] = LSW(RQST_TMPLT);
5368 mcp->mb[3] = MSW(RQST_TMPLT);
5369 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5370 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5371 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5372 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5373 mcp->mb[8] = LSW(size);
5374 mcp->mb[9] = MSW(size);
5375 mcp->mb[10] = offset & 0x0000FFFF;
5376 mcp->mb[11] = offset & 0xFFFF0000;
5377 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5378 mcp->tov = MBX_TOV_SECONDS;
5379 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5380 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5381 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5382 rval = qla2x00_mailbox_command(vha, mcp);
5383
5384 if (rval != QLA_SUCCESS) {
5385 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5386 "mailbox command FAILED=0x%x, subcode=%x.\n",
5387 ((mcp->mb[1] << 16) | mcp->mb[0]),
5388 ((mcp->mb[3] << 16) | mcp->mb[2]));
5389 return rval;
5390 } else
5391 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5392 "Done %s.\n", __func__);
5393 offset = offset + size;
5394 }
5395 return rval;
5396}
5397
6246b8a1
GM		 5398int
5399qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5400{
5401 int rval;
5402 struct qla_hw_data *ha = vha->hw;
5403 mbx_cmd_t mc;
5404 mbx_cmd_t *mcp = &mc;
5405
5406 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5407 return QLA_FUNCTION_FAILED;
5408
5f28d2d7
SK		 5409 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5410 "Entered %s.\n", __func__);
6246b8a1
GM		 5411
5412 memset(mcp, 0, sizeof(mbx_cmd_t));
5413 mcp->mb[0] = MBC_SET_LED_CONFIG;
5414 mcp->mb[1] = led_cfg[0];
5415 mcp->mb[2] = led_cfg[1];
5416 if (IS_QLA8031(ha)) {
5417 mcp->mb[3] = led_cfg[2];
5418 mcp->mb[4] = led_cfg[3];
5419 mcp->mb[5] = led_cfg[4];
5420 mcp->mb[6] = led_cfg[5];
5421 }
5422
5423 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5424 if (IS_QLA8031(ha))
5425 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5426 mcp->in_mb = MBX_0;
5427 mcp->tov = 30;
5428 mcp->flags = 0;
5429
5430 rval = qla2x00_mailbox_command(vha, mcp);
5431 if (rval != QLA_SUCCESS) {
5432 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5433 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5434 } else {
5f28d2d7
SK		 5435 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5436 "Done %s.\n", __func__);
6246b8a1
GM		 5437 }
5438
5439 return rval;
5440}
5441
5442int
5443qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5444{
5445 int rval;
5446 struct qla_hw_data *ha = vha->hw;
5447 mbx_cmd_t mc;
5448 mbx_cmd_t *mcp = &mc;
5449
5450 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5451 return QLA_FUNCTION_FAILED;
5452
5f28d2d7
SK		 5453 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
5454 "Entered %s.\n", __func__);
6246b8a1
GM		 5455
5456 memset(mcp, 0, sizeof(mbx_cmd_t));
5457 mcp->mb[0] = MBC_GET_LED_CONFIG;
5458
5459 mcp->out_mb = MBX_0;
5460 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5461 if (IS_QLA8031(ha))
5462 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5463 mcp->tov = 30;
5464 mcp->flags = 0;
5465
5466 rval = qla2x00_mailbox_command(vha, mcp);
5467 if (rval != QLA_SUCCESS) {
5468 ql_dbg(ql_dbg_mbx, vha, 0x1137,
5469 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5470 } else {
5471 led_cfg[0] = mcp->mb[1];
5472 led_cfg[1] = mcp->mb[2];
5473 if (IS_QLA8031(ha)) {
5474 led_cfg[2] = mcp->mb[3];
5475 led_cfg[3] = mcp->mb[4];
5476 led_cfg[4] = mcp->mb[5];
5477 led_cfg[5] = mcp->mb[6];
5478 }
5f28d2d7
SK		 5479 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
5480 "Done %s.\n", __func__);
6246b8a1
GM		 5481 }
5482
5483 return rval;
5484}
5485
999916dc
SK		 5486int
5487qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
5488{
5489 int rval;
5490 struct qla_hw_data *ha = vha->hw;
5491 mbx_cmd_t mc;
5492 mbx_cmd_t *mcp = &mc;
5493
7ec0effd 5494 if (!IS_P3P_TYPE(ha))
999916dc
SK		 5495 return QLA_FUNCTION_FAILED;
5496
5f28d2d7 5497 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
999916dc
SK		 5498 "Entered %s.\n", __func__);
5499
5500 memset(mcp, 0, sizeof(mbx_cmd_t));
5501 mcp->mb[0] = MBC_SET_LED_CONFIG;
5502 if (enable)
5503 mcp->mb[7] = 0xE;
5504 else
5505 mcp->mb[7] = 0xD;
5506
5507 mcp->out_mb = MBX_7|MBX_0;
5508 mcp->in_mb = MBX_0;
6246b8a1 5509 mcp->tov = MBX_TOV_SECONDS;
999916dc
SK		 5510 mcp->flags = 0;
5511
5512 rval = qla2x00_mailbox_command(vha, mcp);
5513 if (rval != QLA_SUCCESS) {
5514 ql_dbg(ql_dbg_mbx, vha, 0x1128,
5515 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5516 } else {
5f28d2d7 5517 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
999916dc
SK		 5518 "Done %s.\n", __func__);
5519 }
5520
5521 return rval;
5522}
6246b8a1
GM		 5523
5524int
7d613ac6 5525qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6246b8a1
GM		 5526{
5527 int rval;
5528 struct qla_hw_data *ha = vha->hw;
5529 mbx_cmd_t mc;
5530 mbx_cmd_t *mcp = &mc;
5531
f73cb695 5532 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1
GM		 5533 return QLA_FUNCTION_FAILED;
5534
5f28d2d7
SK		 5535 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5536 "Entered %s.\n", __func__);
6246b8a1
GM		 5537
5538 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5539 mcp->mb[1] = LSW(reg);
5540 mcp->mb[2] = MSW(reg);
5541 mcp->mb[3] = LSW(data);
5542 mcp->mb[4] = MSW(data);
5543 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5544
5545 mcp->in_mb = MBX_1|MBX_0;
5546 mcp->tov = MBX_TOV_SECONDS;
5547 mcp->flags = 0;
5548 rval = qla2x00_mailbox_command(vha, mcp);
5549
5550 if (rval != QLA_SUCCESS) {
5551 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5552 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5553 } else {
5f28d2d7 5554 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6246b8a1
GM		 5555 "Done %s.\n", __func__);
5556 }
af11f64d 5557
6246b8a1
GM		 5558 return rval;
5559}
af11f64d
AV		 5560
5561int
5562qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5563{
5564 int rval;
5565 struct qla_hw_data *ha = vha->hw;
5566 mbx_cmd_t mc;
5567 mbx_cmd_t *mcp = &mc;
5568
5569 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5f28d2d7 5570 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
af11f64d
AV		 5571 "Implicit LOGO Unsupported.\n");
5572 return QLA_FUNCTION_FAILED;
5573 }
5574
5575
5f28d2d7
SK		 5576 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5577 "Entering %s.\n", __func__);
af11f64d
AV		 5578
5579 /* Perform Implicit LOGO. */
5580 mcp->mb[0] = MBC_PORT_LOGOUT;
5581 mcp->mb[1] = fcport->loop_id;
5582 mcp->mb[10] = BIT_15;
5583 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5584 mcp->in_mb = MBX_0;
5585 mcp->tov = MBX_TOV_SECONDS;
5586 mcp->flags = 0;
5587 rval = qla2x00_mailbox_command(vha, mcp);
5588 if (rval != QLA_SUCCESS)
5589 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5590 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5591 else
5f28d2d7
SK		 5592 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5593 "Done %s.\n", __func__);
af11f64d
AV		 5594
5595 return rval;
5596}
5597
7d613ac6
SV		 5598int
5599qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5600{
5601 int rval;
5602 mbx_cmd_t mc;
5603 mbx_cmd_t *mcp = &mc;
5604 struct qla_hw_data *ha = vha->hw;
5605 unsigned long retry_max_time = jiffies + (2 * HZ);
5606
f73cb695 5607 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5608 return QLA_FUNCTION_FAILED;
5609
5610 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5611
5612retry_rd_reg:
5613 mcp->mb[0] = MBC_READ_REMOTE_REG;
5614 mcp->mb[1] = LSW(reg);
5615 mcp->mb[2] = MSW(reg);
5616 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5617 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5618 mcp->tov = MBX_TOV_SECONDS;
5619 mcp->flags = 0;
5620 rval = qla2x00_mailbox_command(vha, mcp);
5621
5622 if (rval != QLA_SUCCESS) {
5623 ql_dbg(ql_dbg_mbx, vha, 0x114c,
5624 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5625 rval, mcp->mb[0], mcp->mb[1]);
5626 } else {
5627 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
5628 if (*data == QLA8XXX_BAD_VALUE) {
5629 /*
5630 * During soft-reset CAMRAM register reads might
5631 * return 0xbad0bad0. So retry for MAX of 2 sec
5632 * while reading camram registers.
5633 */
5634 if (time_after(jiffies, retry_max_time)) {
5635 ql_dbg(ql_dbg_mbx, vha, 0x1141,
5636 "Failure to read CAMRAM register. "
5637 "data=0x%x.\n", *data);
5638 return QLA_FUNCTION_FAILED;
5639 }
5640 msleep(100);
5641 goto retry_rd_reg;
5642 }
5643 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
5644 }
5645
5646 return rval;
5647}
5648
5649int
5650qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
5651{
5652 int rval;
5653 mbx_cmd_t mc;
5654 mbx_cmd_t *mcp = &mc;
5655 struct qla_hw_data *ha = vha->hw;
5656
b20f02e1 5657 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5658 return QLA_FUNCTION_FAILED;
5659
5660 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
5661
5662 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
5663 mcp->out_mb = MBX_0;
5664 mcp->in_mb = MBX_1|MBX_0;
5665 mcp->tov = MBX_TOV_SECONDS;
5666 mcp->flags = 0;
5667 rval = qla2x00_mailbox_command(vha, mcp);
5668
5669 if (rval != QLA_SUCCESS) {
5670 ql_dbg(ql_dbg_mbx, vha, 0x1144,
5671 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5672 rval, mcp->mb[0], mcp->mb[1]);
5673 ha->isp_ops->fw_dump(vha, 0);
5674 } else {
5675 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5676 }
5677
5678 return rval;
5679}
5680
5681int
5682qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
5683 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
5684{
5685 int rval;
5686 mbx_cmd_t mc;
5687 mbx_cmd_t *mcp = &mc;
5688 uint8_t subcode = (uint8_t)options;
5689 struct qla_hw_data *ha = vha->hw;
5690
5691 if (!IS_QLA8031(ha))
5692 return QLA_FUNCTION_FAILED;
5693
5694 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
5695
5696 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
5697 mcp->mb[1] = options;
5698 mcp->out_mb = MBX_1|MBX_0;
5699 if (subcode & BIT_2) {
5700 mcp->mb[2] = LSW(start_addr);
5701 mcp->mb[3] = MSW(start_addr);
5702 mcp->mb[4] = LSW(end_addr);
5703 mcp->mb[5] = MSW(end_addr);
5704 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
5705 }
5706 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5707 if (!(subcode & (BIT_2 | BIT_5)))
5708 mcp->in_mb |= MBX_4|MBX_3;
5709 mcp->tov = MBX_TOV_SECONDS;
5710 mcp->flags = 0;
5711 rval = qla2x00_mailbox_command(vha, mcp);
5712
5713 if (rval != QLA_SUCCESS) {
5714 ql_dbg(ql_dbg_mbx, vha, 0x1147,
5715 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5716 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5717 mcp->mb[4]);
5718 ha->isp_ops->fw_dump(vha, 0);
5719 } else {
5720 if (subcode & BIT_5)
5721 *sector_size = mcp->mb[1];
5722 else if (subcode & (BIT_6 | BIT_7)) {
5723 ql_dbg(ql_dbg_mbx, vha, 0x1148,
5724 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5725 } else if (subcode & (BIT_3 | BIT_4)) {
5726 ql_dbg(ql_dbg_mbx, vha, 0x1149,
5727 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5728 }
5729 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5730 }
5731
5732 return rval;
5733}
81178772
SK		 5734
5735int
5736qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
5737 uint32_t size)
5738{
5739 int rval;
5740 mbx_cmd_t mc;
5741 mbx_cmd_t *mcp = &mc;
5742
5743 if (!IS_MCTP_CAPABLE(vha->hw))
5744 return QLA_FUNCTION_FAILED;
5745
5746 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
5747 "Entered %s.\n", __func__);
5748
5749 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
5750 mcp->mb[1] = LSW(addr);
5751 mcp->mb[2] = MSW(req_dma);
5752 mcp->mb[3] = LSW(req_dma);
5753 mcp->mb[4] = MSW(size);
5754 mcp->mb[5] = LSW(size);
5755 mcp->mb[6] = MSW(MSD(req_dma));
5756 mcp->mb[7] = LSW(MSD(req_dma));
5757 mcp->mb[8] = MSW(addr);
5758 /* Setting RAM ID to valid */
5759 mcp->mb[10] |= BIT_7;
5760 /* For MCTP RAM ID is 0x40 */
5761 mcp->mb[10] |= 0x40;
5762
5763 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
5764 MBX_0;
5765
5766 mcp->in_mb = MBX_0;
5767 mcp->tov = MBX_TOV_SECONDS;
5768 mcp->flags = 0;
5769 rval = qla2x00_mailbox_command(vha, mcp);
5770
5771 if (rval != QLA_SUCCESS) {
5772 ql_dbg(ql_dbg_mbx, vha, 0x114e,
5773 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5774 } else {
5775 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
5776 "Done %s.\n", __func__);
5777 }
5778
5779 return rval;
5780}
ec891462
JC		 5781
5782int
5783qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
5784 void *dd_buf, uint size, uint options)
5785{
5786 int rval;
5787 mbx_cmd_t mc;
5788 mbx_cmd_t *mcp = &mc;
5789 dma_addr_t dd_dma;
5790
5791 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
5792 return QLA_FUNCTION_FAILED;
5793
83548fe2 5794 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
ec891462
JC		 5795 "Entered %s.\n", __func__);
5796
ec891462
JC		 5797 dd_dma = dma_map_single(&vha->hw->pdev->dev,
5798 dd_buf, size, DMA_FROM_DEVICE);
5799 if (!dd_dma) {
5800 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
5801 return QLA_MEMORY_ALLOC_FAILED;
5802 }
5803
5804 memset(dd_buf, 0, size);
5805
5806 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
5807 mcp->mb[1] = options;
5808 mcp->mb[2] = MSW(LSD(dd_dma));
5809 mcp->mb[3] = LSW(LSD(dd_dma));
5810 mcp->mb[6] = MSW(MSD(dd_dma));
5811 mcp->mb[7] = LSW(MSD(dd_dma));
5812 mcp->mb[8] = size;
5813 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5814 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5815 mcp->buf_size = size;
5816 mcp->flags = MBX_DMA_IN;
5817 mcp->tov = MBX_TOV_SECONDS * 4;
5818 rval = qla2x00_mailbox_command(vha, mcp);
5819
5820 if (rval != QLA_SUCCESS) {
5821 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
5822 } else {
5823 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
5824 "Done %s.\n", __func__);
5825 }
5826
5827 dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
5828 size, DMA_FROM_DEVICE);
5829
5830 return rval;
5831}
15f30a57
QT		 5832
5833static void qla2x00_async_mb_sp_done(void *s, int res)
5834{
5835 struct srb *sp = s;
5836
5837 sp->u.iocb_cmd.u.mbx.rc = res;
5838
5839 complete(&sp->u.iocb_cmd.u.mbx.comp);
5840 /* don't free sp here. Let the caller do the free */
5841}
5842
5843/*
5844 * This mailbox uses the iocb interface to send MB command.
5845 * This allows non-critial (non chip setup) command to go
5846 * out in parrallel.
5847 */
5848int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp)
5849{
5850 int rval = QLA_FUNCTION_FAILED;
5851 srb_t *sp;
5852 struct srb_iocb *c;
5853
5854 if (!vha->hw->flags.fw_started)
5855 goto done;
5856
5857 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
5858 if (!sp)
5859 goto done;
5860
5861 sp->type = SRB_MB_IOCB;
5862 sp->name = mb_to_str(mcp->mb[0]);
5863
5864 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
5865
5866 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
5867
5868 c = &sp->u.iocb_cmd;
5869 c->timeout = qla2x00_async_iocb_timeout;
5870 init_completion(&c->u.mbx.comp);
5871
5872 sp->done = qla2x00_async_mb_sp_done;
5873
5874 rval = qla2x00_start_sp(sp);
5875 if (rval != QLA_SUCCESS) {
83548fe2 5876 ql_dbg(ql_dbg_mbx, vha, 0x1018,
15f30a57
QT		 5877 "%s: %s Failed submission. %x.\n",
5878 __func__, sp->name, rval);
5879 goto done_free_sp;
5880 }
5881
83548fe2 5882 ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n",
15f30a57
QT		 5883 sp->name, sp->handle);
5884
5885 wait_for_completion(&c->u.mbx.comp);
5886 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
5887
5888 rval = c->u.mbx.rc;
5889 switch (rval) {
5890 case QLA_FUNCTION_TIMEOUT:
83548fe2 5891 ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n",
15f30a57
QT		 5892 __func__, sp->name, rval);
5893 break;
5894 case QLA_SUCCESS:
83548fe2 5895 ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n",
15f30a57
QT		 5896 __func__, sp->name);
5897 sp->free(sp);
5898 break;
5899 default:
83548fe2 5900 ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n",
15f30a57
QT		 5901 __func__, sp->name, rval);
5902 sp->free(sp);
5903 break;
5904 }
5905
5906 return rval;
5907
5908done_free_sp:
5909 sp->free(sp);
5910done:
5911 return rval;
5912}
5913
5914/*
5915 * qla24xx_gpdb_wait
5916 * NOTE: Do not call this routine from DPC thread
5917 */
5918int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
5919{
5920 int rval = QLA_FUNCTION_FAILED;
5921 dma_addr_t pd_dma;
5922 struct port_database_24xx *pd;
5923 struct qla_hw_data *ha = vha->hw;
5924 mbx_cmd_t mc;
5925
5926 if (!vha->hw->flags.fw_started)
5927 goto done;
5928
5929 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
5930 if (pd == NULL) {
83548fe2
QT		 5931 ql_log(ql_log_warn, vha, 0xd047,
5932 "Failed to allocate port database structure.\n");
15f30a57
QT		 5933 goto done_free_sp;
5934 }
5935 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
5936
5937 memset(&mc, 0, sizeof(mc));
5938 mc.mb[0] = MBC_GET_PORT_DATABASE;
5939 mc.mb[1] = cpu_to_le16(fcport->loop_id);
5940 mc.mb[2] = MSW(pd_dma);
5941 mc.mb[3] = LSW(pd_dma);
5942 mc.mb[6] = MSW(MSD(pd_dma));
5943 mc.mb[7] = LSW(MSD(pd_dma));
5944 mc.mb[9] = cpu_to_le16(vha->vp_idx);
5945 mc.mb[10] = cpu_to_le16((uint16_t)opt);
5946
5947 rval = qla24xx_send_mb_cmd(vha, &mc);
5948 if (rval != QLA_SUCCESS) {
83548fe2 5949 ql_dbg(ql_dbg_mbx, vha, 0x1193,
15f30a57
QT		 5950 "%s: %8phC fail\n", __func__, fcport->port_name);
5951 goto done_free_sp;
5952 }
5953
5954 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
5955
83548fe2 5956 ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n",
15f30a57
QT		 5957 __func__, fcport->port_name);
5958
5959done_free_sp:
5960 if (pd)
5961 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
5962done:
5963 return rval;
5964}
5965
5966int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport,
5967 struct port_database_24xx *pd)
5968{
5969 int rval = QLA_SUCCESS;
5970 uint64_t zero = 0;
5971
5972 /* Check for logged in state. */
5973 if (pd->current_login_state != PDS_PRLI_COMPLETE &&
5974 pd->last_login_state != PDS_PRLI_COMPLETE) {
83548fe2
QT		 5975 ql_dbg(ql_dbg_mbx, vha, 0x119a,
5976 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
5977 pd->current_login_state, pd->last_login_state,
5978 fcport->loop_id);
15f30a57
QT		 5979 rval = QLA_FUNCTION_FAILED;
5980 goto gpd_error_out;
5981 }
5982
5983 if (fcport->loop_id == FC_NO_LOOP_ID ||
5984 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
5985 memcmp(fcport->port_name, pd->port_name, 8))) {
5986 /* We lost the device mid way. */
5987 rval = QLA_NOT_LOGGED_IN;
5988 goto gpd_error_out;
5989 }
5990
5991 /* Names are little-endian. */
5992 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
5993 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
5994
5995 /* Get port_id of device. */
5996 fcport->d_id.b.domain = pd->port_id[0];
5997 fcport->d_id.b.area = pd->port_id[1];
5998 fcport->d_id.b.al_pa = pd->port_id[2];
5999 fcport->d_id.b.rsvd_1 = 0;
6000
6001 /* If not target must be initiator or unknown type. */
6002 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6003 fcport->port_type = FCT_INITIATOR;
6004 else
6005 fcport->port_type = FCT_TARGET;
6006
6007 /* Passback COS information. */
6008 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
6009 FC_COS_CLASS2 : FC_COS_CLASS3;
6010
6011 if (pd->prli_svc_param_word_3[0] & BIT_7) {
6012 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
6013 fcport->conf_compl_supported = 1;
6014 }
6015
6016gpd_error_out:
6017 return rval;
6018}
6019
6020/*
6021 * qla24xx_gidlist__wait
6022 * NOTE: don't call this routine from DPC thread.
6023 */
6024int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
6025 void *id_list, dma_addr_t id_list_dma, uint16_t *entries)
6026{
6027 int rval = QLA_FUNCTION_FAILED;
6028 mbx_cmd_t mc;
6029
6030 if (!vha->hw->flags.fw_started)
6031 goto done;
6032
6033 memset(&mc, 0, sizeof(mc));
6034 mc.mb[0] = MBC_GET_ID_LIST;
6035 mc.mb[2] = MSW(id_list_dma);
6036 mc.mb[3] = LSW(id_list_dma);
6037 mc.mb[6] = MSW(MSD(id_list_dma));
6038 mc.mb[7] = LSW(MSD(id_list_dma));
6039 mc.mb[8] = 0;
6040 mc.mb[9] = cpu_to_le16(vha->vp_idx);
6041
6042 rval = qla24xx_send_mb_cmd(vha, &mc);
6043 if (rval != QLA_SUCCESS) {
83548fe2
QT		 6044 ql_dbg(ql_dbg_mbx, vha, 0x119b,
6045 "%s: fail\n", __func__);
15f30a57
QT		 6046 } else {
6047 *entries = mc.mb[1];
83548fe2
QT		 6048 ql_dbg(ql_dbg_mbx, vha, 0x119c,
6049 "%s: done\n", __func__);
15f30a57
QT		 6050 }
6051done:
6052 return rval;
6053}
Linux 6.x block layer and io_uring tree(s)