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[SCSI] qla2xxx: Update the FTP site references in the driver sources.
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_init_rings(scsi_qla_host_t *);
29static int qla2x00_fw_ready(scsi_qla_host_t *);
30static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 31static int qla2x00_configure_loop(scsi_qla_host_t *);
32static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 33static int qla2x00_configure_fabric(scsi_qla_host_t *);
34static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 35static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
36 uint16_t *);
1da177e4
LT		 37
38static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 39
4d4df193
HK		 40static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
41static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 42static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 43
ac280b67
AV		 44/* SRB Extensions ---------------------------------------------------------- */
45
9ba56b95
GM		 46void
47qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 48{
49 srb_t *sp = (srb_t *)__data;
4916392b 50 struct srb_iocb *iocb;
ac280b67
AV		 51 fc_port_t *fcport = sp->fcport;
52 struct qla_hw_data *ha = fcport->vha->hw;
53 struct req_que *req;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ha->hardware_lock, flags);
57 req = ha->req_q_map[0];
58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
9ba56b95 61 sp->free(fcport->vha, sp);
6ac52608 62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95
GM		 65void
66qla2x00_sp_free(void *data, void *ptr)
ac280b67 67{
9ba56b95
GM		 68 srb_t *sp = (srb_t *)ptr;
69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
70 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 71
4d97cc53 72 del_timer(&iocb->timer);
9ba56b95 73 mempool_free(sp, vha->hw->srb_mempool);
feafb7b1
AE		 74
75 QLA_VHA_MARK_NOT_BUSY(vha);
ac280b67
AV		 76}
77
ac280b67
AV		 78/* Asynchronous Login/Logout Routines -------------------------------------- */
79
a9b6f722 80unsigned long
5b91490e
AV		 81qla2x00_get_async_timeout(struct scsi_qla_host *vha)
82{
83 unsigned long tmo;
84 struct qla_hw_data *ha = vha->hw;
85
86 /* Firmware should use switch negotiated r_a_tov for timeout. */
87 tmo = ha->r_a_tov / 10 * 2;
88 if (!IS_FWI2_CAPABLE(ha)) {
89 /*
90 * Except for earlier ISPs where the timeout is seeded from the
91 * initialization control block.
92 */
93 tmo = ha->login_timeout;
94 }
95 return tmo;
96}
ac280b67
AV		 97
98static void
9ba56b95 99qla2x00_async_iocb_timeout(void *data)
ac280b67 100{
9ba56b95 101 srb_t *sp = (srb_t *)data;
ac280b67 102 fc_port_t *fcport = sp->fcport;
ac280b67 103
7c3df132 104 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 105 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 106 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 107 fcport->d_id.b.al_pa);
ac280b67 108
5ff1d584 109 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 110 if (sp->type == SRB_LOGIN_CMD) {
111 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 112 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 113 /* Retry as needed. */
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
117 qla2x00_post_async_login_done_work(fcport->vha, fcport,
118 lio->u.logio.data);
119 }
ac280b67
AV		 120}
121
99b0bec7 122static void
9ba56b95 123qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 124{
9ba56b95
GM		 125 srb_t *sp = (srb_t *)ptr;
126 struct srb_iocb *lio = &sp->u.iocb_cmd;
127 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
128
129 if (!test_bit(UNLOADING, &vha->dpc_flags))
130 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
131 lio->u.logio.data);
132 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 133}
134
ac280b67
AV		 135int
136qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
137 uint16_t *data)
138{
ac280b67 139 srb_t *sp;
4916392b 140 struct srb_iocb *lio;
ac280b67
AV		 141 int rval;
142
143 rval = QLA_FUNCTION_FAILED;
9ba56b95 144 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 145 if (!sp)
146 goto done;
147
9ba56b95
GM		 148 sp->type = SRB_LOGIN_CMD;
149 sp->name = "login";
150 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
151
152 lio = &sp->u.iocb_cmd;
3822263e 153 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 154 sp->done = qla2x00_async_login_sp_done;
4916392b 155 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 156 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 157 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 158 rval = qla2x00_start_sp(sp);
159 if (rval != QLA_SUCCESS)
160 goto done_free_sp;
161
7c3df132 162 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 163 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
164 "retries=%d.\n", sp->handle, fcport->loop_id,
165 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
166 fcport->login_retry);
ac280b67
AV		 167 return rval;
168
169done_free_sp:
9ba56b95 170 sp->free(fcport->vha, sp);
ac280b67
AV		 171done:
172 return rval;
173}
174
99b0bec7 175static void
9ba56b95 176qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 177{
9ba56b95
GM		 178 srb_t *sp = (srb_t *)ptr;
179 struct srb_iocb *lio = &sp->u.iocb_cmd;
180 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
181
182 if (!test_bit(UNLOADING, &vha->dpc_flags))
183 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
184 lio->u.logio.data);
185 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 186}
187
ac280b67
AV		 188int
189qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
190{
ac280b67 191 srb_t *sp;
4916392b 192 struct srb_iocb *lio;
ac280b67
AV		 193 int rval;
194
195 rval = QLA_FUNCTION_FAILED;
9ba56b95 196 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 197 if (!sp)
198 goto done;
199
9ba56b95
GM		 200 sp->type = SRB_LOGOUT_CMD;
201 sp->name = "logout";
202 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
203
204 lio = &sp->u.iocb_cmd;
3822263e 205 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 206 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 207 rval = qla2x00_start_sp(sp);
208 if (rval != QLA_SUCCESS)
209 goto done_free_sp;
210
7c3df132 211 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 212 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
213 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
214 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 215 return rval;
216
217done_free_sp:
9ba56b95 218 sp->free(fcport->vha, sp);
ac280b67
AV		 219done:
220 return rval;
221}
222
5ff1d584 223static void
9ba56b95 224qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 225{
9ba56b95
GM		 226 srb_t *sp = (srb_t *)ptr;
227 struct srb_iocb *lio = &sp->u.iocb_cmd;
228 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
229
230 if (!test_bit(UNLOADING, &vha->dpc_flags))
231 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
232 lio->u.logio.data);
233 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 234}
235
236int
237qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
238 uint16_t *data)
239{
5ff1d584 240 srb_t *sp;
4916392b 241 struct srb_iocb *lio;
5ff1d584
AV		 242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
9ba56b95 245 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 246 if (!sp)
247 goto done;
248
9ba56b95
GM		 249 sp->type = SRB_ADISC_CMD;
250 sp->name = "adisc";
251 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
252
253 lio = &sp->u.iocb_cmd;
3822263e 254 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 255 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 256 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 257 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 258 rval = qla2x00_start_sp(sp);
259 if (rval != QLA_SUCCESS)
260 goto done_free_sp;
261
7c3df132 262 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 263 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
264 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
265 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 266 return rval;
267
268done_free_sp:
9ba56b95 269 sp->free(fcport->vha, sp);
5ff1d584
AV		 270done:
271 return rval;
272}
273
3822263e 274static void
9ba56b95 275qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 276{
9ba56b95
GM		 277 srb_t *sp = (srb_t *)ptr;
278 struct srb_iocb *iocb = &sp->u.iocb_cmd;
279 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
280 uint32_t flags;
281 uint16_t lun;
282 int rval;
3822263e 283
9ba56b95
GM		 284 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
285 flags = iocb->u.tmf.flags;
286 lun = (uint16_t)iocb->u.tmf.lun;
287
288 /* Issue Marker IOCB */
289 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
290 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
291 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
292
293 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
294 ql_dbg(ql_dbg_taskm, vha, 0x8030,
295 "TM IOCB failed (%x).\n", rval);
296 }
297 }
298 sp->free(sp->fcport->vha, sp);
3822263e
MI		 299}
300
301int
9ba56b95 302qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 303 uint32_t tag)
304{
305 struct scsi_qla_host *vha = fcport->vha;
3822263e 306 srb_t *sp;
3822263e
MI		 307 struct srb_iocb *tcf;
308 int rval;
309
310 rval = QLA_FUNCTION_FAILED;
9ba56b95 311 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 312 if (!sp)
313 goto done;
314
9ba56b95
GM		 315 sp->type = SRB_TM_CMD;
316 sp->name = "tmf";
317 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
318
319 tcf = &sp->u.iocb_cmd;
320 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 321 tcf->u.tmf.lun = lun;
322 tcf->u.tmf.data = tag;
323 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 324 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 325
326 rval = qla2x00_start_sp(sp);
327 if (rval != QLA_SUCCESS)
328 goto done_free_sp;
329
7c3df132 330 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 331 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
332 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
333 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 334 return rval;
335
336done_free_sp:
9ba56b95 337 sp->free(fcport->vha, sp);
3822263e
MI		 338done:
339 return rval;
340}
341
4916392b 342void
ac280b67
AV		 343qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
344 uint16_t *data)
345{
346 int rval;
ac280b67
AV		 347
348 switch (data[0]) {
349 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 350 /*
351 * Driver must validate login state - If PRLI not complete,
352 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
353 * requests.
354 */
355 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 356 if (rval == QLA_NOT_LOGGED_IN) {
357 fcport->flags &= ~FCF_ASYNC_SENT;
358 fcport->flags |= FCF_LOGIN_NEEDED;
359 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
360 break;
361 }
362
a4f92a32
AV		 363 if (rval != QLA_SUCCESS) {
364 qla2x00_post_async_logout_work(vha, fcport, NULL);
365 qla2x00_post_async_login_work(vha, fcport, NULL);
366 break;
367 }
99b0bec7 368 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 369 qla2x00_post_async_adisc_work(vha, fcport, data);
370 break;
99b0bec7
AV		 371 }
372 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 373 break;
374 case MBS_COMMAND_ERROR:
5ff1d584 375 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 376 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
377 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
378 else
80d79440 379 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 380 break;
381 case MBS_PORT_ID_USED:
382 fcport->loop_id = data[1];
6ac52608 383 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 384 qla2x00_post_async_login_work(vha, fcport, NULL);
385 break;
386 case MBS_LOOP_ID_USED:
387 fcport->loop_id++;
388 rval = qla2x00_find_new_loop_id(vha, fcport);
389 if (rval != QLA_SUCCESS) {
5ff1d584 390 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 391 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 392 break;
393 }
394 qla2x00_post_async_login_work(vha, fcport, NULL);
395 break;
396 }
4916392b 397 return;
ac280b67
AV		 398}
399
4916392b 400void
ac280b67
AV		 401qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
402 uint16_t *data)
403{
404 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 405 return;
ac280b67
AV		 406}
407
4916392b 408void
5ff1d584
AV		 409qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
410 uint16_t *data)
411{
412 if (data[0] == MBS_COMMAND_COMPLETE) {
413 qla2x00_update_fcport(vha, fcport);
414
4916392b 415 return;
5ff1d584
AV		 416 }
417
418 /* Retry login. */
419 fcport->flags &= ~FCF_ASYNC_SENT;
420 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
421 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
422 else
80d79440 423 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 424
4916392b 425 return;
5ff1d584
AV		 426}
427
1da177e4
LT		 428/****************************************************************************/
429/* QLogic ISP2x00 Hardware Support Functions. */
430/****************************************************************************/
431
fa492630 432static int
7d613ac6
SV		 433qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
434{
435 int rval = QLA_SUCCESS;
436 struct qla_hw_data *ha = vha->hw;
437 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 438 uint16_t config[4];
7d613ac6
SV		 439
440 qla83xx_idc_lock(vha, 0);
441
442 /* SV: TODO: Assign initialization timeout from
443 * flash-info / other param
444 */
445 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
446 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
447
448 /* Set our fcoe function presence */
449 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
450 ql_dbg(ql_dbg_p3p, vha, 0xb077,
451 "Error while setting DRV-Presence.\n");
452 rval = QLA_FUNCTION_FAILED;
453 goto exit;
454 }
455
456 /* Decide the reset ownership */
457 qla83xx_reset_ownership(vha);
458
459 /*
460 * On first protocol driver load:
461 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
462 * register.
463 * Others: Check compatibility with current IDC Major version.
464 */
465 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
466 if (ha->flags.nic_core_reset_owner) {
467 /* Set IDC Major version */
468 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
469 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
470
471 /* Clearing IDC-Lock-Recovery register */
472 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
473 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
474 /*
475 * Clear further IDC participation if we are not compatible with
476 * the current IDC Major Version.
477 */
478 ql_log(ql_log_warn, vha, 0xb07d,
479 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
480 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
481 __qla83xx_clear_drv_presence(vha);
482 rval = QLA_FUNCTION_FAILED;
483 goto exit;
484 }
485 /* Each function sets its supported Minor version. */
486 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
487 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
488 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
489
711aa7f7
SK		 490 if (ha->flags.nic_core_reset_owner) {
491 memset(config, 0, sizeof(config));
492 if (!qla81xx_get_port_config(vha, config))
493 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
494 QLA8XXX_DEV_READY);
495 }
496
7d613ac6
SV		 497 rval = qla83xx_idc_state_handler(vha);
498
499exit:
500 qla83xx_idc_unlock(vha, 0);
501
502 return rval;
503}
504
1da177e4
LT		 505/*
506* qla2x00_initialize_adapter
507* Initialize board.
508*
509* Input:
510* ha = adapter block pointer.
511*
512* Returns:
513* 0 = success
514*/
515int
e315cd28 516qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 517{
518 int rval;
e315cd28 519 struct qla_hw_data *ha = vha->hw;
73208dfd 520 struct req_que *req = ha->req_q_map[0];
2533cf67 521
1da177e4 522 /* Clear adapter flags. */
e315cd28 523 vha->flags.online = 0;
2533cf67 524 ha->flags.chip_reset_done = 0;
e315cd28 525 vha->flags.reset_active = 0;
85880801
AV		 526 ha->flags.pci_channel_io_perm_failure = 0;
527 ha->flags.eeh_busy = 0;
794a5691 528 ha->flags.thermal_supported = 1;
e315cd28
AC		 529 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
530 atomic_set(&vha->loop_state, LOOP_DOWN);
531 vha->device_flags = DFLG_NO_CABLE;
532 vha->dpc_flags = 0;
533 vha->flags.management_server_logged_in = 0;
534 vha->marker_needed = 0;
1da177e4
LT		 535 ha->isp_abort_cnt = 0;
536 ha->beacon_blink_led = 0;
537
73208dfd
AC		 538 set_bit(0, ha->req_qid_map);
539 set_bit(0, ha->rsp_qid_map);
540
cfb0919c 541 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 542 "Configuring PCI space...\n");
e315cd28 543 rval = ha->isp_ops->pci_config(vha);
1da177e4 544 if (rval) {
7c3df132
SK		 545 ql_log(ql_log_warn, vha, 0x0044,
546 "Unable to configure PCI space.\n");
1da177e4
LT		 547 return (rval);
548 }
549
e315cd28 550 ha->isp_ops->reset_chip(vha);
1da177e4 551
e315cd28 552 rval = qla2xxx_get_flash_info(vha);
c00d8994 553 if (rval) {
7c3df132
SK		 554 ql_log(ql_log_fatal, vha, 0x004f,
555 "Unable to validate FLASH data.\n");
c00d8994
AV		 556 return (rval);
557 }
558
73208dfd 559 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 560 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 561 "Configure NVRAM parameters...\n");
0107109e 562
e315cd28 563 ha->isp_ops->nvram_config(vha);
1da177e4 564
d4c760c2
AV		 565 if (ha->flags.disable_serdes) {
566 /* Mask HBA via NVRAM settings? */
7c3df132
SK		 567 ql_log(ql_log_info, vha, 0x0077,
568 "Masking HBA WWPN "
d4c760c2 569 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
e315cd28
AC		 570 vha->port_name[0], vha->port_name[1],
571 vha->port_name[2], vha->port_name[3],
572 vha->port_name[4], vha->port_name[5],
573 vha->port_name[6], vha->port_name[7]);
d4c760c2
AV		 574 return QLA_FUNCTION_FAILED;
575 }
576
cfb0919c 577 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 578 "Verifying loaded RISC code...\n");
1da177e4 579
e315cd28
AC		 580 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
581 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 582 if (rval)
583 return (rval);
e315cd28 584 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 585 if (rval)
586 return (rval);
1da177e4 587 }
a9083016 588
4d4df193 589 if (IS_QLA84XX(ha)) {
e315cd28 590 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 591 if (!ha->cs84xx) {
7c3df132 592 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 593 "Unable to configure ISP84XX.\n");
594 return QLA_FUNCTION_FAILED;
595 }
596 }
2d70c103
NB		 597
598 if (qla_ini_mode_enabled(vha))
599 rval = qla2x00_init_rings(vha);
600
2533cf67 601 ha->flags.chip_reset_done = 1;
1da177e4 602
9a069e19 603 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 604 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 605 rval = qla84xx_init_chip(vha);
606 if (rval != QLA_SUCCESS) {
7c3df132
SK		 607 ql_log(ql_log_warn, vha, 0x00d4,
608 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 609 qla84xx_put_chip(vha);
610 }
611 }
612
7d613ac6
SV		 613 /* Load the NIC Core f/w if we are the first protocol driver. */
614 if (IS_QLA8031(ha)) {
615 rval = qla83xx_nic_core_fw_load(vha);
616 if (rval)
617 ql_log(ql_log_warn, vha, 0x0124,
618 "Error in initializing NIC Core f/w.\n");
619 }
620
2f0f3f4f
MI		 621 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
622 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 623
1da177e4
LT		 624 return (rval);
625}
626
627/**
abbd8870 628 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 629 * @ha: HA context
630 *
631 * Returns 0 on success.
632 */
abbd8870 633int
e315cd28 634qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 635{
a157b101 636 uint16_t w;
abbd8870 637 unsigned long flags;
e315cd28 638 struct qla_hw_data *ha = vha->hw;
3d71644c 639 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 640
1da177e4 641 pci_set_master(ha->pdev);
af6177d8 642 pci_try_set_mwi(ha->pdev);
1da177e4 643
1da177e4 644 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 645 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 646 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
647
737faece 648 pci_disable_rom(ha->pdev);
1da177e4
LT		 649
650 /* Get PCI bus information. */
651 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 652 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 653 spin_unlock_irqrestore(&ha->hardware_lock, flags);
654
abbd8870
AV		 655 return QLA_SUCCESS;
656}
1da177e4 657
abbd8870
AV		 658/**
659 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
660 * @ha: HA context
661 *
662 * Returns 0 on success.
663 */
664int
e315cd28 665qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 666{
a157b101 667 uint16_t w;
abbd8870
AV		 668 unsigned long flags = 0;
669 uint32_t cnt;
e315cd28 670 struct qla_hw_data *ha = vha->hw;
3d71644c 671 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 672
abbd8870 673 pci_set_master(ha->pdev);
af6177d8 674 pci_try_set_mwi(ha->pdev);
1da177e4 675
abbd8870 676 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 677 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 678
abbd8870
AV		 679 if (IS_QLA2322(ha) || IS_QLA6322(ha))
680 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 681 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 682
abbd8870
AV		 683 /*
684 * If this is a 2300 card and not 2312, reset the
685 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
686 * the 2310 also reports itself as a 2300 so we need to get the
687 * fb revision level -- a 6 indicates it really is a 2300 and
688 * not a 2310.
689 */
690 if (IS_QLA2300(ha)) {
691 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 692
abbd8870 693 /* Pause RISC. */
3d71644c 694 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 695 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 696 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 697 break;
1da177e4 698
abbd8870
AV		 699 udelay(10);
700 }
1da177e4 701
abbd8870 702 /* Select FPM registers. */
3d71644c
AV		 703 WRT_REG_WORD(&reg->ctrl_status, 0x20);
704 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 705
706 /* Get the fb rev level */
3d71644c 707 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 708
709 if (ha->fb_rev == FPM_2300)
a157b101 710 pci_clear_mwi(ha->pdev);
abbd8870
AV		 711
712 /* Deselect FPM registers. */
3d71644c
AV		 713 WRT_REG_WORD(&reg->ctrl_status, 0x0);
714 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 715
716 /* Release RISC module. */
3d71644c 717 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 718 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 719 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 720 break;
721
722 udelay(10);
1da177e4 723 }
1da177e4 724
abbd8870
AV		 725 spin_unlock_irqrestore(&ha->hardware_lock, flags);
726 }
1da177e4 727
abbd8870
AV		 728 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
729
737faece 730 pci_disable_rom(ha->pdev);
1da177e4 731
abbd8870
AV		 732 /* Get PCI bus information. */
733 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 734 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 735 spin_unlock_irqrestore(&ha->hardware_lock, flags);
736
737 return QLA_SUCCESS;
1da177e4
LT		 738}
739
0107109e
AV		 740/**
741 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
742 * @ha: HA context
743 *
744 * Returns 0 on success.
745 */
746int
e315cd28 747qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 748{
a157b101 749 uint16_t w;
0107109e 750 unsigned long flags = 0;
e315cd28 751 struct qla_hw_data *ha = vha->hw;
0107109e 752 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 753
754 pci_set_master(ha->pdev);
af6177d8 755 pci_try_set_mwi(ha->pdev);
0107109e
AV		 756
757 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 758 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 759 w &= ~PCI_COMMAND_INTX_DISABLE;
760 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
761
762 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
763
764 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 765 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
766 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 767
768 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 769 if (pci_is_pcie(ha->pdev))
5ffd3a52 770 pcie_set_readrq(ha->pdev, 4096);
0107109e 771
737faece 772 pci_disable_rom(ha->pdev);
0107109e 773
44c10138 774 ha->chip_revision = ha->pdev->revision;
a8488abe 775
0107109e
AV		 776 /* Get PCI bus information. */
777 spin_lock_irqsave(&ha->hardware_lock, flags);
778 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
780
781 return QLA_SUCCESS;
782}
783
c3a2f0df
AV		 784/**
785 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
786 * @ha: HA context
787 *
788 * Returns 0 on success.
789 */
790int
e315cd28 791qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 792{
793 uint16_t w;
e315cd28 794 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 795
796 pci_set_master(ha->pdev);
797 pci_try_set_mwi(ha->pdev);
798
799 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
800 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
801 w &= ~PCI_COMMAND_INTX_DISABLE;
802 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
803
804 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 805 if (pci_is_pcie(ha->pdev))
5ffd3a52 806 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 807
737faece 808 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 809
810 ha->chip_revision = ha->pdev->revision;
811
812 return QLA_SUCCESS;
813}
814
1da177e4
LT		 815/**
816 * qla2x00_isp_firmware() - Choose firmware image.
817 * @ha: HA context
818 *
819 * Returns 0 on success.
820 */
821static int
e315cd28 822qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 823{
824 int rval;
42e421b1
AV		 825 uint16_t loop_id, topo, sw_cap;
826 uint8_t domain, area, al_pa;
e315cd28 827 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 828
829 /* Assume loading risc code */
fa2a1ce5 830 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 831
832 if (ha->flags.disable_risc_code_load) {
7c3df132 833 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 834
835 /* Verify checksum of loaded RISC code. */
e315cd28 836 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 837 if (rval == QLA_SUCCESS) {
838 /* And, verify we are not in ROM code. */
e315cd28 839 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 840 &area, &domain, &topo, &sw_cap);
841 }
1da177e4
LT		 842 }
843
7c3df132
SK		 844 if (rval)
845 ql_dbg(ql_dbg_init, vha, 0x007a,
846 "**** Load RISC code ****.\n");
1da177e4
LT		 847
848 return (rval);
849}
850
851/**
852 * qla2x00_reset_chip() - Reset ISP chip.
853 * @ha: HA context
854 *
855 * Returns 0 on success.
856 */
abbd8870 857void
e315cd28 858qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 859{
860 unsigned long flags = 0;
e315cd28 861 struct qla_hw_data *ha = vha->hw;
3d71644c 862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 863 uint32_t cnt;
1da177e4
LT		 864 uint16_t cmd;
865
85880801
AV		 866 if (unlikely(pci_channel_offline(ha->pdev)))
867 return;
868
fd34f556 869 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 870
871 spin_lock_irqsave(&ha->hardware_lock, flags);
872
873 /* Turn off master enable */
874 cmd = 0;
875 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
876 cmd &= ~PCI_COMMAND_MASTER;
877 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
878
879 if (!IS_QLA2100(ha)) {
880 /* Pause RISC. */
881 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
882 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
883 for (cnt = 0; cnt < 30000; cnt++) {
884 if ((RD_REG_WORD(&reg->hccr) &
885 HCCR_RISC_PAUSE) != 0)
886 break;
887 udelay(100);
888 }
889 } else {
890 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
891 udelay(10);
892 }
893
894 /* Select FPM registers. */
895 WRT_REG_WORD(&reg->ctrl_status, 0x20);
896 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
897
898 /* FPM Soft Reset. */
899 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
900 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
901
902 /* Toggle Fpm Reset. */
903 if (!IS_QLA2200(ha)) {
904 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
905 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
906 }
907
908 /* Select frame buffer registers. */
909 WRT_REG_WORD(&reg->ctrl_status, 0x10);
910 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
911
912 /* Reset frame buffer FIFOs. */
913 if (IS_QLA2200(ha)) {
914 WRT_FB_CMD_REG(ha, reg, 0xa000);
915 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
916 } else {
917 WRT_FB_CMD_REG(ha, reg, 0x00fc);
918
919 /* Read back fb_cmd until zero or 3 seconds max */
920 for (cnt = 0; cnt < 3000; cnt++) {
921 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
922 break;
923 udelay(100);
924 }
925 }
926
927 /* Select RISC module registers. */
928 WRT_REG_WORD(&reg->ctrl_status, 0);
929 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
930
931 /* Reset RISC processor. */
932 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
933 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
934
935 /* Release RISC processor. */
936 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
937 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
938 }
939
940 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
941 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
942
943 /* Reset ISP chip. */
944 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
945
946 /* Wait for RISC to recover from reset. */
947 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
948 /*
949 * It is necessary to for a delay here since the card doesn't
950 * respond to PCI reads during a reset. On some architectures
951 * this will result in an MCA.
952 */
953 udelay(20);
954 for (cnt = 30000; cnt; cnt--) {
955 if ((RD_REG_WORD(&reg->ctrl_status) &
956 CSR_ISP_SOFT_RESET) == 0)
957 break;
958 udelay(100);
959 }
960 } else
961 udelay(10);
962
963 /* Reset RISC processor. */
964 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
965
966 WRT_REG_WORD(&reg->semaphore, 0);
967
968 /* Release RISC processor. */
969 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
970 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
971
972 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
973 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 974 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 975 break;
1da177e4
LT		 976
977 udelay(100);
978 }
979 } else
980 udelay(100);
981
982 /* Turn on master enable */
983 cmd |= PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 /* Disable RISC pause on FPM parity error. */
987 if (!IS_QLA2100(ha)) {
988 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
989 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
990 }
991
992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
993}
994
b1d46989
MI		 995/**
996 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
997 *
998 * Returns 0 on success.
999 */
fa492630 1000static int
b1d46989
MI		 1001qla81xx_reset_mpi(scsi_qla_host_t *vha)
1002{
1003 uint16_t mb[4] = {0x1010, 0, 1, 0};
1004
6246b8a1
GM		 1005 if (!IS_QLA81XX(vha->hw))
1006 return QLA_SUCCESS;
1007
b1d46989
MI		 1008 return qla81xx_write_mpi_register(vha, mb);
1009}
1010
0107109e 1011/**
88c26663 1012 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1013 * @ha: HA context
1014 *
1015 * Returns 0 on success.
1016 */
88c26663 1017static inline void
e315cd28 1018qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1019{
1020 unsigned long flags = 0;
e315cd28 1021 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1022 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1023 uint32_t cnt, d2;
335a1cc9 1024 uint16_t wd;
b1d46989 1025 static int abts_cnt; /* ISP abort retry counts */
0107109e 1026
0107109e
AV		 1027 spin_lock_irqsave(&ha->hardware_lock, flags);
1028
1029 /* Reset RISC. */
1030 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1031 for (cnt = 0; cnt < 30000; cnt++) {
1032 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1033 break;
1034
1035 udelay(10);
1036 }
1037
1038 WRT_REG_DWORD(&reg->ctrl_status,
1039 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1040 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1041
335a1cc9 1042 udelay(100);
88c26663 1043 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1044 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1045 for (cnt = 10000 ; cnt && d2; cnt--) {
1046 udelay(5);
1047 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1048 barrier();
1049 }
1050
335a1cc9 1051 /* Wait for soft-reset to complete. */
0107109e
AV		 1052 d2 = RD_REG_DWORD(&reg->ctrl_status);
1053 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1054 udelay(5);
1055 d2 = RD_REG_DWORD(&reg->ctrl_status);
1056 barrier();
1057 }
1058
b1d46989
MI		 1059 /* If required, do an MPI FW reset now */
1060 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1061 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1062 if (++abts_cnt < 5) {
1063 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1064 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1065 } else {
1066 /*
1067 * We exhausted the ISP abort retries. We have to
1068 * set the board offline.
1069 */
1070 abts_cnt = 0;
1071 vha->flags.online = 0;
1072 }
1073 }
1074 }
1075
0107109e
AV		 1076 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1077 RD_REG_DWORD(&reg->hccr);
1078
1079 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1080 RD_REG_DWORD(&reg->hccr);
1081
1082 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1083 RD_REG_DWORD(&reg->hccr);
1084
1085 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1086 for (cnt = 6000000 ; cnt && d2; cnt--) {
1087 udelay(5);
1088 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1089 barrier();
1090 }
1091
1092 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1093
1094 if (IS_NOPOLLING_TYPE(ha))
1095 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1096}
1097
4ea2c9c7
JC		 1098static void
1099qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1100{
1101 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1102
1103 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1104 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1105
1106}
1107
1108static void
1109qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1110{
1111 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1112
1113 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1114 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1115}
1116
1117static void
1118qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1119{
1120 struct qla_hw_data *ha = vha->hw;
1121 uint32_t wd32 = 0;
1122 uint delta_msec = 100;
1123 uint elapsed_msec = 0;
1124 uint timeout_msec;
1125 ulong n;
1126
1127 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1128 return;
1129
1130attempt:
1131 timeout_msec = TIMEOUT_SEMAPHORE;
1132 n = timeout_msec / delta_msec;
1133 while (n--) {
1134 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1135 qla25xx_read_risc_sema_reg(vha, &wd32);
1136 if (wd32 & RISC_SEMAPHORE)
1137 break;
1138 msleep(delta_msec);
1139 elapsed_msec += delta_msec;
1140 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1141 goto force;
1142 }
1143
1144 if (!(wd32 & RISC_SEMAPHORE))
1145 goto force;
1146
1147 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1148 goto acquired;
1149
1150 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1151 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1152 n = timeout_msec / delta_msec;
1153 while (n--) {
1154 qla25xx_read_risc_sema_reg(vha, &wd32);
1155 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1156 break;
1157 msleep(delta_msec);
1158 elapsed_msec += delta_msec;
1159 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1160 goto force;
1161 }
1162
1163 if (wd32 & RISC_SEMAPHORE_FORCE)
1164 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1165
1166 goto attempt;
1167
1168force:
1169 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1170
1171acquired:
1172 return;
1173}
1174
88c26663
AV		 1175/**
1176 * qla24xx_reset_chip() - Reset ISP24xx chip.
1177 * @ha: HA context
1178 *
1179 * Returns 0 on success.
1180 */
1181void
e315cd28 1182qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1183{
e315cd28 1184 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1185
1186 if (pci_channel_offline(ha->pdev) &&
1187 ha->flags.pci_channel_io_perm_failure) {
1188 return;
1189 }
1190
fd34f556 1191 ha->isp_ops->disable_intrs(ha);
88c26663 1192
4ea2c9c7
JC		 1193 qla25xx_manipulate_risc_semaphore(vha);
1194
88c26663 1195 /* Perform RISC reset. */
e315cd28 1196 qla24xx_reset_risc(vha);
88c26663
AV		 1197}
1198
1da177e4
LT		 1199/**
1200 * qla2x00_chip_diag() - Test chip for proper operation.
1201 * @ha: HA context
1202 *
1203 * Returns 0 on success.
1204 */
abbd8870 1205int
e315cd28 1206qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1207{
1208 int rval;
e315cd28 1209 struct qla_hw_data *ha = vha->hw;
3d71644c 1210 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1211 unsigned long flags = 0;
1212 uint16_t data;
1213 uint32_t cnt;
1214 uint16_t mb[5];
73208dfd 1215 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1216
1217 /* Assume a failed state */
1218 rval = QLA_FUNCTION_FAILED;
1219
7c3df132
SK		 1220 ql_dbg(ql_dbg_init, vha, 0x007b,
1221 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1222
1223 spin_lock_irqsave(&ha->hardware_lock, flags);
1224
1225 /* Reset ISP chip. */
1226 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1227
1228 /*
1229 * We need to have a delay here since the card will not respond while
1230 * in reset causing an MCA on some architectures.
1231 */
1232 udelay(20);
1233 data = qla2x00_debounce_register(&reg->ctrl_status);
1234 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1235 udelay(5);
1236 data = RD_REG_WORD(&reg->ctrl_status);
1237 barrier();
1238 }
1239
1240 if (!cnt)
1241 goto chip_diag_failed;
1242
7c3df132
SK		 1243 ql_dbg(ql_dbg_init, vha, 0x007c,
1244 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1245
1246 /* Reset RISC processor. */
1247 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1248 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1249
1250 /* Workaround for QLA2312 PCI parity error */
1251 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1252 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1253 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1254 udelay(5);
1255 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1256 barrier();
1da177e4
LT		 1257 }
1258 } else
1259 udelay(10);
1260
1261 if (!cnt)
1262 goto chip_diag_failed;
1263
1264 /* Check product ID of chip */
7c3df132 1265 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1266
1267 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1268 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1269 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1270 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1271 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1272 mb[3] != PROD_ID_3) {
7c3df132
SK		 1273 ql_log(ql_log_warn, vha, 0x0062,
1274 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1275 mb[1], mb[2], mb[3]);
1da177e4
LT		 1276
1277 goto chip_diag_failed;
1278 }
1279 ha->product_id[0] = mb[1];
1280 ha->product_id[1] = mb[2];
1281 ha->product_id[2] = mb[3];
1282 ha->product_id[3] = mb[4];
1283
1284 /* Adjust fw RISC transfer size */
73208dfd 1285 if (req->length > 1024)
1da177e4
LT		 1286 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1287 else
1288 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1289 req->length;
1da177e4
LT		 1290
1291 if (IS_QLA2200(ha) &&
1292 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1293 /* Limit firmware transfer size with a 2200A */
7c3df132 1294 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1295
ea5b6382 1296 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1297 ha->fw_transfer_size = 128;
1298 }
1299
1300 /* Wrap Incoming Mailboxes Test. */
1301 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1302
7c3df132 1303 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1304 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1305 if (rval)
1306 ql_log(ql_log_warn, vha, 0x0080,
1307 "Failed mailbox send register test.\n");
1308 else
1da177e4
LT		 1309 /* Flag a successful rval */
1310 rval = QLA_SUCCESS;
1da177e4
LT		 1311 spin_lock_irqsave(&ha->hardware_lock, flags);
1312
1313chip_diag_failed:
1314 if (rval)
7c3df132
SK		 1315 ql_log(ql_log_info, vha, 0x0081,
1316 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1317
1318 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1319
1320 return (rval);
1321}
1322
0107109e
AV		 1323/**
1324 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1325 * @ha: HA context
1326 *
1327 * Returns 0 on success.
1328 */
1329int
e315cd28 1330qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1331{
1332 int rval;
e315cd28 1333 struct qla_hw_data *ha = vha->hw;
73208dfd 1334 struct req_que *req = ha->req_q_map[0];
0107109e 1335
a9083016
GM		 1336 if (IS_QLA82XX(ha))
1337 return QLA_SUCCESS;
1338
73208dfd 1339 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1340
e315cd28 1341 rval = qla2x00_mbx_reg_test(vha);
0107109e 1342 if (rval) {
7c3df132
SK		 1343 ql_log(ql_log_warn, vha, 0x0082,
1344 "Failed mailbox send register test.\n");
0107109e
AV		 1345 } else {
1346 /* Flag a successful rval */
1347 rval = QLA_SUCCESS;
1348 }
1349
1350 return rval;
1351}
1352
a7a167bf 1353void
e315cd28 1354qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1355{
a7a167bf
AV		 1356 int rval;
1357 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1358 eft_size, fce_size, mq_size;
df613b96
AV		 1359 dma_addr_t tc_dma;
1360 void *tc;
e315cd28 1361 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1362 struct req_que *req = ha->req_q_map[0];
1363 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1364
1365 if (ha->fw_dump) {
7c3df132
SK		 1366 ql_dbg(ql_dbg_init, vha, 0x00bd,
1367 "Firmware dump already allocated.\n");
a7a167bf
AV		 1368 return;
1369 }
d4e3e04d 1370
0107109e 1371 ha->fw_dumped = 0;
73208dfd 1372 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
d4e3e04d 1373 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1374 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1375 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1376 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1377 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1378 sizeof(uint16_t);
e428924c 1379 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1380 if (IS_QLA83XX(ha))
1381 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1382 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1383 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1384 else if (IS_QLA25XX(ha))
1385 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1386 else
1387 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
a7a167bf
AV		 1388 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1389 sizeof(uint32_t);
050c9bb1 1390 if (ha->mqenable) {
6246b8a1
GM		 1391 if (!IS_QLA83XX(ha))
1392 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1393 /*
1394 * Allocate maximum buffer size for all queues.
1395 * Resizing must be done at end-of-dump processing.
1396 */
1397 mq_size += ha->max_req_queues *
1398 (req->length * sizeof(request_t));
1399 mq_size += ha->max_rsp_queues *
1400 (rsp->length * sizeof(response_t));
1401 }
2d70c103
NB		 1402 if (ha->tgt.atio_q_length)
1403 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1404 /* Allocate memory for Fibre Channel Event Buffer. */
6246b8a1 1405 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
436a7b11 1406 goto try_eft;
df613b96
AV		 1407
1408 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1409 GFP_KERNEL);
1410 if (!tc) {
7c3df132
SK		 1411 ql_log(ql_log_warn, vha, 0x00be,
1412 "Unable to allocate (%d KB) for FCE.\n",
1413 FCE_SIZE / 1024);
17d98630 1414 goto try_eft;
df613b96
AV		 1415 }
1416
1417 memset(tc, 0, FCE_SIZE);
e315cd28 1418 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1419 ha->fce_mb, &ha->fce_bufs);
1420 if (rval) {
7c3df132
SK		 1421 ql_log(ql_log_warn, vha, 0x00bf,
1422 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1423 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1424 tc_dma);
1425 ha->flags.fce_enabled = 0;
17d98630 1426 goto try_eft;
df613b96 1427 }
cfb0919c 1428 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1429 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1430
7d9dade3 1431 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1432 ha->flags.fce_enabled = 1;
1433 ha->fce_dma = tc_dma;
1434 ha->fce = tc;
436a7b11
AV		 1435try_eft:
1436 /* Allocate memory for Extended Trace Buffer. */
1437 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1438 GFP_KERNEL);
1439 if (!tc) {
7c3df132
SK		 1440 ql_log(ql_log_warn, vha, 0x00c1,
1441 "Unable to allocate (%d KB) for EFT.\n",
1442 EFT_SIZE / 1024);
436a7b11
AV		 1443 goto cont_alloc;
1444 }
1445
1446 memset(tc, 0, EFT_SIZE);
e315cd28 1447 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1448 if (rval) {
7c3df132
SK		 1449 ql_log(ql_log_warn, vha, 0x00c2,
1450 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1451 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1452 tc_dma);
1453 goto cont_alloc;
1454 }
cfb0919c 1455 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1456 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1457
1458 eft_size = EFT_SIZE;
1459 ha->eft_dma = tc_dma;
1460 ha->eft = tc;
d4e3e04d 1461 }
a7a167bf 1462cont_alloc:
73208dfd
AC		 1463 req_q_size = req->length * sizeof(request_t);
1464 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf
AV		 1465
1466 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1467 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1468 ha->chain_offset = dump_size;
1469 dump_size += mq_size + fce_size;
d4e3e04d
AV		 1470
1471 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1472 if (!ha->fw_dump) {
7c3df132
SK		 1473 ql_log(ql_log_warn, vha, 0x00c4,
1474 "Unable to allocate (%d KB) for firmware dump.\n",
1475 dump_size / 1024);
a7a167bf 1476
e30d1756
MI		 1477 if (ha->fce) {
1478 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1479 ha->fce_dma);
1480 ha->fce = NULL;
1481 ha->fce_dma = 0;
1482 }
1483
a7a167bf
AV		 1484 if (ha->eft) {
1485 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1486 ha->eft_dma);
1487 ha->eft = NULL;
1488 ha->eft_dma = 0;
1489 }
1490 return;
1491 }
cfb0919c 1492 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1493 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf
AV		 1494
1495 ha->fw_dump_len = dump_size;
1496 ha->fw_dump->signature[0] = 'Q';
1497 ha->fw_dump->signature[1] = 'L';
1498 ha->fw_dump->signature[2] = 'G';
1499 ha->fw_dump->signature[3] = 'C';
1500 ha->fw_dump->version = __constant_htonl(1);
1501
1502 ha->fw_dump->fixed_size = htonl(fixed_size);
1503 ha->fw_dump->mem_size = htonl(mem_size);
1504 ha->fw_dump->req_q_size = htonl(req_q_size);
1505 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1506
1507 ha->fw_dump->eft_size = htonl(eft_size);
1508 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1509 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1510
1511 ha->fw_dump->header_size =
1512 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1513}
1514
18e7555a
AV		 1515static int
1516qla81xx_mpi_sync(scsi_qla_host_t *vha)
1517{
1518#define MPS_MASK 0xe0
1519 int rval;
1520 uint16_t dc;
1521 uint32_t dw;
18e7555a
AV		 1522
1523 if (!IS_QLA81XX(vha->hw))
1524 return QLA_SUCCESS;
1525
1526 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1527 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1528 ql_log(ql_log_warn, vha, 0x0105,
1529 "Unable to acquire semaphore.\n");
18e7555a
AV		 1530 goto done;
1531 }
1532
1533 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1534 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1535 if (rval != QLA_SUCCESS) {
7c3df132 1536 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1537 goto done_release;
1538 }
1539
1540 dc &= MPS_MASK;
1541 if (dc == (dw & MPS_MASK))
1542 goto done_release;
1543
1544 dw &= ~MPS_MASK;
1545 dw |= dc;
1546 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1547 if (rval != QLA_SUCCESS) {
7c3df132 1548 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1549 }
1550
1551done_release:
1552 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1553 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1554 ql_log(ql_log_warn, vha, 0x006d,
1555 "Unable to release semaphore.\n");
18e7555a
AV		 1556 }
1557
1558done:
1559 return rval;
1560}
1561
8d93f550
CD		 1562int
1563qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1564{
1565 /* Don't try to reallocate the array */
1566 if (req->outstanding_cmds)
1567 return QLA_SUCCESS;
1568
1569 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1570 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1571 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1572 else {
1573 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1574 req->num_outstanding_cmds = ha->fw_xcb_count;
1575 else
1576 req->num_outstanding_cmds = ha->fw_iocb_count;
1577 }
1578
1579 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1580 req->num_outstanding_cmds, GFP_KERNEL);
1581
1582 if (!req->outstanding_cmds) {
1583 /*
1584 * Try to allocate a minimal size just so we can get through
1585 * initialization.
1586 */
1587 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1588 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1589 req->num_outstanding_cmds, GFP_KERNEL);
1590
1591 if (!req->outstanding_cmds) {
1592 ql_log(ql_log_fatal, NULL, 0x0126,
1593 "Failed to allocate memory for "
1594 "outstanding_cmds for req_que %p.\n", req);
1595 req->num_outstanding_cmds = 0;
1596 return QLA_FUNCTION_FAILED;
1597 }
1598 }
1599
1600 return QLA_SUCCESS;
1601}
1602
1da177e4
LT		 1603/**
1604 * qla2x00_setup_chip() - Load and start RISC firmware.
1605 * @ha: HA context
1606 *
1607 * Returns 0 on success.
1608 */
1609static int
e315cd28 1610qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1611{
0107109e
AV		 1612 int rval;
1613 uint32_t srisc_address = 0;
e315cd28 1614 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1615 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1616 unsigned long flags;
dda772e8 1617 uint16_t fw_major_version;
3db0652e 1618
a9083016
GM		 1619 if (IS_QLA82XX(ha)) {
1620 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1621 if (rval == QLA_SUCCESS) {
1622 qla2x00_stop_firmware(vha);
a9083016 1623 goto enable_82xx_npiv;
14e303d9 1624 } else
b963752f 1625 goto failed;
a9083016
GM		 1626 }
1627
3db0652e
AV		 1628 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1629 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1630 spin_lock_irqsave(&ha->hardware_lock, flags);
1631 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1632 RD_REG_WORD(&reg->hccr);
1633 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1634 }
1da177e4 1635
18e7555a
AV		 1636 qla81xx_mpi_sync(vha);
1637
1da177e4 1638 /* Load firmware sequences */
e315cd28 1639 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1640 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1641 ql_dbg(ql_dbg_init, vha, 0x00c9,
1642 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1643
e315cd28 1644 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1645 if (rval == QLA_SUCCESS) {
1646 /* Start firmware execution. */
7c3df132
SK		 1647 ql_dbg(ql_dbg_init, vha, 0x00ca,
1648 "Starting firmware.\n");
1da177e4 1649
e315cd28 1650 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1651 /* Retrieve firmware information. */
dda772e8 1652 if (rval == QLA_SUCCESS) {
a9083016 1653enable_82xx_npiv:
dda772e8 1654 fw_major_version = ha->fw_major_version;
3173167f
GM		 1655 if (IS_QLA82XX(ha))
1656 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1657 else
1658 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1659 if (rval != QLA_SUCCESS)
1660 goto failed;
2c3dfe3f 1661 ha->flags.npiv_supported = 0;
e315cd28 1662 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1663 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1664 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1665 if ((!ha->max_npiv_vports) ||
1666 ((ha->max_npiv_vports + 1) %
eb66dc60 1667 MIN_MULTI_ID_FABRIC))
4d0ea247 1668 ha->max_npiv_vports =
eb66dc60 1669 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1670 }
24a08138 1671 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1672 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1673 &ha->max_npiv_vports, NULL);
d743de66 1674
8d93f550
CD		 1675 /*
1676 * Allocate the array of outstanding commands
1677 * now that we know the firmware resources.
1678 */
1679 rval = qla2x00_alloc_outstanding_cmds(ha,
1680 vha->req);
1681 if (rval != QLA_SUCCESS)
1682 goto failed;
1683
be5ea3cf
SK		 1684 if (!fw_major_version && ql2xallocfwdump
1685 && !IS_QLA82XX(ha))
08de2844 1686 qla2x00_alloc_fw_dump(vha);
1da177e4
LT		 1687 }
1688 } else {
7c3df132
SK		 1689 ql_log(ql_log_fatal, vha, 0x00cd,
1690 "ISP Firmware failed checksum.\n");
1691 goto failed;
1da177e4 1692 }
c74d88a4
AV		 1693 } else
1694 goto failed;
1da177e4 1695
3db0652e
AV		 1696 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1697 /* Enable proper parity. */
1698 spin_lock_irqsave(&ha->hardware_lock, flags);
1699 if (IS_QLA2300(ha))
1700 /* SRAM parity */
1701 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1702 else
1703 /* SRAM, Instruction RAM and GP RAM parity */
1704 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1705 RD_REG_WORD(&reg->hccr);
1706 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1707 }
1708
6246b8a1
GM		 1709 if (IS_QLA83XX(ha))
1710 goto skip_fac_check;
1711
1d2874de
JC		 1712 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1713 uint32_t size;
1714
1715 rval = qla81xx_fac_get_sector_size(vha, &size);
1716 if (rval == QLA_SUCCESS) {
1717 ha->flags.fac_supported = 1;
1718 ha->fdt_block_size = size << 2;
1719 } else {
7c3df132 1720 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1721 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1722 ha->fw_major_version, ha->fw_minor_version,
1723 ha->fw_subminor_version);
6246b8a1
GM		 1724skip_fac_check:
1725 if (IS_QLA83XX(ha)) {
1726 ha->flags.fac_supported = 0;
1727 rval = QLA_SUCCESS;
1728 }
1d2874de
JC		 1729 }
1730 }
ca9e9c3e 1731failed:
1da177e4 1732 if (rval) {
7c3df132
SK		 1733 ql_log(ql_log_fatal, vha, 0x00cf,
1734 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1735 }
1736
1737 return (rval);
1738}
1739
1740/**
1741 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1742 * @ha: HA context
1743 *
1744 * Beginning of request ring has initialization control block already built
1745 * by nvram config routine.
1746 *
1747 * Returns 0 on success.
1748 */
73208dfd
AC		 1749void
1750qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1751{
1752 uint16_t cnt;
1753 response_t *pkt;
1754
2afa19a9
AC		 1755 rsp->ring_ptr = rsp->ring;
1756 rsp->ring_index = 0;
1757 rsp->status_srb = NULL;
e315cd28
AC		 1758 pkt = rsp->ring_ptr;
1759 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1760 pkt->signature = RESPONSE_PROCESSED;
1761 pkt++;
1762 }
1da177e4
LT		 1763}
1764
1765/**
1766 * qla2x00_update_fw_options() - Read and process firmware options.
1767 * @ha: HA context
1768 *
1769 * Returns 0 on success.
1770 */
abbd8870 1771void
e315cd28 1772qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1773{
1774 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1775 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1776
1777 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1778 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1779
1780 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1781 return;
1782
1783 /* Serial Link options. */
7c3df132
SK		 1784 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1785 "Serial link options.\n");
1786 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1787 (uint8_t *)&ha->fw_seriallink_options,
1788 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1789
1790 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1791 if (ha->fw_seriallink_options[3] & BIT_2) {
1792 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1793
1794 /* 1G settings */
1795 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1796 emphasis = (ha->fw_seriallink_options[2] &
1797 (BIT_4 | BIT_3)) >> 3;
1798 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1799 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1800 rx_sens = (ha->fw_seriallink_options[0] &
1801 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1802 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1803 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1804 if (rx_sens == 0x0)
1805 rx_sens = 0x3;
1806 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1807 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1808 ha->fw_options[10] |= BIT_5 |
1809 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1810 (tx_sens & (BIT_1 | BIT_0));
1811
1812 /* 2G settings */
1813 swing = (ha->fw_seriallink_options[2] &
1814 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1815 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1816 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1817 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1818 rx_sens = (ha->fw_seriallink_options[1] &
1819 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1820 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1821 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1822 if (rx_sens == 0x0)
1823 rx_sens = 0x3;
1824 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1825 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1826 ha->fw_options[11] |= BIT_5 |
1827 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1828 (tx_sens & (BIT_1 | BIT_0));
1829 }
1830
1831 /* FCP2 options. */
1832 /* Return command IOCBs without waiting for an ABTS to complete. */
1833 ha->fw_options[3] |= BIT_13;
1834
1835 /* LED scheme. */
1836 if (ha->flags.enable_led_scheme)
1837 ha->fw_options[2] |= BIT_12;
1838
48c02fde 1839 /* Detect ISP6312. */
1840 if (IS_QLA6312(ha))
1841 ha->fw_options[2] |= BIT_13;
1842
1da177e4 1843 /* Update firmware options. */
e315cd28 1844 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1845}
1846
0107109e 1847void
e315cd28 1848qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1849{
1850 int rval;
e315cd28 1851 struct qla_hw_data *ha = vha->hw;
0107109e 1852
a9083016
GM		 1853 if (IS_QLA82XX(ha))
1854 return;
1855
0107109e 1856 /* Update Serial Link options. */
f94097ed 1857 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1858 return;
1859
e315cd28 1860 rval = qla2x00_set_serdes_params(vha,
f94097ed 1861 le16_to_cpu(ha->fw_seriallink_options24[1]),
1862 le16_to_cpu(ha->fw_seriallink_options24[2]),
1863 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1864 if (rval != QLA_SUCCESS) {
7c3df132 1865 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1866 "Unable to update Serial Link options (%x).\n", rval);
1867 }
1868}
1869
abbd8870 1870void
e315cd28 1871qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1872{
e315cd28 1873 struct qla_hw_data *ha = vha->hw;
3d71644c 1874 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1875 struct req_que *req = ha->req_q_map[0];
1876 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1877
1878 /* Setup ring parameters in initialization control block. */
1879 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1880 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1881 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1882 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1883 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1884 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1885 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1886 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1887
1888 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1889 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1890 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1891 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1892 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1893}
1894
0107109e 1895void
e315cd28 1896qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1897{
e315cd28 1898 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1899 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1900 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1901 struct qla_msix_entry *msix;
0107109e 1902 struct init_cb_24xx *icb;
73208dfd
AC		 1903 uint16_t rid = 0;
1904 struct req_que *req = ha->req_q_map[0];
1905 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1906
6246b8a1 1907 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1908 icb = (struct init_cb_24xx *)ha->init_cb;
1909 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1910 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1911 icb->request_q_length = cpu_to_le16(req->length);
1912 icb->response_q_length = cpu_to_le16(rsp->length);
1913 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1914 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1915 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1916 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1917
2d70c103
NB		 1918 /* Setup ATIO queue dma pointers for target mode */
1919 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1920 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1921 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1922 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1923
6246b8a1 1924 if (ha->mqenable || IS_QLA83XX(ha)) {
73208dfd
AC		 1925 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1926 icb->rid = __constant_cpu_to_le16(rid);
1927 if (ha->flags.msix_enabled) {
1928 msix = &ha->msix_entries[1];
7c3df132
SK		 1929 ql_dbg(ql_dbg_init, vha, 0x00fd,
1930 "Registering vector 0x%x for base que.\n",
1931 msix->entry);
73208dfd
AC		 1932 icb->msix = cpu_to_le16(msix->entry);
1933 }
1934 /* Use alternate PCI bus number */
1935 if (MSB(rid))
1936 icb->firmware_options_2 |=
1937 __constant_cpu_to_le32(BIT_19);
1938 /* Use alternate PCI devfn */
1939 if (LSB(rid))
1940 icb->firmware_options_2 |=
1941 __constant_cpu_to_le32(BIT_18);
1942
3155754a 1943 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1944 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1945 (ha->flags.msix_enabled)) {
3155754a
AC		 1946 icb->firmware_options_2 &=
1947 __constant_cpu_to_le32(~BIT_22);
1948 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1949 ql_dbg(ql_dbg_init, vha, 0x00fe,
1950 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1951 } else {
1952 icb->firmware_options_2 |=
1953 __constant_cpu_to_le32(BIT_22);
1954 }
73208dfd 1955 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1956
1957 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1958 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1959 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1960 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1961 } else {
1962 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1963 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1964 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1965 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1966 }
aa230bc5 1967 qlt_24xx_config_rings(vha);
2d70c103 1968
73208dfd
AC		 1969 /* PCI posting */
1970 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 1971}
1972
1da177e4
LT		 1973/**
1974 * qla2x00_init_rings() - Initializes firmware.
1975 * @ha: HA context
1976 *
1977 * Beginning of request ring has initialization control block already built
1978 * by nvram config routine.
1979 *
1980 * Returns 0 on success.
1981 */
1982static int
e315cd28 1983qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 1984{
1985 int rval;
1986 unsigned long flags = 0;
29bdccbe 1987 int cnt, que;
e315cd28 1988 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 1989 struct req_que *req;
1990 struct rsp_que *rsp;
2c3dfe3f
SJ		 1991 struct mid_init_cb_24xx *mid_init_cb =
1992 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 1993
1994 spin_lock_irqsave(&ha->hardware_lock, flags);
1995
1996 /* Clear outstanding commands array. */
2afa19a9 1997 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 1998 req = ha->req_q_map[que];
1999 if (!req)
2000 continue;
8d93f550 2001 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2002 req->outstanding_cmds[cnt] = NULL;
1da177e4 2003
2afa19a9 2004 req->current_outstanding_cmd = 1;
1da177e4 2005
29bdccbe
AC		 2006 /* Initialize firmware. */
2007 req->ring_ptr = req->ring;
2008 req->ring_index = 0;
2009 req->cnt = req->length;
2010 }
1da177e4 2011
2afa19a9 2012 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2013 rsp = ha->rsp_q_map[que];
2014 if (!rsp)
2015 continue;
29bdccbe
AC		 2016 /* Initialize response queue entries */
2017 qla2x00_init_response_q_entries(rsp);
2018 }
1da177e4 2019
2d70c103
NB		 2020 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2021 ha->tgt.atio_ring_index = 0;
2022 /* Initialize ATIO queue entries */
2023 qlt_init_atio_q_entries(vha);
2024
e315cd28 2025 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2026
2027 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2028
2029 /* Update any ISP specific firmware options before initialization. */
e315cd28 2030 ha->isp_ops->update_fw_options(vha);
1da177e4 2031
7c3df132 2032 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2c3dfe3f 2033
605aa2bc 2034 if (ha->flags.npiv_supported) {
45980cc2 2035 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2036 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2037 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2038 }
2039
24a08138
AV		 2040 if (IS_FWI2_CAPABLE(ha)) {
2041 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2042 mid_init_cb->init_cb.execution_throttle =
2043 cpu_to_le16(ha->fw_xcb_count);
2044 }
2c3dfe3f 2045
e315cd28 2046 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
1da177e4 2047 if (rval) {
7c3df132
SK		 2048 ql_log(ql_log_fatal, vha, 0x00d2,
2049 "Init Firmware **** FAILED ****.\n");
1da177e4 2050 } else {
7c3df132
SK		 2051 ql_dbg(ql_dbg_init, vha, 0x00d3,
2052 "Init Firmware -- success.\n");
1da177e4
LT		 2053 }
2054
2055 return (rval);
2056}
2057
2058/**
2059 * qla2x00_fw_ready() - Waits for firmware ready.
2060 * @ha: HA context
2061 *
2062 * Returns 0 on success.
2063 */
2064static int
e315cd28 2065qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2066{
2067 int rval;
4d4df193 2068 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2069 uint16_t min_wait; /* Minimum wait time if loop is down */
2070 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 2071 uint16_t state[5];
e315cd28 2072 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2073
2074 rval = QLA_SUCCESS;
2075
2076 /* 20 seconds for loop down. */
fa2a1ce5 2077 min_wait = 20;
1da177e4
LT		 2078
2079 /*
2080 * Firmware should take at most one RATOV to login, plus 5 seconds for
2081 * our own processing.
2082 */
2083 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2084 wait_time = min_wait;
2085 }
2086
2087 /* Min wait time if loop down */
2088 mtime = jiffies + (min_wait * HZ);
2089
2090 /* wait time before firmware ready */
2091 wtime = jiffies + (wait_time * HZ);
2092
2093 /* Wait for ISP to finish LIP */
e315cd28 2094 if (!vha->flags.init_done)
7c3df132
SK		 2095 ql_log(ql_log_info, vha, 0x801e,
2096 "Waiting for LIP to complete.\n");
1da177e4
LT		 2097
2098 do {
5b939038 2099 memset(state, -1, sizeof(state));
e315cd28 2100 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2101 if (rval == QLA_SUCCESS) {
4d4df193 2102 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2103 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2104 }
4d4df193 2105 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2106 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2107 "fw_state=%x 84xx=%x.\n", state[0],
2108 state[2]);
4d4df193
HK		 2109 if ((state[2] & FSTATE_LOGGED_IN) &&
2110 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2111 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2112 "Sending verify iocb.\n");
4d4df193
HK		 2113
2114 cs84xx_time = jiffies;
e315cd28 2115 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2116 if (rval != QLA_SUCCESS) {
2117 ql_log(ql_log_warn,
cfb0919c 2118 vha, 0x8007,
7c3df132 2119 "Init chip failed.\n");
4d4df193 2120 break;
7c3df132 2121 }
4d4df193
HK		 2122
2123 /* Add time taken to initialize. */
2124 cs84xx_time = jiffies - cs84xx_time;
2125 wtime += cs84xx_time;
2126 mtime += cs84xx_time;
cfb0919c 2127 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2128 "Increasing wait time by %ld. "
2129 "New time %ld.\n", cs84xx_time,
2130 wtime);
4d4df193
HK		 2131 }
2132 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2133 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2134 "F/W Ready - OK.\n");
1da177e4 2135
e315cd28 2136 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2137 &ha->login_timeout, &ha->r_a_tov);
2138
2139 rval = QLA_SUCCESS;
2140 break;
2141 }
2142
2143 rval = QLA_FUNCTION_FAILED;
2144
e315cd28 2145 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2146 state[0] != FSTATE_READY) {
1da177e4 2147 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2148 * other than Wait for Login.
2149 */
1da177e4 2150 if (time_after_eq(jiffies, mtime)) {
7c3df132 2151 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2152 "Cable is unplugged...\n");
2153
e315cd28 2154 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2155 break;
2156 }
2157 }
2158 } else {
2159 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2160 if (time_after_eq(jiffies, mtime) ||
7190575f 2161 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2162 break;
2163 }
2164
2165 if (time_after_eq(jiffies, wtime))
2166 break;
2167
2168 /* Delay for a while */
2169 msleep(500);
1da177e4
LT		 2170 } while (1);
2171
7c3df132
SK		 2172 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2173 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2174 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2175
cfb0919c 2176 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2177 ql_log(ql_log_warn, vha, 0x803b,
2178 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2179 }
2180
2181 return (rval);
2182}
2183
2184/*
2185* qla2x00_configure_hba
2186* Setup adapter context.
2187*
2188* Input:
2189* ha = adapter state pointer.
2190*
2191* Returns:
2192* 0 = success
2193*
2194* Context:
2195* Kernel context.
2196*/
2197static int
e315cd28 2198qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2199{
2200 int rval;
2201 uint16_t loop_id;
2202 uint16_t topo;
2c3dfe3f 2203 uint16_t sw_cap;
1da177e4
LT		 2204 uint8_t al_pa;
2205 uint8_t area;
2206 uint8_t domain;
2207 char connect_type[22];
e315cd28 2208 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2209 unsigned long flags;
1da177e4
LT		 2210
2211 /* Get host addresses. */
e315cd28 2212 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2213 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2214 if (rval != QLA_SUCCESS) {
e315cd28 2215 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2216 IS_CNA_CAPABLE(ha) ||
33135aa2 2217 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2218 ql_dbg(ql_dbg_disc, vha, 0x2008,
2219 "Loop is in a transition state.\n");
33135aa2 2220 } else {
7c3df132
SK		 2221 ql_log(ql_log_warn, vha, 0x2009,
2222 "Unable to get host loop ID.\n");
e315cd28 2223 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2224 }
1da177e4
LT		 2225 return (rval);
2226 }
2227
2228 if (topo == 4) {
7c3df132
SK		 2229 ql_log(ql_log_info, vha, 0x200a,
2230 "Cannot get topology - retrying.\n");
1da177e4
LT		 2231 return (QLA_FUNCTION_FAILED);
2232 }
2233
e315cd28 2234 vha->loop_id = loop_id;
1da177e4
LT		 2235
2236 /* initialize */
2237 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2238 ha->operating_mode = LOOP;
2c3dfe3f 2239 ha->switch_cap = 0;
1da177e4
LT		 2240
2241 switch (topo) {
2242 case 0:
7c3df132 2243 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2244 ha->current_topology = ISP_CFG_NL;
2245 strcpy(connect_type, "(Loop)");
2246 break;
2247
2248 case 1:
7c3df132 2249 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2250 ha->switch_cap = sw_cap;
1da177e4
LT		 2251 ha->current_topology = ISP_CFG_FL;
2252 strcpy(connect_type, "(FL_Port)");
2253 break;
2254
2255 case 2:
7c3df132 2256 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2257 ha->operating_mode = P2P;
2258 ha->current_topology = ISP_CFG_N;
2259 strcpy(connect_type, "(N_Port-to-N_Port)");
2260 break;
2261
2262 case 3:
7c3df132 2263 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2264 ha->switch_cap = sw_cap;
1da177e4
LT		 2265 ha->operating_mode = P2P;
2266 ha->current_topology = ISP_CFG_F;
2267 strcpy(connect_type, "(F_Port)");
2268 break;
2269
2270 default:
7c3df132
SK		 2271 ql_dbg(ql_dbg_disc, vha, 0x200f,
2272 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2273 ha->current_topology = ISP_CFG_NL;
2274 strcpy(connect_type, "(Loop)");
2275 break;
2276 }
2277
2278 /* Save Host port and loop ID. */
2279 /* byte order - Big Endian */
e315cd28
AC		 2280 vha->d_id.b.domain = domain;
2281 vha->d_id.b.area = area;
2282 vha->d_id.b.al_pa = al_pa;
1da177e4 2283
f24b5cb8 2284 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2285 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2286 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2287
e315cd28 2288 if (!vha->flags.init_done)
7c3df132
SK		 2289 ql_log(ql_log_info, vha, 0x2010,
2290 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2291 connect_type, vha->loop_id);
1da177e4
LT		 2292
2293 if (rval) {
7c3df132
SK		 2294 ql_log(ql_log_warn, vha, 0x2011,
2295 "%s FAILED\n", __func__);
1da177e4 2296 } else {
7c3df132
SK		 2297 ql_dbg(ql_dbg_disc, vha, 0x2012,
2298 "%s success\n", __func__);
1da177e4
LT		 2299 }
2300
2301 return(rval);
2302}
2303
a9083016 2304inline void
e315cd28
AC		 2305qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2306 char *def)
9bb9fcf2
AV		 2307{
2308 char *st, *en;
2309 uint16_t index;
e315cd28 2310 struct qla_hw_data *ha = vha->hw;
ab671149 2311 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2312 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2313
2314 if (memcmp(model, BINZERO, len) != 0) {
2315 strncpy(ha->model_number, model, len);
2316 st = en = ha->model_number;
2317 en += len - 1;
2318 while (en > st) {
2319 if (*en != 0x20 && *en != 0x00)
2320 break;
2321 *en-- = '\0';
2322 }
2323
2324 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2325 if (use_tbl &&
2326 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2327 index < QLA_MODEL_NAMES)
1ee27146
JC		 2328 strncpy(ha->model_desc,
2329 qla2x00_model_name[index * 2 + 1],
2330 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2331 } else {
2332 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2333 if (use_tbl &&
2334 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2335 index < QLA_MODEL_NAMES) {
2336 strcpy(ha->model_number,
2337 qla2x00_model_name[index * 2]);
1ee27146
JC		 2338 strncpy(ha->model_desc,
2339 qla2x00_model_name[index * 2 + 1],
2340 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2341 } else {
2342 strcpy(ha->model_number, def);
2343 }
2344 }
1ee27146 2345 if (IS_FWI2_CAPABLE(ha))
e315cd28 2346 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2347 sizeof(ha->model_desc));
9bb9fcf2
AV		 2348}
2349
4e08df3f
DM		 2350/* On sparc systems, obtain port and node WWN from firmware
2351 * properties.
2352 */
e315cd28 2353static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2354{
2355#ifdef CONFIG_SPARC
e315cd28 2356 struct qla_hw_data *ha = vha->hw;
4e08df3f 2357 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2358 struct device_node *dp = pci_device_to_OF_node(pdev);
2359 const u8 *val;
4e08df3f
DM		 2360 int len;
2361
2362 val = of_get_property(dp, "port-wwn", &len);
2363 if (val && len >= WWN_SIZE)
2364 memcpy(nv->port_name, val, WWN_SIZE);
2365
2366 val = of_get_property(dp, "node-wwn", &len);
2367 if (val && len >= WWN_SIZE)
2368 memcpy(nv->node_name, val, WWN_SIZE);
2369#endif
2370}
2371
1da177e4
LT		 2372/*
2373* NVRAM configuration for ISP 2xxx
2374*
2375* Input:
2376* ha = adapter block pointer.
2377*
2378* Output:
2379* initialization control block in response_ring
2380* host adapters parameters in host adapter block
2381*
2382* Returns:
2383* 0 = success.
2384*/
abbd8870 2385int
e315cd28 2386qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2387{
4e08df3f 2388 int rval;
0107109e
AV		 2389 uint8_t chksum = 0;
2390 uint16_t cnt;
2391 uint8_t *dptr1, *dptr2;
e315cd28 2392 struct qla_hw_data *ha = vha->hw;
0107109e 2393 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2394 nvram_t *nv = ha->nvram;
2395 uint8_t *ptr = ha->nvram;
3d71644c 2396 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2397
4e08df3f
DM		 2398 rval = QLA_SUCCESS;
2399
1da177e4 2400 /* Determine NVRAM starting address. */
0107109e 2401 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2402 ha->nvram_base = 0;
2403 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2404 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2405 ha->nvram_base = 0x80;
2406
2407 /* Get NVRAM data and calculate checksum. */
e315cd28 2408 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2409 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2410 chksum += *ptr++;
1da177e4 2411
7c3df132
SK		 2412 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2413 "Contents of NVRAM.\n");
2414 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2415 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2416
2417 /* Bad NVRAM data, set defaults parameters. */
2418 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2419 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2420 /* Reset NVRAM data. */
7c3df132 2421 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2422 "Inconsistent NVRAM "
7c3df132
SK		 2423 "detected: checksum=0x%x id=%c version=0x%x.\n",
2424 chksum, nv->id[0], nv->nvram_version);
2425 ql_log(ql_log_warn, vha, 0x0065,
2426 "Falling back to "
2427 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2428
2429 /*
2430 * Set default initialization control block.
2431 */
2432 memset(nv, 0, ha->nvram_size);
2433 nv->parameter_block_version = ICB_VERSION;
2434
2435 if (IS_QLA23XX(ha)) {
2436 nv->firmware_options[0] = BIT_2 | BIT_1;
2437 nv->firmware_options[1] = BIT_7 | BIT_5;
2438 nv->add_firmware_options[0] = BIT_5;
2439 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2440 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2441 nv->special_options[1] = BIT_7;
2442 } else if (IS_QLA2200(ha)) {
2443 nv->firmware_options[0] = BIT_2 | BIT_1;
2444 nv->firmware_options[1] = BIT_7 | BIT_5;
2445 nv->add_firmware_options[0] = BIT_5;
2446 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2447 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2448 } else if (IS_QLA2100(ha)) {
2449 nv->firmware_options[0] = BIT_3 | BIT_1;
2450 nv->firmware_options[1] = BIT_5;
2451 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2452 }
2453
2454 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2455 nv->execution_throttle = __constant_cpu_to_le16(16);
2456 nv->retry_count = 8;
2457 nv->retry_delay = 1;
2458
2459 nv->port_name[0] = 33;
2460 nv->port_name[3] = 224;
2461 nv->port_name[4] = 139;
2462
e315cd28 2463 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2464
2465 nv->login_timeout = 4;
2466
2467 /*
2468 * Set default host adapter parameters
2469 */
2470 nv->host_p[1] = BIT_2;
2471 nv->reset_delay = 5;
2472 nv->port_down_retry_count = 8;
2473 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2474 nv->link_down_timeout = 60;
2475
2476 rval = 1;
1da177e4
LT		 2477 }
2478
2479#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2480 /*
2481 * The SN2 does not provide BIOS emulation which means you can't change
2482 * potentially bogus BIOS settings. Force the use of default settings
2483 * for link rate and frame size. Hope that the rest of the settings
2484 * are valid.
2485 */
2486 if (ia64_platform_is("sn2")) {
2487 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2488 if (IS_QLA23XX(ha))
2489 nv->special_options[1] = BIT_7;
2490 }
2491#endif
2492
2493 /* Reset Initialization control block */
0107109e 2494 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2495
2496 /*
2497 * Setup driver NVRAM options.
2498 */
2499 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2500 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2501 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2502 nv->firmware_options[1] &= ~BIT_4;
2503
2504 if (IS_QLA23XX(ha)) {
2505 nv->firmware_options[0] |= BIT_2;
2506 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2507 nv->special_options[0] &= ~BIT_6;
0107109e 2508 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2509
2510 if (IS_QLA2300(ha)) {
2511 if (ha->fb_rev == FPM_2310) {
2512 strcpy(ha->model_number, "QLA2310");
2513 } else {
2514 strcpy(ha->model_number, "QLA2300");
2515 }
2516 } else {
e315cd28 2517 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2518 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2519 }
2520 } else if (IS_QLA2200(ha)) {
2521 nv->firmware_options[0] |= BIT_2;
2522 /*
2523 * 'Point-to-point preferred, else loop' is not a safe
2524 * connection mode setting.
2525 */
2526 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2527 (BIT_5 | BIT_4)) {
2528 /* Force 'loop preferred, else point-to-point'. */
2529 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2530 nv->add_firmware_options[0] |= BIT_5;
2531 }
2532 strcpy(ha->model_number, "QLA22xx");
2533 } else /*if (IS_QLA2100(ha))*/ {
2534 strcpy(ha->model_number, "QLA2100");
2535 }
2536
2537 /*
2538 * Copy over NVRAM RISC parameter block to initialization control block.
2539 */
2540 dptr1 = (uint8_t *)icb;
2541 dptr2 = (uint8_t *)&nv->parameter_block_version;
2542 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2543 while (cnt--)
2544 *dptr1++ = *dptr2++;
2545
2546 /* Copy 2nd half. */
2547 dptr1 = (uint8_t *)icb->add_firmware_options;
2548 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2549 while (cnt--)
2550 *dptr1++ = *dptr2++;
2551
5341e868
AV		 2552 /* Use alternate WWN? */
2553 if (nv->host_p[1] & BIT_7) {
2554 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2555 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2556 }
2557
1da177e4
LT		 2558 /* Prepare nodename */
2559 if ((icb->firmware_options[1] & BIT_6) == 0) {
2560 /*
2561 * Firmware will apply the following mask if the nodename was
2562 * not provided.
2563 */
2564 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2565 icb->node_name[0] &= 0xF0;
2566 }
2567
2568 /*
2569 * Set host adapter parameters.
2570 */
3ce8866c
SK		 2571
2572 /*
2573 * BIT_7 in the host-parameters section allows for modification to
2574 * internal driver logging.
2575 */
0181944f 2576 if (nv->host_p[0] & BIT_7)
cfb0919c 2577 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2578 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2579 /* Always load RISC code on non ISP2[12]00 chips. */
2580 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2581 ha->flags.disable_risc_code_load = 0;
2582 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2583 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2584 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2585 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2586 ha->flags.disable_serdes = 0;
1da177e4
LT		 2587
2588 ha->operating_mode =
2589 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2590
2591 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2592 sizeof(ha->fw_seriallink_options));
2593
2594 /* save HBA serial number */
2595 ha->serial0 = icb->port_name[5];
2596 ha->serial1 = icb->port_name[6];
2597 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2598 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2599 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2600
2601 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2602
2603 ha->retry_count = nv->retry_count;
2604
2605 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2606 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2607 nv->login_timeout = ql2xlogintimeout;
2608 if (nv->login_timeout < 4)
2609 nv->login_timeout = 4;
2610 ha->login_timeout = nv->login_timeout;
2611 icb->login_timeout = nv->login_timeout;
2612
00a537b8
AV		 2613 /* Set minimum RATOV to 100 tenths of a second. */
2614 ha->r_a_tov = 100;
1da177e4 2615
1da177e4
LT		 2616 ha->loop_reset_delay = nv->reset_delay;
2617
1da177e4
LT		 2618 /* Link Down Timeout = 0:
2619 *
2620 * When Port Down timer expires we will start returning
2621 * I/O's to OS with "DID_NO_CONNECT".
2622 *
2623 * Link Down Timeout != 0:
2624 *
2625 * The driver waits for the link to come up after link down
2626 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2627 */
1da177e4
LT		 2628 if (nv->link_down_timeout == 0) {
2629 ha->loop_down_abort_time =
354d6b21 2630 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2631 } else {
2632 ha->link_down_timeout = nv->link_down_timeout;
2633 ha->loop_down_abort_time =
2634 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2635 }
1da177e4 2636
1da177e4
LT		 2637 /*
2638 * Need enough time to try and get the port back.
2639 */
2640 ha->port_down_retry_count = nv->port_down_retry_count;
2641 if (qlport_down_retry)
2642 ha->port_down_retry_count = qlport_down_retry;
2643 /* Set login_retry_count */
2644 ha->login_retry_count = nv->retry_count;
2645 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2646 ha->port_down_retry_count > 3)
2647 ha->login_retry_count = ha->port_down_retry_count;
2648 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2649 ha->login_retry_count = ha->port_down_retry_count;
2650 if (ql2xloginretrycount)
2651 ha->login_retry_count = ql2xloginretrycount;
2652
1da177e4
LT		 2653 icb->lun_enables = __constant_cpu_to_le16(0);
2654 icb->command_resource_count = 0;
2655 icb->immediate_notify_resource_count = 0;
2656 icb->timeout = __constant_cpu_to_le16(0);
2657
2658 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2659 /* Enable RIO */
2660 icb->firmware_options[0] &= ~BIT_3;
2661 icb->add_firmware_options[0] &=
2662 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2663 icb->add_firmware_options[0] |= BIT_2;
2664 icb->response_accumulation_timer = 3;
2665 icb->interrupt_delay_timer = 5;
2666
e315cd28 2667 vha->flags.process_response_queue = 1;
1da177e4 2668 } else {
4fdfefe5 2669 /* Enable ZIO. */
e315cd28 2670 if (!vha->flags.init_done) {
4fdfefe5
AV		 2671 ha->zio_mode = icb->add_firmware_options[0] &
2672 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2673 ha->zio_timer = icb->interrupt_delay_timer ?
2674 icb->interrupt_delay_timer: 2;
2675 }
1da177e4
LT		 2676 icb->add_firmware_options[0] &=
2677 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2678 vha->flags.process_response_queue = 0;
4fdfefe5 2679 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 2680 ha->zio_mode = QLA_ZIO_MODE_6;
2681
7c3df132 2682 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2683 "ZIO mode %d enabled; timer delay (%d us).\n",
2684 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2685
4fdfefe5
AV		 2686 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2687 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2688 vha->flags.process_response_queue = 1;
1da177e4
LT		 2689 }
2690 }
2691
4e08df3f 2692 if (rval) {
7c3df132
SK		 2693 ql_log(ql_log_warn, vha, 0x0069,
2694 "NVRAM configuration failed.\n");
4e08df3f
DM		 2695 }
2696 return (rval);
1da177e4
LT		 2697}
2698
19a7b4ae
JSEC		 2699static void
2700qla2x00_rport_del(void *data)
2701{
2702 fc_port_t *fcport = data;
d97994dc 2703 struct fc_rport *rport;
2d70c103 2704 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2705 unsigned long flags;
d97994dc 2706
044d78e1 2707 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2708 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2709 fcport->drport = NULL;
044d78e1 2710 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2711 if (rport) {
d97994dc 2712 fc_remote_port_delete(rport);
2d70c103
NB		 2713 /*
2714 * Release the target mode FC NEXUS in qla_target.c code
2715 * if target mod is enabled.
2716 */
2717 qlt_fc_port_deleted(vha, fcport);
2718 }
19a7b4ae
JSEC		 2719}
2720
1da177e4
LT		 2721/**
2722 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2723 * @ha: HA context
2724 * @flags: allocation flags
2725 *
2726 * Returns a pointer to the allocated fcport, or NULL, if none available.
2727 */
9a069e19 2728fc_port_t *
e315cd28 2729qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2730{
2731 fc_port_t *fcport;
2732
bbfbbbc1
MK		 2733 fcport = kzalloc(sizeof(fc_port_t), flags);
2734 if (!fcport)
2735 return NULL;
1da177e4
LT		 2736
2737 /* Setup fcport template structure. */
e315cd28 2738 fcport->vha = vha;
1da177e4
LT		 2739 fcport->port_type = FCT_UNKNOWN;
2740 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2741 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2742 fcport->supported_classes = FC_COS_UNSPECIFIED;
c0822b63 2743 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 2744
bbfbbbc1 2745 return fcport;
1da177e4
LT		 2746}
2747
2748/*
2749 * qla2x00_configure_loop
2750 * Updates Fibre Channel Device Database with what is actually on loop.
2751 *
2752 * Input:
2753 * ha = adapter block pointer.
2754 *
2755 * Returns:
2756 * 0 = success.
2757 * 1 = error.
2758 * 2 = database was full and device was not configured.
2759 */
2760static int
e315cd28 2761qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2762{
2763 int rval;
2764 unsigned long flags, save_flags;
e315cd28 2765 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2766 rval = QLA_SUCCESS;
2767
2768 /* Get Initiator ID */
e315cd28
AC		 2769 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2770 rval = qla2x00_configure_hba(vha);
1da177e4 2771 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2772 ql_dbg(ql_dbg_disc, vha, 0x2013,
2773 "Unable to configure HBA.\n");
1da177e4
LT		 2774 return (rval);
2775 }
2776 }
2777
e315cd28 2778 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2779 ql_dbg(ql_dbg_disc, vha, 0x2014,
2780 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2781
2782 /*
2783 * If we have both an RSCN and PORT UPDATE pending then handle them
2784 * both at the same time.
2785 */
e315cd28
AC		 2786 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2787 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2788
3064ff39
MH		 2789 qla2x00_get_data_rate(vha);
2790
1da177e4
LT		 2791 /* Determine what we need to do */
2792 if (ha->current_topology == ISP_CFG_FL &&
2793 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2794
1da177e4
LT		 2795 set_bit(RSCN_UPDATE, &flags);
2796
2797 } else if (ha->current_topology == ISP_CFG_F &&
2798 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2799
1da177e4
LT		 2800 set_bit(RSCN_UPDATE, &flags);
2801 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2802
2803 } else if (ha->current_topology == ISP_CFG_N) {
2804 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2805
e315cd28 2806 } else if (!vha->flags.online ||
1da177e4
LT		 2807 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2808
1da177e4
LT		 2809 set_bit(RSCN_UPDATE, &flags);
2810 set_bit(LOCAL_LOOP_UPDATE, &flags);
2811 }
2812
2813 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2814 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2815 ql_dbg(ql_dbg_disc, vha, 0x2015,
2816 "Loop resync needed, failing.\n");
1da177e4 2817 rval = QLA_FUNCTION_FAILED;
642ef983 2818 } else
e315cd28 2819 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2820 }
2821
2822 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2823 if (LOOP_TRANSITION(vha)) {
2824 ql_dbg(ql_dbg_disc, vha, 0x201e,
2825 "Needs RSCN update and loop transition.\n");
1da177e4 2826 rval = QLA_FUNCTION_FAILED;
7c3df132 2827 }
e315cd28
AC		 2828 else
2829 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2830 }
2831
2832 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2833 if (atomic_read(&vha->loop_down_timer) ||
2834 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2835 rval = QLA_FUNCTION_FAILED;
2836 } else {
e315cd28 2837 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2838 ql_dbg(ql_dbg_disc, vha, 0x2069,
2839 "LOOP READY.\n");
1da177e4
LT		 2840 }
2841 }
2842
2843 if (rval) {
7c3df132
SK		 2844 ql_dbg(ql_dbg_disc, vha, 0x206a,
2845 "%s *** FAILED ***.\n", __func__);
1da177e4 2846 } else {
7c3df132
SK		 2847 ql_dbg(ql_dbg_disc, vha, 0x206b,
2848 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2849 }
2850
cc3ef7bc 2851 /* Restore state if a resync event occurred during processing */
e315cd28 2852 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2853 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2854 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2855 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2856 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2857 }
1da177e4
LT		 2858 }
2859
2860 return (rval);
2861}
2862
2863
2864
2865/*
2866 * qla2x00_configure_local_loop
2867 * Updates Fibre Channel Device Database with local loop devices.
2868 *
2869 * Input:
2870 * ha = adapter block pointer.
2871 *
2872 * Returns:
2873 * 0 = success.
2874 */
2875static int
e315cd28 2876qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2877{
2878 int rval, rval2;
2879 int found_devs;
2880 int found;
2881 fc_port_t *fcport, *new_fcport;
2882
2883 uint16_t index;
2884 uint16_t entries;
2885 char *id_iter;
2886 uint16_t loop_id;
2887 uint8_t domain, area, al_pa;
e315cd28 2888 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2889
2890 found_devs = 0;
2891 new_fcport = NULL;
642ef983 2892 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2893
1da177e4 2894 /* Get list of logged in devices. */
642ef983 2895 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2896 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2897 &entries);
2898 if (rval != QLA_SUCCESS)
2899 goto cleanup_allocation;
2900
7c3df132
SK		 2901 ql_dbg(ql_dbg_disc, vha, 0x2017,
2902 "Entries in ID list (%d).\n", entries);
2903 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2904 (uint8_t *)ha->gid_list,
2905 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2906
2907 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2908 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2909 if (new_fcport == NULL) {
7c3df132
SK		 2910 ql_log(ql_log_warn, vha, 0x2018,
2911 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2912 rval = QLA_MEMORY_ALLOC_FAILED;
2913 goto cleanup_allocation;
2914 }
2915 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2916
2917 /*
2918 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2919 */
e315cd28 2920 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2921 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2922 fcport->port_type != FCT_BROADCAST &&
2923 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2924
7c3df132
SK		 2925 ql_dbg(ql_dbg_disc, vha, 0x2019,
2926 "Marking port lost loop_id=0x%04x.\n",
2927 fcport->loop_id);
1da177e4 2928
ec426e10 2929 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2930 }
2931 }
2932
2933 /* Add devices to port list. */
2934 id_iter = (char *)ha->gid_list;
2935 for (index = 0; index < entries; index++) {
2936 domain = ((struct gid_list_info *)id_iter)->domain;
2937 area = ((struct gid_list_info *)id_iter)->area;
2938 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2939 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2940 loop_id = (uint16_t)
2941 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2942 else
1da177e4
LT		 2943 loop_id = le16_to_cpu(
2944 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2945 id_iter += ha->gid_list_info_size;
1da177e4
LT		 2946
2947 /* Bypass reserved domain fields. */
2948 if ((domain & 0xf0) == 0xf0)
2949 continue;
2950
2951 /* Bypass if not same domain and area of adapter. */
f7d289f6 2952 if (area && domain &&
e315cd28 2953 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 2954 continue;
2955
2956 /* Bypass invalid local loop ID. */
2957 if (loop_id > LAST_LOCAL_LOOP_ID)
2958 continue;
2959
370d550e
AE		 2960 memset(new_fcport, 0, sizeof(fc_port_t));
2961
1da177e4
LT		 2962 /* Fill in member data. */
2963 new_fcport->d_id.b.domain = domain;
2964 new_fcport->d_id.b.area = area;
2965 new_fcport->d_id.b.al_pa = al_pa;
2966 new_fcport->loop_id = loop_id;
e315cd28 2967 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 2968 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2969 ql_dbg(ql_dbg_disc, vha, 0x201a,
2970 "Failed to retrieve fcport information "
2971 "-- get_port_database=%x, loop_id=0x%04x.\n",
2972 rval2, new_fcport->loop_id);
2973 ql_dbg(ql_dbg_disc, vha, 0x201b,
2974 "Scheduling resync.\n");
e315cd28 2975 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 2976 continue;
2977 }
2978
2979 /* Check for matching device in port list. */
2980 found = 0;
2981 fcport = NULL;
e315cd28 2982 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2983 if (memcmp(new_fcport->port_name, fcport->port_name,
2984 WWN_SIZE))
2985 continue;
2986
ddb9b126 2987 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 2988 fcport->loop_id = new_fcport->loop_id;
2989 fcport->port_type = new_fcport->port_type;
2990 fcport->d_id.b24 = new_fcport->d_id.b24;
2991 memcpy(fcport->node_name, new_fcport->node_name,
2992 WWN_SIZE);
2993
2994 found++;
2995 break;
2996 }
2997
2998 if (!found) {
2999 /* New device, add to fcports list. */
e315cd28 3000 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3001
3002 /* Allocate a new replacement fcport. */
3003 fcport = new_fcport;
e315cd28 3004 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3005 if (new_fcport == NULL) {
7c3df132
SK		 3006 ql_log(ql_log_warn, vha, 0x201c,
3007 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3008 rval = QLA_MEMORY_ALLOC_FAILED;
3009 goto cleanup_allocation;
3010 }
3011 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3012 }
3013
d8b45213 3014 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3015 fcport->fp_speed = ha->link_data_rate;
d8b45213 3016
e315cd28 3017 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3018
3019 found_devs++;
3020 }
3021
3022cleanup_allocation:
c9475cb0 3023 kfree(new_fcport);
1da177e4
LT		 3024
3025 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3026 ql_dbg(ql_dbg_disc, vha, 0x201d,
3027 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3028 }
3029
1da177e4
LT		 3030 return (rval);
3031}
3032
d8b45213 3033static void
e315cd28 3034qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3035{
d8b45213 3036 int rval;
1bb39548 3037 uint16_t mb[4];
e315cd28 3038 struct qla_hw_data *ha = vha->hw;
d8b45213 3039
c76f2c01 3040 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3041 return;
3042
c9afb9a2
GM		 3043 if (atomic_read(&fcport->state) != FCS_ONLINE)
3044 return;
3045
39bd9622
AV		 3046 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3047 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3048 return;
3049
e315cd28 3050 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3051 mb);
d8b45213 3052 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3053 ql_dbg(ql_dbg_disc, vha, 0x2004,
3054 "Unable to adjust iIDMA "
3055 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
3056 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
d8b45213
AV		 3057 fcport->port_name[2], fcport->port_name[3],
3058 fcport->port_name[4], fcport->port_name[5],
3059 fcport->port_name[6], fcport->port_name[7], rval,
7c3df132 3060 fcport->fp_speed, mb[0], mb[1]);
d8b45213 3061 } else {
7c3df132
SK		 3062 ql_dbg(ql_dbg_disc, vha, 0x2005,
3063 "iIDMA adjusted to %s GB/s "
d0297c9a
JC		 3064 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n",
3065 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7c3df132
SK		 3066 fcport->port_name[0], fcport->port_name[1],
3067 fcport->port_name[2], fcport->port_name[3],
3068 fcport->port_name[4], fcport->port_name[5],
3069 fcport->port_name[6], fcport->port_name[7]);
d8b45213
AV		 3070 }
3071}
3072
23be331d 3073static void
e315cd28 3074qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 3075{
3076 struct fc_rport_identifiers rport_ids;
bdf79621 3077 struct fc_rport *rport;
044d78e1 3078 unsigned long flags;
8482e118 3079
ac280b67 3080 qla2x00_rport_del(fcport);
8482e118 3081
f8b02a85
AV		 3082 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3083 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 3084 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3085 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3086 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3087 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3088 if (!rport) {
7c3df132
SK		 3089 ql_log(ql_log_warn, vha, 0x2006,
3090 "Unable to allocate fc remote port.\n");
77d74143
AV		 3091 return;
3092 }
2d70c103
NB		 3093 /*
3094 * Create target mode FC NEXUS in qla_target.c if target mode is
3095 * enabled..
3096 */
3097 qlt_fc_port_added(vha, fcport);
3098
044d78e1 3099 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3100 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3101 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3102
ad3e0eda 3103 rport->supported_classes = fcport->supported_classes;
77d74143 3104
8482e118 3105 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3106 if (fcport->port_type == FCT_INITIATOR)
3107 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3108 if (fcport->port_type == FCT_TARGET)
3109 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3110 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3111}
3112
23be331d
AB		 3113/*
3114 * qla2x00_update_fcport
3115 * Updates device on list.
3116 *
3117 * Input:
3118 * ha = adapter block pointer.
3119 * fcport = port structure pointer.
3120 *
3121 * Return:
3122 * 0 - Success
3123 * BIT_0 - error
3124 *
3125 * Context:
3126 * Kernel context.
3127 */
3128void
e315cd28 3129qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3130{
e315cd28 3131 fcport->vha = vha;
23be331d 3132 fcport->login_retry = 0;
5ff1d584 3133 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3134
1f93da52 3135 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3136 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3137 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3138 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3139}
3140
1da177e4
LT		 3141/*
3142 * qla2x00_configure_fabric
3143 * Setup SNS devices with loop ID's.
3144 *
3145 * Input:
3146 * ha = adapter block pointer.
3147 *
3148 * Returns:
3149 * 0 = success.
3150 * BIT_0 = error
3151 */
3152static int
e315cd28 3153qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3154{
b3b02e6e 3155 int rval;
4dc77c36 3156 fc_port_t *fcport;
1da177e4
LT		 3157 uint16_t next_loopid;
3158 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3159 uint16_t loop_id;
1da177e4 3160 LIST_HEAD(new_fcports);
e315cd28
AC		 3161 struct qla_hw_data *ha = vha->hw;
3162 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3163
3164 /* If FL port exists, then SNS is present */
e428924c 3165 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3166 loop_id = NPH_F_PORT;
3167 else
3168 loop_id = SNS_FL_PORT;
e315cd28 3169 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3170 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3171 ql_dbg(ql_dbg_disc, vha, 0x201f,
3172 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3173
e315cd28 3174 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3175 return (QLA_SUCCESS);
3176 }
e315cd28 3177 vha->device_flags |= SWITCH_FOUND;
1da177e4 3178
1da177e4 3179 do {
cca5335c
AV		 3180 /* FDMI support. */
3181 if (ql2xfdmienable &&
e315cd28
AC		 3182 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3183 qla2x00_fdmi_register(vha);
cca5335c 3184
1da177e4 3185 /* Ensure we are logged into the SNS. */
e428924c 3186 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3187 loop_id = NPH_SNS;
3188 else
3189 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3190 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3191 0xfc, mb, BIT_1|BIT_0);
3192 if (rval != QLA_SUCCESS) {
3193 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4dc77c36 3194 break;
0b91d116 3195 }
1da177e4 3196 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3197 ql_dbg(ql_dbg_disc, vha, 0x2042,
3198 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3199 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3200 mb[2], mb[6], mb[7]);
1da177e4
LT		 3201 return (QLA_SUCCESS);
3202 }
3203
e315cd28
AC		 3204 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3205 if (qla2x00_rft_id(vha)) {
1da177e4 3206 /* EMPTY */
7c3df132
SK		 3207 ql_dbg(ql_dbg_disc, vha, 0x2045,
3208 "Register FC-4 TYPE failed.\n");
1da177e4 3209 }
e315cd28 3210 if (qla2x00_rff_id(vha)) {
1da177e4 3211 /* EMPTY */
7c3df132
SK		 3212 ql_dbg(ql_dbg_disc, vha, 0x2049,
3213 "Register FC-4 Features failed.\n");
1da177e4 3214 }
e315cd28 3215 if (qla2x00_rnn_id(vha)) {
1da177e4 3216 /* EMPTY */
7c3df132
SK		 3217 ql_dbg(ql_dbg_disc, vha, 0x204f,
3218 "Register Node Name failed.\n");
e315cd28 3219 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3220 /* EMPTY */
7c3df132
SK		 3221 ql_dbg(ql_dbg_disc, vha, 0x2053,
3222 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3223 }
3224 }
3225
e315cd28 3226 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3227 if (rval != QLA_SUCCESS)
3228 break;
3229
4dc77c36
JC		 3230 /* Add new ports to existing port list */
3231 list_splice_tail_init(&new_fcports, &vha->vp_fcports);
3232
3233 /* Starting free loop ID. */
3234 next_loopid = ha->min_external_loopid;
3235
e315cd28
AC		 3236 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3237 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3238 break;
3239
3240 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3241 continue;
3242
4dc77c36 3243 /* Logout lost/gone fabric devices (non-FCP2) */
c0822b63 3244 if (fcport->scan_state != QLA_FCPORT_SCAN_FOUND &&
b3b02e6e 3245 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3246 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3247 ql2xplogiabsentdevice, 0);
1da177e4 3248 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3249 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3250 fcport->port_type != FCT_INITIATOR &&
3251 fcport->port_type != FCT_BROADCAST) {
e315cd28 3252 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3253 fcport->loop_id,
3254 fcport->d_id.b.domain,
3255 fcport->d_id.b.area,
3256 fcport->d_id.b.al_pa);
1da177e4 3257 }
c0822b63 3258 continue;
1da177e4 3259 }
c0822b63 3260 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 3261
4dc77c36
JC		 3262 /* Login fabric devices that need a login */
3263 if ((fcport->flags & FCF_LOGIN_NEEDED) != 0 &&
3264 atomic_read(&vha->loop_down_timer) == 0) {
3265 if (fcport->loop_id == FC_NO_LOOP_ID) {
3266 fcport->loop_id = next_loopid;
3267 rval = qla2x00_find_new_loop_id(
3268 base_vha, fcport);
3269 if (rval != QLA_SUCCESS) {
3270 /* Ran out of IDs to use */
3271 continue;
3272 }
1da177e4
LT		 3273 }
3274 }
1da177e4 3275
bdf79621 3276 /* Login and update database */
e315cd28 3277 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
1da177e4
LT		 3278 }
3279 } while (0);
3280
1da177e4 3281 if (rval) {
7c3df132
SK		 3282 ql_dbg(ql_dbg_disc, vha, 0x2068,
3283 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3284 }
3285
3286 return (rval);
3287}
3288
1da177e4
LT		 3289/*
3290 * qla2x00_find_all_fabric_devs
3291 *
3292 * Input:
3293 * ha = adapter block pointer.
3294 * dev = database device entry pointer.
3295 *
3296 * Returns:
3297 * 0 = success.
3298 *
3299 * Context:
3300 * Kernel context.
3301 */
3302static int
e315cd28
AC		 3303qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3304 struct list_head *new_fcports)
1da177e4
LT		 3305{
3306 int rval;
3307 uint16_t loop_id;
3308 fc_port_t *fcport, *new_fcport, *fcptemp;
3309 int found;
3310
3311 sw_info_t *swl;
3312 int swl_idx;
3313 int first_dev, last_dev;
1516ef44 3314 port_id_t wrap = {}, nxt_d_id;
e315cd28
AC		 3315 struct qla_hw_data *ha = vha->hw;
3316 struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
ee546b6e 3317 struct scsi_qla_host *tvp;
1da177e4
LT		 3318
3319 rval = QLA_SUCCESS;
3320
3321 /* Try GID_PT to get device list, else GAN. */
7a67735b 3322 if (!ha->swl)
642ef983 3323 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3324 GFP_KERNEL);
3325 swl = ha->swl;
bbfbbbc1 3326 if (!swl) {
1da177e4 3327 /*EMPTY*/
7c3df132
SK		 3328 ql_dbg(ql_dbg_disc, vha, 0x2054,
3329 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3330 } else {
642ef983 3331 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3332 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3333 swl = NULL;
e315cd28 3334 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3335 swl = NULL;
e315cd28 3336 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3337 swl = NULL;
e5896bd5 3338 } else if (ql2xiidmaenable &&
e315cd28
AC		 3339 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3340 qla2x00_gpsc(vha, swl);
1da177e4 3341 }
e8c72ba5
CD		 3342
3343 /* If other queries succeeded probe for FC-4 type */
3344 if (swl)
3345 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3346 }
3347 swl_idx = 0;
3348
3349 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3350 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3351 if (new_fcport == NULL) {
7c3df132
SK		 3352 ql_log(ql_log_warn, vha, 0x205e,
3353 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3354 return (QLA_MEMORY_ALLOC_FAILED);
3355 }
3356 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3357 /* Set start port ID scan at adapter ID. */
3358 first_dev = 1;
3359 last_dev = 0;
3360
3361 /* Starting free loop ID. */
e315cd28
AC		 3362 loop_id = ha->min_external_loopid;
3363 for (; loop_id <= ha->max_loop_id; loop_id++) {
3364 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3365 continue;
3366
3a6478df
GM		 3367 if (ha->current_topology == ISP_CFG_FL &&
3368 (atomic_read(&vha->loop_down_timer) ||
3369 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3370 atomic_set(&vha->loop_down_timer, 0);
3371 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3372 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3373 break;
bb2d52b2 3374 }
1da177e4
LT		 3375
3376 if (swl != NULL) {
3377 if (last_dev) {
3378 wrap.b24 = new_fcport->d_id.b24;
3379 } else {
3380 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3381 memcpy(new_fcport->node_name,
3382 swl[swl_idx].node_name, WWN_SIZE);
3383 memcpy(new_fcport->port_name,
3384 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3385 memcpy(new_fcport->fabric_port_name,
3386 swl[swl_idx].fabric_port_name, WWN_SIZE);
3387 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3388 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3389
3390 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3391 last_dev = 1;
3392 }
3393 swl_idx++;
3394 }
3395 } else {
3396 /* Send GA_NXT to the switch */
e315cd28 3397 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3398 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3399 ql_log(ql_log_warn, vha, 0x2064,
3400 "SNS scan failed -- assuming "
3401 "zero-entry result.\n");
1da177e4
LT		 3402 list_for_each_entry_safe(fcport, fcptemp,
3403 new_fcports, list) {
3404 list_del(&fcport->list);
3405 kfree(fcport);
3406 }
3407 rval = QLA_SUCCESS;
3408 break;
3409 }
3410 }
3411
3412 /* If wrap on switch device list, exit. */
3413 if (first_dev) {
3414 wrap.b24 = new_fcport->d_id.b24;
3415 first_dev = 0;
3416 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3417 ql_dbg(ql_dbg_disc, vha, 0x2065,
3418 "Device wrap (%02x%02x%02x).\n",
3419 new_fcport->d_id.b.domain,
3420 new_fcport->d_id.b.area,
3421 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3422 break;
3423 }
3424
2c3dfe3f 3425 /* Bypass if same physical adapter. */
e315cd28 3426 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3427 continue;
3428
2c3dfe3f 3429 /* Bypass virtual ports of the same host. */
e315cd28
AC		 3430 found = 0;
3431 if (ha->num_vhosts) {
feafb7b1
AE		 3432 unsigned long flags;
3433
3434 spin_lock_irqsave(&ha->vport_slock, flags);
ee546b6e 3435 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
e315cd28
AC		 3436 if (new_fcport->d_id.b24 == vp->d_id.b24) {
3437 found = 1;
2c3dfe3f 3438 break;
e315cd28 3439 }
2c3dfe3f 3440 }
feafb7b1
AE		 3441 spin_unlock_irqrestore(&ha->vport_slock, flags);
3442
e315cd28 3443 if (found)
2c3dfe3f
SJ		 3444 continue;
3445 }
3446
f7d289f6
AV		 3447 /* Bypass if same domain and area of adapter. */
3448 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3449 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3450 ISP_CFG_FL)
3451 continue;
3452
1da177e4
LT		 3453 /* Bypass reserved domain fields. */
3454 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3455 continue;
3456
e8c72ba5 3457 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3458 if (ql2xgffidenable &&
3459 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3460 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3461 continue;
3462
1da177e4
LT		 3463 /* Locate matching device in database. */
3464 found = 0;
e315cd28 3465 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3466 if (memcmp(new_fcport->port_name, fcport->port_name,
3467 WWN_SIZE))
3468 continue;
3469
c0822b63 3470 fcport->scan_state = QLA_FCPORT_SCAN_FOUND;
b3b02e6e 3471
1da177e4
LT		 3472 found++;
3473
d8b45213
AV		 3474 /* Update port state. */
3475 memcpy(fcport->fabric_port_name,
3476 new_fcport->fabric_port_name, WWN_SIZE);
3477 fcport->fp_speed = new_fcport->fp_speed;
3478
1da177e4
LT		 3479 /*
3480 * If address the same and state FCS_ONLINE, nothing
3481 * changed.
3482 */
3483 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3484 atomic_read(&fcport->state) == FCS_ONLINE) {
3485 break;
3486 }
3487
3488 /*
3489 * If device was not a fabric device before.
3490 */
3491 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3492 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3493 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3494 fcport->flags |= (FCF_FABRIC_DEVICE |
3495 FCF_LOGIN_NEEDED);
1da177e4
LT		 3496 break;
3497 }
3498
3499 /*
3500 * Port ID changed or device was marked to be updated;
3501 * Log it out if still logged in and mark it for
3502 * relogin later.
3503 */
3504 fcport->d_id.b24 = new_fcport->d_id.b24;
3505 fcport->flags |= FCF_LOGIN_NEEDED;
3506 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3507 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3508 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3509 fcport->port_type != FCT_INITIATOR &&
3510 fcport->port_type != FCT_BROADCAST) {
e315cd28 3511 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3512 fcport->d_id.b.domain, fcport->d_id.b.area,
3513 fcport->d_id.b.al_pa);
5f16b331 3514 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3515 }
3516
3517 break;
3518 }
3519
3520 if (found)
3521 continue;
1da177e4
LT		 3522 /* If device was not in our fcports list, then add it. */
3523 list_add_tail(&new_fcport->list, new_fcports);
3524
3525 /* Allocate a new replacement fcport. */
3526 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3527 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3528 if (new_fcport == NULL) {
7c3df132
SK		 3529 ql_log(ql_log_warn, vha, 0x2066,
3530 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3531 return (QLA_MEMORY_ALLOC_FAILED);
3532 }
3533 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3534 new_fcport->d_id.b24 = nxt_d_id.b24;
3535 }
3536
c9475cb0 3537 kfree(new_fcport);
1da177e4 3538
1da177e4
LT		 3539 return (rval);
3540}
3541
3542/*
3543 * qla2x00_find_new_loop_id
3544 * Scan through our port list and find a new usable loop ID.
3545 *
3546 * Input:
3547 * ha: adapter state pointer.
3548 * dev: port structure pointer.
3549 *
3550 * Returns:
3551 * qla2x00 local function return status code.
3552 *
3553 * Context:
3554 * Kernel context.
3555 */
03bcfb57 3556int
e315cd28 3557qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3558{
3559 int rval;
e315cd28 3560 struct qla_hw_data *ha = vha->hw;
feafb7b1 3561 unsigned long flags = 0;
1da177e4
LT		 3562
3563 rval = QLA_SUCCESS;
3564
5f16b331 3565 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3566
5f16b331
CD		 3567 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3568 LOOPID_MAP_SIZE);
3569 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3570 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3571 dev->loop_id = FC_NO_LOOP_ID;
3572 rval = QLA_FUNCTION_FAILED;
3573 } else
3574 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3575
5f16b331 3576 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3577
5f16b331
CD		 3578 if (rval == QLA_SUCCESS)
3579 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3580 "Assigning new loopid=%x, portid=%x.\n",
3581 dev->loop_id, dev->d_id.b24);
3582 else
3583 ql_log(ql_log_warn, dev->vha, 0x2087,
3584 "No loop_id's available, portid=%x.\n",
3585 dev->d_id.b24);
1da177e4
LT		 3586
3587 return (rval);
3588}
3589
1da177e4
LT		 3590/*
3591 * qla2x00_fabric_dev_login
3592 * Login fabric target device and update FC port database.
3593 *
3594 * Input:
3595 * ha: adapter state pointer.
3596 * fcport: port structure list pointer.
3597 * next_loopid: contains value of a new loop ID that can be used
3598 * by the next login attempt.
3599 *
3600 * Returns:
3601 * qla2x00 local function return status code.
3602 *
3603 * Context:
3604 * Kernel context.
3605 */
3606static int
e315cd28 3607qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3608 uint16_t *next_loopid)
3609{
3610 int rval;
3611 int retry;
0107109e 3612 uint8_t opts;
e315cd28 3613 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3614
3615 rval = QLA_SUCCESS;
3616 retry = 0;
3617
ac280b67 3618 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3619 if (fcport->flags & FCF_ASYNC_SENT)
3620 return rval;
3621 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3622 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3623 if (!rval)
3624 return rval;
3625 }
3626
5ff1d584 3627 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3628 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3629 if (rval == QLA_SUCCESS) {
f08b7251 3630 /* Send an ADISC to FCP2 devices.*/
0107109e 3631 opts = 0;
f08b7251 3632 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3633 opts |= BIT_1;
e315cd28 3634 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3635 if (rval != QLA_SUCCESS) {
e315cd28 3636 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3637 fcport->d_id.b.domain, fcport->d_id.b.area,
3638 fcport->d_id.b.al_pa);
e315cd28 3639 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3640 } else {
e315cd28 3641 qla2x00_update_fcport(vha, fcport);
1da177e4 3642 }
0b91d116
CD		 3643 } else {
3644 /* Retry Login. */
3645 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3646 }
3647
3648 return (rval);
3649}
3650
3651/*
3652 * qla2x00_fabric_login
3653 * Issue fabric login command.
3654 *
3655 * Input:
3656 * ha = adapter block pointer.
3657 * device = pointer to FC device type structure.
3658 *
3659 * Returns:
3660 * 0 - Login successfully
3661 * 1 - Login failed
3662 * 2 - Initiator device
3663 * 3 - Fatal error
3664 */
3665int
e315cd28 3666qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3667 uint16_t *next_loopid)
3668{
3669 int rval;
3670 int retry;
3671 uint16_t tmp_loopid;
3672 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3673 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3674
3675 retry = 0;
3676 tmp_loopid = 0;
3677
3678 for (;;) {
7c3df132
SK		 3679 ql_dbg(ql_dbg_disc, vha, 0x2000,
3680 "Trying Fabric Login w/loop id 0x%04x for port "
3681 "%02x%02x%02x.\n",
3682 fcport->loop_id, fcport->d_id.b.domain,
3683 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3684
3685 /* Login fcport on switch. */
0b91d116 3686 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3687 fcport->d_id.b.domain, fcport->d_id.b.area,
3688 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3689 if (rval != QLA_SUCCESS) {
3690 return rval;
3691 }
1da177e4
LT		 3692 if (mb[0] == MBS_PORT_ID_USED) {
3693 /*
3694 * Device has another loop ID. The firmware team
0107109e
AV		 3695 * recommends the driver perform an implicit login with
3696 * the specified ID again. The ID we just used is save
3697 * here so we return with an ID that can be tried by
3698 * the next login.
1da177e4
LT		 3699 */
3700 retry++;
3701 tmp_loopid = fcport->loop_id;
3702 fcport->loop_id = mb[1];
3703
7c3df132
SK		 3704 ql_dbg(ql_dbg_disc, vha, 0x2001,
3705 "Fabric Login: port in use - next loop "
3706 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3707 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3708 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3709
3710 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3711 /*
3712 * Login succeeded.
3713 */
3714 if (retry) {
3715 /* A retry occurred before. */
3716 *next_loopid = tmp_loopid;
3717 } else {
3718 /*
3719 * No retry occurred before. Just increment the
3720 * ID value for next login.
3721 */
3722 *next_loopid = (fcport->loop_id + 1);
3723 }
3724
3725 if (mb[1] & BIT_0) {
3726 fcport->port_type = FCT_INITIATOR;
3727 } else {
3728 fcport->port_type = FCT_TARGET;
3729 if (mb[1] & BIT_1) {
8474f3a0 3730 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3731 }
3732 }
3733
ad3e0eda
AV		 3734 if (mb[10] & BIT_0)
3735 fcport->supported_classes |= FC_COS_CLASS2;
3736 if (mb[10] & BIT_1)
3737 fcport->supported_classes |= FC_COS_CLASS3;
3738
2d70c103
NB		 3739 if (IS_FWI2_CAPABLE(ha)) {
3740 if (mb[10] & BIT_7)
3741 fcport->flags |=
3742 FCF_CONF_COMP_SUPPORTED;
3743 }
3744
1da177e4
LT		 3745 rval = QLA_SUCCESS;
3746 break;
3747 } else if (mb[0] == MBS_LOOP_ID_USED) {
3748 /*
3749 * Loop ID already used, try next loop ID.
3750 */
3751 fcport->loop_id++;
e315cd28 3752 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3753 if (rval != QLA_SUCCESS) {
3754 /* Ran out of loop IDs to use */
3755 break;
3756 }
3757 } else if (mb[0] == MBS_COMMAND_ERROR) {
3758 /*
3759 * Firmware possibly timed out during login. If NO
3760 * retries are left to do then the device is declared
3761 * dead.
3762 */
3763 *next_loopid = fcport->loop_id;
e315cd28 3764 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3765 fcport->d_id.b.domain, fcport->d_id.b.area,
3766 fcport->d_id.b.al_pa);
e315cd28 3767 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3768
3769 rval = 1;
3770 break;
3771 } else {
3772 /*
3773 * unrecoverable / not handled error
3774 */
7c3df132
SK		 3775 ql_dbg(ql_dbg_disc, vha, 0x2002,
3776 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3777 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3778 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3779 fcport->loop_id, jiffies);
1da177e4
LT		 3780
3781 *next_loopid = fcport->loop_id;
e315cd28 3782 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3783 fcport->d_id.b.domain, fcport->d_id.b.area,
3784 fcport->d_id.b.al_pa);
5f16b331 3785 qla2x00_clear_loop_id(fcport);
0eedfcf0 3786 fcport->login_retry = 0;
1da177e4
LT		 3787
3788 rval = 3;
3789 break;
3790 }
3791 }
3792
3793 return (rval);
3794}
3795
3796/*
3797 * qla2x00_local_device_login
3798 * Issue local device login command.
3799 *
3800 * Input:
3801 * ha = adapter block pointer.
3802 * loop_id = loop id of device to login to.
3803 *
3804 * Returns (Where's the #define!!!!):
3805 * 0 - Login successfully
3806 * 1 - Login failed
3807 * 3 - Fatal error
3808 */
3809int
e315cd28 3810qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3811{
3812 int rval;
3813 uint16_t mb[MAILBOX_REGISTER_COUNT];
3814
3815 memset(mb, 0, sizeof(mb));
e315cd28 3816 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3817 if (rval == QLA_SUCCESS) {
3818 /* Interrogate mailbox registers for any errors */
3819 if (mb[0] == MBS_COMMAND_ERROR)
3820 rval = 1;
3821 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3822 /* device not in PCB table */
3823 rval = 3;
3824 }
3825
3826 return (rval);
3827}
3828
3829/*
3830 * qla2x00_loop_resync
3831 * Resync with fibre channel devices.
3832 *
3833 * Input:
3834 * ha = adapter block pointer.
3835 *
3836 * Returns:
3837 * 0 = success
3838 */
3839int
e315cd28 3840qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3841{
73208dfd 3842 int rval = QLA_SUCCESS;
1da177e4 3843 uint32_t wait_time;
67c2e93a
AC		 3844 struct req_que *req;
3845 struct rsp_que *rsp;
3846
7163ea81 3847 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3848 req = vha->hw->req_q_map[0];
3849 else
3850 req = vha->req;
3851 rsp = req->rsp;
1da177e4 3852
e315cd28
AC		 3853 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3854 if (vha->flags.online) {
3855 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3856 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3857 wait_time = 256;
3858 do {
0107109e 3859 /* Issue a marker after FW becomes ready. */
73208dfd
AC		 3860 qla2x00_marker(vha, req, rsp, 0, 0,
3861 MK_SYNC_ALL);
e315cd28 3862 vha->marker_needed = 0;
1da177e4
LT		 3863
3864 /* Remap devices on Loop. */
e315cd28 3865 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3866
e315cd28 3867 qla2x00_configure_loop(vha);
1da177e4 3868 wait_time--;
e315cd28
AC		 3869 } while (!atomic_read(&vha->loop_down_timer) &&
3870 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3871 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3872 &vha->dpc_flags)));
1da177e4 3873 }
1da177e4
LT		 3874 }
3875
e315cd28 3876 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3877 return (QLA_FUNCTION_FAILED);
1da177e4 3878
e315cd28 3879 if (rval)
7c3df132
SK		 3880 ql_dbg(ql_dbg_disc, vha, 0x206c,
3881 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3882
3883 return (rval);
3884}
3885
579d12b5
SK		 3886/*
3887* qla2x00_perform_loop_resync
3888* Description: This function will set the appropriate flags and call
3889* qla2x00_loop_resync. If successful loop will be resynced
3890* Arguments : scsi_qla_host_t pointer
3891* returm : Success or Failure
3892*/
3893
3894int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3895{
3896 int32_t rval = 0;
3897
3898 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3899 /*Configure the flags so that resync happens properly*/
3900 atomic_set(&ha->loop_down_timer, 0);
3901 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3902 atomic_set(&ha->loop_state, LOOP_UP);
3903 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3904 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3905 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3906
3907 rval = qla2x00_loop_resync(ha);
3908 } else
3909 atomic_set(&ha->loop_state, LOOP_DEAD);
3910
3911 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3912 }
3913
3914 return rval;
3915}
3916
d97994dc 3917void
67becc00 3918qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 3919{
3920 fc_port_t *fcport;
feafb7b1
AE		 3921 struct scsi_qla_host *vha;
3922 struct qla_hw_data *ha = base_vha->hw;
3923 unsigned long flags;
d97994dc 3924
feafb7b1 3925 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 3926 /* Go with deferred removal of rport references. */
feafb7b1
AE		 3927 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3928 atomic_inc(&vha->vref_count);
3929 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 3930 if (fcport->drport &&
feafb7b1
AE		 3931 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3932 spin_unlock_irqrestore(&ha->vport_slock, flags);
3933
67becc00 3934 qla2x00_rport_del(fcport);
feafb7b1
AE		 3935
3936 spin_lock_irqsave(&ha->vport_slock, flags);
3937 }
3938 }
3939 atomic_dec(&vha->vref_count);
3940 }
3941 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 3942}
3943
7d613ac6
SV		 3944/* Assumes idc_lock always held on entry */
3945void
3946qla83xx_reset_ownership(scsi_qla_host_t *vha)
3947{
3948 struct qla_hw_data *ha = vha->hw;
3949 uint32_t drv_presence, drv_presence_mask;
3950 uint32_t dev_part_info1, dev_part_info2, class_type;
3951 uint32_t class_type_mask = 0x3;
3952 uint16_t fcoe_other_function = 0xffff, i;
3953
3954 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
3955
3956 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
3957 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
3958 for (i = 0; i < 8; i++) {
3959 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
3960 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3961 (i != ha->portnum)) {
3962 fcoe_other_function = i;
3963 break;
3964 }
3965 }
3966 if (fcoe_other_function == 0xffff) {
3967 for (i = 0; i < 8; i++) {
3968 class_type = ((dev_part_info2 >> (i * 4)) &
3969 class_type_mask);
3970 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3971 ((i + 8) != ha->portnum)) {
3972 fcoe_other_function = i + 8;
3973 break;
3974 }
3975 }
3976 }
3977 /*
3978 * Prepare drv-presence mask based on fcoe functions present.
3979 * However consider only valid physical fcoe function numbers (0-15).
3980 */
3981 drv_presence_mask = ~((1 << (ha->portnum)) |
3982 ((fcoe_other_function == 0xffff) ?
3983 0 : (1 << (fcoe_other_function))));
3984
3985 /* We are the reset owner iff:
3986 * - No other protocol drivers present.
3987 * - This is the lowest among fcoe functions. */
3988 if (!(drv_presence & drv_presence_mask) &&
3989 (ha->portnum < fcoe_other_function)) {
3990 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
3991 "This host is Reset owner.\n");
3992 ha->flags.nic_core_reset_owner = 1;
3993 }
3994}
3995
fa492630 3996static int
7d613ac6
SV		 3997__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
3998{
3999 int rval = QLA_SUCCESS;
4000 struct qla_hw_data *ha = vha->hw;
4001 uint32_t drv_ack;
4002
4003 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4004 if (rval == QLA_SUCCESS) {
4005 drv_ack |= (1 << ha->portnum);
4006 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4007 }
4008
4009 return rval;
4010}
4011
fa492630 4012static int
7d613ac6
SV		 4013__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4014{
4015 int rval = QLA_SUCCESS;
4016 struct qla_hw_data *ha = vha->hw;
4017 uint32_t drv_ack;
4018
4019 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4020 if (rval == QLA_SUCCESS) {
4021 drv_ack &= ~(1 << ha->portnum);
4022 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4023 }
4024
4025 return rval;
4026}
4027
fa492630 4028static const char *
7d613ac6
SV		 4029qla83xx_dev_state_to_string(uint32_t dev_state)
4030{
4031 switch (dev_state) {
4032 case QLA8XXX_DEV_COLD:
4033 return "COLD/RE-INIT";
4034 case QLA8XXX_DEV_INITIALIZING:
4035 return "INITIALIZING";
4036 case QLA8XXX_DEV_READY:
4037 return "READY";
4038 case QLA8XXX_DEV_NEED_RESET:
4039 return "NEED RESET";
4040 case QLA8XXX_DEV_NEED_QUIESCENT:
4041 return "NEED QUIESCENT";
4042 case QLA8XXX_DEV_FAILED:
4043 return "FAILED";
4044 case QLA8XXX_DEV_QUIESCENT:
4045 return "QUIESCENT";
4046 default:
4047 return "Unknown";
4048 }
4049}
4050
4051/* Assumes idc-lock always held on entry */
4052void
4053qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4054{
4055 struct qla_hw_data *ha = vha->hw;
4056 uint32_t idc_audit_reg = 0, duration_secs = 0;
4057
4058 switch (audit_type) {
4059 case IDC_AUDIT_TIMESTAMP:
4060 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4061 idc_audit_reg = (ha->portnum) |
4062 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4063 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4064 break;
4065
4066 case IDC_AUDIT_COMPLETION:
4067 duration_secs = ((jiffies_to_msecs(jiffies) -
4068 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4069 idc_audit_reg = (ha->portnum) |
4070 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4071 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4072 break;
4073
4074 default:
4075 ql_log(ql_log_warn, vha, 0xb078,
4076 "Invalid audit type specified.\n");
4077 break;
4078 }
4079}
4080
4081/* Assumes idc_lock always held on entry */
fa492630 4082static int
7d613ac6
SV		 4083qla83xx_initiating_reset(scsi_qla_host_t *vha)
4084{
4085 struct qla_hw_data *ha = vha->hw;
4086 uint32_t idc_control, dev_state;
4087
4088 __qla83xx_get_idc_control(vha, &idc_control);
4089 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4090 ql_log(ql_log_info, vha, 0xb080,
4091 "NIC Core reset has been disabled. idc-control=0x%x\n",
4092 idc_control);
4093 return QLA_FUNCTION_FAILED;
4094 }
4095
4096 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4097 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4098 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4099 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4100 QLA8XXX_DEV_NEED_RESET);
4101 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4102 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4103 } else {
4104 const char *state = qla83xx_dev_state_to_string(dev_state);
4105 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4106
4107 /* SV: XXX: Is timeout required here? */
4108 /* Wait for IDC state change READY -> NEED_RESET */
4109 while (dev_state == QLA8XXX_DEV_READY) {
4110 qla83xx_idc_unlock(vha, 0);
4111 msleep(200);
4112 qla83xx_idc_lock(vha, 0);
4113 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4114 }
4115 }
4116
4117 /* Send IDC ack by writing to drv-ack register */
4118 __qla83xx_set_drv_ack(vha);
4119
4120 return QLA_SUCCESS;
4121}
4122
4123int
4124__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4125{
4126 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4127}
4128
7d613ac6
SV		 4129int
4130__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4131{
4132 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4133}
4134
fa492630 4135static int
7d613ac6
SV		 4136qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4137{
4138 uint32_t drv_presence = 0;
4139 struct qla_hw_data *ha = vha->hw;
4140
4141 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4142 if (drv_presence & (1 << ha->portnum))
4143 return QLA_SUCCESS;
4144 else
4145 return QLA_TEST_FAILED;
4146}
4147
4148int
4149qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4150{
4151 int rval = QLA_SUCCESS;
4152 struct qla_hw_data *ha = vha->hw;
4153
4154 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4155 "Entered %s().\n", __func__);
4156
4157 if (vha->device_flags & DFLG_DEV_FAILED) {
4158 ql_log(ql_log_warn, vha, 0xb059,
4159 "Device in unrecoverable FAILED state.\n");
4160 return QLA_FUNCTION_FAILED;
4161 }
4162
4163 qla83xx_idc_lock(vha, 0);
4164
4165 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4166 ql_log(ql_log_warn, vha, 0xb05a,
4167 "Function=0x%x has been removed from IDC participation.\n",
4168 ha->portnum);
4169 rval = QLA_FUNCTION_FAILED;
4170 goto exit;
4171 }
4172
4173 qla83xx_reset_ownership(vha);
4174
4175 rval = qla83xx_initiating_reset(vha);
4176
4177 /*
4178 * Perform reset if we are the reset-owner,
4179 * else wait till IDC state changes to READY/FAILED.
4180 */
4181 if (rval == QLA_SUCCESS) {
4182 rval = qla83xx_idc_state_handler(vha);
4183
4184 if (rval == QLA_SUCCESS)
4185 ha->flags.nic_core_hung = 0;
4186 __qla83xx_clear_drv_ack(vha);
4187 }
4188
4189exit:
4190 qla83xx_idc_unlock(vha, 0);
4191
4192 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4193
4194 return rval;
4195}
4196
81178772
SK		 4197int
4198qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4199{
4200 struct qla_hw_data *ha = vha->hw;
4201 int rval = QLA_FUNCTION_FAILED;
4202
4203 if (!IS_MCTP_CAPABLE(ha)) {
4204 /* This message can be removed from the final version */
4205 ql_log(ql_log_info, vha, 0x506d,
4206 "This board is not MCTP capable\n");
4207 return rval;
4208 }
4209
4210 if (!ha->mctp_dump) {
4211 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4212 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4213
4214 if (!ha->mctp_dump) {
4215 ql_log(ql_log_warn, vha, 0x506e,
4216 "Failed to allocate memory for mctp dump\n");
4217 return rval;
4218 }
4219 }
4220
4221#define MCTP_DUMP_STR_ADDR 0x00000000
4222 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4223 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4224 if (rval != QLA_SUCCESS) {
4225 ql_log(ql_log_warn, vha, 0x506f,
4226 "Failed to capture mctp dump\n");
4227 } else {
4228 ql_log(ql_log_info, vha, 0x5070,
4229 "Mctp dump capture for host (%ld/%p).\n",
4230 vha->host_no, ha->mctp_dump);
4231 ha->mctp_dumped = 1;
4232 }
4233
409ee0fe 4234 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4235 ha->flags.nic_core_reset_hdlr_active = 1;
4236 rval = qla83xx_restart_nic_firmware(vha);
4237 if (rval)
4238 /* NIC Core reset failed. */
4239 ql_log(ql_log_warn, vha, 0x5071,
4240 "Failed to restart nic firmware\n");
4241 else
4242 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4243 "Restarted NIC firmware successfully.\n");
4244 ha->flags.nic_core_reset_hdlr_active = 0;
4245 }
4246
4247 return rval;
4248
4249}
4250
579d12b5 4251/*
8fcd6b8b 4252* qla2x00_quiesce_io
579d12b5
SK		 4253* Description: This function will block the new I/Os
4254* Its not aborting any I/Os as context
4255* is not destroyed during quiescence
4256* Arguments: scsi_qla_host_t
4257* return : void
4258*/
4259void
8fcd6b8b 4260qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4261{
4262 struct qla_hw_data *ha = vha->hw;
4263 struct scsi_qla_host *vp;
4264
8fcd6b8b
CD		 4265 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4266 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4267
4268 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4269 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4270 atomic_set(&vha->loop_state, LOOP_DOWN);
4271 qla2x00_mark_all_devices_lost(vha, 0);
4272 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4273 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4274 } else {
4275 if (!atomic_read(&vha->loop_down_timer))
4276 atomic_set(&vha->loop_down_timer,
4277 LOOP_DOWN_TIME);
4278 }
4279 /* Wait for pending cmds to complete */
4280 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4281}
4282
a9083016
GM		 4283void
4284qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4285{
4286 struct qla_hw_data *ha = vha->hw;
579d12b5 4287 struct scsi_qla_host *vp;
feafb7b1 4288 unsigned long flags;
6aef87be 4289 fc_port_t *fcport;
a9083016 4290
e46ef004
SK		 4291 /* For ISP82XX, driver waits for completion of the commands.
4292 * online flag should be set.
4293 */
4294 if (!IS_QLA82XX(ha))
4295 vha->flags.online = 0;
a9083016
GM		 4296 ha->flags.chip_reset_done = 0;
4297 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4298 vha->qla_stats.total_isp_aborts++;
a9083016 4299
7c3df132
SK		 4300 ql_log(ql_log_info, vha, 0x00af,
4301 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4302
e46ef004
SK		 4303 /* For ISP82XX, reset_chip is just disabling interrupts.
4304 * Driver waits for the completion of the commands.
4305 * the interrupts need to be enabled.
4306 */
a9083016
GM		 4307 if (!IS_QLA82XX(ha))
4308 ha->isp_ops->reset_chip(vha);
4309
4310 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4311 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4312 atomic_set(&vha->loop_state, LOOP_DOWN);
4313 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4314
4315 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4316 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4317 atomic_inc(&vp->vref_count);
4318 spin_unlock_irqrestore(&ha->vport_slock, flags);
4319
a9083016 4320 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4321
4322 spin_lock_irqsave(&ha->vport_slock, flags);
4323 atomic_dec(&vp->vref_count);
4324 }
4325 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4326 } else {
4327 if (!atomic_read(&vha->loop_down_timer))
4328 atomic_set(&vha->loop_down_timer,
4329 LOOP_DOWN_TIME);
4330 }
4331
6aef87be
AV		 4332 /* Clear all async request states across all VPs. */
4333 list_for_each_entry(fcport, &vha->vp_fcports, list)
4334 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4335 spin_lock_irqsave(&ha->vport_slock, flags);
4336 list_for_each_entry(vp, &ha->vp_list, list) {
4337 atomic_inc(&vp->vref_count);
4338 spin_unlock_irqrestore(&ha->vport_slock, flags);
4339
4340 list_for_each_entry(fcport, &vp->vp_fcports, list)
4341 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4342
4343 spin_lock_irqsave(&ha->vport_slock, flags);
4344 atomic_dec(&vp->vref_count);
4345 }
4346 spin_unlock_irqrestore(&ha->vport_slock, flags);
4347
bddd2d65
LC		 4348 if (!ha->flags.eeh_busy) {
4349 /* Make sure for ISP 82XX IO DMA is complete */
4350 if (IS_QLA82XX(ha)) {
7190575f 4351 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4352 ql_log(ql_log_info, vha, 0x00b4,
4353 "Done chip reset cleanup.\n");
a9083016 4354
e46ef004
SK		 4355 /* Done waiting for pending commands.
4356 * Reset the online flag.
4357 */
4358 vha->flags.online = 0;
4d78c973 4359 }
a9083016 4360
bddd2d65
LC		 4361 /* Requeue all commands in outstanding command list. */
4362 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4363 }
a9083016
GM		 4364}
4365
1da177e4
LT		 4366/*
4367* qla2x00_abort_isp
4368* Resets ISP and aborts all outstanding commands.
4369*
4370* Input:
4371* ha = adapter block pointer.
4372*
4373* Returns:
4374* 0 = success
4375*/
4376int
e315cd28 4377qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4378{
476e8978 4379 int rval;
1da177e4 4380 uint8_t status = 0;
e315cd28
AC		 4381 struct qla_hw_data *ha = vha->hw;
4382 struct scsi_qla_host *vp;
73208dfd 4383 struct req_que *req = ha->req_q_map[0];
feafb7b1 4384 unsigned long flags;
1da177e4 4385
e315cd28 4386 if (vha->flags.online) {
a9083016 4387 qla2x00_abort_isp_cleanup(vha);
1da177e4 4388
a6171297
SV		 4389 if (IS_QLA8031(ha)) {
4390 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4391 "Clearing fcoe driver presence.\n");
4392 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4393 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4394 "Error while clearing DRV-Presence.\n");
4395 }
4396
85880801
AV		 4397 if (unlikely(pci_channel_offline(ha->pdev) &&
4398 ha->flags.pci_channel_io_perm_failure)) {
4399 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4400 status = 0;
4401 return status;
4402 }
4403
73208dfd 4404 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4405
e315cd28 4406 ha->isp_ops->nvram_config(vha);
1da177e4 4407
e315cd28
AC		 4408 if (!qla2x00_restart_isp(vha)) {
4409 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4410
e315cd28 4411 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4412 /*
4413 * Issue marker command only when we are going
4414 * to start the I/O .
4415 */
e315cd28 4416 vha->marker_needed = 1;
1da177e4
LT		 4417 }
4418
e315cd28 4419 vha->flags.online = 1;
1da177e4 4420
fd34f556 4421 ha->isp_ops->enable_intrs(ha);
1da177e4 4422
fa2a1ce5 4423 ha->isp_abort_cnt = 0;
e315cd28 4424 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4425
6246b8a1
GM		 4426 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4427 qla2x00_get_fw_version(vha);
df613b96
AV		 4428 if (ha->fce) {
4429 ha->flags.fce_enabled = 1;
4430 memset(ha->fce, 0,
4431 fce_calc_size(ha->fce_bufs));
e315cd28 4432 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4433 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4434 &ha->fce_bufs);
4435 if (rval) {
7c3df132 4436 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4437 "Unable to reinitialize FCE "
4438 "(%d).\n", rval);
4439 ha->flags.fce_enabled = 0;
4440 }
4441 }
436a7b11
AV		 4442
4443 if (ha->eft) {
4444 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4445 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4446 ha->eft_dma, EFT_NUM_BUFFERS);
4447 if (rval) {
7c3df132 4448 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4449 "Unable to reinitialize EFT "
4450 "(%d).\n", rval);
4451 }
4452 }
1da177e4 4453 } else { /* failed the ISP abort */
e315cd28
AC		 4454 vha->flags.online = 1;
4455 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4456 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4457 ql_log(ql_log_fatal, vha, 0x8035,
4458 "ISP error recover failed - "
4459 "board disabled.\n");
fa2a1ce5 4460 /*
1da177e4
LT		 4461 * The next call disables the board
4462 * completely.
4463 */
e315cd28
AC		 4464 ha->isp_ops->reset_adapter(vha);
4465 vha->flags.online = 0;
1da177e4 4466 clear_bit(ISP_ABORT_RETRY,
e315cd28 4467 &vha->dpc_flags);
1da177e4
LT		 4468 status = 0;
4469 } else { /* schedule another ISP abort */
4470 ha->isp_abort_cnt--;
7c3df132
SK		 4471 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4472 "ISP abort - retry remaining %d.\n",
4473 ha->isp_abort_cnt);
1da177e4
LT		 4474 status = 1;
4475 }
4476 } else {
4477 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4478 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4479 "ISP error recovery - retrying (%d) "
4480 "more times.\n", ha->isp_abort_cnt);
e315cd28 4481 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4482 status = 1;
4483 }
4484 }
fa2a1ce5 4485
1da177e4
LT		 4486 }
4487
e315cd28 4488 if (!status) {
7c3df132 4489 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4490
4491 spin_lock_irqsave(&ha->vport_slock, flags);
4492 list_for_each_entry(vp, &ha->vp_list, list) {
4493 if (vp->vp_idx) {
4494 atomic_inc(&vp->vref_count);
4495 spin_unlock_irqrestore(&ha->vport_slock, flags);
4496
e315cd28 4497 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4498
4499 spin_lock_irqsave(&ha->vport_slock, flags);
4500 atomic_dec(&vp->vref_count);
4501 }
e315cd28 4502 }
feafb7b1
AE		 4503 spin_unlock_irqrestore(&ha->vport_slock, flags);
4504
7d613ac6
SV		 4505 if (IS_QLA8031(ha)) {
4506 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4507 "Setting back fcoe driver presence.\n");
4508 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4509 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4510 "Error while setting DRV-Presence.\n");
4511 }
e315cd28 4512 } else {
d8424f68
JP		 4513 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4514 __func__);
1da177e4
LT		 4515 }
4516
4517 return(status);
4518}
4519
4520/*
4521* qla2x00_restart_isp
4522* restarts the ISP after a reset
4523*
4524* Input:
4525* ha = adapter block pointer.
4526*
4527* Returns:
4528* 0 = success
4529*/
4530static int
e315cd28 4531qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4532{
c6b2fca8 4533 int status = 0;
1da177e4 4534 uint32_t wait_time;
e315cd28 4535 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4536 struct req_que *req = ha->req_q_map[0];
4537 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4538 unsigned long flags;
1da177e4
LT		 4539
4540 /* If firmware needs to be loaded */
e315cd28
AC		 4541 if (qla2x00_isp_firmware(vha)) {
4542 vha->flags.online = 0;
4543 status = ha->isp_ops->chip_diag(vha);
4544 if (!status)
4545 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4546 }
4547
e315cd28
AC		 4548 if (!status && !(status = qla2x00_init_rings(vha))) {
4549 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4550 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4551 /* Initialize the queues in use */
4552 qla25xx_init_queues(ha);
4553
e315cd28
AC		 4554 status = qla2x00_fw_ready(vha);
4555 if (!status) {
7c3df132
SK		 4556 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4557 "Start configure loop status = %d.\n", status);
0107109e
AV		 4558
4559 /* Issue a marker after FW becomes ready. */
73208dfd 4560 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4561
e315cd28 4562 vha->flags.online = 1;
2d70c103
NB		 4563
4564 /*
4565 * Process any ATIO queue entries that came in
4566 * while we weren't online.
4567 */
4568 spin_lock_irqsave(&ha->hardware_lock, flags);
4569 if (qla_tgt_mode_enabled(vha))
4570 qlt_24xx_process_atio_queue(vha);
4571 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4572
1da177e4
LT		 4573 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4574 wait_time = 256;
4575 do {
e315cd28
AC		 4576 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4577 qla2x00_configure_loop(vha);
1da177e4 4578 wait_time--;
e315cd28
AC		 4579 } while (!atomic_read(&vha->loop_down_timer) &&
4580 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4581 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4582 &vha->dpc_flags)));
1da177e4
LT		 4583 }
4584
4585 /* if no cable then assume it's good */
e315cd28 4586 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4587 status = 0;
4588
7c3df132
SK		 4589 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4590 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4591 }
4592 return (status);
4593}
4594
73208dfd
AC		 4595static int
4596qla25xx_init_queues(struct qla_hw_data *ha)
4597{
4598 struct rsp_que *rsp = NULL;
4599 struct req_que *req = NULL;
4600 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4601 int ret = -1;
4602 int i;
4603
2afa19a9 4604 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4605 rsp = ha->rsp_q_map[i];
4606 if (rsp) {
4607 rsp->options &= ~BIT_0;
618a7523 4608 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4609 if (ret != QLA_SUCCESS)
7c3df132
SK		 4610 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4611 "%s Rsp que: %d init failed.\n",
4612 __func__, rsp->id);
73208dfd 4613 else
7c3df132
SK		 4614 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4615 "%s Rsp que: %d inited.\n",
4616 __func__, rsp->id);
73208dfd 4617 }
2afa19a9
AC		 4618 }
4619 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4620 req = ha->req_q_map[i];
4621 if (req) {
29bdccbe 4622 /* Clear outstanding commands array. */
73208dfd 4623 req->options &= ~BIT_0;
618a7523 4624 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4625 if (ret != QLA_SUCCESS)
7c3df132
SK		 4626 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4627 "%s Req que: %d init failed.\n",
4628 __func__, req->id);
73208dfd 4629 else
7c3df132
SK		 4630 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4631 "%s Req que: %d inited.\n",
4632 __func__, req->id);
73208dfd
AC		 4633 }
4634 }
4635 return ret;
4636}
4637
1da177e4
LT		 4638/*
4639* qla2x00_reset_adapter
4640* Reset adapter.
4641*
4642* Input:
4643* ha = adapter block pointer.
4644*/
abbd8870 4645void
e315cd28 4646qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4647{
4648 unsigned long flags = 0;
e315cd28 4649 struct qla_hw_data *ha = vha->hw;
3d71644c 4650 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4651
e315cd28 4652 vha->flags.online = 0;
fd34f556 4653 ha->isp_ops->disable_intrs(ha);
1da177e4 4654
1da177e4
LT		 4655 spin_lock_irqsave(&ha->hardware_lock, flags);
4656 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4657 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4658 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4659 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4660 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4661}
0107109e
AV		 4662
4663void
e315cd28 4664qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4665{
4666 unsigned long flags = 0;
e315cd28 4667 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4668 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4669
a9083016
GM		 4670 if (IS_QLA82XX(ha))
4671 return;
4672
e315cd28 4673 vha->flags.online = 0;
fd34f556 4674 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4675
4676 spin_lock_irqsave(&ha->hardware_lock, flags);
4677 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4678 RD_REG_DWORD(&reg->hccr);
4679 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4680 RD_REG_DWORD(&reg->hccr);
4681 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4682
4683 if (IS_NOPOLLING_TYPE(ha))
4684 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4685}
4686
4e08df3f
DM		 4687/* On sparc systems, obtain port and node WWN from firmware
4688 * properties.
4689 */
e315cd28
AC		 4690static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4691 struct nvram_24xx *nv)
4e08df3f
DM		 4692{
4693#ifdef CONFIG_SPARC
e315cd28 4694 struct qla_hw_data *ha = vha->hw;
4e08df3f 4695 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4696 struct device_node *dp = pci_device_to_OF_node(pdev);
4697 const u8 *val;
4e08df3f
DM		 4698 int len;
4699
4700 val = of_get_property(dp, "port-wwn", &len);
4701 if (val && len >= WWN_SIZE)
4702 memcpy(nv->port_name, val, WWN_SIZE);
4703
4704 val = of_get_property(dp, "node-wwn", &len);
4705 if (val && len >= WWN_SIZE)
4706 memcpy(nv->node_name, val, WWN_SIZE);
4707#endif
4708}
4709
0107109e 4710int
e315cd28 4711qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4712{
4e08df3f 4713 int rval;
0107109e
AV		 4714 struct init_cb_24xx *icb;
4715 struct nvram_24xx *nv;
4716 uint32_t *dptr;
4717 uint8_t *dptr1, *dptr2;
4718 uint32_t chksum;
4719 uint16_t cnt;
e315cd28 4720 struct qla_hw_data *ha = vha->hw;
0107109e 4721
4e08df3f 4722 rval = QLA_SUCCESS;
0107109e 4723 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4724 nv = ha->nvram;
0107109e
AV		 4725
4726 /* Determine NVRAM starting address. */
e5b68a61
AC		 4727 if (ha->flags.port0) {
4728 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4729 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4730 } else {
0107109e 4731 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 4732 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4733 }
e5b68a61
AC		 4734 ha->nvram_size = sizeof(struct nvram_24xx);
4735 ha->vpd_size = FA_NVRAM_VPD_SIZE;
a9083016
GM		 4736 if (IS_QLA82XX(ha))
4737 ha->vpd_size = FA_VPD_SIZE_82XX;
0107109e 4738
281afe19
SJ		 4739 /* Get VPD data into cache */
4740 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4741 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4742 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4743
4744 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4745 dptr = (uint32_t *)nv;
e315cd28 4746 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4747 ha->nvram_size);
4748 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4749 chksum += le32_to_cpu(*dptr++);
4750
7c3df132
SK		 4751 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4752 "Contents of NVRAM\n");
4753 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4754 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4755
4756 /* Bad NVRAM data, set defaults parameters. */
4757 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4758 || nv->id[3] != ' ' ||
4759 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4760 /* Reset NVRAM data. */
7c3df132 4761 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4762 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4763 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4764 ql_log(ql_log_warn, vha, 0x006c,
4765 "Falling back to functioning (yet invalid -- WWPN) "
4766 "defaults.\n");
4e08df3f
DM		 4767
4768 /*
4769 * Set default initialization control block.
4770 */
4771 memset(nv, 0, ha->nvram_size);
4772 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4773 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4774 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4775 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4776 nv->exchange_count = __constant_cpu_to_le16(0);
4777 nv->hard_address = __constant_cpu_to_le16(124);
4778 nv->port_name[0] = 0x21;
e5b68a61 4779 nv->port_name[1] = 0x00 + ha->port_no;
4e08df3f
DM		 4780 nv->port_name[2] = 0x00;
4781 nv->port_name[3] = 0xe0;
4782 nv->port_name[4] = 0x8b;
4783 nv->port_name[5] = 0x1c;
4784 nv->port_name[6] = 0x55;
4785 nv->port_name[7] = 0x86;
4786 nv->node_name[0] = 0x20;
4787 nv->node_name[1] = 0x00;
4788 nv->node_name[2] = 0x00;
4789 nv->node_name[3] = 0xe0;
4790 nv->node_name[4] = 0x8b;
4791 nv->node_name[5] = 0x1c;
4792 nv->node_name[6] = 0x55;
4793 nv->node_name[7] = 0x86;
e315cd28 4794 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4795 nv->login_retry_count = __constant_cpu_to_le16(8);
4796 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4797 nv->login_timeout = __constant_cpu_to_le16(0);
4798 nv->firmware_options_1 =
4799 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4800 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4801 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4802 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4803 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4804 nv->efi_parameters = __constant_cpu_to_le32(0);
4805 nv->reset_delay = 5;
4806 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4807 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4808 nv->link_down_timeout = __constant_cpu_to_le16(30);
4809
4810 rval = 1;
0107109e
AV		 4811 }
4812
2d70c103
NB		 4813 if (!qla_ini_mode_enabled(vha)) {
4814 /* Don't enable full login after initial LIP */
4815 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4816 /* Don't enable LIP full login for initiator */
4817 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4818 }
4819
4820 qlt_24xx_config_nvram_stage1(vha, nv);
4821
0107109e 4822 /* Reset Initialization control block */
e315cd28 4823 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4824
4825 /* Copy 1st segment. */
4826 dptr1 = (uint8_t *)icb;
4827 dptr2 = (uint8_t *)&nv->version;
4828 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4829 while (cnt--)
4830 *dptr1++ = *dptr2++;
4831
4832 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4833 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4834
4835 /* Copy 2nd segment. */
4836 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4837 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4838 cnt = (uint8_t *)&icb->reserved_3 -
4839 (uint8_t *)&icb->interrupt_delay_timer;
4840 while (cnt--)
4841 *dptr1++ = *dptr2++;
4842
4843 /*
4844 * Setup driver NVRAM options.
4845 */
e315cd28 4846 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4847 "QLA2462");
0107109e 4848
2d70c103
NB		 4849 qlt_24xx_config_nvram_stage2(vha, icb);
4850
5341e868 4851 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4852 /* Use alternate WWN? */
5341e868
AV		 4853 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4854 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4855 }
4856
0107109e 4857 /* Prepare nodename */
fd0e7e4d 4858 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4859 /*
4860 * Firmware will apply the following mask if the nodename was
4861 * not provided.
4862 */
4863 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4864 icb->node_name[0] &= 0xF0;
4865 }
4866
4867 /* Set host adapter parameters. */
4868 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4869 ha->flags.enable_lip_reset = 0;
4870 ha->flags.enable_lip_full_login =
4871 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4872 ha->flags.enable_target_reset =
4873 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4874 ha->flags.enable_led_scheme = 0;
d4c760c2 4875 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4876
fd0e7e4d
AV		 4877 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4878 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4879
4880 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4881 sizeof(ha->fw_seriallink_options24));
4882
4883 /* save HBA serial number */
4884 ha->serial0 = icb->port_name[5];
4885 ha->serial1 = icb->port_name[6];
4886 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4887 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4888 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4889
bc8fb3cb 4890 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4891
0107109e
AV		 4892 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4893
4894 /* Set minimum login_timeout to 4 seconds. */
4895 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4896 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4897 if (le16_to_cpu(nv->login_timeout) < 4)
4898 nv->login_timeout = __constant_cpu_to_le16(4);
4899 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4900 icb->login_timeout = nv->login_timeout;
0107109e 4901
00a537b8
AV		 4902 /* Set minimum RATOV to 100 tenths of a second. */
4903 ha->r_a_tov = 100;
0107109e
AV		 4904
4905 ha->loop_reset_delay = nv->reset_delay;
4906
4907 /* Link Down Timeout = 0:
4908 *
4909 * When Port Down timer expires we will start returning
4910 * I/O's to OS with "DID_NO_CONNECT".
4911 *
4912 * Link Down Timeout != 0:
4913 *
4914 * The driver waits for the link to come up after link down
4915 * before returning I/Os to OS with "DID_NO_CONNECT".
4916 */
4917 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4918 ha->loop_down_abort_time =
4919 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4920 } else {
4921 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4922 ha->loop_down_abort_time =
4923 (LOOP_DOWN_TIME - ha->link_down_timeout);
4924 }
4925
4926 /* Need enough time to try and get the port back. */
4927 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4928 if (qlport_down_retry)
4929 ha->port_down_retry_count = qlport_down_retry;
4930
4931 /* Set login_retry_count */
4932 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4933 if (ha->port_down_retry_count ==
4934 le16_to_cpu(nv->port_down_retry_count) &&
4935 ha->port_down_retry_count > 3)
4936 ha->login_retry_count = ha->port_down_retry_count;
4937 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4938 ha->login_retry_count = ha->port_down_retry_count;
4939 if (ql2xloginretrycount)
4940 ha->login_retry_count = ql2xloginretrycount;
4941
4fdfefe5 4942 /* Enable ZIO. */
e315cd28 4943 if (!vha->flags.init_done) {
4fdfefe5
AV		 4944 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4945 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4946 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4947 le16_to_cpu(icb->interrupt_delay_timer): 2;
4948 }
4949 icb->firmware_options_2 &= __constant_cpu_to_le32(
4950 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 4951 vha->flags.process_response_queue = 0;
4fdfefe5 4952 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4953 ha->zio_mode = QLA_ZIO_MODE_6;
4954
7c3df132 4955 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 4956 "ZIO mode %d enabled; timer delay (%d us).\n",
4957 ha->zio_mode, ha->zio_timer * 100);
4958
4959 icb->firmware_options_2 |= cpu_to_le32(
4960 (uint32_t)ha->zio_mode);
4961 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 4962 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 4963 }
4964
4e08df3f 4965 if (rval) {
7c3df132
SK		 4966 ql_log(ql_log_warn, vha, 0x0070,
4967 "NVRAM configuration failed.\n");
4e08df3f
DM		 4968 }
4969 return (rval);
0107109e
AV		 4970}
4971
413975a0 4972static int
cbc8eb67
AV		 4973qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
4974 uint32_t faddr)
d1c61909 4975{
73208dfd 4976 int rval = QLA_SUCCESS;
d1c61909 4977 int segments, fragment;
d1c61909
AV		 4978 uint32_t *dcode, dlen;
4979 uint32_t risc_addr;
4980 uint32_t risc_size;
4981 uint32_t i;
e315cd28 4982 struct qla_hw_data *ha = vha->hw;
73208dfd 4983 struct req_que *req = ha->req_q_map[0];
eaac30be 4984
7c3df132 4985 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 4986 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 4987
d1c61909
AV		 4988 rval = QLA_SUCCESS;
4989
4990 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 4991 dcode = (uint32_t *)req->ring;
d1c61909
AV		 4992 *srisc_addr = 0;
4993
4994 /* Validate firmware image by checking version. */
e315cd28 4995 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 4996 for (i = 0; i < 4; i++)
4997 dcode[i] = be32_to_cpu(dcode[i]);
4998 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
4999 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5000 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5001 dcode[3] == 0)) {
7c3df132
SK		 5002 ql_log(ql_log_fatal, vha, 0x008c,
5003 "Unable to verify the integrity of flash firmware "
5004 "image.\n");
5005 ql_log(ql_log_fatal, vha, 0x008d,
5006 "Firmware data: %08x %08x %08x %08x.\n",
5007 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5008
5009 return QLA_FUNCTION_FAILED;
5010 }
5011
5012 while (segments && rval == QLA_SUCCESS) {
5013 /* Read segment's load information. */
e315cd28 5014 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5015
5016 risc_addr = be32_to_cpu(dcode[2]);
5017 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5018 risc_size = be32_to_cpu(dcode[3]);
5019
5020 fragment = 0;
5021 while (risc_size > 0 && rval == QLA_SUCCESS) {
5022 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5023 if (dlen > risc_size)
5024 dlen = risc_size;
5025
7c3df132
SK		 5026 ql_dbg(ql_dbg_init, vha, 0x008e,
5027 "Loading risc segment@ risc addr %x "
5028 "number of dwords 0x%x offset 0x%x.\n",
5029 risc_addr, dlen, faddr);
d1c61909 5030
e315cd28 5031 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5032 for (i = 0; i < dlen; i++)
5033 dcode[i] = swab32(dcode[i]);
5034
73208dfd 5035 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5036 dlen);
5037 if (rval) {
7c3df132
SK		 5038 ql_log(ql_log_fatal, vha, 0x008f,
5039 "Failed to load segment %d of firmware.\n",
5040 fragment);
d1c61909
AV		 5041 break;
5042 }
5043
5044 faddr += dlen;
5045 risc_addr += dlen;
5046 risc_size -= dlen;
5047 fragment++;
5048 }
5049
5050 /* Next segment. */
5051 segments--;
5052 }
5053
5054 return rval;
5055}
5056
e9454a88 5057#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5058
0107109e 5059int
e315cd28 5060qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5061{
5062 int rval;
5063 int i, fragment;
5064 uint16_t *wcode, *fwcode;
5065 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5066 struct fw_blob *blob;
e315cd28 5067 struct qla_hw_data *ha = vha->hw;
73208dfd 5068 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5069
5070 /* Load firmware blob. */
e315cd28 5071 blob = qla2x00_request_firmware(vha);
5433383e 5072 if (!blob) {
7c3df132
SK		 5073 ql_log(ql_log_info, vha, 0x0083,
5074 "Fimware image unavailable.\n");
5075 ql_log(ql_log_info, vha, 0x0084,
5076 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5077 return QLA_FUNCTION_FAILED;
5078 }
5079
5080 rval = QLA_SUCCESS;
5081
73208dfd 5082 wcode = (uint16_t *)req->ring;
5433383e
AV		 5083 *srisc_addr = 0;
5084 fwcode = (uint16_t *)blob->fw->data;
5085 fwclen = 0;
5086
5087 /* Validate firmware image by checking version. */
5088 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5089 ql_log(ql_log_fatal, vha, 0x0085,
5090 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5091 blob->fw->size);
5092 goto fail_fw_integrity;
5093 }
5094 for (i = 0; i < 4; i++)
5095 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5096 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5097 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5098 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5099 ql_log(ql_log_fatal, vha, 0x0086,
5100 "Unable to verify integrity of firmware image.\n");
5101 ql_log(ql_log_fatal, vha, 0x0087,
5102 "Firmware data: %04x %04x %04x %04x.\n",
5103 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5104 goto fail_fw_integrity;
5105 }
5106
5107 seg = blob->segs;
5108 while (*seg && rval == QLA_SUCCESS) {
5109 risc_addr = *seg;
5110 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5111 risc_size = be16_to_cpu(fwcode[3]);
5112
5113 /* Validate firmware image size. */
5114 fwclen += risc_size * sizeof(uint16_t);
5115 if (blob->fw->size < fwclen) {
7c3df132 5116 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5117 "Unable to verify integrity of firmware image "
7c3df132 5118 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5119 goto fail_fw_integrity;
5120 }
5121
5122 fragment = 0;
5123 while (risc_size > 0 && rval == QLA_SUCCESS) {
5124 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5125 if (wlen > risc_size)
5126 wlen = risc_size;
7c3df132
SK		 5127 ql_dbg(ql_dbg_init, vha, 0x0089,
5128 "Loading risc segment@ risc addr %x number of "
5129 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5130
5131 for (i = 0; i < wlen; i++)
5132 wcode[i] = swab16(fwcode[i]);
5133
73208dfd 5134 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5135 wlen);
5136 if (rval) {
7c3df132
SK		 5137 ql_log(ql_log_fatal, vha, 0x008a,
5138 "Failed to load segment %d of firmware.\n",
5139 fragment);
5433383e
AV		 5140 break;
5141 }
5142
5143 fwcode += wlen;
5144 risc_addr += wlen;
5145 risc_size -= wlen;
5146 fragment++;
5147 }
5148
5149 /* Next segment. */
5150 seg++;
5151 }
5152 return rval;
5153
5154fail_fw_integrity:
5155 return QLA_FUNCTION_FAILED;
5156}
5157
eaac30be
AV		 5158static int
5159qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5160{
5161 int rval;
5162 int segments, fragment;
5163 uint32_t *dcode, dlen;
5164 uint32_t risc_addr;
5165 uint32_t risc_size;
5166 uint32_t i;
5433383e 5167 struct fw_blob *blob;
0107109e 5168 uint32_t *fwcode, fwclen;
e315cd28 5169 struct qla_hw_data *ha = vha->hw;
73208dfd 5170 struct req_que *req = ha->req_q_map[0];
0107109e 5171
5433383e 5172 /* Load firmware blob. */
e315cd28 5173 blob = qla2x00_request_firmware(vha);
5433383e 5174 if (!blob) {
7c3df132
SK		 5175 ql_log(ql_log_warn, vha, 0x0090,
5176 "Fimware image unavailable.\n");
5177 ql_log(ql_log_warn, vha, 0x0091,
5178 "Firmware images can be retrieved from: "
5179 QLA_FW_URL ".\n");
d1c61909 5180
eaac30be 5181 return QLA_FUNCTION_FAILED;
0107109e
AV		 5182 }
5183
cfb0919c
CD		 5184 ql_dbg(ql_dbg_init, vha, 0x0092,
5185 "FW: Loading via request-firmware.\n");
eaac30be 5186
0107109e
AV		 5187 rval = QLA_SUCCESS;
5188
5189 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5190 dcode = (uint32_t *)req->ring;
0107109e 5191 *srisc_addr = 0;
5433383e 5192 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5193 fwclen = 0;
5194
5195 /* Validate firmware image by checking version. */
5433383e 5196 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5197 ql_log(ql_log_fatal, vha, 0x0093,
5198 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5199 blob->fw->size);
0107109e
AV		 5200 goto fail_fw_integrity;
5201 }
5202 for (i = 0; i < 4; i++)
5203 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5204 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5205 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5206 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5207 dcode[3] == 0)) {
7c3df132
SK		 5208 ql_log(ql_log_fatal, vha, 0x0094,
5209 "Unable to verify integrity of firmware image (%Zd).\n",
5210 blob->fw->size);
5211 ql_log(ql_log_fatal, vha, 0x0095,
5212 "Firmware data: %08x %08x %08x %08x.\n",
5213 dcode[0], dcode[1], dcode[2], dcode[3]);
0107109e
AV		 5214 goto fail_fw_integrity;
5215 }
5216
5217 while (segments && rval == QLA_SUCCESS) {
5218 risc_addr = be32_to_cpu(fwcode[2]);
5219 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5220 risc_size = be32_to_cpu(fwcode[3]);
5221
5222 /* Validate firmware image size. */
5223 fwclen += risc_size * sizeof(uint32_t);
5433383e 5224 if (blob->fw->size < fwclen) {
7c3df132 5225 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5226 "Unable to verify integrity of firmware image "
7c3df132 5227 "(%Zd).\n", blob->fw->size);
5433383e 5228
0107109e
AV		 5229 goto fail_fw_integrity;
5230 }
5231
5232 fragment = 0;
5233 while (risc_size > 0 && rval == QLA_SUCCESS) {
5234 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5235 if (dlen > risc_size)
5236 dlen = risc_size;
5237
7c3df132
SK		 5238 ql_dbg(ql_dbg_init, vha, 0x0097,
5239 "Loading risc segment@ risc addr %x "
5240 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5241
5242 for (i = 0; i < dlen; i++)
5243 dcode[i] = swab32(fwcode[i]);
5244
73208dfd 5245 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5246 dlen);
0107109e 5247 if (rval) {
7c3df132
SK		 5248 ql_log(ql_log_fatal, vha, 0x0098,
5249 "Failed to load segment %d of firmware.\n",
5250 fragment);
0107109e
AV		 5251 break;
5252 }
5253
5254 fwcode += dlen;
5255 risc_addr += dlen;
5256 risc_size -= dlen;
5257 fragment++;
5258 }
5259
5260 /* Next segment. */
5261 segments--;
5262 }
0107109e
AV		 5263 return rval;
5264
5265fail_fw_integrity:
0107109e 5266 return QLA_FUNCTION_FAILED;
0107109e 5267}
18c6c127 5268
eaac30be
AV		 5269int
5270qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5271{
5272 int rval;
5273
e337d907
AV		 5274 if (ql2xfwloadbin == 1)
5275 return qla81xx_load_risc(vha, srisc_addr);
5276
eaac30be
AV		 5277 /*
5278 * FW Load priority:
5279 * 1) Firmware via request-firmware interface (.bin file).
5280 * 2) Firmware residing in flash.
5281 */
5282 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5283 if (rval == QLA_SUCCESS)
5284 return rval;
5285
cbc8eb67
AV		 5286 return qla24xx_load_risc_flash(vha, srisc_addr,
5287 vha->hw->flt_region_fw);
eaac30be
AV		 5288}
5289
5290int
5291qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5292{
5293 int rval;
cbc8eb67 5294 struct qla_hw_data *ha = vha->hw;
eaac30be 5295
e337d907 5296 if (ql2xfwloadbin == 2)
cbc8eb67 5297 goto try_blob_fw;
e337d907 5298
eaac30be
AV		 5299 /*
5300 * FW Load priority:
5301 * 1) Firmware residing in flash.
5302 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5303 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5304 */
cbc8eb67 5305 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5306 if (rval == QLA_SUCCESS)
5307 return rval;
5308
cbc8eb67
AV		 5309try_blob_fw:
5310 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5311 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5312 return rval;
5313
7c3df132
SK		 5314 ql_log(ql_log_info, vha, 0x0099,
5315 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5316 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5317 if (rval != QLA_SUCCESS)
5318 return rval;
5319
7c3df132 5320 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5321 ha->flags.running_gold_fw = 1;
cbc8eb67 5322 return rval;
eaac30be
AV		 5323}
5324
18c6c127 5325void
e315cd28 5326qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5327{
5328 int ret, retries;
e315cd28 5329 struct qla_hw_data *ha = vha->hw;
18c6c127 5330
85880801
AV		 5331 if (ha->flags.pci_channel_io_perm_failure)
5332 return;
e428924c 5333 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5334 return;
75edf81d
AV		 5335 if (!ha->fw_major_version)
5336 return;
18c6c127 5337
e315cd28 5338 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5339 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5340 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5341 ha->isp_ops->reset_chip(vha);
5342 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5343 continue;
e315cd28 5344 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5345 continue;
7c3df132
SK		 5346 ql_log(ql_log_info, vha, 0x8015,
5347 "Attempting retry of stop-firmware command.\n");
e315cd28 5348 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5349 }
5350}
2c3dfe3f
SJ		 5351
5352int
e315cd28 5353qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5354{
5355 int rval = QLA_SUCCESS;
0b91d116 5356 int rval2;
2c3dfe3f 5357 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5358 struct qla_hw_data *ha = vha->hw;
5359 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5360 struct req_que *req;
5361 struct rsp_que *rsp;
2c3dfe3f 5362
e315cd28 5363 if (!vha->vp_idx)
2c3dfe3f
SJ		 5364 return -EINVAL;
5365
e315cd28 5366 rval = qla2x00_fw_ready(base_vha);
7163ea81 5367 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5368 req = ha->req_q_map[0];
5369 else
5370 req = vha->req;
5371 rsp = req->rsp;
5372
2c3dfe3f 5373 if (rval == QLA_SUCCESS) {
e315cd28 5374 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5375 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5376 }
5377
e315cd28 5378 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5379
5380 /* Login to SNS first */
0b91d116
CD		 5381 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5382 BIT_1);
5383 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5384 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5385 ql_dbg(ql_dbg_init, vha, 0x0120,
5386 "Failed SNS login: loop_id=%x, rval2=%d\n",
5387 NPH_SNS, rval2);
5388 else
5389 ql_dbg(ql_dbg_init, vha, 0x0103,
5390 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5391 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5392 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5393 return (QLA_FUNCTION_FAILED);
5394 }
5395
e315cd28
AC		 5396 atomic_set(&vha->loop_down_timer, 0);
5397 atomic_set(&vha->loop_state, LOOP_UP);
5398 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5399 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5400 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5401
5402 return rval;
5403}
4d4df193
HK		 5404
5405/* 84XX Support **************************************************************/
5406
5407static LIST_HEAD(qla_cs84xx_list);
5408static DEFINE_MUTEX(qla_cs84xx_mutex);
5409
5410static struct qla_chip_state_84xx *
e315cd28 5411qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5412{
5413 struct qla_chip_state_84xx *cs84xx;
e315cd28 5414 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5415
5416 mutex_lock(&qla_cs84xx_mutex);
5417
5418 /* Find any shared 84xx chip. */
5419 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5420 if (cs84xx->bus == ha->pdev->bus) {
5421 kref_get(&cs84xx->kref);
5422 goto done;
5423 }
5424 }
5425
5426 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5427 if (!cs84xx)
5428 goto done;
5429
5430 kref_init(&cs84xx->kref);
5431 spin_lock_init(&cs84xx->access_lock);
5432 mutex_init(&cs84xx->fw_update_mutex);
5433 cs84xx->bus = ha->pdev->bus;
5434
5435 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5436done:
5437 mutex_unlock(&qla_cs84xx_mutex);
5438 return cs84xx;
5439}
5440
5441static void
5442__qla84xx_chip_release(struct kref *kref)
5443{
5444 struct qla_chip_state_84xx *cs84xx =
5445 container_of(kref, struct qla_chip_state_84xx, kref);
5446
5447 mutex_lock(&qla_cs84xx_mutex);
5448 list_del(&cs84xx->list);
5449 mutex_unlock(&qla_cs84xx_mutex);
5450 kfree(cs84xx);
5451}
5452
5453void
e315cd28 5454qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5455{
e315cd28 5456 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5457 if (ha->cs84xx)
5458 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5459}
5460
5461static int
e315cd28 5462qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5463{
5464 int rval;
5465 uint16_t status[2];
e315cd28 5466 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5467
5468 mutex_lock(&ha->cs84xx->fw_update_mutex);
5469
e315cd28 5470 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5471
5472 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5473
5474 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5475 QLA_SUCCESS;
5476}
3a03eb79
AV		 5477
5478/* 81XX Support **************************************************************/
5479
5480int
5481qla81xx_nvram_config(scsi_qla_host_t *vha)
5482{
5483 int rval;
5484 struct init_cb_81xx *icb;
5485 struct nvram_81xx *nv;
5486 uint32_t *dptr;
5487 uint8_t *dptr1, *dptr2;
5488 uint32_t chksum;
5489 uint16_t cnt;
5490 struct qla_hw_data *ha = vha->hw;
5491
5492 rval = QLA_SUCCESS;
5493 icb = (struct init_cb_81xx *)ha->init_cb;
5494 nv = ha->nvram;
5495
5496 /* Determine NVRAM starting address. */
5497 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5498 ha->vpd_size = FA_NVRAM_VPD_SIZE;
3a03eb79
AV		 5499
5500 /* Get VPD data into cache */
5501 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5502 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5503 ha->vpd_size);
3a03eb79
AV		 5504
5505 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5506 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5507 ha->nvram_size);
3d79038f 5508 dptr = (uint32_t *)nv;
3a03eb79
AV		 5509 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5510 chksum += le32_to_cpu(*dptr++);
5511
7c3df132
SK		 5512 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5513 "Contents of NVRAM:\n");
5514 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5515 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5516
5517 /* Bad NVRAM data, set defaults parameters. */
5518 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5519 || nv->id[3] != ' ' ||
5520 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5521 /* Reset NVRAM data. */
7c3df132 5522 ql_log(ql_log_info, vha, 0x0073,
9e336520 5523 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5524 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5525 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5526 ql_log(ql_log_info, vha, 0x0074,
5527 "Falling back to functioning (yet invalid -- WWPN) "
5528 "defaults.\n");
3a03eb79
AV		 5529
5530 /*
5531 * Set default initialization control block.
5532 */
5533 memset(nv, 0, ha->nvram_size);
5534 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5535 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5536 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5537 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5538 nv->exchange_count = __constant_cpu_to_le16(0);
5539 nv->port_name[0] = 0x21;
e5b68a61 5540 nv->port_name[1] = 0x00 + ha->port_no;
3a03eb79
AV		 5541 nv->port_name[2] = 0x00;
5542 nv->port_name[3] = 0xe0;
5543 nv->port_name[4] = 0x8b;
5544 nv->port_name[5] = 0x1c;
5545 nv->port_name[6] = 0x55;
5546 nv->port_name[7] = 0x86;
5547 nv->node_name[0] = 0x20;
5548 nv->node_name[1] = 0x00;
5549 nv->node_name[2] = 0x00;
5550 nv->node_name[3] = 0xe0;
5551 nv->node_name[4] = 0x8b;
5552 nv->node_name[5] = 0x1c;
5553 nv->node_name[6] = 0x55;
5554 nv->node_name[7] = 0x86;
5555 nv->login_retry_count = __constant_cpu_to_le16(8);
5556 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5557 nv->login_timeout = __constant_cpu_to_le16(0);
5558 nv->firmware_options_1 =
5559 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5560 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5561 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5562 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5563 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5564 nv->efi_parameters = __constant_cpu_to_le32(0);
5565 nv->reset_delay = 5;
5566 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5567 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5568 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5569 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5570 nv->enode_mac[1] = 0xC0;
5571 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5572 nv->enode_mac[3] = 0x04;
5573 nv->enode_mac[4] = 0x05;
e5b68a61 5574 nv->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5575
5576 rval = 1;
5577 }
5578
9e522cd8
AE		 5579 if (IS_T10_PI_CAPABLE(ha))
5580 nv->frame_payload_size &= ~7;
5581
aa230bc5
AE		 5582 qlt_81xx_config_nvram_stage1(vha, nv);
5583
3a03eb79 5584 /* Reset Initialization control block */
773120e4 5585 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5586
5587 /* Copy 1st segment. */
5588 dptr1 = (uint8_t *)icb;
5589 dptr2 = (uint8_t *)&nv->version;
5590 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5591 while (cnt--)
5592 *dptr1++ = *dptr2++;
5593
5594 icb->login_retry_count = nv->login_retry_count;
5595
5596 /* Copy 2nd segment. */
5597 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5598 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5599 cnt = (uint8_t *)&icb->reserved_5 -
5600 (uint8_t *)&icb->interrupt_delay_timer;
5601 while (cnt--)
5602 *dptr1++ = *dptr2++;
5603
5604 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5605 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5606 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5607 icb->enode_mac[0] = 0x00;
5608 icb->enode_mac[1] = 0xC0;
5609 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5610 icb->enode_mac[3] = 0x04;
5611 icb->enode_mac[4] = 0x05;
e5b68a61 5612 icb->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5613 }
5614
b64b0e8f
AV		 5615 /* Use extended-initialization control block. */
5616 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5617
3a03eb79
AV		 5618 /*
5619 * Setup driver NVRAM options.
5620 */
5621 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5622 "QLE8XXX");
3a03eb79 5623
aa230bc5
AE		 5624 qlt_81xx_config_nvram_stage2(vha, icb);
5625
3a03eb79
AV		 5626 /* Use alternate WWN? */
5627 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5628 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5629 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5630 }
5631
5632 /* Prepare nodename */
5633 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5634 /*
5635 * Firmware will apply the following mask if the nodename was
5636 * not provided.
5637 */
5638 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5639 icb->node_name[0] &= 0xF0;
5640 }
5641
5642 /* Set host adapter parameters. */
5643 ha->flags.disable_risc_code_load = 0;
5644 ha->flags.enable_lip_reset = 0;
5645 ha->flags.enable_lip_full_login =
5646 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5647 ha->flags.enable_target_reset =
5648 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5649 ha->flags.enable_led_scheme = 0;
5650 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5651
5652 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5653 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5654
5655 /* save HBA serial number */
5656 ha->serial0 = icb->port_name[5];
5657 ha->serial1 = icb->port_name[6];
5658 ha->serial2 = icb->port_name[7];
5659 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5660 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5661
5662 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5663
5664 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5665
5666 /* Set minimum login_timeout to 4 seconds. */
5667 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5668 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5669 if (le16_to_cpu(nv->login_timeout) < 4)
5670 nv->login_timeout = __constant_cpu_to_le16(4);
5671 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5672 icb->login_timeout = nv->login_timeout;
5673
5674 /* Set minimum RATOV to 100 tenths of a second. */
5675 ha->r_a_tov = 100;
5676
5677 ha->loop_reset_delay = nv->reset_delay;
5678
5679 /* Link Down Timeout = 0:
5680 *
5681 * When Port Down timer expires we will start returning
5682 * I/O's to OS with "DID_NO_CONNECT".
5683 *
5684 * Link Down Timeout != 0:
5685 *
5686 * The driver waits for the link to come up after link down
5687 * before returning I/Os to OS with "DID_NO_CONNECT".
5688 */
5689 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5690 ha->loop_down_abort_time =
5691 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5692 } else {
5693 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5694 ha->loop_down_abort_time =
5695 (LOOP_DOWN_TIME - ha->link_down_timeout);
5696 }
5697
5698 /* Need enough time to try and get the port back. */
5699 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5700 if (qlport_down_retry)
5701 ha->port_down_retry_count = qlport_down_retry;
5702
5703 /* Set login_retry_count */
5704 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5705 if (ha->port_down_retry_count ==
5706 le16_to_cpu(nv->port_down_retry_count) &&
5707 ha->port_down_retry_count > 3)
5708 ha->login_retry_count = ha->port_down_retry_count;
5709 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5710 ha->login_retry_count = ha->port_down_retry_count;
5711 if (ql2xloginretrycount)
5712 ha->login_retry_count = ql2xloginretrycount;
5713
6246b8a1
GM		 5714 /* if not running MSI-X we need handshaking on interrupts */
5715 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5716 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5717
3a03eb79
AV		 5718 /* Enable ZIO. */
5719 if (!vha->flags.init_done) {
5720 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5721 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5722 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5723 le16_to_cpu(icb->interrupt_delay_timer): 2;
5724 }
5725 icb->firmware_options_2 &= __constant_cpu_to_le32(
5726 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5727 vha->flags.process_response_queue = 0;
5728 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5729 ha->zio_mode = QLA_ZIO_MODE_6;
5730
7c3df132 5731 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 5732 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 5733 ha->zio_mode,
5734 ha->zio_timer * 100);
3a03eb79
AV		 5735
5736 icb->firmware_options_2 |= cpu_to_le32(
5737 (uint32_t)ha->zio_mode);
5738 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5739 vha->flags.process_response_queue = 1;
5740 }
5741
5742 if (rval) {
7c3df132
SK		 5743 ql_log(ql_log_warn, vha, 0x0076,
5744 "NVRAM configuration failed.\n");
3a03eb79
AV		 5745 }
5746 return (rval);
5747}
5748
a9083016
GM		 5749int
5750qla82xx_restart_isp(scsi_qla_host_t *vha)
5751{
5752 int status, rval;
5753 uint32_t wait_time;
5754 struct qla_hw_data *ha = vha->hw;
5755 struct req_que *req = ha->req_q_map[0];
5756 struct rsp_que *rsp = ha->rsp_q_map[0];
5757 struct scsi_qla_host *vp;
feafb7b1 5758 unsigned long flags;
a9083016
GM		 5759
5760 status = qla2x00_init_rings(vha);
5761 if (!status) {
5762 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5763 ha->flags.chip_reset_done = 1;
5764
5765 status = qla2x00_fw_ready(vha);
5766 if (!status) {
7c3df132
SK		 5767 ql_log(ql_log_info, vha, 0x803c,
5768 "Start configure loop, status =%d.\n", status);
a9083016
GM		 5769
5770 /* Issue a marker after FW becomes ready. */
5771 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5772
5773 vha->flags.online = 1;
5774 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5775 wait_time = 256;
5776 do {
5777 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5778 qla2x00_configure_loop(vha);
5779 wait_time--;
5780 } while (!atomic_read(&vha->loop_down_timer) &&
5781 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5782 wait_time &&
5783 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5784 }
5785
5786 /* if no cable then assume it's good */
5787 if ((vha->device_flags & DFLG_NO_CABLE))
5788 status = 0;
5789
cfb0919c 5790 ql_log(ql_log_info, vha, 0x8000,
7c3df132 5791 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 5792 }
5793
5794 if (!status) {
5795 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5796
5797 if (!atomic_read(&vha->loop_down_timer)) {
5798 /*
5799 * Issue marker command only when we are going
5800 * to start the I/O .
5801 */
5802 vha->marker_needed = 1;
5803 }
5804
5805 vha->flags.online = 1;
5806
5807 ha->isp_ops->enable_intrs(ha);
5808
5809 ha->isp_abort_cnt = 0;
5810 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5811
53296788 5812 /* Update the firmware version */
3173167f 5813 status = qla82xx_check_md_needed(vha);
53296788 5814
a9083016
GM		 5815 if (ha->fce) {
5816 ha->flags.fce_enabled = 1;
5817 memset(ha->fce, 0,
5818 fce_calc_size(ha->fce_bufs));
5819 rval = qla2x00_enable_fce_trace(vha,
5820 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5821 &ha->fce_bufs);
5822 if (rval) {
cfb0919c 5823 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 5824 "Unable to reinitialize FCE (%d).\n",
5825 rval);
a9083016
GM		 5826 ha->flags.fce_enabled = 0;
5827 }
5828 }
5829
5830 if (ha->eft) {
5831 memset(ha->eft, 0, EFT_SIZE);
5832 rval = qla2x00_enable_eft_trace(vha,
5833 ha->eft_dma, EFT_NUM_BUFFERS);
5834 if (rval) {
cfb0919c 5835 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 5836 "Unable to reinitialize EFT (%d).\n",
5837 rval);
a9083016
GM		 5838 }
5839 }
a9083016
GM		 5840 }
5841
5842 if (!status) {
cfb0919c 5843 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 5844 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 5845
5846 spin_lock_irqsave(&ha->vport_slock, flags);
5847 list_for_each_entry(vp, &ha->vp_list, list) {
5848 if (vp->vp_idx) {
5849 atomic_inc(&vp->vref_count);
5850 spin_unlock_irqrestore(&ha->vport_slock, flags);
5851
a9083016 5852 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5853
5854 spin_lock_irqsave(&ha->vport_slock, flags);
5855 atomic_dec(&vp->vref_count);
5856 }
a9083016 5857 }
feafb7b1
AE		 5858 spin_unlock_irqrestore(&ha->vport_slock, flags);
5859
a9083016 5860 } else {
cfb0919c 5861 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 5862 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 5863 }
5864
5865 return status;
5866}
5867
3a03eb79 5868void
ae97c91e 5869qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 5870{
ae97c91e
AV		 5871 struct qla_hw_data *ha = vha->hw;
5872
5873 if (!ql2xetsenable)
5874 return;
5875
5876 /* Enable ETS Burst. */
5877 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5878 ha->fw_options[2] |= BIT_9;
5879 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 5880}
09ff701a
SR		 5881
5882/*
5883 * qla24xx_get_fcp_prio
5884 * Gets the fcp cmd priority value for the logged in port.
5885 * Looks for a match of the port descriptors within
5886 * each of the fcp prio config entries. If a match is found,
5887 * the tag (priority) value is returned.
5888 *
5889 * Input:
21090cbe 5890 * vha = scsi host structure pointer.
09ff701a
SR		 5891 * fcport = port structure pointer.
5892 *
5893 * Return:
6c452a45 5894 * non-zero (if found)
f28a0a96 5895 * -1 (if not found)
09ff701a
SR		 5896 *
5897 * Context:
5898 * Kernel context
5899 */
f28a0a96 5900static int
09ff701a
SR		 5901qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5902{
5903 int i, entries;
5904 uint8_t pid_match, wwn_match;
f28a0a96 5905 int priority;
09ff701a
SR		 5906 uint32_t pid1, pid2;
5907 uint64_t wwn1, wwn2;
5908 struct qla_fcp_prio_entry *pri_entry;
5909 struct qla_hw_data *ha = vha->hw;
5910
5911 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 5912 return -1;
09ff701a 5913
f28a0a96 5914 priority = -1;
09ff701a
SR		 5915 entries = ha->fcp_prio_cfg->num_entries;
5916 pri_entry = &ha->fcp_prio_cfg->entry[0];
5917
5918 for (i = 0; i < entries; i++) {
5919 pid_match = wwn_match = 0;
5920
5921 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5922 pri_entry++;
5923 continue;
5924 }
5925
5926 /* check source pid for a match */
5927 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5928 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5929 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5930 if (pid1 == INVALID_PORT_ID)
5931 pid_match++;
5932 else if (pid1 == pid2)
5933 pid_match++;
5934 }
5935
5936 /* check destination pid for a match */
5937 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5938 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
5939 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
5940 if (pid1 == INVALID_PORT_ID)
5941 pid_match++;
5942 else if (pid1 == pid2)
5943 pid_match++;
5944 }
5945
5946 /* check source WWN for a match */
5947 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
5948 wwn1 = wwn_to_u64(vha->port_name);
5949 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
5950 if (wwn2 == (uint64_t)-1)
5951 wwn_match++;
5952 else if (wwn1 == wwn2)
5953 wwn_match++;
5954 }
5955
5956 /* check destination WWN for a match */
5957 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
5958 wwn1 = wwn_to_u64(fcport->port_name);
5959 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
5960 if (wwn2 == (uint64_t)-1)
5961 wwn_match++;
5962 else if (wwn1 == wwn2)
5963 wwn_match++;
5964 }
5965
5966 if (pid_match == 2 || wwn_match == 2) {
5967 /* Found a matching entry */
5968 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
5969 priority = pri_entry->tag;
5970 break;
5971 }
5972
5973 pri_entry++;
5974 }
5975
5976 return priority;
5977}
5978
5979/*
5980 * qla24xx_update_fcport_fcp_prio
5981 * Activates fcp priority for the logged in fc port
5982 *
5983 * Input:
21090cbe 5984 * vha = scsi host structure pointer.
09ff701a
SR		 5985 * fcp = port structure pointer.
5986 *
5987 * Return:
5988 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5989 *
5990 * Context:
5991 * Kernel context.
5992 */
5993int
21090cbe 5994qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 5995{
5996 int ret;
f28a0a96 5997 int priority;
09ff701a
SR		 5998 uint16_t mb[5];
5999
21090cbe
MI		 6000 if (fcport->port_type != FCT_TARGET ||
6001 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6002 return QLA_FUNCTION_FAILED;
6003
21090cbe 6004 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6005 if (priority < 0)
6006 return QLA_FUNCTION_FAILED;
6007
a00f6296
SK		 6008 if (IS_QLA82XX(vha->hw)) {
6009 fcport->fcp_prio = priority & 0xf;
6010 return QLA_SUCCESS;
6011 }
6012
21090cbe 6013 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6014 if (ret == QLA_SUCCESS) {
6015 if (fcport->fcp_prio != priority)
6016 ql_dbg(ql_dbg_user, vha, 0x709e,
6017 "Updated FCP_CMND priority - value=%d loop_id=%d "
6018 "port_id=%02x%02x%02x.\n", priority,
6019 fcport->loop_id, fcport->d_id.b.domain,
6020 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6021 fcport->fcp_prio = priority & 0xf;
cfb0919c 6022 } else
7c3df132 6023 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6024 "Unable to update FCP_CMND priority - ret=0x%x for "
6025 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6026 fcport->d_id.b.domain, fcport->d_id.b.area,
6027 fcport->d_id.b.al_pa);
09ff701a
SR		 6028 return ret;
6029}
6030
6031/*
6032 * qla24xx_update_all_fcp_prio
6033 * Activates fcp priority for all the logged in ports
6034 *
6035 * Input:
6036 * ha = adapter block pointer.
6037 *
6038 * Return:
6039 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6040 *
6041 * Context:
6042 * Kernel context.
6043 */
6044int
6045qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6046{
6047 int ret;
6048 fc_port_t *fcport;
6049
6050 ret = QLA_FUNCTION_FAILED;
6051 /* We need to set priority for all logged in ports */
6052 list_for_each_entry(fcport, &vha->vp_fcports, list)
6053 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6054
6055 return ret;
6056}
Linux 6.x block layer and io_uring tree(s)