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scsi: qla2xxx: Turn off IOCB timeout timer on IOCB completion
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
a5d42f4c 39static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
726b8548
QT		 40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
a5d42f4c
DG		 42static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
43 struct event_arg *);
a4239945 44static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
4d4df193 45
ac280b67
AV		 46/* SRB Extensions ---------------------------------------------------------- */
47
9ba56b95 48void
8e5f4ba0 49qla2x00_sp_timeout(struct timer_list *t)
ac280b67 50{
8e5f4ba0 51 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
4916392b 52 struct srb_iocb *iocb;
ac280b67
AV		 53 struct req_que *req;
54 unsigned long flags;
55
f6145e86
QT		 56 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
57 req = sp->qpair->req;
ac280b67 58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
f6145e86 60 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
4916392b 61 iocb->timeout(sp);
ac280b67
AV		 62}
63
9ba56b95 64void
25ff6af1 65qla2x00_sp_free(void *ptr)
ac280b67 66{
25ff6af1 67 srb_t *sp = ptr;
9ba56b95 68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 69
4d97cc53 70 del_timer(&iocb->timer);
25ff6af1 71 qla2x00_rel_sp(sp);
ac280b67
AV		 72}
73
ac280b67
AV		 74/* Asynchronous Login/Logout Routines -------------------------------------- */
75
a9b6f722 76unsigned long
5b91490e
AV		 77qla2x00_get_async_timeout(struct scsi_qla_host *vha)
78{
79 unsigned long tmo;
80 struct qla_hw_data *ha = vha->hw;
81
82 /* Firmware should use switch negotiated r_a_tov for timeout. */
83 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 84 if (IS_QLAFX00(ha)) {
85 tmo = FX00_DEF_RATOV * 2;
86 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 87 /*
88 * Except for earlier ISPs where the timeout is seeded from the
89 * initialization control block.
90 */
91 tmo = ha->login_timeout;
92 }
93 return tmo;
94}
ac280b67 95
726b8548 96void
9ba56b95 97qla2x00_async_iocb_timeout(void *data)
ac280b67 98{
25ff6af1 99 srb_t *sp = data;
ac280b67 100 fc_port_t *fcport = sp->fcport;
726b8548 101 struct srb_iocb *lio = &sp->u.iocb_cmd;
f6145e86
QT		 102 int rc, h;
103 unsigned long flags;
ac280b67 104
5c25d451
QT		 105 if (fcport) {
106 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
107 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
108 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
109
6d674927 110 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
5c25d451
QT		 111 } else {
112 pr_info("Async-%s timeout - hdl=%x.\n",
113 sp->name, sp->handle);
114 }
726b8548
QT		 115
116 switch (sp->type) {
117 case SRB_LOGIN_CMD:
f6145e86
QT		 118 rc = qla24xx_async_abort_cmd(sp, false);
119 if (rc) {
120 /* Retry as needed. */
121 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
122 lio->u.logio.data[1] =
123 lio->u.logio.flags & SRB_LOGIN_RETRIED ?
124 QLA_LOGIO_LOGIN_RETRIED : 0;
125 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
126 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
127 h++) {
128 if (sp->qpair->req->outstanding_cmds[h] ==
129 sp) {
130 sp->qpair->req->outstanding_cmds[h] =
131 NULL;
132 break;
133 }
134 }
135 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
136 sp->done(sp, QLA_FUNCTION_TIMEOUT);
137 }
726b8548
QT		 138 break;
139 case SRB_LOGOUT_CMD:
726b8548
QT		 140 case SRB_CT_PTHRU_CMD:
141 case SRB_MB_IOCB:
142 case SRB_NACK_PLOGI:
143 case SRB_NACK_PRLI:
144 case SRB_NACK_LOGO:
2853192e 145 case SRB_CTRL_VP:
f6145e86
QT		 146 rc = qla24xx_async_abort_cmd(sp, false);
147 if (rc) {
148 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
149 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
150 h++) {
151 if (sp->qpair->req->outstanding_cmds[h] ==
152 sp) {
153 sp->qpair->req->outstanding_cmds[h] =
154 NULL;
155 break;
156 }
157 }
158 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
159 sp->done(sp, QLA_FUNCTION_TIMEOUT);
160 }
726b8548 161 break;
6ac52608 162 }
ac280b67
AV		 163}
164
99b0bec7 165static void
25ff6af1 166qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 167{
25ff6af1
JC		 168 srb_t *sp = ptr;
169 struct scsi_qla_host *vha = sp->vha;
9ba56b95 170 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 171 struct event_arg ea;
9ba56b95 172
83548fe2 173 ql_dbg(ql_dbg_disc, vha, 0x20dd,
25ff6af1 174 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548 175
6d674927
QT		 176 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
177
726b8548
QT		 178 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
179 memset(&ea, 0, sizeof(ea));
180 ea.event = FCME_PLOGI_DONE;
181 ea.fcport = sp->fcport;
182 ea.data[0] = lio->u.logio.data[0];
183 ea.data[1] = lio->u.logio.data[1];
184 ea.iop[0] = lio->u.logio.iop[0];
185 ea.iop[1] = lio->u.logio.iop[1];
186 ea.sp = sp;
187 qla2x00_fcport_event_handler(vha, &ea);
188 }
9ba56b95 189
25ff6af1 190 sp->free(sp);
99b0bec7
AV		 191}
192
48acad09
QT		 193static inline bool
194fcport_is_smaller(fc_port_t *fcport)
195{
196 if (wwn_to_u64(fcport->port_name) <
197 wwn_to_u64(fcport->vha->port_name))
198 return true;
199 else
200 return false;
201}
202
203static inline bool
204fcport_is_bigger(fc_port_t *fcport)
205{
206 return !fcport_is_smaller(fcport);
207}
208
ac280b67
AV		 209int
210qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
211 uint16_t *data)
212{
ac280b67 213 srb_t *sp;
4916392b 214 struct srb_iocb *lio;
726b8548
QT		 215 int rval = QLA_FUNCTION_FAILED;
216
217 if (!vha->flags.online)
218 goto done;
219
9ba56b95 220 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 221 if (!sp)
222 goto done;
223
726b8548
QT		 224 fcport->flags |= FCF_ASYNC_SENT;
225 fcport->logout_completed = 0;
226
a4239945 227 fcport->disc_state = DSC_LOGIN_PEND;
9ba56b95
GM		 228 sp->type = SRB_LOGIN_CMD;
229 sp->name = "login";
a4239945
QT		 230 sp->gen1 = fcport->rscn_gen;
231 sp->gen2 = fcport->login_gen;
9ba56b95
GM		 232
233 lio = &sp->u.iocb_cmd;
3822263e 234 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 235 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
236
9ba56b95 237 sp->done = qla2x00_async_login_sp_done;
48acad09
QT		 238 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport)) {
239 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY;
240 } else {
241 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
a5d42f4c 242
48acad09
QT		 243 if (fcport->fc4f_nvme)
244 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
245
48acad09 246 }
a5d42f4c 247
ac280b67 248 rval = qla2x00_start_sp(sp);
080c9517 249 if (rval != QLA_SUCCESS) {
080c9517
CD		 250 fcport->flags |= FCF_LOGIN_NEEDED;
251 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 252 goto done_free_sp;
080c9517 253 }
ac280b67 254
7c3df132 255 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 256 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
257 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 258 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
259 fcport->login_retry);
ac280b67
AV		 260 return rval;
261
262done_free_sp:
25ff6af1 263 sp->free(sp);
726b8548 264 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 265done:
fa83e658 266 fcport->flags &= ~FCF_ASYNC_ACTIVE;
ac280b67
AV		 267 return rval;
268}
269
99b0bec7 270static void
25ff6af1 271qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 272{
25ff6af1 273 srb_t *sp = ptr;
9ba56b95 274
6d674927 275 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
eaf75d18
QT		 276 sp->fcport->login_gen++;
277 qlt_logo_completion_handler(sp->fcport, res);
25ff6af1 278 sp->free(sp);
99b0bec7
AV		 279}
280
ac280b67
AV		 281int
282qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
283{
ac280b67 284 srb_t *sp;
4916392b 285 struct srb_iocb *lio;
3dbec59b
QT		 286 int rval = QLA_FUNCTION_FAILED;
287
288 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
289 return rval;
ac280b67 290
726b8548 291 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 292 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 293 if (!sp)
294 goto done;
295
9ba56b95
GM		 296 sp->type = SRB_LOGOUT_CMD;
297 sp->name = "logout";
9ba56b95
GM		 298
299 lio = &sp->u.iocb_cmd;
3822263e 300 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 301 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
302
9ba56b95 303 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 304 rval = qla2x00_start_sp(sp);
305 if (rval != QLA_SUCCESS)
306 goto done_free_sp;
307
7c3df132 308 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 309 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 310 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 311 fcport->d_id.b.area, fcport->d_id.b.al_pa,
312 fcport->port_name);
ac280b67
AV		 313 return rval;
314
315done_free_sp:
25ff6af1 316 sp->free(sp);
ac280b67 317done:
fa83e658 318 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
ac280b67
AV		 319 return rval;
320}
11aea16a
QT		 321
322void
323qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
324 uint16_t *data)
325{
fa83e658 326 fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 327 /* Don't re-login in target mode */
328 if (!fcport->tgt_session)
329 qla2x00_mark_device_lost(vha, fcport, 1, 0);
330 qlt_logo_completion_handler(fcport, data[0]);
331}
332
333static void
334qla2x00_async_prlo_sp_done(void *s, int res)
335{
336 srb_t *sp = (srb_t *)s;
337 struct srb_iocb *lio = &sp->u.iocb_cmd;
338 struct scsi_qla_host *vha = sp->vha;
339
fa83e658 340 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 341 if (!test_bit(UNLOADING, &vha->dpc_flags))
342 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
343 lio->u.logio.data);
344 sp->free(sp);
345}
346
347int
348qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
349{
350 srb_t *sp;
351 struct srb_iocb *lio;
352 int rval;
353
354 rval = QLA_FUNCTION_FAILED;
355 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
356 if (!sp)
357 goto done;
358
359 sp->type = SRB_PRLO_CMD;
360 sp->name = "prlo";
11aea16a
QT		 361
362 lio = &sp->u.iocb_cmd;
363 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 364 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
365
11aea16a
QT		 366 sp->done = qla2x00_async_prlo_sp_done;
367 rval = qla2x00_start_sp(sp);
368 if (rval != QLA_SUCCESS)
369 goto done_free_sp;
370
371 ql_dbg(ql_dbg_disc, vha, 0x2070,
372 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
373 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
374 fcport->d_id.b.area, fcport->d_id.b.al_pa);
375 return rval;
376
377done_free_sp:
378 sp->free(sp);
379done:
fa83e658 380 fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 381 return rval;
382}
383
f13515ac
QT		 384static
385void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
386{
0616e965
QT		 387 struct fc_port *fcport = ea->fcport;
388
389 ql_dbg(ql_dbg_disc, vha, 0x20d2,
390 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
391 __func__, fcport->port_name, fcport->disc_state,
392 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
393 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
394
395 if (ea->data[0] != MBS_COMMAND_COMPLETE) {
a4239945
QT		 396 ql_dbg(ql_dbg_disc, vha, 0x2066,
397 "%s %8phC: adisc fail: post delete\n",
398 __func__, ea->fcport->port_name);
94cff6e1 399 qlt_schedule_sess_for_deletion(ea->fcport);
a4239945
QT		 400 return;
401 }
a4239945
QT		 402
403 if (ea->fcport->disc_state == DSC_DELETE_PEND)
404 return;
405
406 if (ea->sp->gen2 != ea->fcport->login_gen) {
407 /* target side must have changed it. */
408 ql_dbg(ql_dbg_disc, vha, 0x20d3,
0616e965
QT		 409 "%s %8phC generation changed\n",
410 __func__, ea->fcport->port_name);
a4239945
QT		 411 return;
412 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
413 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
414 __func__, __LINE__, ea->fcport->port_name);
415 qla24xx_post_gidpn_work(vha, ea->fcport);
416 return;
417 }
418
419 __qla24xx_handle_gpdb_event(vha, ea);
f13515ac 420}
ac280b67 421
8777e431
QT		 422int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport)
423{
424 struct qla_work_evt *e;
425
426 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI);
427 if (!e)
428 return QLA_FUNCTION_FAILED;
429
430 e->u.fcport.fcport = fcport;
431 fcport->flags |= FCF_ASYNC_ACTIVE;
432 return qla2x00_post_work(vha, e);
433}
434
5ff1d584 435static void
25ff6af1 436qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 437{
25ff6af1
JC		 438 srb_t *sp = ptr;
439 struct scsi_qla_host *vha = sp->vha;
f13515ac 440 struct event_arg ea;
0616e965 441 struct srb_iocb *lio = &sp->u.iocb_cmd;
f13515ac
QT		 442
443 ql_dbg(ql_dbg_disc, vha, 0x2066,
444 "Async done-%s res %x %8phC\n",
445 sp->name, res, sp->fcport->port_name);
446
15b6c3c9 447 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
fa83e658 448
f13515ac
QT		 449 memset(&ea, 0, sizeof(ea));
450 ea.event = FCME_ADISC_DONE;
451 ea.rc = res;
0616e965
QT		 452 ea.data[0] = lio->u.logio.data[0];
453 ea.data[1] = lio->u.logio.data[1];
454 ea.iop[0] = lio->u.logio.iop[0];
455 ea.iop[1] = lio->u.logio.iop[1];
f13515ac
QT		 456 ea.fcport = sp->fcport;
457 ea.sp = sp;
458
459 qla2x00_fcport_event_handler(vha, &ea);
9ba56b95 460
25ff6af1 461 sp->free(sp);
5ff1d584
AV		 462}
463
464int
465qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
466 uint16_t *data)
467{
5ff1d584 468 srb_t *sp;
4916392b 469 struct srb_iocb *lio;
5ff1d584
AV		 470 int rval;
471
472 rval = QLA_FUNCTION_FAILED;
726b8548 473 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 474 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 475 if (!sp)
476 goto done;
477
9ba56b95
GM		 478 sp->type = SRB_ADISC_CMD;
479 sp->name = "adisc";
9ba56b95
GM		 480
481 lio = &sp->u.iocb_cmd;
3822263e 482 lio->timeout = qla2x00_async_iocb_timeout;
8777e431
QT		 483 sp->gen1 = fcport->rscn_gen;
484 sp->gen2 = fcport->login_gen;
e74e7d95
BH		 485 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
486
9ba56b95 487 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 488 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 489 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 490 rval = qla2x00_start_sp(sp);
491 if (rval != QLA_SUCCESS)
492 goto done_free_sp;
493
7c3df132 494 ql_dbg(ql_dbg_disc, vha, 0x206f,
f13515ac
QT		 495 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
496 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
5ff1d584
AV		 497 return rval;
498
499done_free_sp:
25ff6af1 500 sp->free(sp);
5ff1d584 501done:
fa83e658 502 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
f13515ac 503 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 504 return rval;
505}
506
507static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
508 struct event_arg *ea)
509{
510 fc_port_t *fcport, *conflict_fcport;
511 struct get_name_list_extended *e;
512 u16 i, n, found = 0, loop_id;
513 port_id_t id;
514 u64 wwn;
a4239945
QT		 515 u16 data[2];
516 u8 current_login_state;
726b8548
QT		 517
518 fcport = ea->fcport;
f352eeb7
QT		 519 ql_dbg(ql_dbg_disc, vha, 0xffff,
520 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n",
521 __func__, fcport->port_name, fcport->disc_state,
522 fcport->fw_login_state, ea->rc,
523 fcport->login_gen, fcport->last_login_gen,
524 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id);
726b8548 525
a4239945
QT		 526 if (fcport->disc_state == DSC_DELETE_PEND)
527 return;
528
726b8548
QT		 529 if (ea->rc) { /* rval */
530 if (fcport->login_retry == 0) {
83548fe2
QT		 531 ql_dbg(ql_dbg_disc, vha, 0x20de,
532 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
533 fcport->port_name, fcport->login_retry);
726b8548
QT		 534 }
535 return;
536 }
537
538 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 539 ql_dbg(ql_dbg_disc, vha, 0x20df,
726b8548
QT		 540 "%s %8phC rscn gen changed rscn %d|%d \n",
541 __func__, fcport->port_name,
542 fcport->last_rscn_gen, fcport->rscn_gen);
543 qla24xx_post_gidpn_work(vha, fcport);
544 return;
545 } else if (fcport->last_login_gen != fcport->login_gen) {
83548fe2 546 ql_dbg(ql_dbg_disc, vha, 0x20e0,
f352eeb7
QT		 547 "%s %8phC login gen changed\n",
548 __func__, fcport->port_name);
726b8548
QT		 549 return;
550 }
551
552 n = ea->data[0] / sizeof(struct get_name_list_extended);
553
83548fe2 554 ql_dbg(ql_dbg_disc, vha, 0x20e1,
726b8548
QT		 555 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
556 __func__, __LINE__, fcport->port_name, n,
557 fcport->d_id.b.domain, fcport->d_id.b.area,
558 fcport->d_id.b.al_pa, fcport->loop_id);
559
560 for (i = 0; i < n; i++) {
561 e = &vha->gnl.l[i];
562 wwn = wwn_to_u64(e->port_name);
48acad09
QT		 563 id.b.domain = e->port_id[2];
564 id.b.area = e->port_id[1];
565 id.b.al_pa = e->port_id[0];
566 id.b.rsvd_1 = 0;
726b8548
QT		 567
568 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
569 continue;
570
48acad09
QT		 571 if (IS_SW_RESV_ADDR(id))
572 continue;
573
726b8548 574 found = 1;
726b8548
QT		 575
576 loop_id = le16_to_cpu(e->nport_handle);
577 loop_id = (loop_id & 0x7fff);
8777e431
QT		 578 if (fcport->fc4f_nvme)
579 current_login_state = e->current_login_state >> 4;
580 else
581 current_login_state = e->current_login_state & 0xf;
582
726b8548 583
83548fe2 584 ql_dbg(ql_dbg_disc, vha, 0x20e2,
8777e431 585 "%s found %8phC CLS [%x|%x] nvme %d ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
83548fe2
QT		 586 __func__, fcport->port_name,
587 e->current_login_state, fcport->fw_login_state,
8777e431 588 fcport->fc4f_nvme, id.b.domain, id.b.area, id.b.al_pa,
83548fe2
QT		 589 fcport->d_id.b.domain, fcport->d_id.b.area,
590 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
726b8548 591
48acad09
QT		 592 switch (fcport->disc_state) {
593 case DSC_DELETE_PEND:
594 case DSC_DELETED:
595 break;
596 default:
8777e431
QT		 597 if ((id.b24 != fcport->d_id.b24 &&
598 fcport->d_id.b24) ||
599 (fcport->loop_id != FC_NO_LOOP_ID &&
600 fcport->loop_id != loop_id)) {
601 ql_dbg(ql_dbg_disc, vha, 0x20e3,
602 "%s %d %8phC post del sess\n",
603 __func__, __LINE__, fcport->port_name);
48acad09
QT		 604 qlt_schedule_sess_for_deletion(fcport);
605 return;
606 }
607 break;
726b8548
QT		 608 }
609
610 fcport->loop_id = loop_id;
611
612 wwn = wwn_to_u64(fcport->port_name);
613 qlt_find_sess_invalidate_other(vha, wwn,
614 id, loop_id, &conflict_fcport);
615
616 if (conflict_fcport) {
617 /*
618 * Another share fcport share the same loop_id &
619 * nport id. Conflict fcport needs to finish
620 * cleanup before this fcport can proceed to login.
621 */
622 conflict_fcport->conflict = fcport;
623 fcport->login_pause = 1;
624 }
625
48acad09
QT		 626 switch (vha->hw->current_topology) {
627 default:
628 switch (current_login_state) {
629 case DSC_LS_PRLI_COMP:
630 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
631 vha, 0x20e4, "%s %d %8phC post gpdb\n",
632 __func__, __LINE__, fcport->port_name);
a4239945 633
48acad09
QT		 634 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
635 fcport->port_type = FCT_INITIATOR;
636 else
637 fcport->port_type = FCT_TARGET;
638 data[0] = data[1] = 0;
639 qla2x00_post_async_adisc_work(vha, fcport,
640 data);
641 break;
642 case DSC_LS_PORT_UNAVAIL:
643 default:
644 if (fcport->loop_id != FC_NO_LOOP_ID)
645 qla2x00_clear_loop_id(fcport);
a4239945 646
48acad09 647 fcport->loop_id = loop_id;
726b8548 648 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
48acad09
QT		 649 qla24xx_fcport_handle_login(vha, fcport);
650 break;
726b8548 651 }
726b8548 652 break;
48acad09 653 case ISP_CFG_N:
8777e431
QT		 654 fcport->fw_login_state = current_login_state;
655 fcport->d_id = id;
48acad09
QT		 656 switch (current_login_state) {
657 case DSC_LS_PRLI_COMP:
658 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
659 fcport->port_type = FCT_INITIATOR;
660 else
661 fcport->port_type = FCT_TARGET;
662
663 data[0] = data[1] = 0;
664 qla2x00_post_async_adisc_work(vha, fcport,
665 data);
666 break;
667 case DSC_LS_PLOGI_COMP:
668 if (fcport_is_bigger(fcport)) {
669 /* local adapter is smaller */
670 if (fcport->loop_id != FC_NO_LOOP_ID)
671 qla2x00_clear_loop_id(fcport);
672
673 fcport->loop_id = loop_id;
674 qla24xx_fcport_handle_login(vha,
675 fcport);
676 break;
677 }
678 /* drop through */
679 default:
680 if (fcport_is_smaller(fcport)) {
681 /* local adapter is bigger */
682 if (fcport->loop_id != FC_NO_LOOP_ID)
683 qla2x00_clear_loop_id(fcport);
684
685 fcport->loop_id = loop_id;
686 qla24xx_fcport_handle_login(vha,
687 fcport);
688 }
689 break;
690 }
691 break;
692 } /* switch (ha->current_topology) */
726b8548
QT		 693 }
694
695 if (!found) {
48acad09
QT		 696 switch (vha->hw->current_topology) {
697 case ISP_CFG_F:
698 case ISP_CFG_FL:
699 for (i = 0; i < n; i++) {
700 e = &vha->gnl.l[i];
701 id.b.domain = e->port_id[0];
702 id.b.area = e->port_id[1];
703 id.b.al_pa = e->port_id[2];
704 id.b.rsvd_1 = 0;
705 loop_id = le16_to_cpu(e->nport_handle);
706
707 if (fcport->d_id.b24 == id.b24) {
708 conflict_fcport =
709 qla2x00_find_fcport_by_wwpn(vha,
710 e->port_name, 0);
72f02ba6
LT		 711 if (conflict_fcport) {
712 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
713 vha, 0x20e5,
714 "%s %d %8phC post del sess\n",
715 __func__, __LINE__,
716 conflict_fcport->port_name);
717 qlt_schedule_sess_for_deletion
718 (conflict_fcport);
719 }
36eb8ff6 720 }
48acad09
QT		 721 /*
722 * FW already picked this loop id for
723 * another fcport
724 */
725 if (fcport->loop_id == loop_id)
726 fcport->loop_id = FC_NO_LOOP_ID;
726b8548 727 }
48acad09
QT		 728 qla24xx_fcport_handle_login(vha, fcport);
729 break;
730 case ISP_CFG_N:
8777e431
QT		 731 fcport->disc_state = DSC_DELETED;
732 if (time_after_eq(jiffies, fcport->dm_login_expire)) {
733 if (fcport->n2n_link_reset_cnt < 2) {
734 fcport->n2n_link_reset_cnt++;
735 /*
736 * remote port is not sending PLOGI.
737 * Reset link to kick start his state
738 * machine
739 */
740 set_bit(N2N_LINK_RESET,
741 &vha->dpc_flags);
742 } else {
743 if (fcport->n2n_chip_reset < 1) {
744 ql_log(ql_log_info, vha, 0x705d,
745 "Chip reset to bring laser down");
746 set_bit(ISP_ABORT_NEEDED,
747 &vha->dpc_flags);
748 fcport->n2n_chip_reset++;
749 } else {
750 ql_log(ql_log_info, vha, 0x705d,
751 "Remote port %8ph is not coming back\n",
752 fcport->port_name);
753 fcport->scan_state = 0;
754 }
755 }
756 qla2xxx_wake_dpc(vha);
757 } else {
758 /*
759 * report port suppose to do PLOGI. Give him
760 * more time. FW will catch it.
761 */
762 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
763 }
48acad09
QT		 764 break;
765 default:
766 break;
726b8548 767 }
726b8548
QT		 768 }
769} /* gnl_event */
770
771static void
25ff6af1 772qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 773{
25ff6af1
JC		 774 struct srb *sp = s;
775 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 776 unsigned long flags;
777 struct fc_port *fcport = NULL, *tf;
778 u16 i, n = 0, loop_id;
779 struct event_arg ea;
780 struct get_name_list_extended *e;
781 u64 wwn;
782 struct list_head h;
a4239945 783 bool found = false;
726b8548 784
83548fe2 785 ql_dbg(ql_dbg_disc, vha, 0x20e7,
726b8548
QT		 786 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
787 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
788 sp->u.iocb_cmd.u.mbx.in_mb[2]);
789
790 memset(&ea, 0, sizeof(ea));
791 ea.sp = sp;
792 ea.rc = res;
793 ea.event = FCME_GNL_DONE;
794
795 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
796 sizeof(struct get_name_list_extended)) {
797 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
798 sizeof(struct get_name_list_extended);
799 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
800 }
801
802 for (i = 0; i < n; i++) {
803 e = &vha->gnl.l[i];
804 loop_id = le16_to_cpu(e->nport_handle);
805 /* mask out reserve bit */
806 loop_id = (loop_id & 0x7fff);
807 set_bit(loop_id, vha->hw->loop_id_map);
808 wwn = wwn_to_u64(e->port_name);
809
83548fe2 810 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
726b8548
QT		 811 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
812 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
813 e->port_id[0], e->current_login_state, e->last_login_state,
814 (loop_id & 0x7fff));
815 }
816
1c6cacf4 817 spin_lock_irqsave(&vha->gnl.fcports_lock, flags);
726b8548
QT		 818
819 INIT_LIST_HEAD(&h);
820 fcport = tf = NULL;
821 if (!list_empty(&vha->gnl.fcports))
822 list_splice_init(&vha->gnl.fcports, &h);
823
824 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
825 list_del_init(&fcport->gnl_entry);
1c6cacf4 826 spin_lock(&vha->hw->tgt.sess_lock);
6d674927 827 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1c6cacf4 828 spin_unlock(&vha->hw->tgt.sess_lock);
726b8548
QT		 829 ea.fcport = fcport;
830
831 qla2x00_fcport_event_handler(vha, &ea);
832 }
1c6cacf4 833 spin_unlock_irqrestore(&vha->gnl.fcports_lock, flags);
726b8548 834
1c6cacf4 835 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945
QT		 836 /* create new fcport if fw has knowledge of new sessions */
837 for (i = 0; i < n; i++) {
838 port_id_t id;
839 u64 wwnn;
840
841 e = &vha->gnl.l[i];
842 wwn = wwn_to_u64(e->port_name);
843
844 found = false;
845 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
846 if (!memcmp((u8 *)&wwn, fcport->port_name,
847 WWN_SIZE)) {
848 found = true;
849 break;
850 }
851 }
852
cf055fb0 853 id.b.domain = e->port_id[2];
a4239945 854 id.b.area = e->port_id[1];
cf055fb0 855 id.b.al_pa = e->port_id[0];
a4239945
QT		 856 id.b.rsvd_1 = 0;
857
858 if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
859 ql_dbg(ql_dbg_disc, vha, 0x2065,
cf055fb0
QT		 860 "%s %d %8phC %06x post new sess\n",
861 __func__, __LINE__, (u8 *)&wwn, id.b24);
a4239945
QT		 862 wwnn = wwn_to_u64(e->node_name);
863 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
864 (u8 *)&wwnn, NULL, FC4_TYPE_UNKNOWN);
865 }
866 }
867
726b8548
QT		 868 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
869
25ff6af1 870 sp->free(sp);
726b8548
QT		 871}
872
873int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
874{
875 srb_t *sp;
876 struct srb_iocb *mbx;
877 int rval = QLA_FUNCTION_FAILED;
878 unsigned long flags;
879 u16 *mb;
880
3dbec59b
QT		 881 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
882 return rval;
726b8548 883
83548fe2 884 ql_dbg(ql_dbg_disc, vha, 0x20d9,
726b8548
QT		 885 "Async-gnlist WWPN %8phC \n", fcport->port_name);
886
1c6cacf4
HR		 887 spin_lock_irqsave(&vha->gnl.fcports_lock, flags);
888 if (!list_empty(&fcport->gnl_entry)) {
889 spin_unlock_irqrestore(&vha->gnl.fcports_lock, flags);
890 rval = QLA_SUCCESS;
891 goto done;
892 }
893
894 spin_lock(&vha->hw->tgt.sess_lock);
726b8548
QT		 895 fcport->disc_state = DSC_GNL;
896 fcport->last_rscn_gen = fcport->rscn_gen;
897 fcport->last_login_gen = fcport->login_gen;
1c6cacf4 898 spin_unlock(&vha->hw->tgt.sess_lock);
726b8548
QT		 899
900 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
1c6cacf4 901 spin_unlock_irqrestore(&vha->gnl.fcports_lock, flags);
726b8548
QT		 902
903 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
904 if (!sp)
905 goto done;
3dbec59b
QT		 906
907 fcport->flags |= FCF_ASYNC_SENT;
726b8548
QT		 908 sp->type = SRB_MB_IOCB;
909 sp->name = "gnlist";
910 sp->gen1 = fcport->rscn_gen;
911 sp->gen2 = fcport->login_gen;
912
e74e7d95
BH		 913 mbx = &sp->u.iocb_cmd;
914 mbx->timeout = qla2x00_async_iocb_timeout;
726b8548
QT		 915 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
916
917 mb = sp->u.iocb_cmd.u.mbx.out_mb;
918 mb[0] = MBC_PORT_NODE_NAME_LIST;
919 mb[1] = BIT_2 | BIT_3;
920 mb[2] = MSW(vha->gnl.ldma);
921 mb[3] = LSW(vha->gnl.ldma);
922 mb[6] = MSW(MSD(vha->gnl.ldma));
923 mb[7] = LSW(MSD(vha->gnl.ldma));
924 mb[8] = vha->gnl.size;
925 mb[9] = vha->vp_idx;
926
726b8548
QT		 927 sp->done = qla24xx_async_gnl_sp_done;
928
929 rval = qla2x00_start_sp(sp);
930 if (rval != QLA_SUCCESS)
931 goto done_free_sp;
932
83548fe2
QT		 933 ql_dbg(ql_dbg_disc, vha, 0x20da,
934 "Async-%s - OUT WWPN %8phC hndl %x\n",
935 sp->name, fcport->port_name, sp->handle);
726b8548
QT		 936
937 return rval;
938
939done_free_sp:
25ff6af1 940 sp->free(sp);
726b8548 941 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 942done:
726b8548
QT		 943 return rval;
944}
945
946int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
947{
948 struct qla_work_evt *e;
949
950 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
951 if (!e)
952 return QLA_FUNCTION_FAILED;
953
954 e->u.fcport.fcport = fcport;
6d674927 955 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 956 return qla2x00_post_work(vha, e);
957}
958
959static
25ff6af1 960void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 961{
25ff6af1
JC		 962 struct srb *sp = s;
963 struct scsi_qla_host *vha = sp->vha;
726b8548 964 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 965 fc_port_t *fcport = sp->fcport;
966 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
726b8548
QT		 967 struct event_arg ea;
968
83548fe2 969 ql_dbg(ql_dbg_disc, vha, 0x20db,
726b8548
QT		 970 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
971 sp->name, res, fcport->port_name, mb[1], mb[2]);
972
6d674927 973 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
726b8548 974
726b8548
QT		 975 memset(&ea, 0, sizeof(ea));
976 ea.event = FCME_GPDB_DONE;
726b8548
QT		 977 ea.fcport = fcport;
978 ea.sp = sp;
979
980 qla2x00_fcport_event_handler(vha, &ea);
981
982 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
983 sp->u.iocb_cmd.u.mbx.in_dma);
984
25ff6af1 985 sp->free(sp);
726b8548
QT		 986}
987
a5d42f4c
DG		 988static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
989{
990 struct qla_work_evt *e;
991
992 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
993 if (!e)
994 return QLA_FUNCTION_FAILED;
995
996 e->u.fcport.fcport = fcport;
997
998 return qla2x00_post_work(vha, e);
999}
1000
1001static void
1002qla2x00_async_prli_sp_done(void *ptr, int res)
1003{
1004 srb_t *sp = ptr;
1005 struct scsi_qla_host *vha = sp->vha;
1006 struct srb_iocb *lio = &sp->u.iocb_cmd;
1007 struct event_arg ea;
1008
1009 ql_dbg(ql_dbg_disc, vha, 0x2129,
1010 "%s %8phC res %d \n", __func__,
1011 sp->fcport->port_name, res);
1012
1013 sp->fcport->flags &= ~FCF_ASYNC_SENT;
1014
1015 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
1016 memset(&ea, 0, sizeof(ea));
1017 ea.event = FCME_PRLI_DONE;
1018 ea.fcport = sp->fcport;
1019 ea.data[0] = lio->u.logio.data[0];
1020 ea.data[1] = lio->u.logio.data[1];
1021 ea.iop[0] = lio->u.logio.iop[0];
1022 ea.iop[1] = lio->u.logio.iop[1];
1023 ea.sp = sp;
1024
1025 qla2x00_fcport_event_handler(vha, &ea);
1026 }
1027
1028 sp->free(sp);
1029}
1030
1031int
1032qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
1033{
1034 srb_t *sp;
1035 struct srb_iocb *lio;
1036 int rval = QLA_FUNCTION_FAILED;
1037
1038 if (!vha->flags.online)
1039 return rval;
1040
1041 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
a5d42f4c
DG		 1042 fcport->fw_login_state == DSC_LS_PRLI_PEND)
1043 return rval;
1044
1045 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1046 if (!sp)
1047 return rval;
1048
1049 fcport->flags |= FCF_ASYNC_SENT;
1050 fcport->logout_completed = 0;
1051
1052 sp->type = SRB_PRLI_CMD;
1053 sp->name = "prli";
a5d42f4c
DG		 1054
1055 lio = &sp->u.iocb_cmd;
1056 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 1057 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1058
a5d42f4c
DG		 1059 sp->done = qla2x00_async_prli_sp_done;
1060 lio->u.logio.flags = 0;
1061
1062 if (fcport->fc4f_nvme)
1063 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
1064
1065 rval = qla2x00_start_sp(sp);
1066 if (rval != QLA_SUCCESS) {
a5d42f4c
DG		 1067 fcport->flags |= FCF_LOGIN_NEEDED;
1068 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1069 goto done_free_sp;
1070 }
1071
1072 ql_dbg(ql_dbg_disc, vha, 0x211b,
8777e431
QT		 1073 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d %s.\n",
1074 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24,
1075 fcport->login_retry, fcport->fc4f_nvme ? "nvme" : "fc");
a5d42f4c
DG		 1076
1077 return rval;
1078
1079done_free_sp:
1080 sp->free(sp);
1081 fcport->flags &= ~FCF_ASYNC_SENT;
1082 return rval;
1083}
1084
a07fc0a4 1085int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
726b8548
QT		 1086{
1087 struct qla_work_evt *e;
1088
1089 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
1090 if (!e)
1091 return QLA_FUNCTION_FAILED;
1092
1093 e->u.fcport.fcport = fcport;
1094 e->u.fcport.opt = opt;
6d674927 1095 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 1096 return qla2x00_post_work(vha, e);
1097}
1098
1099int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
1100{
1101 srb_t *sp;
1102 struct srb_iocb *mbx;
1103 int rval = QLA_FUNCTION_FAILED;
1104 u16 *mb;
1105 dma_addr_t pd_dma;
1106 struct port_database_24xx *pd;
1107 struct qla_hw_data *ha = vha->hw;
1108
3dbec59b
QT		 1109 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
1110 return rval;
726b8548 1111
726b8548
QT		 1112 fcport->disc_state = DSC_GPDB;
1113
1114 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1115 if (!sp)
1116 goto done;
1117
3dbec59b 1118 fcport->flags |= FCF_ASYNC_SENT;
e0824e69
JC		 1119 sp->type = SRB_MB_IOCB;
1120 sp->name = "gpdb";
1121 sp->gen1 = fcport->rscn_gen;
1122 sp->gen2 = fcport->login_gen;
e74e7d95
BH		 1123
1124 mbx = &sp->u.iocb_cmd;
1125 mbx->timeout = qla2x00_async_iocb_timeout;
e0824e69
JC		 1126 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1127
08eb7f45 1128 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
726b8548 1129 if (pd == NULL) {
83548fe2
QT		 1130 ql_log(ql_log_warn, vha, 0xd043,
1131 "Failed to allocate port database structure.\n");
726b8548
QT		 1132 goto done_free_sp;
1133 }
726b8548 1134
726b8548
QT		 1135 mb = sp->u.iocb_cmd.u.mbx.out_mb;
1136 mb[0] = MBC_GET_PORT_DATABASE;
1137 mb[1] = fcport->loop_id;
1138 mb[2] = MSW(pd_dma);
1139 mb[3] = LSW(pd_dma);
1140 mb[6] = MSW(MSD(pd_dma));
1141 mb[7] = LSW(MSD(pd_dma));
1142 mb[9] = vha->vp_idx;
1143 mb[10] = opt;
1144
726b8548
QT		 1145 mbx->u.mbx.in = (void *)pd;
1146 mbx->u.mbx.in_dma = pd_dma;
1147
1148 sp->done = qla24xx_async_gpdb_sp_done;
1149
1150 rval = qla2x00_start_sp(sp);
1151 if (rval != QLA_SUCCESS)
1152 goto done_free_sp;
1153
83548fe2
QT		 1154 ql_dbg(ql_dbg_disc, vha, 0x20dc,
1155 "Async-%s %8phC hndl %x opt %x\n",
1156 sp->name, fcport->port_name, sp->handle, opt);
726b8548
QT		 1157
1158 return rval;
1159
1160done_free_sp:
1161 if (pd)
1162 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1163
25ff6af1 1164 sp->free(sp);
726b8548 1165 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 1166done:
726b8548 1167 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 1168 return rval;
1169}
1170
726b8548 1171static
a4239945 1172void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1173{
726b8548
QT		 1174 unsigned long flags;
1175
726b8548 1176 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
f13515ac 1177 ea->fcport->login_gen++;
726b8548
QT		 1178 ea->fcport->deleted = 0;
1179 ea->fcport->logout_on_delete = 1;
1180
1181 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
1182 vha->fcport_count++;
1183 ea->fcport->login_succ = 1;
1184
cd4ed6b4 1185 qla24xx_sched_upd_fcport(ea->fcport);
414d9ff3
QT		 1186 } else if (ea->fcport->login_succ) {
1187 /*
1188 * We have an existing session. A late RSCN delivery
1189 * must have triggered the session to be re-validate.
a4239945 1190 * Session is still valid.
414d9ff3 1191 */
5ef696aa
QT		 1192 ql_dbg(ql_dbg_disc, vha, 0x20d6,
1193 "%s %d %8phC session revalidate success\n",
a4239945 1194 __func__, __LINE__, ea->fcport->port_name);
8a7eac2f 1195 ea->fcport->disc_state = DSC_LOGIN_COMPLETE;
726b8548
QT		 1196 }
1197 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
a4239945
QT		 1198}
1199
1200static
1201void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1202{
a4239945
QT		 1203 fc_port_t *fcport = ea->fcport;
1204 struct port_database_24xx *pd;
1205 struct srb *sp = ea->sp;
2b5b9647 1206 uint8_t ls;
a4239945
QT		 1207
1208 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
1209
1210 fcport->flags &= ~FCF_ASYNC_SENT;
1211
1212 ql_dbg(ql_dbg_disc, vha, 0x20d2,
8777e431
QT		 1213 "%s %8phC DS %d LS %d nvme %x rc %d\n", __func__, fcport->port_name,
1214 fcport->disc_state, pd->current_login_state, fcport->fc4f_nvme,
1215 ea->rc);
a4239945
QT		 1216
1217 if (fcport->disc_state == DSC_DELETE_PEND)
1218 return;
726b8548 1219
2b5b9647
DT		 1220 if (fcport->fc4f_nvme)
1221 ls = pd->current_login_state >> 4;
1222 else
1223 ls = pd->current_login_state & 0xf;
1224
1225 switch (ls) {
a4239945
QT		 1226 case PDS_PRLI_COMPLETE:
1227 __qla24xx_parse_gpdb(vha, fcport, pd);
1228 break;
1229 case PDS_PLOGI_PENDING:
1230 case PDS_PLOGI_COMPLETE:
1231 case PDS_PRLI_PENDING:
1232 case PDS_PRLI2_PENDING:
8fde6977
QT		 1233 /* Set discovery state back to GNL to Relogin attempt */
1234 if (qla_dual_mode_enabled(vha) ||
1235 qla_ini_mode_enabled(vha)) {
1236 fcport->disc_state = DSC_GNL;
1237 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1238 }
a4239945
QT		 1239 return;
1240 case PDS_LOGO_PENDING:
1241 case PDS_PORT_UNAVAILABLE:
1242 default:
1243 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
1244 __func__, __LINE__, fcport->port_name);
d8630bb9 1245 qlt_schedule_sess_for_deletion(fcport);
a4239945
QT		 1246 return;
1247 }
1248 __qla24xx_handle_gpdb_event(vha, ea);
1249} /* gpdb event */
9cd883f0
QT		 1250
1251static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1252{
1253 u8 login = 0;
040036bb 1254 int rc;
9cd883f0
QT		 1255
1256 if (qla_tgt_mode_enabled(vha))
1257 return;
1258
1259 if (qla_dual_mode_enabled(vha)) {
1260 if (N2N_TOPO(vha->hw)) {
1261 u64 mywwn, wwn;
1262
1263 mywwn = wwn_to_u64(vha->port_name);
1264 wwn = wwn_to_u64(fcport->port_name);
1265 if (mywwn > wwn)
1266 login = 1;
1267 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1268 && time_after_eq(jiffies,
1269 fcport->plogi_nack_done_deadline))
1270 login = 1;
1271 } else {
1272 login = 1;
1273 }
1274 } else {
1275 /* initiator mode */
1276 login = 1;
1277 }
1278
0754d5e0
QT		 1279 if (login && fcport->login_retry) {
1280 fcport->login_retry--;
040036bb
QT		 1281 if (fcport->loop_id == FC_NO_LOOP_ID) {
1282 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
1283 rc = qla2x00_find_new_loop_id(vha, fcport);
1284 if (rc) {
1285 ql_dbg(ql_dbg_disc, vha, 0x20e6,
1286 "%s %d %8phC post del sess - out of loopid\n",
1287 __func__, __LINE__, fcport->port_name);
1288 fcport->scan_state = 0;
94cff6e1 1289 qlt_schedule_sess_for_deletion(fcport);
040036bb
QT		 1290 return;
1291 }
1292 }
9cd883f0
QT		 1293 ql_dbg(ql_dbg_disc, vha, 0x20bf,
1294 "%s %d %8phC post login\n",
1295 __func__, __LINE__, fcport->port_name);
9cd883f0
QT		 1296 qla2x00_post_async_login_work(vha, fcport, NULL);
1297 }
1298}
1299
726b8548
QT		 1300int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1301{
f13515ac 1302 u16 data[2];
a4239945 1303 u64 wwn;
cd4ed6b4 1304 u16 sec;
726b8548 1305
0754d5e0
QT		 1306 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20d8,
1307 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d\n",
726b8548
QT		 1308 __func__, fcport->port_name, fcport->disc_state,
1309 fcport->fw_login_state, fcport->login_pause, fcport->flags,
1310 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
0754d5e0 1311 fcport->login_gen, fcport->loop_id, fcport->scan_state);
726b8548 1312
a4239945
QT		 1313 if (fcport->scan_state != QLA_FCPORT_FOUND)
1314 return 0;
726b8548 1315
07ea4b60
HR		 1316 if ((fcport->loop_id != FC_NO_LOOP_ID) &&
1317 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1318 (fcport->fw_login_state == DSC_LS_PRLI_PEND)))
726b8548
QT		 1319 return 0;
1320
5b33469a 1321 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1322 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1323 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1324 return 0;
9cd883f0 1325 }
5b33469a
QT		 1326 }
1327
726b8548
QT		 1328 /* for pure Target Mode. Login will not be initiated */
1329 if (vha->host->active_mode == MODE_TARGET)
1330 return 0;
1331
1332 if (fcport->flags & FCF_ASYNC_SENT) {
1333 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1334 return 0;
1335 }
1336
1337 switch (fcport->disc_state) {
1338 case DSC_DELETED:
a4239945 1339 wwn = wwn_to_u64(fcport->node_name);
8777e431
QT		 1340 switch (vha->hw->current_topology) {
1341 case ISP_CFG_N:
1342 if (fcport_is_smaller(fcport)) {
1343 /* this adapter is bigger */
1344 if (fcport->login_retry) {
1345 if (fcport->loop_id == FC_NO_LOOP_ID) {
1346 qla2x00_find_new_loop_id(vha,
1347 fcport);
1348 fcport->fw_login_state =
1349 DSC_LS_PORT_UNAVAIL;
1350 }
1351 fcport->login_retry--;
1352 qla_post_els_plogi_work(vha, fcport);
1353 } else {
1354 ql_log(ql_log_info, vha, 0x705d,
1355 "Unable to reach remote port %8phC",
1356 fcport->port_name);
1357 }
1358 } else {
1359 qla24xx_post_gnl_work(vha, fcport);
1360 }
1361 break;
1362 default:
1363 if (wwn == 0) {
1364 ql_dbg(ql_dbg_disc, vha, 0xffff,
1365 "%s %d %8phC post GNNID\n",
1366 __func__, __LINE__, fcport->port_name);
1367 qla24xx_post_gnnid_work(vha, fcport);
1368 } else if (fcport->loop_id == FC_NO_LOOP_ID) {
1369 ql_dbg(ql_dbg_disc, vha, 0x20bd,
1370 "%s %d %8phC post gnl\n",
1371 __func__, __LINE__, fcport->port_name);
1372 qla24xx_post_gnl_work(vha, fcport);
1373 } else {
1374 qla_chk_n2n_b4_login(vha, fcport);
1375 }
1376 break;
726b8548
QT		 1377 }
1378 break;
1379
1380 case DSC_GNL:
8777e431
QT		 1381 switch (vha->hw->current_topology) {
1382 case ISP_CFG_N:
1383 if ((fcport->current_login_state & 0xf) == 0x6) {
1384 ql_dbg(ql_dbg_disc, vha, 0x2118,
1385 "%s %d %8phC post GPDB work\n",
1386 __func__, __LINE__, fcport->port_name);
1387 fcport->chip_reset =
1388 vha->hw->base_qpair->chip_reset;
1389 qla24xx_post_gpdb_work(vha, fcport, 0);
1390 } else {
1391 ql_dbg(ql_dbg_disc, vha, 0x2118,
1392 "%s %d %8phC post NVMe PRLI\n",
1393 __func__, __LINE__, fcport->port_name);
1394 qla24xx_post_prli_work(vha, fcport);
1395 }
1396 break;
1397 default:
1398 if (fcport->login_pause) {
1399 fcport->last_rscn_gen = fcport->rscn_gen;
1400 fcport->last_login_gen = fcport->login_gen;
1401 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1402 break;
1403 }
1404 qla_chk_n2n_b4_login(vha, fcport);
726b8548
QT		 1405 break;
1406 }
726b8548
QT		 1407 break;
1408
1409 case DSC_LOGIN_FAILED:
9cd883f0
QT		 1410 if (N2N_TOPO(vha->hw))
1411 qla_chk_n2n_b4_login(vha, fcport);
1412 else
1413 qla24xx_post_gidpn_work(vha, fcport);
726b8548
QT		 1414 break;
1415
1416 case DSC_LOGIN_COMPLETE:
1417 /* recheck login state */
f13515ac
QT		 1418 data[0] = data[1] = 0;
1419 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 1420 break;
1421
1cbc0efc
DT		 1422 case DSC_LOGIN_PEND:
1423 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1424 qla24xx_post_prli_work(vha, fcport);
1425 break;
1426
cd4ed6b4
QT		 1427 case DSC_UPD_FCPORT:
1428 sec = jiffies_to_msecs(jiffies -
1429 fcport->jiffies_at_registration)/1000;
1430 if (fcport->sec_since_registration < sec && sec &&
1431 !(sec % 60)) {
1432 fcport->sec_since_registration = sec;
1433 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
1434 "%s %8phC - Slow Rport registration(%d Sec)\n",
1435 __func__, fcport->port_name, sec);
1436 }
1437
1438 if (fcport->next_disc_state != DSC_DELETE_PEND)
1439 fcport->next_disc_state = DSC_ADISC;
1440 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1441 break;
1442
726b8548
QT		 1443 default:
1444 break;
1445 }
1446
1447 return 0;
1448}
1449
1450static
1451void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
1452{
1453 fcport->rscn_gen++;
1454
83548fe2
QT		 1455 ql_dbg(ql_dbg_disc, fcport->vha, 0x210c,
1456 "%s %8phC DS %d LS %d\n",
1457 __func__, fcport->port_name, fcport->disc_state,
1458 fcport->fw_login_state);
726b8548
QT		 1459
1460 if (fcport->flags & FCF_ASYNC_SENT)
1461 return;
1462
1463 switch (fcport->disc_state) {
1464 case DSC_DELETED:
1465 case DSC_LOGIN_COMPLETE:
5ef696aa 1466 qla24xx_post_gpnid_work(fcport->vha, &ea->id);
726b8548 1467 break;
726b8548
QT		 1468 default:
1469 break;
1470 }
1471}
1472
1473int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
a4239945 1474 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
726b8548
QT		 1475{
1476 struct qla_work_evt *e;
1477 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1478 if (!e)
1479 return QLA_FUNCTION_FAILED;
1480
1481 e->u.new_sess.id = *id;
1482 e->u.new_sess.pla = pla;
a4239945 1483 e->u.new_sess.fc4_type = fc4_type;
726b8548 1484 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
a4239945
QT		 1485 if (node_name)
1486 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
726b8548
QT		 1487
1488 return qla2x00_post_work(vha, e);
1489}
1490
726b8548
QT		 1491static
1492void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1493 struct event_arg *ea)
1494{
1495 fc_port_t *fcport = ea->fcport;
1496
83548fe2
QT		 1497 ql_dbg(ql_dbg_disc, vha, 0x2102,
1498 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1499 __func__, fcport->port_name, fcport->disc_state,
1500 fcport->fw_login_state, fcport->login_pause,
1501 fcport->deleted, fcport->conflict,
1502 fcport->last_rscn_gen, fcport->rscn_gen,
1503 fcport->last_login_gen, fcport->login_gen,
1504 fcport->flags);
726b8548
QT		 1505
1506 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1507 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1508 return;
1509
5b33469a 1510 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1511 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1512 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1513 return;
9cd883f0 1514 }
5b33469a
QT		 1515 }
1516
726b8548 1517 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 1518 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gidpn\n",
726b8548
QT		 1519 __func__, __LINE__, fcport->port_name);
1520
5d3300a9 1521 qla24xx_post_gidpn_work(vha, fcport);
726b8548
QT		 1522 return;
1523 }
1524
1525 qla24xx_fcport_handle_login(vha, fcport);
1526}
1527
8777e431
QT		 1528
1529void qla_handle_els_plogi_done(scsi_qla_host_t *vha, struct event_arg *ea)
1530{
1531 ql_dbg(ql_dbg_disc, vha, 0x2118,
1532 "%s %d %8phC post PRLI\n",
1533 __func__, __LINE__, ea->fcport->port_name);
1534 qla24xx_post_prli_work(vha, ea->fcport);
1535}
1536
41dc529a 1537void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1538{
f352eeb7 1539 fc_port_t *f, *tf;
41dc529a 1540 uint32_t id = 0, mask, rid;
f352eeb7 1541 unsigned long flags;
bee8b846 1542 fc_port_t *fcport;
726b8548
QT		 1543
1544 switch (ea->event) {
1545 case FCME_RELOGIN:
1546 if (test_bit(UNLOADING, &vha->dpc_flags))
1547 return;
5ff1d584 1548
726b8548
QT		 1549 qla24xx_handle_relogin_event(vha, ea);
1550 break;
1551 case FCME_RSCN:
1552 if (test_bit(UNLOADING, &vha->dpc_flags))
1553 return;
41dc529a
QT		 1554 switch (ea->id.b.rsvd_1) {
1555 case RSCN_PORT_ADDR:
bee8b846
QT		 1556 fcport = qla2x00_find_fcport_by_nportid
1557 (vha, &ea->id, 1);
cd4ed6b4 1558 if (fcport) {
cb873ba4 1559 fcport->scan_needed = 1;
cd4ed6b4
QT		 1560 fcport->rscn_gen++;
1561 }
bee8b846 1562
f352eeb7
QT		 1563 spin_lock_irqsave(&vha->work_lock, flags);
1564 if (vha->scan.scan_flags == 0) {
1565 ql_dbg(ql_dbg_disc, vha, 0xffff,
1566 "%s: schedule\n", __func__);
1567 vha->scan.scan_flags |= SF_QUEUED;
1568 schedule_delayed_work(&vha->scan.scan_work, 5);
41dc529a 1569 }
f352eeb7
QT		 1570 spin_unlock_irqrestore(&vha->work_lock, flags);
1571
41dc529a
QT		 1572 break;
1573 case RSCN_AREA_ADDR:
1574 case RSCN_DOM_ADDR:
1575 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1576 mask = 0xffff00;
83548fe2
QT		 1577 ql_dbg(ql_dbg_async, vha, 0x5044,
1578 "RSCN: Area 0x%06x was affected\n",
1579 ea->id.b24);
41dc529a
QT		 1580 } else {
1581 mask = 0xff0000;
83548fe2
QT		 1582 ql_dbg(ql_dbg_async, vha, 0x507a,
1583 "RSCN: Domain 0x%06x was affected\n",
1584 ea->id.b24);
41dc529a 1585 }
726b8548 1586
41dc529a
QT		 1587 rid = ea->id.b24 & mask;
1588 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1589 list) {
1590 id = f->d_id.b24 & mask;
1591 if (rid == id) {
1592 ea->fcport = f;
1593 qla24xx_handle_rscn_event(f, ea);
1594 }
726b8548 1595 }
41dc529a
QT		 1596 break;
1597 case RSCN_FAB_ADDR:
1598 default:
83548fe2
QT		 1599 ql_log(ql_log_warn, vha, 0xd045,
1600 "RSCN: Fabric was affected. Addr format %d\n",
1601 ea->id.b.rsvd_1);
41dc529a
QT		 1602 qla2x00_mark_all_devices_lost(vha, 1);
1603 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1604 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1605 }
1606 break;
1607 case FCME_GIDPN_DONE:
1608 qla24xx_handle_gidpn_event(vha, ea);
1609 break;
1610 case FCME_GNL_DONE:
1611 qla24xx_handle_gnl_done_event(vha, ea);
1612 break;
1613 case FCME_GPSC_DONE:
a4239945 1614 qla24xx_handle_gpsc_event(vha, ea);
726b8548
QT		 1615 break;
1616 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1617 qla24xx_handle_plogi_done_event(vha, ea);
1618 break;
a5d42f4c
DG		 1619 case FCME_PRLI_DONE:
1620 qla24xx_handle_prli_done_event(vha, ea);
1621 break;
726b8548
QT		 1622 case FCME_GPDB_DONE:
1623 qla24xx_handle_gpdb_event(vha, ea);
1624 break;
1625 case FCME_GPNID_DONE:
1626 qla24xx_handle_gpnid_event(vha, ea);
1627 break;
d3bae931
DG		 1628 case FCME_GFFID_DONE:
1629 qla24xx_handle_gffid_event(vha, ea);
1630 break;
f13515ac
QT		 1631 case FCME_ADISC_DONE:
1632 qla24xx_handle_adisc_event(vha, ea);
1633 break;
a4239945
QT		 1634 case FCME_GNNID_DONE:
1635 qla24xx_handle_gnnid_event(vha, ea);
1636 break;
1637 case FCME_GFPNID_DONE:
1638 qla24xx_handle_gfpnid_event(vha, ea);
1639 break;
8777e431
QT		 1640 case FCME_ELS_PLOGI_DONE:
1641 qla_handle_els_plogi_done(vha, ea);
1642 break;
726b8548
QT		 1643 default:
1644 BUG_ON(1);
1645 break;
1646 }
5ff1d584
AV		 1647}
1648
3822263e 1649static void
faef62d1 1650qla2x00_tmf_iocb_timeout(void *data)
3822263e 1651{
25ff6af1 1652 srb_t *sp = data;
faef62d1 1653 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1654
faef62d1
AB		 1655 tmf->u.tmf.comp_status = CS_TIMEOUT;
1656 complete(&tmf->u.tmf.comp);
1657}
9ba56b95 1658
faef62d1 1659static void
25ff6af1 1660qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1661{
25ff6af1 1662 srb_t *sp = ptr;
faef62d1 1663 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1664
faef62d1 1665 complete(&tmf->u.tmf.comp);
3822263e
MI		 1666}
1667
1668int
faef62d1 1669qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1670 uint32_t tag)
1671{
1672 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1673 struct srb_iocb *tm_iocb;
3822263e 1674 srb_t *sp;
faef62d1 1675 int rval = QLA_FUNCTION_FAILED;
3822263e 1676
9ba56b95 1677 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1678 if (!sp)
1679 goto done;
1680
faef62d1 1681 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1682 sp->type = SRB_TM_CMD;
1683 sp->name = "tmf";
e74e7d95
BH		 1684
1685 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1686 init_completion(&tm_iocb->u.tmf.comp);
faef62d1 1687 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
e74e7d95 1688
faef62d1
AB		 1689 tm_iocb->u.tmf.flags = flags;
1690 tm_iocb->u.tmf.lun = lun;
1691 tm_iocb->u.tmf.data = tag;
1692 sp->done = qla2x00_tmf_sp_done;
3822263e
MI		 1693
1694 rval = qla2x00_start_sp(sp);
1695 if (rval != QLA_SUCCESS)
1696 goto done_free_sp;
1697
7c3df132 1698 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1699 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1700 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1701 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1702
1703 wait_for_completion(&tm_iocb->u.tmf.comp);
1704
b4146c49 1705 rval = tm_iocb->u.tmf.data;
faef62d1 1706
b4146c49
AG		 1707 if (rval != QLA_SUCCESS) {
1708 ql_log(ql_log_warn, vha, 0x8030,
faef62d1
AB		 1709 "TM IOCB failed (%x).\n", rval);
1710 }
1711
1712 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1713 flags = tm_iocb->u.tmf.flags;
1714 lun = (uint16_t)tm_iocb->u.tmf.lun;
1715
1716 /* Issue Marker IOCB */
1717 qla2x00_marker(vha, vha->hw->req_q_map[0],
1718 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1719 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1720 }
3822263e
MI		 1721
1722done_free_sp:
25ff6af1 1723 sp->free(sp);
6d674927 1724 sp->fcport->flags &= ~FCF_ASYNC_SENT;
3822263e
MI		 1725done:
1726 return rval;
1727}
1728
4440e46d
AB		 1729static void
1730qla24xx_abort_iocb_timeout(void *data)
1731{
25ff6af1 1732 srb_t *sp = data;
4440e46d
AB		 1733 struct srb_iocb *abt = &sp->u.iocb_cmd;
1734
1735 abt->u.abt.comp_status = CS_TIMEOUT;
f6145e86 1736 sp->done(sp, QLA_FUNCTION_TIMEOUT);
4440e46d
AB		 1737}
1738
1739static void
25ff6af1 1740qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1741{
25ff6af1 1742 srb_t *sp = ptr;
4440e46d
AB		 1743 struct srb_iocb *abt = &sp->u.iocb_cmd;
1744
f6145e86
QT		 1745 if (del_timer(&sp->u.iocb_cmd.timer)) {
1746 if (sp->flags & SRB_WAKEUP_ON_COMP)
1747 complete(&abt->u.abt.comp);
1748 else
1749 sp->free(sp);
1750 }
4440e46d
AB		 1751}
1752
15f30a57 1753int
f6145e86 1754qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait)
4440e46d 1755{
25ff6af1 1756 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1757 struct srb_iocb *abt_iocb;
1758 srb_t *sp;
1759 int rval = QLA_FUNCTION_FAILED;
1760
49cecca7 1761 sp = qla2xxx_get_qpair_sp(cmd_sp->qpair, cmd_sp->fcport, GFP_KERNEL);
4440e46d
AB		 1762 if (!sp)
1763 goto done;
1764
1765 abt_iocb = &sp->u.iocb_cmd;
1766 sp->type = SRB_ABT_CMD;
1767 sp->name = "abort";
49cecca7 1768 sp->qpair = cmd_sp->qpair;
f6145e86
QT		 1769 if (wait)
1770 sp->flags = SRB_WAKEUP_ON_COMP;
e74e7d95
BH		 1771
1772 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1773 init_completion(&abt_iocb->u.abt.comp);
4440e46d 1774 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
e74e7d95 1775
4440e46d 1776 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
49cecca7 1777 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id);
b027a5ac 1778
4440e46d 1779 sp->done = qla24xx_abort_sp_done;
4440e46d
AB		 1780
1781 rval = qla2x00_start_sp(sp);
1782 if (rval != QLA_SUCCESS)
1783 goto done_free_sp;
1784
1785 ql_dbg(ql_dbg_async, vha, 0x507c,
49cecca7
QT		 1786 "Abort command issued - hdl=%x, type=%x\n",
1787 cmd_sp->handle, cmd_sp->type);
4440e46d 1788
f6145e86
QT		 1789 if (wait) {
1790 wait_for_completion(&abt_iocb->u.abt.comp);
1791 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1792 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1793 }
4440e46d
AB		 1794
1795done_free_sp:
25ff6af1 1796 sp->free(sp);
4440e46d
AB		 1797done:
1798 return rval;
1799}
1800
1801int
1802qla24xx_async_abort_command(srb_t *sp)
1803{
1804 unsigned long flags = 0;
1805
1806 uint32_t handle;
1807 fc_port_t *fcport = sp->fcport;
1808 struct scsi_qla_host *vha = fcport->vha;
1809 struct qla_hw_data *ha = vha->hw;
1810 struct req_que *req = vha->req;
1811
b027a5ac
DT		 1812 if (vha->flags.qpairs_available && sp->qpair)
1813 req = sp->qpair->req;
1814
4440e46d
AB		 1815 spin_lock_irqsave(&ha->hardware_lock, flags);
1816 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1817 if (req->outstanding_cmds[handle] == sp)
1818 break;
1819 }
1820 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1821 if (handle == req->num_outstanding_cmds) {
1822 /* Command not found. */
1823 return QLA_FUNCTION_FAILED;
1824 }
1825 if (sp->type == SRB_FXIOCB_DCMD)
1826 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1827 FXDISC_ABORT_IOCTL);
1828
f6145e86 1829 return qla24xx_async_abort_cmd(sp, true);
4440e46d
AB		 1830}
1831
a5d42f4c
DG		 1832static void
1833qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1834{
1835 switch (ea->data[0]) {
1836 case MBS_COMMAND_COMPLETE:
1837 ql_dbg(ql_dbg_disc, vha, 0x2118,
1838 "%s %d %8phC post gpdb\n",
1839 __func__, __LINE__, ea->fcport->port_name);
1840
1841 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1842 ea->fcport->logout_on_delete = 1;
1843 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1844 break;
1845 default:
1cbc0efc
DT		 1846 if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) &&
1847 (ea->iop[1] == 0x50000)) { /* reson 5=busy expl:0x0 */
1848 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1849 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP;
1850 break;
1851 }
1852
edd05de1
DG		 1853 if (ea->fcport->n2n_flag) {
1854 ql_dbg(ql_dbg_disc, vha, 0x2118,
1855 "%s %d %8phC post fc4 prli\n",
1856 __func__, __LINE__, ea->fcport->port_name);
1857 ea->fcport->fc4f_nvme = 0;
1858 ea->fcport->n2n_flag = 0;
1859 qla24xx_post_prli_work(vha, ea->fcport);
1860 }
a5d42f4c
DG		 1861 ql_dbg(ql_dbg_disc, vha, 0x2119,
1862 "%s %d %8phC unhandle event of %x\n",
1863 __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
1864 break;
1865 }
1866}
1867
726b8548
QT		 1868static void
1869qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1870{
726b8548 1871 port_id_t cid; /* conflict Nport id */
a084fd68
QT		 1872 u16 lid;
1873 struct fc_port *conflict_fcport;
82abdcaf 1874 unsigned long flags;
a4239945
QT		 1875 struct fc_port *fcport = ea->fcport;
1876
f352eeb7
QT		 1877 ql_dbg(ql_dbg_disc, vha, 0xffff,
1878 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
1879 __func__, fcport->port_name, fcport->disc_state,
1880 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
1881 ea->sp->gen2, fcport->rscn_gen|ea->sp->gen1,
1882 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
1883
a4239945
QT		 1884 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1885 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) {
1886 ql_dbg(ql_dbg_disc, vha, 0x20ea,
1887 "%s %d %8phC Remote is trying to login\n",
1888 __func__, __LINE__, fcport->port_name);
1889 return;
1890 }
1891
1892 if (fcport->disc_state == DSC_DELETE_PEND)
1893 return;
1894
1895 if (ea->sp->gen2 != fcport->login_gen) {
1896 /* target side must have changed it. */
1897 ql_dbg(ql_dbg_disc, vha, 0x20d3,
f352eeb7
QT		 1898 "%s %8phC generation changed\n",
1899 __func__, fcport->port_name);
1900 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
a4239945
QT		 1901 return;
1902 } else if (ea->sp->gen1 != fcport->rscn_gen) {
1903 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
1904 __func__, __LINE__, fcport->port_name);
1905 qla24xx_post_gidpn_work(vha, fcport);
1906 return;
1907 }
ac280b67 1908
726b8548 1909 switch (ea->data[0]) {
ac280b67 1910 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1911 /*
1912 * Driver must validate login state - If PRLI not complete,
1913 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1914 * requests.
1915 */
a5d42f4c
DG		 1916 if (ea->fcport->fc4f_nvme) {
1917 ql_dbg(ql_dbg_disc, vha, 0x2117,
1918 "%s %d %8phC post prli\n",
1919 __func__, __LINE__, ea->fcport->port_name);
1920 qla24xx_post_prli_work(vha, ea->fcport);
1921 } else {
1922 ql_dbg(ql_dbg_disc, vha, 0x20ea,
a084fd68
QT		 1923 "%s %d %8phC LoopID 0x%x in use with %06x. post gnl\n",
1924 __func__, __LINE__, ea->fcport->port_name,
1925 ea->fcport->loop_id, ea->fcport->d_id.b24);
1926
1927 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
82abdcaf 1928 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a5d42f4c
DG		 1929 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1930 ea->fcport->logout_on_delete = 1;
3515832c 1931 ea->fcport->send_els_logo = 0;
82abdcaf
QT		 1932 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP;
1933 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1934
a5d42f4c
DG		 1935 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1936 }
ac280b67
AV		 1937 break;
1938 case MBS_COMMAND_ERROR:
83548fe2 1939 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
726b8548
QT		 1940 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1941
1942 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1943 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1944 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1945 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1946 else
726b8548 1947 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1948 break;
1949 case MBS_LOOP_ID_USED:
726b8548
QT		 1950 /* data[1] = IO PARAM 1 = nport ID */
1951 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1952 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1953 cid.b.al_pa = ea->iop[1] & 0xff;
1954 cid.b.rsvd_1 = 0;
1955
83548fe2
QT		 1956 ql_dbg(ql_dbg_disc, vha, 0x20ec,
1957 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1958 __func__, __LINE__, ea->fcport->port_name,
1959 ea->fcport->loop_id);
726b8548
QT		 1960
1961 if (IS_SW_RESV_ADDR(cid)) {
1962 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1963 ea->fcport->loop_id = FC_NO_LOOP_ID;
1964 } else {
1965 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1966 }
726b8548
QT		 1967 qla24xx_post_gnl_work(vha, ea->fcport);
1968 break;
1969 case MBS_PORT_ID_USED:
83548fe2
QT		 1970 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1971 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1972 __func__, __LINE__, ea->fcport->port_name,
1973 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1974 ea->fcport->d_id.b.al_pa);
726b8548 1975
a084fd68
QT		 1976 lid = ea->iop[1] & 0xffff;
1977 qlt_find_sess_invalidate_other(vha,
1978 wwn_to_u64(ea->fcport->port_name),
1979 ea->fcport->d_id, lid, &conflict_fcport);
1980
1981 if (conflict_fcport) {
1982 /*
1983 * Another fcport share the same loop_id/nport id.
1984 * Conflict fcport needs to finish cleanup before this
1985 * fcport can proceed to login.
1986 */
1987 conflict_fcport->conflict = ea->fcport;
1988 ea->fcport->login_pause = 1;
1989
1990 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1991 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
1992 __func__, __LINE__, ea->fcport->port_name,
1993 ea->fcport->d_id.b24, lid);
1994 qla2x00_clear_loop_id(ea->fcport);
1995 qla24xx_post_gidpn_work(vha, ea->fcport);
1996 } else {
1997 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1998 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
1999 __func__, __LINE__, ea->fcport->port_name,
2000 ea->fcport->d_id.b24, lid);
2001
2002 qla2x00_clear_loop_id(ea->fcport);
2003 set_bit(lid, vha->hw->loop_id_map);
2004 ea->fcport->loop_id = lid;
2005 ea->fcport->keep_nport_handle = 0;
94cff6e1 2006 qlt_schedule_sess_for_deletion(ea->fcport);
a084fd68 2007 }
ac280b67
AV		 2008 break;
2009 }
4916392b 2010 return;
ac280b67
AV		 2011}
2012
4916392b 2013void
ac280b67
AV		 2014qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
2015 uint16_t *data)
2016{
a6ca8878 2017 qlt_logo_completion_handler(fcport, data[0]);
726b8548 2018 fcport->login_gen++;
fa83e658 2019 fcport->flags &= ~FCF_ASYNC_ACTIVE;
4916392b 2020 return;
ac280b67
AV		 2021}
2022
4916392b 2023void
5ff1d584
AV		 2024qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
2025 uint16_t *data)
2026{
fa83e658 2027 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
5ff1d584
AV		 2028 if (data[0] == MBS_COMMAND_COMPLETE) {
2029 qla2x00_update_fcport(vha, fcport);
2030
4916392b 2031 return;
5ff1d584
AV		 2032 }
2033
2034 /* Retry login. */
5ff1d584
AV		 2035 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
2036 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2037 else
80d79440 2038 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 2039
4916392b 2040 return;
5ff1d584
AV		 2041}
2042
1da177e4
LT		 2043/****************************************************************************/
2044/* QLogic ISP2x00 Hardware Support Functions. */
2045/****************************************************************************/
2046
fa492630 2047static int
7d613ac6
SV		 2048qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
2049{
2050 int rval = QLA_SUCCESS;
2051 struct qla_hw_data *ha = vha->hw;
2052 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 2053 uint16_t config[4];
7d613ac6
SV		 2054
2055 qla83xx_idc_lock(vha, 0);
2056
2057 /* SV: TODO: Assign initialization timeout from
2058 * flash-info / other param
2059 */
2060 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
2061 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
2062
2063 /* Set our fcoe function presence */
2064 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
2065 ql_dbg(ql_dbg_p3p, vha, 0xb077,
2066 "Error while setting DRV-Presence.\n");
2067 rval = QLA_FUNCTION_FAILED;
2068 goto exit;
2069 }
2070
2071 /* Decide the reset ownership */
2072 qla83xx_reset_ownership(vha);
2073
2074 /*
2075 * On first protocol driver load:
2076 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
2077 * register.
2078 * Others: Check compatibility with current IDC Major version.
2079 */
2080 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
2081 if (ha->flags.nic_core_reset_owner) {
2082 /* Set IDC Major version */
2083 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
2084 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
2085
2086 /* Clearing IDC-Lock-Recovery register */
2087 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
2088 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
2089 /*
2090 * Clear further IDC participation if we are not compatible with
2091 * the current IDC Major Version.
2092 */
2093 ql_log(ql_log_warn, vha, 0xb07d,
2094 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
2095 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
2096 __qla83xx_clear_drv_presence(vha);
2097 rval = QLA_FUNCTION_FAILED;
2098 goto exit;
2099 }
2100 /* Each function sets its supported Minor version. */
2101 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
2102 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
2103 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
2104
711aa7f7
SK		 2105 if (ha->flags.nic_core_reset_owner) {
2106 memset(config, 0, sizeof(config));
2107 if (!qla81xx_get_port_config(vha, config))
2108 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
2109 QLA8XXX_DEV_READY);
2110 }
2111
7d613ac6
SV		 2112 rval = qla83xx_idc_state_handler(vha);
2113
2114exit:
2115 qla83xx_idc_unlock(vha, 0);
2116
2117 return rval;
2118}
2119
1da177e4
LT		 2120/*
2121* qla2x00_initialize_adapter
2122* Initialize board.
2123*
2124* Input:
2125* ha = adapter block pointer.
2126*
2127* Returns:
2128* 0 = success
2129*/
2130int
e315cd28 2131qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 2132{
2133 int rval;
e315cd28 2134 struct qla_hw_data *ha = vha->hw;
73208dfd 2135 struct req_que *req = ha->req_q_map[0];
2533cf67 2136
fc90adaf
JC		 2137 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
2138 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
2139
1da177e4 2140 /* Clear adapter flags. */
e315cd28 2141 vha->flags.online = 0;
2533cf67 2142 ha->flags.chip_reset_done = 0;
e315cd28 2143 vha->flags.reset_active = 0;
85880801
AV		 2144 ha->flags.pci_channel_io_perm_failure = 0;
2145 ha->flags.eeh_busy = 0;
fabbb8df 2146 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 2147 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2148 atomic_set(&vha->loop_state, LOOP_DOWN);
2149 vha->device_flags = DFLG_NO_CABLE;
2150 vha->dpc_flags = 0;
2151 vha->flags.management_server_logged_in = 0;
2152 vha->marker_needed = 0;
1da177e4
LT		 2153 ha->isp_abort_cnt = 0;
2154 ha->beacon_blink_led = 0;
2155
73208dfd
AC		 2156 set_bit(0, ha->req_qid_map);
2157 set_bit(0, ha->rsp_qid_map);
2158
cfb0919c 2159 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 2160 "Configuring PCI space...\n");
e315cd28 2161 rval = ha->isp_ops->pci_config(vha);
1da177e4 2162 if (rval) {
7c3df132
SK		 2163 ql_log(ql_log_warn, vha, 0x0044,
2164 "Unable to configure PCI space.\n");
1da177e4
LT		 2165 return (rval);
2166 }
2167
e315cd28 2168 ha->isp_ops->reset_chip(vha);
1da177e4 2169
e315cd28 2170 rval = qla2xxx_get_flash_info(vha);
c00d8994 2171 if (rval) {
7c3df132
SK		 2172 ql_log(ql_log_fatal, vha, 0x004f,
2173 "Unable to validate FLASH data.\n");
7ec0effd
AD		 2174 return rval;
2175 }
2176
2177 if (IS_QLA8044(ha)) {
2178 qla8044_read_reset_template(vha);
2179
2180 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
2181 * If DONRESET_BIT0 is set, drivers should not set dev_state
2182 * to NEED_RESET. But if NEED_RESET is set, drivers should
2183 * should honor the reset. */
2184 if (ql2xdontresethba == 1)
2185 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 2186 }
2187
73208dfd 2188 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 2189 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 2190 "Configure NVRAM parameters...\n");
0107109e 2191
e315cd28 2192 ha->isp_ops->nvram_config(vha);
1da177e4 2193
d4c760c2
AV		 2194 if (ha->flags.disable_serdes) {
2195 /* Mask HBA via NVRAM settings? */
7c3df132 2196 ql_log(ql_log_info, vha, 0x0077,
7b833558 2197 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 2198 return QLA_FUNCTION_FAILED;
2199 }
2200
cfb0919c 2201 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 2202 "Verifying loaded RISC code...\n");
1da177e4 2203
e315cd28
AC		 2204 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
2205 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 2206 if (rval)
2207 return (rval);
e315cd28 2208 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 2209 if (rval)
2210 return (rval);
1da177e4 2211 }
a9083016 2212
4d4df193 2213 if (IS_QLA84XX(ha)) {
e315cd28 2214 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 2215 if (!ha->cs84xx) {
7c3df132 2216 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 2217 "Unable to configure ISP84XX.\n");
2218 return QLA_FUNCTION_FAILED;
2219 }
2220 }
2d70c103 2221
ead03855 2222 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 2223 rval = qla2x00_init_rings(vha);
2224
2533cf67 2225 ha->flags.chip_reset_done = 1;
1da177e4 2226
9a069e19 2227 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 2228 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 2229 rval = qla84xx_init_chip(vha);
2230 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2231 ql_log(ql_log_warn, vha, 0x00d4,
2232 "Unable to initialize ISP84XX.\n");
8d2b21db 2233 qla84xx_put_chip(vha);
9a069e19
GM		 2234 }
2235 }
2236
7d613ac6
SV		 2237 /* Load the NIC Core f/w if we are the first protocol driver. */
2238 if (IS_QLA8031(ha)) {
2239 rval = qla83xx_nic_core_fw_load(vha);
2240 if (rval)
2241 ql_log(ql_log_warn, vha, 0x0124,
2242 "Error in initializing NIC Core f/w.\n");
2243 }
2244
2f0f3f4f
MI		 2245 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
2246 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 2247
c46e65c7
JC		 2248 if (IS_P3P_TYPE(ha))
2249 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
2250 else
2251 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
2252
1da177e4
LT		 2253 return (rval);
2254}
2255
2256/**
abbd8870 2257 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
2db6228d 2258 * @vha: HA context
1da177e4
LT		 2259 *
2260 * Returns 0 on success.
2261 */
abbd8870 2262int
e315cd28 2263qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 2264{
a157b101 2265 uint16_t w;
abbd8870 2266 unsigned long flags;
e315cd28 2267 struct qla_hw_data *ha = vha->hw;
3d71644c 2268 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2269
1da177e4 2270 pci_set_master(ha->pdev);
af6177d8 2271 pci_try_set_mwi(ha->pdev);
1da177e4 2272
1da177e4 2273 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2274 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 2275 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2276
737faece 2277 pci_disable_rom(ha->pdev);
1da177e4
LT		 2278
2279 /* Get PCI bus information. */
2280 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2281 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 2282 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2283
abbd8870
AV		 2284 return QLA_SUCCESS;
2285}
1da177e4 2286
abbd8870
AV		 2287/**
2288 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
2db6228d 2289 * @vha: HA context
abbd8870
AV		 2290 *
2291 * Returns 0 on success.
2292 */
2293int
e315cd28 2294qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 2295{
a157b101 2296 uint16_t w;
abbd8870
AV		 2297 unsigned long flags = 0;
2298 uint32_t cnt;
e315cd28 2299 struct qla_hw_data *ha = vha->hw;
3d71644c 2300 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2301
abbd8870 2302 pci_set_master(ha->pdev);
af6177d8 2303 pci_try_set_mwi(ha->pdev);
1da177e4 2304
abbd8870 2305 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2306 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 2307
abbd8870
AV		 2308 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2309 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 2310 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 2311
abbd8870
AV		 2312 /*
2313 * If this is a 2300 card and not 2312, reset the
2314 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
2315 * the 2310 also reports itself as a 2300 so we need to get the
2316 * fb revision level -- a 6 indicates it really is a 2300 and
2317 * not a 2310.
2318 */
2319 if (IS_QLA2300(ha)) {
2320 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 2321
abbd8870 2322 /* Pause RISC. */
3d71644c 2323 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 2324 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2325 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 2326 break;
1da177e4 2327
abbd8870
AV		 2328 udelay(10);
2329 }
1da177e4 2330
abbd8870 2331 /* Select FPM registers. */
3d71644c
AV		 2332 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2333 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2334
2335 /* Get the fb rev level */
3d71644c 2336 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 2337
2338 if (ha->fb_rev == FPM_2300)
a157b101 2339 pci_clear_mwi(ha->pdev);
abbd8870
AV		 2340
2341 /* Deselect FPM registers. */
3d71644c
AV		 2342 WRT_REG_WORD(&reg->ctrl_status, 0x0);
2343 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2344
2345 /* Release RISC module. */
3d71644c 2346 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 2347 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2348 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 2349 break;
2350
2351 udelay(10);
1da177e4 2352 }
1da177e4 2353
abbd8870
AV		 2354 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2355 }
1da177e4 2356
abbd8870
AV		 2357 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2358
737faece 2359 pci_disable_rom(ha->pdev);
1da177e4 2360
abbd8870
AV		 2361 /* Get PCI bus information. */
2362 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2363 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2364 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2365
2366 return QLA_SUCCESS;
1da177e4
LT		 2367}
2368
0107109e
AV		 2369/**
2370 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
2db6228d 2371 * @vha: HA context
0107109e
AV		 2372 *
2373 * Returns 0 on success.
2374 */
2375int
e315cd28 2376qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 2377{
a157b101 2378 uint16_t w;
0107109e 2379 unsigned long flags = 0;
e315cd28 2380 struct qla_hw_data *ha = vha->hw;
0107109e 2381 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 2382
2383 pci_set_master(ha->pdev);
af6177d8 2384 pci_try_set_mwi(ha->pdev);
0107109e
AV		 2385
2386 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2387 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 2388 w &= ~PCI_COMMAND_INTX_DISABLE;
2389 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2390
2391 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2392
2393 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 2394 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
2395 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 2396
2397 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2398 if (pci_is_pcie(ha->pdev))
5ffd3a52 2399 pcie_set_readrq(ha->pdev, 4096);
0107109e 2400
737faece 2401 pci_disable_rom(ha->pdev);
0107109e 2402
44c10138 2403 ha->chip_revision = ha->pdev->revision;
a8488abe 2404
0107109e
AV		 2405 /* Get PCI bus information. */
2406 spin_lock_irqsave(&ha->hardware_lock, flags);
2407 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
2408 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2409
2410 return QLA_SUCCESS;
2411}
2412
c3a2f0df
AV		 2413/**
2414 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
2db6228d 2415 * @vha: HA context
c3a2f0df
AV		 2416 *
2417 * Returns 0 on success.
2418 */
2419int
e315cd28 2420qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 2421{
2422 uint16_t w;
e315cd28 2423 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 2424
2425 pci_set_master(ha->pdev);
2426 pci_try_set_mwi(ha->pdev);
2427
2428 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2429 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2430 w &= ~PCI_COMMAND_INTX_DISABLE;
2431 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2432
2433 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2434 if (pci_is_pcie(ha->pdev))
5ffd3a52 2435 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 2436
737faece 2437 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 2438
2439 ha->chip_revision = ha->pdev->revision;
2440
2441 return QLA_SUCCESS;
2442}
2443
1da177e4
LT		 2444/**
2445 * qla2x00_isp_firmware() - Choose firmware image.
2db6228d 2446 * @vha: HA context
1da177e4
LT		 2447 *
2448 * Returns 0 on success.
2449 */
2450static int
e315cd28 2451qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 2452{
2453 int rval;
42e421b1
AV		 2454 uint16_t loop_id, topo, sw_cap;
2455 uint8_t domain, area, al_pa;
e315cd28 2456 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2457
2458 /* Assume loading risc code */
fa2a1ce5 2459 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 2460
2461 if (ha->flags.disable_risc_code_load) {
7c3df132 2462 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 2463
2464 /* Verify checksum of loaded RISC code. */
e315cd28 2465 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 2466 if (rval == QLA_SUCCESS) {
2467 /* And, verify we are not in ROM code. */
e315cd28 2468 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 2469 &area, &domain, &topo, &sw_cap);
2470 }
1da177e4
LT		 2471 }
2472
7c3df132
SK		 2473 if (rval)
2474 ql_dbg(ql_dbg_init, vha, 0x007a,
2475 "**** Load RISC code ****.\n");
1da177e4
LT		 2476
2477 return (rval);
2478}
2479
2480/**
2481 * qla2x00_reset_chip() - Reset ISP chip.
2db6228d 2482 * @vha: HA context
1da177e4
LT		 2483 *
2484 * Returns 0 on success.
2485 */
abbd8870 2486void
e315cd28 2487qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 2488{
2489 unsigned long flags = 0;
e315cd28 2490 struct qla_hw_data *ha = vha->hw;
3d71644c 2491 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2492 uint32_t cnt;
1da177e4
LT		 2493 uint16_t cmd;
2494
85880801
AV		 2495 if (unlikely(pci_channel_offline(ha->pdev)))
2496 return;
2497
fd34f556 2498 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 2499
2500 spin_lock_irqsave(&ha->hardware_lock, flags);
2501
2502 /* Turn off master enable */
2503 cmd = 0;
2504 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2505 cmd &= ~PCI_COMMAND_MASTER;
2506 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2507
2508 if (!IS_QLA2100(ha)) {
2509 /* Pause RISC. */
2510 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2511 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2512 for (cnt = 0; cnt < 30000; cnt++) {
2513 if ((RD_REG_WORD(&reg->hccr) &
2514 HCCR_RISC_PAUSE) != 0)
2515 break;
2516 udelay(100);
2517 }
2518 } else {
2519 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2520 udelay(10);
2521 }
2522
2523 /* Select FPM registers. */
2524 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2525 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2526
2527 /* FPM Soft Reset. */
2528 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
2529 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2530
2531 /* Toggle Fpm Reset. */
2532 if (!IS_QLA2200(ha)) {
2533 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
2534 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2535 }
2536
2537 /* Select frame buffer registers. */
2538 WRT_REG_WORD(&reg->ctrl_status, 0x10);
2539 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2540
2541 /* Reset frame buffer FIFOs. */
2542 if (IS_QLA2200(ha)) {
2543 WRT_FB_CMD_REG(ha, reg, 0xa000);
2544 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2545 } else {
2546 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2547
2548 /* Read back fb_cmd until zero or 3 seconds max */
2549 for (cnt = 0; cnt < 3000; cnt++) {
2550 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2551 break;
2552 udelay(100);
2553 }
2554 }
2555
2556 /* Select RISC module registers. */
2557 WRT_REG_WORD(&reg->ctrl_status, 0);
2558 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2559
2560 /* Reset RISC processor. */
2561 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2562 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2563
2564 /* Release RISC processor. */
2565 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2566 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2567 }
2568
2569 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
2570 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
2571
2572 /* Reset ISP chip. */
2573 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2574
2575 /* Wait for RISC to recover from reset. */
2576 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2577 /*
2578 * It is necessary to for a delay here since the card doesn't
2579 * respond to PCI reads during a reset. On some architectures
2580 * this will result in an MCA.
2581 */
2582 udelay(20);
2583 for (cnt = 30000; cnt; cnt--) {
2584 if ((RD_REG_WORD(&reg->ctrl_status) &
2585 CSR_ISP_SOFT_RESET) == 0)
2586 break;
2587 udelay(100);
2588 }
2589 } else
2590 udelay(10);
2591
2592 /* Reset RISC processor. */
2593 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2594
2595 WRT_REG_WORD(&reg->semaphore, 0);
2596
2597 /* Release RISC processor. */
2598 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2599 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2600
2601 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2602 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 2603 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 2604 break;
1da177e4
LT		 2605
2606 udelay(100);
2607 }
2608 } else
2609 udelay(100);
2610
2611 /* Turn on master enable */
2612 cmd |= PCI_COMMAND_MASTER;
2613 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2614
2615 /* Disable RISC pause on FPM parity error. */
2616 if (!IS_QLA2100(ha)) {
2617 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2618 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2619 }
2620
2621 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2622}
2623
b1d46989
MI		 2624/**
2625 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2db6228d 2626 * @vha: HA context
b1d46989
MI		 2627 *
2628 * Returns 0 on success.
2629 */
fa492630 2630static int
b1d46989
MI		 2631qla81xx_reset_mpi(scsi_qla_host_t *vha)
2632{
2633 uint16_t mb[4] = {0x1010, 0, 1, 0};
2634
6246b8a1
GM		 2635 if (!IS_QLA81XX(vha->hw))
2636 return QLA_SUCCESS;
2637
b1d46989
MI		 2638 return qla81xx_write_mpi_register(vha, mb);
2639}
2640
0107109e 2641/**
88c26663 2642 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
2db6228d 2643 * @vha: HA context
0107109e
AV		 2644 *
2645 * Returns 0 on success.
2646 */
d14e72fb 2647static inline int
e315cd28 2648qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2649{
2650 unsigned long flags = 0;
e315cd28 2651 struct qla_hw_data *ha = vha->hw;
0107109e 2652 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2653 uint32_t cnt;
335a1cc9 2654 uint16_t wd;
b1d46989 2655 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2656 int rval = QLA_SUCCESS;
0107109e 2657
0107109e
AV		 2658 spin_lock_irqsave(&ha->hardware_lock, flags);
2659
2660 /* Reset RISC. */
2661 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2662 for (cnt = 0; cnt < 30000; cnt++) {
2663 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2664 break;
2665
2666 udelay(10);
2667 }
2668
d14e72fb
HM		 2669 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2670 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2671
2672 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2673 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2674 RD_REG_DWORD(&reg->hccr),
2675 RD_REG_DWORD(&reg->ctrl_status),
2676 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2677
0107109e
AV		 2678 WRT_REG_DWORD(&reg->ctrl_status,
2679 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2680 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2681
335a1cc9 2682 udelay(100);
d14e72fb 2683
88c26663 2684 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2685 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2686 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2687 rval == QLA_SUCCESS; cnt--) {
88c26663 2688 barrier();
d14e72fb
HM		 2689 if (cnt)
2690 udelay(5);
2691 else
2692 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2693 }
2694
d14e72fb
HM		 2695 if (rval == QLA_SUCCESS)
2696 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2697
2698 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2699 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2700 RD_REG_DWORD(&reg->hccr),
2701 RD_REG_DWORD(&reg->mailbox0));
2702
335a1cc9 2703 /* Wait for soft-reset to complete. */
52c82823 2704 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2705 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2706 barrier();
d14e72fb
HM		 2707 if ((RD_REG_DWORD(&reg->ctrl_status) &
2708 CSRX_ISP_SOFT_RESET) == 0)
2709 break;
2710
2711 udelay(5);
0107109e 2712 }
d14e72fb
HM		 2713 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2714 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2715
2716 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2717 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2718 RD_REG_DWORD(&reg->hccr),
2719 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2720
b1d46989
MI		 2721 /* If required, do an MPI FW reset now */
2722 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2723 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2724 if (++abts_cnt < 5) {
2725 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2726 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2727 } else {
2728 /*
2729 * We exhausted the ISP abort retries. We have to
2730 * set the board offline.
2731 */
2732 abts_cnt = 0;
2733 vha->flags.online = 0;
2734 }
2735 }
2736 }
2737
0107109e
AV		 2738 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2739 RD_REG_DWORD(&reg->hccr);
2740
2741 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2742 RD_REG_DWORD(&reg->hccr);
2743
2744 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2745 RD_REG_DWORD(&reg->hccr);
2746
52c82823 2747 RD_REG_WORD(&reg->mailbox0);
200ffb15 2748 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2749 rval == QLA_SUCCESS; cnt--) {
0107109e 2750 barrier();
d14e72fb
HM		 2751 if (cnt)
2752 udelay(5);
2753 else
2754 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2755 }
d14e72fb
HM		 2756 if (rval == QLA_SUCCESS)
2757 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2758
2759 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2760 "Host Risc 0x%x, mailbox0 0x%x\n",
2761 RD_REG_DWORD(&reg->hccr),
2762 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2763
2764 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2765
d14e72fb
HM		 2766 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2767 "Driver in %s mode\n",
2768 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2769
124f85e6
AV		 2770 if (IS_NOPOLLING_TYPE(ha))
2771 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2772
2773 return rval;
0107109e
AV		 2774}
2775
4ea2c9c7
JC		 2776static void
2777qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2778{
2779 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2780
2781 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2782 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2783
2784}
2785
2786static void
2787qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2788{
2789 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2790
2791 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2792 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2793}
2794
2795static void
2796qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2797{
4ea2c9c7
JC		 2798 uint32_t wd32 = 0;
2799 uint delta_msec = 100;
2800 uint elapsed_msec = 0;
2801 uint timeout_msec;
2802 ulong n;
2803
cc790764
JC		 2804 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2805 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2806 return;
2807
8dd7e3a5
JC		 2808 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2809 udelay(100);
2810
4ea2c9c7
JC		 2811attempt:
2812 timeout_msec = TIMEOUT_SEMAPHORE;
2813 n = timeout_msec / delta_msec;
2814 while (n--) {
2815 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2816 qla25xx_read_risc_sema_reg(vha, &wd32);
2817 if (wd32 & RISC_SEMAPHORE)
2818 break;
2819 msleep(delta_msec);
2820 elapsed_msec += delta_msec;
2821 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2822 goto force;
2823 }
2824
2825 if (!(wd32 & RISC_SEMAPHORE))
2826 goto force;
2827
2828 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2829 goto acquired;
2830
2831 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2832 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2833 n = timeout_msec / delta_msec;
2834 while (n--) {
2835 qla25xx_read_risc_sema_reg(vha, &wd32);
2836 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2837 break;
2838 msleep(delta_msec);
2839 elapsed_msec += delta_msec;
2840 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2841 goto force;
2842 }
2843
2844 if (wd32 & RISC_SEMAPHORE_FORCE)
2845 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2846
2847 goto attempt;
2848
2849force:
2850 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2851
2852acquired:
2853 return;
2854}
2855
88c26663
AV		 2856/**
2857 * qla24xx_reset_chip() - Reset ISP24xx chip.
2db6228d 2858 * @vha: HA context
88c26663
AV		 2859 *
2860 * Returns 0 on success.
2861 */
2862void
e315cd28 2863qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2864{
e315cd28 2865 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2866
2867 if (pci_channel_offline(ha->pdev) &&
2868 ha->flags.pci_channel_io_perm_failure) {
2869 return;
2870 }
2871
fd34f556 2872 ha->isp_ops->disable_intrs(ha);
88c26663 2873
4ea2c9c7
JC		 2874 qla25xx_manipulate_risc_semaphore(vha);
2875
88c26663 2876 /* Perform RISC reset. */
e315cd28 2877 qla24xx_reset_risc(vha);
88c26663
AV		 2878}
2879
1da177e4
LT		 2880/**
2881 * qla2x00_chip_diag() - Test chip for proper operation.
2db6228d 2882 * @vha: HA context
1da177e4
LT		 2883 *
2884 * Returns 0 on success.
2885 */
abbd8870 2886int
e315cd28 2887qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2888{
2889 int rval;
e315cd28 2890 struct qla_hw_data *ha = vha->hw;
3d71644c 2891 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2892 unsigned long flags = 0;
2893 uint16_t data;
2894 uint32_t cnt;
2895 uint16_t mb[5];
73208dfd 2896 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2897
2898 /* Assume a failed state */
2899 rval = QLA_FUNCTION_FAILED;
2900
da4704d9
BVA		 2901 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n",
2902 &reg->flash_address);
1da177e4
LT		 2903
2904 spin_lock_irqsave(&ha->hardware_lock, flags);
2905
2906 /* Reset ISP chip. */
2907 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2908
2909 /*
2910 * We need to have a delay here since the card will not respond while
2911 * in reset causing an MCA on some architectures.
2912 */
2913 udelay(20);
2914 data = qla2x00_debounce_register(&reg->ctrl_status);
2915 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2916 udelay(5);
2917 data = RD_REG_WORD(&reg->ctrl_status);
2918 barrier();
2919 }
2920
2921 if (!cnt)
2922 goto chip_diag_failed;
2923
7c3df132
SK		 2924 ql_dbg(ql_dbg_init, vha, 0x007c,
2925 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2926
2927 /* Reset RISC processor. */
2928 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2929 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2930
2931 /* Workaround for QLA2312 PCI parity error */
2932 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2933 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2934 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2935 udelay(5);
2936 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2937 barrier();
1da177e4
LT		 2938 }
2939 } else
2940 udelay(10);
2941
2942 if (!cnt)
2943 goto chip_diag_failed;
2944
2945 /* Check product ID of chip */
5a68a1c2 2946 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 2947
2948 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2949 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2950 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2951 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2952 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2953 mb[3] != PROD_ID_3) {
7c3df132
SK		 2954 ql_log(ql_log_warn, vha, 0x0062,
2955 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2956 mb[1], mb[2], mb[3]);
1da177e4
LT		 2957
2958 goto chip_diag_failed;
2959 }
2960 ha->product_id[0] = mb[1];
2961 ha->product_id[1] = mb[2];
2962 ha->product_id[2] = mb[3];
2963 ha->product_id[3] = mb[4];
2964
2965 /* Adjust fw RISC transfer size */
73208dfd 2966 if (req->length > 1024)
1da177e4
LT		 2967 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2968 else
2969 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2970 req->length;
1da177e4
LT		 2971
2972 if (IS_QLA2200(ha) &&
2973 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2974 /* Limit firmware transfer size with a 2200A */
7c3df132 2975 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2976
ea5b6382 2977 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2978 ha->fw_transfer_size = 128;
2979 }
2980
2981 /* Wrap Incoming Mailboxes Test. */
2982 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2983
7c3df132 2984 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2985 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2986 if (rval)
2987 ql_log(ql_log_warn, vha, 0x0080,
2988 "Failed mailbox send register test.\n");
2989 else
1da177e4
LT		 2990 /* Flag a successful rval */
2991 rval = QLA_SUCCESS;
1da177e4
LT		 2992 spin_lock_irqsave(&ha->hardware_lock, flags);
2993
2994chip_diag_failed:
2995 if (rval)
7c3df132
SK		 2996 ql_log(ql_log_info, vha, 0x0081,
2997 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 2998
2999 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3000
3001 return (rval);
3002}
3003
0107109e
AV		 3004/**
3005 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2db6228d 3006 * @vha: HA context
0107109e
AV		 3007 *
3008 * Returns 0 on success.
3009 */
3010int
e315cd28 3011qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 3012{
3013 int rval;
e315cd28 3014 struct qla_hw_data *ha = vha->hw;
73208dfd 3015 struct req_que *req = ha->req_q_map[0];
0107109e 3016
7ec0effd 3017 if (IS_P3P_TYPE(ha))
a9083016
GM		 3018 return QLA_SUCCESS;
3019
73208dfd 3020 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 3021
e315cd28 3022 rval = qla2x00_mbx_reg_test(vha);
0107109e 3023 if (rval) {
7c3df132
SK		 3024 ql_log(ql_log_warn, vha, 0x0082,
3025 "Failed mailbox send register test.\n");
0107109e
AV		 3026 } else {
3027 /* Flag a successful rval */
3028 rval = QLA_SUCCESS;
3029 }
3030
3031 return rval;
3032}
3033
ad0a0b01
QT		 3034static void
3035qla2x00_alloc_offload_mem(scsi_qla_host_t *vha)
0107109e 3036{
a7a167bf 3037 int rval;
df613b96
AV		 3038 dma_addr_t tc_dma;
3039 void *tc;
e315cd28 3040 struct qla_hw_data *ha = vha->hw;
a7a167bf 3041
ad0a0b01 3042 if (ha->eft) {
7c3df132 3043 ql_dbg(ql_dbg_init, vha, 0x00bd,
ad0a0b01
QT		 3044 "%s: Offload Mem is already allocated.\n",
3045 __func__);
a7a167bf
AV		 3046 return;
3047 }
d4e3e04d 3048
ad0a0b01 3049 if (IS_FWI2_CAPABLE(ha)) {
df613b96 3050 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 3051 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
3052 !IS_QLA27XX(ha))
436a7b11 3053 goto try_eft;
df613b96 3054
f73cb695
CD		 3055 if (ha->fce)
3056 dma_free_coherent(&ha->pdev->dev,
3057 FCE_SIZE, ha->fce, ha->fce_dma);
3058
3059 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 3060 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
3061 GFP_KERNEL);
df613b96 3062 if (!tc) {
7c3df132
SK		 3063 ql_log(ql_log_warn, vha, 0x00be,
3064 "Unable to allocate (%d KB) for FCE.\n",
3065 FCE_SIZE / 1024);
17d98630 3066 goto try_eft;
df613b96
AV		 3067 }
3068
e315cd28 3069 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 3070 ha->fce_mb, &ha->fce_bufs);
3071 if (rval) {
7c3df132
SK		 3072 ql_log(ql_log_warn, vha, 0x00bf,
3073 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 3074 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
3075 tc_dma);
3076 ha->flags.fce_enabled = 0;
17d98630 3077 goto try_eft;
df613b96 3078 }
cfb0919c 3079 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 3080 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 3081
df613b96
AV		 3082 ha->flags.fce_enabled = 1;
3083 ha->fce_dma = tc_dma;
3084 ha->fce = tc;
f73cb695 3085
436a7b11 3086try_eft:
f73cb695
CD		 3087 if (ha->eft)
3088 dma_free_coherent(&ha->pdev->dev,
3089 EFT_SIZE, ha->eft, ha->eft_dma);
3090
436a7b11 3091 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 3092 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
3093 GFP_KERNEL);
436a7b11 3094 if (!tc) {
7c3df132
SK		 3095 ql_log(ql_log_warn, vha, 0x00c1,
3096 "Unable to allocate (%d KB) for EFT.\n",
3097 EFT_SIZE / 1024);
ad0a0b01 3098 goto eft_err;
436a7b11
AV		 3099 }
3100
e315cd28 3101 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 3102 if (rval) {
7c3df132
SK		 3103 ql_log(ql_log_warn, vha, 0x00c2,
3104 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 3105 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
3106 tc_dma);
ad0a0b01 3107 goto eft_err;
436a7b11 3108 }
cfb0919c 3109 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 3110 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11 3111
436a7b11
AV		 3112 ha->eft_dma = tc_dma;
3113 ha->eft = tc;
d4e3e04d 3114 }
f73cb695 3115
ad0a0b01
QT		 3116eft_err:
3117 return;
3118}
3119
3120void
3121qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
3122{
3123 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
3124 eft_size, fce_size, mq_size;
3125 struct qla_hw_data *ha = vha->hw;
3126 struct req_que *req = ha->req_q_map[0];
3127 struct rsp_que *rsp = ha->rsp_q_map[0];
3128 struct qla2xxx_fw_dump *fw_dump;
3129
3130 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
3131 req_q_size = rsp_q_size = 0;
3132
3133 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3134 fixed_size = sizeof(struct qla2100_fw_dump);
3135 } else if (IS_QLA23XX(ha)) {
3136 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
3137 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
3138 sizeof(uint16_t);
3139 } else if (IS_FWI2_CAPABLE(ha)) {
3140 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3141 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
3142 else if (IS_QLA81XX(ha))
3143 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
3144 else if (IS_QLA25XX(ha))
3145 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
3146 else
3147 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
3148
3149 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
3150 sizeof(uint32_t);
3151 if (ha->mqenable) {
3152 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
3153 mq_size = sizeof(struct qla2xxx_mq_chain);
3154 /*
3155 * Allocate maximum buffer size for all queues.
3156 * Resizing must be done at end-of-dump processing.
3157 */
3158 mq_size += ha->max_req_queues *
3159 (req->length * sizeof(request_t));
3160 mq_size += ha->max_rsp_queues *
3161 (rsp->length * sizeof(response_t));
3162 }
3163 if (ha->tgt.atio_ring)
3164 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
3165 /* Allocate memory for Fibre Channel Event Buffer. */
3166 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
3167 !IS_QLA27XX(ha))
3168 goto try_eft;
3169
3170 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
3171try_eft:
3172 ql_dbg(ql_dbg_init, vha, 0x00c3,
3173 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
3174 eft_size = EFT_SIZE;
3175 }
3176
f73cb695
CD		 3177 if (IS_QLA27XX(ha)) {
3178 if (!ha->fw_dump_template) {
3179 ql_log(ql_log_warn, vha, 0x00ba,
3180 "Failed missing fwdump template\n");
3181 return;
3182 }
3183 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
3184 ql_dbg(ql_dbg_init, vha, 0x00fa,
3185 "-> allocating fwdump (%x bytes)...\n", dump_size);
3186 goto allocate;
3187 }
3188
73208dfd
AC		 3189 req_q_size = req->length * sizeof(request_t);
3190 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 3191 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 3192 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 3193 ha->chain_offset = dump_size;
3194 dump_size += mq_size + fce_size;
d4e3e04d 3195
b945e777
QT		 3196 if (ha->exchoffld_buf)
3197 dump_size += sizeof(struct qla2xxx_offld_chain) +
3198 ha->exchoffld_size;
3199 if (ha->exlogin_buf)
3200 dump_size += sizeof(struct qla2xxx_offld_chain) +
3201 ha->exlogin_size;
3202
f73cb695 3203allocate:
ad0a0b01
QT		 3204 if (!ha->fw_dump_len || dump_size != ha->fw_dump_len) {
3205 fw_dump = vmalloc(dump_size);
3206 if (!fw_dump) {
3207 ql_log(ql_log_warn, vha, 0x00c4,
3208 "Unable to allocate (%d KB) for firmware dump.\n",
3209 dump_size / 1024);
3210 } else {
3211 if (ha->fw_dump)
3212 vfree(ha->fw_dump);
3213 ha->fw_dump = fw_dump;
3214
3215 ha->fw_dump_len = dump_size;
3216 ql_dbg(ql_dbg_init, vha, 0x00c5,
3217 "Allocated (%d KB) for firmware dump.\n",
3218 dump_size / 1024);
3219
3220 if (IS_QLA27XX(ha))
3221 return;
3222
3223 ha->fw_dump->signature[0] = 'Q';
3224 ha->fw_dump->signature[1] = 'L';
3225 ha->fw_dump->signature[2] = 'G';
3226 ha->fw_dump->signature[3] = 'C';
3227 ha->fw_dump->version = htonl(1);
3228
3229 ha->fw_dump->fixed_size = htonl(fixed_size);
3230 ha->fw_dump->mem_size = htonl(mem_size);
3231 ha->fw_dump->req_q_size = htonl(req_q_size);
3232 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
3233
3234 ha->fw_dump->eft_size = htonl(eft_size);
3235 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
3236 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
3237
3238 ha->fw_dump->header_size =
3239 htonl(offsetof(struct qla2xxx_fw_dump, isp));
a7a167bf 3240 }
a7a167bf 3241 }
0107109e
AV		 3242}
3243
18e7555a
AV		 3244static int
3245qla81xx_mpi_sync(scsi_qla_host_t *vha)
3246{
3247#define MPS_MASK 0xe0
3248 int rval;
3249 uint16_t dc;
3250 uint32_t dw;
18e7555a
AV		 3251
3252 if (!IS_QLA81XX(vha->hw))
3253 return QLA_SUCCESS;
3254
3255 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
3256 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3257 ql_log(ql_log_warn, vha, 0x0105,
3258 "Unable to acquire semaphore.\n");
18e7555a
AV		 3259 goto done;
3260 }
3261
3262 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
3263 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
3264 if (rval != QLA_SUCCESS) {
7c3df132 3265 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 3266 goto done_release;
3267 }
3268
3269 dc &= MPS_MASK;
3270 if (dc == (dw & MPS_MASK))
3271 goto done_release;
3272
3273 dw &= ~MPS_MASK;
3274 dw |= dc;
3275 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
3276 if (rval != QLA_SUCCESS) {
7c3df132 3277 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 3278 }
3279
3280done_release:
3281 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
3282 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3283 ql_log(ql_log_warn, vha, 0x006d,
3284 "Unable to release semaphore.\n");
18e7555a
AV		 3285 }
3286
3287done:
3288 return rval;
3289}
3290
8d93f550
CD		 3291int
3292qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
3293{
3294 /* Don't try to reallocate the array */
3295 if (req->outstanding_cmds)
3296 return QLA_SUCCESS;
3297
d7459527 3298 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 3299 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
3300 else {
03e8c680
QT		 3301 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
3302 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 3303 else
03e8c680 3304 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 3305 }
3306
6396bb22
KC		 3307 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3308 sizeof(srb_t *),
3309 GFP_KERNEL);
8d93f550
CD		 3310
3311 if (!req->outstanding_cmds) {
3312 /*
3313 * Try to allocate a minimal size just so we can get through
3314 * initialization.
3315 */
3316 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
6396bb22
KC		 3317 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3318 sizeof(srb_t *),
3319 GFP_KERNEL);
8d93f550
CD		 3320
3321 if (!req->outstanding_cmds) {
3322 ql_log(ql_log_fatal, NULL, 0x0126,
3323 "Failed to allocate memory for "
3324 "outstanding_cmds for req_que %p.\n", req);
3325 req->num_outstanding_cmds = 0;
3326 return QLA_FUNCTION_FAILED;
3327 }
3328 }
3329
3330 return QLA_SUCCESS;
3331}
3332
e4e3a2ce
QT		 3333#define PRINT_FIELD(_field, _flag, _str) { \
3334 if (a0->_field & _flag) {\
3335 if (p) {\
3336 strcat(ptr, "|");\
3337 ptr++;\
3338 leftover--;\
3339 } \
3340 len = snprintf(ptr, leftover, "%s", _str); \
3341 p = 1;\
3342 leftover -= len;\
3343 ptr += len; \
3344 } \
3345}
3346
3347static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
3348{
3349#define STR_LEN 64
3350 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
3351 u8 str[STR_LEN], *ptr, p;
3352 int leftover, len;
3353
3354 memset(str, 0, STR_LEN);
3355 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
3356 ql_dbg(ql_dbg_init, vha, 0x015a,
3357 "SFP MFG Name: %s\n", str);
3358
3359 memset(str, 0, STR_LEN);
3360 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
3361 ql_dbg(ql_dbg_init, vha, 0x015c,
3362 "SFP Part Name: %s\n", str);
3363
3364 /* media */
3365 memset(str, 0, STR_LEN);
3366 ptr = str;
3367 leftover = STR_LEN;
3368 p = len = 0;
3369 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
3370 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
3371 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
3372 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
3373 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
3374 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
3375 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
3376 ql_dbg(ql_dbg_init, vha, 0x0160,
3377 "SFP Media: %s\n", str);
3378
3379 /* link length */
3380 memset(str, 0, STR_LEN);
3381 ptr = str;
3382 leftover = STR_LEN;
3383 p = len = 0;
3384 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
3385 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
3386 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
3387 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
3388 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
3389 ql_dbg(ql_dbg_init, vha, 0x0196,
3390 "SFP Link Length: %s\n", str);
3391
3392 memset(str, 0, STR_LEN);
3393 ptr = str;
3394 leftover = STR_LEN;
3395 p = len = 0;
3396 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
3397 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
3398 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
3399 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
3400 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
3401 ql_dbg(ql_dbg_init, vha, 0x016e,
3402 "SFP FC Link Tech: %s\n", str);
3403
3404 if (a0->length_km)
3405 ql_dbg(ql_dbg_init, vha, 0x016f,
3406 "SFP Distant: %d km\n", a0->length_km);
3407 if (a0->length_100m)
3408 ql_dbg(ql_dbg_init, vha, 0x0170,
3409 "SFP Distant: %d m\n", a0->length_100m*100);
3410 if (a0->length_50um_10m)
3411 ql_dbg(ql_dbg_init, vha, 0x0189,
3412 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
3413 if (a0->length_62um_10m)
3414 ql_dbg(ql_dbg_init, vha, 0x018a,
3415 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
3416 if (a0->length_om4_10m)
3417 ql_dbg(ql_dbg_init, vha, 0x0194,
3418 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
3419 if (a0->length_om3_10m)
3420 ql_dbg(ql_dbg_init, vha, 0x0195,
3421 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
3422}
3423
3424
3425/*
3426 * Return Code:
3427 * QLA_SUCCESS: no action
3428 * QLA_INTERFACE_ERROR: SFP is not there.
3429 * QLA_FUNCTION_FAILED: detected New SFP
3430 */
3431int
3432qla24xx_detect_sfp(scsi_qla_host_t *vha)
3433{
3434 int rc = QLA_SUCCESS;
3435 struct sff_8247_a0 *a;
3436 struct qla_hw_data *ha = vha->hw;
3437
3438 if (!AUTO_DETECT_SFP_SUPPORT(vha))
3439 goto out;
3440
3441 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
3442 if (rc)
3443 goto out;
3444
3445 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
3446 qla2xxx_print_sfp_info(vha);
3447
3448 if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
3449 /* long range */
3450 ha->flags.detected_lr_sfp = 1;
3451
3452 if (a->length_km > 5 || a->length_100m > 50)
3453 ha->long_range_distance = LR_DISTANCE_10K;
3454 else
3455 ha->long_range_distance = LR_DISTANCE_5K;
3456
3457 if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
3458 ql_dbg(ql_dbg_async, vha, 0x507b,
3459 "Detected Long Range SFP.\n");
3460 } else {
3461 /* short range */
3462 ha->flags.detected_lr_sfp = 0;
3463 if (ha->flags.using_lr_setting)
3464 ql_dbg(ql_dbg_async, vha, 0x5084,
3465 "Detected Short Range SFP.\n");
3466 }
3467
3468 if (!vha->flags.init_done)
3469 rc = QLA_SUCCESS;
3470out:
3471 return rc;
3472}
3473
1da177e4
LT		 3474/**
3475 * qla2x00_setup_chip() - Load and start RISC firmware.
2db6228d 3476 * @vha: HA context
1da177e4
LT		 3477 *
3478 * Returns 0 on success.
3479 */
3480static int
e315cd28 3481qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 3482{
0107109e
AV		 3483 int rval;
3484 uint32_t srisc_address = 0;
e315cd28 3485 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 3486 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3487 unsigned long flags;
dda772e8 3488 uint16_t fw_major_version;
3db0652e 3489
7ec0effd 3490 if (IS_P3P_TYPE(ha)) {
a9083016 3491 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 3492 if (rval == QLA_SUCCESS) {
3493 qla2x00_stop_firmware(vha);
a9083016 3494 goto enable_82xx_npiv;
14e303d9 3495 } else
b963752f 3496 goto failed;
a9083016
GM		 3497 }
3498
3db0652e
AV		 3499 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3500 /* Disable SRAM, Instruction RAM and GP RAM parity. */
3501 spin_lock_irqsave(&ha->hardware_lock, flags);
3502 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
3503 RD_REG_WORD(&reg->hccr);
3504 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3505 }
1da177e4 3506
18e7555a
AV		 3507 qla81xx_mpi_sync(vha);
3508
1da177e4 3509 /* Load firmware sequences */
e315cd28 3510 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 3511 if (rval == QLA_SUCCESS) {
7c3df132
SK		 3512 ql_dbg(ql_dbg_init, vha, 0x00c9,
3513 "Verifying Checksum of loaded RISC code.\n");
1da177e4 3514
e315cd28 3515 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 3516 if (rval == QLA_SUCCESS) {
3517 /* Start firmware execution. */
7c3df132
SK		 3518 ql_dbg(ql_dbg_init, vha, 0x00ca,
3519 "Starting firmware.\n");
1da177e4 3520
b0d6cabd
HM		 3521 if (ql2xexlogins)
3522 ha->flags.exlogins_enabled = 1;
3523
99e1b683 3524 if (qla_is_exch_offld_enabled(vha))
2f56a7f1
HM		 3525 ha->flags.exchoffld_enabled = 1;
3526
e315cd28 3527 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 3528 /* Retrieve firmware information. */
dda772e8 3529 if (rval == QLA_SUCCESS) {
e4e3a2ce
QT		 3530 qla24xx_detect_sfp(vha);
3531
b0d6cabd
HM		 3532 rval = qla2x00_set_exlogins_buffer(vha);
3533 if (rval != QLA_SUCCESS)
3534 goto failed;
3535
2f56a7f1
HM		 3536 rval = qla2x00_set_exchoffld_buffer(vha);
3537 if (rval != QLA_SUCCESS)
3538 goto failed;
3539
a9083016 3540enable_82xx_npiv:
dda772e8 3541 fw_major_version = ha->fw_major_version;
7ec0effd 3542 if (IS_P3P_TYPE(ha))
3173167f 3543 qla82xx_check_md_needed(vha);
6246b8a1
GM		 3544 else
3545 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 3546 if (rval != QLA_SUCCESS)
3547 goto failed;
2c3dfe3f 3548 ha->flags.npiv_supported = 0;
e315cd28 3549 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 3550 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 3551 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 3552 if ((!ha->max_npiv_vports) ||
3553 ((ha->max_npiv_vports + 1) %
eb66dc60 3554 MIN_MULTI_ID_FABRIC))
4d0ea247 3555 ha->max_npiv_vports =
eb66dc60 3556 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 3557 }
03e8c680 3558 qla2x00_get_resource_cnts(vha);
d743de66 3559
8d93f550
CD		 3560 /*
3561 * Allocate the array of outstanding commands
3562 * now that we know the firmware resources.
3563 */
3564 rval = qla2x00_alloc_outstanding_cmds(ha,
3565 vha->req);
3566 if (rval != QLA_SUCCESS)
3567 goto failed;
3568
ad0a0b01
QT		 3569 if (!fw_major_version && !(IS_P3P_TYPE(ha)))
3570 qla2x00_alloc_offload_mem(vha);
3571
3572 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
08de2844 3573 qla2x00_alloc_fw_dump(vha);
ad0a0b01 3574
3b6e5b9d
CD		 3575 } else {
3576 goto failed;
1da177e4
LT		 3577 }
3578 } else {
7c3df132
SK		 3579 ql_log(ql_log_fatal, vha, 0x00cd,
3580 "ISP Firmware failed checksum.\n");
3581 goto failed;
1da177e4 3582 }
c74d88a4
AV		 3583 } else
3584 goto failed;
1da177e4 3585
3db0652e
AV		 3586 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3587 /* Enable proper parity. */
3588 spin_lock_irqsave(&ha->hardware_lock, flags);
3589 if (IS_QLA2300(ha))
3590 /* SRAM parity */
3591 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
3592 else
3593 /* SRAM, Instruction RAM and GP RAM parity */
3594 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
3595 RD_REG_WORD(&reg->hccr);
3596 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3597 }
3598
f3982d89
CD		 3599 if (IS_QLA27XX(ha))
3600 ha->flags.fac_supported = 1;
3601 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 3602 uint32_t size;
3603
3604 rval = qla81xx_fac_get_sector_size(vha, &size);
3605 if (rval == QLA_SUCCESS) {
3606 ha->flags.fac_supported = 1;
3607 ha->fdt_block_size = size << 2;
3608 } else {
7c3df132 3609 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 3610 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3611 ha->fw_major_version, ha->fw_minor_version,
3612 ha->fw_subminor_version);
1ca60e3b 3613
f73cb695 3614 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 3615 ha->flags.fac_supported = 0;
3616 rval = QLA_SUCCESS;
3617 }
1d2874de
JC		 3618 }
3619 }
ca9e9c3e 3620failed:
1da177e4 3621 if (rval) {
7c3df132
SK		 3622 ql_log(ql_log_fatal, vha, 0x00cf,
3623 "Setup chip ****FAILED****.\n");
1da177e4
LT		 3624 }
3625
3626 return (rval);
3627}
3628
3629/**
3630 * qla2x00_init_response_q_entries() - Initializes response queue entries.
2db6228d 3631 * @rsp: response queue
1da177e4
LT		 3632 *
3633 * Beginning of request ring has initialization control block already built
3634 * by nvram config routine.
3635 *
3636 * Returns 0 on success.
3637 */
73208dfd
AC		 3638void
3639qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 3640{
3641 uint16_t cnt;
3642 response_t *pkt;
3643
2afa19a9
AC		 3644 rsp->ring_ptr = rsp->ring;
3645 rsp->ring_index = 0;
3646 rsp->status_srb = NULL;
e315cd28
AC		 3647 pkt = rsp->ring_ptr;
3648 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 3649 pkt->signature = RESPONSE_PROCESSED;
3650 pkt++;
3651 }
1da177e4
LT		 3652}
3653
3654/**
3655 * qla2x00_update_fw_options() - Read and process firmware options.
2db6228d 3656 * @vha: HA context
1da177e4
LT		 3657 *
3658 * Returns 0 on success.
3659 */
abbd8870 3660void
e315cd28 3661qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 3662{
3663 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 3664 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3665
3666 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 3667 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 3668
3669 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3670 return;
3671
3672 /* Serial Link options. */
7c3df132
SK		 3673 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3674 "Serial link options.\n");
3675 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
3676 (uint8_t *)&ha->fw_seriallink_options,
3677 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 3678
3679 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3680 if (ha->fw_seriallink_options[3] & BIT_2) {
3681 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3682
3683 /* 1G settings */
3684 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3685 emphasis = (ha->fw_seriallink_options[2] &
3686 (BIT_4 | BIT_3)) >> 3;
3687 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 3688 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3689 rx_sens = (ha->fw_seriallink_options[0] &
3690 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3691 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3692 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3693 if (rx_sens == 0x0)
3694 rx_sens = 0x3;
3695 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3696 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3697 ha->fw_options[10] |= BIT_5 |
3698 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3699 (tx_sens & (BIT_1 | BIT_0));
3700
3701 /* 2G settings */
3702 swing = (ha->fw_seriallink_options[2] &
3703 (BIT_7 | BIT_6 | BIT_5)) >> 5;
3704 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
3705 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 3706 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3707 rx_sens = (ha->fw_seriallink_options[1] &
3708 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3709 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
3710 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3711 if (rx_sens == 0x0)
3712 rx_sens = 0x3;
3713 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
3714 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3715 ha->fw_options[11] |= BIT_5 |
3716 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3717 (tx_sens & (BIT_1 | BIT_0));
3718 }
3719
3720 /* FCP2 options. */
3721 /* Return command IOCBs without waiting for an ABTS to complete. */
3722 ha->fw_options[3] |= BIT_13;
3723
3724 /* LED scheme. */
3725 if (ha->flags.enable_led_scheme)
3726 ha->fw_options[2] |= BIT_12;
3727
48c02fde 3728 /* Detect ISP6312. */
3729 if (IS_QLA6312(ha))
3730 ha->fw_options[2] |= BIT_13;
3731
088d09d4
GM		 3732 /* Set Retry FLOGI in case of P2P connection */
3733 if (ha->operating_mode == P2P) {
3734 ha->fw_options[2] |= BIT_3;
3735 ql_dbg(ql_dbg_disc, vha, 0x2100,
3736 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3737 __func__, ha->fw_options[2]);
3738 }
3739
1da177e4 3740 /* Update firmware options. */
e315cd28 3741 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 3742}
3743
0107109e 3744void
e315cd28 3745qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 3746{
3747 int rval;
e315cd28 3748 struct qla_hw_data *ha = vha->hw;
0107109e 3749
7ec0effd 3750 if (IS_P3P_TYPE(ha))
a9083016
GM		 3751 return;
3752
f198cafa
HM		 3753 /* Hold status IOCBs until ABTS response received. */
3754 if (ql2xfwholdabts)
3755 ha->fw_options[3] |= BIT_12;
3756
088d09d4
GM		 3757 /* Set Retry FLOGI in case of P2P connection */
3758 if (ha->operating_mode == P2P) {
3759 ha->fw_options[2] |= BIT_3;
3760 ql_dbg(ql_dbg_disc, vha, 0x2101,
3761 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3762 __func__, ha->fw_options[2]);
3763 }
3764
41dc529a 3765 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff
QT		 3766 if (ql2xmvasynctoatio &&
3767 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
41dc529a
QT		 3768 if (qla_tgt_mode_enabled(vha) ||
3769 qla_dual_mode_enabled(vha))
3770 ha->fw_options[2] |= BIT_11;
3771 else
3772 ha->fw_options[2] &= ~BIT_11;
3773 }
3774
f7e761f5
QT		 3775 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3776 /*
3777 * Tell FW to track each exchange to prevent
3778 * driver from using stale exchange.
3779 */
3780 if (qla_tgt_mode_enabled(vha) ||
3781 qla_dual_mode_enabled(vha))
3782 ha->fw_options[2] |= BIT_4;
3783 else
3784 ha->fw_options[2] &= ~BIT_4;
9ecf0b0d
QT		 3785
3786 /* Reserve 1/2 of emergency exchanges for ELS.*/
3787 if (qla2xuseresexchforels)
3788 ha->fw_options[2] |= BIT_8;
3789 else
3790 ha->fw_options[2] &= ~BIT_8;
f7e761f5
QT		 3791 }
3792
83548fe2
QT		 3793 ql_dbg(ql_dbg_init, vha, 0x00e8,
3794 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3795 __func__, ha->fw_options[1], ha->fw_options[2],
3796 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 3797
3798 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
3799 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 3800
0107109e 3801 /* Update Serial Link options. */
f94097ed 3802 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3803 return;
3804
e315cd28 3805 rval = qla2x00_set_serdes_params(vha,
f94097ed 3806 le16_to_cpu(ha->fw_seriallink_options24[1]),
3807 le16_to_cpu(ha->fw_seriallink_options24[2]),
3808 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3809 if (rval != QLA_SUCCESS) {
7c3df132 3810 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3811 "Unable to update Serial Link options (%x).\n", rval);
3812 }
3813}
3814
abbd8870 3815void
e315cd28 3816qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3817{
e315cd28 3818 struct qla_hw_data *ha = vha->hw;
3d71644c 3819 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3820 struct req_que *req = ha->req_q_map[0];
3821 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3822
3823 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3824 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3825 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3826 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3827 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
3828 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3829 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3830 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3831 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 3832
3833 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3834 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3835 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3836 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3837 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3838}
3839
0107109e 3840void
e315cd28 3841qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3842{
e315cd28 3843 struct qla_hw_data *ha = vha->hw;
118e2ef9 3844 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3845 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3846 struct qla_msix_entry *msix;
0107109e 3847 struct init_cb_24xx *icb;
73208dfd
AC		 3848 uint16_t rid = 0;
3849 struct req_que *req = ha->req_q_map[0];
3850 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3851
6246b8a1 3852 /* Setup ring parameters in initialization control block. */
0107109e 3853 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3854 icb->request_q_outpointer = cpu_to_le16(0);
3855 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3856 icb->request_q_length = cpu_to_le16(req->length);
3857 icb->response_q_length = cpu_to_le16(rsp->length);
3858 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3859 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3860 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3861 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3862
2d70c103 3863 /* Setup ATIO queue dma pointers for target mode */
ad950360 3864 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3865 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3866 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3867 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3868
7c6300e3 3869 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3870 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3871
f73cb695 3872 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3873 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3874 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3875 if (ha->flags.msix_enabled) {
3876 msix = &ha->msix_entries[1];
83548fe2 3877 ql_dbg(ql_dbg_init, vha, 0x0019,
7c3df132
SK		 3878 "Registering vector 0x%x for base que.\n",
3879 msix->entry);
73208dfd
AC		 3880 icb->msix = cpu_to_le16(msix->entry);
3881 }
3882 /* Use alternate PCI bus number */
3883 if (MSB(rid))
ad950360 3884 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3885 /* Use alternate PCI devfn */
3886 if (LSB(rid))
ad950360 3887 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3888
3155754a 3889 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3890 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3891 (ha->flags.msix_enabled)) {
ad950360 3892 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3893 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3894 ql_dbg(ql_dbg_init, vha, 0x00fe,
3895 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3896 } else {
ad950360 3897 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3898 }
ad950360 3899 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3900
3901 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3902 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3903 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3904 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3905 } else {
3906 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3907 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3908 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3909 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3910 }
aa230bc5 3911 qlt_24xx_config_rings(vha);
2d70c103 3912
73208dfd
AC		 3913 /* PCI posting */
3914 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3915}
3916
1da177e4
LT		 3917/**
3918 * qla2x00_init_rings() - Initializes firmware.
2db6228d 3919 * @vha: HA context
1da177e4
LT		 3920 *
3921 * Beginning of request ring has initialization control block already built
3922 * by nvram config routine.
3923 *
3924 * Returns 0 on success.
3925 */
8ae6d9c7 3926int
e315cd28 3927qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3928{
3929 int rval;
3930 unsigned long flags = 0;
29bdccbe 3931 int cnt, que;
e315cd28 3932 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3933 struct req_que *req;
3934 struct rsp_que *rsp;
2c3dfe3f
SJ		 3935 struct mid_init_cb_24xx *mid_init_cb =
3936 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3937
3938 spin_lock_irqsave(&ha->hardware_lock, flags);
3939
3940 /* Clear outstanding commands array. */
2afa19a9 3941 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3942 req = ha->req_q_map[que];
cb43285f 3943 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3944 continue;
7c6300e3
JC		 3945 req->out_ptr = (void *)(req->ring + req->length);
3946 *req->out_ptr = 0;
8d93f550 3947 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3948 req->outstanding_cmds[cnt] = NULL;
1da177e4 3949
2afa19a9 3950 req->current_outstanding_cmd = 1;
1da177e4 3951
29bdccbe
AC		 3952 /* Initialize firmware. */
3953 req->ring_ptr = req->ring;
3954 req->ring_index = 0;
3955 req->cnt = req->length;
3956 }
1da177e4 3957
2afa19a9 3958 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3959 rsp = ha->rsp_q_map[que];
cb43285f 3960 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3961 continue;
7c6300e3
JC		 3962 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3963 *rsp->in_ptr = 0;
29bdccbe 3964 /* Initialize response queue entries */
8ae6d9c7
GM		 3965 if (IS_QLAFX00(ha))
3966 qlafx00_init_response_q_entries(rsp);
3967 else
3968 qla2x00_init_response_q_entries(rsp);
29bdccbe 3969 }
1da177e4 3970
2d70c103
NB		 3971 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3972 ha->tgt.atio_ring_index = 0;
3973 /* Initialize ATIO queue entries */
3974 qlt_init_atio_q_entries(vha);
3975
e315cd28 3976 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3977
3978 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3979
8ae6d9c7
GM		 3980 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3981
3982 if (IS_QLAFX00(ha)) {
3983 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3984 goto next_check;
3985 }
3986
1da177e4 3987 /* Update any ISP specific firmware options before initialization. */
e315cd28 3988 ha->isp_ops->update_fw_options(vha);
1da177e4 3989
605aa2bc 3990 if (ha->flags.npiv_supported) {
45980cc2 3991 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 3992 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 3993 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 3994 }
3995
24a08138 3996 if (IS_FWI2_CAPABLE(ha)) {
ad950360 3997 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 3998 mid_init_cb->init_cb.execution_throttle =
03e8c680 3999 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 4000 ha->flags.dport_enabled =
4001 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
4002 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
4003 (ha->flags.dport_enabled) ? "enabled" : "disabled");
4004 /* FA-WWPN Status */
2486c627 4005 ha->flags.fawwpn_enabled =
40f3862b 4006 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
83548fe2 4007 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
2486c627 4008 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 4009 }
2c3dfe3f 4010
e315cd28 4011 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 4012next_check:
1da177e4 4013 if (rval) {
7c3df132
SK		 4014 ql_log(ql_log_fatal, vha, 0x00d2,
4015 "Init Firmware **** FAILED ****.\n");
1da177e4 4016 } else {
7c3df132
SK		 4017 ql_dbg(ql_dbg_init, vha, 0x00d3,
4018 "Init Firmware -- success.\n");
4b60c827 4019 QLA_FW_STARTED(ha);
1da177e4
LT		 4020 }
4021
4022 return (rval);
4023}
4024
4025/**
4026 * qla2x00_fw_ready() - Waits for firmware ready.
2db6228d 4027 * @vha: HA context
1da177e4
LT		 4028 *
4029 * Returns 0 on success.
4030 */
4031static int
e315cd28 4032qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 4033{
4034 int rval;
4d4df193 4035 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 4036 uint16_t min_wait; /* Minimum wait time if loop is down */
4037 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 4038 uint16_t state[6];
e315cd28 4039 struct qla_hw_data *ha = vha->hw;
1da177e4 4040
8ae6d9c7
GM		 4041 if (IS_QLAFX00(vha->hw))
4042 return qlafx00_fw_ready(vha);
4043
1da177e4
LT		 4044 rval = QLA_SUCCESS;
4045
33461491
CD		 4046 /* Time to wait for loop down */
4047 if (IS_P3P_TYPE(ha))
4048 min_wait = 30;
4049 else
4050 min_wait = 20;
1da177e4
LT		 4051
4052 /*
4053 * Firmware should take at most one RATOV to login, plus 5 seconds for
4054 * our own processing.
4055 */
4056 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
4057 wait_time = min_wait;
4058 }
4059
4060 /* Min wait time if loop down */
4061 mtime = jiffies + (min_wait * HZ);
4062
4063 /* wait time before firmware ready */
4064 wtime = jiffies + (wait_time * HZ);
4065
4066 /* Wait for ISP to finish LIP */
e315cd28 4067 if (!vha->flags.init_done)
7c3df132
SK		 4068 ql_log(ql_log_info, vha, 0x801e,
4069 "Waiting for LIP to complete.\n");
1da177e4
LT		 4070
4071 do {
5b939038 4072 memset(state, -1, sizeof(state));
e315cd28 4073 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 4074 if (rval == QLA_SUCCESS) {
4d4df193 4075 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 4076 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 4077 }
4d4df193 4078 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 4079 ql_dbg(ql_dbg_taskm, vha, 0x801f,
4080 "fw_state=%x 84xx=%x.\n", state[0],
4081 state[2]);
4d4df193
HK		 4082 if ((state[2] & FSTATE_LOGGED_IN) &&
4083 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 4084 ql_dbg(ql_dbg_taskm, vha, 0x8028,
4085 "Sending verify iocb.\n");
4d4df193
HK		 4086
4087 cs84xx_time = jiffies;
e315cd28 4088 rval = qla84xx_init_chip(vha);
7c3df132
SK		 4089 if (rval != QLA_SUCCESS) {
4090 ql_log(ql_log_warn,
cfb0919c 4091 vha, 0x8007,
7c3df132 4092 "Init chip failed.\n");
4d4df193 4093 break;
7c3df132 4094 }
4d4df193
HK		 4095
4096 /* Add time taken to initialize. */
4097 cs84xx_time = jiffies - cs84xx_time;
4098 wtime += cs84xx_time;
4099 mtime += cs84xx_time;
cfb0919c 4100 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 4101 "Increasing wait time by %ld. "
4102 "New time %ld.\n", cs84xx_time,
4103 wtime);
4d4df193
HK		 4104 }
4105 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 4106 ql_dbg(ql_dbg_taskm, vha, 0x8037,
4107 "F/W Ready - OK.\n");
1da177e4 4108
e315cd28 4109 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 4110 &ha->login_timeout, &ha->r_a_tov);
4111
4112 rval = QLA_SUCCESS;
4113 break;
4114 }
4115
4116 rval = QLA_FUNCTION_FAILED;
4117
e315cd28 4118 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 4119 state[0] != FSTATE_READY) {
1da177e4 4120 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 4121 * other than Wait for Login.
4122 */
1da177e4 4123 if (time_after_eq(jiffies, mtime)) {
7c3df132 4124 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 4125 "Cable is unplugged...\n");
4126
e315cd28 4127 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 4128 break;
4129 }
4130 }
4131 } else {
4132 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 4133 if (time_after_eq(jiffies, mtime) ||
7190575f 4134 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 4135 break;
4136 }
4137
4138 if (time_after_eq(jiffies, wtime))
4139 break;
4140
4141 /* Delay for a while */
4142 msleep(500);
1da177e4
LT		 4143 } while (1);
4144
7c3df132 4145 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 4146 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
4147 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 4148
cfb0919c 4149 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 4150 ql_log(ql_log_warn, vha, 0x803b,
4151 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 4152 }
4153
4154 return (rval);
4155}
4156
4157/*
4158* qla2x00_configure_hba
4159* Setup adapter context.
4160*
4161* Input:
4162* ha = adapter state pointer.
4163*
4164* Returns:
4165* 0 = success
4166*
4167* Context:
4168* Kernel context.
4169*/
4170static int
e315cd28 4171qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 4172{
4173 int rval;
4174 uint16_t loop_id;
4175 uint16_t topo;
2c3dfe3f 4176 uint16_t sw_cap;
1da177e4
LT		 4177 uint8_t al_pa;
4178 uint8_t area;
4179 uint8_t domain;
4180 char connect_type[22];
e315cd28 4181 struct qla_hw_data *ha = vha->hw;
61e1b269 4182 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 4183 port_id_t id;
9d1aa4e1 4184 unsigned long flags;
1da177e4
LT		 4185
4186 /* Get host addresses. */
e315cd28 4187 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 4188 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 4189 if (rval != QLA_SUCCESS) {
e315cd28 4190 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 4191 IS_CNA_CAPABLE(ha) ||
33135aa2 4192 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 4193 ql_dbg(ql_dbg_disc, vha, 0x2008,
4194 "Loop is in a transition state.\n");
33135aa2 4195 } else {
7c3df132
SK		 4196 ql_log(ql_log_warn, vha, 0x2009,
4197 "Unable to get host loop ID.\n");
61e1b269
JC		 4198 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
4199 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
4200 ql_log(ql_log_warn, vha, 0x1151,
4201 "Doing link init.\n");
4202 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
4203 return rval;
4204 }
e315cd28 4205 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 4206 }
1da177e4
LT		 4207 return (rval);
4208 }
4209
4210 if (topo == 4) {
7c3df132
SK		 4211 ql_log(ql_log_info, vha, 0x200a,
4212 "Cannot get topology - retrying.\n");
1da177e4
LT		 4213 return (QLA_FUNCTION_FAILED);
4214 }
4215
e315cd28 4216 vha->loop_id = loop_id;
1da177e4
LT		 4217
4218 /* initialize */
4219 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
4220 ha->operating_mode = LOOP;
2c3dfe3f 4221 ha->switch_cap = 0;
1da177e4
LT		 4222
4223 switch (topo) {
4224 case 0:
7c3df132 4225 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 4226 ha->current_topology = ISP_CFG_NL;
4227 strcpy(connect_type, "(Loop)");
4228 break;
4229
4230 case 1:
7c3df132 4231 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 4232 ha->switch_cap = sw_cap;
1da177e4
LT		 4233 ha->current_topology = ISP_CFG_FL;
4234 strcpy(connect_type, "(FL_Port)");
4235 break;
4236
4237 case 2:
7c3df132 4238 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 4239 ha->operating_mode = P2P;
4240 ha->current_topology = ISP_CFG_N;
4241 strcpy(connect_type, "(N_Port-to-N_Port)");
4242 break;
4243
4244 case 3:
7c3df132 4245 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 4246 ha->switch_cap = sw_cap;
1da177e4
LT		 4247 ha->operating_mode = P2P;
4248 ha->current_topology = ISP_CFG_F;
4249 strcpy(connect_type, "(F_Port)");
4250 break;
4251
4252 default:
7c3df132
SK		 4253 ql_dbg(ql_dbg_disc, vha, 0x200f,
4254 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 4255 ha->current_topology = ISP_CFG_NL;
4256 strcpy(connect_type, "(Loop)");
4257 break;
4258 }
4259
4260 /* Save Host port and loop ID. */
4261 /* byte order - Big Endian */
482c9dc7
QT		 4262 id.b.domain = domain;
4263 id.b.area = area;
4264 id.b.al_pa = al_pa;
4265 id.b.rsvd_1 = 0;
9d1aa4e1 4266 spin_lock_irqsave(&ha->hardware_lock, flags);
8777e431
QT		 4267 if (!(topo == 2 && ha->flags.n2n_bigger))
4268 qlt_update_host_map(vha, id);
9d1aa4e1 4269 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2d70c103 4270
e315cd28 4271 if (!vha->flags.init_done)
7c3df132
SK		 4272 ql_log(ql_log_info, vha, 0x2010,
4273 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 4274 connect_type, vha->loop_id);
1da177e4 4275
1da177e4
LT		 4276 return(rval);
4277}
4278
a9083016 4279inline void
e315cd28
AC		 4280qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
4281 char *def)
9bb9fcf2
AV		 4282{
4283 char *st, *en;
4284 uint16_t index;
e315cd28 4285 struct qla_hw_data *ha = vha->hw;
ab671149 4286 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 4287 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 4288
4289 if (memcmp(model, BINZERO, len) != 0) {
4290 strncpy(ha->model_number, model, len);
4291 st = en = ha->model_number;
4292 en += len - 1;
4293 while (en > st) {
4294 if (*en != 0x20 && *en != 0x00)
4295 break;
4296 *en-- = '\0';
4297 }
4298
4299 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4300 if (use_tbl &&
4301 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 4302 index < QLA_MODEL_NAMES)
1ee27146
JC		 4303 strncpy(ha->model_desc,
4304 qla2x00_model_name[index * 2 + 1],
4305 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4306 } else {
4307 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4308 if (use_tbl &&
4309 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 4310 index < QLA_MODEL_NAMES) {
4311 strcpy(ha->model_number,
4312 qla2x00_model_name[index * 2]);
1ee27146
JC		 4313 strncpy(ha->model_desc,
4314 qla2x00_model_name[index * 2 + 1],
4315 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4316 } else {
4317 strcpy(ha->model_number, def);
4318 }
4319 }
1ee27146 4320 if (IS_FWI2_CAPABLE(ha))
e315cd28 4321 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 4322 sizeof(ha->model_desc));
9bb9fcf2
AV		 4323}
4324
4e08df3f
DM		 4325/* On sparc systems, obtain port and node WWN from firmware
4326 * properties.
4327 */
e315cd28 4328static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 4329{
4330#ifdef CONFIG_SPARC
e315cd28 4331 struct qla_hw_data *ha = vha->hw;
4e08df3f 4332 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4333 struct device_node *dp = pci_device_to_OF_node(pdev);
4334 const u8 *val;
4e08df3f
DM		 4335 int len;
4336
4337 val = of_get_property(dp, "port-wwn", &len);
4338 if (val && len >= WWN_SIZE)
4339 memcpy(nv->port_name, val, WWN_SIZE);
4340
4341 val = of_get_property(dp, "node-wwn", &len);
4342 if (val && len >= WWN_SIZE)
4343 memcpy(nv->node_name, val, WWN_SIZE);
4344#endif
4345}
4346
1da177e4
LT		 4347/*
4348* NVRAM configuration for ISP 2xxx
4349*
4350* Input:
4351* ha = adapter block pointer.
4352*
4353* Output:
4354* initialization control block in response_ring
4355* host adapters parameters in host adapter block
4356*
4357* Returns:
4358* 0 = success.
4359*/
abbd8870 4360int
e315cd28 4361qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 4362{
4e08df3f 4363 int rval;
0107109e
AV		 4364 uint8_t chksum = 0;
4365 uint16_t cnt;
4366 uint8_t *dptr1, *dptr2;
e315cd28 4367 struct qla_hw_data *ha = vha->hw;
0107109e 4368 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 4369 nvram_t *nv = ha->nvram;
4370 uint8_t *ptr = ha->nvram;
3d71644c 4371 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4372
4e08df3f
DM		 4373 rval = QLA_SUCCESS;
4374
1da177e4 4375 /* Determine NVRAM starting address. */
0107109e 4376 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 4377 ha->nvram_base = 0;
4378 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
4379 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
4380 ha->nvram_base = 0x80;
4381
4382 /* Get NVRAM data and calculate checksum. */
e315cd28 4383 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 4384 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
4385 chksum += *ptr++;
1da177e4 4386
7c3df132
SK		 4387 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
4388 "Contents of NVRAM.\n");
4389 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
4390 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 4391
4392 /* Bad NVRAM data, set defaults parameters. */
4393 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
4394 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
4395 /* Reset NVRAM data. */
7c3df132 4396 ql_log(ql_log_warn, vha, 0x0064,
9e336520 4397 "Inconsistent NVRAM "
7c3df132
SK		 4398 "detected: checksum=0x%x id=%c version=0x%x.\n",
4399 chksum, nv->id[0], nv->nvram_version);
4400 ql_log(ql_log_warn, vha, 0x0065,
4401 "Falling back to "
4402 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 4403
4404 /*
4405 * Set default initialization control block.
4406 */
4407 memset(nv, 0, ha->nvram_size);
4408 nv->parameter_block_version = ICB_VERSION;
4409
4410 if (IS_QLA23XX(ha)) {
4411 nv->firmware_options[0] = BIT_2 | BIT_1;
4412 nv->firmware_options[1] = BIT_7 | BIT_5;
4413 nv->add_firmware_options[0] = BIT_5;
4414 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4415 nv->frame_payload_size = 2048;
4e08df3f
DM		 4416 nv->special_options[1] = BIT_7;
4417 } else if (IS_QLA2200(ha)) {
4418 nv->firmware_options[0] = BIT_2 | BIT_1;
4419 nv->firmware_options[1] = BIT_7 | BIT_5;
4420 nv->add_firmware_options[0] = BIT_5;
4421 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4422 nv->frame_payload_size = 1024;
4e08df3f
DM		 4423 } else if (IS_QLA2100(ha)) {
4424 nv->firmware_options[0] = BIT_3 | BIT_1;
4425 nv->firmware_options[1] = BIT_5;
98aee70d 4426 nv->frame_payload_size = 1024;
4e08df3f
DM		 4427 }
4428
ad950360
BVA		 4429 nv->max_iocb_allocation = cpu_to_le16(256);
4430 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 4431 nv->retry_count = 8;
4432 nv->retry_delay = 1;
4433
4434 nv->port_name[0] = 33;
4435 nv->port_name[3] = 224;
4436 nv->port_name[4] = 139;
4437
e315cd28 4438 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4439
4440 nv->login_timeout = 4;
4441
4442 /*
4443 * Set default host adapter parameters
4444 */
4445 nv->host_p[1] = BIT_2;
4446 nv->reset_delay = 5;
4447 nv->port_down_retry_count = 8;
ad950360 4448 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 4449 nv->link_down_timeout = 60;
4450
4451 rval = 1;
1da177e4
LT		 4452 }
4453
4454#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
4455 /*
4456 * The SN2 does not provide BIOS emulation which means you can't change
4457 * potentially bogus BIOS settings. Force the use of default settings
4458 * for link rate and frame size. Hope that the rest of the settings
4459 * are valid.
4460 */
4461 if (ia64_platform_is("sn2")) {
98aee70d 4462 nv->frame_payload_size = 2048;
1da177e4
LT		 4463 if (IS_QLA23XX(ha))
4464 nv->special_options[1] = BIT_7;
4465 }
4466#endif
4467
4468 /* Reset Initialization control block */
0107109e 4469 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 4470
4471 /*
4472 * Setup driver NVRAM options.
4473 */
4474 nv->firmware_options[0] |= (BIT_6 | BIT_1);
4475 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
4476 nv->firmware_options[1] |= (BIT_5 | BIT_0);
4477 nv->firmware_options[1] &= ~BIT_4;
4478
4479 if (IS_QLA23XX(ha)) {
4480 nv->firmware_options[0] |= BIT_2;
4481 nv->firmware_options[0] &= ~BIT_3;
2d70c103 4482 nv->special_options[0] &= ~BIT_6;
0107109e 4483 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 4484
4485 if (IS_QLA2300(ha)) {
4486 if (ha->fb_rev == FPM_2310) {
4487 strcpy(ha->model_number, "QLA2310");
4488 } else {
4489 strcpy(ha->model_number, "QLA2300");
4490 }
4491 } else {
e315cd28 4492 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 4493 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 4494 }
4495 } else if (IS_QLA2200(ha)) {
4496 nv->firmware_options[0] |= BIT_2;
4497 /*
4498 * 'Point-to-point preferred, else loop' is not a safe
4499 * connection mode setting.
4500 */
4501 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
4502 (BIT_5 | BIT_4)) {
4503 /* Force 'loop preferred, else point-to-point'. */
4504 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
4505 nv->add_firmware_options[0] |= BIT_5;
4506 }
4507 strcpy(ha->model_number, "QLA22xx");
4508 } else /*if (IS_QLA2100(ha))*/ {
4509 strcpy(ha->model_number, "QLA2100");
4510 }
4511
4512 /*
4513 * Copy over NVRAM RISC parameter block to initialization control block.
4514 */
4515 dptr1 = (uint8_t *)icb;
4516 dptr2 = (uint8_t *)&nv->parameter_block_version;
4517 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
4518 while (cnt--)
4519 *dptr1++ = *dptr2++;
4520
4521 /* Copy 2nd half. */
4522 dptr1 = (uint8_t *)icb->add_firmware_options;
4523 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4524 while (cnt--)
4525 *dptr1++ = *dptr2++;
0eaaca4c 4526 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
5341e868
AV		 4527 /* Use alternate WWN? */
4528 if (nv->host_p[1] & BIT_7) {
4529 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4530 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4531 }
4532
1da177e4
LT		 4533 /* Prepare nodename */
4534 if ((icb->firmware_options[1] & BIT_6) == 0) {
4535 /*
4536 * Firmware will apply the following mask if the nodename was
4537 * not provided.
4538 */
4539 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4540 icb->node_name[0] &= 0xF0;
4541 }
4542
4543 /*
4544 * Set host adapter parameters.
4545 */
3ce8866c
SK		 4546
4547 /*
4548 * BIT_7 in the host-parameters section allows for modification to
4549 * internal driver logging.
4550 */
0181944f 4551 if (nv->host_p[0] & BIT_7)
cfb0919c 4552 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 4553 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4554 /* Always load RISC code on non ISP2[12]00 chips. */
4555 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4556 ha->flags.disable_risc_code_load = 0;
4557 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4558 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4559 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 4560 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 4561 ha->flags.disable_serdes = 0;
1da177e4
LT		 4562
4563 ha->operating_mode =
4564 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4565
4566 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4567 sizeof(ha->fw_seriallink_options));
4568
4569 /* save HBA serial number */
4570 ha->serial0 = icb->port_name[5];
4571 ha->serial1 = icb->port_name[6];
4572 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4573 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4574 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 4575
ad950360 4576 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 4577
4578 ha->retry_count = nv->retry_count;
4579
4580 /* Set minimum login_timeout to 4 seconds. */
5b91490e 4581 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 4582 nv->login_timeout = ql2xlogintimeout;
4583 if (nv->login_timeout < 4)
4584 nv->login_timeout = 4;
4585 ha->login_timeout = nv->login_timeout;
1da177e4 4586
00a537b8
AV		 4587 /* Set minimum RATOV to 100 tenths of a second. */
4588 ha->r_a_tov = 100;
1da177e4 4589
1da177e4
LT		 4590 ha->loop_reset_delay = nv->reset_delay;
4591
1da177e4
LT		 4592 /* Link Down Timeout = 0:
4593 *
4594 * When Port Down timer expires we will start returning
4595 * I/O's to OS with "DID_NO_CONNECT".
4596 *
4597 * Link Down Timeout != 0:
4598 *
4599 * The driver waits for the link to come up after link down
4600 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 4601 */
1da177e4
LT		 4602 if (nv->link_down_timeout == 0) {
4603 ha->loop_down_abort_time =
354d6b21 4604 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 4605 } else {
4606 ha->link_down_timeout = nv->link_down_timeout;
4607 ha->loop_down_abort_time =
4608 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 4609 }
1da177e4 4610
1da177e4
LT		 4611 /*
4612 * Need enough time to try and get the port back.
4613 */
4614 ha->port_down_retry_count = nv->port_down_retry_count;
4615 if (qlport_down_retry)
4616 ha->port_down_retry_count = qlport_down_retry;
4617 /* Set login_retry_count */
4618 ha->login_retry_count = nv->retry_count;
4619 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4620 ha->port_down_retry_count > 3)
4621 ha->login_retry_count = ha->port_down_retry_count;
4622 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4623 ha->login_retry_count = ha->port_down_retry_count;
4624 if (ql2xloginretrycount)
4625 ha->login_retry_count = ql2xloginretrycount;
4626
ad950360 4627 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 4628 icb->command_resource_count = 0;
4629 icb->immediate_notify_resource_count = 0;
ad950360 4630 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 4631
4632 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4633 /* Enable RIO */
4634 icb->firmware_options[0] &= ~BIT_3;
4635 icb->add_firmware_options[0] &=
4636 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4637 icb->add_firmware_options[0] |= BIT_2;
4638 icb->response_accumulation_timer = 3;
4639 icb->interrupt_delay_timer = 5;
4640
e315cd28 4641 vha->flags.process_response_queue = 1;
1da177e4 4642 } else {
4fdfefe5 4643 /* Enable ZIO. */
e315cd28 4644 if (!vha->flags.init_done) {
4fdfefe5
AV		 4645 ha->zio_mode = icb->add_firmware_options[0] &
4646 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4647 ha->zio_timer = icb->interrupt_delay_timer ?
4648 icb->interrupt_delay_timer: 2;
4649 }
1da177e4
LT		 4650 icb->add_firmware_options[0] &=
4651 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 4652 vha->flags.process_response_queue = 0;
4fdfefe5 4653 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4654 ha->zio_mode = QLA_ZIO_MODE_6;
4655
7c3df132 4656 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 4657 "ZIO mode %d enabled; timer delay (%d us).\n",
4658 ha->zio_mode, ha->zio_timer * 100);
1da177e4 4659
4fdfefe5
AV		 4660 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4661 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 4662 vha->flags.process_response_queue = 1;
1da177e4
LT		 4663 }
4664 }
4665
4e08df3f 4666 if (rval) {
7c3df132
SK		 4667 ql_log(ql_log_warn, vha, 0x0069,
4668 "NVRAM configuration failed.\n");
4e08df3f
DM		 4669 }
4670 return (rval);
1da177e4
LT		 4671}
4672
19a7b4ae
JSEC		 4673static void
4674qla2x00_rport_del(void *data)
4675{
4676 fc_port_t *fcport = data;
d97994dc 4677 struct fc_rport *rport;
044d78e1 4678 unsigned long flags;
d97994dc 4679
044d78e1 4680 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 4681 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 4682 fcport->drport = NULL;
044d78e1 4683 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548 4684 if (rport) {
83548fe2
QT		 4685 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4686 "%s %8phN. rport %p roles %x\n",
4687 __func__, fcport->port_name, rport,
4688 rport->roles);
726b8548 4689
d97994dc 4690 fc_remote_port_delete(rport);
726b8548 4691 }
19a7b4ae
JSEC		 4692}
4693
1da177e4
LT		 4694/**
4695 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2db6228d 4696 * @vha: HA context
1da177e4
LT		 4697 * @flags: allocation flags
4698 *
4699 * Returns a pointer to the allocated fcport, or NULL, if none available.
4700 */
9a069e19 4701fc_port_t *
e315cd28 4702qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 4703{
4704 fc_port_t *fcport;
4705
bbfbbbc1
MK		 4706 fcport = kzalloc(sizeof(fc_port_t), flags);
4707 if (!fcport)
4708 return NULL;
1da177e4
LT		 4709
4710 /* Setup fcport template structure. */
e315cd28 4711 fcport->vha = vha;
1da177e4
LT		 4712 fcport->port_type = FCT_UNKNOWN;
4713 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 4714 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 4715 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 4716
726b8548
QT		 4717 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
4718 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 4719 flags);
726b8548
QT		 4720 fcport->disc_state = DSC_DELETED;
4721 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4722 fcport->deleted = QLA_SESS_DELETED;
4723 fcport->login_retry = vha->hw->login_retry_count;
726b8548
QT		 4724 fcport->logout_on_delete = 1;
4725
4726 if (!fcport->ct_desc.ct_sns) {
83548fe2 4727 ql_log(ql_log_warn, vha, 0xd049,
726b8548
QT		 4728 "Failed to allocate ct_sns request.\n");
4729 kfree(fcport);
4730 fcport = NULL;
4731 }
4732 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
cd4ed6b4 4733 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn);
726b8548
QT		 4734 INIT_LIST_HEAD(&fcport->gnl_entry);
4735 INIT_LIST_HEAD(&fcport->list);
4736
bbfbbbc1 4737 return fcport;
1da177e4
LT		 4738}
4739
726b8548
QT		 4740void
4741qla2x00_free_fcport(fc_port_t *fcport)
4742{
4743 if (fcport->ct_desc.ct_sns) {
4744 dma_free_coherent(&fcport->vha->hw->pdev->dev,
4745 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
4746 fcport->ct_desc.ct_sns_dma);
4747
4748 fcport->ct_desc.ct_sns = NULL;
4749 }
4750 kfree(fcport);
4751}
4752
1da177e4
LT		 4753/*
4754 * qla2x00_configure_loop
4755 * Updates Fibre Channel Device Database with what is actually on loop.
4756 *
4757 * Input:
4758 * ha = adapter block pointer.
4759 *
4760 * Returns:
4761 * 0 = success.
4762 * 1 = error.
4763 * 2 = database was full and device was not configured.
4764 */
4765static int
e315cd28 4766qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4767{
4768 int rval;
4769 unsigned long flags, save_flags;
e315cd28 4770 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4771 rval = QLA_SUCCESS;
4772
4773 /* Get Initiator ID */
e315cd28
AC		 4774 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
4775 rval = qla2x00_configure_hba(vha);
1da177e4 4776 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4777 ql_dbg(ql_dbg_disc, vha, 0x2013,
4778 "Unable to configure HBA.\n");
1da177e4
LT		 4779 return (rval);
4780 }
4781 }
4782
e315cd28 4783 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 4784 ql_dbg(ql_dbg_disc, vha, 0x2014,
4785 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 4786
4787 /*
4788 * If we have both an RSCN and PORT UPDATE pending then handle them
4789 * both at the same time.
4790 */
e315cd28
AC		 4791 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4792 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 4793
3064ff39
MH		 4794 qla2x00_get_data_rate(vha);
4795
1da177e4
LT		 4796 /* Determine what we need to do */
4797 if (ha->current_topology == ISP_CFG_FL &&
4798 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4799
1da177e4
LT		 4800 set_bit(RSCN_UPDATE, &flags);
4801
4802 } else if (ha->current_topology == ISP_CFG_F &&
4803 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4804
1da177e4
LT		 4805 set_bit(RSCN_UPDATE, &flags);
4806 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4807
4808 } else if (ha->current_topology == ISP_CFG_N) {
4809 clear_bit(RSCN_UPDATE, &flags);
48acad09
QT		 4810 if (qla_tgt_mode_enabled(vha)) {
4811 /* allow the other side to start the login */
9cd883f0
QT		 4812 clear_bit(LOCAL_LOOP_UPDATE, &flags);
4813 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
9cd883f0 4814 }
41dc529a
QT		 4815 } else if (ha->current_topology == ISP_CFG_NL) {
4816 clear_bit(RSCN_UPDATE, &flags);
4817 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4818 } else if (!vha->flags.online ||
1da177e4 4819 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 4820 set_bit(RSCN_UPDATE, &flags);
4821 set_bit(LOCAL_LOOP_UPDATE, &flags);
4822 }
4823
4824 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 4825 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
4826 ql_dbg(ql_dbg_disc, vha, 0x2015,
4827 "Loop resync needed, failing.\n");
1da177e4 4828 rval = QLA_FUNCTION_FAILED;
642ef983 4829 } else
e315cd28 4830 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 4831 }
4832
4833 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132 4834 if (LOOP_TRANSITION(vha)) {
83548fe2 4835 ql_dbg(ql_dbg_disc, vha, 0x2099,
7c3df132 4836 "Needs RSCN update and loop transition.\n");
1da177e4 4837 rval = QLA_FUNCTION_FAILED;
7c3df132 4838 }
e315cd28
AC		 4839 else
4840 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 4841 }
4842
4843 if (rval == QLA_SUCCESS) {
e315cd28
AC		 4844 if (atomic_read(&vha->loop_down_timer) ||
4845 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4846 rval = QLA_FUNCTION_FAILED;
4847 } else {
e315cd28 4848 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4849 ql_dbg(ql_dbg_disc, vha, 0x2069,
4850 "LOOP READY.\n");
ec7193e2 4851 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 4852
4853 /*
4854 * Process any ATIO queue entries that came in
4855 * while we weren't online.
4856 */
ead03855
QT		 4857 if (qla_tgt_mode_enabled(vha) ||
4858 qla_dual_mode_enabled(vha)) {
3bb67df5
DKU		 4859 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
4860 spin_lock_irqsave(&ha->tgt.atio_lock,
4861 flags);
4862 qlt_24xx_process_atio_queue(vha, 0);
4863 spin_unlock_irqrestore(
4864 &ha->tgt.atio_lock, flags);
4865 } else {
4866 spin_lock_irqsave(&ha->hardware_lock,
4867 flags);
4868 qlt_24xx_process_atio_queue(vha, 1);
4869 spin_unlock_irqrestore(
4870 &ha->hardware_lock, flags);
4871 }
4872 }
1da177e4
LT		 4873 }
4874 }
4875
4876 if (rval) {
7c3df132
SK		 4877 ql_dbg(ql_dbg_disc, vha, 0x206a,
4878 "%s *** FAILED ***.\n", __func__);
1da177e4 4879 } else {
7c3df132
SK		 4880 ql_dbg(ql_dbg_disc, vha, 0x206b,
4881 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4882 }
4883
cc3ef7bc 4884 /* Restore state if a resync event occurred during processing */
e315cd28 4885 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4886 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4887 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4888 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4889 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4890 }
1da177e4
LT		 4891 }
4892
4893 return (rval);
4894}
4895
1da177e4
LT		 4896/*
4897 * qla2x00_configure_local_loop
4898 * Updates Fibre Channel Device Database with local loop devices.
4899 *
4900 * Input:
4901 * ha = adapter block pointer.
4902 *
4903 * Returns:
4904 * 0 = success.
4905 */
4906static int
e315cd28 4907qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4908{
4909 int rval, rval2;
4910 int found_devs;
4911 int found;
4912 fc_port_t *fcport, *new_fcport;
4913
4914 uint16_t index;
4915 uint16_t entries;
4916 char *id_iter;
4917 uint16_t loop_id;
4918 uint8_t domain, area, al_pa;
e315cd28 4919 struct qla_hw_data *ha = vha->hw;
41dc529a 4920 unsigned long flags;
1da177e4 4921
8777e431
QT		 4922 /* Inititae N2N login. */
4923 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) {
4924 /* borrowing */
4925 u32 *bp, i, sz;
4926
4927 memset(ha->init_cb, 0, ha->init_cb_size);
4928 sz = min_t(int, sizeof(struct els_plogi_payload),
4929 ha->init_cb_size);
4930 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma,
4931 (void *)ha->init_cb, sz);
4932 if (rval == QLA_SUCCESS) {
4933 bp = (uint32_t *)ha->init_cb;
4934 for (i = 0; i < sz/4 ; i++, bp++)
4935 *bp = cpu_to_be32(*bp);
4936
4937 memcpy(&ha->plogi_els_payld.data, (void *)ha->init_cb,
4938 sizeof(ha->plogi_els_payld.data));
4939 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4940 } else {
4941 ql_dbg(ql_dbg_init, vha, 0x00d1,
4942 "PLOGI ELS param read fail.\n");
4943 }
4944 return QLA_SUCCESS;
4945 }
4946
1da177e4
LT		 4947 found_devs = 0;
4948 new_fcport = NULL;
642ef983 4949 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4950
1da177e4 4951 /* Get list of logged in devices. */
642ef983 4952 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4953 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4954 &entries);
4955 if (rval != QLA_SUCCESS)
4956 goto cleanup_allocation;
4957
83548fe2 4958 ql_dbg(ql_dbg_disc, vha, 0x2011,
7c3df132
SK		 4959 "Entries in ID list (%d).\n", entries);
4960 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4961 (uint8_t *)ha->gid_list,
4962 entries * sizeof(struct gid_list_info));
1da177e4 4963
9cd883f0
QT		 4964 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4965 fcport->scan_state = QLA_FCPORT_SCAN;
4966 }
4967
1da177e4 4968 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4969 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4970 if (new_fcport == NULL) {
83548fe2 4971 ql_log(ql_log_warn, vha, 0x2012,
7c3df132 4972 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4973 rval = QLA_MEMORY_ALLOC_FAILED;
4974 goto cleanup_allocation;
4975 }
4976 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4977
1da177e4
LT		 4978 /* Add devices to port list. */
4979 id_iter = (char *)ha->gid_list;
4980 for (index = 0; index < entries; index++) {
4981 domain = ((struct gid_list_info *)id_iter)->domain;
4982 area = ((struct gid_list_info *)id_iter)->area;
4983 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4984 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4985 loop_id = (uint16_t)
4986 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4987 else
1da177e4
LT		 4988 loop_id = le16_to_cpu(
4989 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4990 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4991
4992 /* Bypass reserved domain fields. */
4993 if ((domain & 0xf0) == 0xf0)
4994 continue;
4995
4996 /* Bypass if not same domain and area of adapter. */
f7d289f6 4997 if (area && domain &&
e315cd28 4998 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4999 continue;
5000
5001 /* Bypass invalid local loop ID. */
5002 if (loop_id > LAST_LOCAL_LOOP_ID)
5003 continue;
5004
41dc529a 5005 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 5006
1da177e4
LT		 5007 /* Fill in member data. */
5008 new_fcport->d_id.b.domain = domain;
5009 new_fcport->d_id.b.area = area;
5010 new_fcport->d_id.b.al_pa = al_pa;
5011 new_fcport->loop_id = loop_id;
9cd883f0 5012 new_fcport->scan_state = QLA_FCPORT_FOUND;
41dc529a 5013
e315cd28 5014 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 5015 if (rval2 != QLA_SUCCESS) {
83548fe2 5016 ql_dbg(ql_dbg_disc, vha, 0x2097,
7c3df132
SK		 5017 "Failed to retrieve fcport information "
5018 "-- get_port_database=%x, loop_id=0x%04x.\n",
5019 rval2, new_fcport->loop_id);
edd05de1
DG		 5020 /* Skip retry if N2N */
5021 if (ha->current_topology != ISP_CFG_N) {
5022 ql_dbg(ql_dbg_disc, vha, 0x2105,
5023 "Scheduling resync.\n");
5024 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5025 continue;
5026 }
1da177e4
LT		 5027 }
5028
41dc529a 5029 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 5030 /* Check for matching device in port list. */
5031 found = 0;
5032 fcport = NULL;
e315cd28 5033 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5034 if (memcmp(new_fcport->port_name, fcport->port_name,
5035 WWN_SIZE))
5036 continue;
5037
ddb9b126 5038 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 5039 fcport->loop_id = new_fcport->loop_id;
5040 fcport->port_type = new_fcport->port_type;
5041 fcport->d_id.b24 = new_fcport->d_id.b24;
5042 memcpy(fcport->node_name, new_fcport->node_name,
5043 WWN_SIZE);
9cd883f0 5044 fcport->scan_state = QLA_FCPORT_FOUND;
1da177e4
LT		 5045 found++;
5046 break;
5047 }
5048
5049 if (!found) {
5050 /* New device, add to fcports list. */
e315cd28 5051 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 5052
5053 /* Allocate a new replacement fcport. */
5054 fcport = new_fcport;
41dc529a
QT		 5055
5056 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5057
e315cd28 5058 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 5059
1da177e4 5060 if (new_fcport == NULL) {
83548fe2 5061 ql_log(ql_log_warn, vha, 0xd031,
7c3df132 5062 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5063 rval = QLA_MEMORY_ALLOC_FAILED;
5064 goto cleanup_allocation;
5065 }
41dc529a 5066 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 5067 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5068 }
5069
41dc529a
QT		 5070 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5071
d8b45213 5072 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 5073 fcport->fp_speed = ha->link_data_rate;
d8b45213 5074
1da177e4
LT		 5075 found_devs++;
5076 }
5077
9cd883f0
QT		 5078 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5079 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5080 break;
5081
5082 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5083 if ((qla_dual_mode_enabled(vha) ||
5084 qla_ini_mode_enabled(vha)) &&
5085 atomic_read(&fcport->state) == FCS_ONLINE) {
5086 qla2x00_mark_device_lost(vha, fcport,
5087 ql2xplogiabsentdevice, 0);
5088 if (fcport->loop_id != FC_NO_LOOP_ID &&
5089 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5090 fcport->port_type != FCT_INITIATOR &&
5091 fcport->port_type != FCT_BROADCAST) {
5092 ql_dbg(ql_dbg_disc, vha, 0x20f0,
5093 "%s %d %8phC post del sess\n",
5094 __func__, __LINE__,
5095 fcport->port_name);
5096
d8630bb9 5097 qlt_schedule_sess_for_deletion(fcport);
9cd883f0
QT		 5098 continue;
5099 }
5100 }
5101 }
5102
5103 if (fcport->scan_state == QLA_FCPORT_FOUND)
5104 qla24xx_fcport_handle_login(vha, fcport);
5105 }
5106
1da177e4 5107cleanup_allocation:
c9475cb0 5108 kfree(new_fcport);
1da177e4
LT		 5109
5110 if (rval != QLA_SUCCESS) {
83548fe2 5111 ql_dbg(ql_dbg_disc, vha, 0x2098,
7c3df132 5112 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 5113 }
5114
1da177e4
LT		 5115 return (rval);
5116}
5117
d8b45213 5118static void
e315cd28 5119qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 5120{
d8b45213 5121 int rval;
93f2bd67 5122 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5123 struct qla_hw_data *ha = vha->hw;
d8b45213 5124
c76f2c01 5125 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 5126 return;
5127
c9afb9a2
GM		 5128 if (atomic_read(&fcport->state) != FCS_ONLINE)
5129 return;
5130
39bd9622 5131 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
413c2f33
HM		 5132 fcport->fp_speed > ha->link_data_rate ||
5133 !ha->flags.gpsc_supported)
d8b45213
AV		 5134 return;
5135
e315cd28 5136 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 5137 mb);
d8b45213 5138 if (rval != QLA_SUCCESS) {
7c3df132 5139 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 5140 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
5141 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 5142 } else {
7c3df132 5143 ql_dbg(ql_dbg_disc, vha, 0x2005,
33b28357 5144 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n",
d0297c9a 5145 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
33b28357 5146 fcport->fp_speed, fcport->port_name);
d8b45213
AV		 5147 }
5148}
5149
cc28e0ac
QT		 5150void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5151{
5152 qla2x00_iidma_fcport(vha, fcport);
5153 qla24xx_update_fcport_fcp_prio(vha, fcport);
5154}
5155
5156int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5157{
5158 struct qla_work_evt *e;
5159
5160 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA);
5161 if (!e)
5162 return QLA_FUNCTION_FAILED;
5163
5164 e->u.fcport.fcport = fcport;
5165 return qla2x00_post_work(vha, e);
5166}
5167
726b8548 5168/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 5169static void
e315cd28 5170qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 5171{
5172 struct fc_rport_identifiers rport_ids;
bdf79621 5173 struct fc_rport *rport;
044d78e1 5174 unsigned long flags;
8482e118 5175
b63d8b89
QT		 5176 if (atomic_read(&fcport->state) == FCS_ONLINE)
5177 return;
5178
f8b02a85
AV		 5179 rport_ids.node_name = wwn_to_u64(fcport->node_name);
5180 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 5181 rport_ids.port_id = fcport->d_id.b.domain << 16 |
5182 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 5183 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 5184 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 5185 if (!rport) {
7c3df132
SK		 5186 ql_log(ql_log_warn, vha, 0x2006,
5187 "Unable to allocate fc remote port.\n");
77d74143
AV		 5188 return;
5189 }
2d70c103 5190
044d78e1 5191 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 5192 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 5193 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 5194
ad3e0eda 5195 rport->supported_classes = fcport->supported_classes;
77d74143 5196
8482e118 5197 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
5198 if (fcport->port_type == FCT_INITIATOR)
5199 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
5200 if (fcport->port_type == FCT_TARGET)
5201 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548 5202
83548fe2
QT		 5203 ql_dbg(ql_dbg_disc, vha, 0x20ee,
5204 "%s %8phN. rport %p is %s mode\n",
5205 __func__, fcport->port_name, rport,
5206 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
726b8548 5207
77d74143 5208 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 5209}
5210
23be331d
AB		 5211/*
5212 * qla2x00_update_fcport
5213 * Updates device on list.
5214 *
5215 * Input:
5216 * ha = adapter block pointer.
5217 * fcport = port structure pointer.
5218 *
5219 * Return:
5220 * 0 - Success
5221 * BIT_0 - error
5222 *
5223 * Context:
5224 * Kernel context.
5225 */
5226void
e315cd28 5227qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 5228{
726b8548
QT		 5229 if (IS_SW_RESV_ADDR(fcport->d_id))
5230 return;
5231
cd4ed6b4
QT		 5232 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
5233 __func__, fcport->port_name);
5234
5235 fcport->disc_state = DSC_UPD_FCPORT;
5236 fcport->login_retry = vha->hw->login_retry_count;
b63d8b89 5237 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
b63d8b89
QT		 5238 fcport->deleted = 0;
5239 fcport->logout_on_delete = 1;
5240 fcport->login_retry = vha->hw->login_retry_count;
8777e431 5241 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0;
23be331d 5242
dbe18018
DT		 5243 qla2x00_iidma_fcport(vha, fcport);
5244
8777e431
QT		 5245 switch (vha->hw->current_topology) {
5246 case ISP_CFG_N:
5247 case ISP_CFG_NL:
5248 fcport->keep_nport_handle = 1;
5249 break;
5250 default:
5251 break;
5252 }
5253
e84067d7
DG		 5254 if (fcport->fc4f_nvme) {
5255 qla_nvme_register_remote(vha, fcport);
b63d8b89
QT		 5256 fcport->disc_state = DSC_LOGIN_COMPLETE;
5257 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e84067d7
DG		 5258 return;
5259 }
5260
21090cbe 5261 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b 5262
726b8548
QT		 5263 switch (vha->host->active_mode) {
5264 case MODE_INITIATOR:
d20ed91b 5265 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5266 break;
5267 case MODE_TARGET:
5268 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5269 !vha->vha_tgt.qla_tgt->tgt_stopped)
5270 qlt_fc_port_added(vha, fcport);
5271 break;
5272 case MODE_DUAL:
d20ed91b 5273 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5274 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5275 !vha->vha_tgt.qla_tgt->tgt_stopped)
5276 qlt_fc_port_added(vha, fcport);
5277 break;
5278 default:
5279 break;
d20ed91b 5280 }
cc28e0ac
QT		 5281
5282 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) {
5283 if (fcport->id_changed) {
5284 fcport->id_changed = 0;
5285 ql_dbg(ql_dbg_disc, vha, 0x20d7,
5286 "%s %d %8phC post gfpnid fcp_cnt %d\n",
5287 __func__, __LINE__, fcport->port_name,
5288 vha->fcport_count);
5289 qla24xx_post_gfpnid_work(vha, fcport);
5290 } else {
5291 ql_dbg(ql_dbg_disc, vha, 0x20d7,
5292 "%s %d %8phC post gpsc fcp_cnt %d\n",
5293 __func__, __LINE__, fcport->port_name,
5294 vha->fcport_count);
5295 qla24xx_post_gpsc_work(vha, fcport);
5296 }
5297 }
b63d8b89 5298 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
cd4ed6b4
QT		 5299
5300 fcport->disc_state = DSC_LOGIN_COMPLETE;
5301}
5302
5303void qla_register_fcport_fn(struct work_struct *work)
5304{
5305 fc_port_t *fcport = container_of(work, struct fc_port, reg_work);
5306 u32 rscn_gen = fcport->rscn_gen;
5307 u16 data[2];
5308
5309 if (IS_SW_RESV_ADDR(fcport->d_id))
5310 return;
5311
5312 qla2x00_update_fcport(fcport->vha, fcport);
5313
5314 if (rscn_gen != fcport->rscn_gen) {
5315 /* RSCN(s) came in while registration */
5316 switch (fcport->next_disc_state) {
5317 case DSC_DELETE_PEND:
5318 qlt_schedule_sess_for_deletion(fcport);
5319 break;
5320 case DSC_ADISC:
5321 data[0] = data[1] = 0;
5322 qla2x00_post_async_adisc_work(fcport->vha, fcport,
5323 data);
5324 break;
5325 default:
5326 break;
5327 }
5328 }
23be331d
AB		 5329}
5330
1da177e4
LT		 5331/*
5332 * qla2x00_configure_fabric
5333 * Setup SNS devices with loop ID's.
5334 *
5335 * Input:
5336 * ha = adapter block pointer.
5337 *
5338 * Returns:
5339 * 0 = success.
5340 * BIT_0 = error
5341 */
5342static int
e315cd28 5343qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 5344{
b3b02e6e 5345 int rval;
726b8548 5346 fc_port_t *fcport;
1da177e4 5347 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 5348 uint16_t loop_id;
1da177e4 5349 LIST_HEAD(new_fcports);
e315cd28 5350 struct qla_hw_data *ha = vha->hw;
df673274 5351 int discovery_gen;
1da177e4
LT		 5352
5353 /* If FL port exists, then SNS is present */
e428924c 5354 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 5355 loop_id = NPH_F_PORT;
5356 else
5357 loop_id = SNS_FL_PORT;
e315cd28 5358 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 5359 if (rval != QLA_SUCCESS) {
83548fe2 5360 ql_dbg(ql_dbg_disc, vha, 0x20a0,
7c3df132 5361 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 5362
e315cd28 5363 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 5364 return (QLA_SUCCESS);
5365 }
e315cd28 5366 vha->device_flags |= SWITCH_FOUND;
1da177e4 5367
41dc529a
QT		 5368
5369 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
5370 rval = qla2x00_send_change_request(vha, 0x3, 0);
5371 if (rval != QLA_SUCCESS)
5372 ql_log(ql_log_warn, vha, 0x121,
5373 "Failed to enable receiving of RSCN requests: 0x%x.\n",
5374 rval);
5375 }
5376
5377
1da177e4 5378 do {
726b8548
QT		 5379 qla2x00_mgmt_svr_login(vha);
5380
cca5335c
AV		 5381 /* FDMI support. */
5382 if (ql2xfdmienable &&
e315cd28
AC		 5383 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
5384 qla2x00_fdmi_register(vha);
cca5335c 5385
1da177e4 5386 /* Ensure we are logged into the SNS. */
a14c7711 5387 loop_id = NPH_SNS_LID(ha);
0b91d116
CD		 5388 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
5389 0xfc, mb, BIT_1|BIT_0);
a14c7711
JC		 5390 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5391 ql_dbg(ql_dbg_disc, vha, 0x20a1,
5392 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
5393 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
0b91d116 5394 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 5395 return rval;
0b91d116 5396 }
e315cd28
AC		 5397 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
5398 if (qla2x00_rft_id(vha)) {
1da177e4 5399 /* EMPTY */
83548fe2 5400 ql_dbg(ql_dbg_disc, vha, 0x20a2,
7c3df132 5401 "Register FC-4 TYPE failed.\n");
b98ae0d7
QT		 5402 if (test_bit(LOOP_RESYNC_NEEDED,
5403 &vha->dpc_flags))
5404 break;
1da177e4 5405 }
d3bae931 5406 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
1da177e4 5407 /* EMPTY */
83548fe2 5408 ql_dbg(ql_dbg_disc, vha, 0x209a,
7c3df132 5409 "Register FC-4 Features failed.\n");
b98ae0d7
QT		 5410 if (test_bit(LOOP_RESYNC_NEEDED,
5411 &vha->dpc_flags))
5412 break;
1da177e4 5413 }
d3bae931
DG		 5414 if (vha->flags.nvme_enabled) {
5415 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
5416 ql_dbg(ql_dbg_disc, vha, 0x2049,
5417 "Register NVME FC Type Features failed.\n");
5418 }
5419 }
e315cd28 5420 if (qla2x00_rnn_id(vha)) {
1da177e4 5421 /* EMPTY */
83548fe2 5422 ql_dbg(ql_dbg_disc, vha, 0x2104,
7c3df132 5423 "Register Node Name failed.\n");
b98ae0d7
QT		 5424 if (test_bit(LOOP_RESYNC_NEEDED,
5425 &vha->dpc_flags))
5426 break;
e315cd28 5427 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 5428 /* EMPTY */
83548fe2 5429 ql_dbg(ql_dbg_disc, vha, 0x209b,
0bf0efa1 5430 "Register Symbolic Node Name failed.\n");
b98ae0d7
QT		 5431 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5432 break;
1da177e4
LT		 5433 }
5434 }
5435
827210ba 5436
df673274
AP		 5437 /* Mark the time right before querying FW for connected ports.
5438 * This process is long, asynchronous and by the time it's done,
5439 * collected information might not be accurate anymore. E.g.
5440 * disconnected port might have re-connected and a brand new
5441 * session has been created. In this case session's generation
5442 * will be newer than discovery_gen. */
5443 qlt_do_generation_tick(vha, &discovery_gen);
5444
a4239945 5445 if (USE_ASYNC_SCAN(ha)) {
33b28357
QT		 5446 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI,
5447 NULL);
a4239945
QT		 5448 if (rval)
5449 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5450 } else {
f352eeb7
QT		 5451 list_for_each_entry(fcport, &vha->vp_fcports, list)
5452 fcport->scan_state = QLA_FCPORT_SCAN;
5453
a4239945
QT		 5454 rval = qla2x00_find_all_fabric_devs(vha);
5455 }
1da177e4
LT		 5456 if (rval != QLA_SUCCESS)
5457 break;
1da177e4
LT		 5458 } while (0);
5459
e84067d7
DG		 5460 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
5461 qla_nvme_register_hba(vha);
5462
726b8548 5463 if (rval)
7c3df132
SK		 5464 ql_dbg(ql_dbg_disc, vha, 0x2068,
5465 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 5466
5467 return (rval);
5468}
5469
1da177e4
LT		 5470/*
5471 * qla2x00_find_all_fabric_devs
5472 *
5473 * Input:
5474 * ha = adapter block pointer.
5475 * dev = database device entry pointer.
5476 *
5477 * Returns:
5478 * 0 = success.
5479 *
5480 * Context:
5481 * Kernel context.
5482 */
5483static int
726b8548 5484qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 5485{
5486 int rval;
5487 uint16_t loop_id;
726b8548 5488 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 5489 int found;
5490
5491 sw_info_t *swl;
5492 int swl_idx;
5493 int first_dev, last_dev;
1516ef44 5494 port_id_t wrap = {}, nxt_d_id;
e315cd28 5495 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 5496 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 5497 unsigned long flags;
1da177e4
LT		 5498
5499 rval = QLA_SUCCESS;
5500
5501 /* Try GID_PT to get device list, else GAN. */
7a67735b 5502 if (!ha->swl)
642ef983 5503 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 5504 GFP_KERNEL);
5505 swl = ha->swl;
bbfbbbc1 5506 if (!swl) {
1da177e4 5507 /*EMPTY*/
83548fe2 5508 ql_dbg(ql_dbg_disc, vha, 0x209c,
7c3df132 5509 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 5510 } else {
642ef983 5511 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 5512 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 5513 swl = NULL;
b98ae0d7
QT		 5514 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5515 return rval;
e315cd28 5516 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5517 swl = NULL;
b98ae0d7
QT		 5518 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5519 return rval;
e315cd28 5520 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5521 swl = NULL;
b98ae0d7
QT		 5522 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5523 return rval;
726b8548
QT		 5524 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
5525 swl = NULL;
b98ae0d7
QT		 5526 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5527 return rval;
1da177e4 5528 }
e8c72ba5
CD		 5529
5530 /* If other queries succeeded probe for FC-4 type */
b98ae0d7 5531 if (swl) {
e8c72ba5 5532 qla2x00_gff_id(vha, swl);
b98ae0d7
QT		 5533 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5534 return rval;
5535 }
1da177e4
LT		 5536 }
5537 swl_idx = 0;
5538
5539 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 5540 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5541 if (new_fcport == NULL) {
83548fe2 5542 ql_log(ql_log_warn, vha, 0x209d,
7c3df132 5543 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5544 return (QLA_MEMORY_ALLOC_FAILED);
5545 }
5546 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 5547 /* Set start port ID scan at adapter ID. */
5548 first_dev = 1;
5549 last_dev = 0;
5550
5551 /* Starting free loop ID. */
e315cd28
AC		 5552 loop_id = ha->min_external_loopid;
5553 for (; loop_id <= ha->max_loop_id; loop_id++) {
5554 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 5555 continue;
5556
3a6478df
GM		 5557 if (ha->current_topology == ISP_CFG_FL &&
5558 (atomic_read(&vha->loop_down_timer) ||
5559 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 5560 atomic_set(&vha->loop_down_timer, 0);
5561 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5562 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 5563 break;
bb2d52b2 5564 }
1da177e4
LT		 5565
5566 if (swl != NULL) {
5567 if (last_dev) {
5568 wrap.b24 = new_fcport->d_id.b24;
5569 } else {
5570 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
5571 memcpy(new_fcport->node_name,
5572 swl[swl_idx].node_name, WWN_SIZE);
5573 memcpy(new_fcport->port_name,
5574 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 5575 memcpy(new_fcport->fabric_port_name,
5576 swl[swl_idx].fabric_port_name, WWN_SIZE);
5577 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 5578 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4 5579
a5d42f4c 5580 new_fcport->nvme_flag = 0;
1a28faa0 5581 new_fcport->fc4f_nvme = 0;
a5d42f4c
DG		 5582 if (vha->flags.nvme_enabled &&
5583 swl[swl_idx].fc4f_nvme) {
5584 new_fcport->fc4f_nvme =
5585 swl[swl_idx].fc4f_nvme;
5586 ql_log(ql_log_info, vha, 0x2131,
5587 "FOUND: NVME port %8phC as FC Type 28h\n",
5588 new_fcport->port_name);
5589 }
5590
1da177e4
LT		 5591 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
5592 last_dev = 1;
5593 }
5594 swl_idx++;
5595 }
5596 } else {
5597 /* Send GA_NXT to the switch */
e315cd28 5598 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 5599 if (rval != QLA_SUCCESS) {
83548fe2 5600 ql_log(ql_log_warn, vha, 0x209e,
7c3df132
SK		 5601 "SNS scan failed -- assuming "
5602 "zero-entry result.\n");
1da177e4
LT		 5603 rval = QLA_SUCCESS;
5604 break;
5605 }
5606 }
5607
5608 /* If wrap on switch device list, exit. */
5609 if (first_dev) {
5610 wrap.b24 = new_fcport->d_id.b24;
5611 first_dev = 0;
5612 } else if (new_fcport->d_id.b24 == wrap.b24) {
83548fe2 5613 ql_dbg(ql_dbg_disc, vha, 0x209f,
7c3df132
SK		 5614 "Device wrap (%02x%02x%02x).\n",
5615 new_fcport->d_id.b.domain,
5616 new_fcport->d_id.b.area,
5617 new_fcport->d_id.b.al_pa);
1da177e4
LT		 5618 break;
5619 }
5620
2c3dfe3f 5621 /* Bypass if same physical adapter. */
e315cd28 5622 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 5623 continue;
5624
2c3dfe3f 5625 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 5626 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
5627 continue;
2c3dfe3f 5628
f7d289f6
AV		 5629 /* Bypass if same domain and area of adapter. */
5630 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 5631 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 5632 ISP_CFG_FL)
5633 continue;
5634
1da177e4
LT		 5635 /* Bypass reserved domain fields. */
5636 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
5637 continue;
5638
e8c72ba5 5639 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 5640 if (ql2xgffidenable &&
5641 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
5642 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 5643 continue;
5644
726b8548
QT		 5645 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5646
1da177e4
LT		 5647 /* Locate matching device in database. */
5648 found = 0;
e315cd28 5649 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5650 if (memcmp(new_fcport->port_name, fcport->port_name,
5651 WWN_SIZE))
5652 continue;
5653
827210ba 5654 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 5655
1da177e4
LT		 5656 found++;
5657
d8b45213
AV		 5658 /* Update port state. */
5659 memcpy(fcport->fabric_port_name,
5660 new_fcport->fabric_port_name, WWN_SIZE);
5661 fcport->fp_speed = new_fcport->fp_speed;
5662
1da177e4 5663 /*
b2032fd5
RD		 5664 * If address the same and state FCS_ONLINE
5665 * (or in target mode), nothing changed.
1da177e4
LT		 5666 */
5667 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 5668 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 5669 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 5670 break;
5671 }
5672
5673 /*
5674 * If device was not a fabric device before.
5675 */
5676 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
5677 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 5678 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 5679 fcport->flags |= (FCF_FABRIC_DEVICE |
5680 FCF_LOGIN_NEEDED);
1da177e4
LT		 5681 break;
5682 }
5683
5684 /*
5685 * Port ID changed or device was marked to be updated;
5686 * Log it out if still logged in and mark it for
5687 * relogin later.
5688 */
726b8548 5689 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 5690 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
5691 "port changed FC ID, %8phC"
5692 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
5693 fcport->port_name,
5694 fcport->d_id.b.domain,
5695 fcport->d_id.b.area,
5696 fcport->d_id.b.al_pa,
5697 fcport->loop_id,
5698 new_fcport->d_id.b.domain,
5699 new_fcport->d_id.b.area,
5700 new_fcport->d_id.b.al_pa);
5701 fcport->d_id.b24 = new_fcport->d_id.b24;
5702 break;
5703 }
5704
1da177e4
LT		 5705 fcport->d_id.b24 = new_fcport->d_id.b24;
5706 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 5707 break;
5708 }
5709
9dd9686b
DT		 5710 if (fcport->fc4f_nvme) {
5711 if (fcport->disc_state == DSC_DELETE_PEND) {
5712 fcport->disc_state = DSC_GNL;
5713 vha->fcport_count--;
5714 fcport->login_succ = 0;
5715 }
5716 }
5717
726b8548
QT		 5718 if (found) {
5719 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 5720 continue;
726b8548 5721 }
1da177e4 5722 /* If device was not in our fcports list, then add it. */
b2032fd5 5723 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 5724 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5725
5726 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5727
1da177e4
LT		 5728
5729 /* Allocate a new replacement fcport. */
5730 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 5731 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5732 if (new_fcport == NULL) {
83548fe2 5733 ql_log(ql_log_warn, vha, 0xd032,
7c3df132 5734 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5735 return (QLA_MEMORY_ALLOC_FAILED);
5736 }
5737 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5738 new_fcport->d_id.b24 = nxt_d_id.b24;
5739 }
5740
726b8548
QT		 5741 qla2x00_free_fcport(new_fcport);
5742
5743 /*
5744 * Logout all previous fabric dev marked lost, except FCP2 devices.
5745 */
5746 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5747 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5748 break;
5749
5750 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
5751 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
5752 continue;
5753
5754 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5755 if ((qla_dual_mode_enabled(vha) ||
5756 qla_ini_mode_enabled(vha)) &&
5757 atomic_read(&fcport->state) == FCS_ONLINE) {
5758 qla2x00_mark_device_lost(vha, fcport,
5759 ql2xplogiabsentdevice, 0);
5760 if (fcport->loop_id != FC_NO_LOOP_ID &&
5761 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5762 fcport->port_type != FCT_INITIATOR &&
5763 fcport->port_type != FCT_BROADCAST) {
83548fe2 5764 ql_dbg(ql_dbg_disc, vha, 0x20f0,
726b8548
QT		 5765 "%s %d %8phC post del sess\n",
5766 __func__, __LINE__,
5767 fcport->port_name);
d8630bb9 5768 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 5769 continue;
5770 }
5771 }
5772 }
1da177e4 5773
726b8548
QT		 5774 if (fcport->scan_state == QLA_FCPORT_FOUND)
5775 qla24xx_fcport_handle_login(vha, fcport);
5776 }
1da177e4
LT		 5777 return (rval);
5778}
5779
5780/*
5781 * qla2x00_find_new_loop_id
5782 * Scan through our port list and find a new usable loop ID.
5783 *
5784 * Input:
5785 * ha: adapter state pointer.
5786 * dev: port structure pointer.
5787 *
5788 * Returns:
5789 * qla2x00 local function return status code.
5790 *
5791 * Context:
5792 * Kernel context.
5793 */
03bcfb57 5794int
e315cd28 5795qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 5796{
5797 int rval;
e315cd28 5798 struct qla_hw_data *ha = vha->hw;
feafb7b1 5799 unsigned long flags = 0;
1da177e4
LT		 5800
5801 rval = QLA_SUCCESS;
5802
5f16b331 5803 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 5804
5f16b331
CD		 5805 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
5806 LOOPID_MAP_SIZE);
5807 if (dev->loop_id >= LOOPID_MAP_SIZE ||
5808 qla2x00_is_reserved_id(vha, dev->loop_id)) {
5809 dev->loop_id = FC_NO_LOOP_ID;
5810 rval = QLA_FUNCTION_FAILED;
5811 } else
5812 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 5813
5f16b331 5814 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 5815
5f16b331
CD		 5816 if (rval == QLA_SUCCESS)
5817 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
5818 "Assigning new loopid=%x, portid=%x.\n",
5819 dev->loop_id, dev->d_id.b24);
5820 else
5821 ql_log(ql_log_warn, dev->vha, 0x2087,
5822 "No loop_id's available, portid=%x.\n",
5823 dev->d_id.b24);
1da177e4
LT		 5824
5825 return (rval);
5826}
5827
1da177e4 5828
f6602f3b
QT		 5829/* FW does not set aside Loop id for MGMT Server/FFFFFAh */
5830int
5831qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha)
5832{
5833 int loop_id = FC_NO_LOOP_ID;
5834 int lid = NPH_MGMT_SERVER - vha->vp_idx;
5835 unsigned long flags;
5836 struct qla_hw_data *ha = vha->hw;
5837
5838 if (vha->vp_idx == 0) {
5839 set_bit(NPH_MGMT_SERVER, ha->loop_id_map);
5840 return NPH_MGMT_SERVER;
5841 }
5842
5843 /* pick id from high and work down to low */
5844 spin_lock_irqsave(&ha->vport_slock, flags);
5845 for (; lid > 0; lid--) {
5846 if (!test_bit(lid, vha->hw->loop_id_map)) {
5847 set_bit(lid, vha->hw->loop_id_map);
5848 loop_id = lid;
5849 break;
5850 }
5851 }
5852 spin_unlock_irqrestore(&ha->vport_slock, flags);
5853
5854 return loop_id;
5855}
5856
1da177e4
LT		 5857/*
5858 * qla2x00_fabric_login
5859 * Issue fabric login command.
5860 *
5861 * Input:
5862 * ha = adapter block pointer.
5863 * device = pointer to FC device type structure.
5864 *
5865 * Returns:
5866 * 0 - Login successfully
5867 * 1 - Login failed
5868 * 2 - Initiator device
5869 * 3 - Fatal error
5870 */
5871int
e315cd28 5872qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 5873 uint16_t *next_loopid)
5874{
5875 int rval;
5876 int retry;
5877 uint16_t tmp_loopid;
5878 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5879 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 5880
5881 retry = 0;
5882 tmp_loopid = 0;
5883
5884 for (;;) {
7c3df132
SK		 5885 ql_dbg(ql_dbg_disc, vha, 0x2000,
5886 "Trying Fabric Login w/loop id 0x%04x for port "
5887 "%02x%02x%02x.\n",
5888 fcport->loop_id, fcport->d_id.b.domain,
5889 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5890
5891 /* Login fcport on switch. */
0b91d116 5892 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 5893 fcport->d_id.b.domain, fcport->d_id.b.area,
5894 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 5895 if (rval != QLA_SUCCESS) {
5896 return rval;
5897 }
1da177e4
LT		 5898 if (mb[0] == MBS_PORT_ID_USED) {
5899 /*
5900 * Device has another loop ID. The firmware team
0107109e
AV		 5901 * recommends the driver perform an implicit login with
5902 * the specified ID again. The ID we just used is save
5903 * here so we return with an ID that can be tried by
5904 * the next login.
1da177e4
LT		 5905 */
5906 retry++;
5907 tmp_loopid = fcport->loop_id;
5908 fcport->loop_id = mb[1];
5909
7c3df132
SK		 5910 ql_dbg(ql_dbg_disc, vha, 0x2001,
5911 "Fabric Login: port in use - next loop "
5912 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 5913 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 5914 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5915
5916 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
5917 /*
5918 * Login succeeded.
5919 */
5920 if (retry) {
5921 /* A retry occurred before. */
5922 *next_loopid = tmp_loopid;
5923 } else {
5924 /*
5925 * No retry occurred before. Just increment the
5926 * ID value for next login.
5927 */
5928 *next_loopid = (fcport->loop_id + 1);
5929 }
5930
5931 if (mb[1] & BIT_0) {
5932 fcport->port_type = FCT_INITIATOR;
5933 } else {
5934 fcport->port_type = FCT_TARGET;
5935 if (mb[1] & BIT_1) {
8474f3a0 5936 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 5937 }
5938 }
5939
ad3e0eda
AV		 5940 if (mb[10] & BIT_0)
5941 fcport->supported_classes |= FC_COS_CLASS2;
5942 if (mb[10] & BIT_1)
5943 fcport->supported_classes |= FC_COS_CLASS3;
5944
2d70c103
NB		 5945 if (IS_FWI2_CAPABLE(ha)) {
5946 if (mb[10] & BIT_7)
5947 fcport->flags |=
5948 FCF_CONF_COMP_SUPPORTED;
5949 }
5950
1da177e4
LT		 5951 rval = QLA_SUCCESS;
5952 break;
5953 } else if (mb[0] == MBS_LOOP_ID_USED) {
5954 /*
5955 * Loop ID already used, try next loop ID.
5956 */
5957 fcport->loop_id++;
e315cd28 5958 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 5959 if (rval != QLA_SUCCESS) {
5960 /* Ran out of loop IDs to use */
5961 break;
5962 }
5963 } else if (mb[0] == MBS_COMMAND_ERROR) {
5964 /*
5965 * Firmware possibly timed out during login. If NO
5966 * retries are left to do then the device is declared
5967 * dead.
5968 */
5969 *next_loopid = fcport->loop_id;
e315cd28 5970 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5971 fcport->d_id.b.domain, fcport->d_id.b.area,
5972 fcport->d_id.b.al_pa);
e315cd28 5973 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 5974
5975 rval = 1;
5976 break;
5977 } else {
5978 /*
5979 * unrecoverable / not handled error
5980 */
7c3df132
SK		 5981 ql_dbg(ql_dbg_disc, vha, 0x2002,
5982 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
5983 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
5984 fcport->d_id.b.area, fcport->d_id.b.al_pa,
5985 fcport->loop_id, jiffies);
1da177e4
LT		 5986
5987 *next_loopid = fcport->loop_id;
e315cd28 5988 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5989 fcport->d_id.b.domain, fcport->d_id.b.area,
5990 fcport->d_id.b.al_pa);
5f16b331 5991 qla2x00_clear_loop_id(fcport);
0eedfcf0 5992 fcport->login_retry = 0;
1da177e4
LT		 5993
5994 rval = 3;
5995 break;
5996 }
5997 }
5998
5999 return (rval);
6000}
6001
6002/*
6003 * qla2x00_local_device_login
6004 * Issue local device login command.
6005 *
6006 * Input:
6007 * ha = adapter block pointer.
6008 * loop_id = loop id of device to login to.
6009 *
6010 * Returns (Where's the #define!!!!):
6011 * 0 - Login successfully
6012 * 1 - Login failed
6013 * 3 - Fatal error
6014 */
6015int
e315cd28 6016qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 6017{
6018 int rval;
6019 uint16_t mb[MAILBOX_REGISTER_COUNT];
6020
6021 memset(mb, 0, sizeof(mb));
e315cd28 6022 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 6023 if (rval == QLA_SUCCESS) {
6024 /* Interrogate mailbox registers for any errors */
6025 if (mb[0] == MBS_COMMAND_ERROR)
6026 rval = 1;
6027 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
6028 /* device not in PCB table */
6029 rval = 3;
6030 }
6031
6032 return (rval);
6033}
6034
6035/*
6036 * qla2x00_loop_resync
6037 * Resync with fibre channel devices.
6038 *
6039 * Input:
6040 * ha = adapter block pointer.
6041 *
6042 * Returns:
6043 * 0 = success
6044 */
6045int
e315cd28 6046qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 6047{
73208dfd 6048 int rval = QLA_SUCCESS;
1da177e4 6049 uint32_t wait_time;
67c2e93a
AC		 6050 struct req_que *req;
6051 struct rsp_que *rsp;
6052
d7459527 6053 req = vha->req;
67c2e93a 6054 rsp = req->rsp;
1da177e4 6055
e315cd28
AC		 6056 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6057 if (vha->flags.online) {
6058 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 6059 /* Wait at most MAX_TARGET RSCNs for a stable link. */
6060 wait_time = 256;
6061 do {
8ae6d9c7
GM		 6062 if (!IS_QLAFX00(vha->hw)) {
6063 /*
6064 * Issue a marker after FW becomes
6065 * ready.
6066 */
6067 qla2x00_marker(vha, req, rsp, 0, 0,
6068 MK_SYNC_ALL);
6069 vha->marker_needed = 0;
6070 }
1da177e4
LT		 6071
6072 /* Remap devices on Loop. */
e315cd28 6073 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 6074
8ae6d9c7
GM		 6075 if (IS_QLAFX00(vha->hw))
6076 qlafx00_configure_devices(vha);
6077 else
6078 qla2x00_configure_loop(vha);
6079
1da177e4 6080 wait_time--;
e315cd28
AC		 6081 } while (!atomic_read(&vha->loop_down_timer) &&
6082 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
6083 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
6084 &vha->dpc_flags)));
1da177e4 6085 }
1da177e4
LT		 6086 }
6087
e315cd28 6088 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 6089 return (QLA_FUNCTION_FAILED);
1da177e4 6090
e315cd28 6091 if (rval)
7c3df132
SK		 6092 ql_dbg(ql_dbg_disc, vha, 0x206c,
6093 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 6094
6095 return (rval);
6096}
6097
579d12b5
SK		 6098/*
6099* qla2x00_perform_loop_resync
6100* Description: This function will set the appropriate flags and call
6101* qla2x00_loop_resync. If successful loop will be resynced
6102* Arguments : scsi_qla_host_t pointer
6103* returm : Success or Failure
6104*/
6105
6106int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
6107{
6108 int32_t rval = 0;
6109
6110 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
6111 /*Configure the flags so that resync happens properly*/
6112 atomic_set(&ha->loop_down_timer, 0);
6113 if (!(ha->device_flags & DFLG_NO_CABLE)) {
6114 atomic_set(&ha->loop_state, LOOP_UP);
6115 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
6116 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
6117 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
6118
6119 rval = qla2x00_loop_resync(ha);
6120 } else
6121 atomic_set(&ha->loop_state, LOOP_DEAD);
6122
6123 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
6124 }
6125
6126 return rval;
6127}
6128
d97994dc 6129void
67becc00 6130qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 6131{
6132 fc_port_t *fcport;
feafb7b1
AE		 6133 struct scsi_qla_host *vha;
6134 struct qla_hw_data *ha = base_vha->hw;
6135 unsigned long flags;
d97994dc 6136
feafb7b1 6137 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 6138 /* Go with deferred removal of rport references. */
feafb7b1
AE		 6139 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
6140 atomic_inc(&vha->vref_count);
6141 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 6142 if (fcport->drport &&
feafb7b1
AE		 6143 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
6144 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 6145 qla2x00_rport_del(fcport);
df673274 6146
feafb7b1
AE		 6147 spin_lock_irqsave(&ha->vport_slock, flags);
6148 }
6149 }
6150 atomic_dec(&vha->vref_count);
c4a9b538 6151 wake_up(&vha->vref_waitq);
feafb7b1
AE		 6152 }
6153 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 6154}
6155
7d613ac6
SV		 6156/* Assumes idc_lock always held on entry */
6157void
6158qla83xx_reset_ownership(scsi_qla_host_t *vha)
6159{
6160 struct qla_hw_data *ha = vha->hw;
6161 uint32_t drv_presence, drv_presence_mask;
6162 uint32_t dev_part_info1, dev_part_info2, class_type;
6163 uint32_t class_type_mask = 0x3;
6164 uint16_t fcoe_other_function = 0xffff, i;
6165
7ec0effd
AD		 6166 if (IS_QLA8044(ha)) {
6167 drv_presence = qla8044_rd_direct(vha,
6168 QLA8044_CRB_DRV_ACTIVE_INDEX);
6169 dev_part_info1 = qla8044_rd_direct(vha,
6170 QLA8044_CRB_DEV_PART_INFO_INDEX);
6171 dev_part_info2 = qla8044_rd_direct(vha,
6172 QLA8044_CRB_DEV_PART_INFO2);
6173 } else {
6174 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6175 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
6176 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
6177 }
7d613ac6
SV		 6178 for (i = 0; i < 8; i++) {
6179 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
6180 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6181 (i != ha->portnum)) {
6182 fcoe_other_function = i;
6183 break;
6184 }
6185 }
6186 if (fcoe_other_function == 0xffff) {
6187 for (i = 0; i < 8; i++) {
6188 class_type = ((dev_part_info2 >> (i * 4)) &
6189 class_type_mask);
6190 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6191 ((i + 8) != ha->portnum)) {
6192 fcoe_other_function = i + 8;
6193 break;
6194 }
6195 }
6196 }
6197 /*
6198 * Prepare drv-presence mask based on fcoe functions present.
6199 * However consider only valid physical fcoe function numbers (0-15).
6200 */
6201 drv_presence_mask = ~((1 << (ha->portnum)) |
6202 ((fcoe_other_function == 0xffff) ?
6203 0 : (1 << (fcoe_other_function))));
6204
6205 /* We are the reset owner iff:
6206 * - No other protocol drivers present.
6207 * - This is the lowest among fcoe functions. */
6208 if (!(drv_presence & drv_presence_mask) &&
6209 (ha->portnum < fcoe_other_function)) {
6210 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
6211 "This host is Reset owner.\n");
6212 ha->flags.nic_core_reset_owner = 1;
6213 }
6214}
6215
fa492630 6216static int
7d613ac6
SV		 6217__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
6218{
6219 int rval = QLA_SUCCESS;
6220 struct qla_hw_data *ha = vha->hw;
6221 uint32_t drv_ack;
6222
6223 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6224 if (rval == QLA_SUCCESS) {
6225 drv_ack |= (1 << ha->portnum);
6226 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6227 }
6228
6229 return rval;
6230}
6231
fa492630 6232static int
7d613ac6
SV		 6233__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
6234{
6235 int rval = QLA_SUCCESS;
6236 struct qla_hw_data *ha = vha->hw;
6237 uint32_t drv_ack;
6238
6239 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6240 if (rval == QLA_SUCCESS) {
6241 drv_ack &= ~(1 << ha->portnum);
6242 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6243 }
6244
6245 return rval;
6246}
6247
fa492630 6248static const char *
7d613ac6
SV		 6249qla83xx_dev_state_to_string(uint32_t dev_state)
6250{
6251 switch (dev_state) {
6252 case QLA8XXX_DEV_COLD:
6253 return "COLD/RE-INIT";
6254 case QLA8XXX_DEV_INITIALIZING:
6255 return "INITIALIZING";
6256 case QLA8XXX_DEV_READY:
6257 return "READY";
6258 case QLA8XXX_DEV_NEED_RESET:
6259 return "NEED RESET";
6260 case QLA8XXX_DEV_NEED_QUIESCENT:
6261 return "NEED QUIESCENT";
6262 case QLA8XXX_DEV_FAILED:
6263 return "FAILED";
6264 case QLA8XXX_DEV_QUIESCENT:
6265 return "QUIESCENT";
6266 default:
6267 return "Unknown";
6268 }
6269}
6270
6271/* Assumes idc-lock always held on entry */
6272void
6273qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
6274{
6275 struct qla_hw_data *ha = vha->hw;
6276 uint32_t idc_audit_reg = 0, duration_secs = 0;
6277
6278 switch (audit_type) {
6279 case IDC_AUDIT_TIMESTAMP:
6280 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
6281 idc_audit_reg = (ha->portnum) |
6282 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
6283 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6284 break;
6285
6286 case IDC_AUDIT_COMPLETION:
6287 duration_secs = ((jiffies_to_msecs(jiffies) -
6288 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
6289 idc_audit_reg = (ha->portnum) |
6290 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
6291 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6292 break;
6293
6294 default:
6295 ql_log(ql_log_warn, vha, 0xb078,
6296 "Invalid audit type specified.\n");
6297 break;
6298 }
6299}
6300
6301/* Assumes idc_lock always held on entry */
fa492630 6302static int
7d613ac6
SV		 6303qla83xx_initiating_reset(scsi_qla_host_t *vha)
6304{
6305 struct qla_hw_data *ha = vha->hw;
6306 uint32_t idc_control, dev_state;
6307
6308 __qla83xx_get_idc_control(vha, &idc_control);
6309 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
6310 ql_log(ql_log_info, vha, 0xb080,
6311 "NIC Core reset has been disabled. idc-control=0x%x\n",
6312 idc_control);
6313 return QLA_FUNCTION_FAILED;
6314 }
6315
6316 /* Set NEED-RESET iff in READY state and we are the reset-owner */
6317 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6318 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
6319 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
6320 QLA8XXX_DEV_NEED_RESET);
6321 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
6322 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
6323 } else {
6324 const char *state = qla83xx_dev_state_to_string(dev_state);
6325 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
6326
6327 /* SV: XXX: Is timeout required here? */
6328 /* Wait for IDC state change READY -> NEED_RESET */
6329 while (dev_state == QLA8XXX_DEV_READY) {
6330 qla83xx_idc_unlock(vha, 0);
6331 msleep(200);
6332 qla83xx_idc_lock(vha, 0);
6333 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6334 }
6335 }
6336
6337 /* Send IDC ack by writing to drv-ack register */
6338 __qla83xx_set_drv_ack(vha);
6339
6340 return QLA_SUCCESS;
6341}
6342
6343int
6344__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
6345{
6346 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6347}
6348
7d613ac6
SV		 6349int
6350__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
6351{
6352 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6353}
6354
fa492630 6355static int
7d613ac6
SV		 6356qla83xx_check_driver_presence(scsi_qla_host_t *vha)
6357{
6358 uint32_t drv_presence = 0;
6359 struct qla_hw_data *ha = vha->hw;
6360
6361 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6362 if (drv_presence & (1 << ha->portnum))
6363 return QLA_SUCCESS;
6364 else
6365 return QLA_TEST_FAILED;
6366}
6367
6368int
6369qla83xx_nic_core_reset(scsi_qla_host_t *vha)
6370{
6371 int rval = QLA_SUCCESS;
6372 struct qla_hw_data *ha = vha->hw;
6373
6374 ql_dbg(ql_dbg_p3p, vha, 0xb058,
6375 "Entered %s().\n", __func__);
6376
6377 if (vha->device_flags & DFLG_DEV_FAILED) {
6378 ql_log(ql_log_warn, vha, 0xb059,
6379 "Device in unrecoverable FAILED state.\n");
6380 return QLA_FUNCTION_FAILED;
6381 }
6382
6383 qla83xx_idc_lock(vha, 0);
6384
6385 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
6386 ql_log(ql_log_warn, vha, 0xb05a,
6387 "Function=0x%x has been removed from IDC participation.\n",
6388 ha->portnum);
6389 rval = QLA_FUNCTION_FAILED;
6390 goto exit;
6391 }
6392
6393 qla83xx_reset_ownership(vha);
6394
6395 rval = qla83xx_initiating_reset(vha);
6396
6397 /*
6398 * Perform reset if we are the reset-owner,
6399 * else wait till IDC state changes to READY/FAILED.
6400 */
6401 if (rval == QLA_SUCCESS) {
6402 rval = qla83xx_idc_state_handler(vha);
6403
6404 if (rval == QLA_SUCCESS)
6405 ha->flags.nic_core_hung = 0;
6406 __qla83xx_clear_drv_ack(vha);
6407 }
6408
6409exit:
6410 qla83xx_idc_unlock(vha, 0);
6411
6412 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
6413
6414 return rval;
6415}
6416
81178772
SK		 6417int
6418qla2xxx_mctp_dump(scsi_qla_host_t *vha)
6419{
6420 struct qla_hw_data *ha = vha->hw;
6421 int rval = QLA_FUNCTION_FAILED;
6422
6423 if (!IS_MCTP_CAPABLE(ha)) {
6424 /* This message can be removed from the final version */
6425 ql_log(ql_log_info, vha, 0x506d,
6426 "This board is not MCTP capable\n");
6427 return rval;
6428 }
6429
6430 if (!ha->mctp_dump) {
6431 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
6432 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
6433
6434 if (!ha->mctp_dump) {
6435 ql_log(ql_log_warn, vha, 0x506e,
6436 "Failed to allocate memory for mctp dump\n");
6437 return rval;
6438 }
6439 }
6440
6441#define MCTP_DUMP_STR_ADDR 0x00000000
6442 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
6443 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
6444 if (rval != QLA_SUCCESS) {
6445 ql_log(ql_log_warn, vha, 0x506f,
6446 "Failed to capture mctp dump\n");
6447 } else {
6448 ql_log(ql_log_info, vha, 0x5070,
6449 "Mctp dump capture for host (%ld/%p).\n",
6450 vha->host_no, ha->mctp_dump);
6451 ha->mctp_dumped = 1;
6452 }
6453
409ee0fe 6454 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 6455 ha->flags.nic_core_reset_hdlr_active = 1;
6456 rval = qla83xx_restart_nic_firmware(vha);
6457 if (rval)
6458 /* NIC Core reset failed. */
6459 ql_log(ql_log_warn, vha, 0x5071,
6460 "Failed to restart nic firmware\n");
6461 else
6462 ql_dbg(ql_dbg_p3p, vha, 0xb084,
6463 "Restarted NIC firmware successfully.\n");
6464 ha->flags.nic_core_reset_hdlr_active = 0;
6465 }
6466
6467 return rval;
6468
6469}
6470
579d12b5 6471/*
8fcd6b8b 6472* qla2x00_quiesce_io
579d12b5
SK		 6473* Description: This function will block the new I/Os
6474* Its not aborting any I/Os as context
6475* is not destroyed during quiescence
6476* Arguments: scsi_qla_host_t
6477* return : void
6478*/
6479void
8fcd6b8b 6480qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 6481{
6482 struct qla_hw_data *ha = vha->hw;
6483 struct scsi_qla_host *vp;
6484
8fcd6b8b
CD		 6485 ql_dbg(ql_dbg_dpc, vha, 0x401d,
6486 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 6487
6488 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
6489 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6490 atomic_set(&vha->loop_state, LOOP_DOWN);
6491 qla2x00_mark_all_devices_lost(vha, 0);
6492 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 6493 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 6494 } else {
6495 if (!atomic_read(&vha->loop_down_timer))
6496 atomic_set(&vha->loop_down_timer,
6497 LOOP_DOWN_TIME);
6498 }
6499 /* Wait for pending cmds to complete */
6500 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
6501}
6502
a9083016
GM		 6503void
6504qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
6505{
6506 struct qla_hw_data *ha = vha->hw;
579d12b5 6507 struct scsi_qla_host *vp;
feafb7b1 6508 unsigned long flags;
6aef87be 6509 fc_port_t *fcport;
7c3f8fd1 6510 u16 i;
a9083016 6511
e46ef004
SK		 6512 /* For ISP82XX, driver waits for completion of the commands.
6513 * online flag should be set.
6514 */
7ec0effd 6515 if (!(IS_P3P_TYPE(ha)))
e46ef004 6516 vha->flags.online = 0;
a9083016
GM		 6517 ha->flags.chip_reset_done = 0;
6518 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 6519 vha->qla_stats.total_isp_aborts++;
a9083016 6520
7c3df132
SK		 6521 ql_log(ql_log_info, vha, 0x00af,
6522 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 6523
b2000805 6524 ha->flags.purge_mbox = 1;
e46ef004
SK		 6525 /* For ISP82XX, reset_chip is just disabling interrupts.
6526 * Driver waits for the completion of the commands.
6527 * the interrupts need to be enabled.
6528 */
7ec0effd 6529 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 6530 ha->isp_ops->reset_chip(vha);
6531
9cd883f0
QT		 6532 SAVE_TOPO(ha);
6533 ha->flags.rida_fmt2 = 0;
ec7193e2
QT		 6534 ha->flags.n2n_ae = 0;
6535 ha->flags.lip_ae = 0;
6536 ha->current_topology = 0;
6537 ha->flags.fw_started = 0;
6538 ha->flags.fw_init_done = 0;
b2000805
QT		 6539 ha->chip_reset++;
6540 ha->base_qpair->chip_reset = ha->chip_reset;
7c3f8fd1
QT		 6541 for (i = 0; i < ha->max_qpairs; i++) {
6542 if (ha->queue_pair_map[i])
6543 ha->queue_pair_map[i]->chip_reset =
6544 ha->base_qpair->chip_reset;
6545 }
726b8548 6546
b2000805
QT		 6547 /* purge MBox commands */
6548 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6549 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6550 complete(&ha->mbx_intr_comp);
6551 }
6552
6553 i = 0;
6554 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6555 atomic_read(&ha->num_pend_mbx_stage2) ||
6556 atomic_read(&ha->num_pend_mbx_stage1)) {
6557 msleep(20);
6558 i++;
6559 if (i > 50)
6560 break;
6561 }
6562 ha->flags.purge_mbox = 0;
6563
a9083016
GM		 6564 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
6565 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6566 atomic_set(&vha->loop_state, LOOP_DOWN);
6567 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 6568
6569 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 6570 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 6571 atomic_inc(&vp->vref_count);
6572 spin_unlock_irqrestore(&ha->vport_slock, flags);
6573
a9083016 6574 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 6575
6576 spin_lock_irqsave(&ha->vport_slock, flags);
6577 atomic_dec(&vp->vref_count);
6578 }
6579 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 6580 } else {
6581 if (!atomic_read(&vha->loop_down_timer))
6582 atomic_set(&vha->loop_down_timer,
6583 LOOP_DOWN_TIME);
6584 }
6585
6aef87be
AV		 6586 /* Clear all async request states across all VPs. */
6587 list_for_each_entry(fcport, &vha->vp_fcports, list)
6588 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6589 spin_lock_irqsave(&ha->vport_slock, flags);
6590 list_for_each_entry(vp, &ha->vp_list, list) {
6591 atomic_inc(&vp->vref_count);
6592 spin_unlock_irqrestore(&ha->vport_slock, flags);
6593
6594 list_for_each_entry(fcport, &vp->vp_fcports, list)
6595 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6596
6597 spin_lock_irqsave(&ha->vport_slock, flags);
6598 atomic_dec(&vp->vref_count);
6599 }
6600 spin_unlock_irqrestore(&ha->vport_slock, flags);
6601
bddd2d65
LC		 6602 if (!ha->flags.eeh_busy) {
6603 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 6604 if (IS_P3P_TYPE(ha)) {
7190575f 6605 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 6606 ql_log(ql_log_info, vha, 0x00b4,
6607 "Done chip reset cleanup.\n");
a9083016 6608
e46ef004
SK		 6609 /* Done waiting for pending commands.
6610 * Reset the online flag.
6611 */
6612 vha->flags.online = 0;
4d78c973 6613 }
a9083016 6614
bddd2d65
LC		 6615 /* Requeue all commands in outstanding command list. */
6616 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6617 }
b6a029e1
AE		 6618 /* memory barrier */
6619 wmb();
a9083016
GM		 6620}
6621
1da177e4
LT		 6622/*
6623* qla2x00_abort_isp
6624* Resets ISP and aborts all outstanding commands.
6625*
6626* Input:
6627* ha = adapter block pointer.
6628*
6629* Returns:
6630* 0 = success
6631*/
6632int
e315cd28 6633qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 6634{
476e8978 6635 int rval;
1da177e4 6636 uint8_t status = 0;
e315cd28
AC		 6637 struct qla_hw_data *ha = vha->hw;
6638 struct scsi_qla_host *vp;
73208dfd 6639 struct req_que *req = ha->req_q_map[0];
feafb7b1 6640 unsigned long flags;
1da177e4 6641
e315cd28 6642 if (vha->flags.online) {
a9083016 6643 qla2x00_abort_isp_cleanup(vha);
1da177e4 6644
a6171297
SV		 6645 if (IS_QLA8031(ha)) {
6646 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
6647 "Clearing fcoe driver presence.\n");
6648 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
6649 ql_dbg(ql_dbg_p3p, vha, 0xb073,
6650 "Error while clearing DRV-Presence.\n");
6651 }
6652
85880801
AV		 6653 if (unlikely(pci_channel_offline(ha->pdev) &&
6654 ha->flags.pci_channel_io_perm_failure)) {
6655 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6656 status = 0;
6657 return status;
6658 }
6659
73208dfd 6660 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 6661
e315cd28 6662 ha->isp_ops->nvram_config(vha);
1da177e4 6663
e315cd28
AC		 6664 if (!qla2x00_restart_isp(vha)) {
6665 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 6666
e315cd28 6667 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 6668 /*
6669 * Issue marker command only when we are going
6670 * to start the I/O .
6671 */
e315cd28 6672 vha->marker_needed = 1;
1da177e4
LT		 6673 }
6674
e315cd28 6675 vha->flags.online = 1;
1da177e4 6676
fd34f556 6677 ha->isp_ops->enable_intrs(ha);
1da177e4 6678
fa2a1ce5 6679 ha->isp_abort_cnt = 0;
e315cd28 6680 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 6681
6246b8a1
GM		 6682 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
6683 qla2x00_get_fw_version(vha);
df613b96
AV		 6684 if (ha->fce) {
6685 ha->flags.fce_enabled = 1;
6686 memset(ha->fce, 0,
6687 fce_calc_size(ha->fce_bufs));
e315cd28 6688 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 6689 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6690 &ha->fce_bufs);
6691 if (rval) {
7c3df132 6692 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 6693 "Unable to reinitialize FCE "
6694 "(%d).\n", rval);
6695 ha->flags.fce_enabled = 0;
6696 }
6697 }
436a7b11
AV		 6698
6699 if (ha->eft) {
6700 memset(ha->eft, 0, EFT_SIZE);
e315cd28 6701 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 6702 ha->eft_dma, EFT_NUM_BUFFERS);
6703 if (rval) {
7c3df132 6704 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 6705 "Unable to reinitialize EFT "
6706 "(%d).\n", rval);
6707 }
6708 }
1da177e4 6709 } else { /* failed the ISP abort */
e315cd28
AC		 6710 vha->flags.online = 1;
6711 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 6712 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 6713 ql_log(ql_log_fatal, vha, 0x8035,
6714 "ISP error recover failed - "
6715 "board disabled.\n");
fa2a1ce5 6716 /*
1da177e4
LT		 6717 * The next call disables the board
6718 * completely.
6719 */
e315cd28
AC		 6720 ha->isp_ops->reset_adapter(vha);
6721 vha->flags.online = 0;
1da177e4 6722 clear_bit(ISP_ABORT_RETRY,
e315cd28 6723 &vha->dpc_flags);
1da177e4
LT		 6724 status = 0;
6725 } else { /* schedule another ISP abort */
6726 ha->isp_abort_cnt--;
7c3df132
SK		 6727 ql_dbg(ql_dbg_taskm, vha, 0x8020,
6728 "ISP abort - retry remaining %d.\n",
6729 ha->isp_abort_cnt);
1da177e4
LT		 6730 status = 1;
6731 }
6732 } else {
6733 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 6734 ql_dbg(ql_dbg_taskm, vha, 0x8021,
6735 "ISP error recovery - retrying (%d) "
6736 "more times.\n", ha->isp_abort_cnt);
e315cd28 6737 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 6738 status = 1;
6739 }
6740 }
fa2a1ce5 6741
1da177e4
LT		 6742 }
6743
e315cd28 6744 if (!status) {
7c3df132 6745 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
1608cc4a 6746 qla2x00_configure_hba(vha);
feafb7b1
AE		 6747 spin_lock_irqsave(&ha->vport_slock, flags);
6748 list_for_each_entry(vp, &ha->vp_list, list) {
6749 if (vp->vp_idx) {
6750 atomic_inc(&vp->vref_count);
6751 spin_unlock_irqrestore(&ha->vport_slock, flags);
6752
e315cd28 6753 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6754
6755 spin_lock_irqsave(&ha->vport_slock, flags);
6756 atomic_dec(&vp->vref_count);
6757 }
e315cd28 6758 }
feafb7b1
AE		 6759 spin_unlock_irqrestore(&ha->vport_slock, flags);
6760
7d613ac6
SV		 6761 if (IS_QLA8031(ha)) {
6762 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
6763 "Setting back fcoe driver presence.\n");
6764 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
6765 ql_dbg(ql_dbg_p3p, vha, 0xb074,
6766 "Error while setting DRV-Presence.\n");
6767 }
e315cd28 6768 } else {
d8424f68
JP		 6769 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
6770 __func__);
1da177e4
LT		 6771 }
6772
6773 return(status);
6774}
6775
6776/*
6777* qla2x00_restart_isp
6778* restarts the ISP after a reset
6779*
6780* Input:
6781* ha = adapter block pointer.
6782*
6783* Returns:
6784* 0 = success
6785*/
6786static int
e315cd28 6787qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 6788{
c6b2fca8 6789 int status = 0;
e315cd28 6790 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 6791 struct req_que *req = ha->req_q_map[0];
6792 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 6793
6794 /* If firmware needs to be loaded */
e315cd28
AC		 6795 if (qla2x00_isp_firmware(vha)) {
6796 vha->flags.online = 0;
6797 status = ha->isp_ops->chip_diag(vha);
6798 if (!status)
6799 status = qla2x00_setup_chip(vha);
1da177e4
LT		 6800 }
6801
e315cd28
AC		 6802 if (!status && !(status = qla2x00_init_rings(vha))) {
6803 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 6804 ha->flags.chip_reset_done = 1;
7108b76e 6805
73208dfd
AC		 6806 /* Initialize the queues in use */
6807 qla25xx_init_queues(ha);
6808
e315cd28
AC		 6809 status = qla2x00_fw_ready(vha);
6810 if (!status) {
0107109e 6811 /* Issue a marker after FW becomes ready. */
73208dfd 6812 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 6813 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6814 }
6815
6816 /* if no cable then assume it's good */
e315cd28 6817 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 6818 status = 0;
1da177e4
LT		 6819 }
6820 return (status);
6821}
6822
73208dfd
AC		 6823static int
6824qla25xx_init_queues(struct qla_hw_data *ha)
6825{
6826 struct rsp_que *rsp = NULL;
6827 struct req_que *req = NULL;
6828 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6829 int ret = -1;
6830 int i;
6831
2afa19a9 6832 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 6833 rsp = ha->rsp_q_map[i];
cb43285f 6834 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 6835 rsp->options &= ~BIT_0;
618a7523 6836 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 6837 if (ret != QLA_SUCCESS)
7c3df132
SK		 6838 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
6839 "%s Rsp que: %d init failed.\n",
6840 __func__, rsp->id);
73208dfd 6841 else
7c3df132
SK		 6842 ql_dbg(ql_dbg_init, base_vha, 0x0100,
6843 "%s Rsp que: %d inited.\n",
6844 __func__, rsp->id);
73208dfd 6845 }
2afa19a9
AC		 6846 }
6847 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 6848 req = ha->req_q_map[i];
cb43285f
QT		 6849 if (req && test_bit(i, ha->req_qid_map)) {
6850 /* Clear outstanding commands array. */
73208dfd 6851 req->options &= ~BIT_0;
618a7523 6852 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 6853 if (ret != QLA_SUCCESS)
7c3df132
SK		 6854 ql_dbg(ql_dbg_init, base_vha, 0x0101,
6855 "%s Req que: %d init failed.\n",
6856 __func__, req->id);
73208dfd 6857 else
7c3df132
SK		 6858 ql_dbg(ql_dbg_init, base_vha, 0x0102,
6859 "%s Req que: %d inited.\n",
6860 __func__, req->id);
73208dfd
AC		 6861 }
6862 }
6863 return ret;
6864}
6865
1da177e4
LT		 6866/*
6867* qla2x00_reset_adapter
6868* Reset adapter.
6869*
6870* Input:
6871* ha = adapter block pointer.
6872*/
abbd8870 6873void
e315cd28 6874qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 6875{
6876 unsigned long flags = 0;
e315cd28 6877 struct qla_hw_data *ha = vha->hw;
3d71644c 6878 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 6879
e315cd28 6880 vha->flags.online = 0;
fd34f556 6881 ha->isp_ops->disable_intrs(ha);
1da177e4 6882
1da177e4
LT		 6883 spin_lock_irqsave(&ha->hardware_lock, flags);
6884 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
6885 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6886 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
6887 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6888 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6889}
0107109e
AV		 6890
6891void
e315cd28 6892qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 6893{
6894 unsigned long flags = 0;
e315cd28 6895 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 6896 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
6897
7ec0effd 6898 if (IS_P3P_TYPE(ha))
a9083016
GM		 6899 return;
6900
e315cd28 6901 vha->flags.online = 0;
fd34f556 6902 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 6903
6904 spin_lock_irqsave(&ha->hardware_lock, flags);
6905 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
6906 RD_REG_DWORD(&reg->hccr);
6907 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
6908 RD_REG_DWORD(&reg->hccr);
6909 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 6910
6911 if (IS_NOPOLLING_TYPE(ha))
6912 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 6913}
6914
4e08df3f
DM		 6915/* On sparc systems, obtain port and node WWN from firmware
6916 * properties.
6917 */
e315cd28
AC		 6918static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
6919 struct nvram_24xx *nv)
4e08df3f
DM		 6920{
6921#ifdef CONFIG_SPARC
e315cd28 6922 struct qla_hw_data *ha = vha->hw;
4e08df3f 6923 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 6924 struct device_node *dp = pci_device_to_OF_node(pdev);
6925 const u8 *val;
4e08df3f
DM		 6926 int len;
6927
6928 val = of_get_property(dp, "port-wwn", &len);
6929 if (val && len >= WWN_SIZE)
6930 memcpy(nv->port_name, val, WWN_SIZE);
6931
6932 val = of_get_property(dp, "node-wwn", &len);
6933 if (val && len >= WWN_SIZE)
6934 memcpy(nv->node_name, val, WWN_SIZE);
6935#endif
6936}
6937
0107109e 6938int
e315cd28 6939qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 6940{
4e08df3f 6941 int rval;
0107109e
AV		 6942 struct init_cb_24xx *icb;
6943 struct nvram_24xx *nv;
6944 uint32_t *dptr;
6945 uint8_t *dptr1, *dptr2;
6946 uint32_t chksum;
6947 uint16_t cnt;
e315cd28 6948 struct qla_hw_data *ha = vha->hw;
0107109e 6949
4e08df3f 6950 rval = QLA_SUCCESS;
0107109e 6951 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 6952 nv = ha->nvram;
0107109e
AV		 6953
6954 /* Determine NVRAM starting address. */
f73cb695 6955 if (ha->port_no == 0) {
e5b68a61
AC		 6956 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
6957 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
6958 } else {
0107109e 6959 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 6960 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
6961 }
f73cb695 6962
e5b68a61
AC		 6963 ha->nvram_size = sizeof(struct nvram_24xx);
6964 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 6965
281afe19
SJ		 6966 /* Get VPD data into cache */
6967 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 6968 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 6969 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
6970
6971 /* Get NVRAM data into cache and calculate checksum. */
0107109e 6972 dptr = (uint32_t *)nv;
e315cd28 6973 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 6974 ha->nvram_size);
da08ef5c
JC		 6975 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6976 chksum += le32_to_cpu(*dptr);
0107109e 6977
7c3df132
SK		 6978 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
6979 "Contents of NVRAM\n");
6980 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
6981 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 6982
6983 /* Bad NVRAM data, set defaults parameters. */
6984 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6985 || nv->id[3] != ' ' ||
ad950360 6986 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 6987 /* Reset NVRAM data. */
7c3df132 6988 ql_log(ql_log_warn, vha, 0x006b,
9e336520 6989 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 6990 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
6991 ql_log(ql_log_warn, vha, 0x006c,
6992 "Falling back to functioning (yet invalid -- WWPN) "
6993 "defaults.\n");
4e08df3f
DM		 6994
6995 /*
6996 * Set default initialization control block.
6997 */
6998 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6999 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7000 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7001 nv->frame_payload_size = 2048;
ad950360
BVA		 7002 nv->execution_throttle = cpu_to_le16(0xFFFF);
7003 nv->exchange_count = cpu_to_le16(0);
7004 nv->hard_address = cpu_to_le16(124);
4e08df3f 7005 nv->port_name[0] = 0x21;
f73cb695 7006 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 7007 nv->port_name[2] = 0x00;
7008 nv->port_name[3] = 0xe0;
7009 nv->port_name[4] = 0x8b;
7010 nv->port_name[5] = 0x1c;
7011 nv->port_name[6] = 0x55;
7012 nv->port_name[7] = 0x86;
7013 nv->node_name[0] = 0x20;
7014 nv->node_name[1] = 0x00;
7015 nv->node_name[2] = 0x00;
7016 nv->node_name[3] = 0xe0;
7017 nv->node_name[4] = 0x8b;
7018 nv->node_name[5] = 0x1c;
7019 nv->node_name[6] = 0x55;
7020 nv->node_name[7] = 0x86;
e315cd28 7021 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 7022 nv->login_retry_count = cpu_to_le16(8);
7023 nv->interrupt_delay_timer = cpu_to_le16(0);
7024 nv->login_timeout = cpu_to_le16(0);
4e08df3f 7025 nv->firmware_options_1 =
ad950360
BVA		 7026 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7027 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7028 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7029 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7030 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7031 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 7032 nv->reset_delay = 5;
ad950360
BVA		 7033 nv->max_luns_per_target = cpu_to_le16(128);
7034 nv->port_down_retry_count = cpu_to_le16(30);
7035 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 7036
7037 rval = 1;
0107109e
AV		 7038 }
7039
726b8548 7040 if (qla_tgt_mode_enabled(vha)) {
2d70c103 7041 /* Don't enable full login after initial LIP */
ad950360 7042 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 7043 /* Don't enable LIP full login for initiator */
ad950360 7044 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 7045 }
7046
7047 qlt_24xx_config_nvram_stage1(vha, nv);
7048
0107109e 7049 /* Reset Initialization control block */
e315cd28 7050 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 7051
7052 /* Copy 1st segment. */
7053 dptr1 = (uint8_t *)icb;
7054 dptr2 = (uint8_t *)&nv->version;
7055 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7056 while (cnt--)
7057 *dptr1++ = *dptr2++;
7058
7059 icb->login_retry_count = nv->login_retry_count;
3ea66e28 7060 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 7061
7062 /* Copy 2nd segment. */
7063 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7064 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7065 cnt = (uint8_t *)&icb->reserved_3 -
7066 (uint8_t *)&icb->interrupt_delay_timer;
7067 while (cnt--)
7068 *dptr1++ = *dptr2++;
0eaaca4c 7069 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
0107109e
AV		 7070 /*
7071 * Setup driver NVRAM options.
7072 */
e315cd28 7073 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 7074 "QLA2462");
0107109e 7075
2d70c103
NB		 7076 qlt_24xx_config_nvram_stage2(vha, icb);
7077
ad950360 7078 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 7079 /* Use alternate WWN? */
5341e868
AV		 7080 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7081 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7082 }
7083
0107109e 7084 /* Prepare nodename */
ad950360 7085 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 7086 /*
7087 * Firmware will apply the following mask if the nodename was
7088 * not provided.
7089 */
7090 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7091 icb->node_name[0] &= 0xF0;
7092 }
7093
7094 /* Set host adapter parameters. */
7095 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 7096 ha->flags.enable_lip_reset = 0;
7097 ha->flags.enable_lip_full_login =
7098 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7099 ha->flags.enable_target_reset =
7100 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 7101 ha->flags.enable_led_scheme = 0;
d4c760c2 7102 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 7103
fd0e7e4d
AV		 7104 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7105 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 7106
7107 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
7108 sizeof(ha->fw_seriallink_options24));
7109
7110 /* save HBA serial number */
7111 ha->serial0 = icb->port_name[5];
7112 ha->serial1 = icb->port_name[6];
7113 ha->serial2 = icb->port_name[7];
e315cd28
AC		 7114 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7115 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 7116
ad950360 7117 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 7118
0107109e
AV		 7119 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7120
7121 /* Set minimum login_timeout to 4 seconds. */
7122 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7123 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7124 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7125 nv->login_timeout = cpu_to_le16(4);
0107109e 7126 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 7127
00a537b8
AV		 7128 /* Set minimum RATOV to 100 tenths of a second. */
7129 ha->r_a_tov = 100;
0107109e
AV		 7130
7131 ha->loop_reset_delay = nv->reset_delay;
7132
7133 /* Link Down Timeout = 0:
7134 *
7135 * When Port Down timer expires we will start returning
7136 * I/O's to OS with "DID_NO_CONNECT".
7137 *
7138 * Link Down Timeout != 0:
7139 *
7140 * The driver waits for the link to come up after link down
7141 * before returning I/Os to OS with "DID_NO_CONNECT".
7142 */
7143 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7144 ha->loop_down_abort_time =
7145 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7146 } else {
7147 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7148 ha->loop_down_abort_time =
7149 (LOOP_DOWN_TIME - ha->link_down_timeout);
7150 }
7151
7152 /* Need enough time to try and get the port back. */
7153 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7154 if (qlport_down_retry)
7155 ha->port_down_retry_count = qlport_down_retry;
7156
7157 /* Set login_retry_count */
7158 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7159 if (ha->port_down_retry_count ==
7160 le16_to_cpu(nv->port_down_retry_count) &&
7161 ha->port_down_retry_count > 3)
7162 ha->login_retry_count = ha->port_down_retry_count;
7163 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7164 ha->login_retry_count = ha->port_down_retry_count;
7165 if (ql2xloginretrycount)
7166 ha->login_retry_count = ql2xloginretrycount;
7167
8777e431
QT		 7168 /* N2N: driver will initiate Login instead of FW */
7169 icb->firmware_options_3 |= BIT_8;
7170
4fdfefe5 7171 /* Enable ZIO. */
e315cd28 7172 if (!vha->flags.init_done) {
4fdfefe5
AV		 7173 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7174 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7175 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7176 le16_to_cpu(icb->interrupt_delay_timer): 2;
7177 }
ad950360 7178 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 7179 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
4fdfefe5 7180 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 7181 ha->zio_mode = QLA_ZIO_MODE_6;
7182
7c3df132 7183 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 7184 "ZIO mode %d enabled; timer delay (%d us).\n",
7185 ha->zio_mode, ha->zio_timer * 100);
7186
7187 icb->firmware_options_2 |= cpu_to_le32(
7188 (uint32_t)ha->zio_mode);
7189 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
4fdfefe5
AV		 7190 }
7191
4e08df3f 7192 if (rval) {
7c3df132
SK		 7193 ql_log(ql_log_warn, vha, 0x0070,
7194 "NVRAM configuration failed.\n");
4e08df3f
DM		 7195 }
7196 return (rval);
0107109e
AV		 7197}
7198
4243c115
SC		 7199uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
7200{
7201 struct qla27xx_image_status pri_image_status, sec_image_status;
7202 uint8_t valid_pri_image, valid_sec_image;
7203 uint32_t *wptr;
7204 uint32_t cnt, chksum, size;
7205 struct qla_hw_data *ha = vha->hw;
7206
7207 valid_pri_image = valid_sec_image = 1;
7208 ha->active_image = 0;
7209 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
7210
7211 if (!ha->flt_region_img_status_pri) {
7212 valid_pri_image = 0;
7213 goto check_sec_image;
7214 }
7215
7216 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
7217 ha->flt_region_img_status_pri, size);
7218
7219 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
7220 ql_dbg(ql_dbg_init, vha, 0x018b,
7221 "Primary image signature (0x%x) not valid\n",
7222 pri_image_status.signature);
7223 valid_pri_image = 0;
7224 goto check_sec_image;
7225 }
7226
7227 wptr = (uint32_t *)(&pri_image_status);
7228 cnt = size;
7229
da08ef5c
JC		 7230 for (chksum = 0; cnt--; wptr++)
7231 chksum += le32_to_cpu(*wptr);
41dc529a 7232
4243c115
SC		 7233 if (chksum) {
7234 ql_dbg(ql_dbg_init, vha, 0x018c,
7235 "Checksum validation failed for primary image (0x%x)\n",
7236 chksum);
7237 valid_pri_image = 0;
7238 }
7239
7240check_sec_image:
7241 if (!ha->flt_region_img_status_sec) {
7242 valid_sec_image = 0;
7243 goto check_valid_image;
7244 }
7245
7246 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
7247 ha->flt_region_img_status_sec, size);
7248
7249 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
7250 ql_dbg(ql_dbg_init, vha, 0x018d,
7251 "Secondary image signature(0x%x) not valid\n",
7252 sec_image_status.signature);
7253 valid_sec_image = 0;
7254 goto check_valid_image;
7255 }
7256
7257 wptr = (uint32_t *)(&sec_image_status);
7258 cnt = size;
da08ef5c
JC		 7259 for (chksum = 0; cnt--; wptr++)
7260 chksum += le32_to_cpu(*wptr);
4243c115
SC		 7261 if (chksum) {
7262 ql_dbg(ql_dbg_init, vha, 0x018e,
7263 "Checksum validation failed for secondary image (0x%x)\n",
7264 chksum);
7265 valid_sec_image = 0;
7266 }
7267
7268check_valid_image:
7269 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
7270 ha->active_image = QLA27XX_PRIMARY_IMAGE;
7271 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
7272 if (!ha->active_image ||
7273 pri_image_status.generation_number <
7274 sec_image_status.generation_number)
7275 ha->active_image = QLA27XX_SECONDARY_IMAGE;
7276 }
7277
22ebde16 7278 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x018f, "%s image\n",
4243c115
SC		 7279 ha->active_image == 0 ? "default bootld and fw" :
7280 ha->active_image == 1 ? "primary" :
7281 ha->active_image == 2 ? "secondary" :
7282 "Invalid");
7283
7284 return ha->active_image;
7285}
7286
413975a0 7287static int
cbc8eb67
AV		 7288qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
7289 uint32_t faddr)
d1c61909 7290{
73208dfd 7291 int rval = QLA_SUCCESS;
d1c61909 7292 int segments, fragment;
d1c61909
AV		 7293 uint32_t *dcode, dlen;
7294 uint32_t risc_addr;
7295 uint32_t risc_size;
7296 uint32_t i;
e315cd28 7297 struct qla_hw_data *ha = vha->hw;
73208dfd 7298 struct req_que *req = ha->req_q_map[0];
eaac30be 7299
7c3df132 7300 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 7301 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 7302
d1c61909
AV		 7303 rval = QLA_SUCCESS;
7304
7305 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7306 dcode = (uint32_t *)req->ring;
d1c61909
AV		 7307 *srisc_addr = 0;
7308
4243c115
SC		 7309 if (IS_QLA27XX(ha) &&
7310 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
7311 faddr = ha->flt_region_fw_sec;
7312
d1c61909 7313 /* Validate firmware image by checking version. */
e315cd28 7314 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 7315 for (i = 0; i < 4; i++)
7316 dcode[i] = be32_to_cpu(dcode[i]);
7317 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7318 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7319 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7320 dcode[3] == 0)) {
7c3df132
SK		 7321 ql_log(ql_log_fatal, vha, 0x008c,
7322 "Unable to verify the integrity of flash firmware "
7323 "image.\n");
7324 ql_log(ql_log_fatal, vha, 0x008d,
7325 "Firmware data: %08x %08x %08x %08x.\n",
7326 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 7327
7328 return QLA_FUNCTION_FAILED;
7329 }
7330
7331 while (segments && rval == QLA_SUCCESS) {
7332 /* Read segment's load information. */
e315cd28 7333 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 7334
7335 risc_addr = be32_to_cpu(dcode[2]);
7336 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7337 risc_size = be32_to_cpu(dcode[3]);
7338
7339 fragment = 0;
7340 while (risc_size > 0 && rval == QLA_SUCCESS) {
7341 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7342 if (dlen > risc_size)
7343 dlen = risc_size;
7344
7c3df132
SK		 7345 ql_dbg(ql_dbg_init, vha, 0x008e,
7346 "Loading risc segment@ risc addr %x "
7347 "number of dwords 0x%x offset 0x%x.\n",
7348 risc_addr, dlen, faddr);
d1c61909 7349
e315cd28 7350 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 7351 for (i = 0; i < dlen; i++)
7352 dcode[i] = swab32(dcode[i]);
7353
73208dfd 7354 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 7355 dlen);
7356 if (rval) {
7c3df132
SK		 7357 ql_log(ql_log_fatal, vha, 0x008f,
7358 "Failed to load segment %d of firmware.\n",
7359 fragment);
f261f7af 7360 return QLA_FUNCTION_FAILED;
d1c61909
AV		 7361 }
7362
7363 faddr += dlen;
7364 risc_addr += dlen;
7365 risc_size -= dlen;
7366 fragment++;
7367 }
7368
7369 /* Next segment. */
7370 segments--;
7371 }
7372
f73cb695
CD		 7373 if (!IS_QLA27XX(ha))
7374 return rval;
7375
7376 if (ha->fw_dump_template)
7377 vfree(ha->fw_dump_template);
7378 ha->fw_dump_template = NULL;
7379 ha->fw_dump_template_len = 0;
7380
7381 ql_dbg(ql_dbg_init, vha, 0x0161,
7382 "Loading fwdump template from %x\n", faddr);
7383 qla24xx_read_flash_data(vha, dcode, faddr, 7);
7384 risc_size = be32_to_cpu(dcode[2]);
7385 ql_dbg(ql_dbg_init, vha, 0x0162,
7386 "-> array size %x dwords\n", risc_size);
7387 if (risc_size == 0 || risc_size == ~0)
7388 goto default_template;
7389
7390 dlen = (risc_size - 8) * sizeof(*dcode);
7391 ql_dbg(ql_dbg_init, vha, 0x0163,
7392 "-> template allocating %x bytes...\n", dlen);
7393 ha->fw_dump_template = vmalloc(dlen);
7394 if (!ha->fw_dump_template) {
7395 ql_log(ql_log_warn, vha, 0x0164,
7396 "Failed fwdump template allocate %x bytes.\n", risc_size);
7397 goto default_template;
7398 }
7399
7400 faddr += 7;
7401 risc_size -= 8;
7402 dcode = ha->fw_dump_template;
7403 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
7404 for (i = 0; i < risc_size; i++)
7405 dcode[i] = le32_to_cpu(dcode[i]);
7406
7407 if (!qla27xx_fwdt_template_valid(dcode)) {
7408 ql_log(ql_log_warn, vha, 0x0165,
7409 "Failed fwdump template validate\n");
7410 goto default_template;
7411 }
7412
7413 dlen = qla27xx_fwdt_template_size(dcode);
7414 ql_dbg(ql_dbg_init, vha, 0x0166,
7415 "-> template size %x bytes\n", dlen);
7416 if (dlen > risc_size * sizeof(*dcode)) {
7417 ql_log(ql_log_warn, vha, 0x0167,
4fae52b5 7418 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7419 (size_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 7420 goto default_template;
7421 }
7422 ha->fw_dump_template_len = dlen;
7423 return rval;
7424
7425default_template:
7426 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
7427 if (ha->fw_dump_template)
7428 vfree(ha->fw_dump_template);
7429 ha->fw_dump_template = NULL;
7430 ha->fw_dump_template_len = 0;
7431
7432 dlen = qla27xx_fwdt_template_default_size();
7433 ql_dbg(ql_dbg_init, vha, 0x0169,
7434 "-> template allocating %x bytes...\n", dlen);
7435 ha->fw_dump_template = vmalloc(dlen);
7436 if (!ha->fw_dump_template) {
7437 ql_log(ql_log_warn, vha, 0x016a,
7438 "Failed fwdump template allocate %x bytes.\n", risc_size);
7439 goto failed_template;
7440 }
7441
7442 dcode = ha->fw_dump_template;
7443 risc_size = dlen / sizeof(*dcode);
7444 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
7445 for (i = 0; i < risc_size; i++)
7446 dcode[i] = be32_to_cpu(dcode[i]);
7447
7448 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7449 ql_log(ql_log_warn, vha, 0x016b,
7450 "Failed fwdump template validate\n");
7451 goto failed_template;
7452 }
7453
7454 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7455 ql_dbg(ql_dbg_init, vha, 0x016c,
7456 "-> template size %x bytes\n", dlen);
7457 ha->fw_dump_template_len = dlen;
7458 return rval;
7459
7460failed_template:
7461 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
7462 if (ha->fw_dump_template)
7463 vfree(ha->fw_dump_template);
7464 ha->fw_dump_template = NULL;
7465 ha->fw_dump_template_len = 0;
d1c61909
AV		 7466 return rval;
7467}
7468
e9454a88 7469#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 7470
0107109e 7471int
e315cd28 7472qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 7473{
7474 int rval;
7475 int i, fragment;
7476 uint16_t *wcode, *fwcode;
7477 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
7478 struct fw_blob *blob;
e315cd28 7479 struct qla_hw_data *ha = vha->hw;
73208dfd 7480 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 7481
7482 /* Load firmware blob. */
e315cd28 7483 blob = qla2x00_request_firmware(vha);
5433383e 7484 if (!blob) {
7c3df132 7485 ql_log(ql_log_info, vha, 0x0083,
94bcf830 7486 "Firmware image unavailable.\n");
7c3df132
SK		 7487 ql_log(ql_log_info, vha, 0x0084,
7488 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 7489 return QLA_FUNCTION_FAILED;
7490 }
7491
7492 rval = QLA_SUCCESS;
7493
73208dfd 7494 wcode = (uint16_t *)req->ring;
5433383e
AV		 7495 *srisc_addr = 0;
7496 fwcode = (uint16_t *)blob->fw->data;
7497 fwclen = 0;
7498
7499 /* Validate firmware image by checking version. */
7500 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 7501 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 7502 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 7503 blob->fw->size);
7504 goto fail_fw_integrity;
7505 }
7506 for (i = 0; i < 4; i++)
7507 wcode[i] = be16_to_cpu(fwcode[i + 4]);
7508 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
7509 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
7510 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 7511 ql_log(ql_log_fatal, vha, 0x0086,
7512 "Unable to verify integrity of firmware image.\n");
7513 ql_log(ql_log_fatal, vha, 0x0087,
7514 "Firmware data: %04x %04x %04x %04x.\n",
7515 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 7516 goto fail_fw_integrity;
7517 }
7518
7519 seg = blob->segs;
7520 while (*seg && rval == QLA_SUCCESS) {
7521 risc_addr = *seg;
7522 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
7523 risc_size = be16_to_cpu(fwcode[3]);
7524
7525 /* Validate firmware image size. */
7526 fwclen += risc_size * sizeof(uint16_t);
7527 if (blob->fw->size < fwclen) {
7c3df132 7528 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 7529 "Unable to verify integrity of firmware image "
5b5e0928 7530 "(%zd).\n", blob->fw->size);
5433383e
AV		 7531 goto fail_fw_integrity;
7532 }
7533
7534 fragment = 0;
7535 while (risc_size > 0 && rval == QLA_SUCCESS) {
7536 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
7537 if (wlen > risc_size)
7538 wlen = risc_size;
7c3df132
SK		 7539 ql_dbg(ql_dbg_init, vha, 0x0089,
7540 "Loading risc segment@ risc addr %x number of "
7541 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 7542
7543 for (i = 0; i < wlen; i++)
7544 wcode[i] = swab16(fwcode[i]);
7545
73208dfd 7546 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 7547 wlen);
7548 if (rval) {
7c3df132
SK		 7549 ql_log(ql_log_fatal, vha, 0x008a,
7550 "Failed to load segment %d of firmware.\n",
7551 fragment);
5433383e
AV		 7552 break;
7553 }
7554
7555 fwcode += wlen;
7556 risc_addr += wlen;
7557 risc_size -= wlen;
7558 fragment++;
7559 }
7560
7561 /* Next segment. */
7562 seg++;
7563 }
7564 return rval;
7565
7566fail_fw_integrity:
7567 return QLA_FUNCTION_FAILED;
7568}
7569
eaac30be
AV		 7570static int
7571qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 7572{
7573 int rval;
7574 int segments, fragment;
7575 uint32_t *dcode, dlen;
7576 uint32_t risc_addr;
7577 uint32_t risc_size;
7578 uint32_t i;
5433383e 7579 struct fw_blob *blob;
f73cb695
CD		 7580 const uint32_t *fwcode;
7581 uint32_t fwclen;
e315cd28 7582 struct qla_hw_data *ha = vha->hw;
73208dfd 7583 struct req_que *req = ha->req_q_map[0];
0107109e 7584
5433383e 7585 /* Load firmware blob. */
e315cd28 7586 blob = qla2x00_request_firmware(vha);
5433383e 7587 if (!blob) {
7c3df132 7588 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 7589 "Firmware image unavailable.\n");
7c3df132
SK		 7590 ql_log(ql_log_warn, vha, 0x0091,
7591 "Firmware images can be retrieved from: "
7592 QLA_FW_URL ".\n");
d1c61909 7593
eaac30be 7594 return QLA_FUNCTION_FAILED;
0107109e
AV		 7595 }
7596
cfb0919c
CD		 7597 ql_dbg(ql_dbg_init, vha, 0x0092,
7598 "FW: Loading via request-firmware.\n");
eaac30be 7599
0107109e
AV		 7600 rval = QLA_SUCCESS;
7601
7602 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7603 dcode = (uint32_t *)req->ring;
0107109e 7604 *srisc_addr = 0;
5433383e 7605 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 7606 fwclen = 0;
7607
7608 /* Validate firmware image by checking version. */
5433383e 7609 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 7610 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 7611 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 7612 blob->fw->size);
f73cb695 7613 return QLA_FUNCTION_FAILED;
0107109e
AV		 7614 }
7615 for (i = 0; i < 4; i++)
7616 dcode[i] = be32_to_cpu(fwcode[i + 4]);
7617 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7618 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7619 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7620 dcode[3] == 0)) {
7c3df132 7621 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 7622 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 7623 blob->fw->size);
7624 ql_log(ql_log_fatal, vha, 0x0095,
7625 "Firmware data: %08x %08x %08x %08x.\n",
7626 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 7627 return QLA_FUNCTION_FAILED;
0107109e
AV		 7628 }
7629
7630 while (segments && rval == QLA_SUCCESS) {
7631 risc_addr = be32_to_cpu(fwcode[2]);
7632 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7633 risc_size = be32_to_cpu(fwcode[3]);
7634
7635 /* Validate firmware image size. */
7636 fwclen += risc_size * sizeof(uint32_t);
5433383e 7637 if (blob->fw->size < fwclen) {
7c3df132 7638 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 7639 "Unable to verify integrity of firmware image "
5b5e0928 7640 "(%zd).\n", blob->fw->size);
f73cb695 7641 return QLA_FUNCTION_FAILED;
0107109e
AV		 7642 }
7643
7644 fragment = 0;
7645 while (risc_size > 0 && rval == QLA_SUCCESS) {
7646 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7647 if (dlen > risc_size)
7648 dlen = risc_size;
7649
7c3df132
SK		 7650 ql_dbg(ql_dbg_init, vha, 0x0097,
7651 "Loading risc segment@ risc addr %x "
7652 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 7653
7654 for (i = 0; i < dlen; i++)
7655 dcode[i] = swab32(fwcode[i]);
7656
73208dfd 7657 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 7658 dlen);
0107109e 7659 if (rval) {
7c3df132
SK		 7660 ql_log(ql_log_fatal, vha, 0x0098,
7661 "Failed to load segment %d of firmware.\n",
7662 fragment);
f261f7af 7663 return QLA_FUNCTION_FAILED;
0107109e
AV		 7664 }
7665
7666 fwcode += dlen;
7667 risc_addr += dlen;
7668 risc_size -= dlen;
7669 fragment++;
7670 }
7671
7672 /* Next segment. */
7673 segments--;
7674 }
f73cb695
CD		 7675
7676 if (!IS_QLA27XX(ha))
7677 return rval;
7678
7679 if (ha->fw_dump_template)
7680 vfree(ha->fw_dump_template);
7681 ha->fw_dump_template = NULL;
7682 ha->fw_dump_template_len = 0;
7683
7684 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 7685 "Loading fwdump template from %x\n",
7686 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 7687 risc_size = be32_to_cpu(fwcode[2]);
7688 ql_dbg(ql_dbg_init, vha, 0x172,
7689 "-> array size %x dwords\n", risc_size);
7690 if (risc_size == 0 || risc_size == ~0)
7691 goto default_template;
7692
7693 dlen = (risc_size - 8) * sizeof(*fwcode);
7694 ql_dbg(ql_dbg_init, vha, 0x0173,
7695 "-> template allocating %x bytes...\n", dlen);
7696 ha->fw_dump_template = vmalloc(dlen);
7697 if (!ha->fw_dump_template) {
7698 ql_log(ql_log_warn, vha, 0x0174,
7699 "Failed fwdump template allocate %x bytes.\n", risc_size);
7700 goto default_template;
7701 }
7702
7703 fwcode += 7;
7704 risc_size -= 8;
7705 dcode = ha->fw_dump_template;
7706 for (i = 0; i < risc_size; i++)
7707 dcode[i] = le32_to_cpu(fwcode[i]);
7708
7709 if (!qla27xx_fwdt_template_valid(dcode)) {
7710 ql_log(ql_log_warn, vha, 0x0175,
7711 "Failed fwdump template validate\n");
7712 goto default_template;
7713 }
7714
7715 dlen = qla27xx_fwdt_template_size(dcode);
7716 ql_dbg(ql_dbg_init, vha, 0x0176,
7717 "-> template size %x bytes\n", dlen);
7718 if (dlen > risc_size * sizeof(*fwcode)) {
7719 ql_log(ql_log_warn, vha, 0x0177,
4fae52b5 7720 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7721 (size_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 7722 goto default_template;
7723 }
7724 ha->fw_dump_template_len = dlen;
0107109e
AV		 7725 return rval;
7726
f73cb695
CD		 7727default_template:
7728 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
7729 if (ha->fw_dump_template)
7730 vfree(ha->fw_dump_template);
7731 ha->fw_dump_template = NULL;
7732 ha->fw_dump_template_len = 0;
7733
7734 dlen = qla27xx_fwdt_template_default_size();
7735 ql_dbg(ql_dbg_init, vha, 0x0179,
7736 "-> template allocating %x bytes...\n", dlen);
7737 ha->fw_dump_template = vmalloc(dlen);
7738 if (!ha->fw_dump_template) {
7739 ql_log(ql_log_warn, vha, 0x017a,
7740 "Failed fwdump template allocate %x bytes.\n", risc_size);
7741 goto failed_template;
7742 }
7743
7744 dcode = ha->fw_dump_template;
7745 risc_size = dlen / sizeof(*fwcode);
7746 fwcode = qla27xx_fwdt_template_default();
7747 for (i = 0; i < risc_size; i++)
7748 dcode[i] = be32_to_cpu(fwcode[i]);
7749
7750 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7751 ql_log(ql_log_warn, vha, 0x017b,
7752 "Failed fwdump template validate\n");
7753 goto failed_template;
7754 }
7755
7756 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7757 ql_dbg(ql_dbg_init, vha, 0x017c,
7758 "-> template size %x bytes\n", dlen);
7759 ha->fw_dump_template_len = dlen;
7760 return rval;
7761
7762failed_template:
7763 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
7764 if (ha->fw_dump_template)
7765 vfree(ha->fw_dump_template);
7766 ha->fw_dump_template = NULL;
7767 ha->fw_dump_template_len = 0;
7768 return rval;
0107109e 7769}
18c6c127 7770
eaac30be
AV		 7771int
7772qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7773{
7774 int rval;
7775
e337d907
AV		 7776 if (ql2xfwloadbin == 1)
7777 return qla81xx_load_risc(vha, srisc_addr);
7778
eaac30be
AV		 7779 /*
7780 * FW Load priority:
7781 * 1) Firmware via request-firmware interface (.bin file).
7782 * 2) Firmware residing in flash.
7783 */
7784 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7785 if (rval == QLA_SUCCESS)
7786 return rval;
7787
cbc8eb67
AV		 7788 return qla24xx_load_risc_flash(vha, srisc_addr,
7789 vha->hw->flt_region_fw);
eaac30be
AV		 7790}
7791
7792int
7793qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7794{
7795 int rval;
cbc8eb67 7796 struct qla_hw_data *ha = vha->hw;
eaac30be 7797
e337d907 7798 if (ql2xfwloadbin == 2)
cbc8eb67 7799 goto try_blob_fw;
e337d907 7800
eaac30be
AV		 7801 /*
7802 * FW Load priority:
7803 * 1) Firmware residing in flash.
7804 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 7805 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 7806 */
cbc8eb67 7807 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 7808 if (rval == QLA_SUCCESS)
7809 return rval;
7810
cbc8eb67
AV		 7811try_blob_fw:
7812 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7813 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
7814 return rval;
7815
7c3df132
SK		 7816 ql_log(ql_log_info, vha, 0x0099,
7817 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 7818 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
7819 if (rval != QLA_SUCCESS)
7820 return rval;
7821
7c3df132 7822 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 7823 ha->flags.running_gold_fw = 1;
cbc8eb67 7824 return rval;
eaac30be
AV		 7825}
7826
18c6c127 7827void
e315cd28 7828qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 7829{
7830 int ret, retries;
e315cd28 7831 struct qla_hw_data *ha = vha->hw;
18c6c127 7832
85880801
AV		 7833 if (ha->flags.pci_channel_io_perm_failure)
7834 return;
e428924c 7835 if (!IS_FWI2_CAPABLE(ha))
18c6c127 7836 return;
75edf81d
AV		 7837 if (!ha->fw_major_version)
7838 return;
ec7193e2
QT		 7839 if (!ha->flags.fw_started)
7840 return;
18c6c127 7841
e315cd28 7842 ret = qla2x00_stop_firmware(vha);
7c7f1f29 7843 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 7844 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 7845 ha->isp_ops->reset_chip(vha);
7846 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 7847 continue;
e315cd28 7848 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 7849 continue;
7c3df132
SK		 7850 ql_log(ql_log_info, vha, 0x8015,
7851 "Attempting retry of stop-firmware command.\n");
e315cd28 7852 ret = qla2x00_stop_firmware(vha);
18c6c127 7853 }
ec7193e2 7854
4b60c827 7855 QLA_FW_STOPPED(ha);
ec7193e2 7856 ha->flags.fw_init_done = 0;
18c6c127 7857}
2c3dfe3f
SJ		 7858
7859int
e315cd28 7860qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 7861{
7862 int rval = QLA_SUCCESS;
0b91d116 7863 int rval2;
2c3dfe3f 7864 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 7865 struct qla_hw_data *ha = vha->hw;
7866 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 7867 struct req_que *req;
7868 struct rsp_que *rsp;
2c3dfe3f 7869
e315cd28 7870 if (!vha->vp_idx)
2c3dfe3f
SJ		 7871 return -EINVAL;
7872
e315cd28 7873 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 7874 if (vha->qpair)
7875 req = vha->qpair->req;
67c2e93a 7876 else
d7459527 7877 req = ha->req_q_map[0];
67c2e93a
AC		 7878 rsp = req->rsp;
7879
2c3dfe3f 7880 if (rval == QLA_SUCCESS) {
e315cd28 7881 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 7882 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 7883 }
7884
e315cd28 7885 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 7886
7887 /* Login to SNS first */
0b91d116
CD		 7888 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
7889 BIT_1);
7890 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
7891 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
7892 ql_dbg(ql_dbg_init, vha, 0x0120,
7893 "Failed SNS login: loop_id=%x, rval2=%d\n",
7894 NPH_SNS, rval2);
7895 else
7896 ql_dbg(ql_dbg_init, vha, 0x0103,
7897 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
7898 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
7899 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 7900 return (QLA_FUNCTION_FAILED);
7901 }
7902
e315cd28
AC		 7903 atomic_set(&vha->loop_down_timer, 0);
7904 atomic_set(&vha->loop_state, LOOP_UP);
7905 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7906 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
7907 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 7908
7909 return rval;
7910}
4d4df193
HK		 7911
7912/* 84XX Support **************************************************************/
7913
7914static LIST_HEAD(qla_cs84xx_list);
7915static DEFINE_MUTEX(qla_cs84xx_mutex);
7916
7917static struct qla_chip_state_84xx *
e315cd28 7918qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 7919{
7920 struct qla_chip_state_84xx *cs84xx;
e315cd28 7921 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7922
7923 mutex_lock(&qla_cs84xx_mutex);
7924
7925 /* Find any shared 84xx chip. */
7926 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
7927 if (cs84xx->bus == ha->pdev->bus) {
7928 kref_get(&cs84xx->kref);
7929 goto done;
7930 }
7931 }
7932
7933 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
7934 if (!cs84xx)
7935 goto done;
7936
7937 kref_init(&cs84xx->kref);
7938 spin_lock_init(&cs84xx->access_lock);
7939 mutex_init(&cs84xx->fw_update_mutex);
7940 cs84xx->bus = ha->pdev->bus;
7941
7942 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
7943done:
7944 mutex_unlock(&qla_cs84xx_mutex);
7945 return cs84xx;
7946}
7947
7948static void
7949__qla84xx_chip_release(struct kref *kref)
7950{
7951 struct qla_chip_state_84xx *cs84xx =
7952 container_of(kref, struct qla_chip_state_84xx, kref);
7953
7954 mutex_lock(&qla_cs84xx_mutex);
7955 list_del(&cs84xx->list);
7956 mutex_unlock(&qla_cs84xx_mutex);
7957 kfree(cs84xx);
7958}
7959
7960void
e315cd28 7961qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 7962{
e315cd28 7963 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7964 if (ha->cs84xx)
7965 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
7966}
7967
7968static int
e315cd28 7969qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 7970{
7971 int rval;
7972 uint16_t status[2];
e315cd28 7973 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7974
7975 mutex_lock(&ha->cs84xx->fw_update_mutex);
7976
e315cd28 7977 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 7978
7979 mutex_unlock(&ha->cs84xx->fw_update_mutex);
7980
7981 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
7982 QLA_SUCCESS;
7983}
3a03eb79
AV		 7984
7985/* 81XX Support **************************************************************/
7986
7987int
7988qla81xx_nvram_config(scsi_qla_host_t *vha)
7989{
7990 int rval;
7991 struct init_cb_81xx *icb;
7992 struct nvram_81xx *nv;
7993 uint32_t *dptr;
7994 uint8_t *dptr1, *dptr2;
7995 uint32_t chksum;
7996 uint16_t cnt;
7997 struct qla_hw_data *ha = vha->hw;
7998
7999 rval = QLA_SUCCESS;
8000 icb = (struct init_cb_81xx *)ha->init_cb;
8001 nv = ha->nvram;
8002
8003 /* Determine NVRAM starting address. */
8004 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 8005 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 8006 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
8007 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 8008
8009 /* Get VPD data into cache */
8010 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 8011 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
8012 ha->vpd_size);
3a03eb79
AV		 8013
8014 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 8015 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 8016 ha->nvram_size);
3d79038f 8017 dptr = (uint32_t *)nv;
da08ef5c
JC		 8018 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
8019 chksum += le32_to_cpu(*dptr);
3a03eb79 8020
7c3df132
SK		 8021 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
8022 "Contents of NVRAM:\n");
8023 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
8024 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 8025
8026 /* Bad NVRAM data, set defaults parameters. */
8027 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
8028 || nv->id[3] != ' ' ||
ad950360 8029 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 8030 /* Reset NVRAM data. */
7c3df132 8031 ql_log(ql_log_info, vha, 0x0073,
9e336520 8032 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 8033 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 8034 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 8035 ql_log(ql_log_info, vha, 0x0074,
8036 "Falling back to functioning (yet invalid -- WWPN) "
8037 "defaults.\n");
3a03eb79
AV		 8038
8039 /*
8040 * Set default initialization control block.
8041 */
8042 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 8043 nv->nvram_version = cpu_to_le16(ICB_VERSION);
8044 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 8045 nv->frame_payload_size = 2048;
ad950360
BVA		 8046 nv->execution_throttle = cpu_to_le16(0xFFFF);
8047 nv->exchange_count = cpu_to_le16(0);
3a03eb79 8048 nv->port_name[0] = 0x21;
f73cb695 8049 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 8050 nv->port_name[2] = 0x00;
8051 nv->port_name[3] = 0xe0;
8052 nv->port_name[4] = 0x8b;
8053 nv->port_name[5] = 0x1c;
8054 nv->port_name[6] = 0x55;
8055 nv->port_name[7] = 0x86;
8056 nv->node_name[0] = 0x20;
8057 nv->node_name[1] = 0x00;
8058 nv->node_name[2] = 0x00;
8059 nv->node_name[3] = 0xe0;
8060 nv->node_name[4] = 0x8b;
8061 nv->node_name[5] = 0x1c;
8062 nv->node_name[6] = 0x55;
8063 nv->node_name[7] = 0x86;
ad950360
BVA		 8064 nv->login_retry_count = cpu_to_le16(8);
8065 nv->interrupt_delay_timer = cpu_to_le16(0);
8066 nv->login_timeout = cpu_to_le16(0);
3a03eb79 8067 nv->firmware_options_1 =
ad950360
BVA		 8068 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
8069 nv->firmware_options_2 = cpu_to_le32(2 << 4);
8070 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
8071 nv->firmware_options_3 = cpu_to_le32(2 << 13);
8072 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
8073 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 8074 nv->reset_delay = 5;
ad950360
BVA		 8075 nv->max_luns_per_target = cpu_to_le16(128);
8076 nv->port_down_retry_count = cpu_to_le16(30);
8077 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 8078 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 8079 nv->enode_mac[1] = 0xC0;
8080 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 8081 nv->enode_mac[3] = 0x04;
8082 nv->enode_mac[4] = 0x05;
f73cb695 8083 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 8084
8085 rval = 1;
8086 }
8087
9e522cd8
AE		 8088 if (IS_T10_PI_CAPABLE(ha))
8089 nv->frame_payload_size &= ~7;
8090
aa230bc5
AE		 8091 qlt_81xx_config_nvram_stage1(vha, nv);
8092
3a03eb79 8093 /* Reset Initialization control block */
773120e4 8094 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 8095
8096 /* Copy 1st segment. */
8097 dptr1 = (uint8_t *)icb;
8098 dptr2 = (uint8_t *)&nv->version;
8099 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
8100 while (cnt--)
8101 *dptr1++ = *dptr2++;
8102
8103 icb->login_retry_count = nv->login_retry_count;
8104
8105 /* Copy 2nd segment. */
8106 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
8107 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
8108 cnt = (uint8_t *)&icb->reserved_5 -
8109 (uint8_t *)&icb->interrupt_delay_timer;
8110 while (cnt--)
8111 *dptr1++ = *dptr2++;
8112
8113 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
8114 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
8115 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 8116 icb->enode_mac[0] = 0x00;
8117 icb->enode_mac[1] = 0xC0;
8118 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 8119 icb->enode_mac[3] = 0x04;
8120 icb->enode_mac[4] = 0x05;
f73cb695 8121 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 8122 }
8123
b64b0e8f
AV		 8124 /* Use extended-initialization control block. */
8125 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
0eaaca4c 8126 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
3a03eb79
AV		 8127 /*
8128 * Setup driver NVRAM options.
8129 */
8130 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 8131 "QLE8XXX");
3a03eb79 8132
aa230bc5
AE		 8133 qlt_81xx_config_nvram_stage2(vha, icb);
8134
3a03eb79 8135 /* Use alternate WWN? */
ad950360 8136 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 8137 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
8138 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
8139 }
8140
8141 /* Prepare nodename */
ad950360 8142 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 8143 /*
8144 * Firmware will apply the following mask if the nodename was
8145 * not provided.
8146 */
8147 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
8148 icb->node_name[0] &= 0xF0;
8149 }
8150
8151 /* Set host adapter parameters. */
8152 ha->flags.disable_risc_code_load = 0;
8153 ha->flags.enable_lip_reset = 0;
8154 ha->flags.enable_lip_full_login =
8155 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
8156 ha->flags.enable_target_reset =
8157 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
8158 ha->flags.enable_led_scheme = 0;
8159 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
8160
8161 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
8162 (BIT_6 | BIT_5 | BIT_4)) >> 4;
8163
8164 /* save HBA serial number */
8165 ha->serial0 = icb->port_name[5];
8166 ha->serial1 = icb->port_name[6];
8167 ha->serial2 = icb->port_name[7];
8168 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
8169 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
8170
ad950360 8171 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 8172
8173 ha->retry_count = le16_to_cpu(nv->login_retry_count);
8174
8175 /* Set minimum login_timeout to 4 seconds. */
8176 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
8177 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
8178 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 8179 nv->login_timeout = cpu_to_le16(4);
3a03eb79 8180 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 8181
8182 /* Set minimum RATOV to 100 tenths of a second. */
8183 ha->r_a_tov = 100;
8184
8185 ha->loop_reset_delay = nv->reset_delay;
8186
8187 /* Link Down Timeout = 0:
8188 *
7ec0effd 8189 * When Port Down timer expires we will start returning
3a03eb79
AV		 8190 * I/O's to OS with "DID_NO_CONNECT".
8191 *
8192 * Link Down Timeout != 0:
8193 *
8194 * The driver waits for the link to come up after link down
8195 * before returning I/Os to OS with "DID_NO_CONNECT".
8196 */
8197 if (le16_to_cpu(nv->link_down_timeout) == 0) {
8198 ha->loop_down_abort_time =
8199 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
8200 } else {
8201 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
8202 ha->loop_down_abort_time =
8203 (LOOP_DOWN_TIME - ha->link_down_timeout);
8204 }
8205
8206 /* Need enough time to try and get the port back. */
8207 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
8208 if (qlport_down_retry)
8209 ha->port_down_retry_count = qlport_down_retry;
8210
8211 /* Set login_retry_count */
8212 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
8213 if (ha->port_down_retry_count ==
8214 le16_to_cpu(nv->port_down_retry_count) &&
8215 ha->port_down_retry_count > 3)
8216 ha->login_retry_count = ha->port_down_retry_count;
8217 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
8218 ha->login_retry_count = ha->port_down_retry_count;
8219 if (ql2xloginretrycount)
8220 ha->login_retry_count = ql2xloginretrycount;
8221
6246b8a1 8222 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 8223 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 8224 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 8225
3a03eb79
AV		 8226 /* Enable ZIO. */
8227 if (!vha->flags.init_done) {
8228 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
8229 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
8230 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
8231 le16_to_cpu(icb->interrupt_delay_timer): 2;
8232 }
ad950360 8233 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 8234 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
8235 vha->flags.process_response_queue = 0;
8236 if (ha->zio_mode != QLA_ZIO_DISABLED) {
8237 ha->zio_mode = QLA_ZIO_MODE_6;
8238
7c3df132 8239 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 8240 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 8241 ha->zio_mode,
8242 ha->zio_timer * 100);
3a03eb79
AV		 8243
8244 icb->firmware_options_2 |= cpu_to_le32(
8245 (uint32_t)ha->zio_mode);
8246 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
8247 vha->flags.process_response_queue = 1;
8248 }
8249
41dc529a 8250 /* enable RIDA Format2 */
48acad09 8251 icb->firmware_options_3 |= BIT_0;
41dc529a 8252
8777e431
QT		 8253 /* N2N: driver will initiate Login instead of FW */
8254 icb->firmware_options_3 |= BIT_8;
41dc529a 8255
edd05de1
DG		 8256 if (IS_QLA27XX(ha)) {
8257 icb->firmware_options_3 |= BIT_8;
8258 ql_dbg(ql_log_info, vha, 0x0075,
8259 "Enabling direct connection.\n");
8260 }
8261
3a03eb79 8262 if (rval) {
7c3df132
SK		 8263 ql_log(ql_log_warn, vha, 0x0076,
8264 "NVRAM configuration failed.\n");
3a03eb79
AV		 8265 }
8266 return (rval);
8267}
8268
a9083016
GM		 8269int
8270qla82xx_restart_isp(scsi_qla_host_t *vha)
8271{
8272 int status, rval;
a9083016
GM		 8273 struct qla_hw_data *ha = vha->hw;
8274 struct req_que *req = ha->req_q_map[0];
8275 struct rsp_que *rsp = ha->rsp_q_map[0];
8276 struct scsi_qla_host *vp;
feafb7b1 8277 unsigned long flags;
a9083016
GM		 8278
8279 status = qla2x00_init_rings(vha);
8280 if (!status) {
8281 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8282 ha->flags.chip_reset_done = 1;
8283
8284 status = qla2x00_fw_ready(vha);
8285 if (!status) {
a9083016
GM		 8286 /* Issue a marker after FW becomes ready. */
8287 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 8288 vha->flags.online = 1;
7108b76e 8289 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 8290 }
8291
8292 /* if no cable then assume it's good */
8293 if ((vha->device_flags & DFLG_NO_CABLE))
8294 status = 0;
a9083016
GM		 8295 }
8296
8297 if (!status) {
8298 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8299
8300 if (!atomic_read(&vha->loop_down_timer)) {
8301 /*
8302 * Issue marker command only when we are going
8303 * to start the I/O .
8304 */
8305 vha->marker_needed = 1;
8306 }
8307
a9083016
GM		 8308 ha->isp_ops->enable_intrs(ha);
8309
8310 ha->isp_abort_cnt = 0;
8311 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
8312
53296788 8313 /* Update the firmware version */
3173167f 8314 status = qla82xx_check_md_needed(vha);
53296788 8315
a9083016
GM		 8316 if (ha->fce) {
8317 ha->flags.fce_enabled = 1;
8318 memset(ha->fce, 0,
8319 fce_calc_size(ha->fce_bufs));
8320 rval = qla2x00_enable_fce_trace(vha,
8321 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
8322 &ha->fce_bufs);
8323 if (rval) {
cfb0919c 8324 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 8325 "Unable to reinitialize FCE (%d).\n",
8326 rval);
a9083016
GM		 8327 ha->flags.fce_enabled = 0;
8328 }
8329 }
8330
8331 if (ha->eft) {
8332 memset(ha->eft, 0, EFT_SIZE);
8333 rval = qla2x00_enable_eft_trace(vha,
8334 ha->eft_dma, EFT_NUM_BUFFERS);
8335 if (rval) {
cfb0919c 8336 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 8337 "Unable to reinitialize EFT (%d).\n",
8338 rval);
a9083016
GM		 8339 }
8340 }
a9083016
GM		 8341 }
8342
8343 if (!status) {
cfb0919c 8344 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 8345 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 8346
8347 spin_lock_irqsave(&ha->vport_slock, flags);
8348 list_for_each_entry(vp, &ha->vp_list, list) {
8349 if (vp->vp_idx) {
8350 atomic_inc(&vp->vref_count);
8351 spin_unlock_irqrestore(&ha->vport_slock, flags);
8352
a9083016 8353 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 8354
8355 spin_lock_irqsave(&ha->vport_slock, flags);
8356 atomic_dec(&vp->vref_count);
8357 }
a9083016 8358 }
feafb7b1
AE		 8359 spin_unlock_irqrestore(&ha->vport_slock, flags);
8360
a9083016 8361 } else {
cfb0919c 8362 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 8363 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 8364 }
8365
8366 return status;
8367}
8368
3a03eb79 8369void
ae97c91e 8370qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 8371{
ae97c91e
AV		 8372 struct qla_hw_data *ha = vha->hw;
8373
f198cafa
HM		 8374 /* Hold status IOCBs until ABTS response received. */
8375 if (ql2xfwholdabts)
8376 ha->fw_options[3] |= BIT_12;
8377
088d09d4
GM		 8378 /* Set Retry FLOGI in case of P2P connection */
8379 if (ha->operating_mode == P2P) {
8380 ha->fw_options[2] |= BIT_3;
8381 ql_dbg(ql_dbg_disc, vha, 0x2103,
8382 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
8383 __func__, ha->fw_options[2]);
8384 }
8385
41dc529a
QT		 8386 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
8387 if (ql2xmvasynctoatio) {
8388 if (qla_tgt_mode_enabled(vha) ||
8389 qla_dual_mode_enabled(vha))
8390 ha->fw_options[2] |= BIT_11;
8391 else
8392 ha->fw_options[2] &= ~BIT_11;
8393 }
8394
f7e761f5 8395 if (qla_tgt_mode_enabled(vha) ||
2da52737
QT		 8396 qla_dual_mode_enabled(vha)) {
8397 /* FW auto send SCSI status during */
8398 ha->fw_options[1] |= BIT_8;
8399 ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
8400
8401 /* FW perform Exchange validation */
f7e761f5 8402 ha->fw_options[2] |= BIT_4;
2da52737
QT		 8403 } else {
8404 ha->fw_options[1] &= ~BIT_8;
8405 ha->fw_options[10] &= 0x00ff;
8406
f7e761f5 8407 ha->fw_options[2] &= ~BIT_4;
2da52737 8408 }
f7e761f5 8409
41dc529a
QT		 8410 if (ql2xetsenable) {
8411 /* Enable ETS Burst. */
8412 memset(ha->fw_options, 0, sizeof(ha->fw_options));
8413 ha->fw_options[2] |= BIT_9;
8414 }
8415
83548fe2
QT		 8416 ql_dbg(ql_dbg_init, vha, 0x00e9,
8417 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
8418 __func__, ha->fw_options[1], ha->fw_options[2],
8419 ha->fw_options[3], vha->host->active_mode);
ae97c91e 8420
ae97c91e 8421 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 8422}
09ff701a
SR		 8423
8424/*
8425 * qla24xx_get_fcp_prio
8426 * Gets the fcp cmd priority value for the logged in port.
8427 * Looks for a match of the port descriptors within
8428 * each of the fcp prio config entries. If a match is found,
8429 * the tag (priority) value is returned.
8430 *
8431 * Input:
21090cbe 8432 * vha = scsi host structure pointer.
09ff701a
SR		 8433 * fcport = port structure pointer.
8434 *
8435 * Return:
6c452a45 8436 * non-zero (if found)
f28a0a96 8437 * -1 (if not found)
09ff701a
SR		 8438 *
8439 * Context:
8440 * Kernel context
8441 */
f28a0a96 8442static int
09ff701a
SR		 8443qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
8444{
8445 int i, entries;
8446 uint8_t pid_match, wwn_match;
f28a0a96 8447 int priority;
09ff701a
SR		 8448 uint32_t pid1, pid2;
8449 uint64_t wwn1, wwn2;
8450 struct qla_fcp_prio_entry *pri_entry;
8451 struct qla_hw_data *ha = vha->hw;
8452
8453 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 8454 return -1;
09ff701a 8455
f28a0a96 8456 priority = -1;
09ff701a
SR		 8457 entries = ha->fcp_prio_cfg->num_entries;
8458 pri_entry = &ha->fcp_prio_cfg->entry[0];
8459
8460 for (i = 0; i < entries; i++) {
8461 pid_match = wwn_match = 0;
8462
8463 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
8464 pri_entry++;
8465 continue;
8466 }
8467
8468 /* check source pid for a match */
8469 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
8470 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
8471 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
8472 if (pid1 == INVALID_PORT_ID)
8473 pid_match++;
8474 else if (pid1 == pid2)
8475 pid_match++;
8476 }
8477
8478 /* check destination pid for a match */
8479 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
8480 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
8481 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
8482 if (pid1 == INVALID_PORT_ID)
8483 pid_match++;
8484 else if (pid1 == pid2)
8485 pid_match++;
8486 }
8487
8488 /* check source WWN for a match */
8489 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
8490 wwn1 = wwn_to_u64(vha->port_name);
8491 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
8492 if (wwn2 == (uint64_t)-1)
8493 wwn_match++;
8494 else if (wwn1 == wwn2)
8495 wwn_match++;
8496 }
8497
8498 /* check destination WWN for a match */
8499 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
8500 wwn1 = wwn_to_u64(fcport->port_name);
8501 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
8502 if (wwn2 == (uint64_t)-1)
8503 wwn_match++;
8504 else if (wwn1 == wwn2)
8505 wwn_match++;
8506 }
8507
8508 if (pid_match == 2 || wwn_match == 2) {
8509 /* Found a matching entry */
8510 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
8511 priority = pri_entry->tag;
8512 break;
8513 }
8514
8515 pri_entry++;
8516 }
8517
8518 return priority;
8519}
8520
8521/*
8522 * qla24xx_update_fcport_fcp_prio
8523 * Activates fcp priority for the logged in fc port
8524 *
8525 * Input:
21090cbe 8526 * vha = scsi host structure pointer.
09ff701a
SR		 8527 * fcp = port structure pointer.
8528 *
8529 * Return:
8530 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8531 *
8532 * Context:
8533 * Kernel context.
8534 */
8535int
21090cbe 8536qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 8537{
8538 int ret;
f28a0a96 8539 int priority;
09ff701a
SR		 8540 uint16_t mb[5];
8541
21090cbe
MI		 8542 if (fcport->port_type != FCT_TARGET ||
8543 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 8544 return QLA_FUNCTION_FAILED;
8545
21090cbe 8546 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 8547 if (priority < 0)
8548 return QLA_FUNCTION_FAILED;
8549
7ec0effd 8550 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 8551 fcport->fcp_prio = priority & 0xf;
8552 return QLA_SUCCESS;
8553 }
8554
21090cbe 8555 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 8556 if (ret == QLA_SUCCESS) {
8557 if (fcport->fcp_prio != priority)
8558 ql_dbg(ql_dbg_user, vha, 0x709e,
8559 "Updated FCP_CMND priority - value=%d loop_id=%d "
8560 "port_id=%02x%02x%02x.\n", priority,
8561 fcport->loop_id, fcport->d_id.b.domain,
8562 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 8563 fcport->fcp_prio = priority & 0xf;
cfb0919c 8564 } else
7c3df132 8565 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 8566 "Unable to update FCP_CMND priority - ret=0x%x for "
8567 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
8568 fcport->d_id.b.domain, fcport->d_id.b.area,
8569 fcport->d_id.b.al_pa);
09ff701a
SR		 8570 return ret;
8571}
8572
8573/*
8574 * qla24xx_update_all_fcp_prio
8575 * Activates fcp priority for all the logged in ports
8576 *
8577 * Input:
8578 * ha = adapter block pointer.
8579 *
8580 * Return:
8581 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8582 *
8583 * Context:
8584 * Kernel context.
8585 */
8586int
8587qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
8588{
8589 int ret;
8590 fc_port_t *fcport;
8591
8592 ret = QLA_FUNCTION_FAILED;
8593 /* We need to set priority for all logged in ports */
8594 list_for_each_entry(fcport, &vha->vp_fcports, list)
8595 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
8596
8597 return ret;
8598}
d7459527 8599
82de802a
QT		 8600struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
8601 int vp_idx, bool startqp)
d7459527
MH		 8602{
8603 int rsp_id = 0;
8604 int req_id = 0;
8605 int i;
8606 struct qla_hw_data *ha = vha->hw;
8607 uint16_t qpair_id = 0;
8608 struct qla_qpair *qpair = NULL;
8609 struct qla_msix_entry *msix;
8610
8611 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
8612 ql_log(ql_log_warn, vha, 0x00181,
8613 "FW/Driver is not multi-queue capable.\n");
8614 return NULL;
8615 }
8616
c38d1baf 8617 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 8618 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
8619 if (qpair == NULL) {
8620 ql_log(ql_log_warn, vha, 0x0182,
8621 "Failed to allocate memory for queue pair.\n");
8622 return NULL;
8623 }
8624 memset(qpair, 0, sizeof(struct qla_qpair));
8625
8626 qpair->hw = vha->hw;
25ff6af1 8627 qpair->vha = vha;
82de802a
QT		 8628 qpair->qp_lock_ptr = &qpair->qp_lock;
8629 spin_lock_init(&qpair->qp_lock);
af7bb382 8630 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d7459527
MH		 8631
8632 /* Assign available que pair id */
8633 mutex_lock(&ha->mq_lock);
8634 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 8635 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 8636 mutex_unlock(&ha->mq_lock);
8637 ql_log(ql_log_warn, vha, 0x0183,
8638 "No resources to create additional q pair.\n");
8639 goto fail_qid_map;
8640 }
b95b9452 8641 ha->num_qpairs++;
d7459527
MH		 8642 set_bit(qpair_id, ha->qpair_qid_map);
8643 ha->queue_pair_map[qpair_id] = qpair;
8644 qpair->id = qpair_id;
8645 qpair->vp_idx = vp_idx;
e6373f33 8646 qpair->fw_started = ha->flags.fw_started;
e326d22a 8647 INIT_LIST_HEAD(&qpair->hints_list);
7c3f8fd1
QT		 8648 qpair->chip_reset = ha->base_qpair->chip_reset;
8649 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
8650 qpair->enable_explicit_conf =
8651 ha->base_qpair->enable_explicit_conf;
d7459527
MH		 8652
8653 for (i = 0; i < ha->msix_count; i++) {
093df737 8654 msix = &ha->msix_entries[i];
d7459527
MH		 8655 if (msix->in_use)
8656 continue;
8657 qpair->msix = msix;
83548fe2 8658 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
d7459527
MH		 8659 "Vector %x selected for qpair\n", msix->vector);
8660 break;
8661 }
8662 if (!qpair->msix) {
8663 ql_log(ql_log_warn, vha, 0x0184,
8664 "Out of MSI-X vectors!.\n");
8665 goto fail_msix;
8666 }
8667
8668 qpair->msix->in_use = 1;
8669 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
8abfa9e2
QT		 8670 qpair->pdev = ha->pdev;
8671 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
8672 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
d7459527
MH		 8673
8674 mutex_unlock(&ha->mq_lock);
8675
8676 /* Create response queue first */
82de802a 8677 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
d7459527
MH		 8678 if (!rsp_id) {
8679 ql_log(ql_log_warn, vha, 0x0185,
8680 "Failed to create response queue.\n");
8681 goto fail_rsp;
8682 }
8683
8684 qpair->rsp = ha->rsp_q_map[rsp_id];
8685
8686 /* Create request queue */
82de802a
QT		 8687 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
8688 startqp);
d7459527
MH		 8689 if (!req_id) {
8690 ql_log(ql_log_warn, vha, 0x0186,
8691 "Failed to create request queue.\n");
8692 goto fail_req;
8693 }
8694
8695 qpair->req = ha->req_q_map[req_id];
8696 qpair->rsp->req = qpair->req;
82de802a 8697 qpair->rsp->qpair = qpair;
e326d22a
QT		 8698 /* init qpair to this cpu. Will adjust at run time. */
8699 qla_cpu_update(qpair, smp_processor_id());
d7459527
MH		 8700
8701 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
8702 if (ha->fw_attributes & BIT_4)
8703 qpair->difdix_supported = 1;
8704 }
8705
8706 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
8707 if (!qpair->srb_mempool) {
83548fe2 8708 ql_log(ql_log_warn, vha, 0xd036,
d7459527
MH		 8709 "Failed to create srb mempool for qpair %d\n",
8710 qpair->id);
8711 goto fail_mempool;
8712 }
8713
8714 /* Mark as online */
8715 qpair->online = 1;
8716
8717 if (!vha->flags.qpairs_available)
8718 vha->flags.qpairs_available = 1;
8719
8720 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
8721 "Request/Response queue pair created, id %d\n",
8722 qpair->id);
8723 ql_dbg(ql_dbg_init, vha, 0x0187,
8724 "Request/Response queue pair created, id %d\n",
8725 qpair->id);
8726 }
8727 return qpair;
8728
8729fail_mempool:
8730fail_req:
8731 qla25xx_delete_rsp_que(vha, qpair->rsp);
8732fail_rsp:
8733 mutex_lock(&ha->mq_lock);
8734 qpair->msix->in_use = 0;
8735 list_del(&qpair->qp_list_elem);
8736 if (list_empty(&vha->qp_list))
8737 vha->flags.qpairs_available = 0;
8738fail_msix:
8739 ha->queue_pair_map[qpair_id] = NULL;
8740 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 8741 ha->num_qpairs--;
d7459527
MH		 8742 mutex_unlock(&ha->mq_lock);
8743fail_qid_map:
8744 kfree(qpair);
8745 return NULL;
8746}
8747
8748int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
8749{
d65237c7 8750 int ret = QLA_FUNCTION_FAILED;
d7459527
MH		 8751 struct qla_hw_data *ha = qpair->hw;
8752
8753 qpair->delete_in_progress = 1;
8754 while (atomic_read(&qpair->ref_count))
8755 msleep(500);
8756
8757 ret = qla25xx_delete_req_que(vha, qpair->req);
8758 if (ret != QLA_SUCCESS)
8759 goto fail;
7867b98d 8760
d7459527
MH		 8761 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
8762 if (ret != QLA_SUCCESS)
8763 goto fail;
8764
8765 mutex_lock(&ha->mq_lock);
8766 ha->queue_pair_map[qpair->id] = NULL;
8767 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 8768 ha->num_qpairs--;
d7459527 8769 list_del(&qpair->qp_list_elem);
d65237c7 8770 if (list_empty(&vha->qp_list)) {
d7459527 8771 vha->flags.qpairs_available = 0;
d65237c7
SC		 8772 vha->flags.qpairs_req_created = 0;
8773 vha->flags.qpairs_rsp_created = 0;
8774 }
d7459527
MH		 8775 mempool_destroy(qpair->srb_mempool);
8776 kfree(qpair);
8777 mutex_unlock(&ha->mq_lock);
8778
8779 return QLA_SUCCESS;
8780fail:
8781 return ret;
8782}
Linux 6.x block layer and io_uring tree(s)