projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
scsi: qla2xxx: Remove unused argument from qlt_schedule_sess_for_deletion()
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
a5d42f4c 39static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
726b8548
QT		 40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
a5d42f4c
DG		 42static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
43 struct event_arg *);
a4239945 44static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
4d4df193 45
ac280b67
AV		 46/* SRB Extensions ---------------------------------------------------------- */
47
9ba56b95 48void
8e5f4ba0 49qla2x00_sp_timeout(struct timer_list *t)
ac280b67 50{
8e5f4ba0 51 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
4916392b 52 struct srb_iocb *iocb;
25ff6af1 53 scsi_qla_host_t *vha = sp->vha;
ac280b67
AV		 54 struct req_que *req;
55 unsigned long flags;
56
25ff6af1
JC		 57 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
58 req = vha->hw->req_q_map[0];
ac280b67 59 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 60 iocb = &sp->u.iocb_cmd;
4916392b 61 iocb->timeout(sp);
045d6ea2
GM		 62 if (sp->type != SRB_ELS_DCMD)
63 sp->free(sp);
25ff6af1 64 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
ac280b67
AV		 65}
66
9ba56b95 67void
25ff6af1 68qla2x00_sp_free(void *ptr)
ac280b67 69{
25ff6af1 70 srb_t *sp = ptr;
9ba56b95 71 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 72
4d97cc53 73 del_timer(&iocb->timer);
25ff6af1 74 qla2x00_rel_sp(sp);
ac280b67
AV		 75}
76
ac280b67
AV		 77/* Asynchronous Login/Logout Routines -------------------------------------- */
78
a9b6f722 79unsigned long
5b91490e
AV		 80qla2x00_get_async_timeout(struct scsi_qla_host *vha)
81{
82 unsigned long tmo;
83 struct qla_hw_data *ha = vha->hw;
84
85 /* Firmware should use switch negotiated r_a_tov for timeout. */
86 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 87 if (IS_QLAFX00(ha)) {
88 tmo = FX00_DEF_RATOV * 2;
89 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 90 /*
91 * Except for earlier ISPs where the timeout is seeded from the
92 * initialization control block.
93 */
94 tmo = ha->login_timeout;
95 }
96 return tmo;
97}
ac280b67 98
726b8548 99void
9ba56b95 100qla2x00_async_iocb_timeout(void *data)
ac280b67 101{
25ff6af1 102 srb_t *sp = data;
ac280b67 103 fc_port_t *fcport = sp->fcport;
726b8548
QT		 104 struct srb_iocb *lio = &sp->u.iocb_cmd;
105 struct event_arg ea;
ac280b67 106
5c25d451
QT		 107 if (fcport) {
108 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
109 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
110 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
111
6d674927 112 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
5c25d451
QT		 113 } else {
114 pr_info("Async-%s timeout - hdl=%x.\n",
115 sp->name, sp->handle);
116 }
726b8548
QT		 117
118 switch (sp->type) {
119 case SRB_LOGIN_CMD:
6ac52608
AV		 120 /* Retry as needed. */
121 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
122 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
123 QLA_LOGIO_LOGIN_RETRIED : 0;
726b8548
QT		 124 memset(&ea, 0, sizeof(ea));
125 ea.event = FCME_PLOGI_DONE;
126 ea.fcport = sp->fcport;
127 ea.data[0] = lio->u.logio.data[0];
128 ea.data[1] = lio->u.logio.data[1];
129 ea.sp = sp;
130 qla24xx_handle_plogi_done_event(fcport->vha, &ea);
131 break;
132 case SRB_LOGOUT_CMD:
a6ca8878 133 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
726b8548
QT		 134 break;
135 case SRB_CT_PTHRU_CMD:
136 case SRB_MB_IOCB:
137 case SRB_NACK_PLOGI:
138 case SRB_NACK_PRLI:
139 case SRB_NACK_LOGO:
2853192e 140 case SRB_CTRL_VP:
25ff6af1 141 sp->done(sp, QLA_FUNCTION_TIMEOUT);
726b8548 142 break;
6ac52608 143 }
ac280b67
AV		 144}
145
99b0bec7 146static void
25ff6af1 147qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 148{
25ff6af1
JC		 149 srb_t *sp = ptr;
150 struct scsi_qla_host *vha = sp->vha;
9ba56b95 151 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 152 struct event_arg ea;
9ba56b95 153
83548fe2 154 ql_dbg(ql_dbg_disc, vha, 0x20dd,
25ff6af1 155 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548 156
6d674927
QT		 157 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
158
726b8548
QT		 159 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
160 memset(&ea, 0, sizeof(ea));
161 ea.event = FCME_PLOGI_DONE;
162 ea.fcport = sp->fcport;
163 ea.data[0] = lio->u.logio.data[0];
164 ea.data[1] = lio->u.logio.data[1];
165 ea.iop[0] = lio->u.logio.iop[0];
166 ea.iop[1] = lio->u.logio.iop[1];
167 ea.sp = sp;
168 qla2x00_fcport_event_handler(vha, &ea);
169 }
9ba56b95 170
25ff6af1 171 sp->free(sp);
99b0bec7
AV		 172}
173
ac280b67
AV		 174int
175qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
176 uint16_t *data)
177{
ac280b67 178 srb_t *sp;
4916392b 179 struct srb_iocb *lio;
726b8548
QT		 180 int rval = QLA_FUNCTION_FAILED;
181
182 if (!vha->flags.online)
183 goto done;
184
9ba56b95 185 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 186 if (!sp)
187 goto done;
188
726b8548
QT		 189 fcport->flags |= FCF_ASYNC_SENT;
190 fcport->logout_completed = 0;
191
a4239945 192 fcport->disc_state = DSC_LOGIN_PEND;
9ba56b95
GM		 193 sp->type = SRB_LOGIN_CMD;
194 sp->name = "login";
a4239945
QT		 195 sp->gen1 = fcport->rscn_gen;
196 sp->gen2 = fcport->login_gen;
9ba56b95
GM		 197 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
198
199 lio = &sp->u.iocb_cmd;
3822263e 200 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 201 sp->done = qla2x00_async_login_sp_done;
4916392b 202 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
a5d42f4c
DG		 203
204 if (fcport->fc4f_nvme)
205 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
206
ac280b67 207 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 208 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 209 rval = qla2x00_start_sp(sp);
080c9517 210 if (rval != QLA_SUCCESS) {
080c9517
CD		 211 fcport->flags |= FCF_LOGIN_NEEDED;
212 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 213 goto done_free_sp;
080c9517 214 }
ac280b67 215
7c3df132 216 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 217 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
218 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 219 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
220 fcport->login_retry);
ac280b67
AV		 221 return rval;
222
223done_free_sp:
25ff6af1 224 sp->free(sp);
726b8548 225 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 226done:
ac280b67
AV		 227 return rval;
228}
229
99b0bec7 230static void
25ff6af1 231qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 232{
25ff6af1 233 srb_t *sp = ptr;
9ba56b95 234 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95 235
6d674927 236 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
25ff6af1
JC		 237 if (!test_bit(UNLOADING, &sp->vha->dpc_flags))
238 qla2x00_post_async_logout_done_work(sp->vha, sp->fcport,
9ba56b95 239 lio->u.logio.data);
25ff6af1 240 sp->free(sp);
99b0bec7
AV		 241}
242
ac280b67
AV		 243int
244qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
245{
ac280b67 246 srb_t *sp;
4916392b 247 struct srb_iocb *lio;
3dbec59b
QT		 248 int rval = QLA_FUNCTION_FAILED;
249
250 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
251 return rval;
ac280b67 252
726b8548 253 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 254 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 255 if (!sp)
256 goto done;
257
9ba56b95
GM		 258 sp->type = SRB_LOGOUT_CMD;
259 sp->name = "logout";
260 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
261
262 lio = &sp->u.iocb_cmd;
3822263e 263 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 264 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 265 rval = qla2x00_start_sp(sp);
266 if (rval != QLA_SUCCESS)
267 goto done_free_sp;
268
7c3df132 269 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 270 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 271 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 272 fcport->d_id.b.area, fcport->d_id.b.al_pa,
273 fcport->port_name);
ac280b67
AV		 274 return rval;
275
276done_free_sp:
25ff6af1 277 sp->free(sp);
ac280b67 278done:
726b8548 279 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 280 return rval;
281}
11aea16a
QT		 282
283void
284qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
285 uint16_t *data)
286{
287 /* Don't re-login in target mode */
288 if (!fcport->tgt_session)
289 qla2x00_mark_device_lost(vha, fcport, 1, 0);
290 qlt_logo_completion_handler(fcport, data[0]);
291}
292
293static void
294qla2x00_async_prlo_sp_done(void *s, int res)
295{
296 srb_t *sp = (srb_t *)s;
297 struct srb_iocb *lio = &sp->u.iocb_cmd;
298 struct scsi_qla_host *vha = sp->vha;
299
300 if (!test_bit(UNLOADING, &vha->dpc_flags))
301 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
302 lio->u.logio.data);
303 sp->free(sp);
304}
305
306int
307qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
308{
309 srb_t *sp;
310 struct srb_iocb *lio;
311 int rval;
312
313 rval = QLA_FUNCTION_FAILED;
314 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
315 if (!sp)
316 goto done;
317
318 sp->type = SRB_PRLO_CMD;
319 sp->name = "prlo";
320 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
321
322 lio = &sp->u.iocb_cmd;
323 lio->timeout = qla2x00_async_iocb_timeout;
324 sp->done = qla2x00_async_prlo_sp_done;
325 rval = qla2x00_start_sp(sp);
326 if (rval != QLA_SUCCESS)
327 goto done_free_sp;
328
329 ql_dbg(ql_dbg_disc, vha, 0x2070,
330 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
331 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
332 fcport->d_id.b.area, fcport->d_id.b.al_pa);
333 return rval;
334
335done_free_sp:
336 sp->free(sp);
337done:
338 return rval;
339}
340
f13515ac
QT		 341static
342void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
343{
0616e965
QT		 344 struct fc_port *fcport = ea->fcport;
345
346 ql_dbg(ql_dbg_disc, vha, 0x20d2,
347 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
348 __func__, fcport->port_name, fcport->disc_state,
349 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
350 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
351
352 if (ea->data[0] != MBS_COMMAND_COMPLETE) {
a4239945
QT		 353 ql_dbg(ql_dbg_disc, vha, 0x2066,
354 "%s %8phC: adisc fail: post delete\n",
355 __func__, ea->fcport->port_name);
94cff6e1 356 qlt_schedule_sess_for_deletion(ea->fcport);
a4239945
QT		 357 return;
358 }
a4239945
QT		 359
360 if (ea->fcport->disc_state == DSC_DELETE_PEND)
361 return;
362
363 if (ea->sp->gen2 != ea->fcport->login_gen) {
364 /* target side must have changed it. */
365 ql_dbg(ql_dbg_disc, vha, 0x20d3,
0616e965
QT		 366 "%s %8phC generation changed\n",
367 __func__, ea->fcport->port_name);
a4239945
QT		 368 return;
369 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
370 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
371 __func__, __LINE__, ea->fcport->port_name);
372 qla24xx_post_gidpn_work(vha, ea->fcport);
373 return;
374 }
375
376 __qla24xx_handle_gpdb_event(vha, ea);
f13515ac 377}
ac280b67 378
5ff1d584 379static void
25ff6af1 380qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 381{
25ff6af1
JC		 382 srb_t *sp = ptr;
383 struct scsi_qla_host *vha = sp->vha;
f13515ac 384 struct event_arg ea;
0616e965 385 struct srb_iocb *lio = &sp->u.iocb_cmd;
f13515ac
QT		 386
387 ql_dbg(ql_dbg_disc, vha, 0x2066,
388 "Async done-%s res %x %8phC\n",
389 sp->name, res, sp->fcport->port_name);
390
391 memset(&ea, 0, sizeof(ea));
392 ea.event = FCME_ADISC_DONE;
393 ea.rc = res;
0616e965
QT		 394 ea.data[0] = lio->u.logio.data[0];
395 ea.data[1] = lio->u.logio.data[1];
396 ea.iop[0] = lio->u.logio.iop[0];
397 ea.iop[1] = lio->u.logio.iop[1];
f13515ac
QT		 398 ea.fcport = sp->fcport;
399 ea.sp = sp;
400
401 qla2x00_fcport_event_handler(vha, &ea);
9ba56b95 402
25ff6af1 403 sp->free(sp);
5ff1d584
AV		 404}
405
406int
407qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
408 uint16_t *data)
409{
5ff1d584 410 srb_t *sp;
4916392b 411 struct srb_iocb *lio;
5ff1d584
AV		 412 int rval;
413
414 rval = QLA_FUNCTION_FAILED;
726b8548 415 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 416 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 417 if (!sp)
418 goto done;
419
9ba56b95
GM		 420 sp->type = SRB_ADISC_CMD;
421 sp->name = "adisc";
422 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
423
424 lio = &sp->u.iocb_cmd;
3822263e 425 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 426 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 427 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 428 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 429 rval = qla2x00_start_sp(sp);
430 if (rval != QLA_SUCCESS)
431 goto done_free_sp;
432
7c3df132 433 ql_dbg(ql_dbg_disc, vha, 0x206f,
f13515ac
QT		 434 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
435 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
5ff1d584
AV		 436 return rval;
437
438done_free_sp:
25ff6af1 439 sp->free(sp);
5ff1d584 440done:
726b8548 441 fcport->flags &= ~FCF_ASYNC_SENT;
f13515ac 442 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 443 return rval;
444}
445
446static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
447 struct event_arg *ea)
448{
449 fc_port_t *fcport, *conflict_fcport;
450 struct get_name_list_extended *e;
451 u16 i, n, found = 0, loop_id;
452 port_id_t id;
453 u64 wwn;
a4239945
QT		 454 u16 data[2];
455 u8 current_login_state;
726b8548
QT		 456
457 fcport = ea->fcport;
f352eeb7
QT		 458 ql_dbg(ql_dbg_disc, vha, 0xffff,
459 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n",
460 __func__, fcport->port_name, fcport->disc_state,
461 fcport->fw_login_state, ea->rc,
462 fcport->login_gen, fcport->last_login_gen,
463 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id);
726b8548 464
a4239945
QT		 465 if (fcport->disc_state == DSC_DELETE_PEND)
466 return;
467
726b8548
QT		 468 if (ea->rc) { /* rval */
469 if (fcport->login_retry == 0) {
470 fcport->login_retry = vha->hw->login_retry_count;
83548fe2
QT		 471 ql_dbg(ql_dbg_disc, vha, 0x20de,
472 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
473 fcport->port_name, fcport->login_retry);
726b8548
QT		 474 }
475 return;
476 }
477
478 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 479 ql_dbg(ql_dbg_disc, vha, 0x20df,
726b8548
QT		 480 "%s %8phC rscn gen changed rscn %d|%d \n",
481 __func__, fcport->port_name,
482 fcport->last_rscn_gen, fcport->rscn_gen);
483 qla24xx_post_gidpn_work(vha, fcport);
484 return;
485 } else if (fcport->last_login_gen != fcport->login_gen) {
83548fe2 486 ql_dbg(ql_dbg_disc, vha, 0x20e0,
f352eeb7
QT		 487 "%s %8phC login gen changed\n",
488 __func__, fcport->port_name);
726b8548
QT		 489 return;
490 }
491
492 n = ea->data[0] / sizeof(struct get_name_list_extended);
493
83548fe2 494 ql_dbg(ql_dbg_disc, vha, 0x20e1,
726b8548
QT		 495 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
496 __func__, __LINE__, fcport->port_name, n,
497 fcport->d_id.b.domain, fcport->d_id.b.area,
498 fcport->d_id.b.al_pa, fcport->loop_id);
499
500 for (i = 0; i < n; i++) {
501 e = &vha->gnl.l[i];
502 wwn = wwn_to_u64(e->port_name);
503
504 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
505 continue;
506
507 found = 1;
508 id.b.domain = e->port_id[2];
509 id.b.area = e->port_id[1];
510 id.b.al_pa = e->port_id[0];
511 id.b.rsvd_1 = 0;
512
513 loop_id = le16_to_cpu(e->nport_handle);
514 loop_id = (loop_id & 0x7fff);
515
83548fe2
QT		 516 ql_dbg(ql_dbg_disc, vha, 0x20e2,
517 "%s found %8phC CLS [%d|%d] ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
518 __func__, fcport->port_name,
519 e->current_login_state, fcport->fw_login_state,
520 id.b.domain, id.b.area, id.b.al_pa,
521 fcport->d_id.b.domain, fcport->d_id.b.area,
522 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
726b8548
QT		 523
524 if ((id.b24 != fcport->d_id.b24) ||
525 ((fcport->loop_id != FC_NO_LOOP_ID) &&
526 (fcport->loop_id != loop_id))) {
83548fe2
QT		 527 ql_dbg(ql_dbg_disc, vha, 0x20e3,
528 "%s %d %8phC post del sess\n",
529 __func__, __LINE__, fcport->port_name);
94cff6e1 530 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 531 return;
532 }
533
534 fcport->loop_id = loop_id;
535
536 wwn = wwn_to_u64(fcport->port_name);
537 qlt_find_sess_invalidate_other(vha, wwn,
538 id, loop_id, &conflict_fcport);
539
540 if (conflict_fcport) {
541 /*
542 * Another share fcport share the same loop_id &
543 * nport id. Conflict fcport needs to finish
544 * cleanup before this fcport can proceed to login.
545 */
546 conflict_fcport->conflict = fcport;
547 fcport->login_pause = 1;
548 }
549
a5d42f4c
DG		 550 if (fcport->fc4f_nvme)
551 current_login_state = e->current_login_state >> 4;
552 else
553 current_login_state = e->current_login_state & 0xf;
554
555 switch (current_login_state) {
726b8548 556 case DSC_LS_PRLI_COMP:
83548fe2
QT		 557 ql_dbg(ql_dbg_disc, vha, 0x20e4,
558 "%s %d %8phC post gpdb\n",
559 __func__, __LINE__, fcport->port_name);
a4239945
QT		 560
561 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
562 fcport->port_type = FCT_INITIATOR;
563 else
564 fcport->port_type = FCT_TARGET;
565
566 data[0] = data[1] = 0;
567 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548 568 break;
726b8548
QT		 569 case DSC_LS_PORT_UNAVAIL:
570 default:
571 if (fcport->loop_id == FC_NO_LOOP_ID) {
572 qla2x00_find_new_loop_id(vha, fcport);
573 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
574 }
83548fe2
QT		 575 ql_dbg(ql_dbg_disc, vha, 0x20e5,
576 "%s %d %8phC\n",
577 __func__, __LINE__, fcport->port_name);
726b8548
QT		 578 qla24xx_fcport_handle_login(vha, fcport);
579 break;
580 }
581 }
582
583 if (!found) {
584 /* fw has no record of this port */
040036bb
QT		 585 for (i = 0; i < n; i++) {
586 e = &vha->gnl.l[i];
587 id.b.domain = e->port_id[0];
588 id.b.area = e->port_id[1];
589 id.b.al_pa = e->port_id[2];
590 id.b.rsvd_1 = 0;
591 loop_id = le16_to_cpu(e->nport_handle);
592
593 if (fcport->d_id.b24 == id.b24) {
594 conflict_fcport =
595 qla2x00_find_fcport_by_wwpn(vha,
596 e->port_name, 0);
597 ql_dbg(ql_dbg_disc, vha, 0x20e6,
598 "%s %d %8phC post del sess\n",
599 __func__, __LINE__,
600 conflict_fcport->port_name);
601 qlt_schedule_sess_for_deletion
94cff6e1 602 (conflict_fcport);
726b8548 603 }
040036bb
QT		 604
605 /* FW already picked this loop id for another fcport */
606 if (fcport->loop_id == loop_id)
607 fcport->loop_id = FC_NO_LOOP_ID;
726b8548
QT		 608 }
609 qla24xx_fcport_handle_login(vha, fcport);
610 }
611} /* gnl_event */
612
613static void
25ff6af1 614qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 615{
25ff6af1
JC		 616 struct srb *sp = s;
617 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 618 unsigned long flags;
619 struct fc_port *fcport = NULL, *tf;
620 u16 i, n = 0, loop_id;
621 struct event_arg ea;
622 struct get_name_list_extended *e;
623 u64 wwn;
624 struct list_head h;
a4239945 625 bool found = false;
726b8548 626
83548fe2 627 ql_dbg(ql_dbg_disc, vha, 0x20e7,
726b8548
QT		 628 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
629 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
630 sp->u.iocb_cmd.u.mbx.in_mb[2]);
631
632 memset(&ea, 0, sizeof(ea));
633 ea.sp = sp;
634 ea.rc = res;
635 ea.event = FCME_GNL_DONE;
636
637 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
638 sizeof(struct get_name_list_extended)) {
639 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
640 sizeof(struct get_name_list_extended);
641 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
642 }
643
644 for (i = 0; i < n; i++) {
645 e = &vha->gnl.l[i];
646 loop_id = le16_to_cpu(e->nport_handle);
647 /* mask out reserve bit */
648 loop_id = (loop_id & 0x7fff);
649 set_bit(loop_id, vha->hw->loop_id_map);
650 wwn = wwn_to_u64(e->port_name);
651
83548fe2 652 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
726b8548
QT		 653 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
654 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
655 e->port_id[0], e->current_login_state, e->last_login_state,
656 (loop_id & 0x7fff));
657 }
658
659 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
660 vha->gnl.sent = 0;
661
662 INIT_LIST_HEAD(&h);
663 fcport = tf = NULL;
664 if (!list_empty(&vha->gnl.fcports))
665 list_splice_init(&vha->gnl.fcports, &h);
666
667 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
668 list_del_init(&fcport->gnl_entry);
6d674927 669 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
726b8548
QT		 670 ea.fcport = fcport;
671
672 qla2x00_fcport_event_handler(vha, &ea);
673 }
674
a4239945
QT		 675 /* create new fcport if fw has knowledge of new sessions */
676 for (i = 0; i < n; i++) {
677 port_id_t id;
678 u64 wwnn;
679
680 e = &vha->gnl.l[i];
681 wwn = wwn_to_u64(e->port_name);
682
683 found = false;
684 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
685 if (!memcmp((u8 *)&wwn, fcport->port_name,
686 WWN_SIZE)) {
687 found = true;
688 break;
689 }
690 }
691
cf055fb0 692 id.b.domain = e->port_id[2];
a4239945 693 id.b.area = e->port_id[1];
cf055fb0 694 id.b.al_pa = e->port_id[0];
a4239945
QT		 695 id.b.rsvd_1 = 0;
696
697 if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
698 ql_dbg(ql_dbg_disc, vha, 0x2065,
cf055fb0
QT		 699 "%s %d %8phC %06x post new sess\n",
700 __func__, __LINE__, (u8 *)&wwn, id.b24);
a4239945
QT		 701 wwnn = wwn_to_u64(e->node_name);
702 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
703 (u8 *)&wwnn, NULL, FC4_TYPE_UNKNOWN);
704 }
705 }
706
726b8548
QT		 707 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
708
25ff6af1 709 sp->free(sp);
726b8548
QT		 710}
711
712int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
713{
714 srb_t *sp;
715 struct srb_iocb *mbx;
716 int rval = QLA_FUNCTION_FAILED;
717 unsigned long flags;
718 u16 *mb;
719
3dbec59b
QT		 720 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
721 return rval;
726b8548 722
83548fe2 723 ql_dbg(ql_dbg_disc, vha, 0x20d9,
726b8548
QT		 724 "Async-gnlist WWPN %8phC \n", fcport->port_name);
725
726 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 727 fcport->disc_state = DSC_GNL;
728 fcport->last_rscn_gen = fcport->rscn_gen;
729 fcport->last_login_gen = fcport->login_gen;
730
731 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
732 if (vha->gnl.sent) {
733 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
3dbec59b 734 return QLA_SUCCESS;
726b8548
QT		 735 }
736 vha->gnl.sent = 1;
737 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
738
739 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
740 if (!sp)
741 goto done;
3dbec59b
QT		 742
743 fcport->flags |= FCF_ASYNC_SENT;
726b8548
QT		 744 sp->type = SRB_MB_IOCB;
745 sp->name = "gnlist";
746 sp->gen1 = fcport->rscn_gen;
747 sp->gen2 = fcport->login_gen;
748
749 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
750
751 mb = sp->u.iocb_cmd.u.mbx.out_mb;
752 mb[0] = MBC_PORT_NODE_NAME_LIST;
753 mb[1] = BIT_2 | BIT_3;
754 mb[2] = MSW(vha->gnl.ldma);
755 mb[3] = LSW(vha->gnl.ldma);
756 mb[6] = MSW(MSD(vha->gnl.ldma));
757 mb[7] = LSW(MSD(vha->gnl.ldma));
758 mb[8] = vha->gnl.size;
759 mb[9] = vha->vp_idx;
760
761 mbx = &sp->u.iocb_cmd;
762 mbx->timeout = qla2x00_async_iocb_timeout;
763
764 sp->done = qla24xx_async_gnl_sp_done;
765
766 rval = qla2x00_start_sp(sp);
767 if (rval != QLA_SUCCESS)
768 goto done_free_sp;
769
83548fe2
QT		 770 ql_dbg(ql_dbg_disc, vha, 0x20da,
771 "Async-%s - OUT WWPN %8phC hndl %x\n",
772 sp->name, fcport->port_name, sp->handle);
726b8548
QT		 773
774 return rval;
775
776done_free_sp:
25ff6af1 777 sp->free(sp);
726b8548 778 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 779done:
726b8548
QT		 780 return rval;
781}
782
783int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
784{
785 struct qla_work_evt *e;
786
787 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
788 if (!e)
789 return QLA_FUNCTION_FAILED;
790
791 e->u.fcport.fcport = fcport;
6d674927 792 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 793 return qla2x00_post_work(vha, e);
794}
795
796static
25ff6af1 797void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 798{
25ff6af1
JC		 799 struct srb *sp = s;
800 struct scsi_qla_host *vha = sp->vha;
726b8548 801 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 802 fc_port_t *fcport = sp->fcport;
803 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
726b8548
QT		 804 struct event_arg ea;
805
83548fe2 806 ql_dbg(ql_dbg_disc, vha, 0x20db,
726b8548
QT		 807 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
808 sp->name, res, fcport->port_name, mb[1], mb[2]);
809
6d674927 810 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
726b8548 811
726b8548
QT		 812 memset(&ea, 0, sizeof(ea));
813 ea.event = FCME_GPDB_DONE;
726b8548
QT		 814 ea.fcport = fcport;
815 ea.sp = sp;
816
817 qla2x00_fcport_event_handler(vha, &ea);
818
819 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
820 sp->u.iocb_cmd.u.mbx.in_dma);
821
25ff6af1 822 sp->free(sp);
726b8548
QT		 823}
824
a5d42f4c
DG		 825static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
826{
827 struct qla_work_evt *e;
828
829 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
830 if (!e)
831 return QLA_FUNCTION_FAILED;
832
833 e->u.fcport.fcport = fcport;
834
835 return qla2x00_post_work(vha, e);
836}
837
838static void
839qla2x00_async_prli_sp_done(void *ptr, int res)
840{
841 srb_t *sp = ptr;
842 struct scsi_qla_host *vha = sp->vha;
843 struct srb_iocb *lio = &sp->u.iocb_cmd;
844 struct event_arg ea;
845
846 ql_dbg(ql_dbg_disc, vha, 0x2129,
847 "%s %8phC res %d \n", __func__,
848 sp->fcport->port_name, res);
849
850 sp->fcport->flags &= ~FCF_ASYNC_SENT;
851
852 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
853 memset(&ea, 0, sizeof(ea));
854 ea.event = FCME_PRLI_DONE;
855 ea.fcport = sp->fcport;
856 ea.data[0] = lio->u.logio.data[0];
857 ea.data[1] = lio->u.logio.data[1];
858 ea.iop[0] = lio->u.logio.iop[0];
859 ea.iop[1] = lio->u.logio.iop[1];
860 ea.sp = sp;
861
862 qla2x00_fcport_event_handler(vha, &ea);
863 }
864
865 sp->free(sp);
866}
867
868int
869qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
870{
871 srb_t *sp;
872 struct srb_iocb *lio;
873 int rval = QLA_FUNCTION_FAILED;
874
875 if (!vha->flags.online)
876 return rval;
877
878 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
879 fcport->fw_login_state == DSC_LS_PLOGI_COMP ||
880 fcport->fw_login_state == DSC_LS_PRLI_PEND)
881 return rval;
882
883 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
884 if (!sp)
885 return rval;
886
887 fcport->flags |= FCF_ASYNC_SENT;
888 fcport->logout_completed = 0;
889
890 sp->type = SRB_PRLI_CMD;
891 sp->name = "prli";
892 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
893
894 lio = &sp->u.iocb_cmd;
895 lio->timeout = qla2x00_async_iocb_timeout;
896 sp->done = qla2x00_async_prli_sp_done;
897 lio->u.logio.flags = 0;
898
899 if (fcport->fc4f_nvme)
900 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
901
902 rval = qla2x00_start_sp(sp);
903 if (rval != QLA_SUCCESS) {
a5d42f4c
DG		 904 fcport->flags |= FCF_LOGIN_NEEDED;
905 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
906 goto done_free_sp;
907 }
908
909 ql_dbg(ql_dbg_disc, vha, 0x211b,
910 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d.\n",
911 fcport->port_name, sp->handle, fcport->loop_id,
912 fcport->d_id.b24, fcport->login_retry);
913
914 return rval;
915
916done_free_sp:
917 sp->free(sp);
918 fcport->flags &= ~FCF_ASYNC_SENT;
919 return rval;
920}
921
a07fc0a4 922int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
726b8548
QT		 923{
924 struct qla_work_evt *e;
925
926 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
927 if (!e)
928 return QLA_FUNCTION_FAILED;
929
930 e->u.fcport.fcport = fcport;
931 e->u.fcport.opt = opt;
6d674927 932 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 933 return qla2x00_post_work(vha, e);
934}
935
936int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
937{
938 srb_t *sp;
939 struct srb_iocb *mbx;
940 int rval = QLA_FUNCTION_FAILED;
941 u16 *mb;
942 dma_addr_t pd_dma;
943 struct port_database_24xx *pd;
944 struct qla_hw_data *ha = vha->hw;
945
3dbec59b
QT		 946 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
947 return rval;
726b8548 948
726b8548
QT		 949 fcport->disc_state = DSC_GPDB;
950
951 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
952 if (!sp)
953 goto done;
954
3dbec59b 955 fcport->flags |= FCF_ASYNC_SENT;
e0824e69
JC		 956 sp->type = SRB_MB_IOCB;
957 sp->name = "gpdb";
958 sp->gen1 = fcport->rscn_gen;
959 sp->gen2 = fcport->login_gen;
960 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
961
08eb7f45 962 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
726b8548 963 if (pd == NULL) {
83548fe2
QT		 964 ql_log(ql_log_warn, vha, 0xd043,
965 "Failed to allocate port database structure.\n");
726b8548
QT		 966 goto done_free_sp;
967 }
726b8548 968
726b8548
QT		 969 mb = sp->u.iocb_cmd.u.mbx.out_mb;
970 mb[0] = MBC_GET_PORT_DATABASE;
971 mb[1] = fcport->loop_id;
972 mb[2] = MSW(pd_dma);
973 mb[3] = LSW(pd_dma);
974 mb[6] = MSW(MSD(pd_dma));
975 mb[7] = LSW(MSD(pd_dma));
976 mb[9] = vha->vp_idx;
977 mb[10] = opt;
978
979 mbx = &sp->u.iocb_cmd;
980 mbx->timeout = qla2x00_async_iocb_timeout;
981 mbx->u.mbx.in = (void *)pd;
982 mbx->u.mbx.in_dma = pd_dma;
983
984 sp->done = qla24xx_async_gpdb_sp_done;
985
986 rval = qla2x00_start_sp(sp);
987 if (rval != QLA_SUCCESS)
988 goto done_free_sp;
989
83548fe2
QT		 990 ql_dbg(ql_dbg_disc, vha, 0x20dc,
991 "Async-%s %8phC hndl %x opt %x\n",
992 sp->name, fcport->port_name, sp->handle, opt);
726b8548
QT		 993
994 return rval;
995
996done_free_sp:
997 if (pd)
998 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
999
25ff6af1 1000 sp->free(sp);
726b8548 1001 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 1002done:
726b8548 1003 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 1004 return rval;
1005}
1006
726b8548 1007static
a4239945 1008void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1009{
726b8548
QT		 1010 unsigned long flags;
1011
726b8548 1012 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
f13515ac 1013 ea->fcport->login_gen++;
726b8548
QT		 1014 ea->fcport->deleted = 0;
1015 ea->fcport->logout_on_delete = 1;
1016
1017 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
1018 vha->fcport_count++;
1019 ea->fcport->login_succ = 1;
1020
1021 if (!IS_IIDMA_CAPABLE(vha->hw) ||
1022 !vha->hw->flags.gpsc_supported) {
83548fe2 1023 ql_dbg(ql_dbg_disc, vha, 0x20d6,
726b8548 1024 "%s %d %8phC post upd_fcport fcp_cnt %d\n",
a4239945 1025 __func__, __LINE__, ea->fcport->port_name,
726b8548
QT		 1026 vha->fcport_count);
1027
a4239945 1028 qla24xx_post_upd_fcport_work(vha, ea->fcport);
726b8548 1029 } else {
a4239945
QT		 1030 if (ea->fcport->id_changed) {
1031 ea->fcport->id_changed = 0;
1032 ql_dbg(ql_dbg_disc, vha, 0x20d7,
1033 "%s %d %8phC post gfpnid fcp_cnt %d\n",
1034 __func__, __LINE__, ea->fcport->port_name,
1035 vha->fcport_count);
1036 qla24xx_post_gfpnid_work(vha, ea->fcport);
1037 } else {
1038 ql_dbg(ql_dbg_disc, vha, 0x20d7,
1039 "%s %d %8phC post gpsc fcp_cnt %d\n",
1040 __func__, __LINE__, ea->fcport->port_name,
1041 vha->fcport_count);
1042 qla24xx_post_gpsc_work(vha, ea->fcport);
1043 }
726b8548 1044 }
414d9ff3
QT		 1045 } else if (ea->fcport->login_succ) {
1046 /*
1047 * We have an existing session. A late RSCN delivery
1048 * must have triggered the session to be re-validate.
a4239945 1049 * Session is still valid.
414d9ff3 1050 */
5ef696aa
QT		 1051 ql_dbg(ql_dbg_disc, vha, 0x20d6,
1052 "%s %d %8phC session revalidate success\n",
a4239945
QT		 1053 __func__, __LINE__, ea->fcport->port_name);
1054 ea->fcport->disc_state = DSC_LOGIN_COMPLETE;
726b8548
QT		 1055 }
1056 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
a4239945
QT		 1057}
1058
1059static
1060void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1061{
a4239945
QT		 1062 fc_port_t *fcport = ea->fcport;
1063 struct port_database_24xx *pd;
1064 struct srb *sp = ea->sp;
1065
1066 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
1067
1068 fcport->flags &= ~FCF_ASYNC_SENT;
1069
1070 ql_dbg(ql_dbg_disc, vha, 0x20d2,
f352eeb7
QT		 1071 "%s %8phC DS %d LS %d rc %d\n", __func__, fcport->port_name,
1072 fcport->disc_state, pd->current_login_state, ea->rc);
a4239945
QT		 1073
1074 if (fcport->disc_state == DSC_DELETE_PEND)
1075 return;
726b8548 1076
a4239945
QT		 1077 switch (pd->current_login_state) {
1078 case PDS_PRLI_COMPLETE:
1079 __qla24xx_parse_gpdb(vha, fcport, pd);
1080 break;
1081 case PDS_PLOGI_PENDING:
1082 case PDS_PLOGI_COMPLETE:
1083 case PDS_PRLI_PENDING:
1084 case PDS_PRLI2_PENDING:
1085 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC relogin needed\n",
1086 __func__, __LINE__, fcport->port_name);
1087 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1088 return;
1089 case PDS_LOGO_PENDING:
1090 case PDS_PORT_UNAVAILABLE:
1091 default:
1092 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
1093 __func__, __LINE__, fcport->port_name);
1094 qlt_schedule_sess_for_deletion_lock(fcport);
1095 return;
1096 }
1097 __qla24xx_handle_gpdb_event(vha, ea);
1098} /* gpdb event */
9cd883f0
QT		 1099
1100static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1101{
1102 u8 login = 0;
040036bb 1103 int rc;
9cd883f0
QT		 1104
1105 if (qla_tgt_mode_enabled(vha))
1106 return;
1107
1108 if (qla_dual_mode_enabled(vha)) {
1109 if (N2N_TOPO(vha->hw)) {
1110 u64 mywwn, wwn;
1111
1112 mywwn = wwn_to_u64(vha->port_name);
1113 wwn = wwn_to_u64(fcport->port_name);
1114 if (mywwn > wwn)
1115 login = 1;
1116 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1117 && time_after_eq(jiffies,
1118 fcport->plogi_nack_done_deadline))
1119 login = 1;
1120 } else {
1121 login = 1;
1122 }
1123 } else {
1124 /* initiator mode */
1125 login = 1;
1126 }
1127
1128 if (login) {
040036bb
QT		 1129 if (fcport->loop_id == FC_NO_LOOP_ID) {
1130 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
1131 rc = qla2x00_find_new_loop_id(vha, fcport);
1132 if (rc) {
1133 ql_dbg(ql_dbg_disc, vha, 0x20e6,
1134 "%s %d %8phC post del sess - out of loopid\n",
1135 __func__, __LINE__, fcport->port_name);
1136 fcport->scan_state = 0;
94cff6e1 1137 qlt_schedule_sess_for_deletion(fcport);
040036bb
QT		 1138 return;
1139 }
1140 }
9cd883f0
QT		 1141 ql_dbg(ql_dbg_disc, vha, 0x20bf,
1142 "%s %d %8phC post login\n",
1143 __func__, __LINE__, fcport->port_name);
9cd883f0
QT		 1144 qla2x00_post_async_login_work(vha, fcport, NULL);
1145 }
1146}
1147
726b8548
QT		 1148int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1149{
f13515ac 1150 u16 data[2];
a4239945 1151 u64 wwn;
726b8548 1152
83548fe2 1153 ql_dbg(ql_dbg_disc, vha, 0x20d8,
f352eeb7 1154 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d retry %d lid %d scan %d\n",
726b8548
QT		 1155 __func__, fcport->port_name, fcport->disc_state,
1156 fcport->fw_login_state, fcport->login_pause, fcport->flags,
1157 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
f352eeb7 1158 fcport->login_gen, fcport->login_retry,
a4239945 1159 fcport->loop_id, fcport->scan_state);
726b8548 1160
a4239945
QT		 1161 if (fcport->login_retry == 0)
1162 return 0;
1163
1164 if (fcport->scan_state != QLA_FCPORT_FOUND)
1165 return 0;
726b8548
QT		 1166
1167 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1168 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1169 return 0;
1170
5b33469a 1171 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1172 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1173 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1174 return 0;
9cd883f0 1175 }
5b33469a
QT		 1176 }
1177
726b8548
QT		 1178 /* for pure Target Mode. Login will not be initiated */
1179 if (vha->host->active_mode == MODE_TARGET)
1180 return 0;
1181
1182 if (fcport->flags & FCF_ASYNC_SENT) {
1183 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1184 return 0;
1185 }
1186
a4239945
QT		 1187 fcport->login_retry--;
1188
726b8548
QT		 1189 switch (fcport->disc_state) {
1190 case DSC_DELETED:
a4239945
QT		 1191 wwn = wwn_to_u64(fcport->node_name);
1192 if (wwn == 0) {
1193 ql_dbg(ql_dbg_disc, vha, 0xffff,
1194 "%s %d %8phC post GNNID\n",
1195 __func__, __LINE__, fcport->port_name);
1196 qla24xx_post_gnnid_work(vha, fcport);
1197 } else if (fcport->loop_id == FC_NO_LOOP_ID) {
83548fe2
QT		 1198 ql_dbg(ql_dbg_disc, vha, 0x20bd,
1199 "%s %d %8phC post gnl\n",
1200 __func__, __LINE__, fcport->port_name);
5d3300a9 1201 qla24xx_post_gnl_work(vha, fcport);
726b8548 1202 } else {
9cd883f0 1203 qla_chk_n2n_b4_login(vha, fcport);
726b8548
QT		 1204 }
1205 break;
1206
1207 case DSC_GNL:
1208 if (fcport->login_pause) {
1209 fcport->last_rscn_gen = fcport->rscn_gen;
1210 fcport->last_login_gen = fcport->login_gen;
1211 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1212 break;
1213 }
1214
9cd883f0 1215 qla_chk_n2n_b4_login(vha, fcport);
726b8548
QT		 1216 break;
1217
1218 case DSC_LOGIN_FAILED:
83548fe2
QT		 1219 ql_dbg(ql_dbg_disc, vha, 0x20d0,
1220 "%s %d %8phC post gidpn\n",
1221 __func__, __LINE__, fcport->port_name);
9cd883f0
QT		 1222 if (N2N_TOPO(vha->hw))
1223 qla_chk_n2n_b4_login(vha, fcport);
1224 else
1225 qla24xx_post_gidpn_work(vha, fcport);
726b8548
QT		 1226 break;
1227
1228 case DSC_LOGIN_COMPLETE:
1229 /* recheck login state */
83548fe2 1230 ql_dbg(ql_dbg_disc, vha, 0x20d1,
f13515ac 1231 "%s %d %8phC post adisc\n",
83548fe2 1232 __func__, __LINE__, fcport->port_name);
f13515ac
QT		 1233 data[0] = data[1] = 0;
1234 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 1235 break;
1236
1237 default:
1238 break;
1239 }
1240
1241 return 0;
1242}
1243
1244static
1245void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
1246{
1247 fcport->rscn_gen++;
1248
83548fe2
QT		 1249 ql_dbg(ql_dbg_disc, fcport->vha, 0x210c,
1250 "%s %8phC DS %d LS %d\n",
1251 __func__, fcport->port_name, fcport->disc_state,
1252 fcport->fw_login_state);
726b8548
QT		 1253
1254 if (fcport->flags & FCF_ASYNC_SENT)
1255 return;
1256
1257 switch (fcport->disc_state) {
1258 case DSC_DELETED:
1259 case DSC_LOGIN_COMPLETE:
5ef696aa 1260 qla24xx_post_gpnid_work(fcport->vha, &ea->id);
726b8548 1261 break;
726b8548
QT		 1262 default:
1263 break;
1264 }
1265}
1266
1267int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
a4239945 1268 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
726b8548
QT		 1269{
1270 struct qla_work_evt *e;
1271 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1272 if (!e)
1273 return QLA_FUNCTION_FAILED;
1274
1275 e->u.new_sess.id = *id;
1276 e->u.new_sess.pla = pla;
a4239945 1277 e->u.new_sess.fc4_type = fc4_type;
726b8548 1278 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
a4239945
QT		 1279 if (node_name)
1280 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
726b8548
QT		 1281
1282 return qla2x00_post_work(vha, e);
1283}
1284
726b8548
QT		 1285static
1286void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1287 struct event_arg *ea)
1288{
1289 fc_port_t *fcport = ea->fcport;
1290
83548fe2
QT		 1291 ql_dbg(ql_dbg_disc, vha, 0x2102,
1292 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1293 __func__, fcport->port_name, fcport->disc_state,
1294 fcport->fw_login_state, fcport->login_pause,
1295 fcport->deleted, fcport->conflict,
1296 fcport->last_rscn_gen, fcport->rscn_gen,
1297 fcport->last_login_gen, fcport->login_gen,
1298 fcport->flags);
726b8548
QT		 1299
1300 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1301 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1302 return;
1303
5b33469a 1304 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1305 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1306 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1307 return;
9cd883f0 1308 }
5b33469a
QT		 1309 }
1310
726b8548
QT		 1311 if (fcport->flags & FCF_ASYNC_SENT) {
1312 fcport->login_retry++;
1313 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1314 return;
1315 }
1316
1317 if (fcport->disc_state == DSC_DELETE_PEND) {
1318 fcport->login_retry++;
1319 return;
1320 }
1321
1322 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 1323 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gidpn\n",
726b8548
QT		 1324 __func__, __LINE__, fcport->port_name);
1325
5d3300a9 1326 qla24xx_post_gidpn_work(vha, fcport);
726b8548
QT		 1327 return;
1328 }
1329
1330 qla24xx_fcport_handle_login(vha, fcport);
1331}
1332
41dc529a 1333void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1334{
f352eeb7 1335 fc_port_t *f, *tf;
41dc529a 1336 uint32_t id = 0, mask, rid;
f352eeb7 1337 unsigned long flags;
726b8548 1338
b98ae0d7 1339 switch (ea->event) {
b98ae0d7
QT		 1340 case FCME_RSCN:
1341 case FCME_GIDPN_DONE:
1342 case FCME_GPSC_DONE:
1343 case FCME_GPNID_DONE:
a4239945 1344 case FCME_GNNID_DONE:
b98ae0d7
QT		 1345 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
1346 test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1347 return;
1348 break;
1349 default:
1350 break;
1351 }
1352
726b8548
QT		 1353 switch (ea->event) {
1354 case FCME_RELOGIN:
1355 if (test_bit(UNLOADING, &vha->dpc_flags))
1356 return;
5ff1d584 1357
726b8548
QT		 1358 qla24xx_handle_relogin_event(vha, ea);
1359 break;
1360 case FCME_RSCN:
1361 if (test_bit(UNLOADING, &vha->dpc_flags))
1362 return;
41dc529a
QT		 1363 switch (ea->id.b.rsvd_1) {
1364 case RSCN_PORT_ADDR:
f352eeb7
QT		 1365 spin_lock_irqsave(&vha->work_lock, flags);
1366 if (vha->scan.scan_flags == 0) {
1367 ql_dbg(ql_dbg_disc, vha, 0xffff,
1368 "%s: schedule\n", __func__);
1369 vha->scan.scan_flags |= SF_QUEUED;
1370 schedule_delayed_work(&vha->scan.scan_work, 5);
41dc529a 1371 }
f352eeb7
QT		 1372 spin_unlock_irqrestore(&vha->work_lock, flags);
1373
41dc529a
QT		 1374 break;
1375 case RSCN_AREA_ADDR:
1376 case RSCN_DOM_ADDR:
1377 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1378 mask = 0xffff00;
83548fe2
QT		 1379 ql_dbg(ql_dbg_async, vha, 0x5044,
1380 "RSCN: Area 0x%06x was affected\n",
1381 ea->id.b24);
41dc529a
QT		 1382 } else {
1383 mask = 0xff0000;
83548fe2
QT		 1384 ql_dbg(ql_dbg_async, vha, 0x507a,
1385 "RSCN: Domain 0x%06x was affected\n",
1386 ea->id.b24);
41dc529a 1387 }
726b8548 1388
41dc529a
QT		 1389 rid = ea->id.b24 & mask;
1390 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1391 list) {
1392 id = f->d_id.b24 & mask;
1393 if (rid == id) {
1394 ea->fcport = f;
1395 qla24xx_handle_rscn_event(f, ea);
1396 }
726b8548 1397 }
41dc529a
QT		 1398 break;
1399 case RSCN_FAB_ADDR:
1400 default:
83548fe2
QT		 1401 ql_log(ql_log_warn, vha, 0xd045,
1402 "RSCN: Fabric was affected. Addr format %d\n",
1403 ea->id.b.rsvd_1);
41dc529a
QT		 1404 qla2x00_mark_all_devices_lost(vha, 1);
1405 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1406 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1407 }
1408 break;
1409 case FCME_GIDPN_DONE:
1410 qla24xx_handle_gidpn_event(vha, ea);
1411 break;
1412 case FCME_GNL_DONE:
1413 qla24xx_handle_gnl_done_event(vha, ea);
1414 break;
1415 case FCME_GPSC_DONE:
a4239945 1416 qla24xx_handle_gpsc_event(vha, ea);
726b8548
QT		 1417 break;
1418 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1419 qla24xx_handle_plogi_done_event(vha, ea);
1420 break;
a5d42f4c
DG		 1421 case FCME_PRLI_DONE:
1422 qla24xx_handle_prli_done_event(vha, ea);
1423 break;
726b8548
QT		 1424 case FCME_GPDB_DONE:
1425 qla24xx_handle_gpdb_event(vha, ea);
1426 break;
1427 case FCME_GPNID_DONE:
1428 qla24xx_handle_gpnid_event(vha, ea);
1429 break;
d3bae931
DG		 1430 case FCME_GFFID_DONE:
1431 qla24xx_handle_gffid_event(vha, ea);
1432 break;
f13515ac
QT		 1433 case FCME_ADISC_DONE:
1434 qla24xx_handle_adisc_event(vha, ea);
1435 break;
a4239945
QT		 1436 case FCME_GNNID_DONE:
1437 qla24xx_handle_gnnid_event(vha, ea);
1438 break;
1439 case FCME_GFPNID_DONE:
1440 qla24xx_handle_gfpnid_event(vha, ea);
1441 break;
726b8548
QT		 1442 default:
1443 BUG_ON(1);
1444 break;
1445 }
5ff1d584
AV		 1446}
1447
3822263e 1448static void
faef62d1 1449qla2x00_tmf_iocb_timeout(void *data)
3822263e 1450{
25ff6af1 1451 srb_t *sp = data;
faef62d1 1452 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1453
faef62d1
AB		 1454 tmf->u.tmf.comp_status = CS_TIMEOUT;
1455 complete(&tmf->u.tmf.comp);
1456}
9ba56b95 1457
faef62d1 1458static void
25ff6af1 1459qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1460{
25ff6af1 1461 srb_t *sp = ptr;
faef62d1 1462 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1463
faef62d1 1464 complete(&tmf->u.tmf.comp);
3822263e
MI		 1465}
1466
1467int
faef62d1 1468qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1469 uint32_t tag)
1470{
1471 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1472 struct srb_iocb *tm_iocb;
3822263e 1473 srb_t *sp;
faef62d1 1474 int rval = QLA_FUNCTION_FAILED;
3822263e 1475
9ba56b95 1476 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1477 if (!sp)
1478 goto done;
1479
faef62d1 1480 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1481 sp->type = SRB_TM_CMD;
1482 sp->name = "tmf";
faef62d1
AB		 1483 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1484 tm_iocb->u.tmf.flags = flags;
1485 tm_iocb->u.tmf.lun = lun;
1486 tm_iocb->u.tmf.data = tag;
1487 sp->done = qla2x00_tmf_sp_done;
1488 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1489 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 1490
1491 rval = qla2x00_start_sp(sp);
1492 if (rval != QLA_SUCCESS)
1493 goto done_free_sp;
1494
7c3df132 1495 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1496 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1497 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1498 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1499
1500 wait_for_completion(&tm_iocb->u.tmf.comp);
1501
1502 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
1503 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1504
1505 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
1506 ql_dbg(ql_dbg_taskm, vha, 0x8030,
1507 "TM IOCB failed (%x).\n", rval);
1508 }
1509
1510 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1511 flags = tm_iocb->u.tmf.flags;
1512 lun = (uint16_t)tm_iocb->u.tmf.lun;
1513
1514 /* Issue Marker IOCB */
1515 qla2x00_marker(vha, vha->hw->req_q_map[0],
1516 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1517 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1518 }
3822263e
MI		 1519
1520done_free_sp:
25ff6af1 1521 sp->free(sp);
6d674927 1522 sp->fcport->flags &= ~FCF_ASYNC_SENT;
3822263e
MI		 1523done:
1524 return rval;
1525}
1526
4440e46d
AB		 1527static void
1528qla24xx_abort_iocb_timeout(void *data)
1529{
25ff6af1 1530 srb_t *sp = data;
4440e46d
AB		 1531 struct srb_iocb *abt = &sp->u.iocb_cmd;
1532
1533 abt->u.abt.comp_status = CS_TIMEOUT;
1534 complete(&abt->u.abt.comp);
1535}
1536
1537static void
25ff6af1 1538qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1539{
25ff6af1 1540 srb_t *sp = ptr;
4440e46d
AB		 1541 struct srb_iocb *abt = &sp->u.iocb_cmd;
1542
1543 complete(&abt->u.abt.comp);
1544}
1545
15f30a57 1546int
4440e46d
AB		 1547qla24xx_async_abort_cmd(srb_t *cmd_sp)
1548{
25ff6af1 1549 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1550 fc_port_t *fcport = cmd_sp->fcport;
1551 struct srb_iocb *abt_iocb;
1552 srb_t *sp;
1553 int rval = QLA_FUNCTION_FAILED;
1554
1555 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1556 if (!sp)
1557 goto done;
1558
1559 abt_iocb = &sp->u.iocb_cmd;
1560 sp->type = SRB_ABT_CMD;
1561 sp->name = "abort";
1562 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1563 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
1564 sp->done = qla24xx_abort_sp_done;
1565 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1566 init_completion(&abt_iocb->u.abt.comp);
1567
1568 rval = qla2x00_start_sp(sp);
1569 if (rval != QLA_SUCCESS)
1570 goto done_free_sp;
1571
1572 ql_dbg(ql_dbg_async, vha, 0x507c,
1573 "Abort command issued - hdl=%x, target_id=%x\n",
1574 cmd_sp->handle, fcport->tgt_id);
1575
1576 wait_for_completion(&abt_iocb->u.abt.comp);
1577
1578 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1579 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1580
1581done_free_sp:
25ff6af1 1582 sp->free(sp);
4440e46d
AB		 1583done:
1584 return rval;
1585}
1586
1587int
1588qla24xx_async_abort_command(srb_t *sp)
1589{
1590 unsigned long flags = 0;
1591
1592 uint32_t handle;
1593 fc_port_t *fcport = sp->fcport;
1594 struct scsi_qla_host *vha = fcport->vha;
1595 struct qla_hw_data *ha = vha->hw;
1596 struct req_que *req = vha->req;
1597
1598 spin_lock_irqsave(&ha->hardware_lock, flags);
1599 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1600 if (req->outstanding_cmds[handle] == sp)
1601 break;
1602 }
1603 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1604 if (handle == req->num_outstanding_cmds) {
1605 /* Command not found. */
1606 return QLA_FUNCTION_FAILED;
1607 }
1608 if (sp->type == SRB_FXIOCB_DCMD)
1609 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1610 FXDISC_ABORT_IOCTL);
1611
1612 return qla24xx_async_abort_cmd(sp);
1613}
1614
a5d42f4c
DG		 1615static void
1616qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1617{
1618 switch (ea->data[0]) {
1619 case MBS_COMMAND_COMPLETE:
1620 ql_dbg(ql_dbg_disc, vha, 0x2118,
1621 "%s %d %8phC post gpdb\n",
1622 __func__, __LINE__, ea->fcport->port_name);
1623
1624 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1625 ea->fcport->logout_on_delete = 1;
1626 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1627 break;
1628 default:
edd05de1
DG		 1629 if (ea->fcport->n2n_flag) {
1630 ql_dbg(ql_dbg_disc, vha, 0x2118,
1631 "%s %d %8phC post fc4 prli\n",
1632 __func__, __LINE__, ea->fcport->port_name);
1633 ea->fcport->fc4f_nvme = 0;
1634 ea->fcport->n2n_flag = 0;
1635 qla24xx_post_prli_work(vha, ea->fcport);
1636 }
a5d42f4c
DG		 1637 ql_dbg(ql_dbg_disc, vha, 0x2119,
1638 "%s %d %8phC unhandle event of %x\n",
1639 __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
1640 break;
1641 }
1642}
1643
726b8548
QT		 1644static void
1645qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1646{
726b8548 1647 port_id_t cid; /* conflict Nport id */
a084fd68
QT		 1648 u16 lid;
1649 struct fc_port *conflict_fcport;
82abdcaf 1650 unsigned long flags;
a4239945
QT		 1651 struct fc_port *fcport = ea->fcport;
1652
f352eeb7
QT		 1653 ql_dbg(ql_dbg_disc, vha, 0xffff,
1654 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
1655 __func__, fcport->port_name, fcport->disc_state,
1656 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
1657 ea->sp->gen2, fcport->rscn_gen|ea->sp->gen1,
1658 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
1659
a4239945
QT		 1660 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1661 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) {
1662 ql_dbg(ql_dbg_disc, vha, 0x20ea,
1663 "%s %d %8phC Remote is trying to login\n",
1664 __func__, __LINE__, fcport->port_name);
1665 return;
1666 }
1667
1668 if (fcport->disc_state == DSC_DELETE_PEND)
1669 return;
1670
1671 if (ea->sp->gen2 != fcport->login_gen) {
1672 /* target side must have changed it. */
1673 ql_dbg(ql_dbg_disc, vha, 0x20d3,
f352eeb7
QT		 1674 "%s %8phC generation changed\n",
1675 __func__, fcport->port_name);
1676 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
a4239945
QT		 1677 return;
1678 } else if (ea->sp->gen1 != fcport->rscn_gen) {
1679 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
1680 __func__, __LINE__, fcport->port_name);
1681 qla24xx_post_gidpn_work(vha, fcport);
1682 return;
1683 }
ac280b67 1684
726b8548 1685 switch (ea->data[0]) {
ac280b67 1686 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1687 /*
1688 * Driver must validate login state - If PRLI not complete,
1689 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1690 * requests.
1691 */
a5d42f4c
DG		 1692 if (ea->fcport->fc4f_nvme) {
1693 ql_dbg(ql_dbg_disc, vha, 0x2117,
1694 "%s %d %8phC post prli\n",
1695 __func__, __LINE__, ea->fcport->port_name);
1696 qla24xx_post_prli_work(vha, ea->fcport);
1697 } else {
1698 ql_dbg(ql_dbg_disc, vha, 0x20ea,
a084fd68
QT		 1699 "%s %d %8phC LoopID 0x%x in use with %06x. post gnl\n",
1700 __func__, __LINE__, ea->fcport->port_name,
1701 ea->fcport->loop_id, ea->fcport->d_id.b24);
1702
1703 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
82abdcaf 1704 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a084fd68 1705 ea->fcport->loop_id = FC_NO_LOOP_ID;
a5d42f4c
DG		 1706 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1707 ea->fcport->logout_on_delete = 1;
3515832c 1708 ea->fcport->send_els_logo = 0;
82abdcaf
QT		 1709 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP;
1710 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1711
a5d42f4c
DG		 1712 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1713 }
ac280b67
AV		 1714 break;
1715 case MBS_COMMAND_ERROR:
83548fe2 1716 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
726b8548
QT		 1717 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1718
1719 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1720 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1721 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1722 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1723 else
726b8548 1724 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1725 break;
1726 case MBS_LOOP_ID_USED:
726b8548
QT		 1727 /* data[1] = IO PARAM 1 = nport ID */
1728 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1729 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1730 cid.b.al_pa = ea->iop[1] & 0xff;
1731 cid.b.rsvd_1 = 0;
1732
83548fe2
QT		 1733 ql_dbg(ql_dbg_disc, vha, 0x20ec,
1734 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1735 __func__, __LINE__, ea->fcport->port_name,
1736 ea->fcport->loop_id);
726b8548
QT		 1737
1738 if (IS_SW_RESV_ADDR(cid)) {
1739 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1740 ea->fcport->loop_id = FC_NO_LOOP_ID;
1741 } else {
1742 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1743 }
726b8548
QT		 1744 qla24xx_post_gnl_work(vha, ea->fcport);
1745 break;
1746 case MBS_PORT_ID_USED:
83548fe2
QT		 1747 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1748 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1749 __func__, __LINE__, ea->fcport->port_name,
1750 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1751 ea->fcport->d_id.b.al_pa);
726b8548 1752
a084fd68
QT		 1753 lid = ea->iop[1] & 0xffff;
1754 qlt_find_sess_invalidate_other(vha,
1755 wwn_to_u64(ea->fcport->port_name),
1756 ea->fcport->d_id, lid, &conflict_fcport);
1757
1758 if (conflict_fcport) {
1759 /*
1760 * Another fcport share the same loop_id/nport id.
1761 * Conflict fcport needs to finish cleanup before this
1762 * fcport can proceed to login.
1763 */
1764 conflict_fcport->conflict = ea->fcport;
1765 ea->fcport->login_pause = 1;
1766
1767 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1768 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
1769 __func__, __LINE__, ea->fcport->port_name,
1770 ea->fcport->d_id.b24, lid);
1771 qla2x00_clear_loop_id(ea->fcport);
1772 qla24xx_post_gidpn_work(vha, ea->fcport);
1773 } else {
1774 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1775 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
1776 __func__, __LINE__, ea->fcport->port_name,
1777 ea->fcport->d_id.b24, lid);
1778
1779 qla2x00_clear_loop_id(ea->fcport);
1780 set_bit(lid, vha->hw->loop_id_map);
1781 ea->fcport->loop_id = lid;
1782 ea->fcport->keep_nport_handle = 0;
94cff6e1 1783 qlt_schedule_sess_for_deletion(ea->fcport);
a084fd68 1784 }
ac280b67
AV		 1785 break;
1786 }
4916392b 1787 return;
ac280b67
AV		 1788}
1789
4916392b 1790void
ac280b67
AV		 1791qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1792 uint16_t *data)
1793{
726b8548 1794 qla2x00_mark_device_lost(vha, fcport, 1, 0);
a6ca8878 1795 qlt_logo_completion_handler(fcport, data[0]);
726b8548 1796 fcport->login_gen++;
4916392b 1797 return;
ac280b67
AV		 1798}
1799
4916392b 1800void
5ff1d584
AV		 1801qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1802 uint16_t *data)
1803{
1804 if (data[0] == MBS_COMMAND_COMPLETE) {
1805 qla2x00_update_fcport(vha, fcport);
1806
4916392b 1807 return;
5ff1d584
AV		 1808 }
1809
1810 /* Retry login. */
1811 fcport->flags &= ~FCF_ASYNC_SENT;
1812 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
1813 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1814 else
80d79440 1815 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 1816
4916392b 1817 return;
5ff1d584
AV		 1818}
1819
1da177e4
LT		 1820/****************************************************************************/
1821/* QLogic ISP2x00 Hardware Support Functions. */
1822/****************************************************************************/
1823
fa492630 1824static int
7d613ac6
SV		 1825qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
1826{
1827 int rval = QLA_SUCCESS;
1828 struct qla_hw_data *ha = vha->hw;
1829 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 1830 uint16_t config[4];
7d613ac6
SV		 1831
1832 qla83xx_idc_lock(vha, 0);
1833
1834 /* SV: TODO: Assign initialization timeout from
1835 * flash-info / other param
1836 */
1837 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
1838 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
1839
1840 /* Set our fcoe function presence */
1841 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
1842 ql_dbg(ql_dbg_p3p, vha, 0xb077,
1843 "Error while setting DRV-Presence.\n");
1844 rval = QLA_FUNCTION_FAILED;
1845 goto exit;
1846 }
1847
1848 /* Decide the reset ownership */
1849 qla83xx_reset_ownership(vha);
1850
1851 /*
1852 * On first protocol driver load:
1853 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
1854 * register.
1855 * Others: Check compatibility with current IDC Major version.
1856 */
1857 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
1858 if (ha->flags.nic_core_reset_owner) {
1859 /* Set IDC Major version */
1860 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
1861 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
1862
1863 /* Clearing IDC-Lock-Recovery register */
1864 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
1865 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
1866 /*
1867 * Clear further IDC participation if we are not compatible with
1868 * the current IDC Major Version.
1869 */
1870 ql_log(ql_log_warn, vha, 0xb07d,
1871 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
1872 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
1873 __qla83xx_clear_drv_presence(vha);
1874 rval = QLA_FUNCTION_FAILED;
1875 goto exit;
1876 }
1877 /* Each function sets its supported Minor version. */
1878 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
1879 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
1880 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
1881
711aa7f7
SK		 1882 if (ha->flags.nic_core_reset_owner) {
1883 memset(config, 0, sizeof(config));
1884 if (!qla81xx_get_port_config(vha, config))
1885 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
1886 QLA8XXX_DEV_READY);
1887 }
1888
7d613ac6
SV		 1889 rval = qla83xx_idc_state_handler(vha);
1890
1891exit:
1892 qla83xx_idc_unlock(vha, 0);
1893
1894 return rval;
1895}
1896
1da177e4
LT		 1897/*
1898* qla2x00_initialize_adapter
1899* Initialize board.
1900*
1901* Input:
1902* ha = adapter block pointer.
1903*
1904* Returns:
1905* 0 = success
1906*/
1907int
e315cd28 1908qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 1909{
1910 int rval;
e315cd28 1911 struct qla_hw_data *ha = vha->hw;
73208dfd 1912 struct req_que *req = ha->req_q_map[0];
2533cf67 1913
fc90adaf
JC		 1914 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
1915 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
1916
1da177e4 1917 /* Clear adapter flags. */
e315cd28 1918 vha->flags.online = 0;
2533cf67 1919 ha->flags.chip_reset_done = 0;
e315cd28 1920 vha->flags.reset_active = 0;
85880801
AV		 1921 ha->flags.pci_channel_io_perm_failure = 0;
1922 ha->flags.eeh_busy = 0;
fabbb8df 1923 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 1924 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1925 atomic_set(&vha->loop_state, LOOP_DOWN);
1926 vha->device_flags = DFLG_NO_CABLE;
1927 vha->dpc_flags = 0;
1928 vha->flags.management_server_logged_in = 0;
1929 vha->marker_needed = 0;
1da177e4
LT		 1930 ha->isp_abort_cnt = 0;
1931 ha->beacon_blink_led = 0;
1932
73208dfd
AC		 1933 set_bit(0, ha->req_qid_map);
1934 set_bit(0, ha->rsp_qid_map);
1935
cfb0919c 1936 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 1937 "Configuring PCI space...\n");
e315cd28 1938 rval = ha->isp_ops->pci_config(vha);
1da177e4 1939 if (rval) {
7c3df132
SK		 1940 ql_log(ql_log_warn, vha, 0x0044,
1941 "Unable to configure PCI space.\n");
1da177e4
LT		 1942 return (rval);
1943 }
1944
e315cd28 1945 ha->isp_ops->reset_chip(vha);
1da177e4 1946
e315cd28 1947 rval = qla2xxx_get_flash_info(vha);
c00d8994 1948 if (rval) {
7c3df132
SK		 1949 ql_log(ql_log_fatal, vha, 0x004f,
1950 "Unable to validate FLASH data.\n");
7ec0effd
AD		 1951 return rval;
1952 }
1953
1954 if (IS_QLA8044(ha)) {
1955 qla8044_read_reset_template(vha);
1956
1957 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
1958 * If DONRESET_BIT0 is set, drivers should not set dev_state
1959 * to NEED_RESET. But if NEED_RESET is set, drivers should
1960 * should honor the reset. */
1961 if (ql2xdontresethba == 1)
1962 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 1963 }
1964
73208dfd 1965 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 1966 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 1967 "Configure NVRAM parameters...\n");
0107109e 1968
e315cd28 1969 ha->isp_ops->nvram_config(vha);
1da177e4 1970
d4c760c2
AV		 1971 if (ha->flags.disable_serdes) {
1972 /* Mask HBA via NVRAM settings? */
7c3df132 1973 ql_log(ql_log_info, vha, 0x0077,
7b833558 1974 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 1975 return QLA_FUNCTION_FAILED;
1976 }
1977
cfb0919c 1978 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 1979 "Verifying loaded RISC code...\n");
1da177e4 1980
e315cd28
AC		 1981 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
1982 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 1983 if (rval)
1984 return (rval);
e315cd28 1985 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 1986 if (rval)
1987 return (rval);
1da177e4 1988 }
a9083016 1989
4d4df193 1990 if (IS_QLA84XX(ha)) {
e315cd28 1991 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 1992 if (!ha->cs84xx) {
7c3df132 1993 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 1994 "Unable to configure ISP84XX.\n");
1995 return QLA_FUNCTION_FAILED;
1996 }
1997 }
2d70c103 1998
ead03855 1999 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 2000 rval = qla2x00_init_rings(vha);
2001
2533cf67 2002 ha->flags.chip_reset_done = 1;
1da177e4 2003
9a069e19 2004 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 2005 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 2006 rval = qla84xx_init_chip(vha);
2007 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2008 ql_log(ql_log_warn, vha, 0x00d4,
2009 "Unable to initialize ISP84XX.\n");
8d2b21db 2010 qla84xx_put_chip(vha);
9a069e19
GM		 2011 }
2012 }
2013
7d613ac6
SV		 2014 /* Load the NIC Core f/w if we are the first protocol driver. */
2015 if (IS_QLA8031(ha)) {
2016 rval = qla83xx_nic_core_fw_load(vha);
2017 if (rval)
2018 ql_log(ql_log_warn, vha, 0x0124,
2019 "Error in initializing NIC Core f/w.\n");
2020 }
2021
2f0f3f4f
MI		 2022 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
2023 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 2024
c46e65c7
JC		 2025 if (IS_P3P_TYPE(ha))
2026 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
2027 else
2028 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
2029
1da177e4
LT		 2030 return (rval);
2031}
2032
2033/**
abbd8870 2034 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 2035 * @ha: HA context
2036 *
2037 * Returns 0 on success.
2038 */
abbd8870 2039int
e315cd28 2040qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 2041{
a157b101 2042 uint16_t w;
abbd8870 2043 unsigned long flags;
e315cd28 2044 struct qla_hw_data *ha = vha->hw;
3d71644c 2045 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2046
1da177e4 2047 pci_set_master(ha->pdev);
af6177d8 2048 pci_try_set_mwi(ha->pdev);
1da177e4 2049
1da177e4 2050 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2051 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 2052 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2053
737faece 2054 pci_disable_rom(ha->pdev);
1da177e4
LT		 2055
2056 /* Get PCI bus information. */
2057 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2058 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 2059 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2060
abbd8870
AV		 2061 return QLA_SUCCESS;
2062}
1da177e4 2063
abbd8870
AV		 2064/**
2065 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
2066 * @ha: HA context
2067 *
2068 * Returns 0 on success.
2069 */
2070int
e315cd28 2071qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 2072{
a157b101 2073 uint16_t w;
abbd8870
AV		 2074 unsigned long flags = 0;
2075 uint32_t cnt;
e315cd28 2076 struct qla_hw_data *ha = vha->hw;
3d71644c 2077 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2078
abbd8870 2079 pci_set_master(ha->pdev);
af6177d8 2080 pci_try_set_mwi(ha->pdev);
1da177e4 2081
abbd8870 2082 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2083 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 2084
abbd8870
AV		 2085 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2086 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 2087 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 2088
abbd8870
AV		 2089 /*
2090 * If this is a 2300 card and not 2312, reset the
2091 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
2092 * the 2310 also reports itself as a 2300 so we need to get the
2093 * fb revision level -- a 6 indicates it really is a 2300 and
2094 * not a 2310.
2095 */
2096 if (IS_QLA2300(ha)) {
2097 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 2098
abbd8870 2099 /* Pause RISC. */
3d71644c 2100 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 2101 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2102 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 2103 break;
1da177e4 2104
abbd8870
AV		 2105 udelay(10);
2106 }
1da177e4 2107
abbd8870 2108 /* Select FPM registers. */
3d71644c
AV		 2109 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2110 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2111
2112 /* Get the fb rev level */
3d71644c 2113 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 2114
2115 if (ha->fb_rev == FPM_2300)
a157b101 2116 pci_clear_mwi(ha->pdev);
abbd8870
AV		 2117
2118 /* Deselect FPM registers. */
3d71644c
AV		 2119 WRT_REG_WORD(&reg->ctrl_status, 0x0);
2120 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2121
2122 /* Release RISC module. */
3d71644c 2123 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 2124 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2125 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 2126 break;
2127
2128 udelay(10);
1da177e4 2129 }
1da177e4 2130
abbd8870
AV		 2131 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2132 }
1da177e4 2133
abbd8870
AV		 2134 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2135
737faece 2136 pci_disable_rom(ha->pdev);
1da177e4 2137
abbd8870
AV		 2138 /* Get PCI bus information. */
2139 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2140 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2141 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2142
2143 return QLA_SUCCESS;
1da177e4
LT		 2144}
2145
0107109e
AV		 2146/**
2147 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
2148 * @ha: HA context
2149 *
2150 * Returns 0 on success.
2151 */
2152int
e315cd28 2153qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 2154{
a157b101 2155 uint16_t w;
0107109e 2156 unsigned long flags = 0;
e315cd28 2157 struct qla_hw_data *ha = vha->hw;
0107109e 2158 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 2159
2160 pci_set_master(ha->pdev);
af6177d8 2161 pci_try_set_mwi(ha->pdev);
0107109e
AV		 2162
2163 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2164 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 2165 w &= ~PCI_COMMAND_INTX_DISABLE;
2166 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2167
2168 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2169
2170 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 2171 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
2172 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 2173
2174 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2175 if (pci_is_pcie(ha->pdev))
5ffd3a52 2176 pcie_set_readrq(ha->pdev, 4096);
0107109e 2177
737faece 2178 pci_disable_rom(ha->pdev);
0107109e 2179
44c10138 2180 ha->chip_revision = ha->pdev->revision;
a8488abe 2181
0107109e
AV		 2182 /* Get PCI bus information. */
2183 spin_lock_irqsave(&ha->hardware_lock, flags);
2184 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
2185 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2186
2187 return QLA_SUCCESS;
2188}
2189
c3a2f0df
AV		 2190/**
2191 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
2192 * @ha: HA context
2193 *
2194 * Returns 0 on success.
2195 */
2196int
e315cd28 2197qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 2198{
2199 uint16_t w;
e315cd28 2200 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 2201
2202 pci_set_master(ha->pdev);
2203 pci_try_set_mwi(ha->pdev);
2204
2205 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2206 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2207 w &= ~PCI_COMMAND_INTX_DISABLE;
2208 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2209
2210 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2211 if (pci_is_pcie(ha->pdev))
5ffd3a52 2212 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 2213
737faece 2214 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 2215
2216 ha->chip_revision = ha->pdev->revision;
2217
2218 return QLA_SUCCESS;
2219}
2220
1da177e4
LT		 2221/**
2222 * qla2x00_isp_firmware() - Choose firmware image.
2223 * @ha: HA context
2224 *
2225 * Returns 0 on success.
2226 */
2227static int
e315cd28 2228qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 2229{
2230 int rval;
42e421b1
AV		 2231 uint16_t loop_id, topo, sw_cap;
2232 uint8_t domain, area, al_pa;
e315cd28 2233 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2234
2235 /* Assume loading risc code */
fa2a1ce5 2236 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 2237
2238 if (ha->flags.disable_risc_code_load) {
7c3df132 2239 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 2240
2241 /* Verify checksum of loaded RISC code. */
e315cd28 2242 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 2243 if (rval == QLA_SUCCESS) {
2244 /* And, verify we are not in ROM code. */
e315cd28 2245 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 2246 &area, &domain, &topo, &sw_cap);
2247 }
1da177e4
LT		 2248 }
2249
7c3df132
SK		 2250 if (rval)
2251 ql_dbg(ql_dbg_init, vha, 0x007a,
2252 "**** Load RISC code ****.\n");
1da177e4
LT		 2253
2254 return (rval);
2255}
2256
2257/**
2258 * qla2x00_reset_chip() - Reset ISP chip.
2259 * @ha: HA context
2260 *
2261 * Returns 0 on success.
2262 */
abbd8870 2263void
e315cd28 2264qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 2265{
2266 unsigned long flags = 0;
e315cd28 2267 struct qla_hw_data *ha = vha->hw;
3d71644c 2268 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2269 uint32_t cnt;
1da177e4
LT		 2270 uint16_t cmd;
2271
85880801
AV		 2272 if (unlikely(pci_channel_offline(ha->pdev)))
2273 return;
2274
fd34f556 2275 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 2276
2277 spin_lock_irqsave(&ha->hardware_lock, flags);
2278
2279 /* Turn off master enable */
2280 cmd = 0;
2281 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2282 cmd &= ~PCI_COMMAND_MASTER;
2283 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2284
2285 if (!IS_QLA2100(ha)) {
2286 /* Pause RISC. */
2287 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2288 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2289 for (cnt = 0; cnt < 30000; cnt++) {
2290 if ((RD_REG_WORD(&reg->hccr) &
2291 HCCR_RISC_PAUSE) != 0)
2292 break;
2293 udelay(100);
2294 }
2295 } else {
2296 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2297 udelay(10);
2298 }
2299
2300 /* Select FPM registers. */
2301 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2302 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2303
2304 /* FPM Soft Reset. */
2305 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
2306 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2307
2308 /* Toggle Fpm Reset. */
2309 if (!IS_QLA2200(ha)) {
2310 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
2311 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2312 }
2313
2314 /* Select frame buffer registers. */
2315 WRT_REG_WORD(&reg->ctrl_status, 0x10);
2316 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2317
2318 /* Reset frame buffer FIFOs. */
2319 if (IS_QLA2200(ha)) {
2320 WRT_FB_CMD_REG(ha, reg, 0xa000);
2321 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2322 } else {
2323 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2324
2325 /* Read back fb_cmd until zero or 3 seconds max */
2326 for (cnt = 0; cnt < 3000; cnt++) {
2327 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2328 break;
2329 udelay(100);
2330 }
2331 }
2332
2333 /* Select RISC module registers. */
2334 WRT_REG_WORD(&reg->ctrl_status, 0);
2335 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2336
2337 /* Reset RISC processor. */
2338 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2339 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2340
2341 /* Release RISC processor. */
2342 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2343 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2344 }
2345
2346 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
2347 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
2348
2349 /* Reset ISP chip. */
2350 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2351
2352 /* Wait for RISC to recover from reset. */
2353 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2354 /*
2355 * It is necessary to for a delay here since the card doesn't
2356 * respond to PCI reads during a reset. On some architectures
2357 * this will result in an MCA.
2358 */
2359 udelay(20);
2360 for (cnt = 30000; cnt; cnt--) {
2361 if ((RD_REG_WORD(&reg->ctrl_status) &
2362 CSR_ISP_SOFT_RESET) == 0)
2363 break;
2364 udelay(100);
2365 }
2366 } else
2367 udelay(10);
2368
2369 /* Reset RISC processor. */
2370 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2371
2372 WRT_REG_WORD(&reg->semaphore, 0);
2373
2374 /* Release RISC processor. */
2375 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2376 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2377
2378 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2379 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 2380 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 2381 break;
1da177e4
LT		 2382
2383 udelay(100);
2384 }
2385 } else
2386 udelay(100);
2387
2388 /* Turn on master enable */
2389 cmd |= PCI_COMMAND_MASTER;
2390 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2391
2392 /* Disable RISC pause on FPM parity error. */
2393 if (!IS_QLA2100(ha)) {
2394 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2395 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2396 }
2397
2398 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2399}
2400
b1d46989
MI		 2401/**
2402 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2403 *
2404 * Returns 0 on success.
2405 */
fa492630 2406static int
b1d46989
MI		 2407qla81xx_reset_mpi(scsi_qla_host_t *vha)
2408{
2409 uint16_t mb[4] = {0x1010, 0, 1, 0};
2410
6246b8a1
GM		 2411 if (!IS_QLA81XX(vha->hw))
2412 return QLA_SUCCESS;
2413
b1d46989
MI		 2414 return qla81xx_write_mpi_register(vha, mb);
2415}
2416
0107109e 2417/**
88c26663 2418 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 2419 * @ha: HA context
2420 *
2421 * Returns 0 on success.
2422 */
d14e72fb 2423static inline int
e315cd28 2424qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2425{
2426 unsigned long flags = 0;
e315cd28 2427 struct qla_hw_data *ha = vha->hw;
0107109e 2428 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2429 uint32_t cnt;
335a1cc9 2430 uint16_t wd;
b1d46989 2431 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2432 int rval = QLA_SUCCESS;
0107109e 2433
0107109e
AV		 2434 spin_lock_irqsave(&ha->hardware_lock, flags);
2435
2436 /* Reset RISC. */
2437 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2438 for (cnt = 0; cnt < 30000; cnt++) {
2439 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2440 break;
2441
2442 udelay(10);
2443 }
2444
d14e72fb
HM		 2445 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2446 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2447
2448 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2449 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2450 RD_REG_DWORD(&reg->hccr),
2451 RD_REG_DWORD(&reg->ctrl_status),
2452 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2453
0107109e
AV		 2454 WRT_REG_DWORD(&reg->ctrl_status,
2455 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2456 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2457
335a1cc9 2458 udelay(100);
d14e72fb 2459
88c26663 2460 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2461 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2462 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2463 rval == QLA_SUCCESS; cnt--) {
88c26663 2464 barrier();
d14e72fb
HM		 2465 if (cnt)
2466 udelay(5);
2467 else
2468 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2469 }
2470
d14e72fb
HM		 2471 if (rval == QLA_SUCCESS)
2472 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2473
2474 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2475 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2476 RD_REG_DWORD(&reg->hccr),
2477 RD_REG_DWORD(&reg->mailbox0));
2478
335a1cc9 2479 /* Wait for soft-reset to complete. */
52c82823 2480 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2481 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2482 barrier();
d14e72fb
HM		 2483 if ((RD_REG_DWORD(&reg->ctrl_status) &
2484 CSRX_ISP_SOFT_RESET) == 0)
2485 break;
2486
2487 udelay(5);
0107109e 2488 }
d14e72fb
HM		 2489 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2490 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2491
2492 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2493 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2494 RD_REG_DWORD(&reg->hccr),
2495 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2496
b1d46989
MI		 2497 /* If required, do an MPI FW reset now */
2498 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2499 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2500 if (++abts_cnt < 5) {
2501 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2502 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2503 } else {
2504 /*
2505 * We exhausted the ISP abort retries. We have to
2506 * set the board offline.
2507 */
2508 abts_cnt = 0;
2509 vha->flags.online = 0;
2510 }
2511 }
2512 }
2513
0107109e
AV		 2514 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2515 RD_REG_DWORD(&reg->hccr);
2516
2517 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2518 RD_REG_DWORD(&reg->hccr);
2519
2520 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2521 RD_REG_DWORD(&reg->hccr);
2522
52c82823 2523 RD_REG_WORD(&reg->mailbox0);
200ffb15 2524 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2525 rval == QLA_SUCCESS; cnt--) {
0107109e 2526 barrier();
d14e72fb
HM		 2527 if (cnt)
2528 udelay(5);
2529 else
2530 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2531 }
d14e72fb
HM		 2532 if (rval == QLA_SUCCESS)
2533 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2534
2535 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2536 "Host Risc 0x%x, mailbox0 0x%x\n",
2537 RD_REG_DWORD(&reg->hccr),
2538 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2539
2540 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2541
d14e72fb
HM		 2542 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2543 "Driver in %s mode\n",
2544 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2545
124f85e6
AV		 2546 if (IS_NOPOLLING_TYPE(ha))
2547 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2548
2549 return rval;
0107109e
AV		 2550}
2551
4ea2c9c7
JC		 2552static void
2553qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2554{
2555 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2556
2557 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2558 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2559
2560}
2561
2562static void
2563qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2564{
2565 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2566
2567 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2568 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2569}
2570
2571static void
2572qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2573{
4ea2c9c7
JC		 2574 uint32_t wd32 = 0;
2575 uint delta_msec = 100;
2576 uint elapsed_msec = 0;
2577 uint timeout_msec;
2578 ulong n;
2579
cc790764
JC		 2580 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2581 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2582 return;
2583
8dd7e3a5
JC		 2584 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2585 udelay(100);
2586
4ea2c9c7
JC		 2587attempt:
2588 timeout_msec = TIMEOUT_SEMAPHORE;
2589 n = timeout_msec / delta_msec;
2590 while (n--) {
2591 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2592 qla25xx_read_risc_sema_reg(vha, &wd32);
2593 if (wd32 & RISC_SEMAPHORE)
2594 break;
2595 msleep(delta_msec);
2596 elapsed_msec += delta_msec;
2597 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2598 goto force;
2599 }
2600
2601 if (!(wd32 & RISC_SEMAPHORE))
2602 goto force;
2603
2604 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2605 goto acquired;
2606
2607 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2608 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2609 n = timeout_msec / delta_msec;
2610 while (n--) {
2611 qla25xx_read_risc_sema_reg(vha, &wd32);
2612 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2613 break;
2614 msleep(delta_msec);
2615 elapsed_msec += delta_msec;
2616 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2617 goto force;
2618 }
2619
2620 if (wd32 & RISC_SEMAPHORE_FORCE)
2621 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2622
2623 goto attempt;
2624
2625force:
2626 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2627
2628acquired:
2629 return;
2630}
2631
88c26663
AV		 2632/**
2633 * qla24xx_reset_chip() - Reset ISP24xx chip.
2634 * @ha: HA context
2635 *
2636 * Returns 0 on success.
2637 */
2638void
e315cd28 2639qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2640{
e315cd28 2641 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2642
2643 if (pci_channel_offline(ha->pdev) &&
2644 ha->flags.pci_channel_io_perm_failure) {
2645 return;
2646 }
2647
fd34f556 2648 ha->isp_ops->disable_intrs(ha);
88c26663 2649
4ea2c9c7
JC		 2650 qla25xx_manipulate_risc_semaphore(vha);
2651
88c26663 2652 /* Perform RISC reset. */
e315cd28 2653 qla24xx_reset_risc(vha);
88c26663
AV		 2654}
2655
1da177e4
LT		 2656/**
2657 * qla2x00_chip_diag() - Test chip for proper operation.
2658 * @ha: HA context
2659 *
2660 * Returns 0 on success.
2661 */
abbd8870 2662int
e315cd28 2663qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2664{
2665 int rval;
e315cd28 2666 struct qla_hw_data *ha = vha->hw;
3d71644c 2667 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2668 unsigned long flags = 0;
2669 uint16_t data;
2670 uint32_t cnt;
2671 uint16_t mb[5];
73208dfd 2672 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2673
2674 /* Assume a failed state */
2675 rval = QLA_FUNCTION_FAILED;
2676
7c3df132
SK		 2677 ql_dbg(ql_dbg_init, vha, 0x007b,
2678 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 2679
2680 spin_lock_irqsave(&ha->hardware_lock, flags);
2681
2682 /* Reset ISP chip. */
2683 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2684
2685 /*
2686 * We need to have a delay here since the card will not respond while
2687 * in reset causing an MCA on some architectures.
2688 */
2689 udelay(20);
2690 data = qla2x00_debounce_register(&reg->ctrl_status);
2691 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2692 udelay(5);
2693 data = RD_REG_WORD(&reg->ctrl_status);
2694 barrier();
2695 }
2696
2697 if (!cnt)
2698 goto chip_diag_failed;
2699
7c3df132
SK		 2700 ql_dbg(ql_dbg_init, vha, 0x007c,
2701 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2702
2703 /* Reset RISC processor. */
2704 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2705 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2706
2707 /* Workaround for QLA2312 PCI parity error */
2708 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2709 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2710 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2711 udelay(5);
2712 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2713 barrier();
1da177e4
LT		 2714 }
2715 } else
2716 udelay(10);
2717
2718 if (!cnt)
2719 goto chip_diag_failed;
2720
2721 /* Check product ID of chip */
5a68a1c2 2722 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 2723
2724 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2725 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2726 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2727 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2728 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2729 mb[3] != PROD_ID_3) {
7c3df132
SK		 2730 ql_log(ql_log_warn, vha, 0x0062,
2731 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2732 mb[1], mb[2], mb[3]);
1da177e4
LT		 2733
2734 goto chip_diag_failed;
2735 }
2736 ha->product_id[0] = mb[1];
2737 ha->product_id[1] = mb[2];
2738 ha->product_id[2] = mb[3];
2739 ha->product_id[3] = mb[4];
2740
2741 /* Adjust fw RISC transfer size */
73208dfd 2742 if (req->length > 1024)
1da177e4
LT		 2743 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2744 else
2745 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2746 req->length;
1da177e4
LT		 2747
2748 if (IS_QLA2200(ha) &&
2749 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2750 /* Limit firmware transfer size with a 2200A */
7c3df132 2751 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2752
ea5b6382 2753 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2754 ha->fw_transfer_size = 128;
2755 }
2756
2757 /* Wrap Incoming Mailboxes Test. */
2758 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2759
7c3df132 2760 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2761 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2762 if (rval)
2763 ql_log(ql_log_warn, vha, 0x0080,
2764 "Failed mailbox send register test.\n");
2765 else
1da177e4
LT		 2766 /* Flag a successful rval */
2767 rval = QLA_SUCCESS;
1da177e4
LT		 2768 spin_lock_irqsave(&ha->hardware_lock, flags);
2769
2770chip_diag_failed:
2771 if (rval)
7c3df132
SK		 2772 ql_log(ql_log_info, vha, 0x0081,
2773 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 2774
2775 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2776
2777 return (rval);
2778}
2779
0107109e
AV		 2780/**
2781 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2782 * @ha: HA context
2783 *
2784 * Returns 0 on success.
2785 */
2786int
e315cd28 2787qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 2788{
2789 int rval;
e315cd28 2790 struct qla_hw_data *ha = vha->hw;
73208dfd 2791 struct req_que *req = ha->req_q_map[0];
0107109e 2792
7ec0effd 2793 if (IS_P3P_TYPE(ha))
a9083016
GM		 2794 return QLA_SUCCESS;
2795
73208dfd 2796 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 2797
e315cd28 2798 rval = qla2x00_mbx_reg_test(vha);
0107109e 2799 if (rval) {
7c3df132
SK		 2800 ql_log(ql_log_warn, vha, 0x0082,
2801 "Failed mailbox send register test.\n");
0107109e
AV		 2802 } else {
2803 /* Flag a successful rval */
2804 rval = QLA_SUCCESS;
2805 }
2806
2807 return rval;
2808}
2809
ad0a0b01
QT		 2810static void
2811qla2x00_alloc_offload_mem(scsi_qla_host_t *vha)
0107109e 2812{
a7a167bf 2813 int rval;
df613b96
AV		 2814 dma_addr_t tc_dma;
2815 void *tc;
e315cd28 2816 struct qla_hw_data *ha = vha->hw;
a7a167bf 2817
ad0a0b01 2818 if (ha->eft) {
7c3df132 2819 ql_dbg(ql_dbg_init, vha, 0x00bd,
ad0a0b01
QT		 2820 "%s: Offload Mem is already allocated.\n",
2821 __func__);
a7a167bf
AV		 2822 return;
2823 }
d4e3e04d 2824
ad0a0b01 2825 if (IS_FWI2_CAPABLE(ha)) {
df613b96 2826 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 2827 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2828 !IS_QLA27XX(ha))
436a7b11 2829 goto try_eft;
df613b96 2830
f73cb695
CD		 2831 if (ha->fce)
2832 dma_free_coherent(&ha->pdev->dev,
2833 FCE_SIZE, ha->fce, ha->fce_dma);
2834
2835 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 2836 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
2837 GFP_KERNEL);
df613b96 2838 if (!tc) {
7c3df132
SK		 2839 ql_log(ql_log_warn, vha, 0x00be,
2840 "Unable to allocate (%d KB) for FCE.\n",
2841 FCE_SIZE / 1024);
17d98630 2842 goto try_eft;
df613b96
AV		 2843 }
2844
e315cd28 2845 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 2846 ha->fce_mb, &ha->fce_bufs);
2847 if (rval) {
7c3df132
SK		 2848 ql_log(ql_log_warn, vha, 0x00bf,
2849 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 2850 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
2851 tc_dma);
2852 ha->flags.fce_enabled = 0;
17d98630 2853 goto try_eft;
df613b96 2854 }
cfb0919c 2855 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 2856 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 2857
df613b96
AV		 2858 ha->flags.fce_enabled = 1;
2859 ha->fce_dma = tc_dma;
2860 ha->fce = tc;
f73cb695 2861
436a7b11 2862try_eft:
f73cb695
CD		 2863 if (ha->eft)
2864 dma_free_coherent(&ha->pdev->dev,
2865 EFT_SIZE, ha->eft, ha->eft_dma);
2866
436a7b11 2867 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 2868 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
2869 GFP_KERNEL);
436a7b11 2870 if (!tc) {
7c3df132
SK		 2871 ql_log(ql_log_warn, vha, 0x00c1,
2872 "Unable to allocate (%d KB) for EFT.\n",
2873 EFT_SIZE / 1024);
ad0a0b01 2874 goto eft_err;
436a7b11
AV		 2875 }
2876
e315cd28 2877 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 2878 if (rval) {
7c3df132
SK		 2879 ql_log(ql_log_warn, vha, 0x00c2,
2880 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 2881 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
2882 tc_dma);
ad0a0b01 2883 goto eft_err;
436a7b11 2884 }
cfb0919c 2885 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 2886 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11 2887
436a7b11
AV		 2888 ha->eft_dma = tc_dma;
2889 ha->eft = tc;
d4e3e04d 2890 }
f73cb695 2891
ad0a0b01
QT		 2892eft_err:
2893 return;
2894}
2895
2896void
2897qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
2898{
2899 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
2900 eft_size, fce_size, mq_size;
2901 struct qla_hw_data *ha = vha->hw;
2902 struct req_que *req = ha->req_q_map[0];
2903 struct rsp_que *rsp = ha->rsp_q_map[0];
2904 struct qla2xxx_fw_dump *fw_dump;
2905
2906 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
2907 req_q_size = rsp_q_size = 0;
2908
2909 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2910 fixed_size = sizeof(struct qla2100_fw_dump);
2911 } else if (IS_QLA23XX(ha)) {
2912 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
2913 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
2914 sizeof(uint16_t);
2915 } else if (IS_FWI2_CAPABLE(ha)) {
2916 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
2917 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
2918 else if (IS_QLA81XX(ha))
2919 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
2920 else if (IS_QLA25XX(ha))
2921 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
2922 else
2923 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
2924
2925 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
2926 sizeof(uint32_t);
2927 if (ha->mqenable) {
2928 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
2929 mq_size = sizeof(struct qla2xxx_mq_chain);
2930 /*
2931 * Allocate maximum buffer size for all queues.
2932 * Resizing must be done at end-of-dump processing.
2933 */
2934 mq_size += ha->max_req_queues *
2935 (req->length * sizeof(request_t));
2936 mq_size += ha->max_rsp_queues *
2937 (rsp->length * sizeof(response_t));
2938 }
2939 if (ha->tgt.atio_ring)
2940 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
2941 /* Allocate memory for Fibre Channel Event Buffer. */
2942 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2943 !IS_QLA27XX(ha))
2944 goto try_eft;
2945
2946 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
2947try_eft:
2948 ql_dbg(ql_dbg_init, vha, 0x00c3,
2949 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
2950 eft_size = EFT_SIZE;
2951 }
2952
f73cb695
CD		 2953 if (IS_QLA27XX(ha)) {
2954 if (!ha->fw_dump_template) {
2955 ql_log(ql_log_warn, vha, 0x00ba,
2956 "Failed missing fwdump template\n");
2957 return;
2958 }
2959 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
2960 ql_dbg(ql_dbg_init, vha, 0x00fa,
2961 "-> allocating fwdump (%x bytes)...\n", dump_size);
2962 goto allocate;
2963 }
2964
73208dfd
AC		 2965 req_q_size = req->length * sizeof(request_t);
2966 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 2967 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 2968 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 2969 ha->chain_offset = dump_size;
2970 dump_size += mq_size + fce_size;
d4e3e04d 2971
b945e777
QT		 2972 if (ha->exchoffld_buf)
2973 dump_size += sizeof(struct qla2xxx_offld_chain) +
2974 ha->exchoffld_size;
2975 if (ha->exlogin_buf)
2976 dump_size += sizeof(struct qla2xxx_offld_chain) +
2977 ha->exlogin_size;
2978
f73cb695 2979allocate:
ad0a0b01
QT		 2980 if (!ha->fw_dump_len || dump_size != ha->fw_dump_len) {
2981 fw_dump = vmalloc(dump_size);
2982 if (!fw_dump) {
2983 ql_log(ql_log_warn, vha, 0x00c4,
2984 "Unable to allocate (%d KB) for firmware dump.\n",
2985 dump_size / 1024);
2986 } else {
2987 if (ha->fw_dump)
2988 vfree(ha->fw_dump);
2989 ha->fw_dump = fw_dump;
2990
2991 ha->fw_dump_len = dump_size;
2992 ql_dbg(ql_dbg_init, vha, 0x00c5,
2993 "Allocated (%d KB) for firmware dump.\n",
2994 dump_size / 1024);
2995
2996 if (IS_QLA27XX(ha))
2997 return;
2998
2999 ha->fw_dump->signature[0] = 'Q';
3000 ha->fw_dump->signature[1] = 'L';
3001 ha->fw_dump->signature[2] = 'G';
3002 ha->fw_dump->signature[3] = 'C';
3003 ha->fw_dump->version = htonl(1);
3004
3005 ha->fw_dump->fixed_size = htonl(fixed_size);
3006 ha->fw_dump->mem_size = htonl(mem_size);
3007 ha->fw_dump->req_q_size = htonl(req_q_size);
3008 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
3009
3010 ha->fw_dump->eft_size = htonl(eft_size);
3011 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
3012 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
3013
3014 ha->fw_dump->header_size =
3015 htonl(offsetof(struct qla2xxx_fw_dump, isp));
a7a167bf 3016 }
a7a167bf 3017 }
0107109e
AV		 3018}
3019
18e7555a
AV		 3020static int
3021qla81xx_mpi_sync(scsi_qla_host_t *vha)
3022{
3023#define MPS_MASK 0xe0
3024 int rval;
3025 uint16_t dc;
3026 uint32_t dw;
18e7555a
AV		 3027
3028 if (!IS_QLA81XX(vha->hw))
3029 return QLA_SUCCESS;
3030
3031 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
3032 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3033 ql_log(ql_log_warn, vha, 0x0105,
3034 "Unable to acquire semaphore.\n");
18e7555a
AV		 3035 goto done;
3036 }
3037
3038 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
3039 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
3040 if (rval != QLA_SUCCESS) {
7c3df132 3041 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 3042 goto done_release;
3043 }
3044
3045 dc &= MPS_MASK;
3046 if (dc == (dw & MPS_MASK))
3047 goto done_release;
3048
3049 dw &= ~MPS_MASK;
3050 dw |= dc;
3051 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
3052 if (rval != QLA_SUCCESS) {
7c3df132 3053 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 3054 }
3055
3056done_release:
3057 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
3058 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3059 ql_log(ql_log_warn, vha, 0x006d,
3060 "Unable to release semaphore.\n");
18e7555a
AV		 3061 }
3062
3063done:
3064 return rval;
3065}
3066
8d93f550
CD		 3067int
3068qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
3069{
3070 /* Don't try to reallocate the array */
3071 if (req->outstanding_cmds)
3072 return QLA_SUCCESS;
3073
d7459527 3074 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 3075 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
3076 else {
03e8c680
QT		 3077 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
3078 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 3079 else
03e8c680 3080 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 3081 }
3082
3083 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
3084 req->num_outstanding_cmds, GFP_KERNEL);
3085
3086 if (!req->outstanding_cmds) {
3087 /*
3088 * Try to allocate a minimal size just so we can get through
3089 * initialization.
3090 */
3091 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
3092 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
3093 req->num_outstanding_cmds, GFP_KERNEL);
3094
3095 if (!req->outstanding_cmds) {
3096 ql_log(ql_log_fatal, NULL, 0x0126,
3097 "Failed to allocate memory for "
3098 "outstanding_cmds for req_que %p.\n", req);
3099 req->num_outstanding_cmds = 0;
3100 return QLA_FUNCTION_FAILED;
3101 }
3102 }
3103
3104 return QLA_SUCCESS;
3105}
3106
e4e3a2ce
QT		 3107#define PRINT_FIELD(_field, _flag, _str) { \
3108 if (a0->_field & _flag) {\
3109 if (p) {\
3110 strcat(ptr, "|");\
3111 ptr++;\
3112 leftover--;\
3113 } \
3114 len = snprintf(ptr, leftover, "%s", _str); \
3115 p = 1;\
3116 leftover -= len;\
3117 ptr += len; \
3118 } \
3119}
3120
3121static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
3122{
3123#define STR_LEN 64
3124 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
3125 u8 str[STR_LEN], *ptr, p;
3126 int leftover, len;
3127
3128 memset(str, 0, STR_LEN);
3129 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
3130 ql_dbg(ql_dbg_init, vha, 0x015a,
3131 "SFP MFG Name: %s\n", str);
3132
3133 memset(str, 0, STR_LEN);
3134 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
3135 ql_dbg(ql_dbg_init, vha, 0x015c,
3136 "SFP Part Name: %s\n", str);
3137
3138 /* media */
3139 memset(str, 0, STR_LEN);
3140 ptr = str;
3141 leftover = STR_LEN;
3142 p = len = 0;
3143 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
3144 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
3145 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
3146 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
3147 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
3148 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
3149 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
3150 ql_dbg(ql_dbg_init, vha, 0x0160,
3151 "SFP Media: %s\n", str);
3152
3153 /* link length */
3154 memset(str, 0, STR_LEN);
3155 ptr = str;
3156 leftover = STR_LEN;
3157 p = len = 0;
3158 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
3159 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
3160 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
3161 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
3162 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
3163 ql_dbg(ql_dbg_init, vha, 0x0196,
3164 "SFP Link Length: %s\n", str);
3165
3166 memset(str, 0, STR_LEN);
3167 ptr = str;
3168 leftover = STR_LEN;
3169 p = len = 0;
3170 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
3171 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
3172 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
3173 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
3174 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
3175 ql_dbg(ql_dbg_init, vha, 0x016e,
3176 "SFP FC Link Tech: %s\n", str);
3177
3178 if (a0->length_km)
3179 ql_dbg(ql_dbg_init, vha, 0x016f,
3180 "SFP Distant: %d km\n", a0->length_km);
3181 if (a0->length_100m)
3182 ql_dbg(ql_dbg_init, vha, 0x0170,
3183 "SFP Distant: %d m\n", a0->length_100m*100);
3184 if (a0->length_50um_10m)
3185 ql_dbg(ql_dbg_init, vha, 0x0189,
3186 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
3187 if (a0->length_62um_10m)
3188 ql_dbg(ql_dbg_init, vha, 0x018a,
3189 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
3190 if (a0->length_om4_10m)
3191 ql_dbg(ql_dbg_init, vha, 0x0194,
3192 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
3193 if (a0->length_om3_10m)
3194 ql_dbg(ql_dbg_init, vha, 0x0195,
3195 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
3196}
3197
3198
3199/*
3200 * Return Code:
3201 * QLA_SUCCESS: no action
3202 * QLA_INTERFACE_ERROR: SFP is not there.
3203 * QLA_FUNCTION_FAILED: detected New SFP
3204 */
3205int
3206qla24xx_detect_sfp(scsi_qla_host_t *vha)
3207{
3208 int rc = QLA_SUCCESS;
3209 struct sff_8247_a0 *a;
3210 struct qla_hw_data *ha = vha->hw;
3211
3212 if (!AUTO_DETECT_SFP_SUPPORT(vha))
3213 goto out;
3214
3215 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
3216 if (rc)
3217 goto out;
3218
3219 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
3220 qla2xxx_print_sfp_info(vha);
3221
3222 if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
3223 /* long range */
3224 ha->flags.detected_lr_sfp = 1;
3225
3226 if (a->length_km > 5 || a->length_100m > 50)
3227 ha->long_range_distance = LR_DISTANCE_10K;
3228 else
3229 ha->long_range_distance = LR_DISTANCE_5K;
3230
3231 if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
3232 ql_dbg(ql_dbg_async, vha, 0x507b,
3233 "Detected Long Range SFP.\n");
3234 } else {
3235 /* short range */
3236 ha->flags.detected_lr_sfp = 0;
3237 if (ha->flags.using_lr_setting)
3238 ql_dbg(ql_dbg_async, vha, 0x5084,
3239 "Detected Short Range SFP.\n");
3240 }
3241
3242 if (!vha->flags.init_done)
3243 rc = QLA_SUCCESS;
3244out:
3245 return rc;
3246}
3247
1da177e4
LT		 3248/**
3249 * qla2x00_setup_chip() - Load and start RISC firmware.
3250 * @ha: HA context
3251 *
3252 * Returns 0 on success.
3253 */
3254static int
e315cd28 3255qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 3256{
0107109e
AV		 3257 int rval;
3258 uint32_t srisc_address = 0;
e315cd28 3259 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 3260 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3261 unsigned long flags;
dda772e8 3262 uint16_t fw_major_version;
3db0652e 3263
7ec0effd 3264 if (IS_P3P_TYPE(ha)) {
a9083016 3265 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 3266 if (rval == QLA_SUCCESS) {
3267 qla2x00_stop_firmware(vha);
a9083016 3268 goto enable_82xx_npiv;
14e303d9 3269 } else
b963752f 3270 goto failed;
a9083016
GM		 3271 }
3272
3db0652e
AV		 3273 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3274 /* Disable SRAM, Instruction RAM and GP RAM parity. */
3275 spin_lock_irqsave(&ha->hardware_lock, flags);
3276 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
3277 RD_REG_WORD(&reg->hccr);
3278 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3279 }
1da177e4 3280
18e7555a
AV		 3281 qla81xx_mpi_sync(vha);
3282
1da177e4 3283 /* Load firmware sequences */
e315cd28 3284 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 3285 if (rval == QLA_SUCCESS) {
7c3df132
SK		 3286 ql_dbg(ql_dbg_init, vha, 0x00c9,
3287 "Verifying Checksum of loaded RISC code.\n");
1da177e4 3288
e315cd28 3289 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 3290 if (rval == QLA_SUCCESS) {
3291 /* Start firmware execution. */
7c3df132
SK		 3292 ql_dbg(ql_dbg_init, vha, 0x00ca,
3293 "Starting firmware.\n");
1da177e4 3294
b0d6cabd
HM		 3295 if (ql2xexlogins)
3296 ha->flags.exlogins_enabled = 1;
3297
99e1b683 3298 if (qla_is_exch_offld_enabled(vha))
2f56a7f1
HM		 3299 ha->flags.exchoffld_enabled = 1;
3300
e315cd28 3301 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 3302 /* Retrieve firmware information. */
dda772e8 3303 if (rval == QLA_SUCCESS) {
e4e3a2ce
QT		 3304 qla24xx_detect_sfp(vha);
3305
b0d6cabd
HM		 3306 rval = qla2x00_set_exlogins_buffer(vha);
3307 if (rval != QLA_SUCCESS)
3308 goto failed;
3309
2f56a7f1
HM		 3310 rval = qla2x00_set_exchoffld_buffer(vha);
3311 if (rval != QLA_SUCCESS)
3312 goto failed;
3313
a9083016 3314enable_82xx_npiv:
dda772e8 3315 fw_major_version = ha->fw_major_version;
7ec0effd 3316 if (IS_P3P_TYPE(ha))
3173167f 3317 qla82xx_check_md_needed(vha);
6246b8a1
GM		 3318 else
3319 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 3320 if (rval != QLA_SUCCESS)
3321 goto failed;
2c3dfe3f 3322 ha->flags.npiv_supported = 0;
e315cd28 3323 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 3324 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 3325 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 3326 if ((!ha->max_npiv_vports) ||
3327 ((ha->max_npiv_vports + 1) %
eb66dc60 3328 MIN_MULTI_ID_FABRIC))
4d0ea247 3329 ha->max_npiv_vports =
eb66dc60 3330 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 3331 }
03e8c680 3332 qla2x00_get_resource_cnts(vha);
d743de66 3333
8d93f550
CD		 3334 /*
3335 * Allocate the array of outstanding commands
3336 * now that we know the firmware resources.
3337 */
3338 rval = qla2x00_alloc_outstanding_cmds(ha,
3339 vha->req);
3340 if (rval != QLA_SUCCESS)
3341 goto failed;
3342
ad0a0b01
QT		 3343 if (!fw_major_version && !(IS_P3P_TYPE(ha)))
3344 qla2x00_alloc_offload_mem(vha);
3345
3346 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
08de2844 3347 qla2x00_alloc_fw_dump(vha);
ad0a0b01 3348
3b6e5b9d
CD		 3349 } else {
3350 goto failed;
1da177e4
LT		 3351 }
3352 } else {
7c3df132
SK		 3353 ql_log(ql_log_fatal, vha, 0x00cd,
3354 "ISP Firmware failed checksum.\n");
3355 goto failed;
1da177e4 3356 }
c74d88a4
AV		 3357 } else
3358 goto failed;
1da177e4 3359
3db0652e
AV		 3360 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3361 /* Enable proper parity. */
3362 spin_lock_irqsave(&ha->hardware_lock, flags);
3363 if (IS_QLA2300(ha))
3364 /* SRAM parity */
3365 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
3366 else
3367 /* SRAM, Instruction RAM and GP RAM parity */
3368 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
3369 RD_REG_WORD(&reg->hccr);
3370 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3371 }
3372
f3982d89
CD		 3373 if (IS_QLA27XX(ha))
3374 ha->flags.fac_supported = 1;
3375 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 3376 uint32_t size;
3377
3378 rval = qla81xx_fac_get_sector_size(vha, &size);
3379 if (rval == QLA_SUCCESS) {
3380 ha->flags.fac_supported = 1;
3381 ha->fdt_block_size = size << 2;
3382 } else {
7c3df132 3383 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 3384 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3385 ha->fw_major_version, ha->fw_minor_version,
3386 ha->fw_subminor_version);
1ca60e3b 3387
f73cb695 3388 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 3389 ha->flags.fac_supported = 0;
3390 rval = QLA_SUCCESS;
3391 }
1d2874de
JC		 3392 }
3393 }
ca9e9c3e 3394failed:
1da177e4 3395 if (rval) {
7c3df132
SK		 3396 ql_log(ql_log_fatal, vha, 0x00cf,
3397 "Setup chip ****FAILED****.\n");
1da177e4
LT		 3398 }
3399
3400 return (rval);
3401}
3402
3403/**
3404 * qla2x00_init_response_q_entries() - Initializes response queue entries.
3405 * @ha: HA context
3406 *
3407 * Beginning of request ring has initialization control block already built
3408 * by nvram config routine.
3409 *
3410 * Returns 0 on success.
3411 */
73208dfd
AC		 3412void
3413qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 3414{
3415 uint16_t cnt;
3416 response_t *pkt;
3417
2afa19a9
AC		 3418 rsp->ring_ptr = rsp->ring;
3419 rsp->ring_index = 0;
3420 rsp->status_srb = NULL;
e315cd28
AC		 3421 pkt = rsp->ring_ptr;
3422 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 3423 pkt->signature = RESPONSE_PROCESSED;
3424 pkt++;
3425 }
1da177e4
LT		 3426}
3427
3428/**
3429 * qla2x00_update_fw_options() - Read and process firmware options.
3430 * @ha: HA context
3431 *
3432 * Returns 0 on success.
3433 */
abbd8870 3434void
e315cd28 3435qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 3436{
3437 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 3438 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3439
3440 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 3441 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 3442
3443 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3444 return;
3445
3446 /* Serial Link options. */
7c3df132
SK		 3447 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3448 "Serial link options.\n");
3449 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
3450 (uint8_t *)&ha->fw_seriallink_options,
3451 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 3452
3453 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3454 if (ha->fw_seriallink_options[3] & BIT_2) {
3455 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3456
3457 /* 1G settings */
3458 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3459 emphasis = (ha->fw_seriallink_options[2] &
3460 (BIT_4 | BIT_3)) >> 3;
3461 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 3462 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3463 rx_sens = (ha->fw_seriallink_options[0] &
3464 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3465 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3466 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3467 if (rx_sens == 0x0)
3468 rx_sens = 0x3;
3469 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3470 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3471 ha->fw_options[10] |= BIT_5 |
3472 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3473 (tx_sens & (BIT_1 | BIT_0));
3474
3475 /* 2G settings */
3476 swing = (ha->fw_seriallink_options[2] &
3477 (BIT_7 | BIT_6 | BIT_5)) >> 5;
3478 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
3479 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 3480 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3481 rx_sens = (ha->fw_seriallink_options[1] &
3482 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3483 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
3484 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3485 if (rx_sens == 0x0)
3486 rx_sens = 0x3;
3487 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
3488 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3489 ha->fw_options[11] |= BIT_5 |
3490 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3491 (tx_sens & (BIT_1 | BIT_0));
3492 }
3493
3494 /* FCP2 options. */
3495 /* Return command IOCBs without waiting for an ABTS to complete. */
3496 ha->fw_options[3] |= BIT_13;
3497
3498 /* LED scheme. */
3499 if (ha->flags.enable_led_scheme)
3500 ha->fw_options[2] |= BIT_12;
3501
48c02fde 3502 /* Detect ISP6312. */
3503 if (IS_QLA6312(ha))
3504 ha->fw_options[2] |= BIT_13;
3505
088d09d4
GM		 3506 /* Set Retry FLOGI in case of P2P connection */
3507 if (ha->operating_mode == P2P) {
3508 ha->fw_options[2] |= BIT_3;
3509 ql_dbg(ql_dbg_disc, vha, 0x2100,
3510 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3511 __func__, ha->fw_options[2]);
3512 }
3513
1da177e4 3514 /* Update firmware options. */
e315cd28 3515 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 3516}
3517
0107109e 3518void
e315cd28 3519qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 3520{
3521 int rval;
e315cd28 3522 struct qla_hw_data *ha = vha->hw;
0107109e 3523
7ec0effd 3524 if (IS_P3P_TYPE(ha))
a9083016
GM		 3525 return;
3526
f198cafa
HM		 3527 /* Hold status IOCBs until ABTS response received. */
3528 if (ql2xfwholdabts)
3529 ha->fw_options[3] |= BIT_12;
3530
088d09d4
GM		 3531 /* Set Retry FLOGI in case of P2P connection */
3532 if (ha->operating_mode == P2P) {
3533 ha->fw_options[2] |= BIT_3;
3534 ql_dbg(ql_dbg_disc, vha, 0x2101,
3535 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3536 __func__, ha->fw_options[2]);
3537 }
3538
41dc529a 3539 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff
QT		 3540 if (ql2xmvasynctoatio &&
3541 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
41dc529a
QT		 3542 if (qla_tgt_mode_enabled(vha) ||
3543 qla_dual_mode_enabled(vha))
3544 ha->fw_options[2] |= BIT_11;
3545 else
3546 ha->fw_options[2] &= ~BIT_11;
3547 }
3548
f7e761f5
QT		 3549 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3550 /*
3551 * Tell FW to track each exchange to prevent
3552 * driver from using stale exchange.
3553 */
3554 if (qla_tgt_mode_enabled(vha) ||
3555 qla_dual_mode_enabled(vha))
3556 ha->fw_options[2] |= BIT_4;
3557 else
3558 ha->fw_options[2] &= ~BIT_4;
9ecf0b0d
QT		 3559
3560 /* Reserve 1/2 of emergency exchanges for ELS.*/
3561 if (qla2xuseresexchforels)
3562 ha->fw_options[2] |= BIT_8;
3563 else
3564 ha->fw_options[2] &= ~BIT_8;
f7e761f5
QT		 3565 }
3566
83548fe2
QT		 3567 ql_dbg(ql_dbg_init, vha, 0x00e8,
3568 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3569 __func__, ha->fw_options[1], ha->fw_options[2],
3570 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 3571
3572 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
3573 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 3574
0107109e 3575 /* Update Serial Link options. */
f94097ed 3576 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3577 return;
3578
e315cd28 3579 rval = qla2x00_set_serdes_params(vha,
f94097ed 3580 le16_to_cpu(ha->fw_seriallink_options24[1]),
3581 le16_to_cpu(ha->fw_seriallink_options24[2]),
3582 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3583 if (rval != QLA_SUCCESS) {
7c3df132 3584 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3585 "Unable to update Serial Link options (%x).\n", rval);
3586 }
3587}
3588
abbd8870 3589void
e315cd28 3590qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3591{
e315cd28 3592 struct qla_hw_data *ha = vha->hw;
3d71644c 3593 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3594 struct req_que *req = ha->req_q_map[0];
3595 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3596
3597 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3598 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3599 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3600 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3601 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
3602 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3603 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3604 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3605 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 3606
3607 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3608 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3609 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3610 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3611 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3612}
3613
0107109e 3614void
e315cd28 3615qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3616{
e315cd28 3617 struct qla_hw_data *ha = vha->hw;
118e2ef9 3618 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3619 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3620 struct qla_msix_entry *msix;
0107109e 3621 struct init_cb_24xx *icb;
73208dfd
AC		 3622 uint16_t rid = 0;
3623 struct req_que *req = ha->req_q_map[0];
3624 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3625
6246b8a1 3626 /* Setup ring parameters in initialization control block. */
0107109e 3627 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3628 icb->request_q_outpointer = cpu_to_le16(0);
3629 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3630 icb->request_q_length = cpu_to_le16(req->length);
3631 icb->response_q_length = cpu_to_le16(rsp->length);
3632 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3633 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3634 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3635 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3636
2d70c103 3637 /* Setup ATIO queue dma pointers for target mode */
ad950360 3638 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3639 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3640 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3641 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3642
7c6300e3 3643 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3644 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3645
f73cb695 3646 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3647 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3648 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3649 if (ha->flags.msix_enabled) {
3650 msix = &ha->msix_entries[1];
83548fe2 3651 ql_dbg(ql_dbg_init, vha, 0x0019,
7c3df132
SK		 3652 "Registering vector 0x%x for base que.\n",
3653 msix->entry);
73208dfd
AC		 3654 icb->msix = cpu_to_le16(msix->entry);
3655 }
3656 /* Use alternate PCI bus number */
3657 if (MSB(rid))
ad950360 3658 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3659 /* Use alternate PCI devfn */
3660 if (LSB(rid))
ad950360 3661 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3662
3155754a 3663 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3664 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3665 (ha->flags.msix_enabled)) {
ad950360 3666 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3667 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3668 ql_dbg(ql_dbg_init, vha, 0x00fe,
3669 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3670 } else {
ad950360 3671 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3672 }
ad950360 3673 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3674
3675 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3676 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3677 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3678 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3679 } else {
3680 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3681 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3682 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3683 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3684 }
aa230bc5 3685 qlt_24xx_config_rings(vha);
2d70c103 3686
73208dfd
AC		 3687 /* PCI posting */
3688 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3689}
3690
1da177e4
LT		 3691/**
3692 * qla2x00_init_rings() - Initializes firmware.
3693 * @ha: HA context
3694 *
3695 * Beginning of request ring has initialization control block already built
3696 * by nvram config routine.
3697 *
3698 * Returns 0 on success.
3699 */
8ae6d9c7 3700int
e315cd28 3701qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3702{
3703 int rval;
3704 unsigned long flags = 0;
29bdccbe 3705 int cnt, que;
e315cd28 3706 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3707 struct req_que *req;
3708 struct rsp_que *rsp;
2c3dfe3f
SJ		 3709 struct mid_init_cb_24xx *mid_init_cb =
3710 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3711
3712 spin_lock_irqsave(&ha->hardware_lock, flags);
3713
3714 /* Clear outstanding commands array. */
2afa19a9 3715 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3716 req = ha->req_q_map[que];
cb43285f 3717 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3718 continue;
7c6300e3
JC		 3719 req->out_ptr = (void *)(req->ring + req->length);
3720 *req->out_ptr = 0;
8d93f550 3721 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3722 req->outstanding_cmds[cnt] = NULL;
1da177e4 3723
2afa19a9 3724 req->current_outstanding_cmd = 1;
1da177e4 3725
29bdccbe
AC		 3726 /* Initialize firmware. */
3727 req->ring_ptr = req->ring;
3728 req->ring_index = 0;
3729 req->cnt = req->length;
3730 }
1da177e4 3731
2afa19a9 3732 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3733 rsp = ha->rsp_q_map[que];
cb43285f 3734 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3735 continue;
7c6300e3
JC		 3736 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3737 *rsp->in_ptr = 0;
29bdccbe 3738 /* Initialize response queue entries */
8ae6d9c7
GM		 3739 if (IS_QLAFX00(ha))
3740 qlafx00_init_response_q_entries(rsp);
3741 else
3742 qla2x00_init_response_q_entries(rsp);
29bdccbe 3743 }
1da177e4 3744
2d70c103
NB		 3745 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3746 ha->tgt.atio_ring_index = 0;
3747 /* Initialize ATIO queue entries */
3748 qlt_init_atio_q_entries(vha);
3749
e315cd28 3750 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3751
3752 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3753
8ae6d9c7
GM		 3754 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3755
3756 if (IS_QLAFX00(ha)) {
3757 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3758 goto next_check;
3759 }
3760
1da177e4 3761 /* Update any ISP specific firmware options before initialization. */
e315cd28 3762 ha->isp_ops->update_fw_options(vha);
1da177e4 3763
605aa2bc 3764 if (ha->flags.npiv_supported) {
45980cc2 3765 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 3766 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 3767 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 3768 }
3769
24a08138 3770 if (IS_FWI2_CAPABLE(ha)) {
ad950360 3771 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 3772 mid_init_cb->init_cb.execution_throttle =
03e8c680 3773 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 3774 ha->flags.dport_enabled =
3775 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
3776 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
3777 (ha->flags.dport_enabled) ? "enabled" : "disabled");
3778 /* FA-WWPN Status */
2486c627 3779 ha->flags.fawwpn_enabled =
40f3862b 3780 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
83548fe2 3781 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
2486c627 3782 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 3783 }
2c3dfe3f 3784
e315cd28 3785 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 3786next_check:
1da177e4 3787 if (rval) {
7c3df132
SK		 3788 ql_log(ql_log_fatal, vha, 0x00d2,
3789 "Init Firmware **** FAILED ****.\n");
1da177e4 3790 } else {
7c3df132
SK		 3791 ql_dbg(ql_dbg_init, vha, 0x00d3,
3792 "Init Firmware -- success.\n");
4b60c827 3793 QLA_FW_STARTED(ha);
1da177e4
LT		 3794 }
3795
3796 return (rval);
3797}
3798
3799/**
3800 * qla2x00_fw_ready() - Waits for firmware ready.
3801 * @ha: HA context
3802 *
3803 * Returns 0 on success.
3804 */
3805static int
e315cd28 3806qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 3807{
3808 int rval;
4d4df193 3809 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 3810 uint16_t min_wait; /* Minimum wait time if loop is down */
3811 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 3812 uint16_t state[6];
e315cd28 3813 struct qla_hw_data *ha = vha->hw;
1da177e4 3814
8ae6d9c7
GM		 3815 if (IS_QLAFX00(vha->hw))
3816 return qlafx00_fw_ready(vha);
3817
1da177e4
LT		 3818 rval = QLA_SUCCESS;
3819
33461491
CD		 3820 /* Time to wait for loop down */
3821 if (IS_P3P_TYPE(ha))
3822 min_wait = 30;
3823 else
3824 min_wait = 20;
1da177e4
LT		 3825
3826 /*
3827 * Firmware should take at most one RATOV to login, plus 5 seconds for
3828 * our own processing.
3829 */
3830 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
3831 wait_time = min_wait;
3832 }
3833
3834 /* Min wait time if loop down */
3835 mtime = jiffies + (min_wait * HZ);
3836
3837 /* wait time before firmware ready */
3838 wtime = jiffies + (wait_time * HZ);
3839
3840 /* Wait for ISP to finish LIP */
e315cd28 3841 if (!vha->flags.init_done)
7c3df132
SK		 3842 ql_log(ql_log_info, vha, 0x801e,
3843 "Waiting for LIP to complete.\n");
1da177e4
LT		 3844
3845 do {
5b939038 3846 memset(state, -1, sizeof(state));
e315cd28 3847 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 3848 if (rval == QLA_SUCCESS) {
4d4df193 3849 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 3850 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 3851 }
4d4df193 3852 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 3853 ql_dbg(ql_dbg_taskm, vha, 0x801f,
3854 "fw_state=%x 84xx=%x.\n", state[0],
3855 state[2]);
4d4df193
HK		 3856 if ((state[2] & FSTATE_LOGGED_IN) &&
3857 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 3858 ql_dbg(ql_dbg_taskm, vha, 0x8028,
3859 "Sending verify iocb.\n");
4d4df193
HK		 3860
3861 cs84xx_time = jiffies;
e315cd28 3862 rval = qla84xx_init_chip(vha);
7c3df132
SK		 3863 if (rval != QLA_SUCCESS) {
3864 ql_log(ql_log_warn,
cfb0919c 3865 vha, 0x8007,
7c3df132 3866 "Init chip failed.\n");
4d4df193 3867 break;
7c3df132 3868 }
4d4df193
HK		 3869
3870 /* Add time taken to initialize. */
3871 cs84xx_time = jiffies - cs84xx_time;
3872 wtime += cs84xx_time;
3873 mtime += cs84xx_time;
cfb0919c 3874 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 3875 "Increasing wait time by %ld. "
3876 "New time %ld.\n", cs84xx_time,
3877 wtime);
4d4df193
HK		 3878 }
3879 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 3880 ql_dbg(ql_dbg_taskm, vha, 0x8037,
3881 "F/W Ready - OK.\n");
1da177e4 3882
e315cd28 3883 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 3884 &ha->login_timeout, &ha->r_a_tov);
3885
3886 rval = QLA_SUCCESS;
3887 break;
3888 }
3889
3890 rval = QLA_FUNCTION_FAILED;
3891
e315cd28 3892 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 3893 state[0] != FSTATE_READY) {
1da177e4 3894 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 3895 * other than Wait for Login.
3896 */
1da177e4 3897 if (time_after_eq(jiffies, mtime)) {
7c3df132 3898 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 3899 "Cable is unplugged...\n");
3900
e315cd28 3901 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 3902 break;
3903 }
3904 }
3905 } else {
3906 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 3907 if (time_after_eq(jiffies, mtime) ||
7190575f 3908 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 3909 break;
3910 }
3911
3912 if (time_after_eq(jiffies, wtime))
3913 break;
3914
3915 /* Delay for a while */
3916 msleep(500);
1da177e4
LT		 3917 } while (1);
3918
7c3df132 3919 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 3920 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
3921 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 3922
cfb0919c 3923 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 3924 ql_log(ql_log_warn, vha, 0x803b,
3925 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 3926 }
3927
3928 return (rval);
3929}
3930
3931/*
3932* qla2x00_configure_hba
3933* Setup adapter context.
3934*
3935* Input:
3936* ha = adapter state pointer.
3937*
3938* Returns:
3939* 0 = success
3940*
3941* Context:
3942* Kernel context.
3943*/
3944static int
e315cd28 3945qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 3946{
3947 int rval;
3948 uint16_t loop_id;
3949 uint16_t topo;
2c3dfe3f 3950 uint16_t sw_cap;
1da177e4
LT		 3951 uint8_t al_pa;
3952 uint8_t area;
3953 uint8_t domain;
3954 char connect_type[22];
e315cd28 3955 struct qla_hw_data *ha = vha->hw;
61e1b269 3956 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 3957 port_id_t id;
9d1aa4e1 3958 unsigned long flags;
1da177e4
LT		 3959
3960 /* Get host addresses. */
e315cd28 3961 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 3962 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 3963 if (rval != QLA_SUCCESS) {
e315cd28 3964 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 3965 IS_CNA_CAPABLE(ha) ||
33135aa2 3966 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 3967 ql_dbg(ql_dbg_disc, vha, 0x2008,
3968 "Loop is in a transition state.\n");
33135aa2 3969 } else {
7c3df132
SK		 3970 ql_log(ql_log_warn, vha, 0x2009,
3971 "Unable to get host loop ID.\n");
61e1b269
JC		 3972 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
3973 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
3974 ql_log(ql_log_warn, vha, 0x1151,
3975 "Doing link init.\n");
3976 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
3977 return rval;
3978 }
e315cd28 3979 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 3980 }
1da177e4
LT		 3981 return (rval);
3982 }
3983
3984 if (topo == 4) {
7c3df132
SK		 3985 ql_log(ql_log_info, vha, 0x200a,
3986 "Cannot get topology - retrying.\n");
1da177e4
LT		 3987 return (QLA_FUNCTION_FAILED);
3988 }
3989
e315cd28 3990 vha->loop_id = loop_id;
1da177e4
LT		 3991
3992 /* initialize */
3993 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
3994 ha->operating_mode = LOOP;
2c3dfe3f 3995 ha->switch_cap = 0;
1da177e4
LT		 3996
3997 switch (topo) {
3998 case 0:
7c3df132 3999 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 4000 ha->current_topology = ISP_CFG_NL;
4001 strcpy(connect_type, "(Loop)");
4002 break;
4003
4004 case 1:
7c3df132 4005 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 4006 ha->switch_cap = sw_cap;
1da177e4
LT		 4007 ha->current_topology = ISP_CFG_FL;
4008 strcpy(connect_type, "(FL_Port)");
4009 break;
4010
4011 case 2:
7c3df132 4012 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 4013 ha->operating_mode = P2P;
4014 ha->current_topology = ISP_CFG_N;
4015 strcpy(connect_type, "(N_Port-to-N_Port)");
4016 break;
4017
4018 case 3:
7c3df132 4019 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 4020 ha->switch_cap = sw_cap;
1da177e4
LT		 4021 ha->operating_mode = P2P;
4022 ha->current_topology = ISP_CFG_F;
4023 strcpy(connect_type, "(F_Port)");
4024 break;
4025
4026 default:
7c3df132
SK		 4027 ql_dbg(ql_dbg_disc, vha, 0x200f,
4028 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 4029 ha->current_topology = ISP_CFG_NL;
4030 strcpy(connect_type, "(Loop)");
4031 break;
4032 }
4033
4034 /* Save Host port and loop ID. */
4035 /* byte order - Big Endian */
482c9dc7
QT		 4036 id.b.domain = domain;
4037 id.b.area = area;
4038 id.b.al_pa = al_pa;
4039 id.b.rsvd_1 = 0;
9d1aa4e1 4040 spin_lock_irqsave(&ha->hardware_lock, flags);
482c9dc7 4041 qlt_update_host_map(vha, id);
9d1aa4e1 4042 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2d70c103 4043
e315cd28 4044 if (!vha->flags.init_done)
7c3df132
SK		 4045 ql_log(ql_log_info, vha, 0x2010,
4046 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 4047 connect_type, vha->loop_id);
1da177e4 4048
1da177e4
LT		 4049 return(rval);
4050}
4051
a9083016 4052inline void
e315cd28
AC		 4053qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
4054 char *def)
9bb9fcf2
AV		 4055{
4056 char *st, *en;
4057 uint16_t index;
e315cd28 4058 struct qla_hw_data *ha = vha->hw;
ab671149 4059 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 4060 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 4061
4062 if (memcmp(model, BINZERO, len) != 0) {
4063 strncpy(ha->model_number, model, len);
4064 st = en = ha->model_number;
4065 en += len - 1;
4066 while (en > st) {
4067 if (*en != 0x20 && *en != 0x00)
4068 break;
4069 *en-- = '\0';
4070 }
4071
4072 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4073 if (use_tbl &&
4074 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 4075 index < QLA_MODEL_NAMES)
1ee27146
JC		 4076 strncpy(ha->model_desc,
4077 qla2x00_model_name[index * 2 + 1],
4078 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4079 } else {
4080 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4081 if (use_tbl &&
4082 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 4083 index < QLA_MODEL_NAMES) {
4084 strcpy(ha->model_number,
4085 qla2x00_model_name[index * 2]);
1ee27146
JC		 4086 strncpy(ha->model_desc,
4087 qla2x00_model_name[index * 2 + 1],
4088 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4089 } else {
4090 strcpy(ha->model_number, def);
4091 }
4092 }
1ee27146 4093 if (IS_FWI2_CAPABLE(ha))
e315cd28 4094 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 4095 sizeof(ha->model_desc));
9bb9fcf2
AV		 4096}
4097
4e08df3f
DM		 4098/* On sparc systems, obtain port and node WWN from firmware
4099 * properties.
4100 */
e315cd28 4101static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 4102{
4103#ifdef CONFIG_SPARC
e315cd28 4104 struct qla_hw_data *ha = vha->hw;
4e08df3f 4105 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4106 struct device_node *dp = pci_device_to_OF_node(pdev);
4107 const u8 *val;
4e08df3f
DM		 4108 int len;
4109
4110 val = of_get_property(dp, "port-wwn", &len);
4111 if (val && len >= WWN_SIZE)
4112 memcpy(nv->port_name, val, WWN_SIZE);
4113
4114 val = of_get_property(dp, "node-wwn", &len);
4115 if (val && len >= WWN_SIZE)
4116 memcpy(nv->node_name, val, WWN_SIZE);
4117#endif
4118}
4119
1da177e4
LT		 4120/*
4121* NVRAM configuration for ISP 2xxx
4122*
4123* Input:
4124* ha = adapter block pointer.
4125*
4126* Output:
4127* initialization control block in response_ring
4128* host adapters parameters in host adapter block
4129*
4130* Returns:
4131* 0 = success.
4132*/
abbd8870 4133int
e315cd28 4134qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 4135{
4e08df3f 4136 int rval;
0107109e
AV		 4137 uint8_t chksum = 0;
4138 uint16_t cnt;
4139 uint8_t *dptr1, *dptr2;
e315cd28 4140 struct qla_hw_data *ha = vha->hw;
0107109e 4141 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 4142 nvram_t *nv = ha->nvram;
4143 uint8_t *ptr = ha->nvram;
3d71644c 4144 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4145
4e08df3f
DM		 4146 rval = QLA_SUCCESS;
4147
1da177e4 4148 /* Determine NVRAM starting address. */
0107109e 4149 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 4150 ha->nvram_base = 0;
4151 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
4152 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
4153 ha->nvram_base = 0x80;
4154
4155 /* Get NVRAM data and calculate checksum. */
e315cd28 4156 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 4157 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
4158 chksum += *ptr++;
1da177e4 4159
7c3df132
SK		 4160 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
4161 "Contents of NVRAM.\n");
4162 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
4163 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 4164
4165 /* Bad NVRAM data, set defaults parameters. */
4166 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
4167 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
4168 /* Reset NVRAM data. */
7c3df132 4169 ql_log(ql_log_warn, vha, 0x0064,
9e336520 4170 "Inconsistent NVRAM "
7c3df132
SK		 4171 "detected: checksum=0x%x id=%c version=0x%x.\n",
4172 chksum, nv->id[0], nv->nvram_version);
4173 ql_log(ql_log_warn, vha, 0x0065,
4174 "Falling back to "
4175 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 4176
4177 /*
4178 * Set default initialization control block.
4179 */
4180 memset(nv, 0, ha->nvram_size);
4181 nv->parameter_block_version = ICB_VERSION;
4182
4183 if (IS_QLA23XX(ha)) {
4184 nv->firmware_options[0] = BIT_2 | BIT_1;
4185 nv->firmware_options[1] = BIT_7 | BIT_5;
4186 nv->add_firmware_options[0] = BIT_5;
4187 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4188 nv->frame_payload_size = 2048;
4e08df3f
DM		 4189 nv->special_options[1] = BIT_7;
4190 } else if (IS_QLA2200(ha)) {
4191 nv->firmware_options[0] = BIT_2 | BIT_1;
4192 nv->firmware_options[1] = BIT_7 | BIT_5;
4193 nv->add_firmware_options[0] = BIT_5;
4194 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4195 nv->frame_payload_size = 1024;
4e08df3f
DM		 4196 } else if (IS_QLA2100(ha)) {
4197 nv->firmware_options[0] = BIT_3 | BIT_1;
4198 nv->firmware_options[1] = BIT_5;
98aee70d 4199 nv->frame_payload_size = 1024;
4e08df3f
DM		 4200 }
4201
ad950360
BVA		 4202 nv->max_iocb_allocation = cpu_to_le16(256);
4203 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 4204 nv->retry_count = 8;
4205 nv->retry_delay = 1;
4206
4207 nv->port_name[0] = 33;
4208 nv->port_name[3] = 224;
4209 nv->port_name[4] = 139;
4210
e315cd28 4211 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4212
4213 nv->login_timeout = 4;
4214
4215 /*
4216 * Set default host adapter parameters
4217 */
4218 nv->host_p[1] = BIT_2;
4219 nv->reset_delay = 5;
4220 nv->port_down_retry_count = 8;
ad950360 4221 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 4222 nv->link_down_timeout = 60;
4223
4224 rval = 1;
1da177e4
LT		 4225 }
4226
4227#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
4228 /*
4229 * The SN2 does not provide BIOS emulation which means you can't change
4230 * potentially bogus BIOS settings. Force the use of default settings
4231 * for link rate and frame size. Hope that the rest of the settings
4232 * are valid.
4233 */
4234 if (ia64_platform_is("sn2")) {
98aee70d 4235 nv->frame_payload_size = 2048;
1da177e4
LT		 4236 if (IS_QLA23XX(ha))
4237 nv->special_options[1] = BIT_7;
4238 }
4239#endif
4240
4241 /* Reset Initialization control block */
0107109e 4242 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 4243
4244 /*
4245 * Setup driver NVRAM options.
4246 */
4247 nv->firmware_options[0] |= (BIT_6 | BIT_1);
4248 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
4249 nv->firmware_options[1] |= (BIT_5 | BIT_0);
4250 nv->firmware_options[1] &= ~BIT_4;
4251
4252 if (IS_QLA23XX(ha)) {
4253 nv->firmware_options[0] |= BIT_2;
4254 nv->firmware_options[0] &= ~BIT_3;
2d70c103 4255 nv->special_options[0] &= ~BIT_6;
0107109e 4256 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 4257
4258 if (IS_QLA2300(ha)) {
4259 if (ha->fb_rev == FPM_2310) {
4260 strcpy(ha->model_number, "QLA2310");
4261 } else {
4262 strcpy(ha->model_number, "QLA2300");
4263 }
4264 } else {
e315cd28 4265 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 4266 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 4267 }
4268 } else if (IS_QLA2200(ha)) {
4269 nv->firmware_options[0] |= BIT_2;
4270 /*
4271 * 'Point-to-point preferred, else loop' is not a safe
4272 * connection mode setting.
4273 */
4274 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
4275 (BIT_5 | BIT_4)) {
4276 /* Force 'loop preferred, else point-to-point'. */
4277 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
4278 nv->add_firmware_options[0] |= BIT_5;
4279 }
4280 strcpy(ha->model_number, "QLA22xx");
4281 } else /*if (IS_QLA2100(ha))*/ {
4282 strcpy(ha->model_number, "QLA2100");
4283 }
4284
4285 /*
4286 * Copy over NVRAM RISC parameter block to initialization control block.
4287 */
4288 dptr1 = (uint8_t *)icb;
4289 dptr2 = (uint8_t *)&nv->parameter_block_version;
4290 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
4291 while (cnt--)
4292 *dptr1++ = *dptr2++;
4293
4294 /* Copy 2nd half. */
4295 dptr1 = (uint8_t *)icb->add_firmware_options;
4296 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4297 while (cnt--)
4298 *dptr1++ = *dptr2++;
4299
5341e868
AV		 4300 /* Use alternate WWN? */
4301 if (nv->host_p[1] & BIT_7) {
4302 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4303 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4304 }
4305
1da177e4
LT		 4306 /* Prepare nodename */
4307 if ((icb->firmware_options[1] & BIT_6) == 0) {
4308 /*
4309 * Firmware will apply the following mask if the nodename was
4310 * not provided.
4311 */
4312 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4313 icb->node_name[0] &= 0xF0;
4314 }
4315
4316 /*
4317 * Set host adapter parameters.
4318 */
3ce8866c
SK		 4319
4320 /*
4321 * BIT_7 in the host-parameters section allows for modification to
4322 * internal driver logging.
4323 */
0181944f 4324 if (nv->host_p[0] & BIT_7)
cfb0919c 4325 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 4326 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4327 /* Always load RISC code on non ISP2[12]00 chips. */
4328 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4329 ha->flags.disable_risc_code_load = 0;
4330 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4331 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4332 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 4333 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 4334 ha->flags.disable_serdes = 0;
1da177e4
LT		 4335
4336 ha->operating_mode =
4337 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4338
4339 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4340 sizeof(ha->fw_seriallink_options));
4341
4342 /* save HBA serial number */
4343 ha->serial0 = icb->port_name[5];
4344 ha->serial1 = icb->port_name[6];
4345 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4346 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4347 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 4348
ad950360 4349 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 4350
4351 ha->retry_count = nv->retry_count;
4352
4353 /* Set minimum login_timeout to 4 seconds. */
5b91490e 4354 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 4355 nv->login_timeout = ql2xlogintimeout;
4356 if (nv->login_timeout < 4)
4357 nv->login_timeout = 4;
4358 ha->login_timeout = nv->login_timeout;
1da177e4 4359
00a537b8
AV		 4360 /* Set minimum RATOV to 100 tenths of a second. */
4361 ha->r_a_tov = 100;
1da177e4 4362
1da177e4
LT		 4363 ha->loop_reset_delay = nv->reset_delay;
4364
1da177e4
LT		 4365 /* Link Down Timeout = 0:
4366 *
4367 * When Port Down timer expires we will start returning
4368 * I/O's to OS with "DID_NO_CONNECT".
4369 *
4370 * Link Down Timeout != 0:
4371 *
4372 * The driver waits for the link to come up after link down
4373 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 4374 */
1da177e4
LT		 4375 if (nv->link_down_timeout == 0) {
4376 ha->loop_down_abort_time =
354d6b21 4377 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 4378 } else {
4379 ha->link_down_timeout = nv->link_down_timeout;
4380 ha->loop_down_abort_time =
4381 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 4382 }
1da177e4 4383
1da177e4
LT		 4384 /*
4385 * Need enough time to try and get the port back.
4386 */
4387 ha->port_down_retry_count = nv->port_down_retry_count;
4388 if (qlport_down_retry)
4389 ha->port_down_retry_count = qlport_down_retry;
4390 /* Set login_retry_count */
4391 ha->login_retry_count = nv->retry_count;
4392 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4393 ha->port_down_retry_count > 3)
4394 ha->login_retry_count = ha->port_down_retry_count;
4395 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4396 ha->login_retry_count = ha->port_down_retry_count;
4397 if (ql2xloginretrycount)
4398 ha->login_retry_count = ql2xloginretrycount;
4399
ad950360 4400 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 4401 icb->command_resource_count = 0;
4402 icb->immediate_notify_resource_count = 0;
ad950360 4403 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 4404
4405 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4406 /* Enable RIO */
4407 icb->firmware_options[0] &= ~BIT_3;
4408 icb->add_firmware_options[0] &=
4409 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4410 icb->add_firmware_options[0] |= BIT_2;
4411 icb->response_accumulation_timer = 3;
4412 icb->interrupt_delay_timer = 5;
4413
e315cd28 4414 vha->flags.process_response_queue = 1;
1da177e4 4415 } else {
4fdfefe5 4416 /* Enable ZIO. */
e315cd28 4417 if (!vha->flags.init_done) {
4fdfefe5
AV		 4418 ha->zio_mode = icb->add_firmware_options[0] &
4419 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4420 ha->zio_timer = icb->interrupt_delay_timer ?
4421 icb->interrupt_delay_timer: 2;
4422 }
1da177e4
LT		 4423 icb->add_firmware_options[0] &=
4424 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 4425 vha->flags.process_response_queue = 0;
4fdfefe5 4426 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4427 ha->zio_mode = QLA_ZIO_MODE_6;
4428
7c3df132 4429 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 4430 "ZIO mode %d enabled; timer delay (%d us).\n",
4431 ha->zio_mode, ha->zio_timer * 100);
1da177e4 4432
4fdfefe5
AV		 4433 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4434 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 4435 vha->flags.process_response_queue = 1;
1da177e4
LT		 4436 }
4437 }
4438
4e08df3f 4439 if (rval) {
7c3df132
SK		 4440 ql_log(ql_log_warn, vha, 0x0069,
4441 "NVRAM configuration failed.\n");
4e08df3f
DM		 4442 }
4443 return (rval);
1da177e4
LT		 4444}
4445
19a7b4ae
JSEC		 4446static void
4447qla2x00_rport_del(void *data)
4448{
4449 fc_port_t *fcport = data;
d97994dc 4450 struct fc_rport *rport;
044d78e1 4451 unsigned long flags;
d97994dc 4452
044d78e1 4453 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 4454 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 4455 fcport->drport = NULL;
044d78e1 4456 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548 4457 if (rport) {
83548fe2
QT		 4458 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4459 "%s %8phN. rport %p roles %x\n",
4460 __func__, fcport->port_name, rport,
4461 rport->roles);
726b8548 4462
d97994dc 4463 fc_remote_port_delete(rport);
726b8548 4464 }
19a7b4ae
JSEC		 4465}
4466
1da177e4
LT		 4467/**
4468 * qla2x00_alloc_fcport() - Allocate a generic fcport.
4469 * @ha: HA context
4470 * @flags: allocation flags
4471 *
4472 * Returns a pointer to the allocated fcport, or NULL, if none available.
4473 */
9a069e19 4474fc_port_t *
e315cd28 4475qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 4476{
4477 fc_port_t *fcport;
4478
bbfbbbc1
MK		 4479 fcport = kzalloc(sizeof(fc_port_t), flags);
4480 if (!fcport)
4481 return NULL;
1da177e4
LT		 4482
4483 /* Setup fcport template structure. */
e315cd28 4484 fcport->vha = vha;
1da177e4
LT		 4485 fcport->port_type = FCT_UNKNOWN;
4486 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 4487 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 4488 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 4489
726b8548
QT		 4490 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
4491 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 4492 flags);
726b8548
QT		 4493 fcport->disc_state = DSC_DELETED;
4494 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4495 fcport->deleted = QLA_SESS_DELETED;
4496 fcport->login_retry = vha->hw->login_retry_count;
4497 fcport->login_retry = 5;
4498 fcport->logout_on_delete = 1;
4499
4500 if (!fcport->ct_desc.ct_sns) {
83548fe2 4501 ql_log(ql_log_warn, vha, 0xd049,
726b8548
QT		 4502 "Failed to allocate ct_sns request.\n");
4503 kfree(fcport);
4504 fcport = NULL;
4505 }
4506 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
4507 INIT_LIST_HEAD(&fcport->gnl_entry);
4508 INIT_LIST_HEAD(&fcport->list);
4509
bbfbbbc1 4510 return fcport;
1da177e4
LT		 4511}
4512
726b8548
QT		 4513void
4514qla2x00_free_fcport(fc_port_t *fcport)
4515{
4516 if (fcport->ct_desc.ct_sns) {
4517 dma_free_coherent(&fcport->vha->hw->pdev->dev,
4518 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
4519 fcport->ct_desc.ct_sns_dma);
4520
4521 fcport->ct_desc.ct_sns = NULL;
4522 }
4523 kfree(fcport);
4524}
4525
1da177e4
LT		 4526/*
4527 * qla2x00_configure_loop
4528 * Updates Fibre Channel Device Database with what is actually on loop.
4529 *
4530 * Input:
4531 * ha = adapter block pointer.
4532 *
4533 * Returns:
4534 * 0 = success.
4535 * 1 = error.
4536 * 2 = database was full and device was not configured.
4537 */
4538static int
e315cd28 4539qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4540{
4541 int rval;
4542 unsigned long flags, save_flags;
e315cd28 4543 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4544 rval = QLA_SUCCESS;
4545
4546 /* Get Initiator ID */
e315cd28
AC		 4547 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
4548 rval = qla2x00_configure_hba(vha);
1da177e4 4549 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4550 ql_dbg(ql_dbg_disc, vha, 0x2013,
4551 "Unable to configure HBA.\n");
1da177e4
LT		 4552 return (rval);
4553 }
4554 }
4555
e315cd28 4556 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 4557 ql_dbg(ql_dbg_disc, vha, 0x2014,
4558 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 4559
4560 /*
4561 * If we have both an RSCN and PORT UPDATE pending then handle them
4562 * both at the same time.
4563 */
e315cd28
AC		 4564 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4565 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 4566
3064ff39
MH		 4567 qla2x00_get_data_rate(vha);
4568
1da177e4
LT		 4569 /* Determine what we need to do */
4570 if (ha->current_topology == ISP_CFG_FL &&
4571 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4572
1da177e4
LT		 4573 set_bit(RSCN_UPDATE, &flags);
4574
4575 } else if (ha->current_topology == ISP_CFG_F &&
4576 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4577
1da177e4
LT		 4578 set_bit(RSCN_UPDATE, &flags);
4579 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4580
4581 } else if (ha->current_topology == ISP_CFG_N) {
4582 clear_bit(RSCN_UPDATE, &flags);
9cd883f0
QT		 4583 if (ha->flags.rida_fmt2) {
4584 /* With Rida Format 2, the login is already triggered.
4585 * We know who is on the other side of the wire.
4586 * No need to login to do login to find out or drop into
4587 * qla2x00_configure_local_loop().
4588 */
4589 clear_bit(LOCAL_LOOP_UPDATE, &flags);
4590 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4591 } else {
4592 if (qla_tgt_mode_enabled(vha)) {
4593 /* allow the other side to start the login */
4594 clear_bit(LOCAL_LOOP_UPDATE, &flags);
4595 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4596 }
4597 }
41dc529a
QT		 4598 } else if (ha->current_topology == ISP_CFG_NL) {
4599 clear_bit(RSCN_UPDATE, &flags);
4600 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4601 } else if (!vha->flags.online ||
1da177e4 4602 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 4603 set_bit(RSCN_UPDATE, &flags);
4604 set_bit(LOCAL_LOOP_UPDATE, &flags);
4605 }
4606
4607 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 4608 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
4609 ql_dbg(ql_dbg_disc, vha, 0x2015,
4610 "Loop resync needed, failing.\n");
1da177e4 4611 rval = QLA_FUNCTION_FAILED;
642ef983 4612 } else
e315cd28 4613 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 4614 }
4615
4616 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132 4617 if (LOOP_TRANSITION(vha)) {
83548fe2 4618 ql_dbg(ql_dbg_disc, vha, 0x2099,
7c3df132 4619 "Needs RSCN update and loop transition.\n");
1da177e4 4620 rval = QLA_FUNCTION_FAILED;
7c3df132 4621 }
e315cd28
AC		 4622 else
4623 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 4624 }
4625
4626 if (rval == QLA_SUCCESS) {
e315cd28
AC		 4627 if (atomic_read(&vha->loop_down_timer) ||
4628 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4629 rval = QLA_FUNCTION_FAILED;
4630 } else {
e315cd28 4631 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4632 ql_dbg(ql_dbg_disc, vha, 0x2069,
4633 "LOOP READY.\n");
ec7193e2 4634 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 4635
4636 /*
4637 * Process any ATIO queue entries that came in
4638 * while we weren't online.
4639 */
ead03855
QT		 4640 if (qla_tgt_mode_enabled(vha) ||
4641 qla_dual_mode_enabled(vha)) {
3bb67df5
DKU		 4642 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
4643 spin_lock_irqsave(&ha->tgt.atio_lock,
4644 flags);
4645 qlt_24xx_process_atio_queue(vha, 0);
4646 spin_unlock_irqrestore(
4647 &ha->tgt.atio_lock, flags);
4648 } else {
4649 spin_lock_irqsave(&ha->hardware_lock,
4650 flags);
4651 qlt_24xx_process_atio_queue(vha, 1);
4652 spin_unlock_irqrestore(
4653 &ha->hardware_lock, flags);
4654 }
4655 }
1da177e4
LT		 4656 }
4657 }
4658
4659 if (rval) {
7c3df132
SK		 4660 ql_dbg(ql_dbg_disc, vha, 0x206a,
4661 "%s *** FAILED ***.\n", __func__);
1da177e4 4662 } else {
7c3df132
SK		 4663 ql_dbg(ql_dbg_disc, vha, 0x206b,
4664 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4665 }
4666
cc3ef7bc 4667 /* Restore state if a resync event occurred during processing */
e315cd28 4668 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4669 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4670 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4671 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4672 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4673 }
1da177e4
LT		 4674 }
4675
4676 return (rval);
4677}
4678
edd05de1
DG		 4679/*
4680 * N2N Login
4681 * Updates Fibre Channel Device Database with local loop devices.
4682 *
4683 * Input:
4684 * ha = adapter block pointer.
4685 *
4686 * Returns:
4687 */
4688static int qla24xx_n2n_handle_login(struct scsi_qla_host *vha,
4689 fc_port_t *fcport)
4690{
4691 struct qla_hw_data *ha = vha->hw;
4692 int res = QLA_SUCCESS, rval;
4693 int greater_wwpn = 0;
4694 int logged_in = 0;
4695
4696 if (ha->current_topology != ISP_CFG_N)
4697 return res;
4698
4699 if (wwn_to_u64(vha->port_name) >
4700 wwn_to_u64(vha->n2n_port_name)) {
4701 ql_dbg(ql_dbg_disc, vha, 0x2002,
4702 "HBA WWPN is greater %llx > target %llx\n",
4703 wwn_to_u64(vha->port_name),
4704 wwn_to_u64(vha->n2n_port_name));
4705 greater_wwpn = 1;
4706 fcport->d_id.b24 = vha->n2n_id;
4707 }
4708
4709 fcport->loop_id = vha->loop_id;
4710 fcport->fc4f_nvme = 0;
4711 fcport->query = 1;
4712
4713 ql_dbg(ql_dbg_disc, vha, 0x4001,
4714 "Initiate N2N login handler: HBA port_id=%06x loopid=%d\n",
4715 fcport->d_id.b24, vha->loop_id);
4716
4717 /* Fill in member data. */
4718 if (!greater_wwpn) {
4719 rval = qla2x00_get_port_database(vha, fcport, 0);
4720 ql_dbg(ql_dbg_disc, vha, 0x1051,
4721 "Remote login-state (%x/%x) port_id=%06x loop_id=%x, rval=%d\n",
4722 fcport->current_login_state, fcport->last_login_state,
4723 fcport->d_id.b24, fcport->loop_id, rval);
4724
4725 if (((fcport->current_login_state & 0xf) == 0x4) ||
4726 ((fcport->current_login_state & 0xf) == 0x6))
4727 logged_in = 1;
4728 }
4729
4730 if (logged_in || greater_wwpn) {
4731 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
4732 qla_nvme_register_hba(vha);
4733
4734 /* Set connected N_Port d_id */
4735 if (vha->flags.nvme_enabled)
4736 fcport->fc4f_nvme = 1;
4737
4738 fcport->scan_state = QLA_FCPORT_FOUND;
4739 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4740 fcport->disc_state = DSC_GNL;
4741 fcport->n2n_flag = 1;
4742 fcport->flags = 3;
4743 vha->hw->flags.gpsc_supported = 0;
4744
4745 if (greater_wwpn) {
4746 ql_dbg(ql_dbg_disc, vha, 0x20e5,
4747 "%s %d PLOGI ELS %8phC\n",
4748 __func__, __LINE__, fcport->port_name);
4749
4750 res = qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
4751 fcport, fcport->d_id);
4752 }
4753
4754 if (res != QLA_SUCCESS) {
4755 ql_log(ql_log_info, vha, 0xd04d,
4756 "PLOGI Failed: portid=%06x - retrying\n",
4757 fcport->d_id.b24);
4758 res = QLA_SUCCESS;
4759 } else {
4760 /* State 0x6 means FCP PRLI complete */
4761 if ((fcport->current_login_state & 0xf) == 0x6) {
4762 ql_dbg(ql_dbg_disc, vha, 0x2118,
4763 "%s %d %8phC post GPDB work\n",
4764 __func__, __LINE__, fcport->port_name);
4765 fcport->chip_reset =
4766 vha->hw->base_qpair->chip_reset;
4767 qla24xx_post_gpdb_work(vha, fcport, 0);
4768 } else {
4769 ql_dbg(ql_dbg_disc, vha, 0x2118,
4770 "%s %d %8phC post NVMe PRLI\n",
4771 __func__, __LINE__, fcport->port_name);
4772 qla24xx_post_prli_work(vha, fcport);
4773 }
4774 }
4775 } else {
4776 /* Wait for next database change */
4777 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
4778 }
1da177e4 4779
edd05de1
DG		 4780 return res;
4781}
1da177e4
LT		 4782
4783/*
4784 * qla2x00_configure_local_loop
4785 * Updates Fibre Channel Device Database with local loop devices.
4786 *
4787 * Input:
4788 * ha = adapter block pointer.
4789 *
4790 * Returns:
4791 * 0 = success.
4792 */
4793static int
e315cd28 4794qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4795{
4796 int rval, rval2;
4797 int found_devs;
4798 int found;
4799 fc_port_t *fcport, *new_fcport;
4800
4801 uint16_t index;
4802 uint16_t entries;
4803 char *id_iter;
4804 uint16_t loop_id;
4805 uint8_t domain, area, al_pa;
e315cd28 4806 struct qla_hw_data *ha = vha->hw;
41dc529a 4807 unsigned long flags;
1da177e4
LT		 4808
4809 found_devs = 0;
4810 new_fcport = NULL;
642ef983 4811 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4812
1da177e4 4813 /* Get list of logged in devices. */
642ef983 4814 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4815 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4816 &entries);
4817 if (rval != QLA_SUCCESS)
4818 goto cleanup_allocation;
4819
83548fe2 4820 ql_dbg(ql_dbg_disc, vha, 0x2011,
7c3df132
SK		 4821 "Entries in ID list (%d).\n", entries);
4822 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4823 (uint8_t *)ha->gid_list,
4824 entries * sizeof(struct gid_list_info));
1da177e4 4825
9cd883f0
QT		 4826 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4827 fcport->scan_state = QLA_FCPORT_SCAN;
4828 }
4829
1da177e4 4830 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4831 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4832 if (new_fcport == NULL) {
83548fe2 4833 ql_log(ql_log_warn, vha, 0x2012,
7c3df132 4834 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4835 rval = QLA_MEMORY_ALLOC_FAILED;
4836 goto cleanup_allocation;
4837 }
4838 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4839
edd05de1
DG		 4840 /* Inititae N2N login. */
4841 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) {
4842 rval = qla24xx_n2n_handle_login(vha, new_fcport);
4843 if (rval != QLA_SUCCESS)
4844 goto cleanup_allocation;
4845 return QLA_SUCCESS;
4846 }
4847
1da177e4
LT		 4848 /* Add devices to port list. */
4849 id_iter = (char *)ha->gid_list;
4850 for (index = 0; index < entries; index++) {
4851 domain = ((struct gid_list_info *)id_iter)->domain;
4852 area = ((struct gid_list_info *)id_iter)->area;
4853 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4854 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4855 loop_id = (uint16_t)
4856 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4857 else
1da177e4
LT		 4858 loop_id = le16_to_cpu(
4859 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4860 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4861
4862 /* Bypass reserved domain fields. */
4863 if ((domain & 0xf0) == 0xf0)
4864 continue;
4865
4866 /* Bypass if not same domain and area of adapter. */
f7d289f6 4867 if (area && domain &&
e315cd28 4868 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4869 continue;
4870
4871 /* Bypass invalid local loop ID. */
4872 if (loop_id > LAST_LOCAL_LOOP_ID)
4873 continue;
4874
41dc529a 4875 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 4876
1da177e4
LT		 4877 /* Fill in member data. */
4878 new_fcport->d_id.b.domain = domain;
4879 new_fcport->d_id.b.area = area;
4880 new_fcport->d_id.b.al_pa = al_pa;
4881 new_fcport->loop_id = loop_id;
9cd883f0 4882 new_fcport->scan_state = QLA_FCPORT_FOUND;
41dc529a 4883
e315cd28 4884 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 4885 if (rval2 != QLA_SUCCESS) {
83548fe2 4886 ql_dbg(ql_dbg_disc, vha, 0x2097,
7c3df132
SK		 4887 "Failed to retrieve fcport information "
4888 "-- get_port_database=%x, loop_id=0x%04x.\n",
4889 rval2, new_fcport->loop_id);
edd05de1
DG		 4890 /* Skip retry if N2N */
4891 if (ha->current_topology != ISP_CFG_N) {
4892 ql_dbg(ql_dbg_disc, vha, 0x2105,
4893 "Scheduling resync.\n");
4894 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4895 continue;
4896 }
1da177e4
LT		 4897 }
4898
41dc529a 4899 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4900 /* Check for matching device in port list. */
4901 found = 0;
4902 fcport = NULL;
e315cd28 4903 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4904 if (memcmp(new_fcport->port_name, fcport->port_name,
4905 WWN_SIZE))
4906 continue;
4907
ddb9b126 4908 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 4909 fcport->loop_id = new_fcport->loop_id;
4910 fcport->port_type = new_fcport->port_type;
4911 fcport->d_id.b24 = new_fcport->d_id.b24;
4912 memcpy(fcport->node_name, new_fcport->node_name,
4913 WWN_SIZE);
9cd883f0 4914 fcport->scan_state = QLA_FCPORT_FOUND;
1da177e4
LT		 4915 found++;
4916 break;
4917 }
4918
4919 if (!found) {
4920 /* New device, add to fcports list. */
e315cd28 4921 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 4922
4923 /* Allocate a new replacement fcport. */
4924 fcport = new_fcport;
41dc529a
QT		 4925
4926 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4927
e315cd28 4928 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 4929
1da177e4 4930 if (new_fcport == NULL) {
83548fe2 4931 ql_log(ql_log_warn, vha, 0xd031,
7c3df132 4932 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4933 rval = QLA_MEMORY_ALLOC_FAILED;
4934 goto cleanup_allocation;
4935 }
41dc529a 4936 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4937 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4938 }
4939
41dc529a
QT		 4940 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4941
d8b45213 4942 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 4943 fcport->fp_speed = ha->link_data_rate;
d8b45213 4944
1da177e4
LT		 4945 found_devs++;
4946 }
4947
9cd883f0
QT		 4948 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4949 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4950 break;
4951
4952 if (fcport->scan_state == QLA_FCPORT_SCAN) {
4953 if ((qla_dual_mode_enabled(vha) ||
4954 qla_ini_mode_enabled(vha)) &&
4955 atomic_read(&fcport->state) == FCS_ONLINE) {
4956 qla2x00_mark_device_lost(vha, fcport,
4957 ql2xplogiabsentdevice, 0);
4958 if (fcport->loop_id != FC_NO_LOOP_ID &&
4959 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
4960 fcport->port_type != FCT_INITIATOR &&
4961 fcport->port_type != FCT_BROADCAST) {
4962 ql_dbg(ql_dbg_disc, vha, 0x20f0,
4963 "%s %d %8phC post del sess\n",
4964 __func__, __LINE__,
4965 fcport->port_name);
4966
4967 qlt_schedule_sess_for_deletion_lock
4968 (fcport);
4969 continue;
4970 }
4971 }
4972 }
4973
4974 if (fcport->scan_state == QLA_FCPORT_FOUND)
4975 qla24xx_fcport_handle_login(vha, fcport);
4976 }
4977
1da177e4 4978cleanup_allocation:
c9475cb0 4979 kfree(new_fcport);
1da177e4
LT		 4980
4981 if (rval != QLA_SUCCESS) {
83548fe2 4982 ql_dbg(ql_dbg_disc, vha, 0x2098,
7c3df132 4983 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 4984 }
4985
1da177e4
LT		 4986 return (rval);
4987}
4988
d8b45213 4989static void
e315cd28 4990qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 4991{
d8b45213 4992 int rval;
93f2bd67 4993 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4994 struct qla_hw_data *ha = vha->hw;
d8b45213 4995
c76f2c01 4996 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 4997 return;
4998
c9afb9a2
GM		 4999 if (atomic_read(&fcport->state) != FCS_ONLINE)
5000 return;
5001
39bd9622
AV		 5002 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
5003 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 5004 return;
5005
e315cd28 5006 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 5007 mb);
d8b45213 5008 if (rval != QLA_SUCCESS) {
7c3df132 5009 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 5010 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
5011 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 5012 } else {
7c3df132 5013 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 5014 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 5015 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 5016 fcport->port_name);
d8b45213
AV		 5017 }
5018}
5019
726b8548 5020/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 5021static void
e315cd28 5022qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 5023{
5024 struct fc_rport_identifiers rport_ids;
bdf79621 5025 struct fc_rport *rport;
044d78e1 5026 unsigned long flags;
8482e118 5027
f8b02a85
AV		 5028 rport_ids.node_name = wwn_to_u64(fcport->node_name);
5029 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 5030 rport_ids.port_id = fcport->d_id.b.domain << 16 |
5031 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 5032 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 5033 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 5034 if (!rport) {
7c3df132
SK		 5035 ql_log(ql_log_warn, vha, 0x2006,
5036 "Unable to allocate fc remote port.\n");
77d74143
AV		 5037 return;
5038 }
2d70c103 5039
044d78e1 5040 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 5041 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 5042 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 5043
ad3e0eda 5044 rport->supported_classes = fcport->supported_classes;
77d74143 5045
8482e118 5046 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
5047 if (fcport->port_type == FCT_INITIATOR)
5048 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
5049 if (fcport->port_type == FCT_TARGET)
5050 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548 5051
83548fe2
QT		 5052 ql_dbg(ql_dbg_disc, vha, 0x20ee,
5053 "%s %8phN. rport %p is %s mode\n",
5054 __func__, fcport->port_name, rport,
5055 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
726b8548 5056
77d74143 5057 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 5058}
5059
23be331d
AB		 5060/*
5061 * qla2x00_update_fcport
5062 * Updates device on list.
5063 *
5064 * Input:
5065 * ha = adapter block pointer.
5066 * fcport = port structure pointer.
5067 *
5068 * Return:
5069 * 0 - Success
5070 * BIT_0 - error
5071 *
5072 * Context:
5073 * Kernel context.
5074 */
5075void
e315cd28 5076qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 5077{
e315cd28 5078 fcport->vha = vha;
8ae6d9c7 5079
726b8548
QT		 5080 if (IS_SW_RESV_ADDR(fcport->d_id))
5081 return;
5082
83548fe2 5083 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
726b8548
QT		 5084 __func__, fcport->port_name);
5085
8ae6d9c7
GM		 5086 if (IS_QLAFX00(vha->hw)) {
5087 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 5088 goto reg_port;
8ae6d9c7 5089 }
23be331d 5090 fcport->login_retry = 0;
5ff1d584 5091 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
726b8548
QT		 5092 fcport->disc_state = DSC_LOGIN_COMPLETE;
5093 fcport->deleted = 0;
5094 fcport->logout_on_delete = 1;
23be331d 5095
e84067d7
DG		 5096 if (fcport->fc4f_nvme) {
5097 qla_nvme_register_remote(vha, fcport);
5098 return;
5099 }
5100
1f93da52 5101 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 5102 qla2x00_iidma_fcport(vha, fcport);
21090cbe 5103 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 5104
5105reg_port:
726b8548
QT		 5106 switch (vha->host->active_mode) {
5107 case MODE_INITIATOR:
d20ed91b 5108 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5109 break;
5110 case MODE_TARGET:
5111 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5112 !vha->vha_tgt.qla_tgt->tgt_stopped)
5113 qlt_fc_port_added(vha, fcport);
5114 break;
5115 case MODE_DUAL:
d20ed91b 5116 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5117 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5118 !vha->vha_tgt.qla_tgt->tgt_stopped)
5119 qlt_fc_port_added(vha, fcport);
5120 break;
5121 default:
5122 break;
d20ed91b 5123 }
23be331d
AB		 5124}
5125
1da177e4
LT		 5126/*
5127 * qla2x00_configure_fabric
5128 * Setup SNS devices with loop ID's.
5129 *
5130 * Input:
5131 * ha = adapter block pointer.
5132 *
5133 * Returns:
5134 * 0 = success.
5135 * BIT_0 = error
5136 */
5137static int
e315cd28 5138qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 5139{
b3b02e6e 5140 int rval;
726b8548 5141 fc_port_t *fcport;
1da177e4 5142 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 5143 uint16_t loop_id;
1da177e4 5144 LIST_HEAD(new_fcports);
e315cd28 5145 struct qla_hw_data *ha = vha->hw;
df673274 5146 int discovery_gen;
1da177e4
LT		 5147
5148 /* If FL port exists, then SNS is present */
e428924c 5149 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 5150 loop_id = NPH_F_PORT;
5151 else
5152 loop_id = SNS_FL_PORT;
e315cd28 5153 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 5154 if (rval != QLA_SUCCESS) {
83548fe2 5155 ql_dbg(ql_dbg_disc, vha, 0x20a0,
7c3df132 5156 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 5157
e315cd28 5158 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 5159 return (QLA_SUCCESS);
5160 }
e315cd28 5161 vha->device_flags |= SWITCH_FOUND;
1da177e4 5162
41dc529a
QT		 5163
5164 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
5165 rval = qla2x00_send_change_request(vha, 0x3, 0);
5166 if (rval != QLA_SUCCESS)
5167 ql_log(ql_log_warn, vha, 0x121,
5168 "Failed to enable receiving of RSCN requests: 0x%x.\n",
5169 rval);
5170 }
5171
5172
1da177e4 5173 do {
726b8548
QT		 5174 qla2x00_mgmt_svr_login(vha);
5175
cca5335c
AV		 5176 /* FDMI support. */
5177 if (ql2xfdmienable &&
e315cd28
AC		 5178 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
5179 qla2x00_fdmi_register(vha);
cca5335c 5180
1da177e4 5181 /* Ensure we are logged into the SNS. */
a14c7711 5182 loop_id = NPH_SNS_LID(ha);
0b91d116
CD		 5183 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
5184 0xfc, mb, BIT_1|BIT_0);
a14c7711
JC		 5185 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5186 ql_dbg(ql_dbg_disc, vha, 0x20a1,
5187 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
5188 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
0b91d116 5189 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 5190 return rval;
0b91d116 5191 }
e315cd28
AC		 5192 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
5193 if (qla2x00_rft_id(vha)) {
1da177e4 5194 /* EMPTY */
83548fe2 5195 ql_dbg(ql_dbg_disc, vha, 0x20a2,
7c3df132 5196 "Register FC-4 TYPE failed.\n");
b98ae0d7
QT		 5197 if (test_bit(LOOP_RESYNC_NEEDED,
5198 &vha->dpc_flags))
5199 break;
1da177e4 5200 }
d3bae931 5201 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
1da177e4 5202 /* EMPTY */
83548fe2 5203 ql_dbg(ql_dbg_disc, vha, 0x209a,
7c3df132 5204 "Register FC-4 Features failed.\n");
b98ae0d7
QT		 5205 if (test_bit(LOOP_RESYNC_NEEDED,
5206 &vha->dpc_flags))
5207 break;
1da177e4 5208 }
d3bae931
DG		 5209 if (vha->flags.nvme_enabled) {
5210 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
5211 ql_dbg(ql_dbg_disc, vha, 0x2049,
5212 "Register NVME FC Type Features failed.\n");
5213 }
5214 }
e315cd28 5215 if (qla2x00_rnn_id(vha)) {
1da177e4 5216 /* EMPTY */
83548fe2 5217 ql_dbg(ql_dbg_disc, vha, 0x2104,
7c3df132 5218 "Register Node Name failed.\n");
b98ae0d7
QT		 5219 if (test_bit(LOOP_RESYNC_NEEDED,
5220 &vha->dpc_flags))
5221 break;
e315cd28 5222 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 5223 /* EMPTY */
83548fe2 5224 ql_dbg(ql_dbg_disc, vha, 0x209b,
0bf0efa1 5225 "Register Symbolic Node Name failed.\n");
b98ae0d7
QT		 5226 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5227 break;
1da177e4
LT		 5228 }
5229 }
5230
827210ba 5231
df673274
AP		 5232 /* Mark the time right before querying FW for connected ports.
5233 * This process is long, asynchronous and by the time it's done,
5234 * collected information might not be accurate anymore. E.g.
5235 * disconnected port might have re-connected and a brand new
5236 * session has been created. In this case session's generation
5237 * will be newer than discovery_gen. */
5238 qlt_do_generation_tick(vha, &discovery_gen);
5239
a4239945
QT		 5240 if (USE_ASYNC_SCAN(ha)) {
5241 rval = QLA_SUCCESS;
5242 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI);
5243 if (rval)
5244 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5245 } else {
f352eeb7
QT		 5246 list_for_each_entry(fcport, &vha->vp_fcports, list)
5247 fcport->scan_state = QLA_FCPORT_SCAN;
5248
a4239945
QT		 5249 rval = qla2x00_find_all_fabric_devs(vha);
5250 }
1da177e4
LT		 5251 if (rval != QLA_SUCCESS)
5252 break;
1da177e4
LT		 5253 } while (0);
5254
e84067d7
DG		 5255 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
5256 qla_nvme_register_hba(vha);
5257
726b8548 5258 if (rval)
7c3df132
SK		 5259 ql_dbg(ql_dbg_disc, vha, 0x2068,
5260 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 5261
5262 return (rval);
5263}
5264
1da177e4
LT		 5265/*
5266 * qla2x00_find_all_fabric_devs
5267 *
5268 * Input:
5269 * ha = adapter block pointer.
5270 * dev = database device entry pointer.
5271 *
5272 * Returns:
5273 * 0 = success.
5274 *
5275 * Context:
5276 * Kernel context.
5277 */
5278static int
726b8548 5279qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 5280{
5281 int rval;
5282 uint16_t loop_id;
726b8548 5283 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 5284 int found;
5285
5286 sw_info_t *swl;
5287 int swl_idx;
5288 int first_dev, last_dev;
1516ef44 5289 port_id_t wrap = {}, nxt_d_id;
e315cd28 5290 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 5291 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 5292 unsigned long flags;
1da177e4
LT		 5293
5294 rval = QLA_SUCCESS;
5295
5296 /* Try GID_PT to get device list, else GAN. */
7a67735b 5297 if (!ha->swl)
642ef983 5298 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 5299 GFP_KERNEL);
5300 swl = ha->swl;
bbfbbbc1 5301 if (!swl) {
1da177e4 5302 /*EMPTY*/
83548fe2 5303 ql_dbg(ql_dbg_disc, vha, 0x209c,
7c3df132 5304 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 5305 } else {
642ef983 5306 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 5307 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 5308 swl = NULL;
b98ae0d7
QT		 5309 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5310 return rval;
e315cd28 5311 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5312 swl = NULL;
b98ae0d7
QT		 5313 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5314 return rval;
e315cd28 5315 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5316 swl = NULL;
b98ae0d7
QT		 5317 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5318 return rval;
726b8548
QT		 5319 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
5320 swl = NULL;
b98ae0d7
QT		 5321 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5322 return rval;
1da177e4 5323 }
e8c72ba5
CD		 5324
5325 /* If other queries succeeded probe for FC-4 type */
b98ae0d7 5326 if (swl) {
e8c72ba5 5327 qla2x00_gff_id(vha, swl);
b98ae0d7
QT		 5328 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5329 return rval;
5330 }
1da177e4
LT		 5331 }
5332 swl_idx = 0;
5333
5334 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 5335 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5336 if (new_fcport == NULL) {
83548fe2 5337 ql_log(ql_log_warn, vha, 0x209d,
7c3df132 5338 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5339 return (QLA_MEMORY_ALLOC_FAILED);
5340 }
5341 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 5342 /* Set start port ID scan at adapter ID. */
5343 first_dev = 1;
5344 last_dev = 0;
5345
5346 /* Starting free loop ID. */
e315cd28
AC		 5347 loop_id = ha->min_external_loopid;
5348 for (; loop_id <= ha->max_loop_id; loop_id++) {
5349 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 5350 continue;
5351
3a6478df
GM		 5352 if (ha->current_topology == ISP_CFG_FL &&
5353 (atomic_read(&vha->loop_down_timer) ||
5354 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 5355 atomic_set(&vha->loop_down_timer, 0);
5356 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5357 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 5358 break;
bb2d52b2 5359 }
1da177e4
LT		 5360
5361 if (swl != NULL) {
5362 if (last_dev) {
5363 wrap.b24 = new_fcport->d_id.b24;
5364 } else {
5365 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
5366 memcpy(new_fcport->node_name,
5367 swl[swl_idx].node_name, WWN_SIZE);
5368 memcpy(new_fcport->port_name,
5369 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 5370 memcpy(new_fcport->fabric_port_name,
5371 swl[swl_idx].fabric_port_name, WWN_SIZE);
5372 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 5373 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4 5374
a5d42f4c 5375 new_fcport->nvme_flag = 0;
1a28faa0 5376 new_fcport->fc4f_nvme = 0;
a5d42f4c
DG		 5377 if (vha->flags.nvme_enabled &&
5378 swl[swl_idx].fc4f_nvme) {
5379 new_fcport->fc4f_nvme =
5380 swl[swl_idx].fc4f_nvme;
5381 ql_log(ql_log_info, vha, 0x2131,
5382 "FOUND: NVME port %8phC as FC Type 28h\n",
5383 new_fcport->port_name);
5384 }
5385
1da177e4
LT		 5386 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
5387 last_dev = 1;
5388 }
5389 swl_idx++;
5390 }
5391 } else {
5392 /* Send GA_NXT to the switch */
e315cd28 5393 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 5394 if (rval != QLA_SUCCESS) {
83548fe2 5395 ql_log(ql_log_warn, vha, 0x209e,
7c3df132
SK		 5396 "SNS scan failed -- assuming "
5397 "zero-entry result.\n");
1da177e4
LT		 5398 rval = QLA_SUCCESS;
5399 break;
5400 }
5401 }
5402
5403 /* If wrap on switch device list, exit. */
5404 if (first_dev) {
5405 wrap.b24 = new_fcport->d_id.b24;
5406 first_dev = 0;
5407 } else if (new_fcport->d_id.b24 == wrap.b24) {
83548fe2 5408 ql_dbg(ql_dbg_disc, vha, 0x209f,
7c3df132
SK		 5409 "Device wrap (%02x%02x%02x).\n",
5410 new_fcport->d_id.b.domain,
5411 new_fcport->d_id.b.area,
5412 new_fcport->d_id.b.al_pa);
1da177e4
LT		 5413 break;
5414 }
5415
2c3dfe3f 5416 /* Bypass if same physical adapter. */
e315cd28 5417 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 5418 continue;
5419
2c3dfe3f 5420 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 5421 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
5422 continue;
2c3dfe3f 5423
f7d289f6
AV		 5424 /* Bypass if same domain and area of adapter. */
5425 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 5426 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 5427 ISP_CFG_FL)
5428 continue;
5429
1da177e4
LT		 5430 /* Bypass reserved domain fields. */
5431 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
5432 continue;
5433
e8c72ba5 5434 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 5435 if (ql2xgffidenable &&
5436 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
5437 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 5438 continue;
5439
726b8548
QT		 5440 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5441
1da177e4
LT		 5442 /* Locate matching device in database. */
5443 found = 0;
e315cd28 5444 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5445 if (memcmp(new_fcport->port_name, fcport->port_name,
5446 WWN_SIZE))
5447 continue;
5448
827210ba 5449 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 5450
1da177e4
LT		 5451 found++;
5452
d8b45213
AV		 5453 /* Update port state. */
5454 memcpy(fcport->fabric_port_name,
5455 new_fcport->fabric_port_name, WWN_SIZE);
5456 fcport->fp_speed = new_fcport->fp_speed;
5457
1da177e4 5458 /*
b2032fd5
RD		 5459 * If address the same and state FCS_ONLINE
5460 * (or in target mode), nothing changed.
1da177e4
LT		 5461 */
5462 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 5463 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 5464 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 5465 break;
5466 }
5467
5468 /*
5469 * If device was not a fabric device before.
5470 */
5471 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
5472 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 5473 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 5474 fcport->flags |= (FCF_FABRIC_DEVICE |
5475 FCF_LOGIN_NEEDED);
1da177e4
LT		 5476 break;
5477 }
5478
5479 /*
5480 * Port ID changed or device was marked to be updated;
5481 * Log it out if still logged in and mark it for
5482 * relogin later.
5483 */
726b8548 5484 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 5485 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
5486 "port changed FC ID, %8phC"
5487 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
5488 fcport->port_name,
5489 fcport->d_id.b.domain,
5490 fcport->d_id.b.area,
5491 fcport->d_id.b.al_pa,
5492 fcport->loop_id,
5493 new_fcport->d_id.b.domain,
5494 new_fcport->d_id.b.area,
5495 new_fcport->d_id.b.al_pa);
5496 fcport->d_id.b24 = new_fcport->d_id.b24;
5497 break;
5498 }
5499
1da177e4
LT		 5500 fcport->d_id.b24 = new_fcport->d_id.b24;
5501 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 5502 break;
5503 }
5504
726b8548
QT		 5505 if (found) {
5506 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 5507 continue;
726b8548 5508 }
1da177e4 5509 /* If device was not in our fcports list, then add it. */
b2032fd5 5510 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 5511 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5512
5513 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5514
1da177e4
LT		 5515
5516 /* Allocate a new replacement fcport. */
5517 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 5518 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5519 if (new_fcport == NULL) {
83548fe2 5520 ql_log(ql_log_warn, vha, 0xd032,
7c3df132 5521 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5522 return (QLA_MEMORY_ALLOC_FAILED);
5523 }
5524 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5525 new_fcport->d_id.b24 = nxt_d_id.b24;
5526 }
5527
726b8548
QT		 5528 qla2x00_free_fcport(new_fcport);
5529
5530 /*
5531 * Logout all previous fabric dev marked lost, except FCP2 devices.
5532 */
5533 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5534 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5535 break;
5536
5537 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
5538 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
5539 continue;
5540
5541 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5542 if ((qla_dual_mode_enabled(vha) ||
5543 qla_ini_mode_enabled(vha)) &&
5544 atomic_read(&fcport->state) == FCS_ONLINE) {
5545 qla2x00_mark_device_lost(vha, fcport,
5546 ql2xplogiabsentdevice, 0);
5547 if (fcport->loop_id != FC_NO_LOOP_ID &&
5548 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5549 fcport->port_type != FCT_INITIATOR &&
5550 fcport->port_type != FCT_BROADCAST) {
83548fe2 5551 ql_dbg(ql_dbg_disc, vha, 0x20f0,
726b8548
QT		 5552 "%s %d %8phC post del sess\n",
5553 __func__, __LINE__,
5554 fcport->port_name);
5555
5556 qlt_schedule_sess_for_deletion_lock
5557 (fcport);
5558 continue;
5559 }
5560 }
5561 }
1da177e4 5562
726b8548
QT		 5563 if (fcport->scan_state == QLA_FCPORT_FOUND)
5564 qla24xx_fcport_handle_login(vha, fcport);
5565 }
1da177e4
LT		 5566 return (rval);
5567}
5568
5569/*
5570 * qla2x00_find_new_loop_id
5571 * Scan through our port list and find a new usable loop ID.
5572 *
5573 * Input:
5574 * ha: adapter state pointer.
5575 * dev: port structure pointer.
5576 *
5577 * Returns:
5578 * qla2x00 local function return status code.
5579 *
5580 * Context:
5581 * Kernel context.
5582 */
03bcfb57 5583int
e315cd28 5584qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 5585{
5586 int rval;
e315cd28 5587 struct qla_hw_data *ha = vha->hw;
feafb7b1 5588 unsigned long flags = 0;
1da177e4
LT		 5589
5590 rval = QLA_SUCCESS;
5591
5f16b331 5592 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 5593
5f16b331
CD		 5594 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
5595 LOOPID_MAP_SIZE);
5596 if (dev->loop_id >= LOOPID_MAP_SIZE ||
5597 qla2x00_is_reserved_id(vha, dev->loop_id)) {
5598 dev->loop_id = FC_NO_LOOP_ID;
5599 rval = QLA_FUNCTION_FAILED;
5600 } else
5601 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 5602
5f16b331 5603 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 5604
5f16b331
CD		 5605 if (rval == QLA_SUCCESS)
5606 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
5607 "Assigning new loopid=%x, portid=%x.\n",
5608 dev->loop_id, dev->d_id.b24);
5609 else
5610 ql_log(ql_log_warn, dev->vha, 0x2087,
5611 "No loop_id's available, portid=%x.\n",
5612 dev->d_id.b24);
1da177e4
LT		 5613
5614 return (rval);
5615}
5616
1da177e4
LT		 5617
5618/*
5619 * qla2x00_fabric_login
5620 * Issue fabric login command.
5621 *
5622 * Input:
5623 * ha = adapter block pointer.
5624 * device = pointer to FC device type structure.
5625 *
5626 * Returns:
5627 * 0 - Login successfully
5628 * 1 - Login failed
5629 * 2 - Initiator device
5630 * 3 - Fatal error
5631 */
5632int
e315cd28 5633qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 5634 uint16_t *next_loopid)
5635{
5636 int rval;
5637 int retry;
5638 uint16_t tmp_loopid;
5639 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5640 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 5641
5642 retry = 0;
5643 tmp_loopid = 0;
5644
5645 for (;;) {
7c3df132
SK		 5646 ql_dbg(ql_dbg_disc, vha, 0x2000,
5647 "Trying Fabric Login w/loop id 0x%04x for port "
5648 "%02x%02x%02x.\n",
5649 fcport->loop_id, fcport->d_id.b.domain,
5650 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5651
5652 /* Login fcport on switch. */
0b91d116 5653 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 5654 fcport->d_id.b.domain, fcport->d_id.b.area,
5655 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 5656 if (rval != QLA_SUCCESS) {
5657 return rval;
5658 }
1da177e4
LT		 5659 if (mb[0] == MBS_PORT_ID_USED) {
5660 /*
5661 * Device has another loop ID. The firmware team
0107109e
AV		 5662 * recommends the driver perform an implicit login with
5663 * the specified ID again. The ID we just used is save
5664 * here so we return with an ID that can be tried by
5665 * the next login.
1da177e4
LT		 5666 */
5667 retry++;
5668 tmp_loopid = fcport->loop_id;
5669 fcport->loop_id = mb[1];
5670
7c3df132
SK		 5671 ql_dbg(ql_dbg_disc, vha, 0x2001,
5672 "Fabric Login: port in use - next loop "
5673 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 5674 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 5675 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5676
5677 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
5678 /*
5679 * Login succeeded.
5680 */
5681 if (retry) {
5682 /* A retry occurred before. */
5683 *next_loopid = tmp_loopid;
5684 } else {
5685 /*
5686 * No retry occurred before. Just increment the
5687 * ID value for next login.
5688 */
5689 *next_loopid = (fcport->loop_id + 1);
5690 }
5691
5692 if (mb[1] & BIT_0) {
5693 fcport->port_type = FCT_INITIATOR;
5694 } else {
5695 fcport->port_type = FCT_TARGET;
5696 if (mb[1] & BIT_1) {
8474f3a0 5697 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 5698 }
5699 }
5700
ad3e0eda
AV		 5701 if (mb[10] & BIT_0)
5702 fcport->supported_classes |= FC_COS_CLASS2;
5703 if (mb[10] & BIT_1)
5704 fcport->supported_classes |= FC_COS_CLASS3;
5705
2d70c103
NB		 5706 if (IS_FWI2_CAPABLE(ha)) {
5707 if (mb[10] & BIT_7)
5708 fcport->flags |=
5709 FCF_CONF_COMP_SUPPORTED;
5710 }
5711
1da177e4
LT		 5712 rval = QLA_SUCCESS;
5713 break;
5714 } else if (mb[0] == MBS_LOOP_ID_USED) {
5715 /*
5716 * Loop ID already used, try next loop ID.
5717 */
5718 fcport->loop_id++;
e315cd28 5719 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 5720 if (rval != QLA_SUCCESS) {
5721 /* Ran out of loop IDs to use */
5722 break;
5723 }
5724 } else if (mb[0] == MBS_COMMAND_ERROR) {
5725 /*
5726 * Firmware possibly timed out during login. If NO
5727 * retries are left to do then the device is declared
5728 * dead.
5729 */
5730 *next_loopid = fcport->loop_id;
e315cd28 5731 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5732 fcport->d_id.b.domain, fcport->d_id.b.area,
5733 fcport->d_id.b.al_pa);
e315cd28 5734 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 5735
5736 rval = 1;
5737 break;
5738 } else {
5739 /*
5740 * unrecoverable / not handled error
5741 */
7c3df132
SK		 5742 ql_dbg(ql_dbg_disc, vha, 0x2002,
5743 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
5744 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
5745 fcport->d_id.b.area, fcport->d_id.b.al_pa,
5746 fcport->loop_id, jiffies);
1da177e4
LT		 5747
5748 *next_loopid = fcport->loop_id;
e315cd28 5749 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5750 fcport->d_id.b.domain, fcport->d_id.b.area,
5751 fcport->d_id.b.al_pa);
5f16b331 5752 qla2x00_clear_loop_id(fcport);
0eedfcf0 5753 fcport->login_retry = 0;
1da177e4
LT		 5754
5755 rval = 3;
5756 break;
5757 }
5758 }
5759
5760 return (rval);
5761}
5762
5763/*
5764 * qla2x00_local_device_login
5765 * Issue local device login command.
5766 *
5767 * Input:
5768 * ha = adapter block pointer.
5769 * loop_id = loop id of device to login to.
5770 *
5771 * Returns (Where's the #define!!!!):
5772 * 0 - Login successfully
5773 * 1 - Login failed
5774 * 3 - Fatal error
5775 */
5776int
e315cd28 5777qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 5778{
5779 int rval;
5780 uint16_t mb[MAILBOX_REGISTER_COUNT];
5781
5782 memset(mb, 0, sizeof(mb));
e315cd28 5783 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 5784 if (rval == QLA_SUCCESS) {
5785 /* Interrogate mailbox registers for any errors */
5786 if (mb[0] == MBS_COMMAND_ERROR)
5787 rval = 1;
5788 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
5789 /* device not in PCB table */
5790 rval = 3;
5791 }
5792
5793 return (rval);
5794}
5795
5796/*
5797 * qla2x00_loop_resync
5798 * Resync with fibre channel devices.
5799 *
5800 * Input:
5801 * ha = adapter block pointer.
5802 *
5803 * Returns:
5804 * 0 = success
5805 */
5806int
e315cd28 5807qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 5808{
73208dfd 5809 int rval = QLA_SUCCESS;
1da177e4 5810 uint32_t wait_time;
67c2e93a
AC		 5811 struct req_que *req;
5812 struct rsp_que *rsp;
5813
d7459527 5814 req = vha->req;
67c2e93a 5815 rsp = req->rsp;
1da177e4 5816
e315cd28
AC		 5817 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5818 if (vha->flags.online) {
5819 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 5820 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5821 wait_time = 256;
5822 do {
8ae6d9c7
GM		 5823 if (!IS_QLAFX00(vha->hw)) {
5824 /*
5825 * Issue a marker after FW becomes
5826 * ready.
5827 */
5828 qla2x00_marker(vha, req, rsp, 0, 0,
5829 MK_SYNC_ALL);
5830 vha->marker_needed = 0;
5831 }
1da177e4
LT		 5832
5833 /* Remap devices on Loop. */
e315cd28 5834 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 5835
8ae6d9c7
GM		 5836 if (IS_QLAFX00(vha->hw))
5837 qlafx00_configure_devices(vha);
5838 else
5839 qla2x00_configure_loop(vha);
5840
1da177e4 5841 wait_time--;
e315cd28
AC		 5842 } while (!atomic_read(&vha->loop_down_timer) &&
5843 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
5844 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
5845 &vha->dpc_flags)));
1da177e4 5846 }
1da177e4
LT		 5847 }
5848
e315cd28 5849 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 5850 return (QLA_FUNCTION_FAILED);
1da177e4 5851
e315cd28 5852 if (rval)
7c3df132
SK		 5853 ql_dbg(ql_dbg_disc, vha, 0x206c,
5854 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 5855
5856 return (rval);
5857}
5858
579d12b5
SK		 5859/*
5860* qla2x00_perform_loop_resync
5861* Description: This function will set the appropriate flags and call
5862* qla2x00_loop_resync. If successful loop will be resynced
5863* Arguments : scsi_qla_host_t pointer
5864* returm : Success or Failure
5865*/
5866
5867int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
5868{
5869 int32_t rval = 0;
5870
5871 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
5872 /*Configure the flags so that resync happens properly*/
5873 atomic_set(&ha->loop_down_timer, 0);
5874 if (!(ha->device_flags & DFLG_NO_CABLE)) {
5875 atomic_set(&ha->loop_state, LOOP_UP);
5876 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
5877 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
5878 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
5879
5880 rval = qla2x00_loop_resync(ha);
5881 } else
5882 atomic_set(&ha->loop_state, LOOP_DEAD);
5883
5884 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
5885 }
5886
5887 return rval;
5888}
5889
d97994dc 5890void
67becc00 5891qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 5892{
5893 fc_port_t *fcport;
feafb7b1
AE		 5894 struct scsi_qla_host *vha;
5895 struct qla_hw_data *ha = base_vha->hw;
5896 unsigned long flags;
d97994dc 5897
feafb7b1 5898 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 5899 /* Go with deferred removal of rport references. */
feafb7b1
AE		 5900 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
5901 atomic_inc(&vha->vref_count);
5902 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 5903 if (fcport->drport &&
feafb7b1
AE		 5904 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
5905 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 5906 qla2x00_rport_del(fcport);
df673274 5907
feafb7b1
AE		 5908 spin_lock_irqsave(&ha->vport_slock, flags);
5909 }
5910 }
5911 atomic_dec(&vha->vref_count);
c4a9b538 5912 wake_up(&vha->vref_waitq);
feafb7b1
AE		 5913 }
5914 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 5915}
5916
7d613ac6
SV		 5917/* Assumes idc_lock always held on entry */
5918void
5919qla83xx_reset_ownership(scsi_qla_host_t *vha)
5920{
5921 struct qla_hw_data *ha = vha->hw;
5922 uint32_t drv_presence, drv_presence_mask;
5923 uint32_t dev_part_info1, dev_part_info2, class_type;
5924 uint32_t class_type_mask = 0x3;
5925 uint16_t fcoe_other_function = 0xffff, i;
5926
7ec0effd
AD		 5927 if (IS_QLA8044(ha)) {
5928 drv_presence = qla8044_rd_direct(vha,
5929 QLA8044_CRB_DRV_ACTIVE_INDEX);
5930 dev_part_info1 = qla8044_rd_direct(vha,
5931 QLA8044_CRB_DEV_PART_INFO_INDEX);
5932 dev_part_info2 = qla8044_rd_direct(vha,
5933 QLA8044_CRB_DEV_PART_INFO2);
5934 } else {
5935 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5936 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
5937 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
5938 }
7d613ac6
SV		 5939 for (i = 0; i < 8; i++) {
5940 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
5941 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5942 (i != ha->portnum)) {
5943 fcoe_other_function = i;
5944 break;
5945 }
5946 }
5947 if (fcoe_other_function == 0xffff) {
5948 for (i = 0; i < 8; i++) {
5949 class_type = ((dev_part_info2 >> (i * 4)) &
5950 class_type_mask);
5951 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5952 ((i + 8) != ha->portnum)) {
5953 fcoe_other_function = i + 8;
5954 break;
5955 }
5956 }
5957 }
5958 /*
5959 * Prepare drv-presence mask based on fcoe functions present.
5960 * However consider only valid physical fcoe function numbers (0-15).
5961 */
5962 drv_presence_mask = ~((1 << (ha->portnum)) |
5963 ((fcoe_other_function == 0xffff) ?
5964 0 : (1 << (fcoe_other_function))));
5965
5966 /* We are the reset owner iff:
5967 * - No other protocol drivers present.
5968 * - This is the lowest among fcoe functions. */
5969 if (!(drv_presence & drv_presence_mask) &&
5970 (ha->portnum < fcoe_other_function)) {
5971 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
5972 "This host is Reset owner.\n");
5973 ha->flags.nic_core_reset_owner = 1;
5974 }
5975}
5976
fa492630 5977static int
7d613ac6
SV		 5978__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
5979{
5980 int rval = QLA_SUCCESS;
5981 struct qla_hw_data *ha = vha->hw;
5982 uint32_t drv_ack;
5983
5984 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5985 if (rval == QLA_SUCCESS) {
5986 drv_ack |= (1 << ha->portnum);
5987 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5988 }
5989
5990 return rval;
5991}
5992
fa492630 5993static int
7d613ac6
SV		 5994__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
5995{
5996 int rval = QLA_SUCCESS;
5997 struct qla_hw_data *ha = vha->hw;
5998 uint32_t drv_ack;
5999
6000 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6001 if (rval == QLA_SUCCESS) {
6002 drv_ack &= ~(1 << ha->portnum);
6003 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6004 }
6005
6006 return rval;
6007}
6008
fa492630 6009static const char *
7d613ac6
SV		 6010qla83xx_dev_state_to_string(uint32_t dev_state)
6011{
6012 switch (dev_state) {
6013 case QLA8XXX_DEV_COLD:
6014 return "COLD/RE-INIT";
6015 case QLA8XXX_DEV_INITIALIZING:
6016 return "INITIALIZING";
6017 case QLA8XXX_DEV_READY:
6018 return "READY";
6019 case QLA8XXX_DEV_NEED_RESET:
6020 return "NEED RESET";
6021 case QLA8XXX_DEV_NEED_QUIESCENT:
6022 return "NEED QUIESCENT";
6023 case QLA8XXX_DEV_FAILED:
6024 return "FAILED";
6025 case QLA8XXX_DEV_QUIESCENT:
6026 return "QUIESCENT";
6027 default:
6028 return "Unknown";
6029 }
6030}
6031
6032/* Assumes idc-lock always held on entry */
6033void
6034qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
6035{
6036 struct qla_hw_data *ha = vha->hw;
6037 uint32_t idc_audit_reg = 0, duration_secs = 0;
6038
6039 switch (audit_type) {
6040 case IDC_AUDIT_TIMESTAMP:
6041 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
6042 idc_audit_reg = (ha->portnum) |
6043 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
6044 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6045 break;
6046
6047 case IDC_AUDIT_COMPLETION:
6048 duration_secs = ((jiffies_to_msecs(jiffies) -
6049 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
6050 idc_audit_reg = (ha->portnum) |
6051 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
6052 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6053 break;
6054
6055 default:
6056 ql_log(ql_log_warn, vha, 0xb078,
6057 "Invalid audit type specified.\n");
6058 break;
6059 }
6060}
6061
6062/* Assumes idc_lock always held on entry */
fa492630 6063static int
7d613ac6
SV		 6064qla83xx_initiating_reset(scsi_qla_host_t *vha)
6065{
6066 struct qla_hw_data *ha = vha->hw;
6067 uint32_t idc_control, dev_state;
6068
6069 __qla83xx_get_idc_control(vha, &idc_control);
6070 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
6071 ql_log(ql_log_info, vha, 0xb080,
6072 "NIC Core reset has been disabled. idc-control=0x%x\n",
6073 idc_control);
6074 return QLA_FUNCTION_FAILED;
6075 }
6076
6077 /* Set NEED-RESET iff in READY state and we are the reset-owner */
6078 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6079 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
6080 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
6081 QLA8XXX_DEV_NEED_RESET);
6082 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
6083 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
6084 } else {
6085 const char *state = qla83xx_dev_state_to_string(dev_state);
6086 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
6087
6088 /* SV: XXX: Is timeout required here? */
6089 /* Wait for IDC state change READY -> NEED_RESET */
6090 while (dev_state == QLA8XXX_DEV_READY) {
6091 qla83xx_idc_unlock(vha, 0);
6092 msleep(200);
6093 qla83xx_idc_lock(vha, 0);
6094 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6095 }
6096 }
6097
6098 /* Send IDC ack by writing to drv-ack register */
6099 __qla83xx_set_drv_ack(vha);
6100
6101 return QLA_SUCCESS;
6102}
6103
6104int
6105__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
6106{
6107 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6108}
6109
7d613ac6
SV		 6110int
6111__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
6112{
6113 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6114}
6115
fa492630 6116static int
7d613ac6
SV		 6117qla83xx_check_driver_presence(scsi_qla_host_t *vha)
6118{
6119 uint32_t drv_presence = 0;
6120 struct qla_hw_data *ha = vha->hw;
6121
6122 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6123 if (drv_presence & (1 << ha->portnum))
6124 return QLA_SUCCESS;
6125 else
6126 return QLA_TEST_FAILED;
6127}
6128
6129int
6130qla83xx_nic_core_reset(scsi_qla_host_t *vha)
6131{
6132 int rval = QLA_SUCCESS;
6133 struct qla_hw_data *ha = vha->hw;
6134
6135 ql_dbg(ql_dbg_p3p, vha, 0xb058,
6136 "Entered %s().\n", __func__);
6137
6138 if (vha->device_flags & DFLG_DEV_FAILED) {
6139 ql_log(ql_log_warn, vha, 0xb059,
6140 "Device in unrecoverable FAILED state.\n");
6141 return QLA_FUNCTION_FAILED;
6142 }
6143
6144 qla83xx_idc_lock(vha, 0);
6145
6146 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
6147 ql_log(ql_log_warn, vha, 0xb05a,
6148 "Function=0x%x has been removed from IDC participation.\n",
6149 ha->portnum);
6150 rval = QLA_FUNCTION_FAILED;
6151 goto exit;
6152 }
6153
6154 qla83xx_reset_ownership(vha);
6155
6156 rval = qla83xx_initiating_reset(vha);
6157
6158 /*
6159 * Perform reset if we are the reset-owner,
6160 * else wait till IDC state changes to READY/FAILED.
6161 */
6162 if (rval == QLA_SUCCESS) {
6163 rval = qla83xx_idc_state_handler(vha);
6164
6165 if (rval == QLA_SUCCESS)
6166 ha->flags.nic_core_hung = 0;
6167 __qla83xx_clear_drv_ack(vha);
6168 }
6169
6170exit:
6171 qla83xx_idc_unlock(vha, 0);
6172
6173 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
6174
6175 return rval;
6176}
6177
81178772
SK		 6178int
6179qla2xxx_mctp_dump(scsi_qla_host_t *vha)
6180{
6181 struct qla_hw_data *ha = vha->hw;
6182 int rval = QLA_FUNCTION_FAILED;
6183
6184 if (!IS_MCTP_CAPABLE(ha)) {
6185 /* This message can be removed from the final version */
6186 ql_log(ql_log_info, vha, 0x506d,
6187 "This board is not MCTP capable\n");
6188 return rval;
6189 }
6190
6191 if (!ha->mctp_dump) {
6192 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
6193 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
6194
6195 if (!ha->mctp_dump) {
6196 ql_log(ql_log_warn, vha, 0x506e,
6197 "Failed to allocate memory for mctp dump\n");
6198 return rval;
6199 }
6200 }
6201
6202#define MCTP_DUMP_STR_ADDR 0x00000000
6203 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
6204 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
6205 if (rval != QLA_SUCCESS) {
6206 ql_log(ql_log_warn, vha, 0x506f,
6207 "Failed to capture mctp dump\n");
6208 } else {
6209 ql_log(ql_log_info, vha, 0x5070,
6210 "Mctp dump capture for host (%ld/%p).\n",
6211 vha->host_no, ha->mctp_dump);
6212 ha->mctp_dumped = 1;
6213 }
6214
409ee0fe 6215 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 6216 ha->flags.nic_core_reset_hdlr_active = 1;
6217 rval = qla83xx_restart_nic_firmware(vha);
6218 if (rval)
6219 /* NIC Core reset failed. */
6220 ql_log(ql_log_warn, vha, 0x5071,
6221 "Failed to restart nic firmware\n");
6222 else
6223 ql_dbg(ql_dbg_p3p, vha, 0xb084,
6224 "Restarted NIC firmware successfully.\n");
6225 ha->flags.nic_core_reset_hdlr_active = 0;
6226 }
6227
6228 return rval;
6229
6230}
6231
579d12b5 6232/*
8fcd6b8b 6233* qla2x00_quiesce_io
579d12b5
SK		 6234* Description: This function will block the new I/Os
6235* Its not aborting any I/Os as context
6236* is not destroyed during quiescence
6237* Arguments: scsi_qla_host_t
6238* return : void
6239*/
6240void
8fcd6b8b 6241qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 6242{
6243 struct qla_hw_data *ha = vha->hw;
6244 struct scsi_qla_host *vp;
6245
8fcd6b8b
CD		 6246 ql_dbg(ql_dbg_dpc, vha, 0x401d,
6247 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 6248
6249 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
6250 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6251 atomic_set(&vha->loop_state, LOOP_DOWN);
6252 qla2x00_mark_all_devices_lost(vha, 0);
6253 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 6254 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 6255 } else {
6256 if (!atomic_read(&vha->loop_down_timer))
6257 atomic_set(&vha->loop_down_timer,
6258 LOOP_DOWN_TIME);
6259 }
6260 /* Wait for pending cmds to complete */
6261 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
6262}
6263
a9083016
GM		 6264void
6265qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
6266{
6267 struct qla_hw_data *ha = vha->hw;
579d12b5 6268 struct scsi_qla_host *vp;
feafb7b1 6269 unsigned long flags;
6aef87be 6270 fc_port_t *fcport;
7c3f8fd1 6271 u16 i;
a9083016 6272
e46ef004
SK		 6273 /* For ISP82XX, driver waits for completion of the commands.
6274 * online flag should be set.
6275 */
7ec0effd 6276 if (!(IS_P3P_TYPE(ha)))
e46ef004 6277 vha->flags.online = 0;
a9083016
GM		 6278 ha->flags.chip_reset_done = 0;
6279 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 6280 vha->qla_stats.total_isp_aborts++;
a9083016 6281
7c3df132
SK		 6282 ql_log(ql_log_info, vha, 0x00af,
6283 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 6284
e46ef004
SK		 6285 /* For ISP82XX, reset_chip is just disabling interrupts.
6286 * Driver waits for the completion of the commands.
6287 * the interrupts need to be enabled.
6288 */
7ec0effd 6289 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 6290 ha->isp_ops->reset_chip(vha);
6291
9cd883f0
QT		 6292 SAVE_TOPO(ha);
6293 ha->flags.rida_fmt2 = 0;
ec7193e2
QT		 6294 ha->flags.n2n_ae = 0;
6295 ha->flags.lip_ae = 0;
6296 ha->current_topology = 0;
6297 ha->flags.fw_started = 0;
6298 ha->flags.fw_init_done = 0;
7c3f8fd1
QT		 6299 ha->base_qpair->chip_reset++;
6300 for (i = 0; i < ha->max_qpairs; i++) {
6301 if (ha->queue_pair_map[i])
6302 ha->queue_pair_map[i]->chip_reset =
6303 ha->base_qpair->chip_reset;
6304 }
726b8548 6305
a9083016
GM		 6306 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
6307 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6308 atomic_set(&vha->loop_state, LOOP_DOWN);
6309 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 6310
6311 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 6312 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 6313 atomic_inc(&vp->vref_count);
6314 spin_unlock_irqrestore(&ha->vport_slock, flags);
6315
a9083016 6316 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 6317
6318 spin_lock_irqsave(&ha->vport_slock, flags);
6319 atomic_dec(&vp->vref_count);
6320 }
6321 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 6322 } else {
6323 if (!atomic_read(&vha->loop_down_timer))
6324 atomic_set(&vha->loop_down_timer,
6325 LOOP_DOWN_TIME);
6326 }
6327
6aef87be
AV		 6328 /* Clear all async request states across all VPs. */
6329 list_for_each_entry(fcport, &vha->vp_fcports, list)
6330 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6331 spin_lock_irqsave(&ha->vport_slock, flags);
6332 list_for_each_entry(vp, &ha->vp_list, list) {
6333 atomic_inc(&vp->vref_count);
6334 spin_unlock_irqrestore(&ha->vport_slock, flags);
6335
6336 list_for_each_entry(fcport, &vp->vp_fcports, list)
6337 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6338
6339 spin_lock_irqsave(&ha->vport_slock, flags);
6340 atomic_dec(&vp->vref_count);
6341 }
6342 spin_unlock_irqrestore(&ha->vport_slock, flags);
6343
bddd2d65
LC		 6344 if (!ha->flags.eeh_busy) {
6345 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 6346 if (IS_P3P_TYPE(ha)) {
7190575f 6347 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 6348 ql_log(ql_log_info, vha, 0x00b4,
6349 "Done chip reset cleanup.\n");
a9083016 6350
e46ef004
SK		 6351 /* Done waiting for pending commands.
6352 * Reset the online flag.
6353 */
6354 vha->flags.online = 0;
4d78c973 6355 }
a9083016 6356
bddd2d65
LC		 6357 /* Requeue all commands in outstanding command list. */
6358 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6359 }
b6a029e1
AE		 6360 /* memory barrier */
6361 wmb();
a9083016
GM		 6362}
6363
1da177e4
LT		 6364/*
6365* qla2x00_abort_isp
6366* Resets ISP and aborts all outstanding commands.
6367*
6368* Input:
6369* ha = adapter block pointer.
6370*
6371* Returns:
6372* 0 = success
6373*/
6374int
e315cd28 6375qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 6376{
476e8978 6377 int rval;
1da177e4 6378 uint8_t status = 0;
e315cd28
AC		 6379 struct qla_hw_data *ha = vha->hw;
6380 struct scsi_qla_host *vp;
73208dfd 6381 struct req_que *req = ha->req_q_map[0];
feafb7b1 6382 unsigned long flags;
1da177e4 6383
e315cd28 6384 if (vha->flags.online) {
a9083016 6385 qla2x00_abort_isp_cleanup(vha);
1da177e4 6386
a6171297
SV		 6387 if (IS_QLA8031(ha)) {
6388 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
6389 "Clearing fcoe driver presence.\n");
6390 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
6391 ql_dbg(ql_dbg_p3p, vha, 0xb073,
6392 "Error while clearing DRV-Presence.\n");
6393 }
6394
85880801
AV		 6395 if (unlikely(pci_channel_offline(ha->pdev) &&
6396 ha->flags.pci_channel_io_perm_failure)) {
6397 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6398 status = 0;
6399 return status;
6400 }
6401
73208dfd 6402 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 6403
e315cd28 6404 ha->isp_ops->nvram_config(vha);
1da177e4 6405
e315cd28
AC		 6406 if (!qla2x00_restart_isp(vha)) {
6407 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 6408
e315cd28 6409 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 6410 /*
6411 * Issue marker command only when we are going
6412 * to start the I/O .
6413 */
e315cd28 6414 vha->marker_needed = 1;
1da177e4
LT		 6415 }
6416
e315cd28 6417 vha->flags.online = 1;
1da177e4 6418
fd34f556 6419 ha->isp_ops->enable_intrs(ha);
1da177e4 6420
fa2a1ce5 6421 ha->isp_abort_cnt = 0;
e315cd28 6422 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 6423
6246b8a1
GM		 6424 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
6425 qla2x00_get_fw_version(vha);
df613b96
AV		 6426 if (ha->fce) {
6427 ha->flags.fce_enabled = 1;
6428 memset(ha->fce, 0,
6429 fce_calc_size(ha->fce_bufs));
e315cd28 6430 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 6431 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6432 &ha->fce_bufs);
6433 if (rval) {
7c3df132 6434 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 6435 "Unable to reinitialize FCE "
6436 "(%d).\n", rval);
6437 ha->flags.fce_enabled = 0;
6438 }
6439 }
436a7b11
AV		 6440
6441 if (ha->eft) {
6442 memset(ha->eft, 0, EFT_SIZE);
e315cd28 6443 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 6444 ha->eft_dma, EFT_NUM_BUFFERS);
6445 if (rval) {
7c3df132 6446 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 6447 "Unable to reinitialize EFT "
6448 "(%d).\n", rval);
6449 }
6450 }
1da177e4 6451 } else { /* failed the ISP abort */
e315cd28
AC		 6452 vha->flags.online = 1;
6453 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 6454 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 6455 ql_log(ql_log_fatal, vha, 0x8035,
6456 "ISP error recover failed - "
6457 "board disabled.\n");
fa2a1ce5 6458 /*
1da177e4
LT		 6459 * The next call disables the board
6460 * completely.
6461 */
e315cd28
AC		 6462 ha->isp_ops->reset_adapter(vha);
6463 vha->flags.online = 0;
1da177e4 6464 clear_bit(ISP_ABORT_RETRY,
e315cd28 6465 &vha->dpc_flags);
1da177e4
LT		 6466 status = 0;
6467 } else { /* schedule another ISP abort */
6468 ha->isp_abort_cnt--;
7c3df132
SK		 6469 ql_dbg(ql_dbg_taskm, vha, 0x8020,
6470 "ISP abort - retry remaining %d.\n",
6471 ha->isp_abort_cnt);
1da177e4
LT		 6472 status = 1;
6473 }
6474 } else {
6475 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 6476 ql_dbg(ql_dbg_taskm, vha, 0x8021,
6477 "ISP error recovery - retrying (%d) "
6478 "more times.\n", ha->isp_abort_cnt);
e315cd28 6479 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 6480 status = 1;
6481 }
6482 }
fa2a1ce5 6483
1da177e4
LT		 6484 }
6485
e315cd28 6486 if (!status) {
7c3df132 6487 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
1608cc4a 6488 qla2x00_configure_hba(vha);
feafb7b1
AE		 6489 spin_lock_irqsave(&ha->vport_slock, flags);
6490 list_for_each_entry(vp, &ha->vp_list, list) {
6491 if (vp->vp_idx) {
6492 atomic_inc(&vp->vref_count);
6493 spin_unlock_irqrestore(&ha->vport_slock, flags);
6494
e315cd28 6495 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6496
6497 spin_lock_irqsave(&ha->vport_slock, flags);
6498 atomic_dec(&vp->vref_count);
6499 }
e315cd28 6500 }
feafb7b1
AE		 6501 spin_unlock_irqrestore(&ha->vport_slock, flags);
6502
7d613ac6
SV		 6503 if (IS_QLA8031(ha)) {
6504 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
6505 "Setting back fcoe driver presence.\n");
6506 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
6507 ql_dbg(ql_dbg_p3p, vha, 0xb074,
6508 "Error while setting DRV-Presence.\n");
6509 }
e315cd28 6510 } else {
d8424f68
JP		 6511 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
6512 __func__);
1da177e4
LT		 6513 }
6514
6515 return(status);
6516}
6517
6518/*
6519* qla2x00_restart_isp
6520* restarts the ISP after a reset
6521*
6522* Input:
6523* ha = adapter block pointer.
6524*
6525* Returns:
6526* 0 = success
6527*/
6528static int
e315cd28 6529qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 6530{
c6b2fca8 6531 int status = 0;
e315cd28 6532 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 6533 struct req_que *req = ha->req_q_map[0];
6534 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 6535
6536 /* If firmware needs to be loaded */
e315cd28
AC		 6537 if (qla2x00_isp_firmware(vha)) {
6538 vha->flags.online = 0;
6539 status = ha->isp_ops->chip_diag(vha);
6540 if (!status)
6541 status = qla2x00_setup_chip(vha);
1da177e4
LT		 6542 }
6543
e315cd28
AC		 6544 if (!status && !(status = qla2x00_init_rings(vha))) {
6545 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 6546 ha->flags.chip_reset_done = 1;
7108b76e 6547
73208dfd
AC		 6548 /* Initialize the queues in use */
6549 qla25xx_init_queues(ha);
6550
e315cd28
AC		 6551 status = qla2x00_fw_ready(vha);
6552 if (!status) {
0107109e 6553 /* Issue a marker after FW becomes ready. */
73208dfd 6554 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 6555 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6556 }
6557
6558 /* if no cable then assume it's good */
e315cd28 6559 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 6560 status = 0;
1da177e4
LT		 6561 }
6562 return (status);
6563}
6564
73208dfd
AC		 6565static int
6566qla25xx_init_queues(struct qla_hw_data *ha)
6567{
6568 struct rsp_que *rsp = NULL;
6569 struct req_que *req = NULL;
6570 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6571 int ret = -1;
6572 int i;
6573
2afa19a9 6574 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 6575 rsp = ha->rsp_q_map[i];
cb43285f 6576 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 6577 rsp->options &= ~BIT_0;
618a7523 6578 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 6579 if (ret != QLA_SUCCESS)
7c3df132
SK		 6580 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
6581 "%s Rsp que: %d init failed.\n",
6582 __func__, rsp->id);
73208dfd 6583 else
7c3df132
SK		 6584 ql_dbg(ql_dbg_init, base_vha, 0x0100,
6585 "%s Rsp que: %d inited.\n",
6586 __func__, rsp->id);
73208dfd 6587 }
2afa19a9
AC		 6588 }
6589 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 6590 req = ha->req_q_map[i];
cb43285f
QT		 6591 if (req && test_bit(i, ha->req_qid_map)) {
6592 /* Clear outstanding commands array. */
73208dfd 6593 req->options &= ~BIT_0;
618a7523 6594 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 6595 if (ret != QLA_SUCCESS)
7c3df132
SK		 6596 ql_dbg(ql_dbg_init, base_vha, 0x0101,
6597 "%s Req que: %d init failed.\n",
6598 __func__, req->id);
73208dfd 6599 else
7c3df132
SK		 6600 ql_dbg(ql_dbg_init, base_vha, 0x0102,
6601 "%s Req que: %d inited.\n",
6602 __func__, req->id);
73208dfd
AC		 6603 }
6604 }
6605 return ret;
6606}
6607
1da177e4
LT		 6608/*
6609* qla2x00_reset_adapter
6610* Reset adapter.
6611*
6612* Input:
6613* ha = adapter block pointer.
6614*/
abbd8870 6615void
e315cd28 6616qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 6617{
6618 unsigned long flags = 0;
e315cd28 6619 struct qla_hw_data *ha = vha->hw;
3d71644c 6620 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 6621
e315cd28 6622 vha->flags.online = 0;
fd34f556 6623 ha->isp_ops->disable_intrs(ha);
1da177e4 6624
1da177e4
LT		 6625 spin_lock_irqsave(&ha->hardware_lock, flags);
6626 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
6627 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6628 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
6629 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6630 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6631}
0107109e
AV		 6632
6633void
e315cd28 6634qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 6635{
6636 unsigned long flags = 0;
e315cd28 6637 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 6638 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
6639
7ec0effd 6640 if (IS_P3P_TYPE(ha))
a9083016
GM		 6641 return;
6642
e315cd28 6643 vha->flags.online = 0;
fd34f556 6644 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 6645
6646 spin_lock_irqsave(&ha->hardware_lock, flags);
6647 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
6648 RD_REG_DWORD(&reg->hccr);
6649 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
6650 RD_REG_DWORD(&reg->hccr);
6651 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 6652
6653 if (IS_NOPOLLING_TYPE(ha))
6654 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 6655}
6656
4e08df3f
DM		 6657/* On sparc systems, obtain port and node WWN from firmware
6658 * properties.
6659 */
e315cd28
AC		 6660static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
6661 struct nvram_24xx *nv)
4e08df3f
DM		 6662{
6663#ifdef CONFIG_SPARC
e315cd28 6664 struct qla_hw_data *ha = vha->hw;
4e08df3f 6665 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 6666 struct device_node *dp = pci_device_to_OF_node(pdev);
6667 const u8 *val;
4e08df3f
DM		 6668 int len;
6669
6670 val = of_get_property(dp, "port-wwn", &len);
6671 if (val && len >= WWN_SIZE)
6672 memcpy(nv->port_name, val, WWN_SIZE);
6673
6674 val = of_get_property(dp, "node-wwn", &len);
6675 if (val && len >= WWN_SIZE)
6676 memcpy(nv->node_name, val, WWN_SIZE);
6677#endif
6678}
6679
0107109e 6680int
e315cd28 6681qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 6682{
4e08df3f 6683 int rval;
0107109e
AV		 6684 struct init_cb_24xx *icb;
6685 struct nvram_24xx *nv;
6686 uint32_t *dptr;
6687 uint8_t *dptr1, *dptr2;
6688 uint32_t chksum;
6689 uint16_t cnt;
e315cd28 6690 struct qla_hw_data *ha = vha->hw;
0107109e 6691
4e08df3f 6692 rval = QLA_SUCCESS;
0107109e 6693 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 6694 nv = ha->nvram;
0107109e
AV		 6695
6696 /* Determine NVRAM starting address. */
f73cb695 6697 if (ha->port_no == 0) {
e5b68a61
AC		 6698 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
6699 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
6700 } else {
0107109e 6701 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 6702 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
6703 }
f73cb695 6704
e5b68a61
AC		 6705 ha->nvram_size = sizeof(struct nvram_24xx);
6706 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 6707
281afe19
SJ		 6708 /* Get VPD data into cache */
6709 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 6710 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 6711 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
6712
6713 /* Get NVRAM data into cache and calculate checksum. */
0107109e 6714 dptr = (uint32_t *)nv;
e315cd28 6715 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 6716 ha->nvram_size);
da08ef5c
JC		 6717 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6718 chksum += le32_to_cpu(*dptr);
0107109e 6719
7c3df132
SK		 6720 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
6721 "Contents of NVRAM\n");
6722 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
6723 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 6724
6725 /* Bad NVRAM data, set defaults parameters. */
6726 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6727 || nv->id[3] != ' ' ||
ad950360 6728 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 6729 /* Reset NVRAM data. */
7c3df132 6730 ql_log(ql_log_warn, vha, 0x006b,
9e336520 6731 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 6732 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
6733 ql_log(ql_log_warn, vha, 0x006c,
6734 "Falling back to functioning (yet invalid -- WWPN) "
6735 "defaults.\n");
4e08df3f
DM		 6736
6737 /*
6738 * Set default initialization control block.
6739 */
6740 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6741 nv->nvram_version = cpu_to_le16(ICB_VERSION);
6742 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 6743 nv->frame_payload_size = 2048;
ad950360
BVA		 6744 nv->execution_throttle = cpu_to_le16(0xFFFF);
6745 nv->exchange_count = cpu_to_le16(0);
6746 nv->hard_address = cpu_to_le16(124);
4e08df3f 6747 nv->port_name[0] = 0x21;
f73cb695 6748 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 6749 nv->port_name[2] = 0x00;
6750 nv->port_name[3] = 0xe0;
6751 nv->port_name[4] = 0x8b;
6752 nv->port_name[5] = 0x1c;
6753 nv->port_name[6] = 0x55;
6754 nv->port_name[7] = 0x86;
6755 nv->node_name[0] = 0x20;
6756 nv->node_name[1] = 0x00;
6757 nv->node_name[2] = 0x00;
6758 nv->node_name[3] = 0xe0;
6759 nv->node_name[4] = 0x8b;
6760 nv->node_name[5] = 0x1c;
6761 nv->node_name[6] = 0x55;
6762 nv->node_name[7] = 0x86;
e315cd28 6763 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 6764 nv->login_retry_count = cpu_to_le16(8);
6765 nv->interrupt_delay_timer = cpu_to_le16(0);
6766 nv->login_timeout = cpu_to_le16(0);
4e08df3f 6767 nv->firmware_options_1 =
ad950360
BVA		 6768 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
6769 nv->firmware_options_2 = cpu_to_le32(2 << 4);
6770 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
6771 nv->firmware_options_3 = cpu_to_le32(2 << 13);
6772 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
6773 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 6774 nv->reset_delay = 5;
ad950360
BVA		 6775 nv->max_luns_per_target = cpu_to_le16(128);
6776 nv->port_down_retry_count = cpu_to_le16(30);
6777 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 6778
6779 rval = 1;
0107109e
AV		 6780 }
6781
726b8548 6782 if (qla_tgt_mode_enabled(vha)) {
2d70c103 6783 /* Don't enable full login after initial LIP */
ad950360 6784 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 6785 /* Don't enable LIP full login for initiator */
ad950360 6786 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 6787 }
6788
6789 qlt_24xx_config_nvram_stage1(vha, nv);
6790
0107109e 6791 /* Reset Initialization control block */
e315cd28 6792 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 6793
6794 /* Copy 1st segment. */
6795 dptr1 = (uint8_t *)icb;
6796 dptr2 = (uint8_t *)&nv->version;
6797 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6798 while (cnt--)
6799 *dptr1++ = *dptr2++;
6800
6801 icb->login_retry_count = nv->login_retry_count;
3ea66e28 6802 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 6803
6804 /* Copy 2nd segment. */
6805 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6806 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6807 cnt = (uint8_t *)&icb->reserved_3 -
6808 (uint8_t *)&icb->interrupt_delay_timer;
6809 while (cnt--)
6810 *dptr1++ = *dptr2++;
6811
6812 /*
6813 * Setup driver NVRAM options.
6814 */
e315cd28 6815 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 6816 "QLA2462");
0107109e 6817
2d70c103
NB		 6818 qlt_24xx_config_nvram_stage2(vha, icb);
6819
ad950360 6820 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 6821 /* Use alternate WWN? */
5341e868
AV		 6822 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6823 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6824 }
6825
0107109e 6826 /* Prepare nodename */
ad950360 6827 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 6828 /*
6829 * Firmware will apply the following mask if the nodename was
6830 * not provided.
6831 */
6832 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6833 icb->node_name[0] &= 0xF0;
6834 }
6835
6836 /* Set host adapter parameters. */
6837 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 6838 ha->flags.enable_lip_reset = 0;
6839 ha->flags.enable_lip_full_login =
6840 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6841 ha->flags.enable_target_reset =
6842 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 6843 ha->flags.enable_led_scheme = 0;
d4c760c2 6844 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 6845
fd0e7e4d
AV		 6846 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6847 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 6848
6849 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
6850 sizeof(ha->fw_seriallink_options24));
6851
6852 /* save HBA serial number */
6853 ha->serial0 = icb->port_name[5];
6854 ha->serial1 = icb->port_name[6];
6855 ha->serial2 = icb->port_name[7];
e315cd28
AC		 6856 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6857 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 6858
ad950360 6859 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 6860
0107109e
AV		 6861 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6862
6863 /* Set minimum login_timeout to 4 seconds. */
6864 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6865 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6866 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6867 nv->login_timeout = cpu_to_le16(4);
0107109e 6868 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 6869
00a537b8
AV		 6870 /* Set minimum RATOV to 100 tenths of a second. */
6871 ha->r_a_tov = 100;
0107109e
AV		 6872
6873 ha->loop_reset_delay = nv->reset_delay;
6874
6875 /* Link Down Timeout = 0:
6876 *
6877 * When Port Down timer expires we will start returning
6878 * I/O's to OS with "DID_NO_CONNECT".
6879 *
6880 * Link Down Timeout != 0:
6881 *
6882 * The driver waits for the link to come up after link down
6883 * before returning I/Os to OS with "DID_NO_CONNECT".
6884 */
6885 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6886 ha->loop_down_abort_time =
6887 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6888 } else {
6889 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6890 ha->loop_down_abort_time =
6891 (LOOP_DOWN_TIME - ha->link_down_timeout);
6892 }
6893
6894 /* Need enough time to try and get the port back. */
6895 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6896 if (qlport_down_retry)
6897 ha->port_down_retry_count = qlport_down_retry;
6898
6899 /* Set login_retry_count */
6900 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6901 if (ha->port_down_retry_count ==
6902 le16_to_cpu(nv->port_down_retry_count) &&
6903 ha->port_down_retry_count > 3)
6904 ha->login_retry_count = ha->port_down_retry_count;
6905 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6906 ha->login_retry_count = ha->port_down_retry_count;
6907 if (ql2xloginretrycount)
6908 ha->login_retry_count = ql2xloginretrycount;
6909
4fdfefe5 6910 /* Enable ZIO. */
e315cd28 6911 if (!vha->flags.init_done) {
4fdfefe5
AV		 6912 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6913 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6914 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6915 le16_to_cpu(icb->interrupt_delay_timer): 2;
6916 }
ad950360 6917 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 6918 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 6919 vha->flags.process_response_queue = 0;
4fdfefe5 6920 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 6921 ha->zio_mode = QLA_ZIO_MODE_6;
6922
7c3df132 6923 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 6924 "ZIO mode %d enabled; timer delay (%d us).\n",
6925 ha->zio_mode, ha->zio_timer * 100);
6926
6927 icb->firmware_options_2 |= cpu_to_le32(
6928 (uint32_t)ha->zio_mode);
6929 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 6930 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 6931 }
6932
4e08df3f 6933 if (rval) {
7c3df132
SK		 6934 ql_log(ql_log_warn, vha, 0x0070,
6935 "NVRAM configuration failed.\n");
4e08df3f
DM		 6936 }
6937 return (rval);
0107109e
AV		 6938}
6939
4243c115
SC		 6940uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
6941{
6942 struct qla27xx_image_status pri_image_status, sec_image_status;
6943 uint8_t valid_pri_image, valid_sec_image;
6944 uint32_t *wptr;
6945 uint32_t cnt, chksum, size;
6946 struct qla_hw_data *ha = vha->hw;
6947
6948 valid_pri_image = valid_sec_image = 1;
6949 ha->active_image = 0;
6950 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
6951
6952 if (!ha->flt_region_img_status_pri) {
6953 valid_pri_image = 0;
6954 goto check_sec_image;
6955 }
6956
6957 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
6958 ha->flt_region_img_status_pri, size);
6959
6960 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6961 ql_dbg(ql_dbg_init, vha, 0x018b,
6962 "Primary image signature (0x%x) not valid\n",
6963 pri_image_status.signature);
6964 valid_pri_image = 0;
6965 goto check_sec_image;
6966 }
6967
6968 wptr = (uint32_t *)(&pri_image_status);
6969 cnt = size;
6970
da08ef5c
JC		 6971 for (chksum = 0; cnt--; wptr++)
6972 chksum += le32_to_cpu(*wptr);
41dc529a 6973
4243c115
SC		 6974 if (chksum) {
6975 ql_dbg(ql_dbg_init, vha, 0x018c,
6976 "Checksum validation failed for primary image (0x%x)\n",
6977 chksum);
6978 valid_pri_image = 0;
6979 }
6980
6981check_sec_image:
6982 if (!ha->flt_region_img_status_sec) {
6983 valid_sec_image = 0;
6984 goto check_valid_image;
6985 }
6986
6987 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
6988 ha->flt_region_img_status_sec, size);
6989
6990 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6991 ql_dbg(ql_dbg_init, vha, 0x018d,
6992 "Secondary image signature(0x%x) not valid\n",
6993 sec_image_status.signature);
6994 valid_sec_image = 0;
6995 goto check_valid_image;
6996 }
6997
6998 wptr = (uint32_t *)(&sec_image_status);
6999 cnt = size;
da08ef5c
JC		 7000 for (chksum = 0; cnt--; wptr++)
7001 chksum += le32_to_cpu(*wptr);
4243c115
SC		 7002 if (chksum) {
7003 ql_dbg(ql_dbg_init, vha, 0x018e,
7004 "Checksum validation failed for secondary image (0x%x)\n",
7005 chksum);
7006 valid_sec_image = 0;
7007 }
7008
7009check_valid_image:
7010 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
7011 ha->active_image = QLA27XX_PRIMARY_IMAGE;
7012 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
7013 if (!ha->active_image ||
7014 pri_image_status.generation_number <
7015 sec_image_status.generation_number)
7016 ha->active_image = QLA27XX_SECONDARY_IMAGE;
7017 }
7018
7019 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
7020 ha->active_image == 0 ? "default bootld and fw" :
7021 ha->active_image == 1 ? "primary" :
7022 ha->active_image == 2 ? "secondary" :
7023 "Invalid");
7024
7025 return ha->active_image;
7026}
7027
413975a0 7028static int
cbc8eb67
AV		 7029qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
7030 uint32_t faddr)
d1c61909 7031{
73208dfd 7032 int rval = QLA_SUCCESS;
d1c61909 7033 int segments, fragment;
d1c61909
AV		 7034 uint32_t *dcode, dlen;
7035 uint32_t risc_addr;
7036 uint32_t risc_size;
7037 uint32_t i;
e315cd28 7038 struct qla_hw_data *ha = vha->hw;
73208dfd 7039 struct req_que *req = ha->req_q_map[0];
eaac30be 7040
7c3df132 7041 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 7042 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 7043
d1c61909
AV		 7044 rval = QLA_SUCCESS;
7045
7046 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7047 dcode = (uint32_t *)req->ring;
d1c61909
AV		 7048 *srisc_addr = 0;
7049
4243c115
SC		 7050 if (IS_QLA27XX(ha) &&
7051 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
7052 faddr = ha->flt_region_fw_sec;
7053
d1c61909 7054 /* Validate firmware image by checking version. */
e315cd28 7055 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 7056 for (i = 0; i < 4; i++)
7057 dcode[i] = be32_to_cpu(dcode[i]);
7058 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7059 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7060 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7061 dcode[3] == 0)) {
7c3df132
SK		 7062 ql_log(ql_log_fatal, vha, 0x008c,
7063 "Unable to verify the integrity of flash firmware "
7064 "image.\n");
7065 ql_log(ql_log_fatal, vha, 0x008d,
7066 "Firmware data: %08x %08x %08x %08x.\n",
7067 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 7068
7069 return QLA_FUNCTION_FAILED;
7070 }
7071
7072 while (segments && rval == QLA_SUCCESS) {
7073 /* Read segment's load information. */
e315cd28 7074 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 7075
7076 risc_addr = be32_to_cpu(dcode[2]);
7077 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7078 risc_size = be32_to_cpu(dcode[3]);
7079
7080 fragment = 0;
7081 while (risc_size > 0 && rval == QLA_SUCCESS) {
7082 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7083 if (dlen > risc_size)
7084 dlen = risc_size;
7085
7c3df132
SK		 7086 ql_dbg(ql_dbg_init, vha, 0x008e,
7087 "Loading risc segment@ risc addr %x "
7088 "number of dwords 0x%x offset 0x%x.\n",
7089 risc_addr, dlen, faddr);
d1c61909 7090
e315cd28 7091 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 7092 for (i = 0; i < dlen; i++)
7093 dcode[i] = swab32(dcode[i]);
7094
73208dfd 7095 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 7096 dlen);
7097 if (rval) {
7c3df132
SK		 7098 ql_log(ql_log_fatal, vha, 0x008f,
7099 "Failed to load segment %d of firmware.\n",
7100 fragment);
f261f7af 7101 return QLA_FUNCTION_FAILED;
d1c61909
AV		 7102 }
7103
7104 faddr += dlen;
7105 risc_addr += dlen;
7106 risc_size -= dlen;
7107 fragment++;
7108 }
7109
7110 /* Next segment. */
7111 segments--;
7112 }
7113
f73cb695
CD		 7114 if (!IS_QLA27XX(ha))
7115 return rval;
7116
7117 if (ha->fw_dump_template)
7118 vfree(ha->fw_dump_template);
7119 ha->fw_dump_template = NULL;
7120 ha->fw_dump_template_len = 0;
7121
7122 ql_dbg(ql_dbg_init, vha, 0x0161,
7123 "Loading fwdump template from %x\n", faddr);
7124 qla24xx_read_flash_data(vha, dcode, faddr, 7);
7125 risc_size = be32_to_cpu(dcode[2]);
7126 ql_dbg(ql_dbg_init, vha, 0x0162,
7127 "-> array size %x dwords\n", risc_size);
7128 if (risc_size == 0 || risc_size == ~0)
7129 goto default_template;
7130
7131 dlen = (risc_size - 8) * sizeof(*dcode);
7132 ql_dbg(ql_dbg_init, vha, 0x0163,
7133 "-> template allocating %x bytes...\n", dlen);
7134 ha->fw_dump_template = vmalloc(dlen);
7135 if (!ha->fw_dump_template) {
7136 ql_log(ql_log_warn, vha, 0x0164,
7137 "Failed fwdump template allocate %x bytes.\n", risc_size);
7138 goto default_template;
7139 }
7140
7141 faddr += 7;
7142 risc_size -= 8;
7143 dcode = ha->fw_dump_template;
7144 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
7145 for (i = 0; i < risc_size; i++)
7146 dcode[i] = le32_to_cpu(dcode[i]);
7147
7148 if (!qla27xx_fwdt_template_valid(dcode)) {
7149 ql_log(ql_log_warn, vha, 0x0165,
7150 "Failed fwdump template validate\n");
7151 goto default_template;
7152 }
7153
7154 dlen = qla27xx_fwdt_template_size(dcode);
7155 ql_dbg(ql_dbg_init, vha, 0x0166,
7156 "-> template size %x bytes\n", dlen);
7157 if (dlen > risc_size * sizeof(*dcode)) {
7158 ql_log(ql_log_warn, vha, 0x0167,
4fae52b5 7159 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7160 (size_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 7161 goto default_template;
7162 }
7163 ha->fw_dump_template_len = dlen;
7164 return rval;
7165
7166default_template:
7167 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
7168 if (ha->fw_dump_template)
7169 vfree(ha->fw_dump_template);
7170 ha->fw_dump_template = NULL;
7171 ha->fw_dump_template_len = 0;
7172
7173 dlen = qla27xx_fwdt_template_default_size();
7174 ql_dbg(ql_dbg_init, vha, 0x0169,
7175 "-> template allocating %x bytes...\n", dlen);
7176 ha->fw_dump_template = vmalloc(dlen);
7177 if (!ha->fw_dump_template) {
7178 ql_log(ql_log_warn, vha, 0x016a,
7179 "Failed fwdump template allocate %x bytes.\n", risc_size);
7180 goto failed_template;
7181 }
7182
7183 dcode = ha->fw_dump_template;
7184 risc_size = dlen / sizeof(*dcode);
7185 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
7186 for (i = 0; i < risc_size; i++)
7187 dcode[i] = be32_to_cpu(dcode[i]);
7188
7189 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7190 ql_log(ql_log_warn, vha, 0x016b,
7191 "Failed fwdump template validate\n");
7192 goto failed_template;
7193 }
7194
7195 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7196 ql_dbg(ql_dbg_init, vha, 0x016c,
7197 "-> template size %x bytes\n", dlen);
7198 ha->fw_dump_template_len = dlen;
7199 return rval;
7200
7201failed_template:
7202 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
7203 if (ha->fw_dump_template)
7204 vfree(ha->fw_dump_template);
7205 ha->fw_dump_template = NULL;
7206 ha->fw_dump_template_len = 0;
d1c61909
AV		 7207 return rval;
7208}
7209
e9454a88 7210#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 7211
0107109e 7212int
e315cd28 7213qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 7214{
7215 int rval;
7216 int i, fragment;
7217 uint16_t *wcode, *fwcode;
7218 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
7219 struct fw_blob *blob;
e315cd28 7220 struct qla_hw_data *ha = vha->hw;
73208dfd 7221 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 7222
7223 /* Load firmware blob. */
e315cd28 7224 blob = qla2x00_request_firmware(vha);
5433383e 7225 if (!blob) {
7c3df132 7226 ql_log(ql_log_info, vha, 0x0083,
94bcf830 7227 "Firmware image unavailable.\n");
7c3df132
SK		 7228 ql_log(ql_log_info, vha, 0x0084,
7229 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 7230 return QLA_FUNCTION_FAILED;
7231 }
7232
7233 rval = QLA_SUCCESS;
7234
73208dfd 7235 wcode = (uint16_t *)req->ring;
5433383e
AV		 7236 *srisc_addr = 0;
7237 fwcode = (uint16_t *)blob->fw->data;
7238 fwclen = 0;
7239
7240 /* Validate firmware image by checking version. */
7241 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 7242 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 7243 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 7244 blob->fw->size);
7245 goto fail_fw_integrity;
7246 }
7247 for (i = 0; i < 4; i++)
7248 wcode[i] = be16_to_cpu(fwcode[i + 4]);
7249 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
7250 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
7251 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 7252 ql_log(ql_log_fatal, vha, 0x0086,
7253 "Unable to verify integrity of firmware image.\n");
7254 ql_log(ql_log_fatal, vha, 0x0087,
7255 "Firmware data: %04x %04x %04x %04x.\n",
7256 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 7257 goto fail_fw_integrity;
7258 }
7259
7260 seg = blob->segs;
7261 while (*seg && rval == QLA_SUCCESS) {
7262 risc_addr = *seg;
7263 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
7264 risc_size = be16_to_cpu(fwcode[3]);
7265
7266 /* Validate firmware image size. */
7267 fwclen += risc_size * sizeof(uint16_t);
7268 if (blob->fw->size < fwclen) {
7c3df132 7269 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 7270 "Unable to verify integrity of firmware image "
5b5e0928 7271 "(%zd).\n", blob->fw->size);
5433383e
AV		 7272 goto fail_fw_integrity;
7273 }
7274
7275 fragment = 0;
7276 while (risc_size > 0 && rval == QLA_SUCCESS) {
7277 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
7278 if (wlen > risc_size)
7279 wlen = risc_size;
7c3df132
SK		 7280 ql_dbg(ql_dbg_init, vha, 0x0089,
7281 "Loading risc segment@ risc addr %x number of "
7282 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 7283
7284 for (i = 0; i < wlen; i++)
7285 wcode[i] = swab16(fwcode[i]);
7286
73208dfd 7287 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 7288 wlen);
7289 if (rval) {
7c3df132
SK		 7290 ql_log(ql_log_fatal, vha, 0x008a,
7291 "Failed to load segment %d of firmware.\n",
7292 fragment);
5433383e
AV		 7293 break;
7294 }
7295
7296 fwcode += wlen;
7297 risc_addr += wlen;
7298 risc_size -= wlen;
7299 fragment++;
7300 }
7301
7302 /* Next segment. */
7303 seg++;
7304 }
7305 return rval;
7306
7307fail_fw_integrity:
7308 return QLA_FUNCTION_FAILED;
7309}
7310
eaac30be
AV		 7311static int
7312qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 7313{
7314 int rval;
7315 int segments, fragment;
7316 uint32_t *dcode, dlen;
7317 uint32_t risc_addr;
7318 uint32_t risc_size;
7319 uint32_t i;
5433383e 7320 struct fw_blob *blob;
f73cb695
CD		 7321 const uint32_t *fwcode;
7322 uint32_t fwclen;
e315cd28 7323 struct qla_hw_data *ha = vha->hw;
73208dfd 7324 struct req_que *req = ha->req_q_map[0];
0107109e 7325
5433383e 7326 /* Load firmware blob. */
e315cd28 7327 blob = qla2x00_request_firmware(vha);
5433383e 7328 if (!blob) {
7c3df132 7329 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 7330 "Firmware image unavailable.\n");
7c3df132
SK		 7331 ql_log(ql_log_warn, vha, 0x0091,
7332 "Firmware images can be retrieved from: "
7333 QLA_FW_URL ".\n");
d1c61909 7334
eaac30be 7335 return QLA_FUNCTION_FAILED;
0107109e
AV		 7336 }
7337
cfb0919c
CD		 7338 ql_dbg(ql_dbg_init, vha, 0x0092,
7339 "FW: Loading via request-firmware.\n");
eaac30be 7340
0107109e
AV		 7341 rval = QLA_SUCCESS;
7342
7343 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7344 dcode = (uint32_t *)req->ring;
0107109e 7345 *srisc_addr = 0;
5433383e 7346 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 7347 fwclen = 0;
7348
7349 /* Validate firmware image by checking version. */
5433383e 7350 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 7351 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 7352 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 7353 blob->fw->size);
f73cb695 7354 return QLA_FUNCTION_FAILED;
0107109e
AV		 7355 }
7356 for (i = 0; i < 4; i++)
7357 dcode[i] = be32_to_cpu(fwcode[i + 4]);
7358 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7359 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7360 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7361 dcode[3] == 0)) {
7c3df132 7362 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 7363 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 7364 blob->fw->size);
7365 ql_log(ql_log_fatal, vha, 0x0095,
7366 "Firmware data: %08x %08x %08x %08x.\n",
7367 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 7368 return QLA_FUNCTION_FAILED;
0107109e
AV		 7369 }
7370
7371 while (segments && rval == QLA_SUCCESS) {
7372 risc_addr = be32_to_cpu(fwcode[2]);
7373 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7374 risc_size = be32_to_cpu(fwcode[3]);
7375
7376 /* Validate firmware image size. */
7377 fwclen += risc_size * sizeof(uint32_t);
5433383e 7378 if (blob->fw->size < fwclen) {
7c3df132 7379 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 7380 "Unable to verify integrity of firmware image "
5b5e0928 7381 "(%zd).\n", blob->fw->size);
f73cb695 7382 return QLA_FUNCTION_FAILED;
0107109e
AV		 7383 }
7384
7385 fragment = 0;
7386 while (risc_size > 0 && rval == QLA_SUCCESS) {
7387 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7388 if (dlen > risc_size)
7389 dlen = risc_size;
7390
7c3df132
SK		 7391 ql_dbg(ql_dbg_init, vha, 0x0097,
7392 "Loading risc segment@ risc addr %x "
7393 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 7394
7395 for (i = 0; i < dlen; i++)
7396 dcode[i] = swab32(fwcode[i]);
7397
73208dfd 7398 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 7399 dlen);
0107109e 7400 if (rval) {
7c3df132
SK		 7401 ql_log(ql_log_fatal, vha, 0x0098,
7402 "Failed to load segment %d of firmware.\n",
7403 fragment);
f261f7af 7404 return QLA_FUNCTION_FAILED;
0107109e
AV		 7405 }
7406
7407 fwcode += dlen;
7408 risc_addr += dlen;
7409 risc_size -= dlen;
7410 fragment++;
7411 }
7412
7413 /* Next segment. */
7414 segments--;
7415 }
f73cb695
CD		 7416
7417 if (!IS_QLA27XX(ha))
7418 return rval;
7419
7420 if (ha->fw_dump_template)
7421 vfree(ha->fw_dump_template);
7422 ha->fw_dump_template = NULL;
7423 ha->fw_dump_template_len = 0;
7424
7425 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 7426 "Loading fwdump template from %x\n",
7427 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 7428 risc_size = be32_to_cpu(fwcode[2]);
7429 ql_dbg(ql_dbg_init, vha, 0x172,
7430 "-> array size %x dwords\n", risc_size);
7431 if (risc_size == 0 || risc_size == ~0)
7432 goto default_template;
7433
7434 dlen = (risc_size - 8) * sizeof(*fwcode);
7435 ql_dbg(ql_dbg_init, vha, 0x0173,
7436 "-> template allocating %x bytes...\n", dlen);
7437 ha->fw_dump_template = vmalloc(dlen);
7438 if (!ha->fw_dump_template) {
7439 ql_log(ql_log_warn, vha, 0x0174,
7440 "Failed fwdump template allocate %x bytes.\n", risc_size);
7441 goto default_template;
7442 }
7443
7444 fwcode += 7;
7445 risc_size -= 8;
7446 dcode = ha->fw_dump_template;
7447 for (i = 0; i < risc_size; i++)
7448 dcode[i] = le32_to_cpu(fwcode[i]);
7449
7450 if (!qla27xx_fwdt_template_valid(dcode)) {
7451 ql_log(ql_log_warn, vha, 0x0175,
7452 "Failed fwdump template validate\n");
7453 goto default_template;
7454 }
7455
7456 dlen = qla27xx_fwdt_template_size(dcode);
7457 ql_dbg(ql_dbg_init, vha, 0x0176,
7458 "-> template size %x bytes\n", dlen);
7459 if (dlen > risc_size * sizeof(*fwcode)) {
7460 ql_log(ql_log_warn, vha, 0x0177,
4fae52b5 7461 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7462 (size_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 7463 goto default_template;
7464 }
7465 ha->fw_dump_template_len = dlen;
0107109e
AV		 7466 return rval;
7467
f73cb695
CD		 7468default_template:
7469 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
7470 if (ha->fw_dump_template)
7471 vfree(ha->fw_dump_template);
7472 ha->fw_dump_template = NULL;
7473 ha->fw_dump_template_len = 0;
7474
7475 dlen = qla27xx_fwdt_template_default_size();
7476 ql_dbg(ql_dbg_init, vha, 0x0179,
7477 "-> template allocating %x bytes...\n", dlen);
7478 ha->fw_dump_template = vmalloc(dlen);
7479 if (!ha->fw_dump_template) {
7480 ql_log(ql_log_warn, vha, 0x017a,
7481 "Failed fwdump template allocate %x bytes.\n", risc_size);
7482 goto failed_template;
7483 }
7484
7485 dcode = ha->fw_dump_template;
7486 risc_size = dlen / sizeof(*fwcode);
7487 fwcode = qla27xx_fwdt_template_default();
7488 for (i = 0; i < risc_size; i++)
7489 dcode[i] = be32_to_cpu(fwcode[i]);
7490
7491 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7492 ql_log(ql_log_warn, vha, 0x017b,
7493 "Failed fwdump template validate\n");
7494 goto failed_template;
7495 }
7496
7497 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7498 ql_dbg(ql_dbg_init, vha, 0x017c,
7499 "-> template size %x bytes\n", dlen);
7500 ha->fw_dump_template_len = dlen;
7501 return rval;
7502
7503failed_template:
7504 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
7505 if (ha->fw_dump_template)
7506 vfree(ha->fw_dump_template);
7507 ha->fw_dump_template = NULL;
7508 ha->fw_dump_template_len = 0;
7509 return rval;
0107109e 7510}
18c6c127 7511
eaac30be
AV		 7512int
7513qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7514{
7515 int rval;
7516
e337d907
AV		 7517 if (ql2xfwloadbin == 1)
7518 return qla81xx_load_risc(vha, srisc_addr);
7519
eaac30be
AV		 7520 /*
7521 * FW Load priority:
7522 * 1) Firmware via request-firmware interface (.bin file).
7523 * 2) Firmware residing in flash.
7524 */
7525 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7526 if (rval == QLA_SUCCESS)
7527 return rval;
7528
cbc8eb67
AV		 7529 return qla24xx_load_risc_flash(vha, srisc_addr,
7530 vha->hw->flt_region_fw);
eaac30be
AV		 7531}
7532
7533int
7534qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7535{
7536 int rval;
cbc8eb67 7537 struct qla_hw_data *ha = vha->hw;
eaac30be 7538
e337d907 7539 if (ql2xfwloadbin == 2)
cbc8eb67 7540 goto try_blob_fw;
e337d907 7541
eaac30be
AV		 7542 /*
7543 * FW Load priority:
7544 * 1) Firmware residing in flash.
7545 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 7546 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 7547 */
cbc8eb67 7548 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 7549 if (rval == QLA_SUCCESS)
7550 return rval;
7551
cbc8eb67
AV		 7552try_blob_fw:
7553 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7554 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
7555 return rval;
7556
7c3df132
SK		 7557 ql_log(ql_log_info, vha, 0x0099,
7558 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 7559 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
7560 if (rval != QLA_SUCCESS)
7561 return rval;
7562
7c3df132 7563 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 7564 ha->flags.running_gold_fw = 1;
cbc8eb67 7565 return rval;
eaac30be
AV		 7566}
7567
18c6c127 7568void
e315cd28 7569qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 7570{
7571 int ret, retries;
e315cd28 7572 struct qla_hw_data *ha = vha->hw;
18c6c127 7573
85880801
AV		 7574 if (ha->flags.pci_channel_io_perm_failure)
7575 return;
e428924c 7576 if (!IS_FWI2_CAPABLE(ha))
18c6c127 7577 return;
75edf81d
AV		 7578 if (!ha->fw_major_version)
7579 return;
ec7193e2
QT		 7580 if (!ha->flags.fw_started)
7581 return;
18c6c127 7582
e315cd28 7583 ret = qla2x00_stop_firmware(vha);
7c7f1f29 7584 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 7585 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 7586 ha->isp_ops->reset_chip(vha);
7587 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 7588 continue;
e315cd28 7589 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 7590 continue;
7c3df132
SK		 7591 ql_log(ql_log_info, vha, 0x8015,
7592 "Attempting retry of stop-firmware command.\n");
e315cd28 7593 ret = qla2x00_stop_firmware(vha);
18c6c127 7594 }
ec7193e2 7595
4b60c827 7596 QLA_FW_STOPPED(ha);
ec7193e2 7597 ha->flags.fw_init_done = 0;
18c6c127 7598}
2c3dfe3f
SJ		 7599
7600int
e315cd28 7601qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 7602{
7603 int rval = QLA_SUCCESS;
0b91d116 7604 int rval2;
2c3dfe3f 7605 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 7606 struct qla_hw_data *ha = vha->hw;
7607 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 7608 struct req_que *req;
7609 struct rsp_que *rsp;
2c3dfe3f 7610
e315cd28 7611 if (!vha->vp_idx)
2c3dfe3f
SJ		 7612 return -EINVAL;
7613
e315cd28 7614 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 7615 if (vha->qpair)
7616 req = vha->qpair->req;
67c2e93a 7617 else
d7459527 7618 req = ha->req_q_map[0];
67c2e93a
AC		 7619 rsp = req->rsp;
7620
2c3dfe3f 7621 if (rval == QLA_SUCCESS) {
e315cd28 7622 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 7623 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 7624 }
7625
e315cd28 7626 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 7627
7628 /* Login to SNS first */
0b91d116
CD		 7629 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
7630 BIT_1);
7631 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
7632 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
7633 ql_dbg(ql_dbg_init, vha, 0x0120,
7634 "Failed SNS login: loop_id=%x, rval2=%d\n",
7635 NPH_SNS, rval2);
7636 else
7637 ql_dbg(ql_dbg_init, vha, 0x0103,
7638 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
7639 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
7640 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 7641 return (QLA_FUNCTION_FAILED);
7642 }
7643
e315cd28
AC		 7644 atomic_set(&vha->loop_down_timer, 0);
7645 atomic_set(&vha->loop_state, LOOP_UP);
7646 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7647 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
7648 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 7649
7650 return rval;
7651}
4d4df193
HK		 7652
7653/* 84XX Support **************************************************************/
7654
7655static LIST_HEAD(qla_cs84xx_list);
7656static DEFINE_MUTEX(qla_cs84xx_mutex);
7657
7658static struct qla_chip_state_84xx *
e315cd28 7659qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 7660{
7661 struct qla_chip_state_84xx *cs84xx;
e315cd28 7662 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7663
7664 mutex_lock(&qla_cs84xx_mutex);
7665
7666 /* Find any shared 84xx chip. */
7667 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
7668 if (cs84xx->bus == ha->pdev->bus) {
7669 kref_get(&cs84xx->kref);
7670 goto done;
7671 }
7672 }
7673
7674 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
7675 if (!cs84xx)
7676 goto done;
7677
7678 kref_init(&cs84xx->kref);
7679 spin_lock_init(&cs84xx->access_lock);
7680 mutex_init(&cs84xx->fw_update_mutex);
7681 cs84xx->bus = ha->pdev->bus;
7682
7683 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
7684done:
7685 mutex_unlock(&qla_cs84xx_mutex);
7686 return cs84xx;
7687}
7688
7689static void
7690__qla84xx_chip_release(struct kref *kref)
7691{
7692 struct qla_chip_state_84xx *cs84xx =
7693 container_of(kref, struct qla_chip_state_84xx, kref);
7694
7695 mutex_lock(&qla_cs84xx_mutex);
7696 list_del(&cs84xx->list);
7697 mutex_unlock(&qla_cs84xx_mutex);
7698 kfree(cs84xx);
7699}
7700
7701void
e315cd28 7702qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 7703{
e315cd28 7704 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7705 if (ha->cs84xx)
7706 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
7707}
7708
7709static int
e315cd28 7710qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 7711{
7712 int rval;
7713 uint16_t status[2];
e315cd28 7714 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7715
7716 mutex_lock(&ha->cs84xx->fw_update_mutex);
7717
e315cd28 7718 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 7719
7720 mutex_unlock(&ha->cs84xx->fw_update_mutex);
7721
7722 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
7723 QLA_SUCCESS;
7724}
3a03eb79
AV		 7725
7726/* 81XX Support **************************************************************/
7727
7728int
7729qla81xx_nvram_config(scsi_qla_host_t *vha)
7730{
7731 int rval;
7732 struct init_cb_81xx *icb;
7733 struct nvram_81xx *nv;
7734 uint32_t *dptr;
7735 uint8_t *dptr1, *dptr2;
7736 uint32_t chksum;
7737 uint16_t cnt;
7738 struct qla_hw_data *ha = vha->hw;
7739
7740 rval = QLA_SUCCESS;
7741 icb = (struct init_cb_81xx *)ha->init_cb;
7742 nv = ha->nvram;
7743
7744 /* Determine NVRAM starting address. */
7745 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 7746 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 7747 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
7748 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 7749
7750 /* Get VPD data into cache */
7751 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 7752 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
7753 ha->vpd_size);
3a03eb79
AV		 7754
7755 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 7756 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 7757 ha->nvram_size);
3d79038f 7758 dptr = (uint32_t *)nv;
da08ef5c
JC		 7759 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7760 chksum += le32_to_cpu(*dptr);
3a03eb79 7761
7c3df132
SK		 7762 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
7763 "Contents of NVRAM:\n");
7764 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
7765 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 7766
7767 /* Bad NVRAM data, set defaults parameters. */
7768 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
7769 || nv->id[3] != ' ' ||
ad950360 7770 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 7771 /* Reset NVRAM data. */
7c3df132 7772 ql_log(ql_log_info, vha, 0x0073,
9e336520 7773 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 7774 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 7775 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 7776 ql_log(ql_log_info, vha, 0x0074,
7777 "Falling back to functioning (yet invalid -- WWPN) "
7778 "defaults.\n");
3a03eb79
AV		 7779
7780 /*
7781 * Set default initialization control block.
7782 */
7783 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 7784 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7785 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7786 nv->frame_payload_size = 2048;
ad950360
BVA		 7787 nv->execution_throttle = cpu_to_le16(0xFFFF);
7788 nv->exchange_count = cpu_to_le16(0);
3a03eb79 7789 nv->port_name[0] = 0x21;
f73cb695 7790 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 7791 nv->port_name[2] = 0x00;
7792 nv->port_name[3] = 0xe0;
7793 nv->port_name[4] = 0x8b;
7794 nv->port_name[5] = 0x1c;
7795 nv->port_name[6] = 0x55;
7796 nv->port_name[7] = 0x86;
7797 nv->node_name[0] = 0x20;
7798 nv->node_name[1] = 0x00;
7799 nv->node_name[2] = 0x00;
7800 nv->node_name[3] = 0xe0;
7801 nv->node_name[4] = 0x8b;
7802 nv->node_name[5] = 0x1c;
7803 nv->node_name[6] = 0x55;
7804 nv->node_name[7] = 0x86;
ad950360
BVA		 7805 nv->login_retry_count = cpu_to_le16(8);
7806 nv->interrupt_delay_timer = cpu_to_le16(0);
7807 nv->login_timeout = cpu_to_le16(0);
3a03eb79 7808 nv->firmware_options_1 =
ad950360
BVA		 7809 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7810 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7811 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7812 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7813 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7814 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 7815 nv->reset_delay = 5;
ad950360
BVA		 7816 nv->max_luns_per_target = cpu_to_le16(128);
7817 nv->port_down_retry_count = cpu_to_le16(30);
7818 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 7819 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 7820 nv->enode_mac[1] = 0xC0;
7821 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 7822 nv->enode_mac[3] = 0x04;
7823 nv->enode_mac[4] = 0x05;
f73cb695 7824 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7825
7826 rval = 1;
7827 }
7828
9e522cd8
AE		 7829 if (IS_T10_PI_CAPABLE(ha))
7830 nv->frame_payload_size &= ~7;
7831
aa230bc5
AE		 7832 qlt_81xx_config_nvram_stage1(vha, nv);
7833
3a03eb79 7834 /* Reset Initialization control block */
773120e4 7835 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 7836
7837 /* Copy 1st segment. */
7838 dptr1 = (uint8_t *)icb;
7839 dptr2 = (uint8_t *)&nv->version;
7840 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7841 while (cnt--)
7842 *dptr1++ = *dptr2++;
7843
7844 icb->login_retry_count = nv->login_retry_count;
7845
7846 /* Copy 2nd segment. */
7847 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7848 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7849 cnt = (uint8_t *)&icb->reserved_5 -
7850 (uint8_t *)&icb->interrupt_delay_timer;
7851 while (cnt--)
7852 *dptr1++ = *dptr2++;
7853
7854 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
7855 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
7856 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 7857 icb->enode_mac[0] = 0x00;
7858 icb->enode_mac[1] = 0xC0;
7859 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 7860 icb->enode_mac[3] = 0x04;
7861 icb->enode_mac[4] = 0x05;
f73cb695 7862 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7863 }
7864
b64b0e8f
AV		 7865 /* Use extended-initialization control block. */
7866 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
7867
3a03eb79
AV		 7868 /*
7869 * Setup driver NVRAM options.
7870 */
7871 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 7872 "QLE8XXX");
3a03eb79 7873
aa230bc5
AE		 7874 qlt_81xx_config_nvram_stage2(vha, icb);
7875
3a03eb79 7876 /* Use alternate WWN? */
ad950360 7877 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 7878 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7879 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7880 }
7881
7882 /* Prepare nodename */
ad950360 7883 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 7884 /*
7885 * Firmware will apply the following mask if the nodename was
7886 * not provided.
7887 */
7888 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7889 icb->node_name[0] &= 0xF0;
7890 }
7891
7892 /* Set host adapter parameters. */
7893 ha->flags.disable_risc_code_load = 0;
7894 ha->flags.enable_lip_reset = 0;
7895 ha->flags.enable_lip_full_login =
7896 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7897 ha->flags.enable_target_reset =
7898 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
7899 ha->flags.enable_led_scheme = 0;
7900 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
7901
7902 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7903 (BIT_6 | BIT_5 | BIT_4)) >> 4;
7904
7905 /* save HBA serial number */
7906 ha->serial0 = icb->port_name[5];
7907 ha->serial1 = icb->port_name[6];
7908 ha->serial2 = icb->port_name[7];
7909 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7910 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7911
ad950360 7912 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 7913
7914 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7915
7916 /* Set minimum login_timeout to 4 seconds. */
7917 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7918 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7919 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7920 nv->login_timeout = cpu_to_le16(4);
3a03eb79 7921 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 7922
7923 /* Set minimum RATOV to 100 tenths of a second. */
7924 ha->r_a_tov = 100;
7925
7926 ha->loop_reset_delay = nv->reset_delay;
7927
7928 /* Link Down Timeout = 0:
7929 *
7ec0effd 7930 * When Port Down timer expires we will start returning
3a03eb79
AV		 7931 * I/O's to OS with "DID_NO_CONNECT".
7932 *
7933 * Link Down Timeout != 0:
7934 *
7935 * The driver waits for the link to come up after link down
7936 * before returning I/Os to OS with "DID_NO_CONNECT".
7937 */
7938 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7939 ha->loop_down_abort_time =
7940 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7941 } else {
7942 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7943 ha->loop_down_abort_time =
7944 (LOOP_DOWN_TIME - ha->link_down_timeout);
7945 }
7946
7947 /* Need enough time to try and get the port back. */
7948 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7949 if (qlport_down_retry)
7950 ha->port_down_retry_count = qlport_down_retry;
7951
7952 /* Set login_retry_count */
7953 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7954 if (ha->port_down_retry_count ==
7955 le16_to_cpu(nv->port_down_retry_count) &&
7956 ha->port_down_retry_count > 3)
7957 ha->login_retry_count = ha->port_down_retry_count;
7958 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7959 ha->login_retry_count = ha->port_down_retry_count;
7960 if (ql2xloginretrycount)
7961 ha->login_retry_count = ql2xloginretrycount;
7962
6246b8a1 7963 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 7964 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 7965 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 7966
3a03eb79
AV		 7967 /* Enable ZIO. */
7968 if (!vha->flags.init_done) {
7969 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7970 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7971 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7972 le16_to_cpu(icb->interrupt_delay_timer): 2;
7973 }
ad950360 7974 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 7975 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
7976 vha->flags.process_response_queue = 0;
7977 if (ha->zio_mode != QLA_ZIO_DISABLED) {
7978 ha->zio_mode = QLA_ZIO_MODE_6;
7979
7c3df132 7980 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 7981 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 7982 ha->zio_mode,
7983 ha->zio_timer * 100);
3a03eb79
AV		 7984
7985 icb->firmware_options_2 |= cpu_to_le32(
7986 (uint32_t)ha->zio_mode);
7987 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
7988 vha->flags.process_response_queue = 1;
7989 }
7990
41dc529a
QT		 7991 /* enable RIDA Format2 */
7992 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha))
7993 icb->firmware_options_3 |= BIT_0;
7994
edd05de1
DG		 7995 if (IS_QLA27XX(ha)) {
7996 icb->firmware_options_3 |= BIT_8;
7997 ql_dbg(ql_log_info, vha, 0x0075,
7998 "Enabling direct connection.\n");
7999 }
8000
3a03eb79 8001 if (rval) {
7c3df132
SK		 8002 ql_log(ql_log_warn, vha, 0x0076,
8003 "NVRAM configuration failed.\n");
3a03eb79
AV		 8004 }
8005 return (rval);
8006}
8007
a9083016
GM		 8008int
8009qla82xx_restart_isp(scsi_qla_host_t *vha)
8010{
8011 int status, rval;
a9083016
GM		 8012 struct qla_hw_data *ha = vha->hw;
8013 struct req_que *req = ha->req_q_map[0];
8014 struct rsp_que *rsp = ha->rsp_q_map[0];
8015 struct scsi_qla_host *vp;
feafb7b1 8016 unsigned long flags;
a9083016
GM		 8017
8018 status = qla2x00_init_rings(vha);
8019 if (!status) {
8020 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8021 ha->flags.chip_reset_done = 1;
8022
8023 status = qla2x00_fw_ready(vha);
8024 if (!status) {
a9083016
GM		 8025 /* Issue a marker after FW becomes ready. */
8026 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 8027 vha->flags.online = 1;
7108b76e 8028 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 8029 }
8030
8031 /* if no cable then assume it's good */
8032 if ((vha->device_flags & DFLG_NO_CABLE))
8033 status = 0;
a9083016
GM		 8034 }
8035
8036 if (!status) {
8037 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8038
8039 if (!atomic_read(&vha->loop_down_timer)) {
8040 /*
8041 * Issue marker command only when we are going
8042 * to start the I/O .
8043 */
8044 vha->marker_needed = 1;
8045 }
8046
a9083016
GM		 8047 ha->isp_ops->enable_intrs(ha);
8048
8049 ha->isp_abort_cnt = 0;
8050 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
8051
53296788 8052 /* Update the firmware version */
3173167f 8053 status = qla82xx_check_md_needed(vha);
53296788 8054
a9083016
GM		 8055 if (ha->fce) {
8056 ha->flags.fce_enabled = 1;
8057 memset(ha->fce, 0,
8058 fce_calc_size(ha->fce_bufs));
8059 rval = qla2x00_enable_fce_trace(vha,
8060 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
8061 &ha->fce_bufs);
8062 if (rval) {
cfb0919c 8063 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 8064 "Unable to reinitialize FCE (%d).\n",
8065 rval);
a9083016
GM		 8066 ha->flags.fce_enabled = 0;
8067 }
8068 }
8069
8070 if (ha->eft) {
8071 memset(ha->eft, 0, EFT_SIZE);
8072 rval = qla2x00_enable_eft_trace(vha,
8073 ha->eft_dma, EFT_NUM_BUFFERS);
8074 if (rval) {
cfb0919c 8075 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 8076 "Unable to reinitialize EFT (%d).\n",
8077 rval);
a9083016
GM		 8078 }
8079 }
a9083016
GM		 8080 }
8081
8082 if (!status) {
cfb0919c 8083 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 8084 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 8085
8086 spin_lock_irqsave(&ha->vport_slock, flags);
8087 list_for_each_entry(vp, &ha->vp_list, list) {
8088 if (vp->vp_idx) {
8089 atomic_inc(&vp->vref_count);
8090 spin_unlock_irqrestore(&ha->vport_slock, flags);
8091
a9083016 8092 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 8093
8094 spin_lock_irqsave(&ha->vport_slock, flags);
8095 atomic_dec(&vp->vref_count);
8096 }
a9083016 8097 }
feafb7b1
AE		 8098 spin_unlock_irqrestore(&ha->vport_slock, flags);
8099
a9083016 8100 } else {
cfb0919c 8101 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 8102 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 8103 }
8104
8105 return status;
8106}
8107
3a03eb79 8108void
ae97c91e 8109qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 8110{
ae97c91e
AV		 8111 struct qla_hw_data *ha = vha->hw;
8112
f198cafa
HM		 8113 /* Hold status IOCBs until ABTS response received. */
8114 if (ql2xfwholdabts)
8115 ha->fw_options[3] |= BIT_12;
8116
088d09d4
GM		 8117 /* Set Retry FLOGI in case of P2P connection */
8118 if (ha->operating_mode == P2P) {
8119 ha->fw_options[2] |= BIT_3;
8120 ql_dbg(ql_dbg_disc, vha, 0x2103,
8121 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
8122 __func__, ha->fw_options[2]);
8123 }
8124
41dc529a
QT		 8125 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
8126 if (ql2xmvasynctoatio) {
8127 if (qla_tgt_mode_enabled(vha) ||
8128 qla_dual_mode_enabled(vha))
8129 ha->fw_options[2] |= BIT_11;
8130 else
8131 ha->fw_options[2] &= ~BIT_11;
8132 }
8133
f7e761f5 8134 if (qla_tgt_mode_enabled(vha) ||
2da52737
QT		 8135 qla_dual_mode_enabled(vha)) {
8136 /* FW auto send SCSI status during */
8137 ha->fw_options[1] |= BIT_8;
8138 ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
8139
8140 /* FW perform Exchange validation */
f7e761f5 8141 ha->fw_options[2] |= BIT_4;
2da52737
QT		 8142 } else {
8143 ha->fw_options[1] &= ~BIT_8;
8144 ha->fw_options[10] &= 0x00ff;
8145
f7e761f5 8146 ha->fw_options[2] &= ~BIT_4;
2da52737 8147 }
f7e761f5 8148
41dc529a
QT		 8149 if (ql2xetsenable) {
8150 /* Enable ETS Burst. */
8151 memset(ha->fw_options, 0, sizeof(ha->fw_options));
8152 ha->fw_options[2] |= BIT_9;
8153 }
8154
83548fe2
QT		 8155 ql_dbg(ql_dbg_init, vha, 0x00e9,
8156 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
8157 __func__, ha->fw_options[1], ha->fw_options[2],
8158 ha->fw_options[3], vha->host->active_mode);
ae97c91e 8159
ae97c91e 8160 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 8161}
09ff701a
SR		 8162
8163/*
8164 * qla24xx_get_fcp_prio
8165 * Gets the fcp cmd priority value for the logged in port.
8166 * Looks for a match of the port descriptors within
8167 * each of the fcp prio config entries. If a match is found,
8168 * the tag (priority) value is returned.
8169 *
8170 * Input:
21090cbe 8171 * vha = scsi host structure pointer.
09ff701a
SR		 8172 * fcport = port structure pointer.
8173 *
8174 * Return:
6c452a45 8175 * non-zero (if found)
f28a0a96 8176 * -1 (if not found)
09ff701a
SR		 8177 *
8178 * Context:
8179 * Kernel context
8180 */
f28a0a96 8181static int
09ff701a
SR		 8182qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
8183{
8184 int i, entries;
8185 uint8_t pid_match, wwn_match;
f28a0a96 8186 int priority;
09ff701a
SR		 8187 uint32_t pid1, pid2;
8188 uint64_t wwn1, wwn2;
8189 struct qla_fcp_prio_entry *pri_entry;
8190 struct qla_hw_data *ha = vha->hw;
8191
8192 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 8193 return -1;
09ff701a 8194
f28a0a96 8195 priority = -1;
09ff701a
SR		 8196 entries = ha->fcp_prio_cfg->num_entries;
8197 pri_entry = &ha->fcp_prio_cfg->entry[0];
8198
8199 for (i = 0; i < entries; i++) {
8200 pid_match = wwn_match = 0;
8201
8202 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
8203 pri_entry++;
8204 continue;
8205 }
8206
8207 /* check source pid for a match */
8208 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
8209 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
8210 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
8211 if (pid1 == INVALID_PORT_ID)
8212 pid_match++;
8213 else if (pid1 == pid2)
8214 pid_match++;
8215 }
8216
8217 /* check destination pid for a match */
8218 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
8219 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
8220 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
8221 if (pid1 == INVALID_PORT_ID)
8222 pid_match++;
8223 else if (pid1 == pid2)
8224 pid_match++;
8225 }
8226
8227 /* check source WWN for a match */
8228 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
8229 wwn1 = wwn_to_u64(vha->port_name);
8230 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
8231 if (wwn2 == (uint64_t)-1)
8232 wwn_match++;
8233 else if (wwn1 == wwn2)
8234 wwn_match++;
8235 }
8236
8237 /* check destination WWN for a match */
8238 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
8239 wwn1 = wwn_to_u64(fcport->port_name);
8240 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
8241 if (wwn2 == (uint64_t)-1)
8242 wwn_match++;
8243 else if (wwn1 == wwn2)
8244 wwn_match++;
8245 }
8246
8247 if (pid_match == 2 || wwn_match == 2) {
8248 /* Found a matching entry */
8249 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
8250 priority = pri_entry->tag;
8251 break;
8252 }
8253
8254 pri_entry++;
8255 }
8256
8257 return priority;
8258}
8259
8260/*
8261 * qla24xx_update_fcport_fcp_prio
8262 * Activates fcp priority for the logged in fc port
8263 *
8264 * Input:
21090cbe 8265 * vha = scsi host structure pointer.
09ff701a
SR		 8266 * fcp = port structure pointer.
8267 *
8268 * Return:
8269 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8270 *
8271 * Context:
8272 * Kernel context.
8273 */
8274int
21090cbe 8275qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 8276{
8277 int ret;
f28a0a96 8278 int priority;
09ff701a
SR		 8279 uint16_t mb[5];
8280
21090cbe
MI		 8281 if (fcport->port_type != FCT_TARGET ||
8282 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 8283 return QLA_FUNCTION_FAILED;
8284
21090cbe 8285 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 8286 if (priority < 0)
8287 return QLA_FUNCTION_FAILED;
8288
7ec0effd 8289 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 8290 fcport->fcp_prio = priority & 0xf;
8291 return QLA_SUCCESS;
8292 }
8293
21090cbe 8294 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 8295 if (ret == QLA_SUCCESS) {
8296 if (fcport->fcp_prio != priority)
8297 ql_dbg(ql_dbg_user, vha, 0x709e,
8298 "Updated FCP_CMND priority - value=%d loop_id=%d "
8299 "port_id=%02x%02x%02x.\n", priority,
8300 fcport->loop_id, fcport->d_id.b.domain,
8301 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 8302 fcport->fcp_prio = priority & 0xf;
cfb0919c 8303 } else
7c3df132 8304 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 8305 "Unable to update FCP_CMND priority - ret=0x%x for "
8306 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
8307 fcport->d_id.b.domain, fcport->d_id.b.area,
8308 fcport->d_id.b.al_pa);
09ff701a
SR		 8309 return ret;
8310}
8311
8312/*
8313 * qla24xx_update_all_fcp_prio
8314 * Activates fcp priority for all the logged in ports
8315 *
8316 * Input:
8317 * ha = adapter block pointer.
8318 *
8319 * Return:
8320 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8321 *
8322 * Context:
8323 * Kernel context.
8324 */
8325int
8326qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
8327{
8328 int ret;
8329 fc_port_t *fcport;
8330
8331 ret = QLA_FUNCTION_FAILED;
8332 /* We need to set priority for all logged in ports */
8333 list_for_each_entry(fcport, &vha->vp_fcports, list)
8334 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
8335
8336 return ret;
8337}
d7459527 8338
82de802a
QT		 8339struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
8340 int vp_idx, bool startqp)
d7459527
MH		 8341{
8342 int rsp_id = 0;
8343 int req_id = 0;
8344 int i;
8345 struct qla_hw_data *ha = vha->hw;
8346 uint16_t qpair_id = 0;
8347 struct qla_qpair *qpair = NULL;
8348 struct qla_msix_entry *msix;
8349
8350 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
8351 ql_log(ql_log_warn, vha, 0x00181,
8352 "FW/Driver is not multi-queue capable.\n");
8353 return NULL;
8354 }
8355
c38d1baf 8356 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 8357 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
8358 if (qpair == NULL) {
8359 ql_log(ql_log_warn, vha, 0x0182,
8360 "Failed to allocate memory for queue pair.\n");
8361 return NULL;
8362 }
8363 memset(qpair, 0, sizeof(struct qla_qpair));
8364
8365 qpair->hw = vha->hw;
25ff6af1 8366 qpair->vha = vha;
82de802a
QT		 8367 qpair->qp_lock_ptr = &qpair->qp_lock;
8368 spin_lock_init(&qpair->qp_lock);
af7bb382 8369 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d7459527
MH		 8370
8371 /* Assign available que pair id */
8372 mutex_lock(&ha->mq_lock);
8373 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 8374 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 8375 mutex_unlock(&ha->mq_lock);
8376 ql_log(ql_log_warn, vha, 0x0183,
8377 "No resources to create additional q pair.\n");
8378 goto fail_qid_map;
8379 }
b95b9452 8380 ha->num_qpairs++;
d7459527
MH		 8381 set_bit(qpair_id, ha->qpair_qid_map);
8382 ha->queue_pair_map[qpair_id] = qpair;
8383 qpair->id = qpair_id;
8384 qpair->vp_idx = vp_idx;
e6373f33 8385 qpair->fw_started = ha->flags.fw_started;
e326d22a 8386 INIT_LIST_HEAD(&qpair->hints_list);
cf19c45d 8387 INIT_LIST_HEAD(&qpair->nvme_done_list);
7c3f8fd1
QT		 8388 qpair->chip_reset = ha->base_qpair->chip_reset;
8389 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
8390 qpair->enable_explicit_conf =
8391 ha->base_qpair->enable_explicit_conf;
d7459527
MH		 8392
8393 for (i = 0; i < ha->msix_count; i++) {
093df737 8394 msix = &ha->msix_entries[i];
d7459527
MH		 8395 if (msix->in_use)
8396 continue;
8397 qpair->msix = msix;
83548fe2 8398 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
d7459527
MH		 8399 "Vector %x selected for qpair\n", msix->vector);
8400 break;
8401 }
8402 if (!qpair->msix) {
8403 ql_log(ql_log_warn, vha, 0x0184,
8404 "Out of MSI-X vectors!.\n");
8405 goto fail_msix;
8406 }
8407
8408 qpair->msix->in_use = 1;
8409 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
8abfa9e2
QT		 8410 qpair->pdev = ha->pdev;
8411 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
8412 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
d7459527
MH		 8413
8414 mutex_unlock(&ha->mq_lock);
8415
8416 /* Create response queue first */
82de802a 8417 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
d7459527
MH		 8418 if (!rsp_id) {
8419 ql_log(ql_log_warn, vha, 0x0185,
8420 "Failed to create response queue.\n");
8421 goto fail_rsp;
8422 }
8423
8424 qpair->rsp = ha->rsp_q_map[rsp_id];
8425
8426 /* Create request queue */
82de802a
QT		 8427 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
8428 startqp);
d7459527
MH		 8429 if (!req_id) {
8430 ql_log(ql_log_warn, vha, 0x0186,
8431 "Failed to create request queue.\n");
8432 goto fail_req;
8433 }
8434
8435 qpair->req = ha->req_q_map[req_id];
8436 qpair->rsp->req = qpair->req;
82de802a 8437 qpair->rsp->qpair = qpair;
e326d22a
QT		 8438 /* init qpair to this cpu. Will adjust at run time. */
8439 qla_cpu_update(qpair, smp_processor_id());
d7459527
MH		 8440
8441 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
8442 if (ha->fw_attributes & BIT_4)
8443 qpair->difdix_supported = 1;
8444 }
8445
8446 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
8447 if (!qpair->srb_mempool) {
83548fe2 8448 ql_log(ql_log_warn, vha, 0xd036,
d7459527
MH		 8449 "Failed to create srb mempool for qpair %d\n",
8450 qpair->id);
8451 goto fail_mempool;
8452 }
8453
8454 /* Mark as online */
8455 qpair->online = 1;
8456
8457 if (!vha->flags.qpairs_available)
8458 vha->flags.qpairs_available = 1;
8459
8460 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
8461 "Request/Response queue pair created, id %d\n",
8462 qpair->id);
8463 ql_dbg(ql_dbg_init, vha, 0x0187,
8464 "Request/Response queue pair created, id %d\n",
8465 qpair->id);
8466 }
8467 return qpair;
8468
8469fail_mempool:
8470fail_req:
8471 qla25xx_delete_rsp_que(vha, qpair->rsp);
8472fail_rsp:
8473 mutex_lock(&ha->mq_lock);
8474 qpair->msix->in_use = 0;
8475 list_del(&qpair->qp_list_elem);
8476 if (list_empty(&vha->qp_list))
8477 vha->flags.qpairs_available = 0;
8478fail_msix:
8479 ha->queue_pair_map[qpair_id] = NULL;
8480 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 8481 ha->num_qpairs--;
d7459527
MH		 8482 mutex_unlock(&ha->mq_lock);
8483fail_qid_map:
8484 kfree(qpair);
8485 return NULL;
8486}
8487
8488int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
8489{
d65237c7 8490 int ret = QLA_FUNCTION_FAILED;
d7459527
MH		 8491 struct qla_hw_data *ha = qpair->hw;
8492
8493 qpair->delete_in_progress = 1;
8494 while (atomic_read(&qpair->ref_count))
8495 msleep(500);
8496
8497 ret = qla25xx_delete_req_que(vha, qpair->req);
8498 if (ret != QLA_SUCCESS)
8499 goto fail;
7867b98d 8500
d7459527
MH		 8501 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
8502 if (ret != QLA_SUCCESS)
8503 goto fail;
8504
8505 mutex_lock(&ha->mq_lock);
8506 ha->queue_pair_map[qpair->id] = NULL;
8507 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 8508 ha->num_qpairs--;
d7459527 8509 list_del(&qpair->qp_list_elem);
d65237c7 8510 if (list_empty(&vha->qp_list)) {
d7459527 8511 vha->flags.qpairs_available = 0;
d65237c7
SC		 8512 vha->flags.qpairs_req_created = 0;
8513 vha->flags.qpairs_rsp_created = 0;
8514 }
d7459527
MH		 8515 mempool_destroy(qpair->srb_mempool);
8516 kfree(qpair);
8517 mutex_unlock(&ha->mq_lock);
8518
8519 return QLA_SUCCESS;
8520fail:
8521 return ret;
8522}
Linux 6.x block layer and io_uring tree(s)