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scsi: qla2xxx: Fix warning for code intentation in __qla24xx_handle_gpdb_event()
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
a5d42f4c 39static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
726b8548
QT		 40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
a5d42f4c
DG		 42static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
43 struct event_arg *);
a4239945 44static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
4d4df193 45
ac280b67
AV		 46/* SRB Extensions ---------------------------------------------------------- */
47
9ba56b95 48void
8e5f4ba0 49qla2x00_sp_timeout(struct timer_list *t)
ac280b67 50{
8e5f4ba0 51 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
4916392b 52 struct srb_iocb *iocb;
25ff6af1 53 scsi_qla_host_t *vha = sp->vha;
ac280b67
AV		 54 struct req_que *req;
55 unsigned long flags;
56
25ff6af1
JC		 57 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
58 req = vha->hw->req_q_map[0];
ac280b67 59 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 60 iocb = &sp->u.iocb_cmd;
4916392b 61 iocb->timeout(sp);
045d6ea2
GM		 62 if (sp->type != SRB_ELS_DCMD)
63 sp->free(sp);
25ff6af1 64 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
ac280b67
AV		 65}
66
9ba56b95 67void
25ff6af1 68qla2x00_sp_free(void *ptr)
ac280b67 69{
25ff6af1 70 srb_t *sp = ptr;
9ba56b95 71 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 72
4d97cc53 73 del_timer(&iocb->timer);
25ff6af1 74 qla2x00_rel_sp(sp);
ac280b67
AV		 75}
76
ac280b67
AV		 77/* Asynchronous Login/Logout Routines -------------------------------------- */
78
a9b6f722 79unsigned long
5b91490e
AV		 80qla2x00_get_async_timeout(struct scsi_qla_host *vha)
81{
82 unsigned long tmo;
83 struct qla_hw_data *ha = vha->hw;
84
85 /* Firmware should use switch negotiated r_a_tov for timeout. */
86 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 87 if (IS_QLAFX00(ha)) {
88 tmo = FX00_DEF_RATOV * 2;
89 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 90 /*
91 * Except for earlier ISPs where the timeout is seeded from the
92 * initialization control block.
93 */
94 tmo = ha->login_timeout;
95 }
96 return tmo;
97}
ac280b67 98
726b8548 99void
9ba56b95 100qla2x00_async_iocb_timeout(void *data)
ac280b67 101{
25ff6af1 102 srb_t *sp = data;
ac280b67 103 fc_port_t *fcport = sp->fcport;
726b8548
QT		 104 struct srb_iocb *lio = &sp->u.iocb_cmd;
105 struct event_arg ea;
ac280b67 106
5c25d451
QT		 107 if (fcport) {
108 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
109 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
110 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
111
6d674927 112 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
5c25d451
QT		 113 } else {
114 pr_info("Async-%s timeout - hdl=%x.\n",
115 sp->name, sp->handle);
116 }
726b8548
QT		 117
118 switch (sp->type) {
119 case SRB_LOGIN_CMD:
7ac0c332 120 if (!fcport)
121 break;
6ac52608
AV		 122 /* Retry as needed. */
123 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
124 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
125 QLA_LOGIO_LOGIN_RETRIED : 0;
726b8548
QT		 126 memset(&ea, 0, sizeof(ea));
127 ea.event = FCME_PLOGI_DONE;
128 ea.fcport = sp->fcport;
129 ea.data[0] = lio->u.logio.data[0];
130 ea.data[1] = lio->u.logio.data[1];
131 ea.sp = sp;
132 qla24xx_handle_plogi_done_event(fcport->vha, &ea);
133 break;
134 case SRB_LOGOUT_CMD:
7ac0c332 135 if (!fcport)
136 break;
a6ca8878 137 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
726b8548
QT		 138 break;
139 case SRB_CT_PTHRU_CMD:
140 case SRB_MB_IOCB:
141 case SRB_NACK_PLOGI:
142 case SRB_NACK_PRLI:
143 case SRB_NACK_LOGO:
2853192e 144 case SRB_CTRL_VP:
25ff6af1 145 sp->done(sp, QLA_FUNCTION_TIMEOUT);
726b8548 146 break;
6ac52608 147 }
ac280b67
AV		 148}
149
99b0bec7 150static void
25ff6af1 151qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 152{
25ff6af1
JC		 153 srb_t *sp = ptr;
154 struct scsi_qla_host *vha = sp->vha;
9ba56b95 155 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 156 struct event_arg ea;
9ba56b95 157
83548fe2 158 ql_dbg(ql_dbg_disc, vha, 0x20dd,
25ff6af1 159 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548 160
6d674927
QT		 161 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
162
726b8548
QT		 163 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
164 memset(&ea, 0, sizeof(ea));
165 ea.event = FCME_PLOGI_DONE;
166 ea.fcport = sp->fcport;
167 ea.data[0] = lio->u.logio.data[0];
168 ea.data[1] = lio->u.logio.data[1];
169 ea.iop[0] = lio->u.logio.iop[0];
170 ea.iop[1] = lio->u.logio.iop[1];
171 ea.sp = sp;
172 qla2x00_fcport_event_handler(vha, &ea);
173 }
9ba56b95 174
25ff6af1 175 sp->free(sp);
99b0bec7
AV		 176}
177
ac280b67
AV		 178int
179qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
180 uint16_t *data)
181{
ac280b67 182 srb_t *sp;
4916392b 183 struct srb_iocb *lio;
726b8548
QT		 184 int rval = QLA_FUNCTION_FAILED;
185
186 if (!vha->flags.online)
187 goto done;
188
9ba56b95 189 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 190 if (!sp)
191 goto done;
192
726b8548
QT		 193 fcport->flags |= FCF_ASYNC_SENT;
194 fcport->logout_completed = 0;
195
a4239945 196 fcport->disc_state = DSC_LOGIN_PEND;
9ba56b95
GM		 197 sp->type = SRB_LOGIN_CMD;
198 sp->name = "login";
a4239945
QT		 199 sp->gen1 = fcport->rscn_gen;
200 sp->gen2 = fcport->login_gen;
9ba56b95
GM		 201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_login_sp_done;
4916392b 206 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
a5d42f4c
DG		 207
208 if (fcport->fc4f_nvme)
209 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
210
ac280b67 211 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 212 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 213 rval = qla2x00_start_sp(sp);
080c9517 214 if (rval != QLA_SUCCESS) {
080c9517
CD		 215 fcport->flags |= FCF_LOGIN_NEEDED;
216 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 217 goto done_free_sp;
080c9517 218 }
ac280b67 219
7c3df132 220 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 221 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
222 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 223 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
224 fcport->login_retry);
ac280b67
AV		 225 return rval;
226
227done_free_sp:
25ff6af1 228 sp->free(sp);
726b8548 229 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 230done:
ac280b67
AV		 231 return rval;
232}
233
99b0bec7 234static void
25ff6af1 235qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 236{
25ff6af1 237 srb_t *sp = ptr;
9ba56b95 238 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95 239
6d674927 240 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
25ff6af1
JC		 241 if (!test_bit(UNLOADING, &sp->vha->dpc_flags))
242 qla2x00_post_async_logout_done_work(sp->vha, sp->fcport,
9ba56b95 243 lio->u.logio.data);
25ff6af1 244 sp->free(sp);
99b0bec7
AV		 245}
246
ac280b67
AV		 247int
248qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
249{
ac280b67 250 srb_t *sp;
4916392b 251 struct srb_iocb *lio;
3dbec59b
QT		 252 int rval = QLA_FUNCTION_FAILED;
253
254 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
255 return rval;
ac280b67 256
726b8548 257 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 258 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 259 if (!sp)
260 goto done;
261
9ba56b95
GM		 262 sp->type = SRB_LOGOUT_CMD;
263 sp->name = "logout";
264 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
265
266 lio = &sp->u.iocb_cmd;
3822263e 267 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 268 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 269 rval = qla2x00_start_sp(sp);
270 if (rval != QLA_SUCCESS)
271 goto done_free_sp;
272
7c3df132 273 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 274 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 275 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 276 fcport->d_id.b.area, fcport->d_id.b.al_pa,
277 fcport->port_name);
ac280b67
AV		 278 return rval;
279
280done_free_sp:
25ff6af1 281 sp->free(sp);
ac280b67 282done:
726b8548 283 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 284 return rval;
285}
11aea16a
QT		 286
287void
288qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
289 uint16_t *data)
290{
291 /* Don't re-login in target mode */
292 if (!fcport->tgt_session)
293 qla2x00_mark_device_lost(vha, fcport, 1, 0);
294 qlt_logo_completion_handler(fcport, data[0]);
295}
296
297static void
298qla2x00_async_prlo_sp_done(void *s, int res)
299{
300 srb_t *sp = (srb_t *)s;
301 struct srb_iocb *lio = &sp->u.iocb_cmd;
302 struct scsi_qla_host *vha = sp->vha;
303
304 if (!test_bit(UNLOADING, &vha->dpc_flags))
305 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
306 lio->u.logio.data);
307 sp->free(sp);
308}
309
310int
311qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
312{
313 srb_t *sp;
314 struct srb_iocb *lio;
315 int rval;
316
317 rval = QLA_FUNCTION_FAILED;
318 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
319 if (!sp)
320 goto done;
321
322 sp->type = SRB_PRLO_CMD;
323 sp->name = "prlo";
324 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
325
326 lio = &sp->u.iocb_cmd;
327 lio->timeout = qla2x00_async_iocb_timeout;
328 sp->done = qla2x00_async_prlo_sp_done;
329 rval = qla2x00_start_sp(sp);
330 if (rval != QLA_SUCCESS)
331 goto done_free_sp;
332
333 ql_dbg(ql_dbg_disc, vha, 0x2070,
334 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
335 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
336 fcport->d_id.b.area, fcport->d_id.b.al_pa);
337 return rval;
338
339done_free_sp:
340 sp->free(sp);
341done:
342 return rval;
343}
344
f13515ac
QT		 345static
346void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
347{
0616e965
QT		 348 struct fc_port *fcport = ea->fcport;
349
350 ql_dbg(ql_dbg_disc, vha, 0x20d2,
351 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
352 __func__, fcport->port_name, fcport->disc_state,
353 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
354 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
355
356 if (ea->data[0] != MBS_COMMAND_COMPLETE) {
a4239945
QT		 357 ql_dbg(ql_dbg_disc, vha, 0x2066,
358 "%s %8phC: adisc fail: post delete\n",
359 __func__, ea->fcport->port_name);
94cff6e1 360 qlt_schedule_sess_for_deletion(ea->fcport);
a4239945
QT		 361 return;
362 }
a4239945
QT		 363
364 if (ea->fcport->disc_state == DSC_DELETE_PEND)
365 return;
366
367 if (ea->sp->gen2 != ea->fcport->login_gen) {
368 /* target side must have changed it. */
369 ql_dbg(ql_dbg_disc, vha, 0x20d3,
0616e965
QT		 370 "%s %8phC generation changed\n",
371 __func__, ea->fcport->port_name);
a4239945
QT		 372 return;
373 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
374 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
375 __func__, __LINE__, ea->fcport->port_name);
376 qla24xx_post_gidpn_work(vha, ea->fcport);
377 return;
378 }
379
380 __qla24xx_handle_gpdb_event(vha, ea);
f13515ac 381}
ac280b67 382
5ff1d584 383static void
25ff6af1 384qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 385{
25ff6af1
JC		 386 srb_t *sp = ptr;
387 struct scsi_qla_host *vha = sp->vha;
f13515ac 388 struct event_arg ea;
0616e965 389 struct srb_iocb *lio = &sp->u.iocb_cmd;
f13515ac
QT		 390
391 ql_dbg(ql_dbg_disc, vha, 0x2066,
392 "Async done-%s res %x %8phC\n",
393 sp->name, res, sp->fcport->port_name);
394
395 memset(&ea, 0, sizeof(ea));
396 ea.event = FCME_ADISC_DONE;
397 ea.rc = res;
0616e965
QT		 398 ea.data[0] = lio->u.logio.data[0];
399 ea.data[1] = lio->u.logio.data[1];
400 ea.iop[0] = lio->u.logio.iop[0];
401 ea.iop[1] = lio->u.logio.iop[1];
f13515ac
QT		 402 ea.fcport = sp->fcport;
403 ea.sp = sp;
404
405 qla2x00_fcport_event_handler(vha, &ea);
9ba56b95 406
25ff6af1 407 sp->free(sp);
5ff1d584
AV		 408}
409
410int
411qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
412 uint16_t *data)
413{
5ff1d584 414 srb_t *sp;
4916392b 415 struct srb_iocb *lio;
5ff1d584
AV		 416 int rval;
417
418 rval = QLA_FUNCTION_FAILED;
726b8548 419 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 420 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 421 if (!sp)
422 goto done;
423
9ba56b95
GM		 424 sp->type = SRB_ADISC_CMD;
425 sp->name = "adisc";
426 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
427
428 lio = &sp->u.iocb_cmd;
3822263e 429 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 430 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 431 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 432 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 433 rval = qla2x00_start_sp(sp);
434 if (rval != QLA_SUCCESS)
435 goto done_free_sp;
436
7c3df132 437 ql_dbg(ql_dbg_disc, vha, 0x206f,
f13515ac
QT		 438 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
439 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
5ff1d584
AV		 440 return rval;
441
442done_free_sp:
25ff6af1 443 sp->free(sp);
5ff1d584 444done:
726b8548 445 fcport->flags &= ~FCF_ASYNC_SENT;
f13515ac 446 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 447 return rval;
448}
449
450static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
451 struct event_arg *ea)
452{
453 fc_port_t *fcport, *conflict_fcport;
454 struct get_name_list_extended *e;
455 u16 i, n, found = 0, loop_id;
456 port_id_t id;
457 u64 wwn;
a4239945
QT		 458 u16 data[2];
459 u8 current_login_state;
726b8548
QT		 460
461 fcport = ea->fcport;
f352eeb7
QT		 462 ql_dbg(ql_dbg_disc, vha, 0xffff,
463 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n",
464 __func__, fcport->port_name, fcport->disc_state,
465 fcport->fw_login_state, ea->rc,
466 fcport->login_gen, fcport->last_login_gen,
467 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id);
726b8548 468
a4239945
QT		 469 if (fcport->disc_state == DSC_DELETE_PEND)
470 return;
471
726b8548
QT		 472 if (ea->rc) { /* rval */
473 if (fcport->login_retry == 0) {
474 fcport->login_retry = vha->hw->login_retry_count;
83548fe2
QT		 475 ql_dbg(ql_dbg_disc, vha, 0x20de,
476 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
477 fcport->port_name, fcport->login_retry);
726b8548
QT		 478 }
479 return;
480 }
481
482 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 483 ql_dbg(ql_dbg_disc, vha, 0x20df,
726b8548
QT		 484 "%s %8phC rscn gen changed rscn %d|%d \n",
485 __func__, fcport->port_name,
486 fcport->last_rscn_gen, fcport->rscn_gen);
487 qla24xx_post_gidpn_work(vha, fcport);
488 return;
489 } else if (fcport->last_login_gen != fcport->login_gen) {
83548fe2 490 ql_dbg(ql_dbg_disc, vha, 0x20e0,
f352eeb7
QT		 491 "%s %8phC login gen changed\n",
492 __func__, fcport->port_name);
726b8548
QT		 493 return;
494 }
495
496 n = ea->data[0] / sizeof(struct get_name_list_extended);
497
83548fe2 498 ql_dbg(ql_dbg_disc, vha, 0x20e1,
726b8548
QT		 499 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
500 __func__, __LINE__, fcport->port_name, n,
501 fcport->d_id.b.domain, fcport->d_id.b.area,
502 fcport->d_id.b.al_pa, fcport->loop_id);
503
504 for (i = 0; i < n; i++) {
505 e = &vha->gnl.l[i];
506 wwn = wwn_to_u64(e->port_name);
507
508 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
509 continue;
510
511 found = 1;
512 id.b.domain = e->port_id[2];
513 id.b.area = e->port_id[1];
514 id.b.al_pa = e->port_id[0];
515 id.b.rsvd_1 = 0;
516
517 loop_id = le16_to_cpu(e->nport_handle);
518 loop_id = (loop_id & 0x7fff);
519
83548fe2
QT		 520 ql_dbg(ql_dbg_disc, vha, 0x20e2,
521 "%s found %8phC CLS [%d|%d] ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
522 __func__, fcport->port_name,
523 e->current_login_state, fcport->fw_login_state,
524 id.b.domain, id.b.area, id.b.al_pa,
525 fcport->d_id.b.domain, fcport->d_id.b.area,
526 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
726b8548
QT		 527
528 if ((id.b24 != fcport->d_id.b24) ||
529 ((fcport->loop_id != FC_NO_LOOP_ID) &&
530 (fcport->loop_id != loop_id))) {
83548fe2
QT		 531 ql_dbg(ql_dbg_disc, vha, 0x20e3,
532 "%s %d %8phC post del sess\n",
533 __func__, __LINE__, fcport->port_name);
94cff6e1 534 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 535 return;
536 }
537
538 fcport->loop_id = loop_id;
539
540 wwn = wwn_to_u64(fcport->port_name);
541 qlt_find_sess_invalidate_other(vha, wwn,
542 id, loop_id, &conflict_fcport);
543
544 if (conflict_fcport) {
545 /*
546 * Another share fcport share the same loop_id &
547 * nport id. Conflict fcport needs to finish
548 * cleanup before this fcport can proceed to login.
549 */
550 conflict_fcport->conflict = fcport;
551 fcport->login_pause = 1;
552 }
553
a5d42f4c
DG		 554 if (fcport->fc4f_nvme)
555 current_login_state = e->current_login_state >> 4;
556 else
557 current_login_state = e->current_login_state & 0xf;
558
559 switch (current_login_state) {
726b8548 560 case DSC_LS_PRLI_COMP:
83548fe2
QT		 561 ql_dbg(ql_dbg_disc, vha, 0x20e4,
562 "%s %d %8phC post gpdb\n",
563 __func__, __LINE__, fcport->port_name);
a4239945
QT		 564
565 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
566 fcport->port_type = FCT_INITIATOR;
567 else
568 fcport->port_type = FCT_TARGET;
569
570 data[0] = data[1] = 0;
571 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548 572 break;
726b8548
QT		 573 case DSC_LS_PORT_UNAVAIL:
574 default:
575 if (fcport->loop_id == FC_NO_LOOP_ID) {
576 qla2x00_find_new_loop_id(vha, fcport);
577 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
578 }
83548fe2
QT		 579 ql_dbg(ql_dbg_disc, vha, 0x20e5,
580 "%s %d %8phC\n",
581 __func__, __LINE__, fcport->port_name);
726b8548
QT		 582 qla24xx_fcport_handle_login(vha, fcport);
583 break;
584 }
585 }
586
587 if (!found) {
588 /* fw has no record of this port */
040036bb
QT		 589 for (i = 0; i < n; i++) {
590 e = &vha->gnl.l[i];
591 id.b.domain = e->port_id[0];
592 id.b.area = e->port_id[1];
593 id.b.al_pa = e->port_id[2];
594 id.b.rsvd_1 = 0;
595 loop_id = le16_to_cpu(e->nport_handle);
596
597 if (fcport->d_id.b24 == id.b24) {
598 conflict_fcport =
599 qla2x00_find_fcport_by_wwpn(vha,
600 e->port_name, 0);
601 ql_dbg(ql_dbg_disc, vha, 0x20e6,
602 "%s %d %8phC post del sess\n",
603 __func__, __LINE__,
604 conflict_fcport->port_name);
605 qlt_schedule_sess_for_deletion
94cff6e1 606 (conflict_fcport);
726b8548 607 }
040036bb
QT		 608
609 /* FW already picked this loop id for another fcport */
610 if (fcport->loop_id == loop_id)
611 fcport->loop_id = FC_NO_LOOP_ID;
726b8548
QT		 612 }
613 qla24xx_fcport_handle_login(vha, fcport);
614 }
615} /* gnl_event */
616
617static void
25ff6af1 618qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 619{
25ff6af1
JC		 620 struct srb *sp = s;
621 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 622 unsigned long flags;
623 struct fc_port *fcport = NULL, *tf;
624 u16 i, n = 0, loop_id;
625 struct event_arg ea;
626 struct get_name_list_extended *e;
627 u64 wwn;
628 struct list_head h;
a4239945 629 bool found = false;
726b8548 630
83548fe2 631 ql_dbg(ql_dbg_disc, vha, 0x20e7,
726b8548
QT		 632 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
633 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
634 sp->u.iocb_cmd.u.mbx.in_mb[2]);
635
636 memset(&ea, 0, sizeof(ea));
637 ea.sp = sp;
638 ea.rc = res;
639 ea.event = FCME_GNL_DONE;
640
641 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
642 sizeof(struct get_name_list_extended)) {
643 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
644 sizeof(struct get_name_list_extended);
645 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
646 }
647
648 for (i = 0; i < n; i++) {
649 e = &vha->gnl.l[i];
650 loop_id = le16_to_cpu(e->nport_handle);
651 /* mask out reserve bit */
652 loop_id = (loop_id & 0x7fff);
653 set_bit(loop_id, vha->hw->loop_id_map);
654 wwn = wwn_to_u64(e->port_name);
655
83548fe2 656 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
726b8548
QT		 657 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
658 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
659 e->port_id[0], e->current_login_state, e->last_login_state,
660 (loop_id & 0x7fff));
661 }
662
663 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
664 vha->gnl.sent = 0;
665
666 INIT_LIST_HEAD(&h);
667 fcport = tf = NULL;
668 if (!list_empty(&vha->gnl.fcports))
669 list_splice_init(&vha->gnl.fcports, &h);
670
671 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
672 list_del_init(&fcport->gnl_entry);
6d674927 673 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
726b8548
QT		 674 ea.fcport = fcport;
675
676 qla2x00_fcport_event_handler(vha, &ea);
677 }
678
a4239945
QT		 679 /* create new fcport if fw has knowledge of new sessions */
680 for (i = 0; i < n; i++) {
681 port_id_t id;
682 u64 wwnn;
683
684 e = &vha->gnl.l[i];
685 wwn = wwn_to_u64(e->port_name);
686
687 found = false;
688 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
689 if (!memcmp((u8 *)&wwn, fcport->port_name,
690 WWN_SIZE)) {
691 found = true;
692 break;
693 }
694 }
695
cf055fb0 696 id.b.domain = e->port_id[2];
a4239945 697 id.b.area = e->port_id[1];
cf055fb0 698 id.b.al_pa = e->port_id[0];
a4239945
QT		 699 id.b.rsvd_1 = 0;
700
701 if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
702 ql_dbg(ql_dbg_disc, vha, 0x2065,
cf055fb0
QT		 703 "%s %d %8phC %06x post new sess\n",
704 __func__, __LINE__, (u8 *)&wwn, id.b24);
a4239945
QT		 705 wwnn = wwn_to_u64(e->node_name);
706 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
707 (u8 *)&wwnn, NULL, FC4_TYPE_UNKNOWN);
708 }
709 }
710
726b8548
QT		 711 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
712
25ff6af1 713 sp->free(sp);
726b8548
QT		 714}
715
716int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
717{
718 srb_t *sp;
719 struct srb_iocb *mbx;
720 int rval = QLA_FUNCTION_FAILED;
721 unsigned long flags;
722 u16 *mb;
723
3dbec59b
QT		 724 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
725 return rval;
726b8548 726
83548fe2 727 ql_dbg(ql_dbg_disc, vha, 0x20d9,
726b8548
QT		 728 "Async-gnlist WWPN %8phC \n", fcport->port_name);
729
730 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 731 fcport->disc_state = DSC_GNL;
732 fcport->last_rscn_gen = fcport->rscn_gen;
733 fcport->last_login_gen = fcport->login_gen;
734
735 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
736 if (vha->gnl.sent) {
737 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
3dbec59b 738 return QLA_SUCCESS;
726b8548
QT		 739 }
740 vha->gnl.sent = 1;
741 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
742
743 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
744 if (!sp)
745 goto done;
3dbec59b
QT		 746
747 fcport->flags |= FCF_ASYNC_SENT;
726b8548
QT		 748 sp->type = SRB_MB_IOCB;
749 sp->name = "gnlist";
750 sp->gen1 = fcport->rscn_gen;
751 sp->gen2 = fcport->login_gen;
752
753 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
754
755 mb = sp->u.iocb_cmd.u.mbx.out_mb;
756 mb[0] = MBC_PORT_NODE_NAME_LIST;
757 mb[1] = BIT_2 | BIT_3;
758 mb[2] = MSW(vha->gnl.ldma);
759 mb[3] = LSW(vha->gnl.ldma);
760 mb[6] = MSW(MSD(vha->gnl.ldma));
761 mb[7] = LSW(MSD(vha->gnl.ldma));
762 mb[8] = vha->gnl.size;
763 mb[9] = vha->vp_idx;
764
765 mbx = &sp->u.iocb_cmd;
766 mbx->timeout = qla2x00_async_iocb_timeout;
767
768 sp->done = qla24xx_async_gnl_sp_done;
769
770 rval = qla2x00_start_sp(sp);
771 if (rval != QLA_SUCCESS)
772 goto done_free_sp;
773
83548fe2
QT		 774 ql_dbg(ql_dbg_disc, vha, 0x20da,
775 "Async-%s - OUT WWPN %8phC hndl %x\n",
776 sp->name, fcport->port_name, sp->handle);
726b8548
QT		 777
778 return rval;
779
780done_free_sp:
25ff6af1 781 sp->free(sp);
726b8548 782 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 783done:
726b8548
QT		 784 return rval;
785}
786
787int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
788{
789 struct qla_work_evt *e;
790
791 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
792 if (!e)
793 return QLA_FUNCTION_FAILED;
794
795 e->u.fcport.fcport = fcport;
6d674927 796 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 797 return qla2x00_post_work(vha, e);
798}
799
800static
25ff6af1 801void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 802{
25ff6af1
JC		 803 struct srb *sp = s;
804 struct scsi_qla_host *vha = sp->vha;
726b8548 805 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 806 fc_port_t *fcport = sp->fcport;
807 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
726b8548
QT		 808 struct event_arg ea;
809
83548fe2 810 ql_dbg(ql_dbg_disc, vha, 0x20db,
726b8548
QT		 811 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
812 sp->name, res, fcport->port_name, mb[1], mb[2]);
813
6d674927 814 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
726b8548 815
726b8548
QT		 816 memset(&ea, 0, sizeof(ea));
817 ea.event = FCME_GPDB_DONE;
726b8548
QT		 818 ea.fcport = fcport;
819 ea.sp = sp;
820
821 qla2x00_fcport_event_handler(vha, &ea);
822
823 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
824 sp->u.iocb_cmd.u.mbx.in_dma);
825
25ff6af1 826 sp->free(sp);
726b8548
QT		 827}
828
a5d42f4c
DG		 829static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
830{
831 struct qla_work_evt *e;
832
833 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
834 if (!e)
835 return QLA_FUNCTION_FAILED;
836
837 e->u.fcport.fcport = fcport;
838
839 return qla2x00_post_work(vha, e);
840}
841
842static void
843qla2x00_async_prli_sp_done(void *ptr, int res)
844{
845 srb_t *sp = ptr;
846 struct scsi_qla_host *vha = sp->vha;
847 struct srb_iocb *lio = &sp->u.iocb_cmd;
848 struct event_arg ea;
849
850 ql_dbg(ql_dbg_disc, vha, 0x2129,
851 "%s %8phC res %d \n", __func__,
852 sp->fcport->port_name, res);
853
854 sp->fcport->flags &= ~FCF_ASYNC_SENT;
855
856 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
857 memset(&ea, 0, sizeof(ea));
858 ea.event = FCME_PRLI_DONE;
859 ea.fcport = sp->fcport;
860 ea.data[0] = lio->u.logio.data[0];
861 ea.data[1] = lio->u.logio.data[1];
862 ea.iop[0] = lio->u.logio.iop[0];
863 ea.iop[1] = lio->u.logio.iop[1];
864 ea.sp = sp;
865
866 qla2x00_fcport_event_handler(vha, &ea);
867 }
868
869 sp->free(sp);
870}
871
872int
873qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
874{
875 srb_t *sp;
876 struct srb_iocb *lio;
877 int rval = QLA_FUNCTION_FAILED;
878
879 if (!vha->flags.online)
880 return rval;
881
882 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
883 fcport->fw_login_state == DSC_LS_PLOGI_COMP ||
884 fcport->fw_login_state == DSC_LS_PRLI_PEND)
885 return rval;
886
887 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
888 if (!sp)
889 return rval;
890
891 fcport->flags |= FCF_ASYNC_SENT;
892 fcport->logout_completed = 0;
893
894 sp->type = SRB_PRLI_CMD;
895 sp->name = "prli";
896 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
897
898 lio = &sp->u.iocb_cmd;
899 lio->timeout = qla2x00_async_iocb_timeout;
900 sp->done = qla2x00_async_prli_sp_done;
901 lio->u.logio.flags = 0;
902
903 if (fcport->fc4f_nvme)
904 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
905
906 rval = qla2x00_start_sp(sp);
907 if (rval != QLA_SUCCESS) {
a5d42f4c
DG		 908 fcport->flags |= FCF_LOGIN_NEEDED;
909 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
910 goto done_free_sp;
911 }
912
913 ql_dbg(ql_dbg_disc, vha, 0x211b,
914 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d.\n",
915 fcport->port_name, sp->handle, fcport->loop_id,
916 fcport->d_id.b24, fcport->login_retry);
917
918 return rval;
919
920done_free_sp:
921 sp->free(sp);
922 fcport->flags &= ~FCF_ASYNC_SENT;
923 return rval;
924}
925
a07fc0a4 926int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
726b8548
QT		 927{
928 struct qla_work_evt *e;
929
930 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
931 if (!e)
932 return QLA_FUNCTION_FAILED;
933
934 e->u.fcport.fcport = fcport;
935 e->u.fcport.opt = opt;
6d674927 936 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 937 return qla2x00_post_work(vha, e);
938}
939
940int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
941{
942 srb_t *sp;
943 struct srb_iocb *mbx;
944 int rval = QLA_FUNCTION_FAILED;
945 u16 *mb;
946 dma_addr_t pd_dma;
947 struct port_database_24xx *pd;
948 struct qla_hw_data *ha = vha->hw;
949
3dbec59b
QT		 950 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
951 return rval;
726b8548 952
726b8548
QT		 953 fcport->disc_state = DSC_GPDB;
954
955 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
956 if (!sp)
957 goto done;
958
3dbec59b 959 fcport->flags |= FCF_ASYNC_SENT;
e0824e69
JC		 960 sp->type = SRB_MB_IOCB;
961 sp->name = "gpdb";
962 sp->gen1 = fcport->rscn_gen;
963 sp->gen2 = fcport->login_gen;
964 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
965
08eb7f45 966 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
726b8548 967 if (pd == NULL) {
83548fe2
QT		 968 ql_log(ql_log_warn, vha, 0xd043,
969 "Failed to allocate port database structure.\n");
726b8548
QT		 970 goto done_free_sp;
971 }
726b8548 972
726b8548
QT		 973 mb = sp->u.iocb_cmd.u.mbx.out_mb;
974 mb[0] = MBC_GET_PORT_DATABASE;
975 mb[1] = fcport->loop_id;
976 mb[2] = MSW(pd_dma);
977 mb[3] = LSW(pd_dma);
978 mb[6] = MSW(MSD(pd_dma));
979 mb[7] = LSW(MSD(pd_dma));
980 mb[9] = vha->vp_idx;
981 mb[10] = opt;
982
983 mbx = &sp->u.iocb_cmd;
984 mbx->timeout = qla2x00_async_iocb_timeout;
985 mbx->u.mbx.in = (void *)pd;
986 mbx->u.mbx.in_dma = pd_dma;
987
988 sp->done = qla24xx_async_gpdb_sp_done;
989
990 rval = qla2x00_start_sp(sp);
991 if (rval != QLA_SUCCESS)
992 goto done_free_sp;
993
83548fe2
QT		 994 ql_dbg(ql_dbg_disc, vha, 0x20dc,
995 "Async-%s %8phC hndl %x opt %x\n",
996 sp->name, fcport->port_name, sp->handle, opt);
726b8548
QT		 997
998 return rval;
999
1000done_free_sp:
1001 if (pd)
1002 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1003
25ff6af1 1004 sp->free(sp);
726b8548 1005 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 1006done:
726b8548 1007 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 1008 return rval;
1009}
1010
726b8548 1011static
a4239945 1012void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1013{
726b8548
QT		 1014 unsigned long flags;
1015
726b8548 1016 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
f13515ac 1017 ea->fcport->login_gen++;
726b8548
QT		 1018 ea->fcport->deleted = 0;
1019 ea->fcport->logout_on_delete = 1;
1020
1021 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
1022 vha->fcport_count++;
1023 ea->fcport->login_succ = 1;
1024
1025 if (!IS_IIDMA_CAPABLE(vha->hw) ||
1026 !vha->hw->flags.gpsc_supported) {
83548fe2 1027 ql_dbg(ql_dbg_disc, vha, 0x20d6,
726b8548 1028 "%s %d %8phC post upd_fcport fcp_cnt %d\n",
a4239945 1029 __func__, __LINE__, ea->fcport->port_name,
726b8548
QT		 1030 vha->fcport_count);
1031
a4239945 1032 qla24xx_post_upd_fcport_work(vha, ea->fcport);
726b8548 1033 } else {
a4239945
QT		 1034 if (ea->fcport->id_changed) {
1035 ea->fcport->id_changed = 0;
1036 ql_dbg(ql_dbg_disc, vha, 0x20d7,
1037 "%s %d %8phC post gfpnid fcp_cnt %d\n",
1038 __func__, __LINE__, ea->fcport->port_name,
1039 vha->fcport_count);
1040 qla24xx_post_gfpnid_work(vha, ea->fcport);
1041 } else {
1042 ql_dbg(ql_dbg_disc, vha, 0x20d7,
1043 "%s %d %8phC post gpsc fcp_cnt %d\n",
1044 __func__, __LINE__, ea->fcport->port_name,
1045 vha->fcport_count);
1046 qla24xx_post_gpsc_work(vha, ea->fcport);
1047 }
726b8548 1048 }
414d9ff3
QT		 1049 } else if (ea->fcport->login_succ) {
1050 /*
1051 * We have an existing session. A late RSCN delivery
1052 * must have triggered the session to be re-validate.
a4239945 1053 * Session is still valid.
414d9ff3 1054 */
5ef696aa
QT		 1055 ql_dbg(ql_dbg_disc, vha, 0x20d6,
1056 "%s %d %8phC session revalidate success\n",
a4239945 1057 __func__, __LINE__, ea->fcport->port_name);
8a7eac2f 1058 ea->fcport->disc_state = DSC_LOGIN_COMPLETE;
726b8548
QT		 1059 }
1060 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
a4239945
QT		 1061}
1062
1063static
1064void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1065{
a4239945
QT		 1066 fc_port_t *fcport = ea->fcport;
1067 struct port_database_24xx *pd;
1068 struct srb *sp = ea->sp;
1069
1070 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
1071
1072 fcport->flags &= ~FCF_ASYNC_SENT;
1073
1074 ql_dbg(ql_dbg_disc, vha, 0x20d2,
f352eeb7
QT		 1075 "%s %8phC DS %d LS %d rc %d\n", __func__, fcport->port_name,
1076 fcport->disc_state, pd->current_login_state, ea->rc);
a4239945
QT		 1077
1078 if (fcport->disc_state == DSC_DELETE_PEND)
1079 return;
726b8548 1080
a4239945
QT		 1081 switch (pd->current_login_state) {
1082 case PDS_PRLI_COMPLETE:
1083 __qla24xx_parse_gpdb(vha, fcport, pd);
1084 break;
1085 case PDS_PLOGI_PENDING:
1086 case PDS_PLOGI_COMPLETE:
1087 case PDS_PRLI_PENDING:
1088 case PDS_PRLI2_PENDING:
1089 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC relogin needed\n",
1090 __func__, __LINE__, fcport->port_name);
1091 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1092 return;
1093 case PDS_LOGO_PENDING:
1094 case PDS_PORT_UNAVAILABLE:
1095 default:
1096 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
1097 __func__, __LINE__, fcport->port_name);
d8630bb9 1098 qlt_schedule_sess_for_deletion(fcport);
a4239945
QT		 1099 return;
1100 }
1101 __qla24xx_handle_gpdb_event(vha, ea);
1102} /* gpdb event */
9cd883f0
QT		 1103
1104static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1105{
1106 u8 login = 0;
040036bb 1107 int rc;
9cd883f0
QT		 1108
1109 if (qla_tgt_mode_enabled(vha))
1110 return;
1111
1112 if (qla_dual_mode_enabled(vha)) {
1113 if (N2N_TOPO(vha->hw)) {
1114 u64 mywwn, wwn;
1115
1116 mywwn = wwn_to_u64(vha->port_name);
1117 wwn = wwn_to_u64(fcport->port_name);
1118 if (mywwn > wwn)
1119 login = 1;
1120 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1121 && time_after_eq(jiffies,
1122 fcport->plogi_nack_done_deadline))
1123 login = 1;
1124 } else {
1125 login = 1;
1126 }
1127 } else {
1128 /* initiator mode */
1129 login = 1;
1130 }
1131
1132 if (login) {
040036bb
QT		 1133 if (fcport->loop_id == FC_NO_LOOP_ID) {
1134 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
1135 rc = qla2x00_find_new_loop_id(vha, fcport);
1136 if (rc) {
1137 ql_dbg(ql_dbg_disc, vha, 0x20e6,
1138 "%s %d %8phC post del sess - out of loopid\n",
1139 __func__, __LINE__, fcport->port_name);
1140 fcport->scan_state = 0;
94cff6e1 1141 qlt_schedule_sess_for_deletion(fcport);
040036bb
QT		 1142 return;
1143 }
1144 }
9cd883f0
QT		 1145 ql_dbg(ql_dbg_disc, vha, 0x20bf,
1146 "%s %d %8phC post login\n",
1147 __func__, __LINE__, fcport->port_name);
9cd883f0
QT		 1148 qla2x00_post_async_login_work(vha, fcport, NULL);
1149 }
1150}
1151
726b8548
QT		 1152int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1153{
f13515ac 1154 u16 data[2];
a4239945 1155 u64 wwn;
726b8548 1156
83548fe2 1157 ql_dbg(ql_dbg_disc, vha, 0x20d8,
f352eeb7 1158 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d retry %d lid %d scan %d\n",
726b8548
QT		 1159 __func__, fcport->port_name, fcport->disc_state,
1160 fcport->fw_login_state, fcport->login_pause, fcport->flags,
1161 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
f352eeb7 1162 fcport->login_gen, fcport->login_retry,
a4239945 1163 fcport->loop_id, fcport->scan_state);
726b8548 1164
a4239945
QT		 1165 if (fcport->login_retry == 0)
1166 return 0;
1167
1168 if (fcport->scan_state != QLA_FCPORT_FOUND)
1169 return 0;
726b8548
QT		 1170
1171 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1172 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1173 return 0;
1174
5b33469a 1175 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1176 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1177 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1178 return 0;
9cd883f0 1179 }
5b33469a
QT		 1180 }
1181
726b8548
QT		 1182 /* for pure Target Mode. Login will not be initiated */
1183 if (vha->host->active_mode == MODE_TARGET)
1184 return 0;
1185
1186 if (fcport->flags & FCF_ASYNC_SENT) {
1187 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1188 return 0;
1189 }
1190
a4239945
QT		 1191 fcport->login_retry--;
1192
726b8548
QT		 1193 switch (fcport->disc_state) {
1194 case DSC_DELETED:
a4239945
QT		 1195 wwn = wwn_to_u64(fcport->node_name);
1196 if (wwn == 0) {
1197 ql_dbg(ql_dbg_disc, vha, 0xffff,
1198 "%s %d %8phC post GNNID\n",
1199 __func__, __LINE__, fcport->port_name);
1200 qla24xx_post_gnnid_work(vha, fcport);
1201 } else if (fcport->loop_id == FC_NO_LOOP_ID) {
83548fe2
QT		 1202 ql_dbg(ql_dbg_disc, vha, 0x20bd,
1203 "%s %d %8phC post gnl\n",
1204 __func__, __LINE__, fcport->port_name);
5d3300a9 1205 qla24xx_post_gnl_work(vha, fcport);
726b8548 1206 } else {
9cd883f0 1207 qla_chk_n2n_b4_login(vha, fcport);
726b8548
QT		 1208 }
1209 break;
1210
1211 case DSC_GNL:
1212 if (fcport->login_pause) {
1213 fcport->last_rscn_gen = fcport->rscn_gen;
1214 fcport->last_login_gen = fcport->login_gen;
1215 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1216 break;
1217 }
1218
9cd883f0 1219 qla_chk_n2n_b4_login(vha, fcport);
726b8548
QT		 1220 break;
1221
1222 case DSC_LOGIN_FAILED:
83548fe2
QT		 1223 ql_dbg(ql_dbg_disc, vha, 0x20d0,
1224 "%s %d %8phC post gidpn\n",
1225 __func__, __LINE__, fcport->port_name);
9cd883f0
QT		 1226 if (N2N_TOPO(vha->hw))
1227 qla_chk_n2n_b4_login(vha, fcport);
1228 else
1229 qla24xx_post_gidpn_work(vha, fcport);
726b8548
QT		 1230 break;
1231
1232 case DSC_LOGIN_COMPLETE:
1233 /* recheck login state */
83548fe2 1234 ql_dbg(ql_dbg_disc, vha, 0x20d1,
f13515ac 1235 "%s %d %8phC post adisc\n",
83548fe2 1236 __func__, __LINE__, fcport->port_name);
f13515ac
QT		 1237 data[0] = data[1] = 0;
1238 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 1239 break;
1240
1241 default:
1242 break;
1243 }
1244
1245 return 0;
1246}
1247
1248static
1249void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
1250{
1251 fcport->rscn_gen++;
1252
83548fe2
QT		 1253 ql_dbg(ql_dbg_disc, fcport->vha, 0x210c,
1254 "%s %8phC DS %d LS %d\n",
1255 __func__, fcport->port_name, fcport->disc_state,
1256 fcport->fw_login_state);
726b8548
QT		 1257
1258 if (fcport->flags & FCF_ASYNC_SENT)
1259 return;
1260
1261 switch (fcport->disc_state) {
1262 case DSC_DELETED:
1263 case DSC_LOGIN_COMPLETE:
5ef696aa 1264 qla24xx_post_gpnid_work(fcport->vha, &ea->id);
726b8548 1265 break;
726b8548
QT		 1266 default:
1267 break;
1268 }
1269}
1270
1271int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
a4239945 1272 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
726b8548
QT		 1273{
1274 struct qla_work_evt *e;
1275 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1276 if (!e)
1277 return QLA_FUNCTION_FAILED;
1278
1279 e->u.new_sess.id = *id;
1280 e->u.new_sess.pla = pla;
a4239945 1281 e->u.new_sess.fc4_type = fc4_type;
726b8548 1282 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
a4239945
QT		 1283 if (node_name)
1284 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
726b8548
QT		 1285
1286 return qla2x00_post_work(vha, e);
1287}
1288
726b8548
QT		 1289static
1290void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1291 struct event_arg *ea)
1292{
1293 fc_port_t *fcport = ea->fcport;
1294
83548fe2
QT		 1295 ql_dbg(ql_dbg_disc, vha, 0x2102,
1296 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1297 __func__, fcport->port_name, fcport->disc_state,
1298 fcport->fw_login_state, fcport->login_pause,
1299 fcport->deleted, fcport->conflict,
1300 fcport->last_rscn_gen, fcport->rscn_gen,
1301 fcport->last_login_gen, fcport->login_gen,
1302 fcport->flags);
726b8548
QT		 1303
1304 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1305 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1306 return;
1307
5b33469a 1308 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1309 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1310 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1311 return;
9cd883f0 1312 }
5b33469a
QT		 1313 }
1314
726b8548
QT		 1315 if (fcport->flags & FCF_ASYNC_SENT) {
1316 fcport->login_retry++;
1317 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1318 return;
1319 }
1320
1321 if (fcport->disc_state == DSC_DELETE_PEND) {
1322 fcport->login_retry++;
1323 return;
1324 }
1325
1326 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 1327 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gidpn\n",
726b8548
QT		 1328 __func__, __LINE__, fcport->port_name);
1329
5d3300a9 1330 qla24xx_post_gidpn_work(vha, fcport);
726b8548
QT		 1331 return;
1332 }
1333
1334 qla24xx_fcport_handle_login(vha, fcport);
1335}
1336
41dc529a 1337void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1338{
f352eeb7 1339 fc_port_t *f, *tf;
41dc529a 1340 uint32_t id = 0, mask, rid;
f352eeb7 1341 unsigned long flags;
726b8548 1342
b98ae0d7 1343 switch (ea->event) {
b98ae0d7
QT		 1344 case FCME_RSCN:
1345 case FCME_GIDPN_DONE:
1346 case FCME_GPSC_DONE:
1347 case FCME_GPNID_DONE:
a4239945 1348 case FCME_GNNID_DONE:
b98ae0d7
QT		 1349 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
1350 test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1351 return;
1352 break;
1353 default:
1354 break;
1355 }
1356
726b8548
QT		 1357 switch (ea->event) {
1358 case FCME_RELOGIN:
1359 if (test_bit(UNLOADING, &vha->dpc_flags))
1360 return;
5ff1d584 1361
726b8548
QT		 1362 qla24xx_handle_relogin_event(vha, ea);
1363 break;
1364 case FCME_RSCN:
1365 if (test_bit(UNLOADING, &vha->dpc_flags))
1366 return;
41dc529a
QT		 1367 switch (ea->id.b.rsvd_1) {
1368 case RSCN_PORT_ADDR:
f352eeb7
QT		 1369 spin_lock_irqsave(&vha->work_lock, flags);
1370 if (vha->scan.scan_flags == 0) {
1371 ql_dbg(ql_dbg_disc, vha, 0xffff,
1372 "%s: schedule\n", __func__);
1373 vha->scan.scan_flags |= SF_QUEUED;
1374 schedule_delayed_work(&vha->scan.scan_work, 5);
41dc529a 1375 }
f352eeb7
QT		 1376 spin_unlock_irqrestore(&vha->work_lock, flags);
1377
41dc529a
QT		 1378 break;
1379 case RSCN_AREA_ADDR:
1380 case RSCN_DOM_ADDR:
1381 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1382 mask = 0xffff00;
83548fe2
QT		 1383 ql_dbg(ql_dbg_async, vha, 0x5044,
1384 "RSCN: Area 0x%06x was affected\n",
1385 ea->id.b24);
41dc529a
QT		 1386 } else {
1387 mask = 0xff0000;
83548fe2
QT		 1388 ql_dbg(ql_dbg_async, vha, 0x507a,
1389 "RSCN: Domain 0x%06x was affected\n",
1390 ea->id.b24);
41dc529a 1391 }
726b8548 1392
41dc529a
QT		 1393 rid = ea->id.b24 & mask;
1394 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1395 list) {
1396 id = f->d_id.b24 & mask;
1397 if (rid == id) {
1398 ea->fcport = f;
1399 qla24xx_handle_rscn_event(f, ea);
1400 }
726b8548 1401 }
41dc529a
QT		 1402 break;
1403 case RSCN_FAB_ADDR:
1404 default:
83548fe2
QT		 1405 ql_log(ql_log_warn, vha, 0xd045,
1406 "RSCN: Fabric was affected. Addr format %d\n",
1407 ea->id.b.rsvd_1);
41dc529a
QT		 1408 qla2x00_mark_all_devices_lost(vha, 1);
1409 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1410 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1411 }
1412 break;
1413 case FCME_GIDPN_DONE:
1414 qla24xx_handle_gidpn_event(vha, ea);
1415 break;
1416 case FCME_GNL_DONE:
1417 qla24xx_handle_gnl_done_event(vha, ea);
1418 break;
1419 case FCME_GPSC_DONE:
a4239945 1420 qla24xx_handle_gpsc_event(vha, ea);
726b8548
QT		 1421 break;
1422 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1423 qla24xx_handle_plogi_done_event(vha, ea);
1424 break;
a5d42f4c
DG		 1425 case FCME_PRLI_DONE:
1426 qla24xx_handle_prli_done_event(vha, ea);
1427 break;
726b8548
QT		 1428 case FCME_GPDB_DONE:
1429 qla24xx_handle_gpdb_event(vha, ea);
1430 break;
1431 case FCME_GPNID_DONE:
1432 qla24xx_handle_gpnid_event(vha, ea);
1433 break;
d3bae931
DG		 1434 case FCME_GFFID_DONE:
1435 qla24xx_handle_gffid_event(vha, ea);
1436 break;
f13515ac
QT		 1437 case FCME_ADISC_DONE:
1438 qla24xx_handle_adisc_event(vha, ea);
1439 break;
a4239945
QT		 1440 case FCME_GNNID_DONE:
1441 qla24xx_handle_gnnid_event(vha, ea);
1442 break;
1443 case FCME_GFPNID_DONE:
1444 qla24xx_handle_gfpnid_event(vha, ea);
1445 break;
726b8548
QT		 1446 default:
1447 BUG_ON(1);
1448 break;
1449 }
5ff1d584
AV		 1450}
1451
3822263e 1452static void
faef62d1 1453qla2x00_tmf_iocb_timeout(void *data)
3822263e 1454{
25ff6af1 1455 srb_t *sp = data;
faef62d1 1456 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1457
faef62d1
AB		 1458 tmf->u.tmf.comp_status = CS_TIMEOUT;
1459 complete(&tmf->u.tmf.comp);
1460}
9ba56b95 1461
faef62d1 1462static void
25ff6af1 1463qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1464{
25ff6af1 1465 srb_t *sp = ptr;
faef62d1 1466 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1467
faef62d1 1468 complete(&tmf->u.tmf.comp);
3822263e
MI		 1469}
1470
1471int
faef62d1 1472qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1473 uint32_t tag)
1474{
1475 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1476 struct srb_iocb *tm_iocb;
3822263e 1477 srb_t *sp;
faef62d1 1478 int rval = QLA_FUNCTION_FAILED;
3822263e 1479
9ba56b95 1480 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1481 if (!sp)
1482 goto done;
1483
faef62d1 1484 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1485 sp->type = SRB_TM_CMD;
1486 sp->name = "tmf";
faef62d1
AB		 1487 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1488 tm_iocb->u.tmf.flags = flags;
1489 tm_iocb->u.tmf.lun = lun;
1490 tm_iocb->u.tmf.data = tag;
1491 sp->done = qla2x00_tmf_sp_done;
1492 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1493 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 1494
1495 rval = qla2x00_start_sp(sp);
1496 if (rval != QLA_SUCCESS)
1497 goto done_free_sp;
1498
7c3df132 1499 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1500 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1501 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1502 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1503
1504 wait_for_completion(&tm_iocb->u.tmf.comp);
1505
1506 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
1507 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1508
1509 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
1510 ql_dbg(ql_dbg_taskm, vha, 0x8030,
1511 "TM IOCB failed (%x).\n", rval);
1512 }
1513
1514 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1515 flags = tm_iocb->u.tmf.flags;
1516 lun = (uint16_t)tm_iocb->u.tmf.lun;
1517
1518 /* Issue Marker IOCB */
1519 qla2x00_marker(vha, vha->hw->req_q_map[0],
1520 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1521 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1522 }
3822263e
MI		 1523
1524done_free_sp:
25ff6af1 1525 sp->free(sp);
6d674927 1526 sp->fcport->flags &= ~FCF_ASYNC_SENT;
3822263e
MI		 1527done:
1528 return rval;
1529}
1530
4440e46d
AB		 1531static void
1532qla24xx_abort_iocb_timeout(void *data)
1533{
25ff6af1 1534 srb_t *sp = data;
4440e46d
AB		 1535 struct srb_iocb *abt = &sp->u.iocb_cmd;
1536
1537 abt->u.abt.comp_status = CS_TIMEOUT;
1538 complete(&abt->u.abt.comp);
1539}
1540
1541static void
25ff6af1 1542qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1543{
25ff6af1 1544 srb_t *sp = ptr;
4440e46d
AB		 1545 struct srb_iocb *abt = &sp->u.iocb_cmd;
1546
1547 complete(&abt->u.abt.comp);
1548}
1549
15f30a57 1550int
4440e46d
AB		 1551qla24xx_async_abort_cmd(srb_t *cmd_sp)
1552{
25ff6af1 1553 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1554 fc_port_t *fcport = cmd_sp->fcport;
1555 struct srb_iocb *abt_iocb;
1556 srb_t *sp;
1557 int rval = QLA_FUNCTION_FAILED;
1558
1559 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1560 if (!sp)
1561 goto done;
1562
1563 abt_iocb = &sp->u.iocb_cmd;
1564 sp->type = SRB_ABT_CMD;
1565 sp->name = "abort";
1566 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1567 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
1568 sp->done = qla24xx_abort_sp_done;
1569 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1570 init_completion(&abt_iocb->u.abt.comp);
1571
1572 rval = qla2x00_start_sp(sp);
1573 if (rval != QLA_SUCCESS)
1574 goto done_free_sp;
1575
1576 ql_dbg(ql_dbg_async, vha, 0x507c,
1577 "Abort command issued - hdl=%x, target_id=%x\n",
1578 cmd_sp->handle, fcport->tgt_id);
1579
1580 wait_for_completion(&abt_iocb->u.abt.comp);
1581
1582 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1583 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1584
1585done_free_sp:
25ff6af1 1586 sp->free(sp);
4440e46d
AB		 1587done:
1588 return rval;
1589}
1590
1591int
1592qla24xx_async_abort_command(srb_t *sp)
1593{
1594 unsigned long flags = 0;
1595
1596 uint32_t handle;
1597 fc_port_t *fcport = sp->fcport;
1598 struct scsi_qla_host *vha = fcport->vha;
1599 struct qla_hw_data *ha = vha->hw;
1600 struct req_que *req = vha->req;
1601
1602 spin_lock_irqsave(&ha->hardware_lock, flags);
1603 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1604 if (req->outstanding_cmds[handle] == sp)
1605 break;
1606 }
1607 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1608 if (handle == req->num_outstanding_cmds) {
1609 /* Command not found. */
1610 return QLA_FUNCTION_FAILED;
1611 }
1612 if (sp->type == SRB_FXIOCB_DCMD)
1613 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1614 FXDISC_ABORT_IOCTL);
1615
1616 return qla24xx_async_abort_cmd(sp);
1617}
1618
a5d42f4c
DG		 1619static void
1620qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1621{
1622 switch (ea->data[0]) {
1623 case MBS_COMMAND_COMPLETE:
1624 ql_dbg(ql_dbg_disc, vha, 0x2118,
1625 "%s %d %8phC post gpdb\n",
1626 __func__, __LINE__, ea->fcport->port_name);
1627
1628 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1629 ea->fcport->logout_on_delete = 1;
1630 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1631 break;
1632 default:
edd05de1
DG		 1633 if (ea->fcport->n2n_flag) {
1634 ql_dbg(ql_dbg_disc, vha, 0x2118,
1635 "%s %d %8phC post fc4 prli\n",
1636 __func__, __LINE__, ea->fcport->port_name);
1637 ea->fcport->fc4f_nvme = 0;
1638 ea->fcport->n2n_flag = 0;
1639 qla24xx_post_prli_work(vha, ea->fcport);
1640 }
a5d42f4c
DG		 1641 ql_dbg(ql_dbg_disc, vha, 0x2119,
1642 "%s %d %8phC unhandle event of %x\n",
1643 __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
1644 break;
1645 }
1646}
1647
726b8548
QT		 1648static void
1649qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1650{
726b8548 1651 port_id_t cid; /* conflict Nport id */
a084fd68
QT		 1652 u16 lid;
1653 struct fc_port *conflict_fcport;
82abdcaf 1654 unsigned long flags;
a4239945
QT		 1655 struct fc_port *fcport = ea->fcport;
1656
f352eeb7
QT		 1657 ql_dbg(ql_dbg_disc, vha, 0xffff,
1658 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
1659 __func__, fcport->port_name, fcport->disc_state,
1660 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
1661 ea->sp->gen2, fcport->rscn_gen|ea->sp->gen1,
1662 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
1663
a4239945
QT		 1664 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1665 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) {
1666 ql_dbg(ql_dbg_disc, vha, 0x20ea,
1667 "%s %d %8phC Remote is trying to login\n",
1668 __func__, __LINE__, fcport->port_name);
1669 return;
1670 }
1671
1672 if (fcport->disc_state == DSC_DELETE_PEND)
1673 return;
1674
1675 if (ea->sp->gen2 != fcport->login_gen) {
1676 /* target side must have changed it. */
1677 ql_dbg(ql_dbg_disc, vha, 0x20d3,
f352eeb7
QT		 1678 "%s %8phC generation changed\n",
1679 __func__, fcport->port_name);
1680 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
a4239945
QT		 1681 return;
1682 } else if (ea->sp->gen1 != fcport->rscn_gen) {
1683 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
1684 __func__, __LINE__, fcport->port_name);
1685 qla24xx_post_gidpn_work(vha, fcport);
1686 return;
1687 }
ac280b67 1688
726b8548 1689 switch (ea->data[0]) {
ac280b67 1690 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1691 /*
1692 * Driver must validate login state - If PRLI not complete,
1693 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1694 * requests.
1695 */
a5d42f4c
DG		 1696 if (ea->fcport->fc4f_nvme) {
1697 ql_dbg(ql_dbg_disc, vha, 0x2117,
1698 "%s %d %8phC post prli\n",
1699 __func__, __LINE__, ea->fcport->port_name);
1700 qla24xx_post_prli_work(vha, ea->fcport);
1701 } else {
1702 ql_dbg(ql_dbg_disc, vha, 0x20ea,
a084fd68
QT		 1703 "%s %d %8phC LoopID 0x%x in use with %06x. post gnl\n",
1704 __func__, __LINE__, ea->fcport->port_name,
1705 ea->fcport->loop_id, ea->fcport->d_id.b24);
1706
1707 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
82abdcaf 1708 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a084fd68 1709 ea->fcport->loop_id = FC_NO_LOOP_ID;
a5d42f4c
DG		 1710 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1711 ea->fcport->logout_on_delete = 1;
3515832c 1712 ea->fcport->send_els_logo = 0;
82abdcaf
QT		 1713 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP;
1714 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1715
a5d42f4c
DG		 1716 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1717 }
ac280b67
AV		 1718 break;
1719 case MBS_COMMAND_ERROR:
83548fe2 1720 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
726b8548
QT		 1721 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1722
1723 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1724 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1725 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1726 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1727 else
726b8548 1728 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1729 break;
1730 case MBS_LOOP_ID_USED:
726b8548
QT		 1731 /* data[1] = IO PARAM 1 = nport ID */
1732 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1733 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1734 cid.b.al_pa = ea->iop[1] & 0xff;
1735 cid.b.rsvd_1 = 0;
1736
83548fe2
QT		 1737 ql_dbg(ql_dbg_disc, vha, 0x20ec,
1738 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1739 __func__, __LINE__, ea->fcport->port_name,
1740 ea->fcport->loop_id);
726b8548
QT		 1741
1742 if (IS_SW_RESV_ADDR(cid)) {
1743 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1744 ea->fcport->loop_id = FC_NO_LOOP_ID;
1745 } else {
1746 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1747 }
726b8548
QT		 1748 qla24xx_post_gnl_work(vha, ea->fcport);
1749 break;
1750 case MBS_PORT_ID_USED:
83548fe2
QT		 1751 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1752 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1753 __func__, __LINE__, ea->fcport->port_name,
1754 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1755 ea->fcport->d_id.b.al_pa);
726b8548 1756
a084fd68
QT		 1757 lid = ea->iop[1] & 0xffff;
1758 qlt_find_sess_invalidate_other(vha,
1759 wwn_to_u64(ea->fcport->port_name),
1760 ea->fcport->d_id, lid, &conflict_fcport);
1761
1762 if (conflict_fcport) {
1763 /*
1764 * Another fcport share the same loop_id/nport id.
1765 * Conflict fcport needs to finish cleanup before this
1766 * fcport can proceed to login.
1767 */
1768 conflict_fcport->conflict = ea->fcport;
1769 ea->fcport->login_pause = 1;
1770
1771 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1772 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
1773 __func__, __LINE__, ea->fcport->port_name,
1774 ea->fcport->d_id.b24, lid);
1775 qla2x00_clear_loop_id(ea->fcport);
1776 qla24xx_post_gidpn_work(vha, ea->fcport);
1777 } else {
1778 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1779 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
1780 __func__, __LINE__, ea->fcport->port_name,
1781 ea->fcport->d_id.b24, lid);
1782
1783 qla2x00_clear_loop_id(ea->fcport);
1784 set_bit(lid, vha->hw->loop_id_map);
1785 ea->fcport->loop_id = lid;
1786 ea->fcport->keep_nport_handle = 0;
94cff6e1 1787 qlt_schedule_sess_for_deletion(ea->fcport);
a084fd68 1788 }
ac280b67
AV		 1789 break;
1790 }
4916392b 1791 return;
ac280b67
AV		 1792}
1793
4916392b 1794void
ac280b67
AV		 1795qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1796 uint16_t *data)
1797{
726b8548 1798 qla2x00_mark_device_lost(vha, fcport, 1, 0);
a6ca8878 1799 qlt_logo_completion_handler(fcport, data[0]);
726b8548 1800 fcport->login_gen++;
4916392b 1801 return;
ac280b67
AV		 1802}
1803
4916392b 1804void
5ff1d584
AV		 1805qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1806 uint16_t *data)
1807{
1808 if (data[0] == MBS_COMMAND_COMPLETE) {
1809 qla2x00_update_fcport(vha, fcport);
1810
4916392b 1811 return;
5ff1d584
AV		 1812 }
1813
1814 /* Retry login. */
1815 fcport->flags &= ~FCF_ASYNC_SENT;
1816 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
1817 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1818 else
80d79440 1819 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 1820
4916392b 1821 return;
5ff1d584
AV		 1822}
1823
1da177e4
LT		 1824/****************************************************************************/
1825/* QLogic ISP2x00 Hardware Support Functions. */
1826/****************************************************************************/
1827
fa492630 1828static int
7d613ac6
SV		 1829qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
1830{
1831 int rval = QLA_SUCCESS;
1832 struct qla_hw_data *ha = vha->hw;
1833 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 1834 uint16_t config[4];
7d613ac6
SV		 1835
1836 qla83xx_idc_lock(vha, 0);
1837
1838 /* SV: TODO: Assign initialization timeout from
1839 * flash-info / other param
1840 */
1841 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
1842 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
1843
1844 /* Set our fcoe function presence */
1845 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
1846 ql_dbg(ql_dbg_p3p, vha, 0xb077,
1847 "Error while setting DRV-Presence.\n");
1848 rval = QLA_FUNCTION_FAILED;
1849 goto exit;
1850 }
1851
1852 /* Decide the reset ownership */
1853 qla83xx_reset_ownership(vha);
1854
1855 /*
1856 * On first protocol driver load:
1857 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
1858 * register.
1859 * Others: Check compatibility with current IDC Major version.
1860 */
1861 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
1862 if (ha->flags.nic_core_reset_owner) {
1863 /* Set IDC Major version */
1864 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
1865 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
1866
1867 /* Clearing IDC-Lock-Recovery register */
1868 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
1869 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
1870 /*
1871 * Clear further IDC participation if we are not compatible with
1872 * the current IDC Major Version.
1873 */
1874 ql_log(ql_log_warn, vha, 0xb07d,
1875 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
1876 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
1877 __qla83xx_clear_drv_presence(vha);
1878 rval = QLA_FUNCTION_FAILED;
1879 goto exit;
1880 }
1881 /* Each function sets its supported Minor version. */
1882 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
1883 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
1884 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
1885
711aa7f7
SK		 1886 if (ha->flags.nic_core_reset_owner) {
1887 memset(config, 0, sizeof(config));
1888 if (!qla81xx_get_port_config(vha, config))
1889 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
1890 QLA8XXX_DEV_READY);
1891 }
1892
7d613ac6
SV		 1893 rval = qla83xx_idc_state_handler(vha);
1894
1895exit:
1896 qla83xx_idc_unlock(vha, 0);
1897
1898 return rval;
1899}
1900
1da177e4
LT		 1901/*
1902* qla2x00_initialize_adapter
1903* Initialize board.
1904*
1905* Input:
1906* ha = adapter block pointer.
1907*
1908* Returns:
1909* 0 = success
1910*/
1911int
e315cd28 1912qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 1913{
1914 int rval;
e315cd28 1915 struct qla_hw_data *ha = vha->hw;
73208dfd 1916 struct req_que *req = ha->req_q_map[0];
2533cf67 1917
fc90adaf
JC		 1918 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
1919 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
1920
1da177e4 1921 /* Clear adapter flags. */
e315cd28 1922 vha->flags.online = 0;
2533cf67 1923 ha->flags.chip_reset_done = 0;
e315cd28 1924 vha->flags.reset_active = 0;
85880801
AV		 1925 ha->flags.pci_channel_io_perm_failure = 0;
1926 ha->flags.eeh_busy = 0;
fabbb8df 1927 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 1928 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1929 atomic_set(&vha->loop_state, LOOP_DOWN);
1930 vha->device_flags = DFLG_NO_CABLE;
1931 vha->dpc_flags = 0;
1932 vha->flags.management_server_logged_in = 0;
1933 vha->marker_needed = 0;
1da177e4
LT		 1934 ha->isp_abort_cnt = 0;
1935 ha->beacon_blink_led = 0;
1936
73208dfd
AC		 1937 set_bit(0, ha->req_qid_map);
1938 set_bit(0, ha->rsp_qid_map);
1939
cfb0919c 1940 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 1941 "Configuring PCI space...\n");
e315cd28 1942 rval = ha->isp_ops->pci_config(vha);
1da177e4 1943 if (rval) {
7c3df132
SK		 1944 ql_log(ql_log_warn, vha, 0x0044,
1945 "Unable to configure PCI space.\n");
1da177e4
LT		 1946 return (rval);
1947 }
1948
e315cd28 1949 ha->isp_ops->reset_chip(vha);
1da177e4 1950
e315cd28 1951 rval = qla2xxx_get_flash_info(vha);
c00d8994 1952 if (rval) {
7c3df132
SK		 1953 ql_log(ql_log_fatal, vha, 0x004f,
1954 "Unable to validate FLASH data.\n");
7ec0effd
AD		 1955 return rval;
1956 }
1957
1958 if (IS_QLA8044(ha)) {
1959 qla8044_read_reset_template(vha);
1960
1961 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
1962 * If DONRESET_BIT0 is set, drivers should not set dev_state
1963 * to NEED_RESET. But if NEED_RESET is set, drivers should
1964 * should honor the reset. */
1965 if (ql2xdontresethba == 1)
1966 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 1967 }
1968
73208dfd 1969 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 1970 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 1971 "Configure NVRAM parameters...\n");
0107109e 1972
e315cd28 1973 ha->isp_ops->nvram_config(vha);
1da177e4 1974
d4c760c2
AV		 1975 if (ha->flags.disable_serdes) {
1976 /* Mask HBA via NVRAM settings? */
7c3df132 1977 ql_log(ql_log_info, vha, 0x0077,
7b833558 1978 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 1979 return QLA_FUNCTION_FAILED;
1980 }
1981
cfb0919c 1982 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 1983 "Verifying loaded RISC code...\n");
1da177e4 1984
e315cd28
AC		 1985 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
1986 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 1987 if (rval)
1988 return (rval);
e315cd28 1989 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 1990 if (rval)
1991 return (rval);
1da177e4 1992 }
a9083016 1993
4d4df193 1994 if (IS_QLA84XX(ha)) {
e315cd28 1995 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 1996 if (!ha->cs84xx) {
7c3df132 1997 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 1998 "Unable to configure ISP84XX.\n");
1999 return QLA_FUNCTION_FAILED;
2000 }
2001 }
2d70c103 2002
ead03855 2003 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 2004 rval = qla2x00_init_rings(vha);
2005
2533cf67 2006 ha->flags.chip_reset_done = 1;
1da177e4 2007
9a069e19 2008 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 2009 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 2010 rval = qla84xx_init_chip(vha);
2011 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2012 ql_log(ql_log_warn, vha, 0x00d4,
2013 "Unable to initialize ISP84XX.\n");
8d2b21db 2014 qla84xx_put_chip(vha);
9a069e19
GM		 2015 }
2016 }
2017
7d613ac6
SV		 2018 /* Load the NIC Core f/w if we are the first protocol driver. */
2019 if (IS_QLA8031(ha)) {
2020 rval = qla83xx_nic_core_fw_load(vha);
2021 if (rval)
2022 ql_log(ql_log_warn, vha, 0x0124,
2023 "Error in initializing NIC Core f/w.\n");
2024 }
2025
2f0f3f4f
MI		 2026 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
2027 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 2028
c46e65c7
JC		 2029 if (IS_P3P_TYPE(ha))
2030 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
2031 else
2032 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
2033
1da177e4
LT		 2034 return (rval);
2035}
2036
2037/**
abbd8870 2038 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 2039 * @ha: HA context
2040 *
2041 * Returns 0 on success.
2042 */
abbd8870 2043int
e315cd28 2044qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 2045{
a157b101 2046 uint16_t w;
abbd8870 2047 unsigned long flags;
e315cd28 2048 struct qla_hw_data *ha = vha->hw;
3d71644c 2049 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2050
1da177e4 2051 pci_set_master(ha->pdev);
af6177d8 2052 pci_try_set_mwi(ha->pdev);
1da177e4 2053
1da177e4 2054 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2055 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 2056 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2057
737faece 2058 pci_disable_rom(ha->pdev);
1da177e4
LT		 2059
2060 /* Get PCI bus information. */
2061 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2062 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 2063 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2064
abbd8870
AV		 2065 return QLA_SUCCESS;
2066}
1da177e4 2067
abbd8870
AV		 2068/**
2069 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
2070 * @ha: HA context
2071 *
2072 * Returns 0 on success.
2073 */
2074int
e315cd28 2075qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 2076{
a157b101 2077 uint16_t w;
abbd8870
AV		 2078 unsigned long flags = 0;
2079 uint32_t cnt;
e315cd28 2080 struct qla_hw_data *ha = vha->hw;
3d71644c 2081 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2082
abbd8870 2083 pci_set_master(ha->pdev);
af6177d8 2084 pci_try_set_mwi(ha->pdev);
1da177e4 2085
abbd8870 2086 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2087 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 2088
abbd8870
AV		 2089 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2090 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 2091 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 2092
abbd8870
AV		 2093 /*
2094 * If this is a 2300 card and not 2312, reset the
2095 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
2096 * the 2310 also reports itself as a 2300 so we need to get the
2097 * fb revision level -- a 6 indicates it really is a 2300 and
2098 * not a 2310.
2099 */
2100 if (IS_QLA2300(ha)) {
2101 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 2102
abbd8870 2103 /* Pause RISC. */
3d71644c 2104 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 2105 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2106 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 2107 break;
1da177e4 2108
abbd8870
AV		 2109 udelay(10);
2110 }
1da177e4 2111
abbd8870 2112 /* Select FPM registers. */
3d71644c
AV		 2113 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2114 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2115
2116 /* Get the fb rev level */
3d71644c 2117 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 2118
2119 if (ha->fb_rev == FPM_2300)
a157b101 2120 pci_clear_mwi(ha->pdev);
abbd8870
AV		 2121
2122 /* Deselect FPM registers. */
3d71644c
AV		 2123 WRT_REG_WORD(&reg->ctrl_status, 0x0);
2124 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2125
2126 /* Release RISC module. */
3d71644c 2127 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 2128 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2129 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 2130 break;
2131
2132 udelay(10);
1da177e4 2133 }
1da177e4 2134
abbd8870
AV		 2135 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2136 }
1da177e4 2137
abbd8870
AV		 2138 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2139
737faece 2140 pci_disable_rom(ha->pdev);
1da177e4 2141
abbd8870
AV		 2142 /* Get PCI bus information. */
2143 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2144 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2145 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2146
2147 return QLA_SUCCESS;
1da177e4
LT		 2148}
2149
0107109e
AV		 2150/**
2151 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
2152 * @ha: HA context
2153 *
2154 * Returns 0 on success.
2155 */
2156int
e315cd28 2157qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 2158{
a157b101 2159 uint16_t w;
0107109e 2160 unsigned long flags = 0;
e315cd28 2161 struct qla_hw_data *ha = vha->hw;
0107109e 2162 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 2163
2164 pci_set_master(ha->pdev);
af6177d8 2165 pci_try_set_mwi(ha->pdev);
0107109e
AV		 2166
2167 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2168 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 2169 w &= ~PCI_COMMAND_INTX_DISABLE;
2170 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2171
2172 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2173
2174 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 2175 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
2176 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 2177
2178 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2179 if (pci_is_pcie(ha->pdev))
5ffd3a52 2180 pcie_set_readrq(ha->pdev, 4096);
0107109e 2181
737faece 2182 pci_disable_rom(ha->pdev);
0107109e 2183
44c10138 2184 ha->chip_revision = ha->pdev->revision;
a8488abe 2185
0107109e
AV		 2186 /* Get PCI bus information. */
2187 spin_lock_irqsave(&ha->hardware_lock, flags);
2188 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
2189 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2190
2191 return QLA_SUCCESS;
2192}
2193
c3a2f0df
AV		 2194/**
2195 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
2196 * @ha: HA context
2197 *
2198 * Returns 0 on success.
2199 */
2200int
e315cd28 2201qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 2202{
2203 uint16_t w;
e315cd28 2204 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 2205
2206 pci_set_master(ha->pdev);
2207 pci_try_set_mwi(ha->pdev);
2208
2209 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2210 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2211 w &= ~PCI_COMMAND_INTX_DISABLE;
2212 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2213
2214 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2215 if (pci_is_pcie(ha->pdev))
5ffd3a52 2216 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 2217
737faece 2218 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 2219
2220 ha->chip_revision = ha->pdev->revision;
2221
2222 return QLA_SUCCESS;
2223}
2224
1da177e4
LT		 2225/**
2226 * qla2x00_isp_firmware() - Choose firmware image.
2227 * @ha: HA context
2228 *
2229 * Returns 0 on success.
2230 */
2231static int
e315cd28 2232qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 2233{
2234 int rval;
42e421b1
AV		 2235 uint16_t loop_id, topo, sw_cap;
2236 uint8_t domain, area, al_pa;
e315cd28 2237 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2238
2239 /* Assume loading risc code */
fa2a1ce5 2240 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 2241
2242 if (ha->flags.disable_risc_code_load) {
7c3df132 2243 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 2244
2245 /* Verify checksum of loaded RISC code. */
e315cd28 2246 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 2247 if (rval == QLA_SUCCESS) {
2248 /* And, verify we are not in ROM code. */
e315cd28 2249 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 2250 &area, &domain, &topo, &sw_cap);
2251 }
1da177e4
LT		 2252 }
2253
7c3df132
SK		 2254 if (rval)
2255 ql_dbg(ql_dbg_init, vha, 0x007a,
2256 "**** Load RISC code ****.\n");
1da177e4
LT		 2257
2258 return (rval);
2259}
2260
2261/**
2262 * qla2x00_reset_chip() - Reset ISP chip.
2263 * @ha: HA context
2264 *
2265 * Returns 0 on success.
2266 */
abbd8870 2267void
e315cd28 2268qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 2269{
2270 unsigned long flags = 0;
e315cd28 2271 struct qla_hw_data *ha = vha->hw;
3d71644c 2272 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2273 uint32_t cnt;
1da177e4
LT		 2274 uint16_t cmd;
2275
85880801
AV		 2276 if (unlikely(pci_channel_offline(ha->pdev)))
2277 return;
2278
fd34f556 2279 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 2280
2281 spin_lock_irqsave(&ha->hardware_lock, flags);
2282
2283 /* Turn off master enable */
2284 cmd = 0;
2285 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2286 cmd &= ~PCI_COMMAND_MASTER;
2287 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2288
2289 if (!IS_QLA2100(ha)) {
2290 /* Pause RISC. */
2291 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2292 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2293 for (cnt = 0; cnt < 30000; cnt++) {
2294 if ((RD_REG_WORD(&reg->hccr) &
2295 HCCR_RISC_PAUSE) != 0)
2296 break;
2297 udelay(100);
2298 }
2299 } else {
2300 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2301 udelay(10);
2302 }
2303
2304 /* Select FPM registers. */
2305 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2306 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2307
2308 /* FPM Soft Reset. */
2309 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
2310 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2311
2312 /* Toggle Fpm Reset. */
2313 if (!IS_QLA2200(ha)) {
2314 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
2315 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2316 }
2317
2318 /* Select frame buffer registers. */
2319 WRT_REG_WORD(&reg->ctrl_status, 0x10);
2320 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2321
2322 /* Reset frame buffer FIFOs. */
2323 if (IS_QLA2200(ha)) {
2324 WRT_FB_CMD_REG(ha, reg, 0xa000);
2325 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2326 } else {
2327 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2328
2329 /* Read back fb_cmd until zero or 3 seconds max */
2330 for (cnt = 0; cnt < 3000; cnt++) {
2331 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2332 break;
2333 udelay(100);
2334 }
2335 }
2336
2337 /* Select RISC module registers. */
2338 WRT_REG_WORD(&reg->ctrl_status, 0);
2339 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2340
2341 /* Reset RISC processor. */
2342 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2343 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2344
2345 /* Release RISC processor. */
2346 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2347 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2348 }
2349
2350 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
2351 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
2352
2353 /* Reset ISP chip. */
2354 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2355
2356 /* Wait for RISC to recover from reset. */
2357 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2358 /*
2359 * It is necessary to for a delay here since the card doesn't
2360 * respond to PCI reads during a reset. On some architectures
2361 * this will result in an MCA.
2362 */
2363 udelay(20);
2364 for (cnt = 30000; cnt; cnt--) {
2365 if ((RD_REG_WORD(&reg->ctrl_status) &
2366 CSR_ISP_SOFT_RESET) == 0)
2367 break;
2368 udelay(100);
2369 }
2370 } else
2371 udelay(10);
2372
2373 /* Reset RISC processor. */
2374 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2375
2376 WRT_REG_WORD(&reg->semaphore, 0);
2377
2378 /* Release RISC processor. */
2379 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2380 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2381
2382 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2383 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 2384 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 2385 break;
1da177e4
LT		 2386
2387 udelay(100);
2388 }
2389 } else
2390 udelay(100);
2391
2392 /* Turn on master enable */
2393 cmd |= PCI_COMMAND_MASTER;
2394 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2395
2396 /* Disable RISC pause on FPM parity error. */
2397 if (!IS_QLA2100(ha)) {
2398 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2399 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2400 }
2401
2402 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2403}
2404
b1d46989
MI		 2405/**
2406 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2407 *
2408 * Returns 0 on success.
2409 */
fa492630 2410static int
b1d46989
MI		 2411qla81xx_reset_mpi(scsi_qla_host_t *vha)
2412{
2413 uint16_t mb[4] = {0x1010, 0, 1, 0};
2414
6246b8a1
GM		 2415 if (!IS_QLA81XX(vha->hw))
2416 return QLA_SUCCESS;
2417
b1d46989
MI		 2418 return qla81xx_write_mpi_register(vha, mb);
2419}
2420
0107109e 2421/**
88c26663 2422 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 2423 * @ha: HA context
2424 *
2425 * Returns 0 on success.
2426 */
d14e72fb 2427static inline int
e315cd28 2428qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2429{
2430 unsigned long flags = 0;
e315cd28 2431 struct qla_hw_data *ha = vha->hw;
0107109e 2432 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2433 uint32_t cnt;
335a1cc9 2434 uint16_t wd;
b1d46989 2435 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2436 int rval = QLA_SUCCESS;
0107109e 2437
0107109e
AV		 2438 spin_lock_irqsave(&ha->hardware_lock, flags);
2439
2440 /* Reset RISC. */
2441 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2442 for (cnt = 0; cnt < 30000; cnt++) {
2443 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2444 break;
2445
2446 udelay(10);
2447 }
2448
d14e72fb
HM		 2449 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2450 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2451
2452 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2453 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2454 RD_REG_DWORD(&reg->hccr),
2455 RD_REG_DWORD(&reg->ctrl_status),
2456 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2457
0107109e
AV		 2458 WRT_REG_DWORD(&reg->ctrl_status,
2459 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2460 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2461
335a1cc9 2462 udelay(100);
d14e72fb 2463
88c26663 2464 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2465 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2466 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2467 rval == QLA_SUCCESS; cnt--) {
88c26663 2468 barrier();
d14e72fb
HM		 2469 if (cnt)
2470 udelay(5);
2471 else
2472 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2473 }
2474
d14e72fb
HM		 2475 if (rval == QLA_SUCCESS)
2476 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2477
2478 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2479 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2480 RD_REG_DWORD(&reg->hccr),
2481 RD_REG_DWORD(&reg->mailbox0));
2482
335a1cc9 2483 /* Wait for soft-reset to complete. */
52c82823 2484 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2485 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2486 barrier();
d14e72fb
HM		 2487 if ((RD_REG_DWORD(&reg->ctrl_status) &
2488 CSRX_ISP_SOFT_RESET) == 0)
2489 break;
2490
2491 udelay(5);
0107109e 2492 }
d14e72fb
HM		 2493 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2494 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2495
2496 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2497 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2498 RD_REG_DWORD(&reg->hccr),
2499 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2500
b1d46989
MI		 2501 /* If required, do an MPI FW reset now */
2502 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2503 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2504 if (++abts_cnt < 5) {
2505 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2506 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2507 } else {
2508 /*
2509 * We exhausted the ISP abort retries. We have to
2510 * set the board offline.
2511 */
2512 abts_cnt = 0;
2513 vha->flags.online = 0;
2514 }
2515 }
2516 }
2517
0107109e
AV		 2518 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2519 RD_REG_DWORD(&reg->hccr);
2520
2521 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2522 RD_REG_DWORD(&reg->hccr);
2523
2524 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2525 RD_REG_DWORD(&reg->hccr);
2526
52c82823 2527 RD_REG_WORD(&reg->mailbox0);
200ffb15 2528 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2529 rval == QLA_SUCCESS; cnt--) {
0107109e 2530 barrier();
d14e72fb
HM		 2531 if (cnt)
2532 udelay(5);
2533 else
2534 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2535 }
d14e72fb
HM		 2536 if (rval == QLA_SUCCESS)
2537 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2538
2539 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2540 "Host Risc 0x%x, mailbox0 0x%x\n",
2541 RD_REG_DWORD(&reg->hccr),
2542 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2543
2544 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2545
d14e72fb
HM		 2546 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2547 "Driver in %s mode\n",
2548 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2549
124f85e6
AV		 2550 if (IS_NOPOLLING_TYPE(ha))
2551 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2552
2553 return rval;
0107109e
AV		 2554}
2555
4ea2c9c7
JC		 2556static void
2557qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2558{
2559 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2560
2561 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2562 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2563
2564}
2565
2566static void
2567qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2568{
2569 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2570
2571 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2572 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2573}
2574
2575static void
2576qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2577{
4ea2c9c7
JC		 2578 uint32_t wd32 = 0;
2579 uint delta_msec = 100;
2580 uint elapsed_msec = 0;
2581 uint timeout_msec;
2582 ulong n;
2583
cc790764
JC		 2584 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2585 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2586 return;
2587
8dd7e3a5
JC		 2588 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2589 udelay(100);
2590
4ea2c9c7
JC		 2591attempt:
2592 timeout_msec = TIMEOUT_SEMAPHORE;
2593 n = timeout_msec / delta_msec;
2594 while (n--) {
2595 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2596 qla25xx_read_risc_sema_reg(vha, &wd32);
2597 if (wd32 & RISC_SEMAPHORE)
2598 break;
2599 msleep(delta_msec);
2600 elapsed_msec += delta_msec;
2601 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2602 goto force;
2603 }
2604
2605 if (!(wd32 & RISC_SEMAPHORE))
2606 goto force;
2607
2608 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2609 goto acquired;
2610
2611 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2612 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2613 n = timeout_msec / delta_msec;
2614 while (n--) {
2615 qla25xx_read_risc_sema_reg(vha, &wd32);
2616 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2617 break;
2618 msleep(delta_msec);
2619 elapsed_msec += delta_msec;
2620 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2621 goto force;
2622 }
2623
2624 if (wd32 & RISC_SEMAPHORE_FORCE)
2625 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2626
2627 goto attempt;
2628
2629force:
2630 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2631
2632acquired:
2633 return;
2634}
2635
88c26663
AV		 2636/**
2637 * qla24xx_reset_chip() - Reset ISP24xx chip.
2638 * @ha: HA context
2639 *
2640 * Returns 0 on success.
2641 */
2642void
e315cd28 2643qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2644{
e315cd28 2645 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2646
2647 if (pci_channel_offline(ha->pdev) &&
2648 ha->flags.pci_channel_io_perm_failure) {
2649 return;
2650 }
2651
fd34f556 2652 ha->isp_ops->disable_intrs(ha);
88c26663 2653
4ea2c9c7
JC		 2654 qla25xx_manipulate_risc_semaphore(vha);
2655
88c26663 2656 /* Perform RISC reset. */
e315cd28 2657 qla24xx_reset_risc(vha);
88c26663
AV		 2658}
2659
1da177e4
LT		 2660/**
2661 * qla2x00_chip_diag() - Test chip for proper operation.
2662 * @ha: HA context
2663 *
2664 * Returns 0 on success.
2665 */
abbd8870 2666int
e315cd28 2667qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2668{
2669 int rval;
e315cd28 2670 struct qla_hw_data *ha = vha->hw;
3d71644c 2671 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2672 unsigned long flags = 0;
2673 uint16_t data;
2674 uint32_t cnt;
2675 uint16_t mb[5];
73208dfd 2676 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2677
2678 /* Assume a failed state */
2679 rval = QLA_FUNCTION_FAILED;
2680
7c3df132
SK		 2681 ql_dbg(ql_dbg_init, vha, 0x007b,
2682 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 2683
2684 spin_lock_irqsave(&ha->hardware_lock, flags);
2685
2686 /* Reset ISP chip. */
2687 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2688
2689 /*
2690 * We need to have a delay here since the card will not respond while
2691 * in reset causing an MCA on some architectures.
2692 */
2693 udelay(20);
2694 data = qla2x00_debounce_register(&reg->ctrl_status);
2695 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2696 udelay(5);
2697 data = RD_REG_WORD(&reg->ctrl_status);
2698 barrier();
2699 }
2700
2701 if (!cnt)
2702 goto chip_diag_failed;
2703
7c3df132
SK		 2704 ql_dbg(ql_dbg_init, vha, 0x007c,
2705 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2706
2707 /* Reset RISC processor. */
2708 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2709 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2710
2711 /* Workaround for QLA2312 PCI parity error */
2712 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2713 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2714 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2715 udelay(5);
2716 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2717 barrier();
1da177e4
LT		 2718 }
2719 } else
2720 udelay(10);
2721
2722 if (!cnt)
2723 goto chip_diag_failed;
2724
2725 /* Check product ID of chip */
5a68a1c2 2726 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 2727
2728 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2729 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2730 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2731 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2732 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2733 mb[3] != PROD_ID_3) {
7c3df132
SK		 2734 ql_log(ql_log_warn, vha, 0x0062,
2735 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2736 mb[1], mb[2], mb[3]);
1da177e4
LT		 2737
2738 goto chip_diag_failed;
2739 }
2740 ha->product_id[0] = mb[1];
2741 ha->product_id[1] = mb[2];
2742 ha->product_id[2] = mb[3];
2743 ha->product_id[3] = mb[4];
2744
2745 /* Adjust fw RISC transfer size */
73208dfd 2746 if (req->length > 1024)
1da177e4
LT		 2747 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2748 else
2749 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2750 req->length;
1da177e4
LT		 2751
2752 if (IS_QLA2200(ha) &&
2753 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2754 /* Limit firmware transfer size with a 2200A */
7c3df132 2755 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2756
ea5b6382 2757 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2758 ha->fw_transfer_size = 128;
2759 }
2760
2761 /* Wrap Incoming Mailboxes Test. */
2762 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2763
7c3df132 2764 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2765 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2766 if (rval)
2767 ql_log(ql_log_warn, vha, 0x0080,
2768 "Failed mailbox send register test.\n");
2769 else
1da177e4
LT		 2770 /* Flag a successful rval */
2771 rval = QLA_SUCCESS;
1da177e4
LT		 2772 spin_lock_irqsave(&ha->hardware_lock, flags);
2773
2774chip_diag_failed:
2775 if (rval)
7c3df132
SK		 2776 ql_log(ql_log_info, vha, 0x0081,
2777 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 2778
2779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2780
2781 return (rval);
2782}
2783
0107109e
AV		 2784/**
2785 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2786 * @ha: HA context
2787 *
2788 * Returns 0 on success.
2789 */
2790int
e315cd28 2791qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 2792{
2793 int rval;
e315cd28 2794 struct qla_hw_data *ha = vha->hw;
73208dfd 2795 struct req_que *req = ha->req_q_map[0];
0107109e 2796
7ec0effd 2797 if (IS_P3P_TYPE(ha))
a9083016
GM		 2798 return QLA_SUCCESS;
2799
73208dfd 2800 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 2801
e315cd28 2802 rval = qla2x00_mbx_reg_test(vha);
0107109e 2803 if (rval) {
7c3df132
SK		 2804 ql_log(ql_log_warn, vha, 0x0082,
2805 "Failed mailbox send register test.\n");
0107109e
AV		 2806 } else {
2807 /* Flag a successful rval */
2808 rval = QLA_SUCCESS;
2809 }
2810
2811 return rval;
2812}
2813
ad0a0b01
QT		 2814static void
2815qla2x00_alloc_offload_mem(scsi_qla_host_t *vha)
0107109e 2816{
a7a167bf 2817 int rval;
df613b96
AV		 2818 dma_addr_t tc_dma;
2819 void *tc;
e315cd28 2820 struct qla_hw_data *ha = vha->hw;
a7a167bf 2821
ad0a0b01 2822 if (ha->eft) {
7c3df132 2823 ql_dbg(ql_dbg_init, vha, 0x00bd,
ad0a0b01
QT		 2824 "%s: Offload Mem is already allocated.\n",
2825 __func__);
a7a167bf
AV		 2826 return;
2827 }
d4e3e04d 2828
ad0a0b01 2829 if (IS_FWI2_CAPABLE(ha)) {
df613b96 2830 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 2831 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2832 !IS_QLA27XX(ha))
436a7b11 2833 goto try_eft;
df613b96 2834
f73cb695
CD		 2835 if (ha->fce)
2836 dma_free_coherent(&ha->pdev->dev,
2837 FCE_SIZE, ha->fce, ha->fce_dma);
2838
2839 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 2840 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
2841 GFP_KERNEL);
df613b96 2842 if (!tc) {
7c3df132
SK		 2843 ql_log(ql_log_warn, vha, 0x00be,
2844 "Unable to allocate (%d KB) for FCE.\n",
2845 FCE_SIZE / 1024);
17d98630 2846 goto try_eft;
df613b96
AV		 2847 }
2848
e315cd28 2849 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 2850 ha->fce_mb, &ha->fce_bufs);
2851 if (rval) {
7c3df132
SK		 2852 ql_log(ql_log_warn, vha, 0x00bf,
2853 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 2854 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
2855 tc_dma);
2856 ha->flags.fce_enabled = 0;
17d98630 2857 goto try_eft;
df613b96 2858 }
cfb0919c 2859 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 2860 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 2861
df613b96
AV		 2862 ha->flags.fce_enabled = 1;
2863 ha->fce_dma = tc_dma;
2864 ha->fce = tc;
f73cb695 2865
436a7b11 2866try_eft:
f73cb695
CD		 2867 if (ha->eft)
2868 dma_free_coherent(&ha->pdev->dev,
2869 EFT_SIZE, ha->eft, ha->eft_dma);
2870
436a7b11 2871 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 2872 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
2873 GFP_KERNEL);
436a7b11 2874 if (!tc) {
7c3df132
SK		 2875 ql_log(ql_log_warn, vha, 0x00c1,
2876 "Unable to allocate (%d KB) for EFT.\n",
2877 EFT_SIZE / 1024);
ad0a0b01 2878 goto eft_err;
436a7b11
AV		 2879 }
2880
e315cd28 2881 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 2882 if (rval) {
7c3df132
SK		 2883 ql_log(ql_log_warn, vha, 0x00c2,
2884 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 2885 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
2886 tc_dma);
ad0a0b01 2887 goto eft_err;
436a7b11 2888 }
cfb0919c 2889 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 2890 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11 2891
436a7b11
AV		 2892 ha->eft_dma = tc_dma;
2893 ha->eft = tc;
d4e3e04d 2894 }
f73cb695 2895
ad0a0b01
QT		 2896eft_err:
2897 return;
2898}
2899
2900void
2901qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
2902{
2903 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
2904 eft_size, fce_size, mq_size;
2905 struct qla_hw_data *ha = vha->hw;
2906 struct req_que *req = ha->req_q_map[0];
2907 struct rsp_que *rsp = ha->rsp_q_map[0];
2908 struct qla2xxx_fw_dump *fw_dump;
2909
2910 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
2911 req_q_size = rsp_q_size = 0;
2912
2913 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2914 fixed_size = sizeof(struct qla2100_fw_dump);
2915 } else if (IS_QLA23XX(ha)) {
2916 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
2917 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
2918 sizeof(uint16_t);
2919 } else if (IS_FWI2_CAPABLE(ha)) {
2920 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
2921 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
2922 else if (IS_QLA81XX(ha))
2923 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
2924 else if (IS_QLA25XX(ha))
2925 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
2926 else
2927 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
2928
2929 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
2930 sizeof(uint32_t);
2931 if (ha->mqenable) {
2932 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
2933 mq_size = sizeof(struct qla2xxx_mq_chain);
2934 /*
2935 * Allocate maximum buffer size for all queues.
2936 * Resizing must be done at end-of-dump processing.
2937 */
2938 mq_size += ha->max_req_queues *
2939 (req->length * sizeof(request_t));
2940 mq_size += ha->max_rsp_queues *
2941 (rsp->length * sizeof(response_t));
2942 }
2943 if (ha->tgt.atio_ring)
2944 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
2945 /* Allocate memory for Fibre Channel Event Buffer. */
2946 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2947 !IS_QLA27XX(ha))
2948 goto try_eft;
2949
2950 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
2951try_eft:
2952 ql_dbg(ql_dbg_init, vha, 0x00c3,
2953 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
2954 eft_size = EFT_SIZE;
2955 }
2956
f73cb695
CD		 2957 if (IS_QLA27XX(ha)) {
2958 if (!ha->fw_dump_template) {
2959 ql_log(ql_log_warn, vha, 0x00ba,
2960 "Failed missing fwdump template\n");
2961 return;
2962 }
2963 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
2964 ql_dbg(ql_dbg_init, vha, 0x00fa,
2965 "-> allocating fwdump (%x bytes)...\n", dump_size);
2966 goto allocate;
2967 }
2968
73208dfd
AC		 2969 req_q_size = req->length * sizeof(request_t);
2970 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 2971 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 2972 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 2973 ha->chain_offset = dump_size;
2974 dump_size += mq_size + fce_size;
d4e3e04d 2975
b945e777
QT		 2976 if (ha->exchoffld_buf)
2977 dump_size += sizeof(struct qla2xxx_offld_chain) +
2978 ha->exchoffld_size;
2979 if (ha->exlogin_buf)
2980 dump_size += sizeof(struct qla2xxx_offld_chain) +
2981 ha->exlogin_size;
2982
f73cb695 2983allocate:
ad0a0b01
QT		 2984 if (!ha->fw_dump_len || dump_size != ha->fw_dump_len) {
2985 fw_dump = vmalloc(dump_size);
2986 if (!fw_dump) {
2987 ql_log(ql_log_warn, vha, 0x00c4,
2988 "Unable to allocate (%d KB) for firmware dump.\n",
2989 dump_size / 1024);
2990 } else {
2991 if (ha->fw_dump)
2992 vfree(ha->fw_dump);
2993 ha->fw_dump = fw_dump;
2994
2995 ha->fw_dump_len = dump_size;
2996 ql_dbg(ql_dbg_init, vha, 0x00c5,
2997 "Allocated (%d KB) for firmware dump.\n",
2998 dump_size / 1024);
2999
3000 if (IS_QLA27XX(ha))
3001 return;
3002
3003 ha->fw_dump->signature[0] = 'Q';
3004 ha->fw_dump->signature[1] = 'L';
3005 ha->fw_dump->signature[2] = 'G';
3006 ha->fw_dump->signature[3] = 'C';
3007 ha->fw_dump->version = htonl(1);
3008
3009 ha->fw_dump->fixed_size = htonl(fixed_size);
3010 ha->fw_dump->mem_size = htonl(mem_size);
3011 ha->fw_dump->req_q_size = htonl(req_q_size);
3012 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
3013
3014 ha->fw_dump->eft_size = htonl(eft_size);
3015 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
3016 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
3017
3018 ha->fw_dump->header_size =
3019 htonl(offsetof(struct qla2xxx_fw_dump, isp));
a7a167bf 3020 }
a7a167bf 3021 }
0107109e
AV		 3022}
3023
18e7555a
AV		 3024static int
3025qla81xx_mpi_sync(scsi_qla_host_t *vha)
3026{
3027#define MPS_MASK 0xe0
3028 int rval;
3029 uint16_t dc;
3030 uint32_t dw;
18e7555a
AV		 3031
3032 if (!IS_QLA81XX(vha->hw))
3033 return QLA_SUCCESS;
3034
3035 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
3036 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3037 ql_log(ql_log_warn, vha, 0x0105,
3038 "Unable to acquire semaphore.\n");
18e7555a
AV		 3039 goto done;
3040 }
3041
3042 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
3043 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
3044 if (rval != QLA_SUCCESS) {
7c3df132 3045 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 3046 goto done_release;
3047 }
3048
3049 dc &= MPS_MASK;
3050 if (dc == (dw & MPS_MASK))
3051 goto done_release;
3052
3053 dw &= ~MPS_MASK;
3054 dw |= dc;
3055 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
3056 if (rval != QLA_SUCCESS) {
7c3df132 3057 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 3058 }
3059
3060done_release:
3061 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
3062 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3063 ql_log(ql_log_warn, vha, 0x006d,
3064 "Unable to release semaphore.\n");
18e7555a
AV		 3065 }
3066
3067done:
3068 return rval;
3069}
3070
8d93f550
CD		 3071int
3072qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
3073{
3074 /* Don't try to reallocate the array */
3075 if (req->outstanding_cmds)
3076 return QLA_SUCCESS;
3077
d7459527 3078 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 3079 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
3080 else {
03e8c680
QT		 3081 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
3082 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 3083 else
03e8c680 3084 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 3085 }
3086
3087 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
3088 req->num_outstanding_cmds, GFP_KERNEL);
3089
3090 if (!req->outstanding_cmds) {
3091 /*
3092 * Try to allocate a minimal size just so we can get through
3093 * initialization.
3094 */
3095 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
3096 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
3097 req->num_outstanding_cmds, GFP_KERNEL);
3098
3099 if (!req->outstanding_cmds) {
3100 ql_log(ql_log_fatal, NULL, 0x0126,
3101 "Failed to allocate memory for "
3102 "outstanding_cmds for req_que %p.\n", req);
3103 req->num_outstanding_cmds = 0;
3104 return QLA_FUNCTION_FAILED;
3105 }
3106 }
3107
3108 return QLA_SUCCESS;
3109}
3110
e4e3a2ce
QT		 3111#define PRINT_FIELD(_field, _flag, _str) { \
3112 if (a0->_field & _flag) {\
3113 if (p) {\
3114 strcat(ptr, "|");\
3115 ptr++;\
3116 leftover--;\
3117 } \
3118 len = snprintf(ptr, leftover, "%s", _str); \
3119 p = 1;\
3120 leftover -= len;\
3121 ptr += len; \
3122 } \
3123}
3124
3125static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
3126{
3127#define STR_LEN 64
3128 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
3129 u8 str[STR_LEN], *ptr, p;
3130 int leftover, len;
3131
3132 memset(str, 0, STR_LEN);
3133 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
3134 ql_dbg(ql_dbg_init, vha, 0x015a,
3135 "SFP MFG Name: %s\n", str);
3136
3137 memset(str, 0, STR_LEN);
3138 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
3139 ql_dbg(ql_dbg_init, vha, 0x015c,
3140 "SFP Part Name: %s\n", str);
3141
3142 /* media */
3143 memset(str, 0, STR_LEN);
3144 ptr = str;
3145 leftover = STR_LEN;
3146 p = len = 0;
3147 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
3148 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
3149 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
3150 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
3151 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
3152 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
3153 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
3154 ql_dbg(ql_dbg_init, vha, 0x0160,
3155 "SFP Media: %s\n", str);
3156
3157 /* link length */
3158 memset(str, 0, STR_LEN);
3159 ptr = str;
3160 leftover = STR_LEN;
3161 p = len = 0;
3162 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
3163 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
3164 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
3165 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
3166 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
3167 ql_dbg(ql_dbg_init, vha, 0x0196,
3168 "SFP Link Length: %s\n", str);
3169
3170 memset(str, 0, STR_LEN);
3171 ptr = str;
3172 leftover = STR_LEN;
3173 p = len = 0;
3174 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
3175 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
3176 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
3177 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
3178 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
3179 ql_dbg(ql_dbg_init, vha, 0x016e,
3180 "SFP FC Link Tech: %s\n", str);
3181
3182 if (a0->length_km)
3183 ql_dbg(ql_dbg_init, vha, 0x016f,
3184 "SFP Distant: %d km\n", a0->length_km);
3185 if (a0->length_100m)
3186 ql_dbg(ql_dbg_init, vha, 0x0170,
3187 "SFP Distant: %d m\n", a0->length_100m*100);
3188 if (a0->length_50um_10m)
3189 ql_dbg(ql_dbg_init, vha, 0x0189,
3190 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
3191 if (a0->length_62um_10m)
3192 ql_dbg(ql_dbg_init, vha, 0x018a,
3193 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
3194 if (a0->length_om4_10m)
3195 ql_dbg(ql_dbg_init, vha, 0x0194,
3196 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
3197 if (a0->length_om3_10m)
3198 ql_dbg(ql_dbg_init, vha, 0x0195,
3199 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
3200}
3201
3202
3203/*
3204 * Return Code:
3205 * QLA_SUCCESS: no action
3206 * QLA_INTERFACE_ERROR: SFP is not there.
3207 * QLA_FUNCTION_FAILED: detected New SFP
3208 */
3209int
3210qla24xx_detect_sfp(scsi_qla_host_t *vha)
3211{
3212 int rc = QLA_SUCCESS;
3213 struct sff_8247_a0 *a;
3214 struct qla_hw_data *ha = vha->hw;
3215
3216 if (!AUTO_DETECT_SFP_SUPPORT(vha))
3217 goto out;
3218
3219 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
3220 if (rc)
3221 goto out;
3222
3223 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
3224 qla2xxx_print_sfp_info(vha);
3225
3226 if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
3227 /* long range */
3228 ha->flags.detected_lr_sfp = 1;
3229
3230 if (a->length_km > 5 || a->length_100m > 50)
3231 ha->long_range_distance = LR_DISTANCE_10K;
3232 else
3233 ha->long_range_distance = LR_DISTANCE_5K;
3234
3235 if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
3236 ql_dbg(ql_dbg_async, vha, 0x507b,
3237 "Detected Long Range SFP.\n");
3238 } else {
3239 /* short range */
3240 ha->flags.detected_lr_sfp = 0;
3241 if (ha->flags.using_lr_setting)
3242 ql_dbg(ql_dbg_async, vha, 0x5084,
3243 "Detected Short Range SFP.\n");
3244 }
3245
3246 if (!vha->flags.init_done)
3247 rc = QLA_SUCCESS;
3248out:
3249 return rc;
3250}
3251
1da177e4
LT		 3252/**
3253 * qla2x00_setup_chip() - Load and start RISC firmware.
3254 * @ha: HA context
3255 *
3256 * Returns 0 on success.
3257 */
3258static int
e315cd28 3259qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 3260{
0107109e
AV		 3261 int rval;
3262 uint32_t srisc_address = 0;
e315cd28 3263 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 3264 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3265 unsigned long flags;
dda772e8 3266 uint16_t fw_major_version;
3db0652e 3267
7ec0effd 3268 if (IS_P3P_TYPE(ha)) {
a9083016 3269 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 3270 if (rval == QLA_SUCCESS) {
3271 qla2x00_stop_firmware(vha);
a9083016 3272 goto enable_82xx_npiv;
14e303d9 3273 } else
b963752f 3274 goto failed;
a9083016
GM		 3275 }
3276
3db0652e
AV		 3277 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3278 /* Disable SRAM, Instruction RAM and GP RAM parity. */
3279 spin_lock_irqsave(&ha->hardware_lock, flags);
3280 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
3281 RD_REG_WORD(&reg->hccr);
3282 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3283 }
1da177e4 3284
18e7555a
AV		 3285 qla81xx_mpi_sync(vha);
3286
1da177e4 3287 /* Load firmware sequences */
e315cd28 3288 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 3289 if (rval == QLA_SUCCESS) {
7c3df132
SK		 3290 ql_dbg(ql_dbg_init, vha, 0x00c9,
3291 "Verifying Checksum of loaded RISC code.\n");
1da177e4 3292
e315cd28 3293 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 3294 if (rval == QLA_SUCCESS) {
3295 /* Start firmware execution. */
7c3df132
SK		 3296 ql_dbg(ql_dbg_init, vha, 0x00ca,
3297 "Starting firmware.\n");
1da177e4 3298
b0d6cabd
HM		 3299 if (ql2xexlogins)
3300 ha->flags.exlogins_enabled = 1;
3301
99e1b683 3302 if (qla_is_exch_offld_enabled(vha))
2f56a7f1
HM		 3303 ha->flags.exchoffld_enabled = 1;
3304
e315cd28 3305 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 3306 /* Retrieve firmware information. */
dda772e8 3307 if (rval == QLA_SUCCESS) {
e4e3a2ce
QT		 3308 qla24xx_detect_sfp(vha);
3309
b0d6cabd
HM		 3310 rval = qla2x00_set_exlogins_buffer(vha);
3311 if (rval != QLA_SUCCESS)
3312 goto failed;
3313
2f56a7f1
HM		 3314 rval = qla2x00_set_exchoffld_buffer(vha);
3315 if (rval != QLA_SUCCESS)
3316 goto failed;
3317
a9083016 3318enable_82xx_npiv:
dda772e8 3319 fw_major_version = ha->fw_major_version;
7ec0effd 3320 if (IS_P3P_TYPE(ha))
3173167f 3321 qla82xx_check_md_needed(vha);
6246b8a1
GM		 3322 else
3323 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 3324 if (rval != QLA_SUCCESS)
3325 goto failed;
2c3dfe3f 3326 ha->flags.npiv_supported = 0;
e315cd28 3327 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 3328 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 3329 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 3330 if ((!ha->max_npiv_vports) ||
3331 ((ha->max_npiv_vports + 1) %
eb66dc60 3332 MIN_MULTI_ID_FABRIC))
4d0ea247 3333 ha->max_npiv_vports =
eb66dc60 3334 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 3335 }
03e8c680 3336 qla2x00_get_resource_cnts(vha);
d743de66 3337
8d93f550
CD		 3338 /*
3339 * Allocate the array of outstanding commands
3340 * now that we know the firmware resources.
3341 */
3342 rval = qla2x00_alloc_outstanding_cmds(ha,
3343 vha->req);
3344 if (rval != QLA_SUCCESS)
3345 goto failed;
3346
ad0a0b01
QT		 3347 if (!fw_major_version && !(IS_P3P_TYPE(ha)))
3348 qla2x00_alloc_offload_mem(vha);
3349
3350 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
08de2844 3351 qla2x00_alloc_fw_dump(vha);
ad0a0b01 3352
3b6e5b9d
CD		 3353 } else {
3354 goto failed;
1da177e4
LT		 3355 }
3356 } else {
7c3df132
SK		 3357 ql_log(ql_log_fatal, vha, 0x00cd,
3358 "ISP Firmware failed checksum.\n");
3359 goto failed;
1da177e4 3360 }
c74d88a4
AV		 3361 } else
3362 goto failed;
1da177e4 3363
3db0652e
AV		 3364 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3365 /* Enable proper parity. */
3366 spin_lock_irqsave(&ha->hardware_lock, flags);
3367 if (IS_QLA2300(ha))
3368 /* SRAM parity */
3369 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
3370 else
3371 /* SRAM, Instruction RAM and GP RAM parity */
3372 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
3373 RD_REG_WORD(&reg->hccr);
3374 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3375 }
3376
f3982d89
CD		 3377 if (IS_QLA27XX(ha))
3378 ha->flags.fac_supported = 1;
3379 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 3380 uint32_t size;
3381
3382 rval = qla81xx_fac_get_sector_size(vha, &size);
3383 if (rval == QLA_SUCCESS) {
3384 ha->flags.fac_supported = 1;
3385 ha->fdt_block_size = size << 2;
3386 } else {
7c3df132 3387 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 3388 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3389 ha->fw_major_version, ha->fw_minor_version,
3390 ha->fw_subminor_version);
1ca60e3b 3391
f73cb695 3392 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 3393 ha->flags.fac_supported = 0;
3394 rval = QLA_SUCCESS;
3395 }
1d2874de
JC		 3396 }
3397 }
ca9e9c3e 3398failed:
1da177e4 3399 if (rval) {
7c3df132
SK		 3400 ql_log(ql_log_fatal, vha, 0x00cf,
3401 "Setup chip ****FAILED****.\n");
1da177e4
LT		 3402 }
3403
3404 return (rval);
3405}
3406
3407/**
3408 * qla2x00_init_response_q_entries() - Initializes response queue entries.
3409 * @ha: HA context
3410 *
3411 * Beginning of request ring has initialization control block already built
3412 * by nvram config routine.
3413 *
3414 * Returns 0 on success.
3415 */
73208dfd
AC		 3416void
3417qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 3418{
3419 uint16_t cnt;
3420 response_t *pkt;
3421
2afa19a9
AC		 3422 rsp->ring_ptr = rsp->ring;
3423 rsp->ring_index = 0;
3424 rsp->status_srb = NULL;
e315cd28
AC		 3425 pkt = rsp->ring_ptr;
3426 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 3427 pkt->signature = RESPONSE_PROCESSED;
3428 pkt++;
3429 }
1da177e4
LT		 3430}
3431
3432/**
3433 * qla2x00_update_fw_options() - Read and process firmware options.
3434 * @ha: HA context
3435 *
3436 * Returns 0 on success.
3437 */
abbd8870 3438void
e315cd28 3439qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 3440{
3441 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 3442 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3443
3444 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 3445 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 3446
3447 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3448 return;
3449
3450 /* Serial Link options. */
7c3df132
SK		 3451 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3452 "Serial link options.\n");
3453 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
3454 (uint8_t *)&ha->fw_seriallink_options,
3455 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 3456
3457 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3458 if (ha->fw_seriallink_options[3] & BIT_2) {
3459 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3460
3461 /* 1G settings */
3462 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3463 emphasis = (ha->fw_seriallink_options[2] &
3464 (BIT_4 | BIT_3)) >> 3;
3465 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 3466 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3467 rx_sens = (ha->fw_seriallink_options[0] &
3468 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3469 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3470 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3471 if (rx_sens == 0x0)
3472 rx_sens = 0x3;
3473 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3474 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3475 ha->fw_options[10] |= BIT_5 |
3476 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3477 (tx_sens & (BIT_1 | BIT_0));
3478
3479 /* 2G settings */
3480 swing = (ha->fw_seriallink_options[2] &
3481 (BIT_7 | BIT_6 | BIT_5)) >> 5;
3482 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
3483 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 3484 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3485 rx_sens = (ha->fw_seriallink_options[1] &
3486 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3487 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
3488 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3489 if (rx_sens == 0x0)
3490 rx_sens = 0x3;
3491 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
3492 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3493 ha->fw_options[11] |= BIT_5 |
3494 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3495 (tx_sens & (BIT_1 | BIT_0));
3496 }
3497
3498 /* FCP2 options. */
3499 /* Return command IOCBs without waiting for an ABTS to complete. */
3500 ha->fw_options[3] |= BIT_13;
3501
3502 /* LED scheme. */
3503 if (ha->flags.enable_led_scheme)
3504 ha->fw_options[2] |= BIT_12;
3505
48c02fde 3506 /* Detect ISP6312. */
3507 if (IS_QLA6312(ha))
3508 ha->fw_options[2] |= BIT_13;
3509
088d09d4
GM		 3510 /* Set Retry FLOGI in case of P2P connection */
3511 if (ha->operating_mode == P2P) {
3512 ha->fw_options[2] |= BIT_3;
3513 ql_dbg(ql_dbg_disc, vha, 0x2100,
3514 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3515 __func__, ha->fw_options[2]);
3516 }
3517
1da177e4 3518 /* Update firmware options. */
e315cd28 3519 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 3520}
3521
0107109e 3522void
e315cd28 3523qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 3524{
3525 int rval;
e315cd28 3526 struct qla_hw_data *ha = vha->hw;
0107109e 3527
7ec0effd 3528 if (IS_P3P_TYPE(ha))
a9083016
GM		 3529 return;
3530
f198cafa
HM		 3531 /* Hold status IOCBs until ABTS response received. */
3532 if (ql2xfwholdabts)
3533 ha->fw_options[3] |= BIT_12;
3534
088d09d4
GM		 3535 /* Set Retry FLOGI in case of P2P connection */
3536 if (ha->operating_mode == P2P) {
3537 ha->fw_options[2] |= BIT_3;
3538 ql_dbg(ql_dbg_disc, vha, 0x2101,
3539 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3540 __func__, ha->fw_options[2]);
3541 }
3542
41dc529a 3543 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff
QT		 3544 if (ql2xmvasynctoatio &&
3545 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
41dc529a
QT		 3546 if (qla_tgt_mode_enabled(vha) ||
3547 qla_dual_mode_enabled(vha))
3548 ha->fw_options[2] |= BIT_11;
3549 else
3550 ha->fw_options[2] &= ~BIT_11;
3551 }
3552
f7e761f5
QT		 3553 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3554 /*
3555 * Tell FW to track each exchange to prevent
3556 * driver from using stale exchange.
3557 */
3558 if (qla_tgt_mode_enabled(vha) ||
3559 qla_dual_mode_enabled(vha))
3560 ha->fw_options[2] |= BIT_4;
3561 else
3562 ha->fw_options[2] &= ~BIT_4;
9ecf0b0d
QT		 3563
3564 /* Reserve 1/2 of emergency exchanges for ELS.*/
3565 if (qla2xuseresexchforels)
3566 ha->fw_options[2] |= BIT_8;
3567 else
3568 ha->fw_options[2] &= ~BIT_8;
f7e761f5
QT		 3569 }
3570
83548fe2
QT		 3571 ql_dbg(ql_dbg_init, vha, 0x00e8,
3572 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3573 __func__, ha->fw_options[1], ha->fw_options[2],
3574 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 3575
3576 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
3577 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 3578
0107109e 3579 /* Update Serial Link options. */
f94097ed 3580 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3581 return;
3582
e315cd28 3583 rval = qla2x00_set_serdes_params(vha,
f94097ed 3584 le16_to_cpu(ha->fw_seriallink_options24[1]),
3585 le16_to_cpu(ha->fw_seriallink_options24[2]),
3586 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3587 if (rval != QLA_SUCCESS) {
7c3df132 3588 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3589 "Unable to update Serial Link options (%x).\n", rval);
3590 }
3591}
3592
abbd8870 3593void
e315cd28 3594qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3595{
e315cd28 3596 struct qla_hw_data *ha = vha->hw;
3d71644c 3597 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3598 struct req_que *req = ha->req_q_map[0];
3599 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3600
3601 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3602 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3603 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3604 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3605 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
3606 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3607 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3608 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3609 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 3610
3611 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3612 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3613 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3614 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3615 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3616}
3617
0107109e 3618void
e315cd28 3619qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3620{
e315cd28 3621 struct qla_hw_data *ha = vha->hw;
118e2ef9 3622 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3623 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3624 struct qla_msix_entry *msix;
0107109e 3625 struct init_cb_24xx *icb;
73208dfd
AC		 3626 uint16_t rid = 0;
3627 struct req_que *req = ha->req_q_map[0];
3628 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3629
6246b8a1 3630 /* Setup ring parameters in initialization control block. */
0107109e 3631 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3632 icb->request_q_outpointer = cpu_to_le16(0);
3633 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3634 icb->request_q_length = cpu_to_le16(req->length);
3635 icb->response_q_length = cpu_to_le16(rsp->length);
3636 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3637 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3638 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3639 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3640
2d70c103 3641 /* Setup ATIO queue dma pointers for target mode */
ad950360 3642 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3643 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3644 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3645 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3646
7c6300e3 3647 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3648 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3649
f73cb695 3650 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3651 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3652 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3653 if (ha->flags.msix_enabled) {
3654 msix = &ha->msix_entries[1];
83548fe2 3655 ql_dbg(ql_dbg_init, vha, 0x0019,
7c3df132
SK		 3656 "Registering vector 0x%x for base que.\n",
3657 msix->entry);
73208dfd
AC		 3658 icb->msix = cpu_to_le16(msix->entry);
3659 }
3660 /* Use alternate PCI bus number */
3661 if (MSB(rid))
ad950360 3662 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3663 /* Use alternate PCI devfn */
3664 if (LSB(rid))
ad950360 3665 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3666
3155754a 3667 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3668 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3669 (ha->flags.msix_enabled)) {
ad950360 3670 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3671 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3672 ql_dbg(ql_dbg_init, vha, 0x00fe,
3673 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3674 } else {
ad950360 3675 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3676 }
ad950360 3677 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3678
3679 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3680 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3681 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3682 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3683 } else {
3684 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3685 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3686 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3687 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3688 }
aa230bc5 3689 qlt_24xx_config_rings(vha);
2d70c103 3690
73208dfd
AC		 3691 /* PCI posting */
3692 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3693}
3694
1da177e4
LT		 3695/**
3696 * qla2x00_init_rings() - Initializes firmware.
3697 * @ha: HA context
3698 *
3699 * Beginning of request ring has initialization control block already built
3700 * by nvram config routine.
3701 *
3702 * Returns 0 on success.
3703 */
8ae6d9c7 3704int
e315cd28 3705qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3706{
3707 int rval;
3708 unsigned long flags = 0;
29bdccbe 3709 int cnt, que;
e315cd28 3710 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3711 struct req_que *req;
3712 struct rsp_que *rsp;
2c3dfe3f
SJ		 3713 struct mid_init_cb_24xx *mid_init_cb =
3714 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3715
3716 spin_lock_irqsave(&ha->hardware_lock, flags);
3717
3718 /* Clear outstanding commands array. */
2afa19a9 3719 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3720 req = ha->req_q_map[que];
cb43285f 3721 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3722 continue;
7c6300e3
JC		 3723 req->out_ptr = (void *)(req->ring + req->length);
3724 *req->out_ptr = 0;
8d93f550 3725 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3726 req->outstanding_cmds[cnt] = NULL;
1da177e4 3727
2afa19a9 3728 req->current_outstanding_cmd = 1;
1da177e4 3729
29bdccbe
AC		 3730 /* Initialize firmware. */
3731 req->ring_ptr = req->ring;
3732 req->ring_index = 0;
3733 req->cnt = req->length;
3734 }
1da177e4 3735
2afa19a9 3736 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3737 rsp = ha->rsp_q_map[que];
cb43285f 3738 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3739 continue;
7c6300e3
JC		 3740 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3741 *rsp->in_ptr = 0;
29bdccbe 3742 /* Initialize response queue entries */
8ae6d9c7
GM		 3743 if (IS_QLAFX00(ha))
3744 qlafx00_init_response_q_entries(rsp);
3745 else
3746 qla2x00_init_response_q_entries(rsp);
29bdccbe 3747 }
1da177e4 3748
2d70c103
NB		 3749 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3750 ha->tgt.atio_ring_index = 0;
3751 /* Initialize ATIO queue entries */
3752 qlt_init_atio_q_entries(vha);
3753
e315cd28 3754 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3755
3756 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3757
8ae6d9c7
GM		 3758 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3759
3760 if (IS_QLAFX00(ha)) {
3761 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3762 goto next_check;
3763 }
3764
1da177e4 3765 /* Update any ISP specific firmware options before initialization. */
e315cd28 3766 ha->isp_ops->update_fw_options(vha);
1da177e4 3767
605aa2bc 3768 if (ha->flags.npiv_supported) {
45980cc2 3769 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 3770 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 3771 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 3772 }
3773
24a08138 3774 if (IS_FWI2_CAPABLE(ha)) {
ad950360 3775 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 3776 mid_init_cb->init_cb.execution_throttle =
03e8c680 3777 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 3778 ha->flags.dport_enabled =
3779 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
3780 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
3781 (ha->flags.dport_enabled) ? "enabled" : "disabled");
3782 /* FA-WWPN Status */
2486c627 3783 ha->flags.fawwpn_enabled =
40f3862b 3784 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
83548fe2 3785 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
2486c627 3786 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 3787 }
2c3dfe3f 3788
e315cd28 3789 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 3790next_check:
1da177e4 3791 if (rval) {
7c3df132
SK		 3792 ql_log(ql_log_fatal, vha, 0x00d2,
3793 "Init Firmware **** FAILED ****.\n");
1da177e4 3794 } else {
7c3df132
SK		 3795 ql_dbg(ql_dbg_init, vha, 0x00d3,
3796 "Init Firmware -- success.\n");
4b60c827 3797 QLA_FW_STARTED(ha);
1da177e4
LT		 3798 }
3799
3800 return (rval);
3801}
3802
3803/**
3804 * qla2x00_fw_ready() - Waits for firmware ready.
3805 * @ha: HA context
3806 *
3807 * Returns 0 on success.
3808 */
3809static int
e315cd28 3810qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 3811{
3812 int rval;
4d4df193 3813 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 3814 uint16_t min_wait; /* Minimum wait time if loop is down */
3815 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 3816 uint16_t state[6];
e315cd28 3817 struct qla_hw_data *ha = vha->hw;
1da177e4 3818
8ae6d9c7
GM		 3819 if (IS_QLAFX00(vha->hw))
3820 return qlafx00_fw_ready(vha);
3821
1da177e4
LT		 3822 rval = QLA_SUCCESS;
3823
33461491
CD		 3824 /* Time to wait for loop down */
3825 if (IS_P3P_TYPE(ha))
3826 min_wait = 30;
3827 else
3828 min_wait = 20;
1da177e4
LT		 3829
3830 /*
3831 * Firmware should take at most one RATOV to login, plus 5 seconds for
3832 * our own processing.
3833 */
3834 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
3835 wait_time = min_wait;
3836 }
3837
3838 /* Min wait time if loop down */
3839 mtime = jiffies + (min_wait * HZ);
3840
3841 /* wait time before firmware ready */
3842 wtime = jiffies + (wait_time * HZ);
3843
3844 /* Wait for ISP to finish LIP */
e315cd28 3845 if (!vha->flags.init_done)
7c3df132
SK		 3846 ql_log(ql_log_info, vha, 0x801e,
3847 "Waiting for LIP to complete.\n");
1da177e4
LT		 3848
3849 do {
5b939038 3850 memset(state, -1, sizeof(state));
e315cd28 3851 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 3852 if (rval == QLA_SUCCESS) {
4d4df193 3853 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 3854 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 3855 }
4d4df193 3856 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 3857 ql_dbg(ql_dbg_taskm, vha, 0x801f,
3858 "fw_state=%x 84xx=%x.\n", state[0],
3859 state[2]);
4d4df193
HK		 3860 if ((state[2] & FSTATE_LOGGED_IN) &&
3861 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 3862 ql_dbg(ql_dbg_taskm, vha, 0x8028,
3863 "Sending verify iocb.\n");
4d4df193
HK		 3864
3865 cs84xx_time = jiffies;
e315cd28 3866 rval = qla84xx_init_chip(vha);
7c3df132
SK		 3867 if (rval != QLA_SUCCESS) {
3868 ql_log(ql_log_warn,
cfb0919c 3869 vha, 0x8007,
7c3df132 3870 "Init chip failed.\n");
4d4df193 3871 break;
7c3df132 3872 }
4d4df193
HK		 3873
3874 /* Add time taken to initialize. */
3875 cs84xx_time = jiffies - cs84xx_time;
3876 wtime += cs84xx_time;
3877 mtime += cs84xx_time;
cfb0919c 3878 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 3879 "Increasing wait time by %ld. "
3880 "New time %ld.\n", cs84xx_time,
3881 wtime);
4d4df193
HK		 3882 }
3883 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 3884 ql_dbg(ql_dbg_taskm, vha, 0x8037,
3885 "F/W Ready - OK.\n");
1da177e4 3886
e315cd28 3887 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 3888 &ha->login_timeout, &ha->r_a_tov);
3889
3890 rval = QLA_SUCCESS;
3891 break;
3892 }
3893
3894 rval = QLA_FUNCTION_FAILED;
3895
e315cd28 3896 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 3897 state[0] != FSTATE_READY) {
1da177e4 3898 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 3899 * other than Wait for Login.
3900 */
1da177e4 3901 if (time_after_eq(jiffies, mtime)) {
7c3df132 3902 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 3903 "Cable is unplugged...\n");
3904
e315cd28 3905 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 3906 break;
3907 }
3908 }
3909 } else {
3910 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 3911 if (time_after_eq(jiffies, mtime) ||
7190575f 3912 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 3913 break;
3914 }
3915
3916 if (time_after_eq(jiffies, wtime))
3917 break;
3918
3919 /* Delay for a while */
3920 msleep(500);
1da177e4
LT		 3921 } while (1);
3922
7c3df132 3923 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 3924 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
3925 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 3926
cfb0919c 3927 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 3928 ql_log(ql_log_warn, vha, 0x803b,
3929 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 3930 }
3931
3932 return (rval);
3933}
3934
3935/*
3936* qla2x00_configure_hba
3937* Setup adapter context.
3938*
3939* Input:
3940* ha = adapter state pointer.
3941*
3942* Returns:
3943* 0 = success
3944*
3945* Context:
3946* Kernel context.
3947*/
3948static int
e315cd28 3949qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 3950{
3951 int rval;
3952 uint16_t loop_id;
3953 uint16_t topo;
2c3dfe3f 3954 uint16_t sw_cap;
1da177e4
LT		 3955 uint8_t al_pa;
3956 uint8_t area;
3957 uint8_t domain;
3958 char connect_type[22];
e315cd28 3959 struct qla_hw_data *ha = vha->hw;
61e1b269 3960 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 3961 port_id_t id;
9d1aa4e1 3962 unsigned long flags;
1da177e4
LT		 3963
3964 /* Get host addresses. */
e315cd28 3965 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 3966 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 3967 if (rval != QLA_SUCCESS) {
e315cd28 3968 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 3969 IS_CNA_CAPABLE(ha) ||
33135aa2 3970 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 3971 ql_dbg(ql_dbg_disc, vha, 0x2008,
3972 "Loop is in a transition state.\n");
33135aa2 3973 } else {
7c3df132
SK		 3974 ql_log(ql_log_warn, vha, 0x2009,
3975 "Unable to get host loop ID.\n");
61e1b269
JC		 3976 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
3977 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
3978 ql_log(ql_log_warn, vha, 0x1151,
3979 "Doing link init.\n");
3980 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
3981 return rval;
3982 }
e315cd28 3983 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 3984 }
1da177e4
LT		 3985 return (rval);
3986 }
3987
3988 if (topo == 4) {
7c3df132
SK		 3989 ql_log(ql_log_info, vha, 0x200a,
3990 "Cannot get topology - retrying.\n");
1da177e4
LT		 3991 return (QLA_FUNCTION_FAILED);
3992 }
3993
e315cd28 3994 vha->loop_id = loop_id;
1da177e4
LT		 3995
3996 /* initialize */
3997 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
3998 ha->operating_mode = LOOP;
2c3dfe3f 3999 ha->switch_cap = 0;
1da177e4
LT		 4000
4001 switch (topo) {
4002 case 0:
7c3df132 4003 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 4004 ha->current_topology = ISP_CFG_NL;
4005 strcpy(connect_type, "(Loop)");
4006 break;
4007
4008 case 1:
7c3df132 4009 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 4010 ha->switch_cap = sw_cap;
1da177e4
LT		 4011 ha->current_topology = ISP_CFG_FL;
4012 strcpy(connect_type, "(FL_Port)");
4013 break;
4014
4015 case 2:
7c3df132 4016 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 4017 ha->operating_mode = P2P;
4018 ha->current_topology = ISP_CFG_N;
4019 strcpy(connect_type, "(N_Port-to-N_Port)");
4020 break;
4021
4022 case 3:
7c3df132 4023 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 4024 ha->switch_cap = sw_cap;
1da177e4
LT		 4025 ha->operating_mode = P2P;
4026 ha->current_topology = ISP_CFG_F;
4027 strcpy(connect_type, "(F_Port)");
4028 break;
4029
4030 default:
7c3df132
SK		 4031 ql_dbg(ql_dbg_disc, vha, 0x200f,
4032 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 4033 ha->current_topology = ISP_CFG_NL;
4034 strcpy(connect_type, "(Loop)");
4035 break;
4036 }
4037
4038 /* Save Host port and loop ID. */
4039 /* byte order - Big Endian */
482c9dc7
QT		 4040 id.b.domain = domain;
4041 id.b.area = area;
4042 id.b.al_pa = al_pa;
4043 id.b.rsvd_1 = 0;
9d1aa4e1 4044 spin_lock_irqsave(&ha->hardware_lock, flags);
482c9dc7 4045 qlt_update_host_map(vha, id);
9d1aa4e1 4046 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2d70c103 4047
e315cd28 4048 if (!vha->flags.init_done)
7c3df132
SK		 4049 ql_log(ql_log_info, vha, 0x2010,
4050 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 4051 connect_type, vha->loop_id);
1da177e4 4052
1da177e4
LT		 4053 return(rval);
4054}
4055
a9083016 4056inline void
e315cd28
AC		 4057qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
4058 char *def)
9bb9fcf2
AV		 4059{
4060 char *st, *en;
4061 uint16_t index;
e315cd28 4062 struct qla_hw_data *ha = vha->hw;
ab671149 4063 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 4064 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 4065
4066 if (memcmp(model, BINZERO, len) != 0) {
4067 strncpy(ha->model_number, model, len);
4068 st = en = ha->model_number;
4069 en += len - 1;
4070 while (en > st) {
4071 if (*en != 0x20 && *en != 0x00)
4072 break;
4073 *en-- = '\0';
4074 }
4075
4076 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4077 if (use_tbl &&
4078 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 4079 index < QLA_MODEL_NAMES)
1ee27146
JC		 4080 strncpy(ha->model_desc,
4081 qla2x00_model_name[index * 2 + 1],
4082 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4083 } else {
4084 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4085 if (use_tbl &&
4086 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 4087 index < QLA_MODEL_NAMES) {
4088 strcpy(ha->model_number,
4089 qla2x00_model_name[index * 2]);
1ee27146
JC		 4090 strncpy(ha->model_desc,
4091 qla2x00_model_name[index * 2 + 1],
4092 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4093 } else {
4094 strcpy(ha->model_number, def);
4095 }
4096 }
1ee27146 4097 if (IS_FWI2_CAPABLE(ha))
e315cd28 4098 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 4099 sizeof(ha->model_desc));
9bb9fcf2
AV		 4100}
4101
4e08df3f
DM		 4102/* On sparc systems, obtain port and node WWN from firmware
4103 * properties.
4104 */
e315cd28 4105static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 4106{
4107#ifdef CONFIG_SPARC
e315cd28 4108 struct qla_hw_data *ha = vha->hw;
4e08df3f 4109 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4110 struct device_node *dp = pci_device_to_OF_node(pdev);
4111 const u8 *val;
4e08df3f
DM		 4112 int len;
4113
4114 val = of_get_property(dp, "port-wwn", &len);
4115 if (val && len >= WWN_SIZE)
4116 memcpy(nv->port_name, val, WWN_SIZE);
4117
4118 val = of_get_property(dp, "node-wwn", &len);
4119 if (val && len >= WWN_SIZE)
4120 memcpy(nv->node_name, val, WWN_SIZE);
4121#endif
4122}
4123
1da177e4
LT		 4124/*
4125* NVRAM configuration for ISP 2xxx
4126*
4127* Input:
4128* ha = adapter block pointer.
4129*
4130* Output:
4131* initialization control block in response_ring
4132* host adapters parameters in host adapter block
4133*
4134* Returns:
4135* 0 = success.
4136*/
abbd8870 4137int
e315cd28 4138qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 4139{
4e08df3f 4140 int rval;
0107109e
AV		 4141 uint8_t chksum = 0;
4142 uint16_t cnt;
4143 uint8_t *dptr1, *dptr2;
e315cd28 4144 struct qla_hw_data *ha = vha->hw;
0107109e 4145 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 4146 nvram_t *nv = ha->nvram;
4147 uint8_t *ptr = ha->nvram;
3d71644c 4148 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4149
4e08df3f
DM		 4150 rval = QLA_SUCCESS;
4151
1da177e4 4152 /* Determine NVRAM starting address. */
0107109e 4153 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 4154 ha->nvram_base = 0;
4155 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
4156 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
4157 ha->nvram_base = 0x80;
4158
4159 /* Get NVRAM data and calculate checksum. */
e315cd28 4160 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 4161 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
4162 chksum += *ptr++;
1da177e4 4163
7c3df132
SK		 4164 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
4165 "Contents of NVRAM.\n");
4166 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
4167 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 4168
4169 /* Bad NVRAM data, set defaults parameters. */
4170 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
4171 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
4172 /* Reset NVRAM data. */
7c3df132 4173 ql_log(ql_log_warn, vha, 0x0064,
9e336520 4174 "Inconsistent NVRAM "
7c3df132
SK		 4175 "detected: checksum=0x%x id=%c version=0x%x.\n",
4176 chksum, nv->id[0], nv->nvram_version);
4177 ql_log(ql_log_warn, vha, 0x0065,
4178 "Falling back to "
4179 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 4180
4181 /*
4182 * Set default initialization control block.
4183 */
4184 memset(nv, 0, ha->nvram_size);
4185 nv->parameter_block_version = ICB_VERSION;
4186
4187 if (IS_QLA23XX(ha)) {
4188 nv->firmware_options[0] = BIT_2 | BIT_1;
4189 nv->firmware_options[1] = BIT_7 | BIT_5;
4190 nv->add_firmware_options[0] = BIT_5;
4191 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4192 nv->frame_payload_size = 2048;
4e08df3f
DM		 4193 nv->special_options[1] = BIT_7;
4194 } else if (IS_QLA2200(ha)) {
4195 nv->firmware_options[0] = BIT_2 | BIT_1;
4196 nv->firmware_options[1] = BIT_7 | BIT_5;
4197 nv->add_firmware_options[0] = BIT_5;
4198 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4199 nv->frame_payload_size = 1024;
4e08df3f
DM		 4200 } else if (IS_QLA2100(ha)) {
4201 nv->firmware_options[0] = BIT_3 | BIT_1;
4202 nv->firmware_options[1] = BIT_5;
98aee70d 4203 nv->frame_payload_size = 1024;
4e08df3f
DM		 4204 }
4205
ad950360
BVA		 4206 nv->max_iocb_allocation = cpu_to_le16(256);
4207 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 4208 nv->retry_count = 8;
4209 nv->retry_delay = 1;
4210
4211 nv->port_name[0] = 33;
4212 nv->port_name[3] = 224;
4213 nv->port_name[4] = 139;
4214
e315cd28 4215 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4216
4217 nv->login_timeout = 4;
4218
4219 /*
4220 * Set default host adapter parameters
4221 */
4222 nv->host_p[1] = BIT_2;
4223 nv->reset_delay = 5;
4224 nv->port_down_retry_count = 8;
ad950360 4225 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 4226 nv->link_down_timeout = 60;
4227
4228 rval = 1;
1da177e4
LT		 4229 }
4230
4231#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
4232 /*
4233 * The SN2 does not provide BIOS emulation which means you can't change
4234 * potentially bogus BIOS settings. Force the use of default settings
4235 * for link rate and frame size. Hope that the rest of the settings
4236 * are valid.
4237 */
4238 if (ia64_platform_is("sn2")) {
98aee70d 4239 nv->frame_payload_size = 2048;
1da177e4
LT		 4240 if (IS_QLA23XX(ha))
4241 nv->special_options[1] = BIT_7;
4242 }
4243#endif
4244
4245 /* Reset Initialization control block */
0107109e 4246 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 4247
4248 /*
4249 * Setup driver NVRAM options.
4250 */
4251 nv->firmware_options[0] |= (BIT_6 | BIT_1);
4252 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
4253 nv->firmware_options[1] |= (BIT_5 | BIT_0);
4254 nv->firmware_options[1] &= ~BIT_4;
4255
4256 if (IS_QLA23XX(ha)) {
4257 nv->firmware_options[0] |= BIT_2;
4258 nv->firmware_options[0] &= ~BIT_3;
2d70c103 4259 nv->special_options[0] &= ~BIT_6;
0107109e 4260 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 4261
4262 if (IS_QLA2300(ha)) {
4263 if (ha->fb_rev == FPM_2310) {
4264 strcpy(ha->model_number, "QLA2310");
4265 } else {
4266 strcpy(ha->model_number, "QLA2300");
4267 }
4268 } else {
e315cd28 4269 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 4270 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 4271 }
4272 } else if (IS_QLA2200(ha)) {
4273 nv->firmware_options[0] |= BIT_2;
4274 /*
4275 * 'Point-to-point preferred, else loop' is not a safe
4276 * connection mode setting.
4277 */
4278 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
4279 (BIT_5 | BIT_4)) {
4280 /* Force 'loop preferred, else point-to-point'. */
4281 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
4282 nv->add_firmware_options[0] |= BIT_5;
4283 }
4284 strcpy(ha->model_number, "QLA22xx");
4285 } else /*if (IS_QLA2100(ha))*/ {
4286 strcpy(ha->model_number, "QLA2100");
4287 }
4288
4289 /*
4290 * Copy over NVRAM RISC parameter block to initialization control block.
4291 */
4292 dptr1 = (uint8_t *)icb;
4293 dptr2 = (uint8_t *)&nv->parameter_block_version;
4294 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
4295 while (cnt--)
4296 *dptr1++ = *dptr2++;
4297
4298 /* Copy 2nd half. */
4299 dptr1 = (uint8_t *)icb->add_firmware_options;
4300 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4301 while (cnt--)
4302 *dptr1++ = *dptr2++;
4303
5341e868
AV		 4304 /* Use alternate WWN? */
4305 if (nv->host_p[1] & BIT_7) {
4306 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4307 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4308 }
4309
1da177e4
LT		 4310 /* Prepare nodename */
4311 if ((icb->firmware_options[1] & BIT_6) == 0) {
4312 /*
4313 * Firmware will apply the following mask if the nodename was
4314 * not provided.
4315 */
4316 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4317 icb->node_name[0] &= 0xF0;
4318 }
4319
4320 /*
4321 * Set host adapter parameters.
4322 */
3ce8866c
SK		 4323
4324 /*
4325 * BIT_7 in the host-parameters section allows for modification to
4326 * internal driver logging.
4327 */
0181944f 4328 if (nv->host_p[0] & BIT_7)
cfb0919c 4329 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 4330 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4331 /* Always load RISC code on non ISP2[12]00 chips. */
4332 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4333 ha->flags.disable_risc_code_load = 0;
4334 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4335 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4336 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 4337 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 4338 ha->flags.disable_serdes = 0;
1da177e4
LT		 4339
4340 ha->operating_mode =
4341 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4342
4343 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4344 sizeof(ha->fw_seriallink_options));
4345
4346 /* save HBA serial number */
4347 ha->serial0 = icb->port_name[5];
4348 ha->serial1 = icb->port_name[6];
4349 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4350 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4351 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 4352
ad950360 4353 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 4354
4355 ha->retry_count = nv->retry_count;
4356
4357 /* Set minimum login_timeout to 4 seconds. */
5b91490e 4358 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 4359 nv->login_timeout = ql2xlogintimeout;
4360 if (nv->login_timeout < 4)
4361 nv->login_timeout = 4;
4362 ha->login_timeout = nv->login_timeout;
1da177e4 4363
00a537b8
AV		 4364 /* Set minimum RATOV to 100 tenths of a second. */
4365 ha->r_a_tov = 100;
1da177e4 4366
1da177e4
LT		 4367 ha->loop_reset_delay = nv->reset_delay;
4368
1da177e4
LT		 4369 /* Link Down Timeout = 0:
4370 *
4371 * When Port Down timer expires we will start returning
4372 * I/O's to OS with "DID_NO_CONNECT".
4373 *
4374 * Link Down Timeout != 0:
4375 *
4376 * The driver waits for the link to come up after link down
4377 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 4378 */
1da177e4
LT		 4379 if (nv->link_down_timeout == 0) {
4380 ha->loop_down_abort_time =
354d6b21 4381 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 4382 } else {
4383 ha->link_down_timeout = nv->link_down_timeout;
4384 ha->loop_down_abort_time =
4385 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 4386 }
1da177e4 4387
1da177e4
LT		 4388 /*
4389 * Need enough time to try and get the port back.
4390 */
4391 ha->port_down_retry_count = nv->port_down_retry_count;
4392 if (qlport_down_retry)
4393 ha->port_down_retry_count = qlport_down_retry;
4394 /* Set login_retry_count */
4395 ha->login_retry_count = nv->retry_count;
4396 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4397 ha->port_down_retry_count > 3)
4398 ha->login_retry_count = ha->port_down_retry_count;
4399 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4400 ha->login_retry_count = ha->port_down_retry_count;
4401 if (ql2xloginretrycount)
4402 ha->login_retry_count = ql2xloginretrycount;
4403
ad950360 4404 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 4405 icb->command_resource_count = 0;
4406 icb->immediate_notify_resource_count = 0;
ad950360 4407 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 4408
4409 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4410 /* Enable RIO */
4411 icb->firmware_options[0] &= ~BIT_3;
4412 icb->add_firmware_options[0] &=
4413 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4414 icb->add_firmware_options[0] |= BIT_2;
4415 icb->response_accumulation_timer = 3;
4416 icb->interrupt_delay_timer = 5;
4417
e315cd28 4418 vha->flags.process_response_queue = 1;
1da177e4 4419 } else {
4fdfefe5 4420 /* Enable ZIO. */
e315cd28 4421 if (!vha->flags.init_done) {
4fdfefe5
AV		 4422 ha->zio_mode = icb->add_firmware_options[0] &
4423 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4424 ha->zio_timer = icb->interrupt_delay_timer ?
4425 icb->interrupt_delay_timer: 2;
4426 }
1da177e4
LT		 4427 icb->add_firmware_options[0] &=
4428 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 4429 vha->flags.process_response_queue = 0;
4fdfefe5 4430 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4431 ha->zio_mode = QLA_ZIO_MODE_6;
4432
7c3df132 4433 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 4434 "ZIO mode %d enabled; timer delay (%d us).\n",
4435 ha->zio_mode, ha->zio_timer * 100);
1da177e4 4436
4fdfefe5
AV		 4437 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4438 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 4439 vha->flags.process_response_queue = 1;
1da177e4
LT		 4440 }
4441 }
4442
4e08df3f 4443 if (rval) {
7c3df132
SK		 4444 ql_log(ql_log_warn, vha, 0x0069,
4445 "NVRAM configuration failed.\n");
4e08df3f
DM		 4446 }
4447 return (rval);
1da177e4
LT		 4448}
4449
19a7b4ae
JSEC		 4450static void
4451qla2x00_rport_del(void *data)
4452{
4453 fc_port_t *fcport = data;
d97994dc 4454 struct fc_rport *rport;
044d78e1 4455 unsigned long flags;
d97994dc 4456
044d78e1 4457 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 4458 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 4459 fcport->drport = NULL;
044d78e1 4460 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548 4461 if (rport) {
83548fe2
QT		 4462 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4463 "%s %8phN. rport %p roles %x\n",
4464 __func__, fcport->port_name, rport,
4465 rport->roles);
726b8548 4466
d97994dc 4467 fc_remote_port_delete(rport);
726b8548 4468 }
19a7b4ae
JSEC		 4469}
4470
1da177e4
LT		 4471/**
4472 * qla2x00_alloc_fcport() - Allocate a generic fcport.
4473 * @ha: HA context
4474 * @flags: allocation flags
4475 *
4476 * Returns a pointer to the allocated fcport, or NULL, if none available.
4477 */
9a069e19 4478fc_port_t *
e315cd28 4479qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 4480{
4481 fc_port_t *fcport;
4482
bbfbbbc1
MK		 4483 fcport = kzalloc(sizeof(fc_port_t), flags);
4484 if (!fcport)
4485 return NULL;
1da177e4
LT		 4486
4487 /* Setup fcport template structure. */
e315cd28 4488 fcport->vha = vha;
1da177e4
LT		 4489 fcport->port_type = FCT_UNKNOWN;
4490 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 4491 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 4492 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 4493
726b8548
QT		 4494 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
4495 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 4496 flags);
726b8548
QT		 4497 fcport->disc_state = DSC_DELETED;
4498 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4499 fcport->deleted = QLA_SESS_DELETED;
4500 fcport->login_retry = vha->hw->login_retry_count;
4501 fcport->login_retry = 5;
4502 fcport->logout_on_delete = 1;
4503
4504 if (!fcport->ct_desc.ct_sns) {
83548fe2 4505 ql_log(ql_log_warn, vha, 0xd049,
726b8548
QT		 4506 "Failed to allocate ct_sns request.\n");
4507 kfree(fcport);
4508 fcport = NULL;
4509 }
4510 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
4511 INIT_LIST_HEAD(&fcport->gnl_entry);
4512 INIT_LIST_HEAD(&fcport->list);
4513
bbfbbbc1 4514 return fcport;
1da177e4
LT		 4515}
4516
726b8548
QT		 4517void
4518qla2x00_free_fcport(fc_port_t *fcport)
4519{
4520 if (fcport->ct_desc.ct_sns) {
4521 dma_free_coherent(&fcport->vha->hw->pdev->dev,
4522 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
4523 fcport->ct_desc.ct_sns_dma);
4524
4525 fcport->ct_desc.ct_sns = NULL;
4526 }
4527 kfree(fcport);
4528}
4529
1da177e4
LT		 4530/*
4531 * qla2x00_configure_loop
4532 * Updates Fibre Channel Device Database with what is actually on loop.
4533 *
4534 * Input:
4535 * ha = adapter block pointer.
4536 *
4537 * Returns:
4538 * 0 = success.
4539 * 1 = error.
4540 * 2 = database was full and device was not configured.
4541 */
4542static int
e315cd28 4543qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4544{
4545 int rval;
4546 unsigned long flags, save_flags;
e315cd28 4547 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4548 rval = QLA_SUCCESS;
4549
4550 /* Get Initiator ID */
e315cd28
AC		 4551 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
4552 rval = qla2x00_configure_hba(vha);
1da177e4 4553 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4554 ql_dbg(ql_dbg_disc, vha, 0x2013,
4555 "Unable to configure HBA.\n");
1da177e4
LT		 4556 return (rval);
4557 }
4558 }
4559
e315cd28 4560 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 4561 ql_dbg(ql_dbg_disc, vha, 0x2014,
4562 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 4563
4564 /*
4565 * If we have both an RSCN and PORT UPDATE pending then handle them
4566 * both at the same time.
4567 */
e315cd28
AC		 4568 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4569 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 4570
3064ff39
MH		 4571 qla2x00_get_data_rate(vha);
4572
1da177e4
LT		 4573 /* Determine what we need to do */
4574 if (ha->current_topology == ISP_CFG_FL &&
4575 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4576
1da177e4
LT		 4577 set_bit(RSCN_UPDATE, &flags);
4578
4579 } else if (ha->current_topology == ISP_CFG_F &&
4580 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4581
1da177e4
LT		 4582 set_bit(RSCN_UPDATE, &flags);
4583 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4584
4585 } else if (ha->current_topology == ISP_CFG_N) {
4586 clear_bit(RSCN_UPDATE, &flags);
9cd883f0
QT		 4587 if (ha->flags.rida_fmt2) {
4588 /* With Rida Format 2, the login is already triggered.
4589 * We know who is on the other side of the wire.
4590 * No need to login to do login to find out or drop into
4591 * qla2x00_configure_local_loop().
4592 */
4593 clear_bit(LOCAL_LOOP_UPDATE, &flags);
4594 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4595 } else {
4596 if (qla_tgt_mode_enabled(vha)) {
4597 /* allow the other side to start the login */
4598 clear_bit(LOCAL_LOOP_UPDATE, &flags);
4599 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4600 }
4601 }
41dc529a
QT		 4602 } else if (ha->current_topology == ISP_CFG_NL) {
4603 clear_bit(RSCN_UPDATE, &flags);
4604 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4605 } else if (!vha->flags.online ||
1da177e4 4606 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 4607 set_bit(RSCN_UPDATE, &flags);
4608 set_bit(LOCAL_LOOP_UPDATE, &flags);
4609 }
4610
4611 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 4612 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
4613 ql_dbg(ql_dbg_disc, vha, 0x2015,
4614 "Loop resync needed, failing.\n");
1da177e4 4615 rval = QLA_FUNCTION_FAILED;
642ef983 4616 } else
e315cd28 4617 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 4618 }
4619
4620 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132 4621 if (LOOP_TRANSITION(vha)) {
83548fe2 4622 ql_dbg(ql_dbg_disc, vha, 0x2099,
7c3df132 4623 "Needs RSCN update and loop transition.\n");
1da177e4 4624 rval = QLA_FUNCTION_FAILED;
7c3df132 4625 }
e315cd28
AC		 4626 else
4627 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 4628 }
4629
4630 if (rval == QLA_SUCCESS) {
e315cd28
AC		 4631 if (atomic_read(&vha->loop_down_timer) ||
4632 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4633 rval = QLA_FUNCTION_FAILED;
4634 } else {
e315cd28 4635 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4636 ql_dbg(ql_dbg_disc, vha, 0x2069,
4637 "LOOP READY.\n");
ec7193e2 4638 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 4639
4640 /*
4641 * Process any ATIO queue entries that came in
4642 * while we weren't online.
4643 */
ead03855
QT		 4644 if (qla_tgt_mode_enabled(vha) ||
4645 qla_dual_mode_enabled(vha)) {
3bb67df5
DKU		 4646 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
4647 spin_lock_irqsave(&ha->tgt.atio_lock,
4648 flags);
4649 qlt_24xx_process_atio_queue(vha, 0);
4650 spin_unlock_irqrestore(
4651 &ha->tgt.atio_lock, flags);
4652 } else {
4653 spin_lock_irqsave(&ha->hardware_lock,
4654 flags);
4655 qlt_24xx_process_atio_queue(vha, 1);
4656 spin_unlock_irqrestore(
4657 &ha->hardware_lock, flags);
4658 }
4659 }
1da177e4
LT		 4660 }
4661 }
4662
4663 if (rval) {
7c3df132
SK		 4664 ql_dbg(ql_dbg_disc, vha, 0x206a,
4665 "%s *** FAILED ***.\n", __func__);
1da177e4 4666 } else {
7c3df132
SK		 4667 ql_dbg(ql_dbg_disc, vha, 0x206b,
4668 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4669 }
4670
cc3ef7bc 4671 /* Restore state if a resync event occurred during processing */
e315cd28 4672 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4673 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4674 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4675 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4676 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4677 }
1da177e4
LT		 4678 }
4679
4680 return (rval);
4681}
4682
edd05de1
DG		 4683/*
4684 * N2N Login
4685 * Updates Fibre Channel Device Database with local loop devices.
4686 *
4687 * Input:
4688 * ha = adapter block pointer.
4689 *
4690 * Returns:
4691 */
4692static int qla24xx_n2n_handle_login(struct scsi_qla_host *vha,
4693 fc_port_t *fcport)
4694{
4695 struct qla_hw_data *ha = vha->hw;
4696 int res = QLA_SUCCESS, rval;
4697 int greater_wwpn = 0;
4698 int logged_in = 0;
4699
4700 if (ha->current_topology != ISP_CFG_N)
4701 return res;
4702
4703 if (wwn_to_u64(vha->port_name) >
4704 wwn_to_u64(vha->n2n_port_name)) {
4705 ql_dbg(ql_dbg_disc, vha, 0x2002,
4706 "HBA WWPN is greater %llx > target %llx\n",
4707 wwn_to_u64(vha->port_name),
4708 wwn_to_u64(vha->n2n_port_name));
4709 greater_wwpn = 1;
4710 fcport->d_id.b24 = vha->n2n_id;
4711 }
4712
4713 fcport->loop_id = vha->loop_id;
4714 fcport->fc4f_nvme = 0;
4715 fcport->query = 1;
4716
4717 ql_dbg(ql_dbg_disc, vha, 0x4001,
4718 "Initiate N2N login handler: HBA port_id=%06x loopid=%d\n",
4719 fcport->d_id.b24, vha->loop_id);
4720
4721 /* Fill in member data. */
4722 if (!greater_wwpn) {
4723 rval = qla2x00_get_port_database(vha, fcport, 0);
4724 ql_dbg(ql_dbg_disc, vha, 0x1051,
4725 "Remote login-state (%x/%x) port_id=%06x loop_id=%x, rval=%d\n",
4726 fcport->current_login_state, fcport->last_login_state,
4727 fcport->d_id.b24, fcport->loop_id, rval);
4728
4729 if (((fcport->current_login_state & 0xf) == 0x4) ||
4730 ((fcport->current_login_state & 0xf) == 0x6))
4731 logged_in = 1;
4732 }
4733
4734 if (logged_in || greater_wwpn) {
4735 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
4736 qla_nvme_register_hba(vha);
4737
4738 /* Set connected N_Port d_id */
4739 if (vha->flags.nvme_enabled)
4740 fcport->fc4f_nvme = 1;
4741
4742 fcport->scan_state = QLA_FCPORT_FOUND;
4743 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4744 fcport->disc_state = DSC_GNL;
4745 fcport->n2n_flag = 1;
4746 fcport->flags = 3;
4747 vha->hw->flags.gpsc_supported = 0;
4748
4749 if (greater_wwpn) {
4750 ql_dbg(ql_dbg_disc, vha, 0x20e5,
4751 "%s %d PLOGI ELS %8phC\n",
4752 __func__, __LINE__, fcport->port_name);
4753
4754 res = qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
4755 fcport, fcport->d_id);
4756 }
4757
4758 if (res != QLA_SUCCESS) {
4759 ql_log(ql_log_info, vha, 0xd04d,
4760 "PLOGI Failed: portid=%06x - retrying\n",
4761 fcport->d_id.b24);
4762 res = QLA_SUCCESS;
4763 } else {
4764 /* State 0x6 means FCP PRLI complete */
4765 if ((fcport->current_login_state & 0xf) == 0x6) {
4766 ql_dbg(ql_dbg_disc, vha, 0x2118,
4767 "%s %d %8phC post GPDB work\n",
4768 __func__, __LINE__, fcport->port_name);
4769 fcport->chip_reset =
4770 vha->hw->base_qpair->chip_reset;
4771 qla24xx_post_gpdb_work(vha, fcport, 0);
4772 } else {
4773 ql_dbg(ql_dbg_disc, vha, 0x2118,
4774 "%s %d %8phC post NVMe PRLI\n",
4775 __func__, __LINE__, fcport->port_name);
4776 qla24xx_post_prli_work(vha, fcport);
4777 }
4778 }
4779 } else {
4780 /* Wait for next database change */
4781 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
4782 }
1da177e4 4783
edd05de1
DG		 4784 return res;
4785}
1da177e4
LT		 4786
4787/*
4788 * qla2x00_configure_local_loop
4789 * Updates Fibre Channel Device Database with local loop devices.
4790 *
4791 * Input:
4792 * ha = adapter block pointer.
4793 *
4794 * Returns:
4795 * 0 = success.
4796 */
4797static int
e315cd28 4798qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4799{
4800 int rval, rval2;
4801 int found_devs;
4802 int found;
4803 fc_port_t *fcport, *new_fcport;
4804
4805 uint16_t index;
4806 uint16_t entries;
4807 char *id_iter;
4808 uint16_t loop_id;
4809 uint8_t domain, area, al_pa;
e315cd28 4810 struct qla_hw_data *ha = vha->hw;
41dc529a 4811 unsigned long flags;
1da177e4
LT		 4812
4813 found_devs = 0;
4814 new_fcport = NULL;
642ef983 4815 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4816
1da177e4 4817 /* Get list of logged in devices. */
642ef983 4818 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4819 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4820 &entries);
4821 if (rval != QLA_SUCCESS)
4822 goto cleanup_allocation;
4823
83548fe2 4824 ql_dbg(ql_dbg_disc, vha, 0x2011,
7c3df132
SK		 4825 "Entries in ID list (%d).\n", entries);
4826 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4827 (uint8_t *)ha->gid_list,
4828 entries * sizeof(struct gid_list_info));
1da177e4 4829
9cd883f0
QT		 4830 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4831 fcport->scan_state = QLA_FCPORT_SCAN;
4832 }
4833
1da177e4 4834 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4835 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4836 if (new_fcport == NULL) {
83548fe2 4837 ql_log(ql_log_warn, vha, 0x2012,
7c3df132 4838 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4839 rval = QLA_MEMORY_ALLOC_FAILED;
4840 goto cleanup_allocation;
4841 }
4842 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4843
edd05de1
DG		 4844 /* Inititae N2N login. */
4845 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) {
4846 rval = qla24xx_n2n_handle_login(vha, new_fcport);
4847 if (rval != QLA_SUCCESS)
4848 goto cleanup_allocation;
4849 return QLA_SUCCESS;
4850 }
4851
1da177e4
LT		 4852 /* Add devices to port list. */
4853 id_iter = (char *)ha->gid_list;
4854 for (index = 0; index < entries; index++) {
4855 domain = ((struct gid_list_info *)id_iter)->domain;
4856 area = ((struct gid_list_info *)id_iter)->area;
4857 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4858 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4859 loop_id = (uint16_t)
4860 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4861 else
1da177e4
LT		 4862 loop_id = le16_to_cpu(
4863 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4864 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4865
4866 /* Bypass reserved domain fields. */
4867 if ((domain & 0xf0) == 0xf0)
4868 continue;
4869
4870 /* Bypass if not same domain and area of adapter. */
f7d289f6 4871 if (area && domain &&
e315cd28 4872 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4873 continue;
4874
4875 /* Bypass invalid local loop ID. */
4876 if (loop_id > LAST_LOCAL_LOOP_ID)
4877 continue;
4878
41dc529a 4879 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 4880
1da177e4
LT		 4881 /* Fill in member data. */
4882 new_fcport->d_id.b.domain = domain;
4883 new_fcport->d_id.b.area = area;
4884 new_fcport->d_id.b.al_pa = al_pa;
4885 new_fcport->loop_id = loop_id;
9cd883f0 4886 new_fcport->scan_state = QLA_FCPORT_FOUND;
41dc529a 4887
e315cd28 4888 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 4889 if (rval2 != QLA_SUCCESS) {
83548fe2 4890 ql_dbg(ql_dbg_disc, vha, 0x2097,
7c3df132
SK		 4891 "Failed to retrieve fcport information "
4892 "-- get_port_database=%x, loop_id=0x%04x.\n",
4893 rval2, new_fcport->loop_id);
edd05de1
DG		 4894 /* Skip retry if N2N */
4895 if (ha->current_topology != ISP_CFG_N) {
4896 ql_dbg(ql_dbg_disc, vha, 0x2105,
4897 "Scheduling resync.\n");
4898 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4899 continue;
4900 }
1da177e4
LT		 4901 }
4902
41dc529a 4903 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4904 /* Check for matching device in port list. */
4905 found = 0;
4906 fcport = NULL;
e315cd28 4907 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4908 if (memcmp(new_fcport->port_name, fcport->port_name,
4909 WWN_SIZE))
4910 continue;
4911
ddb9b126 4912 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 4913 fcport->loop_id = new_fcport->loop_id;
4914 fcport->port_type = new_fcport->port_type;
4915 fcport->d_id.b24 = new_fcport->d_id.b24;
4916 memcpy(fcport->node_name, new_fcport->node_name,
4917 WWN_SIZE);
9cd883f0 4918 fcport->scan_state = QLA_FCPORT_FOUND;
1da177e4
LT		 4919 found++;
4920 break;
4921 }
4922
4923 if (!found) {
4924 /* New device, add to fcports list. */
e315cd28 4925 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 4926
4927 /* Allocate a new replacement fcport. */
4928 fcport = new_fcport;
41dc529a
QT		 4929
4930 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4931
e315cd28 4932 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 4933
1da177e4 4934 if (new_fcport == NULL) {
83548fe2 4935 ql_log(ql_log_warn, vha, 0xd031,
7c3df132 4936 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4937 rval = QLA_MEMORY_ALLOC_FAILED;
4938 goto cleanup_allocation;
4939 }
41dc529a 4940 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4941 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4942 }
4943
41dc529a
QT		 4944 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4945
d8b45213 4946 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 4947 fcport->fp_speed = ha->link_data_rate;
d8b45213 4948
1da177e4
LT		 4949 found_devs++;
4950 }
4951
9cd883f0
QT		 4952 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4953 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4954 break;
4955
4956 if (fcport->scan_state == QLA_FCPORT_SCAN) {
4957 if ((qla_dual_mode_enabled(vha) ||
4958 qla_ini_mode_enabled(vha)) &&
4959 atomic_read(&fcport->state) == FCS_ONLINE) {
4960 qla2x00_mark_device_lost(vha, fcport,
4961 ql2xplogiabsentdevice, 0);
4962 if (fcport->loop_id != FC_NO_LOOP_ID &&
4963 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
4964 fcport->port_type != FCT_INITIATOR &&
4965 fcport->port_type != FCT_BROADCAST) {
4966 ql_dbg(ql_dbg_disc, vha, 0x20f0,
4967 "%s %d %8phC post del sess\n",
4968 __func__, __LINE__,
4969 fcport->port_name);
4970
d8630bb9 4971 qlt_schedule_sess_for_deletion(fcport);
9cd883f0
QT		 4972 continue;
4973 }
4974 }
4975 }
4976
4977 if (fcport->scan_state == QLA_FCPORT_FOUND)
4978 qla24xx_fcport_handle_login(vha, fcport);
4979 }
4980
1da177e4 4981cleanup_allocation:
c9475cb0 4982 kfree(new_fcport);
1da177e4
LT		 4983
4984 if (rval != QLA_SUCCESS) {
83548fe2 4985 ql_dbg(ql_dbg_disc, vha, 0x2098,
7c3df132 4986 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 4987 }
4988
1da177e4
LT		 4989 return (rval);
4990}
4991
d8b45213 4992static void
e315cd28 4993qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 4994{
d8b45213 4995 int rval;
93f2bd67 4996 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4997 struct qla_hw_data *ha = vha->hw;
d8b45213 4998
c76f2c01 4999 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 5000 return;
5001
c9afb9a2
GM		 5002 if (atomic_read(&fcport->state) != FCS_ONLINE)
5003 return;
5004
39bd9622
AV		 5005 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
5006 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 5007 return;
5008
e315cd28 5009 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 5010 mb);
d8b45213 5011 if (rval != QLA_SUCCESS) {
7c3df132 5012 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 5013 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
5014 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 5015 } else {
7c3df132 5016 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 5017 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 5018 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 5019 fcport->port_name);
d8b45213
AV		 5020 }
5021}
5022
726b8548 5023/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 5024static void
e315cd28 5025qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 5026{
5027 struct fc_rport_identifiers rport_ids;
bdf79621 5028 struct fc_rport *rport;
044d78e1 5029 unsigned long flags;
8482e118 5030
f8b02a85
AV		 5031 rport_ids.node_name = wwn_to_u64(fcport->node_name);
5032 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 5033 rport_ids.port_id = fcport->d_id.b.domain << 16 |
5034 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 5035 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 5036 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 5037 if (!rport) {
7c3df132
SK		 5038 ql_log(ql_log_warn, vha, 0x2006,
5039 "Unable to allocate fc remote port.\n");
77d74143
AV		 5040 return;
5041 }
2d70c103 5042
044d78e1 5043 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 5044 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 5045 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 5046
ad3e0eda 5047 rport->supported_classes = fcport->supported_classes;
77d74143 5048
8482e118 5049 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
5050 if (fcport->port_type == FCT_INITIATOR)
5051 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
5052 if (fcport->port_type == FCT_TARGET)
5053 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548 5054
83548fe2
QT		 5055 ql_dbg(ql_dbg_disc, vha, 0x20ee,
5056 "%s %8phN. rport %p is %s mode\n",
5057 __func__, fcport->port_name, rport,
5058 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
726b8548 5059
77d74143 5060 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 5061}
5062
23be331d
AB		 5063/*
5064 * qla2x00_update_fcport
5065 * Updates device on list.
5066 *
5067 * Input:
5068 * ha = adapter block pointer.
5069 * fcport = port structure pointer.
5070 *
5071 * Return:
5072 * 0 - Success
5073 * BIT_0 - error
5074 *
5075 * Context:
5076 * Kernel context.
5077 */
5078void
e315cd28 5079qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 5080{
e315cd28 5081 fcport->vha = vha;
8ae6d9c7 5082
726b8548
QT		 5083 if (IS_SW_RESV_ADDR(fcport->d_id))
5084 return;
5085
83548fe2 5086 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
726b8548
QT		 5087 __func__, fcport->port_name);
5088
8ae6d9c7
GM		 5089 if (IS_QLAFX00(vha->hw)) {
5090 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 5091 goto reg_port;
8ae6d9c7 5092 }
23be331d 5093 fcport->login_retry = 0;
5ff1d584 5094 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
726b8548
QT		 5095 fcport->disc_state = DSC_LOGIN_COMPLETE;
5096 fcport->deleted = 0;
5097 fcport->logout_on_delete = 1;
23be331d 5098
e84067d7
DG		 5099 if (fcport->fc4f_nvme) {
5100 qla_nvme_register_remote(vha, fcport);
5101 return;
5102 }
5103
1f93da52 5104 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 5105 qla2x00_iidma_fcport(vha, fcport);
21090cbe 5106 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 5107
5108reg_port:
726b8548
QT		 5109 switch (vha->host->active_mode) {
5110 case MODE_INITIATOR:
d20ed91b 5111 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5112 break;
5113 case MODE_TARGET:
5114 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5115 !vha->vha_tgt.qla_tgt->tgt_stopped)
5116 qlt_fc_port_added(vha, fcport);
5117 break;
5118 case MODE_DUAL:
d20ed91b 5119 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5120 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5121 !vha->vha_tgt.qla_tgt->tgt_stopped)
5122 qlt_fc_port_added(vha, fcport);
5123 break;
5124 default:
5125 break;
d20ed91b 5126 }
23be331d
AB		 5127}
5128
1da177e4
LT		 5129/*
5130 * qla2x00_configure_fabric
5131 * Setup SNS devices with loop ID's.
5132 *
5133 * Input:
5134 * ha = adapter block pointer.
5135 *
5136 * Returns:
5137 * 0 = success.
5138 * BIT_0 = error
5139 */
5140static int
e315cd28 5141qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 5142{
b3b02e6e 5143 int rval;
726b8548 5144 fc_port_t *fcport;
1da177e4 5145 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 5146 uint16_t loop_id;
1da177e4 5147 LIST_HEAD(new_fcports);
e315cd28 5148 struct qla_hw_data *ha = vha->hw;
df673274 5149 int discovery_gen;
1da177e4
LT		 5150
5151 /* If FL port exists, then SNS is present */
e428924c 5152 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 5153 loop_id = NPH_F_PORT;
5154 else
5155 loop_id = SNS_FL_PORT;
e315cd28 5156 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 5157 if (rval != QLA_SUCCESS) {
83548fe2 5158 ql_dbg(ql_dbg_disc, vha, 0x20a0,
7c3df132 5159 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 5160
e315cd28 5161 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 5162 return (QLA_SUCCESS);
5163 }
e315cd28 5164 vha->device_flags |= SWITCH_FOUND;
1da177e4 5165
41dc529a
QT		 5166
5167 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
5168 rval = qla2x00_send_change_request(vha, 0x3, 0);
5169 if (rval != QLA_SUCCESS)
5170 ql_log(ql_log_warn, vha, 0x121,
5171 "Failed to enable receiving of RSCN requests: 0x%x.\n",
5172 rval);
5173 }
5174
5175
1da177e4 5176 do {
726b8548
QT		 5177 qla2x00_mgmt_svr_login(vha);
5178
cca5335c
AV		 5179 /* FDMI support. */
5180 if (ql2xfdmienable &&
e315cd28
AC		 5181 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
5182 qla2x00_fdmi_register(vha);
cca5335c 5183
1da177e4 5184 /* Ensure we are logged into the SNS. */
a14c7711 5185 loop_id = NPH_SNS_LID(ha);
0b91d116
CD		 5186 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
5187 0xfc, mb, BIT_1|BIT_0);
a14c7711
JC		 5188 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5189 ql_dbg(ql_dbg_disc, vha, 0x20a1,
5190 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
5191 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
0b91d116 5192 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 5193 return rval;
0b91d116 5194 }
e315cd28
AC		 5195 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
5196 if (qla2x00_rft_id(vha)) {
1da177e4 5197 /* EMPTY */
83548fe2 5198 ql_dbg(ql_dbg_disc, vha, 0x20a2,
7c3df132 5199 "Register FC-4 TYPE failed.\n");
b98ae0d7
QT		 5200 if (test_bit(LOOP_RESYNC_NEEDED,
5201 &vha->dpc_flags))
5202 break;
1da177e4 5203 }
d3bae931 5204 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
1da177e4 5205 /* EMPTY */
83548fe2 5206 ql_dbg(ql_dbg_disc, vha, 0x209a,
7c3df132 5207 "Register FC-4 Features failed.\n");
b98ae0d7
QT		 5208 if (test_bit(LOOP_RESYNC_NEEDED,
5209 &vha->dpc_flags))
5210 break;
1da177e4 5211 }
d3bae931
DG		 5212 if (vha->flags.nvme_enabled) {
5213 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
5214 ql_dbg(ql_dbg_disc, vha, 0x2049,
5215 "Register NVME FC Type Features failed.\n");
5216 }
5217 }
e315cd28 5218 if (qla2x00_rnn_id(vha)) {
1da177e4 5219 /* EMPTY */
83548fe2 5220 ql_dbg(ql_dbg_disc, vha, 0x2104,
7c3df132 5221 "Register Node Name failed.\n");
b98ae0d7
QT		 5222 if (test_bit(LOOP_RESYNC_NEEDED,
5223 &vha->dpc_flags))
5224 break;
e315cd28 5225 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 5226 /* EMPTY */
83548fe2 5227 ql_dbg(ql_dbg_disc, vha, 0x209b,
0bf0efa1 5228 "Register Symbolic Node Name failed.\n");
b98ae0d7
QT		 5229 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5230 break;
1da177e4
LT		 5231 }
5232 }
5233
827210ba 5234
df673274
AP		 5235 /* Mark the time right before querying FW for connected ports.
5236 * This process is long, asynchronous and by the time it's done,
5237 * collected information might not be accurate anymore. E.g.
5238 * disconnected port might have re-connected and a brand new
5239 * session has been created. In this case session's generation
5240 * will be newer than discovery_gen. */
5241 qlt_do_generation_tick(vha, &discovery_gen);
5242
a4239945
QT		 5243 if (USE_ASYNC_SCAN(ha)) {
5244 rval = QLA_SUCCESS;
5245 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI);
5246 if (rval)
5247 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5248 } else {
f352eeb7
QT		 5249 list_for_each_entry(fcport, &vha->vp_fcports, list)
5250 fcport->scan_state = QLA_FCPORT_SCAN;
5251
a4239945
QT		 5252 rval = qla2x00_find_all_fabric_devs(vha);
5253 }
1da177e4
LT		 5254 if (rval != QLA_SUCCESS)
5255 break;
1da177e4
LT		 5256 } while (0);
5257
e84067d7
DG		 5258 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
5259 qla_nvme_register_hba(vha);
5260
726b8548 5261 if (rval)
7c3df132
SK		 5262 ql_dbg(ql_dbg_disc, vha, 0x2068,
5263 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 5264
5265 return (rval);
5266}
5267
1da177e4
LT		 5268/*
5269 * qla2x00_find_all_fabric_devs
5270 *
5271 * Input:
5272 * ha = adapter block pointer.
5273 * dev = database device entry pointer.
5274 *
5275 * Returns:
5276 * 0 = success.
5277 *
5278 * Context:
5279 * Kernel context.
5280 */
5281static int
726b8548 5282qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 5283{
5284 int rval;
5285 uint16_t loop_id;
726b8548 5286 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 5287 int found;
5288
5289 sw_info_t *swl;
5290 int swl_idx;
5291 int first_dev, last_dev;
1516ef44 5292 port_id_t wrap = {}, nxt_d_id;
e315cd28 5293 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 5294 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 5295 unsigned long flags;
1da177e4
LT		 5296
5297 rval = QLA_SUCCESS;
5298
5299 /* Try GID_PT to get device list, else GAN. */
7a67735b 5300 if (!ha->swl)
642ef983 5301 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 5302 GFP_KERNEL);
5303 swl = ha->swl;
bbfbbbc1 5304 if (!swl) {
1da177e4 5305 /*EMPTY*/
83548fe2 5306 ql_dbg(ql_dbg_disc, vha, 0x209c,
7c3df132 5307 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 5308 } else {
642ef983 5309 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 5310 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 5311 swl = NULL;
b98ae0d7
QT		 5312 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5313 return rval;
e315cd28 5314 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5315 swl = NULL;
b98ae0d7
QT		 5316 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5317 return rval;
e315cd28 5318 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5319 swl = NULL;
b98ae0d7
QT		 5320 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5321 return rval;
726b8548
QT		 5322 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
5323 swl = NULL;
b98ae0d7
QT		 5324 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5325 return rval;
1da177e4 5326 }
e8c72ba5
CD		 5327
5328 /* If other queries succeeded probe for FC-4 type */
b98ae0d7 5329 if (swl) {
e8c72ba5 5330 qla2x00_gff_id(vha, swl);
b98ae0d7
QT		 5331 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5332 return rval;
5333 }
1da177e4
LT		 5334 }
5335 swl_idx = 0;
5336
5337 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 5338 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5339 if (new_fcport == NULL) {
83548fe2 5340 ql_log(ql_log_warn, vha, 0x209d,
7c3df132 5341 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5342 return (QLA_MEMORY_ALLOC_FAILED);
5343 }
5344 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 5345 /* Set start port ID scan at adapter ID. */
5346 first_dev = 1;
5347 last_dev = 0;
5348
5349 /* Starting free loop ID. */
e315cd28
AC		 5350 loop_id = ha->min_external_loopid;
5351 for (; loop_id <= ha->max_loop_id; loop_id++) {
5352 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 5353 continue;
5354
3a6478df
GM		 5355 if (ha->current_topology == ISP_CFG_FL &&
5356 (atomic_read(&vha->loop_down_timer) ||
5357 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 5358 atomic_set(&vha->loop_down_timer, 0);
5359 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5360 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 5361 break;
bb2d52b2 5362 }
1da177e4
LT		 5363
5364 if (swl != NULL) {
5365 if (last_dev) {
5366 wrap.b24 = new_fcport->d_id.b24;
5367 } else {
5368 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
5369 memcpy(new_fcport->node_name,
5370 swl[swl_idx].node_name, WWN_SIZE);
5371 memcpy(new_fcport->port_name,
5372 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 5373 memcpy(new_fcport->fabric_port_name,
5374 swl[swl_idx].fabric_port_name, WWN_SIZE);
5375 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 5376 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4 5377
a5d42f4c 5378 new_fcport->nvme_flag = 0;
1a28faa0 5379 new_fcport->fc4f_nvme = 0;
a5d42f4c
DG		 5380 if (vha->flags.nvme_enabled &&
5381 swl[swl_idx].fc4f_nvme) {
5382 new_fcport->fc4f_nvme =
5383 swl[swl_idx].fc4f_nvme;
5384 ql_log(ql_log_info, vha, 0x2131,
5385 "FOUND: NVME port %8phC as FC Type 28h\n",
5386 new_fcport->port_name);
5387 }
5388
1da177e4
LT		 5389 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
5390 last_dev = 1;
5391 }
5392 swl_idx++;
5393 }
5394 } else {
5395 /* Send GA_NXT to the switch */
e315cd28 5396 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 5397 if (rval != QLA_SUCCESS) {
83548fe2 5398 ql_log(ql_log_warn, vha, 0x209e,
7c3df132
SK		 5399 "SNS scan failed -- assuming "
5400 "zero-entry result.\n");
1da177e4
LT		 5401 rval = QLA_SUCCESS;
5402 break;
5403 }
5404 }
5405
5406 /* If wrap on switch device list, exit. */
5407 if (first_dev) {
5408 wrap.b24 = new_fcport->d_id.b24;
5409 first_dev = 0;
5410 } else if (new_fcport->d_id.b24 == wrap.b24) {
83548fe2 5411 ql_dbg(ql_dbg_disc, vha, 0x209f,
7c3df132
SK		 5412 "Device wrap (%02x%02x%02x).\n",
5413 new_fcport->d_id.b.domain,
5414 new_fcport->d_id.b.area,
5415 new_fcport->d_id.b.al_pa);
1da177e4
LT		 5416 break;
5417 }
5418
2c3dfe3f 5419 /* Bypass if same physical adapter. */
e315cd28 5420 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 5421 continue;
5422
2c3dfe3f 5423 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 5424 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
5425 continue;
2c3dfe3f 5426
f7d289f6
AV		 5427 /* Bypass if same domain and area of adapter. */
5428 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 5429 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 5430 ISP_CFG_FL)
5431 continue;
5432
1da177e4
LT		 5433 /* Bypass reserved domain fields. */
5434 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
5435 continue;
5436
e8c72ba5 5437 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 5438 if (ql2xgffidenable &&
5439 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
5440 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 5441 continue;
5442
726b8548
QT		 5443 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5444
1da177e4
LT		 5445 /* Locate matching device in database. */
5446 found = 0;
e315cd28 5447 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5448 if (memcmp(new_fcport->port_name, fcport->port_name,
5449 WWN_SIZE))
5450 continue;
5451
827210ba 5452 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 5453
1da177e4
LT		 5454 found++;
5455
d8b45213
AV		 5456 /* Update port state. */
5457 memcpy(fcport->fabric_port_name,
5458 new_fcport->fabric_port_name, WWN_SIZE);
5459 fcport->fp_speed = new_fcport->fp_speed;
5460
1da177e4 5461 /*
b2032fd5
RD		 5462 * If address the same and state FCS_ONLINE
5463 * (or in target mode), nothing changed.
1da177e4
LT		 5464 */
5465 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 5466 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 5467 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 5468 break;
5469 }
5470
5471 /*
5472 * If device was not a fabric device before.
5473 */
5474 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
5475 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 5476 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 5477 fcport->flags |= (FCF_FABRIC_DEVICE |
5478 FCF_LOGIN_NEEDED);
1da177e4
LT		 5479 break;
5480 }
5481
5482 /*
5483 * Port ID changed or device was marked to be updated;
5484 * Log it out if still logged in and mark it for
5485 * relogin later.
5486 */
726b8548 5487 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 5488 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
5489 "port changed FC ID, %8phC"
5490 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
5491 fcport->port_name,
5492 fcport->d_id.b.domain,
5493 fcport->d_id.b.area,
5494 fcport->d_id.b.al_pa,
5495 fcport->loop_id,
5496 new_fcport->d_id.b.domain,
5497 new_fcport->d_id.b.area,
5498 new_fcport->d_id.b.al_pa);
5499 fcport->d_id.b24 = new_fcport->d_id.b24;
5500 break;
5501 }
5502
1da177e4
LT		 5503 fcport->d_id.b24 = new_fcport->d_id.b24;
5504 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 5505 break;
5506 }
5507
726b8548
QT		 5508 if (found) {
5509 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 5510 continue;
726b8548 5511 }
1da177e4 5512 /* If device was not in our fcports list, then add it. */
b2032fd5 5513 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 5514 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5515
5516 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5517
1da177e4
LT		 5518
5519 /* Allocate a new replacement fcport. */
5520 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 5521 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5522 if (new_fcport == NULL) {
83548fe2 5523 ql_log(ql_log_warn, vha, 0xd032,
7c3df132 5524 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5525 return (QLA_MEMORY_ALLOC_FAILED);
5526 }
5527 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5528 new_fcport->d_id.b24 = nxt_d_id.b24;
5529 }
5530
726b8548
QT		 5531 qla2x00_free_fcport(new_fcport);
5532
5533 /*
5534 * Logout all previous fabric dev marked lost, except FCP2 devices.
5535 */
5536 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5537 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5538 break;
5539
5540 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
5541 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
5542 continue;
5543
5544 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5545 if ((qla_dual_mode_enabled(vha) ||
5546 qla_ini_mode_enabled(vha)) &&
5547 atomic_read(&fcport->state) == FCS_ONLINE) {
5548 qla2x00_mark_device_lost(vha, fcport,
5549 ql2xplogiabsentdevice, 0);
5550 if (fcport->loop_id != FC_NO_LOOP_ID &&
5551 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5552 fcport->port_type != FCT_INITIATOR &&
5553 fcport->port_type != FCT_BROADCAST) {
83548fe2 5554 ql_dbg(ql_dbg_disc, vha, 0x20f0,
726b8548
QT		 5555 "%s %d %8phC post del sess\n",
5556 __func__, __LINE__,
5557 fcport->port_name);
d8630bb9 5558 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 5559 continue;
5560 }
5561 }
5562 }
1da177e4 5563
726b8548
QT		 5564 if (fcport->scan_state == QLA_FCPORT_FOUND)
5565 qla24xx_fcport_handle_login(vha, fcport);
5566 }
1da177e4
LT		 5567 return (rval);
5568}
5569
5570/*
5571 * qla2x00_find_new_loop_id
5572 * Scan through our port list and find a new usable loop ID.
5573 *
5574 * Input:
5575 * ha: adapter state pointer.
5576 * dev: port structure pointer.
5577 *
5578 * Returns:
5579 * qla2x00 local function return status code.
5580 *
5581 * Context:
5582 * Kernel context.
5583 */
03bcfb57 5584int
e315cd28 5585qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 5586{
5587 int rval;
e315cd28 5588 struct qla_hw_data *ha = vha->hw;
feafb7b1 5589 unsigned long flags = 0;
1da177e4
LT		 5590
5591 rval = QLA_SUCCESS;
5592
5f16b331 5593 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 5594
5f16b331
CD		 5595 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
5596 LOOPID_MAP_SIZE);
5597 if (dev->loop_id >= LOOPID_MAP_SIZE ||
5598 qla2x00_is_reserved_id(vha, dev->loop_id)) {
5599 dev->loop_id = FC_NO_LOOP_ID;
5600 rval = QLA_FUNCTION_FAILED;
5601 } else
5602 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 5603
5f16b331 5604 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 5605
5f16b331
CD		 5606 if (rval == QLA_SUCCESS)
5607 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
5608 "Assigning new loopid=%x, portid=%x.\n",
5609 dev->loop_id, dev->d_id.b24);
5610 else
5611 ql_log(ql_log_warn, dev->vha, 0x2087,
5612 "No loop_id's available, portid=%x.\n",
5613 dev->d_id.b24);
1da177e4
LT		 5614
5615 return (rval);
5616}
5617
1da177e4
LT		 5618
5619/*
5620 * qla2x00_fabric_login
5621 * Issue fabric login command.
5622 *
5623 * Input:
5624 * ha = adapter block pointer.
5625 * device = pointer to FC device type structure.
5626 *
5627 * Returns:
5628 * 0 - Login successfully
5629 * 1 - Login failed
5630 * 2 - Initiator device
5631 * 3 - Fatal error
5632 */
5633int
e315cd28 5634qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 5635 uint16_t *next_loopid)
5636{
5637 int rval;
5638 int retry;
5639 uint16_t tmp_loopid;
5640 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5641 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 5642
5643 retry = 0;
5644 tmp_loopid = 0;
5645
5646 for (;;) {
7c3df132
SK		 5647 ql_dbg(ql_dbg_disc, vha, 0x2000,
5648 "Trying Fabric Login w/loop id 0x%04x for port "
5649 "%02x%02x%02x.\n",
5650 fcport->loop_id, fcport->d_id.b.domain,
5651 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5652
5653 /* Login fcport on switch. */
0b91d116 5654 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 5655 fcport->d_id.b.domain, fcport->d_id.b.area,
5656 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 5657 if (rval != QLA_SUCCESS) {
5658 return rval;
5659 }
1da177e4
LT		 5660 if (mb[0] == MBS_PORT_ID_USED) {
5661 /*
5662 * Device has another loop ID. The firmware team
0107109e
AV		 5663 * recommends the driver perform an implicit login with
5664 * the specified ID again. The ID we just used is save
5665 * here so we return with an ID that can be tried by
5666 * the next login.
1da177e4
LT		 5667 */
5668 retry++;
5669 tmp_loopid = fcport->loop_id;
5670 fcport->loop_id = mb[1];
5671
7c3df132
SK		 5672 ql_dbg(ql_dbg_disc, vha, 0x2001,
5673 "Fabric Login: port in use - next loop "
5674 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 5675 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 5676 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5677
5678 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
5679 /*
5680 * Login succeeded.
5681 */
5682 if (retry) {
5683 /* A retry occurred before. */
5684 *next_loopid = tmp_loopid;
5685 } else {
5686 /*
5687 * No retry occurred before. Just increment the
5688 * ID value for next login.
5689 */
5690 *next_loopid = (fcport->loop_id + 1);
5691 }
5692
5693 if (mb[1] & BIT_0) {
5694 fcport->port_type = FCT_INITIATOR;
5695 } else {
5696 fcport->port_type = FCT_TARGET;
5697 if (mb[1] & BIT_1) {
8474f3a0 5698 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 5699 }
5700 }
5701
ad3e0eda
AV		 5702 if (mb[10] & BIT_0)
5703 fcport->supported_classes |= FC_COS_CLASS2;
5704 if (mb[10] & BIT_1)
5705 fcport->supported_classes |= FC_COS_CLASS3;
5706
2d70c103
NB		 5707 if (IS_FWI2_CAPABLE(ha)) {
5708 if (mb[10] & BIT_7)
5709 fcport->flags |=
5710 FCF_CONF_COMP_SUPPORTED;
5711 }
5712
1da177e4
LT		 5713 rval = QLA_SUCCESS;
5714 break;
5715 } else if (mb[0] == MBS_LOOP_ID_USED) {
5716 /*
5717 * Loop ID already used, try next loop ID.
5718 */
5719 fcport->loop_id++;
e315cd28 5720 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 5721 if (rval != QLA_SUCCESS) {
5722 /* Ran out of loop IDs to use */
5723 break;
5724 }
5725 } else if (mb[0] == MBS_COMMAND_ERROR) {
5726 /*
5727 * Firmware possibly timed out during login. If NO
5728 * retries are left to do then the device is declared
5729 * dead.
5730 */
5731 *next_loopid = fcport->loop_id;
e315cd28 5732 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5733 fcport->d_id.b.domain, fcport->d_id.b.area,
5734 fcport->d_id.b.al_pa);
e315cd28 5735 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 5736
5737 rval = 1;
5738 break;
5739 } else {
5740 /*
5741 * unrecoverable / not handled error
5742 */
7c3df132
SK		 5743 ql_dbg(ql_dbg_disc, vha, 0x2002,
5744 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
5745 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
5746 fcport->d_id.b.area, fcport->d_id.b.al_pa,
5747 fcport->loop_id, jiffies);
1da177e4
LT		 5748
5749 *next_loopid = fcport->loop_id;
e315cd28 5750 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5751 fcport->d_id.b.domain, fcport->d_id.b.area,
5752 fcport->d_id.b.al_pa);
5f16b331 5753 qla2x00_clear_loop_id(fcport);
0eedfcf0 5754 fcport->login_retry = 0;
1da177e4
LT		 5755
5756 rval = 3;
5757 break;
5758 }
5759 }
5760
5761 return (rval);
5762}
5763
5764/*
5765 * qla2x00_local_device_login
5766 * Issue local device login command.
5767 *
5768 * Input:
5769 * ha = adapter block pointer.
5770 * loop_id = loop id of device to login to.
5771 *
5772 * Returns (Where's the #define!!!!):
5773 * 0 - Login successfully
5774 * 1 - Login failed
5775 * 3 - Fatal error
5776 */
5777int
e315cd28 5778qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 5779{
5780 int rval;
5781 uint16_t mb[MAILBOX_REGISTER_COUNT];
5782
5783 memset(mb, 0, sizeof(mb));
e315cd28 5784 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 5785 if (rval == QLA_SUCCESS) {
5786 /* Interrogate mailbox registers for any errors */
5787 if (mb[0] == MBS_COMMAND_ERROR)
5788 rval = 1;
5789 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
5790 /* device not in PCB table */
5791 rval = 3;
5792 }
5793
5794 return (rval);
5795}
5796
5797/*
5798 * qla2x00_loop_resync
5799 * Resync with fibre channel devices.
5800 *
5801 * Input:
5802 * ha = adapter block pointer.
5803 *
5804 * Returns:
5805 * 0 = success
5806 */
5807int
e315cd28 5808qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 5809{
73208dfd 5810 int rval = QLA_SUCCESS;
1da177e4 5811 uint32_t wait_time;
67c2e93a
AC		 5812 struct req_que *req;
5813 struct rsp_que *rsp;
5814
d7459527 5815 req = vha->req;
67c2e93a 5816 rsp = req->rsp;
1da177e4 5817
e315cd28
AC		 5818 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5819 if (vha->flags.online) {
5820 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 5821 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5822 wait_time = 256;
5823 do {
8ae6d9c7
GM		 5824 if (!IS_QLAFX00(vha->hw)) {
5825 /*
5826 * Issue a marker after FW becomes
5827 * ready.
5828 */
5829 qla2x00_marker(vha, req, rsp, 0, 0,
5830 MK_SYNC_ALL);
5831 vha->marker_needed = 0;
5832 }
1da177e4
LT		 5833
5834 /* Remap devices on Loop. */
e315cd28 5835 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 5836
8ae6d9c7
GM		 5837 if (IS_QLAFX00(vha->hw))
5838 qlafx00_configure_devices(vha);
5839 else
5840 qla2x00_configure_loop(vha);
5841
1da177e4 5842 wait_time--;
e315cd28
AC		 5843 } while (!atomic_read(&vha->loop_down_timer) &&
5844 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
5845 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
5846 &vha->dpc_flags)));
1da177e4 5847 }
1da177e4
LT		 5848 }
5849
e315cd28 5850 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 5851 return (QLA_FUNCTION_FAILED);
1da177e4 5852
e315cd28 5853 if (rval)
7c3df132
SK		 5854 ql_dbg(ql_dbg_disc, vha, 0x206c,
5855 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 5856
5857 return (rval);
5858}
5859
579d12b5
SK		 5860/*
5861* qla2x00_perform_loop_resync
5862* Description: This function will set the appropriate flags and call
5863* qla2x00_loop_resync. If successful loop will be resynced
5864* Arguments : scsi_qla_host_t pointer
5865* returm : Success or Failure
5866*/
5867
5868int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
5869{
5870 int32_t rval = 0;
5871
5872 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
5873 /*Configure the flags so that resync happens properly*/
5874 atomic_set(&ha->loop_down_timer, 0);
5875 if (!(ha->device_flags & DFLG_NO_CABLE)) {
5876 atomic_set(&ha->loop_state, LOOP_UP);
5877 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
5878 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
5879 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
5880
5881 rval = qla2x00_loop_resync(ha);
5882 } else
5883 atomic_set(&ha->loop_state, LOOP_DEAD);
5884
5885 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
5886 }
5887
5888 return rval;
5889}
5890
d97994dc 5891void
67becc00 5892qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 5893{
5894 fc_port_t *fcport;
feafb7b1
AE		 5895 struct scsi_qla_host *vha;
5896 struct qla_hw_data *ha = base_vha->hw;
5897 unsigned long flags;
d97994dc 5898
feafb7b1 5899 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 5900 /* Go with deferred removal of rport references. */
feafb7b1
AE		 5901 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
5902 atomic_inc(&vha->vref_count);
5903 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 5904 if (fcport->drport &&
feafb7b1
AE		 5905 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
5906 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 5907 qla2x00_rport_del(fcport);
df673274 5908
feafb7b1
AE		 5909 spin_lock_irqsave(&ha->vport_slock, flags);
5910 }
5911 }
5912 atomic_dec(&vha->vref_count);
c4a9b538 5913 wake_up(&vha->vref_waitq);
feafb7b1
AE		 5914 }
5915 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 5916}
5917
7d613ac6
SV		 5918/* Assumes idc_lock always held on entry */
5919void
5920qla83xx_reset_ownership(scsi_qla_host_t *vha)
5921{
5922 struct qla_hw_data *ha = vha->hw;
5923 uint32_t drv_presence, drv_presence_mask;
5924 uint32_t dev_part_info1, dev_part_info2, class_type;
5925 uint32_t class_type_mask = 0x3;
5926 uint16_t fcoe_other_function = 0xffff, i;
5927
7ec0effd
AD		 5928 if (IS_QLA8044(ha)) {
5929 drv_presence = qla8044_rd_direct(vha,
5930 QLA8044_CRB_DRV_ACTIVE_INDEX);
5931 dev_part_info1 = qla8044_rd_direct(vha,
5932 QLA8044_CRB_DEV_PART_INFO_INDEX);
5933 dev_part_info2 = qla8044_rd_direct(vha,
5934 QLA8044_CRB_DEV_PART_INFO2);
5935 } else {
5936 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5937 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
5938 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
5939 }
7d613ac6
SV		 5940 for (i = 0; i < 8; i++) {
5941 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
5942 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5943 (i != ha->portnum)) {
5944 fcoe_other_function = i;
5945 break;
5946 }
5947 }
5948 if (fcoe_other_function == 0xffff) {
5949 for (i = 0; i < 8; i++) {
5950 class_type = ((dev_part_info2 >> (i * 4)) &
5951 class_type_mask);
5952 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5953 ((i + 8) != ha->portnum)) {
5954 fcoe_other_function = i + 8;
5955 break;
5956 }
5957 }
5958 }
5959 /*
5960 * Prepare drv-presence mask based on fcoe functions present.
5961 * However consider only valid physical fcoe function numbers (0-15).
5962 */
5963 drv_presence_mask = ~((1 << (ha->portnum)) |
5964 ((fcoe_other_function == 0xffff) ?
5965 0 : (1 << (fcoe_other_function))));
5966
5967 /* We are the reset owner iff:
5968 * - No other protocol drivers present.
5969 * - This is the lowest among fcoe functions. */
5970 if (!(drv_presence & drv_presence_mask) &&
5971 (ha->portnum < fcoe_other_function)) {
5972 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
5973 "This host is Reset owner.\n");
5974 ha->flags.nic_core_reset_owner = 1;
5975 }
5976}
5977
fa492630 5978static int
7d613ac6
SV		 5979__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
5980{
5981 int rval = QLA_SUCCESS;
5982 struct qla_hw_data *ha = vha->hw;
5983 uint32_t drv_ack;
5984
5985 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5986 if (rval == QLA_SUCCESS) {
5987 drv_ack |= (1 << ha->portnum);
5988 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5989 }
5990
5991 return rval;
5992}
5993
fa492630 5994static int
7d613ac6
SV		 5995__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
5996{
5997 int rval = QLA_SUCCESS;
5998 struct qla_hw_data *ha = vha->hw;
5999 uint32_t drv_ack;
6000
6001 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6002 if (rval == QLA_SUCCESS) {
6003 drv_ack &= ~(1 << ha->portnum);
6004 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6005 }
6006
6007 return rval;
6008}
6009
fa492630 6010static const char *
7d613ac6
SV		 6011qla83xx_dev_state_to_string(uint32_t dev_state)
6012{
6013 switch (dev_state) {
6014 case QLA8XXX_DEV_COLD:
6015 return "COLD/RE-INIT";
6016 case QLA8XXX_DEV_INITIALIZING:
6017 return "INITIALIZING";
6018 case QLA8XXX_DEV_READY:
6019 return "READY";
6020 case QLA8XXX_DEV_NEED_RESET:
6021 return "NEED RESET";
6022 case QLA8XXX_DEV_NEED_QUIESCENT:
6023 return "NEED QUIESCENT";
6024 case QLA8XXX_DEV_FAILED:
6025 return "FAILED";
6026 case QLA8XXX_DEV_QUIESCENT:
6027 return "QUIESCENT";
6028 default:
6029 return "Unknown";
6030 }
6031}
6032
6033/* Assumes idc-lock always held on entry */
6034void
6035qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
6036{
6037 struct qla_hw_data *ha = vha->hw;
6038 uint32_t idc_audit_reg = 0, duration_secs = 0;
6039
6040 switch (audit_type) {
6041 case IDC_AUDIT_TIMESTAMP:
6042 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
6043 idc_audit_reg = (ha->portnum) |
6044 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
6045 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6046 break;
6047
6048 case IDC_AUDIT_COMPLETION:
6049 duration_secs = ((jiffies_to_msecs(jiffies) -
6050 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
6051 idc_audit_reg = (ha->portnum) |
6052 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
6053 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6054 break;
6055
6056 default:
6057 ql_log(ql_log_warn, vha, 0xb078,
6058 "Invalid audit type specified.\n");
6059 break;
6060 }
6061}
6062
6063/* Assumes idc_lock always held on entry */
fa492630 6064static int
7d613ac6
SV		 6065qla83xx_initiating_reset(scsi_qla_host_t *vha)
6066{
6067 struct qla_hw_data *ha = vha->hw;
6068 uint32_t idc_control, dev_state;
6069
6070 __qla83xx_get_idc_control(vha, &idc_control);
6071 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
6072 ql_log(ql_log_info, vha, 0xb080,
6073 "NIC Core reset has been disabled. idc-control=0x%x\n",
6074 idc_control);
6075 return QLA_FUNCTION_FAILED;
6076 }
6077
6078 /* Set NEED-RESET iff in READY state and we are the reset-owner */
6079 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6080 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
6081 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
6082 QLA8XXX_DEV_NEED_RESET);
6083 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
6084 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
6085 } else {
6086 const char *state = qla83xx_dev_state_to_string(dev_state);
6087 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
6088
6089 /* SV: XXX: Is timeout required here? */
6090 /* Wait for IDC state change READY -> NEED_RESET */
6091 while (dev_state == QLA8XXX_DEV_READY) {
6092 qla83xx_idc_unlock(vha, 0);
6093 msleep(200);
6094 qla83xx_idc_lock(vha, 0);
6095 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6096 }
6097 }
6098
6099 /* Send IDC ack by writing to drv-ack register */
6100 __qla83xx_set_drv_ack(vha);
6101
6102 return QLA_SUCCESS;
6103}
6104
6105int
6106__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
6107{
6108 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6109}
6110
7d613ac6
SV		 6111int
6112__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
6113{
6114 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6115}
6116
fa492630 6117static int
7d613ac6
SV		 6118qla83xx_check_driver_presence(scsi_qla_host_t *vha)
6119{
6120 uint32_t drv_presence = 0;
6121 struct qla_hw_data *ha = vha->hw;
6122
6123 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6124 if (drv_presence & (1 << ha->portnum))
6125 return QLA_SUCCESS;
6126 else
6127 return QLA_TEST_FAILED;
6128}
6129
6130int
6131qla83xx_nic_core_reset(scsi_qla_host_t *vha)
6132{
6133 int rval = QLA_SUCCESS;
6134 struct qla_hw_data *ha = vha->hw;
6135
6136 ql_dbg(ql_dbg_p3p, vha, 0xb058,
6137 "Entered %s().\n", __func__);
6138
6139 if (vha->device_flags & DFLG_DEV_FAILED) {
6140 ql_log(ql_log_warn, vha, 0xb059,
6141 "Device in unrecoverable FAILED state.\n");
6142 return QLA_FUNCTION_FAILED;
6143 }
6144
6145 qla83xx_idc_lock(vha, 0);
6146
6147 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
6148 ql_log(ql_log_warn, vha, 0xb05a,
6149 "Function=0x%x has been removed from IDC participation.\n",
6150 ha->portnum);
6151 rval = QLA_FUNCTION_FAILED;
6152 goto exit;
6153 }
6154
6155 qla83xx_reset_ownership(vha);
6156
6157 rval = qla83xx_initiating_reset(vha);
6158
6159 /*
6160 * Perform reset if we are the reset-owner,
6161 * else wait till IDC state changes to READY/FAILED.
6162 */
6163 if (rval == QLA_SUCCESS) {
6164 rval = qla83xx_idc_state_handler(vha);
6165
6166 if (rval == QLA_SUCCESS)
6167 ha->flags.nic_core_hung = 0;
6168 __qla83xx_clear_drv_ack(vha);
6169 }
6170
6171exit:
6172 qla83xx_idc_unlock(vha, 0);
6173
6174 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
6175
6176 return rval;
6177}
6178
81178772
SK		 6179int
6180qla2xxx_mctp_dump(scsi_qla_host_t *vha)
6181{
6182 struct qla_hw_data *ha = vha->hw;
6183 int rval = QLA_FUNCTION_FAILED;
6184
6185 if (!IS_MCTP_CAPABLE(ha)) {
6186 /* This message can be removed from the final version */
6187 ql_log(ql_log_info, vha, 0x506d,
6188 "This board is not MCTP capable\n");
6189 return rval;
6190 }
6191
6192 if (!ha->mctp_dump) {
6193 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
6194 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
6195
6196 if (!ha->mctp_dump) {
6197 ql_log(ql_log_warn, vha, 0x506e,
6198 "Failed to allocate memory for mctp dump\n");
6199 return rval;
6200 }
6201 }
6202
6203#define MCTP_DUMP_STR_ADDR 0x00000000
6204 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
6205 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
6206 if (rval != QLA_SUCCESS) {
6207 ql_log(ql_log_warn, vha, 0x506f,
6208 "Failed to capture mctp dump\n");
6209 } else {
6210 ql_log(ql_log_info, vha, 0x5070,
6211 "Mctp dump capture for host (%ld/%p).\n",
6212 vha->host_no, ha->mctp_dump);
6213 ha->mctp_dumped = 1;
6214 }
6215
409ee0fe 6216 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 6217 ha->flags.nic_core_reset_hdlr_active = 1;
6218 rval = qla83xx_restart_nic_firmware(vha);
6219 if (rval)
6220 /* NIC Core reset failed. */
6221 ql_log(ql_log_warn, vha, 0x5071,
6222 "Failed to restart nic firmware\n");
6223 else
6224 ql_dbg(ql_dbg_p3p, vha, 0xb084,
6225 "Restarted NIC firmware successfully.\n");
6226 ha->flags.nic_core_reset_hdlr_active = 0;
6227 }
6228
6229 return rval;
6230
6231}
6232
579d12b5 6233/*
8fcd6b8b 6234* qla2x00_quiesce_io
579d12b5
SK		 6235* Description: This function will block the new I/Os
6236* Its not aborting any I/Os as context
6237* is not destroyed during quiescence
6238* Arguments: scsi_qla_host_t
6239* return : void
6240*/
6241void
8fcd6b8b 6242qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 6243{
6244 struct qla_hw_data *ha = vha->hw;
6245 struct scsi_qla_host *vp;
6246
8fcd6b8b
CD		 6247 ql_dbg(ql_dbg_dpc, vha, 0x401d,
6248 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 6249
6250 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
6251 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6252 atomic_set(&vha->loop_state, LOOP_DOWN);
6253 qla2x00_mark_all_devices_lost(vha, 0);
6254 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 6255 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 6256 } else {
6257 if (!atomic_read(&vha->loop_down_timer))
6258 atomic_set(&vha->loop_down_timer,
6259 LOOP_DOWN_TIME);
6260 }
6261 /* Wait for pending cmds to complete */
6262 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
6263}
6264
a9083016
GM		 6265void
6266qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
6267{
6268 struct qla_hw_data *ha = vha->hw;
579d12b5 6269 struct scsi_qla_host *vp;
feafb7b1 6270 unsigned long flags;
6aef87be 6271 fc_port_t *fcport;
7c3f8fd1 6272 u16 i;
a9083016 6273
e46ef004
SK		 6274 /* For ISP82XX, driver waits for completion of the commands.
6275 * online flag should be set.
6276 */
7ec0effd 6277 if (!(IS_P3P_TYPE(ha)))
e46ef004 6278 vha->flags.online = 0;
a9083016
GM		 6279 ha->flags.chip_reset_done = 0;
6280 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 6281 vha->qla_stats.total_isp_aborts++;
a9083016 6282
7c3df132
SK		 6283 ql_log(ql_log_info, vha, 0x00af,
6284 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 6285
e46ef004
SK		 6286 /* For ISP82XX, reset_chip is just disabling interrupts.
6287 * Driver waits for the completion of the commands.
6288 * the interrupts need to be enabled.
6289 */
7ec0effd 6290 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 6291 ha->isp_ops->reset_chip(vha);
6292
9cd883f0
QT		 6293 SAVE_TOPO(ha);
6294 ha->flags.rida_fmt2 = 0;
ec7193e2
QT		 6295 ha->flags.n2n_ae = 0;
6296 ha->flags.lip_ae = 0;
6297 ha->current_topology = 0;
6298 ha->flags.fw_started = 0;
6299 ha->flags.fw_init_done = 0;
7c3f8fd1
QT		 6300 ha->base_qpair->chip_reset++;
6301 for (i = 0; i < ha->max_qpairs; i++) {
6302 if (ha->queue_pair_map[i])
6303 ha->queue_pair_map[i]->chip_reset =
6304 ha->base_qpair->chip_reset;
6305 }
726b8548 6306
a9083016
GM		 6307 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
6308 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6309 atomic_set(&vha->loop_state, LOOP_DOWN);
6310 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 6311
6312 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 6313 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 6314 atomic_inc(&vp->vref_count);
6315 spin_unlock_irqrestore(&ha->vport_slock, flags);
6316
a9083016 6317 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 6318
6319 spin_lock_irqsave(&ha->vport_slock, flags);
6320 atomic_dec(&vp->vref_count);
6321 }
6322 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 6323 } else {
6324 if (!atomic_read(&vha->loop_down_timer))
6325 atomic_set(&vha->loop_down_timer,
6326 LOOP_DOWN_TIME);
6327 }
6328
6aef87be
AV		 6329 /* Clear all async request states across all VPs. */
6330 list_for_each_entry(fcport, &vha->vp_fcports, list)
6331 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6332 spin_lock_irqsave(&ha->vport_slock, flags);
6333 list_for_each_entry(vp, &ha->vp_list, list) {
6334 atomic_inc(&vp->vref_count);
6335 spin_unlock_irqrestore(&ha->vport_slock, flags);
6336
6337 list_for_each_entry(fcport, &vp->vp_fcports, list)
6338 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6339
6340 spin_lock_irqsave(&ha->vport_slock, flags);
6341 atomic_dec(&vp->vref_count);
6342 }
6343 spin_unlock_irqrestore(&ha->vport_slock, flags);
6344
bddd2d65
LC		 6345 if (!ha->flags.eeh_busy) {
6346 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 6347 if (IS_P3P_TYPE(ha)) {
7190575f 6348 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 6349 ql_log(ql_log_info, vha, 0x00b4,
6350 "Done chip reset cleanup.\n");
a9083016 6351
e46ef004
SK		 6352 /* Done waiting for pending commands.
6353 * Reset the online flag.
6354 */
6355 vha->flags.online = 0;
4d78c973 6356 }
a9083016 6357
bddd2d65
LC		 6358 /* Requeue all commands in outstanding command list. */
6359 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6360 }
b6a029e1
AE		 6361 /* memory barrier */
6362 wmb();
a9083016
GM		 6363}
6364
1da177e4
LT		 6365/*
6366* qla2x00_abort_isp
6367* Resets ISP and aborts all outstanding commands.
6368*
6369* Input:
6370* ha = adapter block pointer.
6371*
6372* Returns:
6373* 0 = success
6374*/
6375int
e315cd28 6376qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 6377{
476e8978 6378 int rval;
1da177e4 6379 uint8_t status = 0;
e315cd28
AC		 6380 struct qla_hw_data *ha = vha->hw;
6381 struct scsi_qla_host *vp;
73208dfd 6382 struct req_que *req = ha->req_q_map[0];
feafb7b1 6383 unsigned long flags;
1da177e4 6384
e315cd28 6385 if (vha->flags.online) {
a9083016 6386 qla2x00_abort_isp_cleanup(vha);
1da177e4 6387
a6171297
SV		 6388 if (IS_QLA8031(ha)) {
6389 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
6390 "Clearing fcoe driver presence.\n");
6391 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
6392 ql_dbg(ql_dbg_p3p, vha, 0xb073,
6393 "Error while clearing DRV-Presence.\n");
6394 }
6395
85880801
AV		 6396 if (unlikely(pci_channel_offline(ha->pdev) &&
6397 ha->flags.pci_channel_io_perm_failure)) {
6398 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6399 status = 0;
6400 return status;
6401 }
6402
73208dfd 6403 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 6404
e315cd28 6405 ha->isp_ops->nvram_config(vha);
1da177e4 6406
e315cd28
AC		 6407 if (!qla2x00_restart_isp(vha)) {
6408 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 6409
e315cd28 6410 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 6411 /*
6412 * Issue marker command only when we are going
6413 * to start the I/O .
6414 */
e315cd28 6415 vha->marker_needed = 1;
1da177e4
LT		 6416 }
6417
e315cd28 6418 vha->flags.online = 1;
1da177e4 6419
fd34f556 6420 ha->isp_ops->enable_intrs(ha);
1da177e4 6421
fa2a1ce5 6422 ha->isp_abort_cnt = 0;
e315cd28 6423 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 6424
6246b8a1
GM		 6425 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
6426 qla2x00_get_fw_version(vha);
df613b96
AV		 6427 if (ha->fce) {
6428 ha->flags.fce_enabled = 1;
6429 memset(ha->fce, 0,
6430 fce_calc_size(ha->fce_bufs));
e315cd28 6431 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 6432 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6433 &ha->fce_bufs);
6434 if (rval) {
7c3df132 6435 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 6436 "Unable to reinitialize FCE "
6437 "(%d).\n", rval);
6438 ha->flags.fce_enabled = 0;
6439 }
6440 }
436a7b11
AV		 6441
6442 if (ha->eft) {
6443 memset(ha->eft, 0, EFT_SIZE);
e315cd28 6444 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 6445 ha->eft_dma, EFT_NUM_BUFFERS);
6446 if (rval) {
7c3df132 6447 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 6448 "Unable to reinitialize EFT "
6449 "(%d).\n", rval);
6450 }
6451 }
1da177e4 6452 } else { /* failed the ISP abort */
e315cd28
AC		 6453 vha->flags.online = 1;
6454 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 6455 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 6456 ql_log(ql_log_fatal, vha, 0x8035,
6457 "ISP error recover failed - "
6458 "board disabled.\n");
fa2a1ce5 6459 /*
1da177e4
LT		 6460 * The next call disables the board
6461 * completely.
6462 */
e315cd28
AC		 6463 ha->isp_ops->reset_adapter(vha);
6464 vha->flags.online = 0;
1da177e4 6465 clear_bit(ISP_ABORT_RETRY,
e315cd28 6466 &vha->dpc_flags);
1da177e4
LT		 6467 status = 0;
6468 } else { /* schedule another ISP abort */
6469 ha->isp_abort_cnt--;
7c3df132
SK		 6470 ql_dbg(ql_dbg_taskm, vha, 0x8020,
6471 "ISP abort - retry remaining %d.\n",
6472 ha->isp_abort_cnt);
1da177e4
LT		 6473 status = 1;
6474 }
6475 } else {
6476 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 6477 ql_dbg(ql_dbg_taskm, vha, 0x8021,
6478 "ISP error recovery - retrying (%d) "
6479 "more times.\n", ha->isp_abort_cnt);
e315cd28 6480 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 6481 status = 1;
6482 }
6483 }
fa2a1ce5 6484
1da177e4
LT		 6485 }
6486
e315cd28 6487 if (!status) {
7c3df132 6488 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
1608cc4a 6489 qla2x00_configure_hba(vha);
feafb7b1
AE		 6490 spin_lock_irqsave(&ha->vport_slock, flags);
6491 list_for_each_entry(vp, &ha->vp_list, list) {
6492 if (vp->vp_idx) {
6493 atomic_inc(&vp->vref_count);
6494 spin_unlock_irqrestore(&ha->vport_slock, flags);
6495
e315cd28 6496 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6497
6498 spin_lock_irqsave(&ha->vport_slock, flags);
6499 atomic_dec(&vp->vref_count);
6500 }
e315cd28 6501 }
feafb7b1
AE		 6502 spin_unlock_irqrestore(&ha->vport_slock, flags);
6503
7d613ac6
SV		 6504 if (IS_QLA8031(ha)) {
6505 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
6506 "Setting back fcoe driver presence.\n");
6507 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
6508 ql_dbg(ql_dbg_p3p, vha, 0xb074,
6509 "Error while setting DRV-Presence.\n");
6510 }
e315cd28 6511 } else {
d8424f68
JP		 6512 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
6513 __func__);
1da177e4
LT		 6514 }
6515
6516 return(status);
6517}
6518
6519/*
6520* qla2x00_restart_isp
6521* restarts the ISP after a reset
6522*
6523* Input:
6524* ha = adapter block pointer.
6525*
6526* Returns:
6527* 0 = success
6528*/
6529static int
e315cd28 6530qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 6531{
c6b2fca8 6532 int status = 0;
e315cd28 6533 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 6534 struct req_que *req = ha->req_q_map[0];
6535 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 6536
6537 /* If firmware needs to be loaded */
e315cd28
AC		 6538 if (qla2x00_isp_firmware(vha)) {
6539 vha->flags.online = 0;
6540 status = ha->isp_ops->chip_diag(vha);
6541 if (!status)
6542 status = qla2x00_setup_chip(vha);
1da177e4
LT		 6543 }
6544
e315cd28
AC		 6545 if (!status && !(status = qla2x00_init_rings(vha))) {
6546 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 6547 ha->flags.chip_reset_done = 1;
7108b76e 6548
73208dfd
AC		 6549 /* Initialize the queues in use */
6550 qla25xx_init_queues(ha);
6551
e315cd28
AC		 6552 status = qla2x00_fw_ready(vha);
6553 if (!status) {
0107109e 6554 /* Issue a marker after FW becomes ready. */
73208dfd 6555 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 6556 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6557 }
6558
6559 /* if no cable then assume it's good */
e315cd28 6560 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 6561 status = 0;
1da177e4
LT		 6562 }
6563 return (status);
6564}
6565
73208dfd
AC		 6566static int
6567qla25xx_init_queues(struct qla_hw_data *ha)
6568{
6569 struct rsp_que *rsp = NULL;
6570 struct req_que *req = NULL;
6571 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6572 int ret = -1;
6573 int i;
6574
2afa19a9 6575 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 6576 rsp = ha->rsp_q_map[i];
cb43285f 6577 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 6578 rsp->options &= ~BIT_0;
618a7523 6579 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 6580 if (ret != QLA_SUCCESS)
7c3df132
SK		 6581 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
6582 "%s Rsp que: %d init failed.\n",
6583 __func__, rsp->id);
73208dfd 6584 else
7c3df132
SK		 6585 ql_dbg(ql_dbg_init, base_vha, 0x0100,
6586 "%s Rsp que: %d inited.\n",
6587 __func__, rsp->id);
73208dfd 6588 }
2afa19a9
AC		 6589 }
6590 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 6591 req = ha->req_q_map[i];
cb43285f
QT		 6592 if (req && test_bit(i, ha->req_qid_map)) {
6593 /* Clear outstanding commands array. */
73208dfd 6594 req->options &= ~BIT_0;
618a7523 6595 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 6596 if (ret != QLA_SUCCESS)
7c3df132
SK		 6597 ql_dbg(ql_dbg_init, base_vha, 0x0101,
6598 "%s Req que: %d init failed.\n",
6599 __func__, req->id);
73208dfd 6600 else
7c3df132
SK		 6601 ql_dbg(ql_dbg_init, base_vha, 0x0102,
6602 "%s Req que: %d inited.\n",
6603 __func__, req->id);
73208dfd
AC		 6604 }
6605 }
6606 return ret;
6607}
6608
1da177e4
LT		 6609/*
6610* qla2x00_reset_adapter
6611* Reset adapter.
6612*
6613* Input:
6614* ha = adapter block pointer.
6615*/
abbd8870 6616void
e315cd28 6617qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 6618{
6619 unsigned long flags = 0;
e315cd28 6620 struct qla_hw_data *ha = vha->hw;
3d71644c 6621 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 6622
e315cd28 6623 vha->flags.online = 0;
fd34f556 6624 ha->isp_ops->disable_intrs(ha);
1da177e4 6625
1da177e4
LT		 6626 spin_lock_irqsave(&ha->hardware_lock, flags);
6627 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
6628 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6629 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
6630 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6631 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6632}
0107109e
AV		 6633
6634void
e315cd28 6635qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 6636{
6637 unsigned long flags = 0;
e315cd28 6638 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 6639 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
6640
7ec0effd 6641 if (IS_P3P_TYPE(ha))
a9083016
GM		 6642 return;
6643
e315cd28 6644 vha->flags.online = 0;
fd34f556 6645 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 6646
6647 spin_lock_irqsave(&ha->hardware_lock, flags);
6648 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
6649 RD_REG_DWORD(&reg->hccr);
6650 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
6651 RD_REG_DWORD(&reg->hccr);
6652 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 6653
6654 if (IS_NOPOLLING_TYPE(ha))
6655 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 6656}
6657
4e08df3f
DM		 6658/* On sparc systems, obtain port and node WWN from firmware
6659 * properties.
6660 */
e315cd28
AC		 6661static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
6662 struct nvram_24xx *nv)
4e08df3f
DM		 6663{
6664#ifdef CONFIG_SPARC
e315cd28 6665 struct qla_hw_data *ha = vha->hw;
4e08df3f 6666 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 6667 struct device_node *dp = pci_device_to_OF_node(pdev);
6668 const u8 *val;
4e08df3f
DM		 6669 int len;
6670
6671 val = of_get_property(dp, "port-wwn", &len);
6672 if (val && len >= WWN_SIZE)
6673 memcpy(nv->port_name, val, WWN_SIZE);
6674
6675 val = of_get_property(dp, "node-wwn", &len);
6676 if (val && len >= WWN_SIZE)
6677 memcpy(nv->node_name, val, WWN_SIZE);
6678#endif
6679}
6680
0107109e 6681int
e315cd28 6682qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 6683{
4e08df3f 6684 int rval;
0107109e
AV		 6685 struct init_cb_24xx *icb;
6686 struct nvram_24xx *nv;
6687 uint32_t *dptr;
6688 uint8_t *dptr1, *dptr2;
6689 uint32_t chksum;
6690 uint16_t cnt;
e315cd28 6691 struct qla_hw_data *ha = vha->hw;
0107109e 6692
4e08df3f 6693 rval = QLA_SUCCESS;
0107109e 6694 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 6695 nv = ha->nvram;
0107109e
AV		 6696
6697 /* Determine NVRAM starting address. */
f73cb695 6698 if (ha->port_no == 0) {
e5b68a61
AC		 6699 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
6700 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
6701 } else {
0107109e 6702 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 6703 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
6704 }
f73cb695 6705
e5b68a61
AC		 6706 ha->nvram_size = sizeof(struct nvram_24xx);
6707 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 6708
281afe19
SJ		 6709 /* Get VPD data into cache */
6710 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 6711 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 6712 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
6713
6714 /* Get NVRAM data into cache and calculate checksum. */
0107109e 6715 dptr = (uint32_t *)nv;
e315cd28 6716 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 6717 ha->nvram_size);
da08ef5c
JC		 6718 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6719 chksum += le32_to_cpu(*dptr);
0107109e 6720
7c3df132
SK		 6721 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
6722 "Contents of NVRAM\n");
6723 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
6724 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 6725
6726 /* Bad NVRAM data, set defaults parameters. */
6727 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6728 || nv->id[3] != ' ' ||
ad950360 6729 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 6730 /* Reset NVRAM data. */
7c3df132 6731 ql_log(ql_log_warn, vha, 0x006b,
9e336520 6732 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 6733 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
6734 ql_log(ql_log_warn, vha, 0x006c,
6735 "Falling back to functioning (yet invalid -- WWPN) "
6736 "defaults.\n");
4e08df3f
DM		 6737
6738 /*
6739 * Set default initialization control block.
6740 */
6741 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6742 nv->nvram_version = cpu_to_le16(ICB_VERSION);
6743 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 6744 nv->frame_payload_size = 2048;
ad950360
BVA		 6745 nv->execution_throttle = cpu_to_le16(0xFFFF);
6746 nv->exchange_count = cpu_to_le16(0);
6747 nv->hard_address = cpu_to_le16(124);
4e08df3f 6748 nv->port_name[0] = 0x21;
f73cb695 6749 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 6750 nv->port_name[2] = 0x00;
6751 nv->port_name[3] = 0xe0;
6752 nv->port_name[4] = 0x8b;
6753 nv->port_name[5] = 0x1c;
6754 nv->port_name[6] = 0x55;
6755 nv->port_name[7] = 0x86;
6756 nv->node_name[0] = 0x20;
6757 nv->node_name[1] = 0x00;
6758 nv->node_name[2] = 0x00;
6759 nv->node_name[3] = 0xe0;
6760 nv->node_name[4] = 0x8b;
6761 nv->node_name[5] = 0x1c;
6762 nv->node_name[6] = 0x55;
6763 nv->node_name[7] = 0x86;
e315cd28 6764 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 6765 nv->login_retry_count = cpu_to_le16(8);
6766 nv->interrupt_delay_timer = cpu_to_le16(0);
6767 nv->login_timeout = cpu_to_le16(0);
4e08df3f 6768 nv->firmware_options_1 =
ad950360
BVA		 6769 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
6770 nv->firmware_options_2 = cpu_to_le32(2 << 4);
6771 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
6772 nv->firmware_options_3 = cpu_to_le32(2 << 13);
6773 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
6774 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 6775 nv->reset_delay = 5;
ad950360
BVA		 6776 nv->max_luns_per_target = cpu_to_le16(128);
6777 nv->port_down_retry_count = cpu_to_le16(30);
6778 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 6779
6780 rval = 1;
0107109e
AV		 6781 }
6782
726b8548 6783 if (qla_tgt_mode_enabled(vha)) {
2d70c103 6784 /* Don't enable full login after initial LIP */
ad950360 6785 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 6786 /* Don't enable LIP full login for initiator */
ad950360 6787 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 6788 }
6789
6790 qlt_24xx_config_nvram_stage1(vha, nv);
6791
0107109e 6792 /* Reset Initialization control block */
e315cd28 6793 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 6794
6795 /* Copy 1st segment. */
6796 dptr1 = (uint8_t *)icb;
6797 dptr2 = (uint8_t *)&nv->version;
6798 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6799 while (cnt--)
6800 *dptr1++ = *dptr2++;
6801
6802 icb->login_retry_count = nv->login_retry_count;
3ea66e28 6803 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 6804
6805 /* Copy 2nd segment. */
6806 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6807 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6808 cnt = (uint8_t *)&icb->reserved_3 -
6809 (uint8_t *)&icb->interrupt_delay_timer;
6810 while (cnt--)
6811 *dptr1++ = *dptr2++;
6812
6813 /*
6814 * Setup driver NVRAM options.
6815 */
e315cd28 6816 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 6817 "QLA2462");
0107109e 6818
2d70c103
NB		 6819 qlt_24xx_config_nvram_stage2(vha, icb);
6820
ad950360 6821 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 6822 /* Use alternate WWN? */
5341e868
AV		 6823 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6824 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6825 }
6826
0107109e 6827 /* Prepare nodename */
ad950360 6828 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 6829 /*
6830 * Firmware will apply the following mask if the nodename was
6831 * not provided.
6832 */
6833 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6834 icb->node_name[0] &= 0xF0;
6835 }
6836
6837 /* Set host adapter parameters. */
6838 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 6839 ha->flags.enable_lip_reset = 0;
6840 ha->flags.enable_lip_full_login =
6841 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6842 ha->flags.enable_target_reset =
6843 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 6844 ha->flags.enable_led_scheme = 0;
d4c760c2 6845 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 6846
fd0e7e4d
AV		 6847 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6848 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 6849
6850 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
6851 sizeof(ha->fw_seriallink_options24));
6852
6853 /* save HBA serial number */
6854 ha->serial0 = icb->port_name[5];
6855 ha->serial1 = icb->port_name[6];
6856 ha->serial2 = icb->port_name[7];
e315cd28
AC		 6857 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6858 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 6859
ad950360 6860 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 6861
0107109e
AV		 6862 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6863
6864 /* Set minimum login_timeout to 4 seconds. */
6865 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6866 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6867 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6868 nv->login_timeout = cpu_to_le16(4);
0107109e 6869 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 6870
00a537b8
AV		 6871 /* Set minimum RATOV to 100 tenths of a second. */
6872 ha->r_a_tov = 100;
0107109e
AV		 6873
6874 ha->loop_reset_delay = nv->reset_delay;
6875
6876 /* Link Down Timeout = 0:
6877 *
6878 * When Port Down timer expires we will start returning
6879 * I/O's to OS with "DID_NO_CONNECT".
6880 *
6881 * Link Down Timeout != 0:
6882 *
6883 * The driver waits for the link to come up after link down
6884 * before returning I/Os to OS with "DID_NO_CONNECT".
6885 */
6886 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6887 ha->loop_down_abort_time =
6888 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6889 } else {
6890 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6891 ha->loop_down_abort_time =
6892 (LOOP_DOWN_TIME - ha->link_down_timeout);
6893 }
6894
6895 /* Need enough time to try and get the port back. */
6896 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6897 if (qlport_down_retry)
6898 ha->port_down_retry_count = qlport_down_retry;
6899
6900 /* Set login_retry_count */
6901 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6902 if (ha->port_down_retry_count ==
6903 le16_to_cpu(nv->port_down_retry_count) &&
6904 ha->port_down_retry_count > 3)
6905 ha->login_retry_count = ha->port_down_retry_count;
6906 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6907 ha->login_retry_count = ha->port_down_retry_count;
6908 if (ql2xloginretrycount)
6909 ha->login_retry_count = ql2xloginretrycount;
6910
4fdfefe5 6911 /* Enable ZIO. */
e315cd28 6912 if (!vha->flags.init_done) {
4fdfefe5
AV		 6913 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6914 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6915 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6916 le16_to_cpu(icb->interrupt_delay_timer): 2;
6917 }
ad950360 6918 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 6919 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 6920 vha->flags.process_response_queue = 0;
4fdfefe5 6921 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 6922 ha->zio_mode = QLA_ZIO_MODE_6;
6923
7c3df132 6924 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 6925 "ZIO mode %d enabled; timer delay (%d us).\n",
6926 ha->zio_mode, ha->zio_timer * 100);
6927
6928 icb->firmware_options_2 |= cpu_to_le32(
6929 (uint32_t)ha->zio_mode);
6930 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 6931 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 6932 }
6933
4e08df3f 6934 if (rval) {
7c3df132
SK		 6935 ql_log(ql_log_warn, vha, 0x0070,
6936 "NVRAM configuration failed.\n");
4e08df3f
DM		 6937 }
6938 return (rval);
0107109e
AV		 6939}
6940
4243c115
SC		 6941uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
6942{
6943 struct qla27xx_image_status pri_image_status, sec_image_status;
6944 uint8_t valid_pri_image, valid_sec_image;
6945 uint32_t *wptr;
6946 uint32_t cnt, chksum, size;
6947 struct qla_hw_data *ha = vha->hw;
6948
6949 valid_pri_image = valid_sec_image = 1;
6950 ha->active_image = 0;
6951 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
6952
6953 if (!ha->flt_region_img_status_pri) {
6954 valid_pri_image = 0;
6955 goto check_sec_image;
6956 }
6957
6958 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
6959 ha->flt_region_img_status_pri, size);
6960
6961 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6962 ql_dbg(ql_dbg_init, vha, 0x018b,
6963 "Primary image signature (0x%x) not valid\n",
6964 pri_image_status.signature);
6965 valid_pri_image = 0;
6966 goto check_sec_image;
6967 }
6968
6969 wptr = (uint32_t *)(&pri_image_status);
6970 cnt = size;
6971
da08ef5c
JC		 6972 for (chksum = 0; cnt--; wptr++)
6973 chksum += le32_to_cpu(*wptr);
41dc529a 6974
4243c115
SC		 6975 if (chksum) {
6976 ql_dbg(ql_dbg_init, vha, 0x018c,
6977 "Checksum validation failed for primary image (0x%x)\n",
6978 chksum);
6979 valid_pri_image = 0;
6980 }
6981
6982check_sec_image:
6983 if (!ha->flt_region_img_status_sec) {
6984 valid_sec_image = 0;
6985 goto check_valid_image;
6986 }
6987
6988 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
6989 ha->flt_region_img_status_sec, size);
6990
6991 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6992 ql_dbg(ql_dbg_init, vha, 0x018d,
6993 "Secondary image signature(0x%x) not valid\n",
6994 sec_image_status.signature);
6995 valid_sec_image = 0;
6996 goto check_valid_image;
6997 }
6998
6999 wptr = (uint32_t *)(&sec_image_status);
7000 cnt = size;
da08ef5c
JC		 7001 for (chksum = 0; cnt--; wptr++)
7002 chksum += le32_to_cpu(*wptr);
4243c115
SC		 7003 if (chksum) {
7004 ql_dbg(ql_dbg_init, vha, 0x018e,
7005 "Checksum validation failed for secondary image (0x%x)\n",
7006 chksum);
7007 valid_sec_image = 0;
7008 }
7009
7010check_valid_image:
7011 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
7012 ha->active_image = QLA27XX_PRIMARY_IMAGE;
7013 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
7014 if (!ha->active_image ||
7015 pri_image_status.generation_number <
7016 sec_image_status.generation_number)
7017 ha->active_image = QLA27XX_SECONDARY_IMAGE;
7018 }
7019
7020 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
7021 ha->active_image == 0 ? "default bootld and fw" :
7022 ha->active_image == 1 ? "primary" :
7023 ha->active_image == 2 ? "secondary" :
7024 "Invalid");
7025
7026 return ha->active_image;
7027}
7028
413975a0 7029static int
cbc8eb67
AV		 7030qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
7031 uint32_t faddr)
d1c61909 7032{
73208dfd 7033 int rval = QLA_SUCCESS;
d1c61909 7034 int segments, fragment;
d1c61909
AV		 7035 uint32_t *dcode, dlen;
7036 uint32_t risc_addr;
7037 uint32_t risc_size;
7038 uint32_t i;
e315cd28 7039 struct qla_hw_data *ha = vha->hw;
73208dfd 7040 struct req_que *req = ha->req_q_map[0];
eaac30be 7041
7c3df132 7042 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 7043 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 7044
d1c61909
AV		 7045 rval = QLA_SUCCESS;
7046
7047 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7048 dcode = (uint32_t *)req->ring;
d1c61909
AV		 7049 *srisc_addr = 0;
7050
4243c115
SC		 7051 if (IS_QLA27XX(ha) &&
7052 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
7053 faddr = ha->flt_region_fw_sec;
7054
d1c61909 7055 /* Validate firmware image by checking version. */
e315cd28 7056 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 7057 for (i = 0; i < 4; i++)
7058 dcode[i] = be32_to_cpu(dcode[i]);
7059 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7060 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7061 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7062 dcode[3] == 0)) {
7c3df132
SK		 7063 ql_log(ql_log_fatal, vha, 0x008c,
7064 "Unable to verify the integrity of flash firmware "
7065 "image.\n");
7066 ql_log(ql_log_fatal, vha, 0x008d,
7067 "Firmware data: %08x %08x %08x %08x.\n",
7068 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 7069
7070 return QLA_FUNCTION_FAILED;
7071 }
7072
7073 while (segments && rval == QLA_SUCCESS) {
7074 /* Read segment's load information. */
e315cd28 7075 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 7076
7077 risc_addr = be32_to_cpu(dcode[2]);
7078 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7079 risc_size = be32_to_cpu(dcode[3]);
7080
7081 fragment = 0;
7082 while (risc_size > 0 && rval == QLA_SUCCESS) {
7083 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7084 if (dlen > risc_size)
7085 dlen = risc_size;
7086
7c3df132
SK		 7087 ql_dbg(ql_dbg_init, vha, 0x008e,
7088 "Loading risc segment@ risc addr %x "
7089 "number of dwords 0x%x offset 0x%x.\n",
7090 risc_addr, dlen, faddr);
d1c61909 7091
e315cd28 7092 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 7093 for (i = 0; i < dlen; i++)
7094 dcode[i] = swab32(dcode[i]);
7095
73208dfd 7096 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 7097 dlen);
7098 if (rval) {
7c3df132
SK		 7099 ql_log(ql_log_fatal, vha, 0x008f,
7100 "Failed to load segment %d of firmware.\n",
7101 fragment);
f261f7af 7102 return QLA_FUNCTION_FAILED;
d1c61909
AV		 7103 }
7104
7105 faddr += dlen;
7106 risc_addr += dlen;
7107 risc_size -= dlen;
7108 fragment++;
7109 }
7110
7111 /* Next segment. */
7112 segments--;
7113 }
7114
f73cb695
CD		 7115 if (!IS_QLA27XX(ha))
7116 return rval;
7117
7118 if (ha->fw_dump_template)
7119 vfree(ha->fw_dump_template);
7120 ha->fw_dump_template = NULL;
7121 ha->fw_dump_template_len = 0;
7122
7123 ql_dbg(ql_dbg_init, vha, 0x0161,
7124 "Loading fwdump template from %x\n", faddr);
7125 qla24xx_read_flash_data(vha, dcode, faddr, 7);
7126 risc_size = be32_to_cpu(dcode[2]);
7127 ql_dbg(ql_dbg_init, vha, 0x0162,
7128 "-> array size %x dwords\n", risc_size);
7129 if (risc_size == 0 || risc_size == ~0)
7130 goto default_template;
7131
7132 dlen = (risc_size - 8) * sizeof(*dcode);
7133 ql_dbg(ql_dbg_init, vha, 0x0163,
7134 "-> template allocating %x bytes...\n", dlen);
7135 ha->fw_dump_template = vmalloc(dlen);
7136 if (!ha->fw_dump_template) {
7137 ql_log(ql_log_warn, vha, 0x0164,
7138 "Failed fwdump template allocate %x bytes.\n", risc_size);
7139 goto default_template;
7140 }
7141
7142 faddr += 7;
7143 risc_size -= 8;
7144 dcode = ha->fw_dump_template;
7145 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
7146 for (i = 0; i < risc_size; i++)
7147 dcode[i] = le32_to_cpu(dcode[i]);
7148
7149 if (!qla27xx_fwdt_template_valid(dcode)) {
7150 ql_log(ql_log_warn, vha, 0x0165,
7151 "Failed fwdump template validate\n");
7152 goto default_template;
7153 }
7154
7155 dlen = qla27xx_fwdt_template_size(dcode);
7156 ql_dbg(ql_dbg_init, vha, 0x0166,
7157 "-> template size %x bytes\n", dlen);
7158 if (dlen > risc_size * sizeof(*dcode)) {
7159 ql_log(ql_log_warn, vha, 0x0167,
4fae52b5 7160 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7161 (size_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 7162 goto default_template;
7163 }
7164 ha->fw_dump_template_len = dlen;
7165 return rval;
7166
7167default_template:
7168 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
7169 if (ha->fw_dump_template)
7170 vfree(ha->fw_dump_template);
7171 ha->fw_dump_template = NULL;
7172 ha->fw_dump_template_len = 0;
7173
7174 dlen = qla27xx_fwdt_template_default_size();
7175 ql_dbg(ql_dbg_init, vha, 0x0169,
7176 "-> template allocating %x bytes...\n", dlen);
7177 ha->fw_dump_template = vmalloc(dlen);
7178 if (!ha->fw_dump_template) {
7179 ql_log(ql_log_warn, vha, 0x016a,
7180 "Failed fwdump template allocate %x bytes.\n", risc_size);
7181 goto failed_template;
7182 }
7183
7184 dcode = ha->fw_dump_template;
7185 risc_size = dlen / sizeof(*dcode);
7186 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
7187 for (i = 0; i < risc_size; i++)
7188 dcode[i] = be32_to_cpu(dcode[i]);
7189
7190 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7191 ql_log(ql_log_warn, vha, 0x016b,
7192 "Failed fwdump template validate\n");
7193 goto failed_template;
7194 }
7195
7196 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7197 ql_dbg(ql_dbg_init, vha, 0x016c,
7198 "-> template size %x bytes\n", dlen);
7199 ha->fw_dump_template_len = dlen;
7200 return rval;
7201
7202failed_template:
7203 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
7204 if (ha->fw_dump_template)
7205 vfree(ha->fw_dump_template);
7206 ha->fw_dump_template = NULL;
7207 ha->fw_dump_template_len = 0;
d1c61909
AV		 7208 return rval;
7209}
7210
e9454a88 7211#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 7212
0107109e 7213int
e315cd28 7214qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 7215{
7216 int rval;
7217 int i, fragment;
7218 uint16_t *wcode, *fwcode;
7219 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
7220 struct fw_blob *blob;
e315cd28 7221 struct qla_hw_data *ha = vha->hw;
73208dfd 7222 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 7223
7224 /* Load firmware blob. */
e315cd28 7225 blob = qla2x00_request_firmware(vha);
5433383e 7226 if (!blob) {
7c3df132 7227 ql_log(ql_log_info, vha, 0x0083,
94bcf830 7228 "Firmware image unavailable.\n");
7c3df132
SK		 7229 ql_log(ql_log_info, vha, 0x0084,
7230 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 7231 return QLA_FUNCTION_FAILED;
7232 }
7233
7234 rval = QLA_SUCCESS;
7235
73208dfd 7236 wcode = (uint16_t *)req->ring;
5433383e
AV		 7237 *srisc_addr = 0;
7238 fwcode = (uint16_t *)blob->fw->data;
7239 fwclen = 0;
7240
7241 /* Validate firmware image by checking version. */
7242 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 7243 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 7244 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 7245 blob->fw->size);
7246 goto fail_fw_integrity;
7247 }
7248 for (i = 0; i < 4; i++)
7249 wcode[i] = be16_to_cpu(fwcode[i + 4]);
7250 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
7251 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
7252 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 7253 ql_log(ql_log_fatal, vha, 0x0086,
7254 "Unable to verify integrity of firmware image.\n");
7255 ql_log(ql_log_fatal, vha, 0x0087,
7256 "Firmware data: %04x %04x %04x %04x.\n",
7257 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 7258 goto fail_fw_integrity;
7259 }
7260
7261 seg = blob->segs;
7262 while (*seg && rval == QLA_SUCCESS) {
7263 risc_addr = *seg;
7264 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
7265 risc_size = be16_to_cpu(fwcode[3]);
7266
7267 /* Validate firmware image size. */
7268 fwclen += risc_size * sizeof(uint16_t);
7269 if (blob->fw->size < fwclen) {
7c3df132 7270 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 7271 "Unable to verify integrity of firmware image "
5b5e0928 7272 "(%zd).\n", blob->fw->size);
5433383e
AV		 7273 goto fail_fw_integrity;
7274 }
7275
7276 fragment = 0;
7277 while (risc_size > 0 && rval == QLA_SUCCESS) {
7278 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
7279 if (wlen > risc_size)
7280 wlen = risc_size;
7c3df132
SK		 7281 ql_dbg(ql_dbg_init, vha, 0x0089,
7282 "Loading risc segment@ risc addr %x number of "
7283 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 7284
7285 for (i = 0; i < wlen; i++)
7286 wcode[i] = swab16(fwcode[i]);
7287
73208dfd 7288 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 7289 wlen);
7290 if (rval) {
7c3df132
SK		 7291 ql_log(ql_log_fatal, vha, 0x008a,
7292 "Failed to load segment %d of firmware.\n",
7293 fragment);
5433383e
AV		 7294 break;
7295 }
7296
7297 fwcode += wlen;
7298 risc_addr += wlen;
7299 risc_size -= wlen;
7300 fragment++;
7301 }
7302
7303 /* Next segment. */
7304 seg++;
7305 }
7306 return rval;
7307
7308fail_fw_integrity:
7309 return QLA_FUNCTION_FAILED;
7310}
7311
eaac30be
AV		 7312static int
7313qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 7314{
7315 int rval;
7316 int segments, fragment;
7317 uint32_t *dcode, dlen;
7318 uint32_t risc_addr;
7319 uint32_t risc_size;
7320 uint32_t i;
5433383e 7321 struct fw_blob *blob;
f73cb695
CD		 7322 const uint32_t *fwcode;
7323 uint32_t fwclen;
e315cd28 7324 struct qla_hw_data *ha = vha->hw;
73208dfd 7325 struct req_que *req = ha->req_q_map[0];
0107109e 7326
5433383e 7327 /* Load firmware blob. */
e315cd28 7328 blob = qla2x00_request_firmware(vha);
5433383e 7329 if (!blob) {
7c3df132 7330 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 7331 "Firmware image unavailable.\n");
7c3df132
SK		 7332 ql_log(ql_log_warn, vha, 0x0091,
7333 "Firmware images can be retrieved from: "
7334 QLA_FW_URL ".\n");
d1c61909 7335
eaac30be 7336 return QLA_FUNCTION_FAILED;
0107109e
AV		 7337 }
7338
cfb0919c
CD		 7339 ql_dbg(ql_dbg_init, vha, 0x0092,
7340 "FW: Loading via request-firmware.\n");
eaac30be 7341
0107109e
AV		 7342 rval = QLA_SUCCESS;
7343
7344 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7345 dcode = (uint32_t *)req->ring;
0107109e 7346 *srisc_addr = 0;
5433383e 7347 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 7348 fwclen = 0;
7349
7350 /* Validate firmware image by checking version. */
5433383e 7351 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 7352 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 7353 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 7354 blob->fw->size);
f73cb695 7355 return QLA_FUNCTION_FAILED;
0107109e
AV		 7356 }
7357 for (i = 0; i < 4; i++)
7358 dcode[i] = be32_to_cpu(fwcode[i + 4]);
7359 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7360 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7361 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7362 dcode[3] == 0)) {
7c3df132 7363 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 7364 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 7365 blob->fw->size);
7366 ql_log(ql_log_fatal, vha, 0x0095,
7367 "Firmware data: %08x %08x %08x %08x.\n",
7368 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 7369 return QLA_FUNCTION_FAILED;
0107109e
AV		 7370 }
7371
7372 while (segments && rval == QLA_SUCCESS) {
7373 risc_addr = be32_to_cpu(fwcode[2]);
7374 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7375 risc_size = be32_to_cpu(fwcode[3]);
7376
7377 /* Validate firmware image size. */
7378 fwclen += risc_size * sizeof(uint32_t);
5433383e 7379 if (blob->fw->size < fwclen) {
7c3df132 7380 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 7381 "Unable to verify integrity of firmware image "
5b5e0928 7382 "(%zd).\n", blob->fw->size);
f73cb695 7383 return QLA_FUNCTION_FAILED;
0107109e
AV		 7384 }
7385
7386 fragment = 0;
7387 while (risc_size > 0 && rval == QLA_SUCCESS) {
7388 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7389 if (dlen > risc_size)
7390 dlen = risc_size;
7391
7c3df132
SK		 7392 ql_dbg(ql_dbg_init, vha, 0x0097,
7393 "Loading risc segment@ risc addr %x "
7394 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 7395
7396 for (i = 0; i < dlen; i++)
7397 dcode[i] = swab32(fwcode[i]);
7398
73208dfd 7399 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 7400 dlen);
0107109e 7401 if (rval) {
7c3df132
SK		 7402 ql_log(ql_log_fatal, vha, 0x0098,
7403 "Failed to load segment %d of firmware.\n",
7404 fragment);
f261f7af 7405 return QLA_FUNCTION_FAILED;
0107109e
AV		 7406 }
7407
7408 fwcode += dlen;
7409 risc_addr += dlen;
7410 risc_size -= dlen;
7411 fragment++;
7412 }
7413
7414 /* Next segment. */
7415 segments--;
7416 }
f73cb695
CD		 7417
7418 if (!IS_QLA27XX(ha))
7419 return rval;
7420
7421 if (ha->fw_dump_template)
7422 vfree(ha->fw_dump_template);
7423 ha->fw_dump_template = NULL;
7424 ha->fw_dump_template_len = 0;
7425
7426 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 7427 "Loading fwdump template from %x\n",
7428 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 7429 risc_size = be32_to_cpu(fwcode[2]);
7430 ql_dbg(ql_dbg_init, vha, 0x172,
7431 "-> array size %x dwords\n", risc_size);
7432 if (risc_size == 0 || risc_size == ~0)
7433 goto default_template;
7434
7435 dlen = (risc_size - 8) * sizeof(*fwcode);
7436 ql_dbg(ql_dbg_init, vha, 0x0173,
7437 "-> template allocating %x bytes...\n", dlen);
7438 ha->fw_dump_template = vmalloc(dlen);
7439 if (!ha->fw_dump_template) {
7440 ql_log(ql_log_warn, vha, 0x0174,
7441 "Failed fwdump template allocate %x bytes.\n", risc_size);
7442 goto default_template;
7443 }
7444
7445 fwcode += 7;
7446 risc_size -= 8;
7447 dcode = ha->fw_dump_template;
7448 for (i = 0; i < risc_size; i++)
7449 dcode[i] = le32_to_cpu(fwcode[i]);
7450
7451 if (!qla27xx_fwdt_template_valid(dcode)) {
7452 ql_log(ql_log_warn, vha, 0x0175,
7453 "Failed fwdump template validate\n");
7454 goto default_template;
7455 }
7456
7457 dlen = qla27xx_fwdt_template_size(dcode);
7458 ql_dbg(ql_dbg_init, vha, 0x0176,
7459 "-> template size %x bytes\n", dlen);
7460 if (dlen > risc_size * sizeof(*fwcode)) {
7461 ql_log(ql_log_warn, vha, 0x0177,
4fae52b5 7462 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7463 (size_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 7464 goto default_template;
7465 }
7466 ha->fw_dump_template_len = dlen;
0107109e
AV		 7467 return rval;
7468
f73cb695
CD		 7469default_template:
7470 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
7471 if (ha->fw_dump_template)
7472 vfree(ha->fw_dump_template);
7473 ha->fw_dump_template = NULL;
7474 ha->fw_dump_template_len = 0;
7475
7476 dlen = qla27xx_fwdt_template_default_size();
7477 ql_dbg(ql_dbg_init, vha, 0x0179,
7478 "-> template allocating %x bytes...\n", dlen);
7479 ha->fw_dump_template = vmalloc(dlen);
7480 if (!ha->fw_dump_template) {
7481 ql_log(ql_log_warn, vha, 0x017a,
7482 "Failed fwdump template allocate %x bytes.\n", risc_size);
7483 goto failed_template;
7484 }
7485
7486 dcode = ha->fw_dump_template;
7487 risc_size = dlen / sizeof(*fwcode);
7488 fwcode = qla27xx_fwdt_template_default();
7489 for (i = 0; i < risc_size; i++)
7490 dcode[i] = be32_to_cpu(fwcode[i]);
7491
7492 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7493 ql_log(ql_log_warn, vha, 0x017b,
7494 "Failed fwdump template validate\n");
7495 goto failed_template;
7496 }
7497
7498 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7499 ql_dbg(ql_dbg_init, vha, 0x017c,
7500 "-> template size %x bytes\n", dlen);
7501 ha->fw_dump_template_len = dlen;
7502 return rval;
7503
7504failed_template:
7505 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
7506 if (ha->fw_dump_template)
7507 vfree(ha->fw_dump_template);
7508 ha->fw_dump_template = NULL;
7509 ha->fw_dump_template_len = 0;
7510 return rval;
0107109e 7511}
18c6c127 7512
eaac30be
AV		 7513int
7514qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7515{
7516 int rval;
7517
e337d907
AV		 7518 if (ql2xfwloadbin == 1)
7519 return qla81xx_load_risc(vha, srisc_addr);
7520
eaac30be
AV		 7521 /*
7522 * FW Load priority:
7523 * 1) Firmware via request-firmware interface (.bin file).
7524 * 2) Firmware residing in flash.
7525 */
7526 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7527 if (rval == QLA_SUCCESS)
7528 return rval;
7529
cbc8eb67
AV		 7530 return qla24xx_load_risc_flash(vha, srisc_addr,
7531 vha->hw->flt_region_fw);
eaac30be
AV		 7532}
7533
7534int
7535qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7536{
7537 int rval;
cbc8eb67 7538 struct qla_hw_data *ha = vha->hw;
eaac30be 7539
e337d907 7540 if (ql2xfwloadbin == 2)
cbc8eb67 7541 goto try_blob_fw;
e337d907 7542
eaac30be
AV		 7543 /*
7544 * FW Load priority:
7545 * 1) Firmware residing in flash.
7546 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 7547 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 7548 */
cbc8eb67 7549 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 7550 if (rval == QLA_SUCCESS)
7551 return rval;
7552
cbc8eb67
AV		 7553try_blob_fw:
7554 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7555 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
7556 return rval;
7557
7c3df132
SK		 7558 ql_log(ql_log_info, vha, 0x0099,
7559 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 7560 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
7561 if (rval != QLA_SUCCESS)
7562 return rval;
7563
7c3df132 7564 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 7565 ha->flags.running_gold_fw = 1;
cbc8eb67 7566 return rval;
eaac30be
AV		 7567}
7568
18c6c127 7569void
e315cd28 7570qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 7571{
7572 int ret, retries;
e315cd28 7573 struct qla_hw_data *ha = vha->hw;
18c6c127 7574
85880801
AV		 7575 if (ha->flags.pci_channel_io_perm_failure)
7576 return;
e428924c 7577 if (!IS_FWI2_CAPABLE(ha))
18c6c127 7578 return;
75edf81d
AV		 7579 if (!ha->fw_major_version)
7580 return;
ec7193e2
QT		 7581 if (!ha->flags.fw_started)
7582 return;
18c6c127 7583
e315cd28 7584 ret = qla2x00_stop_firmware(vha);
7c7f1f29 7585 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 7586 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 7587 ha->isp_ops->reset_chip(vha);
7588 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 7589 continue;
e315cd28 7590 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 7591 continue;
7c3df132
SK		 7592 ql_log(ql_log_info, vha, 0x8015,
7593 "Attempting retry of stop-firmware command.\n");
e315cd28 7594 ret = qla2x00_stop_firmware(vha);
18c6c127 7595 }
ec7193e2 7596
4b60c827 7597 QLA_FW_STOPPED(ha);
ec7193e2 7598 ha->flags.fw_init_done = 0;
18c6c127 7599}
2c3dfe3f
SJ		 7600
7601int
e315cd28 7602qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 7603{
7604 int rval = QLA_SUCCESS;
0b91d116 7605 int rval2;
2c3dfe3f 7606 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 7607 struct qla_hw_data *ha = vha->hw;
7608 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 7609 struct req_que *req;
7610 struct rsp_que *rsp;
2c3dfe3f 7611
e315cd28 7612 if (!vha->vp_idx)
2c3dfe3f
SJ		 7613 return -EINVAL;
7614
e315cd28 7615 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 7616 if (vha->qpair)
7617 req = vha->qpair->req;
67c2e93a 7618 else
d7459527 7619 req = ha->req_q_map[0];
67c2e93a
AC		 7620 rsp = req->rsp;
7621
2c3dfe3f 7622 if (rval == QLA_SUCCESS) {
e315cd28 7623 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 7624 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 7625 }
7626
e315cd28 7627 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 7628
7629 /* Login to SNS first */
0b91d116
CD		 7630 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
7631 BIT_1);
7632 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
7633 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
7634 ql_dbg(ql_dbg_init, vha, 0x0120,
7635 "Failed SNS login: loop_id=%x, rval2=%d\n",
7636 NPH_SNS, rval2);
7637 else
7638 ql_dbg(ql_dbg_init, vha, 0x0103,
7639 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
7640 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
7641 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 7642 return (QLA_FUNCTION_FAILED);
7643 }
7644
e315cd28
AC		 7645 atomic_set(&vha->loop_down_timer, 0);
7646 atomic_set(&vha->loop_state, LOOP_UP);
7647 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7648 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
7649 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 7650
7651 return rval;
7652}
4d4df193
HK		 7653
7654/* 84XX Support **************************************************************/
7655
7656static LIST_HEAD(qla_cs84xx_list);
7657static DEFINE_MUTEX(qla_cs84xx_mutex);
7658
7659static struct qla_chip_state_84xx *
e315cd28 7660qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 7661{
7662 struct qla_chip_state_84xx *cs84xx;
e315cd28 7663 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7664
7665 mutex_lock(&qla_cs84xx_mutex);
7666
7667 /* Find any shared 84xx chip. */
7668 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
7669 if (cs84xx->bus == ha->pdev->bus) {
7670 kref_get(&cs84xx->kref);
7671 goto done;
7672 }
7673 }
7674
7675 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
7676 if (!cs84xx)
7677 goto done;
7678
7679 kref_init(&cs84xx->kref);
7680 spin_lock_init(&cs84xx->access_lock);
7681 mutex_init(&cs84xx->fw_update_mutex);
7682 cs84xx->bus = ha->pdev->bus;
7683
7684 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
7685done:
7686 mutex_unlock(&qla_cs84xx_mutex);
7687 return cs84xx;
7688}
7689
7690static void
7691__qla84xx_chip_release(struct kref *kref)
7692{
7693 struct qla_chip_state_84xx *cs84xx =
7694 container_of(kref, struct qla_chip_state_84xx, kref);
7695
7696 mutex_lock(&qla_cs84xx_mutex);
7697 list_del(&cs84xx->list);
7698 mutex_unlock(&qla_cs84xx_mutex);
7699 kfree(cs84xx);
7700}
7701
7702void
e315cd28 7703qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 7704{
e315cd28 7705 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7706 if (ha->cs84xx)
7707 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
7708}
7709
7710static int
e315cd28 7711qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 7712{
7713 int rval;
7714 uint16_t status[2];
e315cd28 7715 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7716
7717 mutex_lock(&ha->cs84xx->fw_update_mutex);
7718
e315cd28 7719 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 7720
7721 mutex_unlock(&ha->cs84xx->fw_update_mutex);
7722
7723 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
7724 QLA_SUCCESS;
7725}
3a03eb79
AV		 7726
7727/* 81XX Support **************************************************************/
7728
7729int
7730qla81xx_nvram_config(scsi_qla_host_t *vha)
7731{
7732 int rval;
7733 struct init_cb_81xx *icb;
7734 struct nvram_81xx *nv;
7735 uint32_t *dptr;
7736 uint8_t *dptr1, *dptr2;
7737 uint32_t chksum;
7738 uint16_t cnt;
7739 struct qla_hw_data *ha = vha->hw;
7740
7741 rval = QLA_SUCCESS;
7742 icb = (struct init_cb_81xx *)ha->init_cb;
7743 nv = ha->nvram;
7744
7745 /* Determine NVRAM starting address. */
7746 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 7747 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 7748 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
7749 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 7750
7751 /* Get VPD data into cache */
7752 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 7753 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
7754 ha->vpd_size);
3a03eb79
AV		 7755
7756 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 7757 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 7758 ha->nvram_size);
3d79038f 7759 dptr = (uint32_t *)nv;
da08ef5c
JC		 7760 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7761 chksum += le32_to_cpu(*dptr);
3a03eb79 7762
7c3df132
SK		 7763 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
7764 "Contents of NVRAM:\n");
7765 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
7766 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 7767
7768 /* Bad NVRAM data, set defaults parameters. */
7769 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
7770 || nv->id[3] != ' ' ||
ad950360 7771 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 7772 /* Reset NVRAM data. */
7c3df132 7773 ql_log(ql_log_info, vha, 0x0073,
9e336520 7774 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 7775 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 7776 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 7777 ql_log(ql_log_info, vha, 0x0074,
7778 "Falling back to functioning (yet invalid -- WWPN) "
7779 "defaults.\n");
3a03eb79
AV		 7780
7781 /*
7782 * Set default initialization control block.
7783 */
7784 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 7785 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7786 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7787 nv->frame_payload_size = 2048;
ad950360
BVA		 7788 nv->execution_throttle = cpu_to_le16(0xFFFF);
7789 nv->exchange_count = cpu_to_le16(0);
3a03eb79 7790 nv->port_name[0] = 0x21;
f73cb695 7791 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 7792 nv->port_name[2] = 0x00;
7793 nv->port_name[3] = 0xe0;
7794 nv->port_name[4] = 0x8b;
7795 nv->port_name[5] = 0x1c;
7796 nv->port_name[6] = 0x55;
7797 nv->port_name[7] = 0x86;
7798 nv->node_name[0] = 0x20;
7799 nv->node_name[1] = 0x00;
7800 nv->node_name[2] = 0x00;
7801 nv->node_name[3] = 0xe0;
7802 nv->node_name[4] = 0x8b;
7803 nv->node_name[5] = 0x1c;
7804 nv->node_name[6] = 0x55;
7805 nv->node_name[7] = 0x86;
ad950360
BVA		 7806 nv->login_retry_count = cpu_to_le16(8);
7807 nv->interrupt_delay_timer = cpu_to_le16(0);
7808 nv->login_timeout = cpu_to_le16(0);
3a03eb79 7809 nv->firmware_options_1 =
ad950360
BVA		 7810 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7811 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7812 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7813 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7814 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7815 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 7816 nv->reset_delay = 5;
ad950360
BVA		 7817 nv->max_luns_per_target = cpu_to_le16(128);
7818 nv->port_down_retry_count = cpu_to_le16(30);
7819 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 7820 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 7821 nv->enode_mac[1] = 0xC0;
7822 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 7823 nv->enode_mac[3] = 0x04;
7824 nv->enode_mac[4] = 0x05;
f73cb695 7825 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7826
7827 rval = 1;
7828 }
7829
9e522cd8
AE		 7830 if (IS_T10_PI_CAPABLE(ha))
7831 nv->frame_payload_size &= ~7;
7832
aa230bc5
AE		 7833 qlt_81xx_config_nvram_stage1(vha, nv);
7834
3a03eb79 7835 /* Reset Initialization control block */
773120e4 7836 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 7837
7838 /* Copy 1st segment. */
7839 dptr1 = (uint8_t *)icb;
7840 dptr2 = (uint8_t *)&nv->version;
7841 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7842 while (cnt--)
7843 *dptr1++ = *dptr2++;
7844
7845 icb->login_retry_count = nv->login_retry_count;
7846
7847 /* Copy 2nd segment. */
7848 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7849 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7850 cnt = (uint8_t *)&icb->reserved_5 -
7851 (uint8_t *)&icb->interrupt_delay_timer;
7852 while (cnt--)
7853 *dptr1++ = *dptr2++;
7854
7855 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
7856 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
7857 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 7858 icb->enode_mac[0] = 0x00;
7859 icb->enode_mac[1] = 0xC0;
7860 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 7861 icb->enode_mac[3] = 0x04;
7862 icb->enode_mac[4] = 0x05;
f73cb695 7863 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7864 }
7865
b64b0e8f
AV		 7866 /* Use extended-initialization control block. */
7867 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
7868
3a03eb79
AV		 7869 /*
7870 * Setup driver NVRAM options.
7871 */
7872 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 7873 "QLE8XXX");
3a03eb79 7874
aa230bc5
AE		 7875 qlt_81xx_config_nvram_stage2(vha, icb);
7876
3a03eb79 7877 /* Use alternate WWN? */
ad950360 7878 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 7879 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7880 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7881 }
7882
7883 /* Prepare nodename */
ad950360 7884 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 7885 /*
7886 * Firmware will apply the following mask if the nodename was
7887 * not provided.
7888 */
7889 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7890 icb->node_name[0] &= 0xF0;
7891 }
7892
7893 /* Set host adapter parameters. */
7894 ha->flags.disable_risc_code_load = 0;
7895 ha->flags.enable_lip_reset = 0;
7896 ha->flags.enable_lip_full_login =
7897 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7898 ha->flags.enable_target_reset =
7899 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
7900 ha->flags.enable_led_scheme = 0;
7901 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
7902
7903 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7904 (BIT_6 | BIT_5 | BIT_4)) >> 4;
7905
7906 /* save HBA serial number */
7907 ha->serial0 = icb->port_name[5];
7908 ha->serial1 = icb->port_name[6];
7909 ha->serial2 = icb->port_name[7];
7910 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7911 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7912
ad950360 7913 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 7914
7915 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7916
7917 /* Set minimum login_timeout to 4 seconds. */
7918 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7919 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7920 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7921 nv->login_timeout = cpu_to_le16(4);
3a03eb79 7922 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 7923
7924 /* Set minimum RATOV to 100 tenths of a second. */
7925 ha->r_a_tov = 100;
7926
7927 ha->loop_reset_delay = nv->reset_delay;
7928
7929 /* Link Down Timeout = 0:
7930 *
7ec0effd 7931 * When Port Down timer expires we will start returning
3a03eb79
AV		 7932 * I/O's to OS with "DID_NO_CONNECT".
7933 *
7934 * Link Down Timeout != 0:
7935 *
7936 * The driver waits for the link to come up after link down
7937 * before returning I/Os to OS with "DID_NO_CONNECT".
7938 */
7939 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7940 ha->loop_down_abort_time =
7941 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7942 } else {
7943 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7944 ha->loop_down_abort_time =
7945 (LOOP_DOWN_TIME - ha->link_down_timeout);
7946 }
7947
7948 /* Need enough time to try and get the port back. */
7949 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7950 if (qlport_down_retry)
7951 ha->port_down_retry_count = qlport_down_retry;
7952
7953 /* Set login_retry_count */
7954 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7955 if (ha->port_down_retry_count ==
7956 le16_to_cpu(nv->port_down_retry_count) &&
7957 ha->port_down_retry_count > 3)
7958 ha->login_retry_count = ha->port_down_retry_count;
7959 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7960 ha->login_retry_count = ha->port_down_retry_count;
7961 if (ql2xloginretrycount)
7962 ha->login_retry_count = ql2xloginretrycount;
7963
6246b8a1 7964 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 7965 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 7966 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 7967
3a03eb79
AV		 7968 /* Enable ZIO. */
7969 if (!vha->flags.init_done) {
7970 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7971 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7972 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7973 le16_to_cpu(icb->interrupt_delay_timer): 2;
7974 }
ad950360 7975 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 7976 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
7977 vha->flags.process_response_queue = 0;
7978 if (ha->zio_mode != QLA_ZIO_DISABLED) {
7979 ha->zio_mode = QLA_ZIO_MODE_6;
7980
7c3df132 7981 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 7982 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 7983 ha->zio_mode,
7984 ha->zio_timer * 100);
3a03eb79
AV		 7985
7986 icb->firmware_options_2 |= cpu_to_le32(
7987 (uint32_t)ha->zio_mode);
7988 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
7989 vha->flags.process_response_queue = 1;
7990 }
7991
41dc529a
QT		 7992 /* enable RIDA Format2 */
7993 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha))
7994 icb->firmware_options_3 |= BIT_0;
7995
edd05de1
DG		 7996 if (IS_QLA27XX(ha)) {
7997 icb->firmware_options_3 |= BIT_8;
7998 ql_dbg(ql_log_info, vha, 0x0075,
7999 "Enabling direct connection.\n");
8000 }
8001
3a03eb79 8002 if (rval) {
7c3df132
SK		 8003 ql_log(ql_log_warn, vha, 0x0076,
8004 "NVRAM configuration failed.\n");
3a03eb79
AV		 8005 }
8006 return (rval);
8007}
8008
a9083016
GM		 8009int
8010qla82xx_restart_isp(scsi_qla_host_t *vha)
8011{
8012 int status, rval;
a9083016
GM		 8013 struct qla_hw_data *ha = vha->hw;
8014 struct req_que *req = ha->req_q_map[0];
8015 struct rsp_que *rsp = ha->rsp_q_map[0];
8016 struct scsi_qla_host *vp;
feafb7b1 8017 unsigned long flags;
a9083016
GM		 8018
8019 status = qla2x00_init_rings(vha);
8020 if (!status) {
8021 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8022 ha->flags.chip_reset_done = 1;
8023
8024 status = qla2x00_fw_ready(vha);
8025 if (!status) {
a9083016
GM		 8026 /* Issue a marker after FW becomes ready. */
8027 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 8028 vha->flags.online = 1;
7108b76e 8029 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 8030 }
8031
8032 /* if no cable then assume it's good */
8033 if ((vha->device_flags & DFLG_NO_CABLE))
8034 status = 0;
a9083016
GM		 8035 }
8036
8037 if (!status) {
8038 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8039
8040 if (!atomic_read(&vha->loop_down_timer)) {
8041 /*
8042 * Issue marker command only when we are going
8043 * to start the I/O .
8044 */
8045 vha->marker_needed = 1;
8046 }
8047
a9083016
GM		 8048 ha->isp_ops->enable_intrs(ha);
8049
8050 ha->isp_abort_cnt = 0;
8051 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
8052
53296788 8053 /* Update the firmware version */
3173167f 8054 status = qla82xx_check_md_needed(vha);
53296788 8055
a9083016
GM		 8056 if (ha->fce) {
8057 ha->flags.fce_enabled = 1;
8058 memset(ha->fce, 0,
8059 fce_calc_size(ha->fce_bufs));
8060 rval = qla2x00_enable_fce_trace(vha,
8061 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
8062 &ha->fce_bufs);
8063 if (rval) {
cfb0919c 8064 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 8065 "Unable to reinitialize FCE (%d).\n",
8066 rval);
a9083016
GM		 8067 ha->flags.fce_enabled = 0;
8068 }
8069 }
8070
8071 if (ha->eft) {
8072 memset(ha->eft, 0, EFT_SIZE);
8073 rval = qla2x00_enable_eft_trace(vha,
8074 ha->eft_dma, EFT_NUM_BUFFERS);
8075 if (rval) {
cfb0919c 8076 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 8077 "Unable to reinitialize EFT (%d).\n",
8078 rval);
a9083016
GM		 8079 }
8080 }
a9083016
GM		 8081 }
8082
8083 if (!status) {
cfb0919c 8084 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 8085 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 8086
8087 spin_lock_irqsave(&ha->vport_slock, flags);
8088 list_for_each_entry(vp, &ha->vp_list, list) {
8089 if (vp->vp_idx) {
8090 atomic_inc(&vp->vref_count);
8091 spin_unlock_irqrestore(&ha->vport_slock, flags);
8092
a9083016 8093 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 8094
8095 spin_lock_irqsave(&ha->vport_slock, flags);
8096 atomic_dec(&vp->vref_count);
8097 }
a9083016 8098 }
feafb7b1
AE		 8099 spin_unlock_irqrestore(&ha->vport_slock, flags);
8100
a9083016 8101 } else {
cfb0919c 8102 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 8103 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 8104 }
8105
8106 return status;
8107}
8108
3a03eb79 8109void
ae97c91e 8110qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 8111{
ae97c91e
AV		 8112 struct qla_hw_data *ha = vha->hw;
8113
f198cafa
HM		 8114 /* Hold status IOCBs until ABTS response received. */
8115 if (ql2xfwholdabts)
8116 ha->fw_options[3] |= BIT_12;
8117
088d09d4
GM		 8118 /* Set Retry FLOGI in case of P2P connection */
8119 if (ha->operating_mode == P2P) {
8120 ha->fw_options[2] |= BIT_3;
8121 ql_dbg(ql_dbg_disc, vha, 0x2103,
8122 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
8123 __func__, ha->fw_options[2]);
8124 }
8125
41dc529a
QT		 8126 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
8127 if (ql2xmvasynctoatio) {
8128 if (qla_tgt_mode_enabled(vha) ||
8129 qla_dual_mode_enabled(vha))
8130 ha->fw_options[2] |= BIT_11;
8131 else
8132 ha->fw_options[2] &= ~BIT_11;
8133 }
8134
f7e761f5 8135 if (qla_tgt_mode_enabled(vha) ||
2da52737
QT		 8136 qla_dual_mode_enabled(vha)) {
8137 /* FW auto send SCSI status during */
8138 ha->fw_options[1] |= BIT_8;
8139 ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
8140
8141 /* FW perform Exchange validation */
f7e761f5 8142 ha->fw_options[2] |= BIT_4;
2da52737
QT		 8143 } else {
8144 ha->fw_options[1] &= ~BIT_8;
8145 ha->fw_options[10] &= 0x00ff;
8146
f7e761f5 8147 ha->fw_options[2] &= ~BIT_4;
2da52737 8148 }
f7e761f5 8149
41dc529a
QT		 8150 if (ql2xetsenable) {
8151 /* Enable ETS Burst. */
8152 memset(ha->fw_options, 0, sizeof(ha->fw_options));
8153 ha->fw_options[2] |= BIT_9;
8154 }
8155
83548fe2
QT		 8156 ql_dbg(ql_dbg_init, vha, 0x00e9,
8157 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
8158 __func__, ha->fw_options[1], ha->fw_options[2],
8159 ha->fw_options[3], vha->host->active_mode);
ae97c91e 8160
ae97c91e 8161 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 8162}
09ff701a
SR		 8163
8164/*
8165 * qla24xx_get_fcp_prio
8166 * Gets the fcp cmd priority value for the logged in port.
8167 * Looks for a match of the port descriptors within
8168 * each of the fcp prio config entries. If a match is found,
8169 * the tag (priority) value is returned.
8170 *
8171 * Input:
21090cbe 8172 * vha = scsi host structure pointer.
09ff701a
SR		 8173 * fcport = port structure pointer.
8174 *
8175 * Return:
6c452a45 8176 * non-zero (if found)
f28a0a96 8177 * -1 (if not found)
09ff701a
SR		 8178 *
8179 * Context:
8180 * Kernel context
8181 */
f28a0a96 8182static int
09ff701a
SR		 8183qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
8184{
8185 int i, entries;
8186 uint8_t pid_match, wwn_match;
f28a0a96 8187 int priority;
09ff701a
SR		 8188 uint32_t pid1, pid2;
8189 uint64_t wwn1, wwn2;
8190 struct qla_fcp_prio_entry *pri_entry;
8191 struct qla_hw_data *ha = vha->hw;
8192
8193 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 8194 return -1;
09ff701a 8195
f28a0a96 8196 priority = -1;
09ff701a
SR		 8197 entries = ha->fcp_prio_cfg->num_entries;
8198 pri_entry = &ha->fcp_prio_cfg->entry[0];
8199
8200 for (i = 0; i < entries; i++) {
8201 pid_match = wwn_match = 0;
8202
8203 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
8204 pri_entry++;
8205 continue;
8206 }
8207
8208 /* check source pid for a match */
8209 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
8210 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
8211 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
8212 if (pid1 == INVALID_PORT_ID)
8213 pid_match++;
8214 else if (pid1 == pid2)
8215 pid_match++;
8216 }
8217
8218 /* check destination pid for a match */
8219 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
8220 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
8221 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
8222 if (pid1 == INVALID_PORT_ID)
8223 pid_match++;
8224 else if (pid1 == pid2)
8225 pid_match++;
8226 }
8227
8228 /* check source WWN for a match */
8229 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
8230 wwn1 = wwn_to_u64(vha->port_name);
8231 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
8232 if (wwn2 == (uint64_t)-1)
8233 wwn_match++;
8234 else if (wwn1 == wwn2)
8235 wwn_match++;
8236 }
8237
8238 /* check destination WWN for a match */
8239 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
8240 wwn1 = wwn_to_u64(fcport->port_name);
8241 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
8242 if (wwn2 == (uint64_t)-1)
8243 wwn_match++;
8244 else if (wwn1 == wwn2)
8245 wwn_match++;
8246 }
8247
8248 if (pid_match == 2 || wwn_match == 2) {
8249 /* Found a matching entry */
8250 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
8251 priority = pri_entry->tag;
8252 break;
8253 }
8254
8255 pri_entry++;
8256 }
8257
8258 return priority;
8259}
8260
8261/*
8262 * qla24xx_update_fcport_fcp_prio
8263 * Activates fcp priority for the logged in fc port
8264 *
8265 * Input:
21090cbe 8266 * vha = scsi host structure pointer.
09ff701a
SR		 8267 * fcp = port structure pointer.
8268 *
8269 * Return:
8270 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8271 *
8272 * Context:
8273 * Kernel context.
8274 */
8275int
21090cbe 8276qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 8277{
8278 int ret;
f28a0a96 8279 int priority;
09ff701a
SR		 8280 uint16_t mb[5];
8281
21090cbe
MI		 8282 if (fcport->port_type != FCT_TARGET ||
8283 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 8284 return QLA_FUNCTION_FAILED;
8285
21090cbe 8286 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 8287 if (priority < 0)
8288 return QLA_FUNCTION_FAILED;
8289
7ec0effd 8290 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 8291 fcport->fcp_prio = priority & 0xf;
8292 return QLA_SUCCESS;
8293 }
8294
21090cbe 8295 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 8296 if (ret == QLA_SUCCESS) {
8297 if (fcport->fcp_prio != priority)
8298 ql_dbg(ql_dbg_user, vha, 0x709e,
8299 "Updated FCP_CMND priority - value=%d loop_id=%d "
8300 "port_id=%02x%02x%02x.\n", priority,
8301 fcport->loop_id, fcport->d_id.b.domain,
8302 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 8303 fcport->fcp_prio = priority & 0xf;
cfb0919c 8304 } else
7c3df132 8305 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 8306 "Unable to update FCP_CMND priority - ret=0x%x for "
8307 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
8308 fcport->d_id.b.domain, fcport->d_id.b.area,
8309 fcport->d_id.b.al_pa);
09ff701a
SR		 8310 return ret;
8311}
8312
8313/*
8314 * qla24xx_update_all_fcp_prio
8315 * Activates fcp priority for all the logged in ports
8316 *
8317 * Input:
8318 * ha = adapter block pointer.
8319 *
8320 * Return:
8321 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8322 *
8323 * Context:
8324 * Kernel context.
8325 */
8326int
8327qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
8328{
8329 int ret;
8330 fc_port_t *fcport;
8331
8332 ret = QLA_FUNCTION_FAILED;
8333 /* We need to set priority for all logged in ports */
8334 list_for_each_entry(fcport, &vha->vp_fcports, list)
8335 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
8336
8337 return ret;
8338}
d7459527 8339
82de802a
QT		 8340struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
8341 int vp_idx, bool startqp)
d7459527
MH		 8342{
8343 int rsp_id = 0;
8344 int req_id = 0;
8345 int i;
8346 struct qla_hw_data *ha = vha->hw;
8347 uint16_t qpair_id = 0;
8348 struct qla_qpair *qpair = NULL;
8349 struct qla_msix_entry *msix;
8350
8351 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
8352 ql_log(ql_log_warn, vha, 0x00181,
8353 "FW/Driver is not multi-queue capable.\n");
8354 return NULL;
8355 }
8356
c38d1baf 8357 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 8358 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
8359 if (qpair == NULL) {
8360 ql_log(ql_log_warn, vha, 0x0182,
8361 "Failed to allocate memory for queue pair.\n");
8362 return NULL;
8363 }
8364 memset(qpair, 0, sizeof(struct qla_qpair));
8365
8366 qpair->hw = vha->hw;
25ff6af1 8367 qpair->vha = vha;
82de802a
QT		 8368 qpair->qp_lock_ptr = &qpair->qp_lock;
8369 spin_lock_init(&qpair->qp_lock);
af7bb382 8370 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d7459527
MH		 8371
8372 /* Assign available que pair id */
8373 mutex_lock(&ha->mq_lock);
8374 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 8375 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 8376 mutex_unlock(&ha->mq_lock);
8377 ql_log(ql_log_warn, vha, 0x0183,
8378 "No resources to create additional q pair.\n");
8379 goto fail_qid_map;
8380 }
b95b9452 8381 ha->num_qpairs++;
d7459527
MH		 8382 set_bit(qpair_id, ha->qpair_qid_map);
8383 ha->queue_pair_map[qpair_id] = qpair;
8384 qpair->id = qpair_id;
8385 qpair->vp_idx = vp_idx;
e6373f33 8386 qpair->fw_started = ha->flags.fw_started;
e326d22a 8387 INIT_LIST_HEAD(&qpair->hints_list);
cf19c45d 8388 INIT_LIST_HEAD(&qpair->nvme_done_list);
7c3f8fd1
QT		 8389 qpair->chip_reset = ha->base_qpair->chip_reset;
8390 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
8391 qpair->enable_explicit_conf =
8392 ha->base_qpair->enable_explicit_conf;
d7459527
MH		 8393
8394 for (i = 0; i < ha->msix_count; i++) {
093df737 8395 msix = &ha->msix_entries[i];
d7459527
MH		 8396 if (msix->in_use)
8397 continue;
8398 qpair->msix = msix;
83548fe2 8399 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
d7459527
MH		 8400 "Vector %x selected for qpair\n", msix->vector);
8401 break;
8402 }
8403 if (!qpair->msix) {
8404 ql_log(ql_log_warn, vha, 0x0184,
8405 "Out of MSI-X vectors!.\n");
8406 goto fail_msix;
8407 }
8408
8409 qpair->msix->in_use = 1;
8410 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
8abfa9e2
QT		 8411 qpair->pdev = ha->pdev;
8412 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
8413 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
d7459527
MH		 8414
8415 mutex_unlock(&ha->mq_lock);
8416
8417 /* Create response queue first */
82de802a 8418 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
d7459527
MH		 8419 if (!rsp_id) {
8420 ql_log(ql_log_warn, vha, 0x0185,
8421 "Failed to create response queue.\n");
8422 goto fail_rsp;
8423 }
8424
8425 qpair->rsp = ha->rsp_q_map[rsp_id];
8426
8427 /* Create request queue */
82de802a
QT		 8428 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
8429 startqp);
d7459527
MH		 8430 if (!req_id) {
8431 ql_log(ql_log_warn, vha, 0x0186,
8432 "Failed to create request queue.\n");
8433 goto fail_req;
8434 }
8435
8436 qpair->req = ha->req_q_map[req_id];
8437 qpair->rsp->req = qpair->req;
82de802a 8438 qpair->rsp->qpair = qpair;
e326d22a
QT		 8439 /* init qpair to this cpu. Will adjust at run time. */
8440 qla_cpu_update(qpair, smp_processor_id());
d7459527
MH		 8441
8442 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
8443 if (ha->fw_attributes & BIT_4)
8444 qpair->difdix_supported = 1;
8445 }
8446
8447 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
8448 if (!qpair->srb_mempool) {
83548fe2 8449 ql_log(ql_log_warn, vha, 0xd036,
d7459527
MH		 8450 "Failed to create srb mempool for qpair %d\n",
8451 qpair->id);
8452 goto fail_mempool;
8453 }
8454
8455 /* Mark as online */
8456 qpair->online = 1;
8457
8458 if (!vha->flags.qpairs_available)
8459 vha->flags.qpairs_available = 1;
8460
8461 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
8462 "Request/Response queue pair created, id %d\n",
8463 qpair->id);
8464 ql_dbg(ql_dbg_init, vha, 0x0187,
8465 "Request/Response queue pair created, id %d\n",
8466 qpair->id);
8467 }
8468 return qpair;
8469
8470fail_mempool:
8471fail_req:
8472 qla25xx_delete_rsp_que(vha, qpair->rsp);
8473fail_rsp:
8474 mutex_lock(&ha->mq_lock);
8475 qpair->msix->in_use = 0;
8476 list_del(&qpair->qp_list_elem);
8477 if (list_empty(&vha->qp_list))
8478 vha->flags.qpairs_available = 0;
8479fail_msix:
8480 ha->queue_pair_map[qpair_id] = NULL;
8481 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 8482 ha->num_qpairs--;
d7459527
MH		 8483 mutex_unlock(&ha->mq_lock);
8484fail_qid_map:
8485 kfree(qpair);
8486 return NULL;
8487}
8488
8489int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
8490{
d65237c7 8491 int ret = QLA_FUNCTION_FAILED;
d7459527
MH		 8492 struct qla_hw_data *ha = qpair->hw;
8493
8494 qpair->delete_in_progress = 1;
8495 while (atomic_read(&qpair->ref_count))
8496 msleep(500);
8497
8498 ret = qla25xx_delete_req_que(vha, qpair->req);
8499 if (ret != QLA_SUCCESS)
8500 goto fail;
7867b98d 8501
d7459527
MH		 8502 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
8503 if (ret != QLA_SUCCESS)
8504 goto fail;
8505
8506 mutex_lock(&ha->mq_lock);
8507 ha->queue_pair_map[qpair->id] = NULL;
8508 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 8509 ha->num_qpairs--;
d7459527 8510 list_del(&qpair->qp_list_elem);
d65237c7 8511 if (list_empty(&vha->qp_list)) {
d7459527 8512 vha->flags.qpairs_available = 0;
d65237c7
SC		 8513 vha->flags.qpairs_req_created = 0;
8514 vha->flags.qpairs_rsp_created = 0;
8515 }
d7459527
MH		 8516 mempool_destroy(qpair->srb_mempool);
8517 kfree(qpair);
8518 mutex_unlock(&ha->mq_lock);
8519
8520 return QLA_SUCCESS;
8521fail:
8522 return ret;
8523}
Linux 6.x block layer and io_uring tree(s)