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scsi: qla2xxx: Move {get|rel}_sp to base_qpair struct
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
a5d42f4c 39static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
726b8548
QT		 40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
a5d42f4c
DG		 42static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
43 struct event_arg *);
a4239945 44static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
4d4df193 45
ac280b67
AV		 46/* SRB Extensions ---------------------------------------------------------- */
47
9ba56b95 48void
8e5f4ba0 49qla2x00_sp_timeout(struct timer_list *t)
ac280b67 50{
8e5f4ba0 51 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
4916392b 52 struct srb_iocb *iocb;
ac280b67
AV		 53 struct req_que *req;
54 unsigned long flags;
55
f6145e86
QT		 56 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
57 req = sp->qpair->req;
ac280b67 58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
f6145e86 60 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
4916392b 61 iocb->timeout(sp);
ac280b67
AV		 62}
63
9ba56b95 64void
25ff6af1 65qla2x00_sp_free(void *ptr)
ac280b67 66{
25ff6af1 67 srb_t *sp = ptr;
9ba56b95 68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 69
4d97cc53 70 del_timer(&iocb->timer);
25ff6af1 71 qla2x00_rel_sp(sp);
ac280b67
AV		 72}
73
ac280b67
AV		 74/* Asynchronous Login/Logout Routines -------------------------------------- */
75
a9b6f722 76unsigned long
5b91490e
AV		 77qla2x00_get_async_timeout(struct scsi_qla_host *vha)
78{
79 unsigned long tmo;
80 struct qla_hw_data *ha = vha->hw;
81
82 /* Firmware should use switch negotiated r_a_tov for timeout. */
83 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 84 if (IS_QLAFX00(ha)) {
85 tmo = FX00_DEF_RATOV * 2;
86 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 87 /*
88 * Except for earlier ISPs where the timeout is seeded from the
89 * initialization control block.
90 */
91 tmo = ha->login_timeout;
92 }
93 return tmo;
94}
ac280b67 95
726b8548 96void
9ba56b95 97qla2x00_async_iocb_timeout(void *data)
ac280b67 98{
25ff6af1 99 srb_t *sp = data;
ac280b67 100 fc_port_t *fcport = sp->fcport;
726b8548 101 struct srb_iocb *lio = &sp->u.iocb_cmd;
f6145e86
QT		 102 int rc, h;
103 unsigned long flags;
ac280b67 104
5c25d451
QT		 105 if (fcport) {
106 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
107 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
108 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
109
6d674927 110 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
5c25d451
QT		 111 } else {
112 pr_info("Async-%s timeout - hdl=%x.\n",
113 sp->name, sp->handle);
114 }
726b8548
QT		 115
116 switch (sp->type) {
117 case SRB_LOGIN_CMD:
f6145e86
QT		 118 rc = qla24xx_async_abort_cmd(sp, false);
119 if (rc) {
120 /* Retry as needed. */
121 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
122 lio->u.logio.data[1] =
123 lio->u.logio.flags & SRB_LOGIN_RETRIED ?
124 QLA_LOGIO_LOGIN_RETRIED : 0;
125 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
126 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
127 h++) {
128 if (sp->qpair->req->outstanding_cmds[h] ==
129 sp) {
130 sp->qpair->req->outstanding_cmds[h] =
131 NULL;
132 break;
133 }
134 }
135 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
136 sp->done(sp, QLA_FUNCTION_TIMEOUT);
137 }
726b8548
QT		 138 break;
139 case SRB_LOGOUT_CMD:
726b8548
QT		 140 case SRB_CT_PTHRU_CMD:
141 case SRB_MB_IOCB:
142 case SRB_NACK_PLOGI:
143 case SRB_NACK_PRLI:
144 case SRB_NACK_LOGO:
2853192e 145 case SRB_CTRL_VP:
f6145e86
QT		 146 rc = qla24xx_async_abort_cmd(sp, false);
147 if (rc) {
148 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
149 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
150 h++) {
151 if (sp->qpair->req->outstanding_cmds[h] ==
152 sp) {
153 sp->qpair->req->outstanding_cmds[h] =
154 NULL;
155 break;
156 }
157 }
158 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
159 sp->done(sp, QLA_FUNCTION_TIMEOUT);
160 }
726b8548 161 break;
6ac52608 162 }
ac280b67
AV		 163}
164
99b0bec7 165static void
25ff6af1 166qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 167{
25ff6af1
JC		 168 srb_t *sp = ptr;
169 struct scsi_qla_host *vha = sp->vha;
9ba56b95 170 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 171 struct event_arg ea;
9ba56b95 172
83548fe2 173 ql_dbg(ql_dbg_disc, vha, 0x20dd,
25ff6af1 174 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548 175
6d674927
QT		 176 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
177
726b8548
QT		 178 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
179 memset(&ea, 0, sizeof(ea));
180 ea.event = FCME_PLOGI_DONE;
181 ea.fcport = sp->fcport;
182 ea.data[0] = lio->u.logio.data[0];
183 ea.data[1] = lio->u.logio.data[1];
184 ea.iop[0] = lio->u.logio.iop[0];
185 ea.iop[1] = lio->u.logio.iop[1];
186 ea.sp = sp;
187 qla2x00_fcport_event_handler(vha, &ea);
188 }
9ba56b95 189
25ff6af1 190 sp->free(sp);
99b0bec7
AV		 191}
192
48acad09
QT		 193static inline bool
194fcport_is_smaller(fc_port_t *fcport)
195{
196 if (wwn_to_u64(fcport->port_name) <
197 wwn_to_u64(fcport->vha->port_name))
198 return true;
199 else
200 return false;
201}
202
203static inline bool
204fcport_is_bigger(fc_port_t *fcport)
205{
206 return !fcport_is_smaller(fcport);
207}
208
ac280b67
AV		 209int
210qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
211 uint16_t *data)
212{
ac280b67 213 srb_t *sp;
4916392b 214 struct srb_iocb *lio;
726b8548
QT		 215 int rval = QLA_FUNCTION_FAILED;
216
217 if (!vha->flags.online)
218 goto done;
219
9ba56b95 220 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 221 if (!sp)
222 goto done;
223
726b8548
QT		 224 fcport->flags |= FCF_ASYNC_SENT;
225 fcport->logout_completed = 0;
226
a4239945 227 fcport->disc_state = DSC_LOGIN_PEND;
9ba56b95
GM		 228 sp->type = SRB_LOGIN_CMD;
229 sp->name = "login";
a4239945
QT		 230 sp->gen1 = fcport->rscn_gen;
231 sp->gen2 = fcport->login_gen;
9ba56b95
GM		 232
233 lio = &sp->u.iocb_cmd;
3822263e 234 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 235 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
236
9ba56b95 237 sp->done = qla2x00_async_login_sp_done;
48acad09
QT		 238 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport)) {
239 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY;
240 } else {
241 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
a5d42f4c 242
48acad09
QT		 243 if (fcport->fc4f_nvme)
244 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
245
48acad09 246 }
a5d42f4c 247
ac280b67 248 rval = qla2x00_start_sp(sp);
080c9517 249 if (rval != QLA_SUCCESS) {
080c9517
CD		 250 fcport->flags |= FCF_LOGIN_NEEDED;
251 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 252 goto done_free_sp;
080c9517 253 }
ac280b67 254
7c3df132 255 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 256 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
257 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 258 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
259 fcport->login_retry);
ac280b67
AV		 260 return rval;
261
262done_free_sp:
25ff6af1 263 sp->free(sp);
726b8548 264 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 265done:
fa83e658 266 fcport->flags &= ~FCF_ASYNC_ACTIVE;
ac280b67
AV		 267 return rval;
268}
269
99b0bec7 270static void
25ff6af1 271qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 272{
25ff6af1 273 srb_t *sp = ptr;
9ba56b95 274
6d674927 275 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
eaf75d18
QT		 276 sp->fcport->login_gen++;
277 qlt_logo_completion_handler(sp->fcport, res);
25ff6af1 278 sp->free(sp);
99b0bec7
AV		 279}
280
ac280b67
AV		 281int
282qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
283{
ac280b67 284 srb_t *sp;
4916392b 285 struct srb_iocb *lio;
3dbec59b
QT		 286 int rval = QLA_FUNCTION_FAILED;
287
288 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
289 return rval;
ac280b67 290
726b8548 291 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 292 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 293 if (!sp)
294 goto done;
295
9ba56b95
GM		 296 sp->type = SRB_LOGOUT_CMD;
297 sp->name = "logout";
9ba56b95
GM		 298
299 lio = &sp->u.iocb_cmd;
3822263e 300 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 301 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
302
9ba56b95 303 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 304 rval = qla2x00_start_sp(sp);
305 if (rval != QLA_SUCCESS)
306 goto done_free_sp;
307
7c3df132 308 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 309 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 310 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 311 fcport->d_id.b.area, fcport->d_id.b.al_pa,
312 fcport->port_name);
ac280b67
AV		 313 return rval;
314
315done_free_sp:
25ff6af1 316 sp->free(sp);
ac280b67 317done:
fa83e658 318 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
ac280b67
AV		 319 return rval;
320}
11aea16a
QT		 321
322void
323qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
324 uint16_t *data)
325{
fa83e658 326 fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 327 /* Don't re-login in target mode */
328 if (!fcport->tgt_session)
329 qla2x00_mark_device_lost(vha, fcport, 1, 0);
330 qlt_logo_completion_handler(fcport, data[0]);
331}
332
333static void
334qla2x00_async_prlo_sp_done(void *s, int res)
335{
336 srb_t *sp = (srb_t *)s;
337 struct srb_iocb *lio = &sp->u.iocb_cmd;
338 struct scsi_qla_host *vha = sp->vha;
339
fa83e658 340 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 341 if (!test_bit(UNLOADING, &vha->dpc_flags))
342 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
343 lio->u.logio.data);
344 sp->free(sp);
345}
346
347int
348qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
349{
350 srb_t *sp;
351 struct srb_iocb *lio;
352 int rval;
353
354 rval = QLA_FUNCTION_FAILED;
355 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
356 if (!sp)
357 goto done;
358
359 sp->type = SRB_PRLO_CMD;
360 sp->name = "prlo";
11aea16a
QT		 361
362 lio = &sp->u.iocb_cmd;
363 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 364 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
365
11aea16a
QT		 366 sp->done = qla2x00_async_prlo_sp_done;
367 rval = qla2x00_start_sp(sp);
368 if (rval != QLA_SUCCESS)
369 goto done_free_sp;
370
371 ql_dbg(ql_dbg_disc, vha, 0x2070,
372 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
373 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
374 fcport->d_id.b.area, fcport->d_id.b.al_pa);
375 return rval;
376
377done_free_sp:
378 sp->free(sp);
379done:
fa83e658 380 fcport->flags &= ~FCF_ASYNC_ACTIVE;
11aea16a
QT		 381 return rval;
382}
383
f13515ac
QT		 384static
385void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
386{
0616e965
QT		 387 struct fc_port *fcport = ea->fcport;
388
389 ql_dbg(ql_dbg_disc, vha, 0x20d2,
390 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
391 __func__, fcport->port_name, fcport->disc_state,
392 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
393 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
394
395 if (ea->data[0] != MBS_COMMAND_COMPLETE) {
a4239945
QT		 396 ql_dbg(ql_dbg_disc, vha, 0x2066,
397 "%s %8phC: adisc fail: post delete\n",
398 __func__, ea->fcport->port_name);
2d3fdbeb
QT		 399 /* deleted = 0 & logout_on_delete = force fw cleanup */
400 fcport->deleted = 0;
401 fcport->logout_on_delete = 1;
94cff6e1 402 qlt_schedule_sess_for_deletion(ea->fcport);
a4239945
QT		 403 return;
404 }
a4239945
QT		 405
406 if (ea->fcport->disc_state == DSC_DELETE_PEND)
407 return;
408
409 if (ea->sp->gen2 != ea->fcport->login_gen) {
410 /* target side must have changed it. */
411 ql_dbg(ql_dbg_disc, vha, 0x20d3,
0616e965
QT		 412 "%s %8phC generation changed\n",
413 __func__, ea->fcport->port_name);
a4239945
QT		 414 return;
415 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
416 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
417 __func__, __LINE__, ea->fcport->port_name);
418 qla24xx_post_gidpn_work(vha, ea->fcport);
419 return;
420 }
421
422 __qla24xx_handle_gpdb_event(vha, ea);
f13515ac 423}
ac280b67 424
8777e431
QT		 425int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport)
426{
427 struct qla_work_evt *e;
428
429 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI);
430 if (!e)
431 return QLA_FUNCTION_FAILED;
432
433 e->u.fcport.fcport = fcport;
434 fcport->flags |= FCF_ASYNC_ACTIVE;
435 return qla2x00_post_work(vha, e);
436}
437
5ff1d584 438static void
25ff6af1 439qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 440{
25ff6af1
JC		 441 srb_t *sp = ptr;
442 struct scsi_qla_host *vha = sp->vha;
f13515ac 443 struct event_arg ea;
0616e965 444 struct srb_iocb *lio = &sp->u.iocb_cmd;
f13515ac
QT		 445
446 ql_dbg(ql_dbg_disc, vha, 0x2066,
447 "Async done-%s res %x %8phC\n",
448 sp->name, res, sp->fcport->port_name);
449
15b6c3c9 450 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
fa83e658 451
f13515ac
QT		 452 memset(&ea, 0, sizeof(ea));
453 ea.event = FCME_ADISC_DONE;
454 ea.rc = res;
0616e965
QT		 455 ea.data[0] = lio->u.logio.data[0];
456 ea.data[1] = lio->u.logio.data[1];
457 ea.iop[0] = lio->u.logio.iop[0];
458 ea.iop[1] = lio->u.logio.iop[1];
f13515ac
QT		 459 ea.fcport = sp->fcport;
460 ea.sp = sp;
461
462 qla2x00_fcport_event_handler(vha, &ea);
9ba56b95 463
25ff6af1 464 sp->free(sp);
5ff1d584
AV		 465}
466
467int
468qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
469 uint16_t *data)
470{
5ff1d584 471 srb_t *sp;
4916392b 472 struct srb_iocb *lio;
5ff1d584
AV		 473 int rval;
474
475 rval = QLA_FUNCTION_FAILED;
726b8548 476 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 477 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 478 if (!sp)
479 goto done;
480
9ba56b95
GM		 481 sp->type = SRB_ADISC_CMD;
482 sp->name = "adisc";
9ba56b95
GM		 483
484 lio = &sp->u.iocb_cmd;
3822263e 485 lio->timeout = qla2x00_async_iocb_timeout;
8777e431
QT		 486 sp->gen1 = fcport->rscn_gen;
487 sp->gen2 = fcport->login_gen;
e74e7d95
BH		 488 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
489
9ba56b95 490 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 491 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 492 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 493 rval = qla2x00_start_sp(sp);
494 if (rval != QLA_SUCCESS)
495 goto done_free_sp;
496
7c3df132 497 ql_dbg(ql_dbg_disc, vha, 0x206f,
f13515ac
QT		 498 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
499 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
5ff1d584
AV		 500 return rval;
501
502done_free_sp:
25ff6af1 503 sp->free(sp);
5ff1d584 504done:
fa83e658 505 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
f13515ac 506 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 507 return rval;
508}
509
510static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
511 struct event_arg *ea)
512{
513 fc_port_t *fcport, *conflict_fcport;
514 struct get_name_list_extended *e;
515 u16 i, n, found = 0, loop_id;
516 port_id_t id;
517 u64 wwn;
a4239945
QT		 518 u16 data[2];
519 u8 current_login_state;
726b8548
QT		 520
521 fcport = ea->fcport;
f352eeb7
QT		 522 ql_dbg(ql_dbg_disc, vha, 0xffff,
523 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n",
524 __func__, fcport->port_name, fcport->disc_state,
525 fcport->fw_login_state, ea->rc,
526 fcport->login_gen, fcport->last_login_gen,
527 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id);
726b8548 528
a4239945
QT		 529 if (fcport->disc_state == DSC_DELETE_PEND)
530 return;
531
726b8548
QT		 532 if (ea->rc) { /* rval */
533 if (fcport->login_retry == 0) {
83548fe2
QT		 534 ql_dbg(ql_dbg_disc, vha, 0x20de,
535 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
536 fcport->port_name, fcport->login_retry);
726b8548
QT		 537 }
538 return;
539 }
540
541 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 542 ql_dbg(ql_dbg_disc, vha, 0x20df,
726b8548
QT		 543 "%s %8phC rscn gen changed rscn %d|%d \n",
544 __func__, fcport->port_name,
545 fcport->last_rscn_gen, fcport->rscn_gen);
546 qla24xx_post_gidpn_work(vha, fcport);
547 return;
548 } else if (fcport->last_login_gen != fcport->login_gen) {
83548fe2 549 ql_dbg(ql_dbg_disc, vha, 0x20e0,
f352eeb7
QT		 550 "%s %8phC login gen changed\n",
551 __func__, fcport->port_name);
726b8548
QT		 552 return;
553 }
554
555 n = ea->data[0] / sizeof(struct get_name_list_extended);
556
83548fe2 557 ql_dbg(ql_dbg_disc, vha, 0x20e1,
726b8548
QT		 558 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
559 __func__, __LINE__, fcport->port_name, n,
560 fcport->d_id.b.domain, fcport->d_id.b.area,
561 fcport->d_id.b.al_pa, fcport->loop_id);
562
563 for (i = 0; i < n; i++) {
564 e = &vha->gnl.l[i];
565 wwn = wwn_to_u64(e->port_name);
48acad09
QT		 566 id.b.domain = e->port_id[2];
567 id.b.area = e->port_id[1];
568 id.b.al_pa = e->port_id[0];
569 id.b.rsvd_1 = 0;
726b8548
QT		 570
571 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
572 continue;
573
48acad09
QT		 574 if (IS_SW_RESV_ADDR(id))
575 continue;
576
726b8548 577 found = 1;
726b8548
QT		 578
579 loop_id = le16_to_cpu(e->nport_handle);
580 loop_id = (loop_id & 0x7fff);
8777e431
QT		 581 if (fcport->fc4f_nvme)
582 current_login_state = e->current_login_state >> 4;
583 else
584 current_login_state = e->current_login_state & 0xf;
585
726b8548 586
83548fe2 587 ql_dbg(ql_dbg_disc, vha, 0x20e2,
8777e431 588 "%s found %8phC CLS [%x|%x] nvme %d ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
83548fe2
QT		 589 __func__, fcport->port_name,
590 e->current_login_state, fcport->fw_login_state,
8777e431 591 fcport->fc4f_nvme, id.b.domain, id.b.area, id.b.al_pa,
83548fe2
QT		 592 fcport->d_id.b.domain, fcport->d_id.b.area,
593 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
726b8548 594
48acad09
QT		 595 switch (fcport->disc_state) {
596 case DSC_DELETE_PEND:
597 case DSC_DELETED:
598 break;
599 default:
8777e431
QT		 600 if ((id.b24 != fcport->d_id.b24 &&
601 fcport->d_id.b24) ||
602 (fcport->loop_id != FC_NO_LOOP_ID &&
603 fcport->loop_id != loop_id)) {
604 ql_dbg(ql_dbg_disc, vha, 0x20e3,
605 "%s %d %8phC post del sess\n",
606 __func__, __LINE__, fcport->port_name);
48acad09
QT		 607 qlt_schedule_sess_for_deletion(fcport);
608 return;
609 }
610 break;
726b8548
QT		 611 }
612
613 fcport->loop_id = loop_id;
614
615 wwn = wwn_to_u64(fcport->port_name);
616 qlt_find_sess_invalidate_other(vha, wwn,
617 id, loop_id, &conflict_fcport);
618
619 if (conflict_fcport) {
620 /*
621 * Another share fcport share the same loop_id &
622 * nport id. Conflict fcport needs to finish
623 * cleanup before this fcport can proceed to login.
624 */
625 conflict_fcport->conflict = fcport;
626 fcport->login_pause = 1;
627 }
628
48acad09
QT		 629 switch (vha->hw->current_topology) {
630 default:
631 switch (current_login_state) {
632 case DSC_LS_PRLI_COMP:
633 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
634 vha, 0x20e4, "%s %d %8phC post gpdb\n",
635 __func__, __LINE__, fcport->port_name);
a4239945 636
48acad09
QT		 637 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
638 fcport->port_type = FCT_INITIATOR;
639 else
640 fcport->port_type = FCT_TARGET;
641 data[0] = data[1] = 0;
642 qla2x00_post_async_adisc_work(vha, fcport,
643 data);
644 break;
645 case DSC_LS_PORT_UNAVAIL:
646 default:
647 if (fcport->loop_id != FC_NO_LOOP_ID)
648 qla2x00_clear_loop_id(fcport);
a4239945 649
48acad09 650 fcport->loop_id = loop_id;
726b8548 651 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
48acad09
QT		 652 qla24xx_fcport_handle_login(vha, fcport);
653 break;
726b8548 654 }
726b8548 655 break;
48acad09 656 case ISP_CFG_N:
8777e431
QT		 657 fcport->fw_login_state = current_login_state;
658 fcport->d_id = id;
48acad09
QT		 659 switch (current_login_state) {
660 case DSC_LS_PRLI_COMP:
661 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
662 fcport->port_type = FCT_INITIATOR;
663 else
664 fcport->port_type = FCT_TARGET;
665
666 data[0] = data[1] = 0;
667 qla2x00_post_async_adisc_work(vha, fcport,
668 data);
669 break;
670 case DSC_LS_PLOGI_COMP:
671 if (fcport_is_bigger(fcport)) {
672 /* local adapter is smaller */
673 if (fcport->loop_id != FC_NO_LOOP_ID)
674 qla2x00_clear_loop_id(fcport);
675
676 fcport->loop_id = loop_id;
677 qla24xx_fcport_handle_login(vha,
678 fcport);
679 break;
680 }
681 /* drop through */
682 default:
683 if (fcport_is_smaller(fcport)) {
684 /* local adapter is bigger */
685 if (fcport->loop_id != FC_NO_LOOP_ID)
686 qla2x00_clear_loop_id(fcport);
687
688 fcport->loop_id = loop_id;
689 qla24xx_fcport_handle_login(vha,
690 fcport);
691 }
692 break;
693 }
694 break;
695 } /* switch (ha->current_topology) */
726b8548
QT		 696 }
697
698 if (!found) {
48acad09
QT		 699 switch (vha->hw->current_topology) {
700 case ISP_CFG_F:
701 case ISP_CFG_FL:
702 for (i = 0; i < n; i++) {
703 e = &vha->gnl.l[i];
704 id.b.domain = e->port_id[0];
705 id.b.area = e->port_id[1];
706 id.b.al_pa = e->port_id[2];
707 id.b.rsvd_1 = 0;
708 loop_id = le16_to_cpu(e->nport_handle);
709
710 if (fcport->d_id.b24 == id.b24) {
711 conflict_fcport =
712 qla2x00_find_fcport_by_wwpn(vha,
713 e->port_name, 0);
72f02ba6
LT		 714 if (conflict_fcport) {
715 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
716 vha, 0x20e5,
717 "%s %d %8phC post del sess\n",
718 __func__, __LINE__,
719 conflict_fcport->port_name);
720 qlt_schedule_sess_for_deletion
721 (conflict_fcport);
722 }
36eb8ff6 723 }
48acad09
QT		 724 /*
725 * FW already picked this loop id for
726 * another fcport
727 */
728 if (fcport->loop_id == loop_id)
729 fcport->loop_id = FC_NO_LOOP_ID;
726b8548 730 }
48acad09
QT		 731 qla24xx_fcport_handle_login(vha, fcport);
732 break;
733 case ISP_CFG_N:
8777e431
QT		 734 fcport->disc_state = DSC_DELETED;
735 if (time_after_eq(jiffies, fcport->dm_login_expire)) {
736 if (fcport->n2n_link_reset_cnt < 2) {
737 fcport->n2n_link_reset_cnt++;
738 /*
739 * remote port is not sending PLOGI.
740 * Reset link to kick start his state
741 * machine
742 */
743 set_bit(N2N_LINK_RESET,
744 &vha->dpc_flags);
745 } else {
746 if (fcport->n2n_chip_reset < 1) {
747 ql_log(ql_log_info, vha, 0x705d,
748 "Chip reset to bring laser down");
749 set_bit(ISP_ABORT_NEEDED,
750 &vha->dpc_flags);
751 fcport->n2n_chip_reset++;
752 } else {
753 ql_log(ql_log_info, vha, 0x705d,
754 "Remote port %8ph is not coming back\n",
755 fcport->port_name);
756 fcport->scan_state = 0;
757 }
758 }
759 qla2xxx_wake_dpc(vha);
760 } else {
761 /*
762 * report port suppose to do PLOGI. Give him
763 * more time. FW will catch it.
764 */
765 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
766 }
48acad09
QT		 767 break;
768 default:
769 break;
726b8548 770 }
726b8548
QT		 771 }
772} /* gnl_event */
773
774static void
25ff6af1 775qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 776{
25ff6af1
JC		 777 struct srb *sp = s;
778 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 779 unsigned long flags;
780 struct fc_port *fcport = NULL, *tf;
781 u16 i, n = 0, loop_id;
782 struct event_arg ea;
783 struct get_name_list_extended *e;
784 u64 wwn;
785 struct list_head h;
a4239945 786 bool found = false;
726b8548 787
83548fe2 788 ql_dbg(ql_dbg_disc, vha, 0x20e7,
726b8548
QT		 789 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
790 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
791 sp->u.iocb_cmd.u.mbx.in_mb[2]);
792
793 memset(&ea, 0, sizeof(ea));
794 ea.sp = sp;
795 ea.rc = res;
796 ea.event = FCME_GNL_DONE;
797
798 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
799 sizeof(struct get_name_list_extended)) {
800 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
801 sizeof(struct get_name_list_extended);
802 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
803 }
804
805 for (i = 0; i < n; i++) {
806 e = &vha->gnl.l[i];
807 loop_id = le16_to_cpu(e->nport_handle);
808 /* mask out reserve bit */
809 loop_id = (loop_id & 0x7fff);
810 set_bit(loop_id, vha->hw->loop_id_map);
811 wwn = wwn_to_u64(e->port_name);
812
83548fe2 813 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
726b8548
QT		 814 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
815 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
816 e->port_id[0], e->current_login_state, e->last_login_state,
817 (loop_id & 0x7fff));
818 }
819
1c6cacf4 820 spin_lock_irqsave(&vha->gnl.fcports_lock, flags);
726b8548
QT		 821
822 INIT_LIST_HEAD(&h);
823 fcport = tf = NULL;
824 if (!list_empty(&vha->gnl.fcports))
825 list_splice_init(&vha->gnl.fcports, &h);
826
827 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
828 list_del_init(&fcport->gnl_entry);
1c6cacf4 829 spin_lock(&vha->hw->tgt.sess_lock);
6d674927 830 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1c6cacf4 831 spin_unlock(&vha->hw->tgt.sess_lock);
726b8548
QT		 832 ea.fcport = fcport;
833
834 qla2x00_fcport_event_handler(vha, &ea);
835 }
1c6cacf4 836 spin_unlock_irqrestore(&vha->gnl.fcports_lock, flags);
726b8548 837
1c6cacf4 838 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945
QT		 839 /* create new fcport if fw has knowledge of new sessions */
840 for (i = 0; i < n; i++) {
841 port_id_t id;
842 u64 wwnn;
843
844 e = &vha->gnl.l[i];
845 wwn = wwn_to_u64(e->port_name);
846
847 found = false;
848 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
849 if (!memcmp((u8 *)&wwn, fcport->port_name,
850 WWN_SIZE)) {
851 found = true;
852 break;
853 }
854 }
855
cf055fb0 856 id.b.domain = e->port_id[2];
a4239945 857 id.b.area = e->port_id[1];
cf055fb0 858 id.b.al_pa = e->port_id[0];
a4239945
QT		 859 id.b.rsvd_1 = 0;
860
861 if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
862 ql_dbg(ql_dbg_disc, vha, 0x2065,
cf055fb0
QT		 863 "%s %d %8phC %06x post new sess\n",
864 __func__, __LINE__, (u8 *)&wwn, id.b24);
a4239945
QT		 865 wwnn = wwn_to_u64(e->node_name);
866 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
867 (u8 *)&wwnn, NULL, FC4_TYPE_UNKNOWN);
868 }
869 }
870
726b8548
QT		 871 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
872
25ff6af1 873 sp->free(sp);
726b8548
QT		 874}
875
876int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
877{
878 srb_t *sp;
879 struct srb_iocb *mbx;
880 int rval = QLA_FUNCTION_FAILED;
881 unsigned long flags;
882 u16 *mb;
883
3dbec59b
QT		 884 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
885 return rval;
726b8548 886
83548fe2 887 ql_dbg(ql_dbg_disc, vha, 0x20d9,
726b8548
QT		 888 "Async-gnlist WWPN %8phC \n", fcport->port_name);
889
1c6cacf4
HR		 890 spin_lock_irqsave(&vha->gnl.fcports_lock, flags);
891 if (!list_empty(&fcport->gnl_entry)) {
892 spin_unlock_irqrestore(&vha->gnl.fcports_lock, flags);
893 rval = QLA_SUCCESS;
894 goto done;
895 }
896
897 spin_lock(&vha->hw->tgt.sess_lock);
726b8548
QT		 898 fcport->disc_state = DSC_GNL;
899 fcport->last_rscn_gen = fcport->rscn_gen;
900 fcport->last_login_gen = fcport->login_gen;
1c6cacf4 901 spin_unlock(&vha->hw->tgt.sess_lock);
726b8548
QT		 902
903 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
1c6cacf4 904 spin_unlock_irqrestore(&vha->gnl.fcports_lock, flags);
726b8548
QT		 905
906 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
907 if (!sp)
908 goto done;
3dbec59b
QT		 909
910 fcport->flags |= FCF_ASYNC_SENT;
726b8548
QT		 911 sp->type = SRB_MB_IOCB;
912 sp->name = "gnlist";
913 sp->gen1 = fcport->rscn_gen;
914 sp->gen2 = fcport->login_gen;
915
e74e7d95
BH		 916 mbx = &sp->u.iocb_cmd;
917 mbx->timeout = qla2x00_async_iocb_timeout;
726b8548
QT		 918 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
919
920 mb = sp->u.iocb_cmd.u.mbx.out_mb;
921 mb[0] = MBC_PORT_NODE_NAME_LIST;
922 mb[1] = BIT_2 | BIT_3;
923 mb[2] = MSW(vha->gnl.ldma);
924 mb[3] = LSW(vha->gnl.ldma);
925 mb[6] = MSW(MSD(vha->gnl.ldma));
926 mb[7] = LSW(MSD(vha->gnl.ldma));
927 mb[8] = vha->gnl.size;
928 mb[9] = vha->vp_idx;
929
726b8548
QT		 930 sp->done = qla24xx_async_gnl_sp_done;
931
932 rval = qla2x00_start_sp(sp);
933 if (rval != QLA_SUCCESS)
934 goto done_free_sp;
935
83548fe2
QT		 936 ql_dbg(ql_dbg_disc, vha, 0x20da,
937 "Async-%s - OUT WWPN %8phC hndl %x\n",
938 sp->name, fcport->port_name, sp->handle);
726b8548
QT		 939
940 return rval;
941
942done_free_sp:
25ff6af1 943 sp->free(sp);
726b8548 944 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 945done:
726b8548
QT		 946 return rval;
947}
948
949int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
950{
951 struct qla_work_evt *e;
952
953 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
954 if (!e)
955 return QLA_FUNCTION_FAILED;
956
957 e->u.fcport.fcport = fcport;
6d674927 958 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 959 return qla2x00_post_work(vha, e);
960}
961
962static
25ff6af1 963void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 964{
25ff6af1
JC		 965 struct srb *sp = s;
966 struct scsi_qla_host *vha = sp->vha;
726b8548 967 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 968 fc_port_t *fcport = sp->fcport;
969 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
726b8548
QT		 970 struct event_arg ea;
971
83548fe2 972 ql_dbg(ql_dbg_disc, vha, 0x20db,
726b8548
QT		 973 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
974 sp->name, res, fcport->port_name, mb[1], mb[2]);
975
6d674927 976 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
726b8548 977
726b8548
QT		 978 memset(&ea, 0, sizeof(ea));
979 ea.event = FCME_GPDB_DONE;
726b8548
QT		 980 ea.fcport = fcport;
981 ea.sp = sp;
982
983 qla2x00_fcport_event_handler(vha, &ea);
984
985 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
986 sp->u.iocb_cmd.u.mbx.in_dma);
987
25ff6af1 988 sp->free(sp);
726b8548
QT		 989}
990
a5d42f4c
DG		 991static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
992{
993 struct qla_work_evt *e;
994
995 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
996 if (!e)
997 return QLA_FUNCTION_FAILED;
998
999 e->u.fcport.fcport = fcport;
1000
1001 return qla2x00_post_work(vha, e);
1002}
1003
1004static void
1005qla2x00_async_prli_sp_done(void *ptr, int res)
1006{
1007 srb_t *sp = ptr;
1008 struct scsi_qla_host *vha = sp->vha;
1009 struct srb_iocb *lio = &sp->u.iocb_cmd;
1010 struct event_arg ea;
1011
1012 ql_dbg(ql_dbg_disc, vha, 0x2129,
1013 "%s %8phC res %d \n", __func__,
1014 sp->fcport->port_name, res);
1015
1016 sp->fcport->flags &= ~FCF_ASYNC_SENT;
1017
1018 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
1019 memset(&ea, 0, sizeof(ea));
1020 ea.event = FCME_PRLI_DONE;
1021 ea.fcport = sp->fcport;
1022 ea.data[0] = lio->u.logio.data[0];
1023 ea.data[1] = lio->u.logio.data[1];
1024 ea.iop[0] = lio->u.logio.iop[0];
1025 ea.iop[1] = lio->u.logio.iop[1];
1026 ea.sp = sp;
1027
1028 qla2x00_fcport_event_handler(vha, &ea);
1029 }
1030
1031 sp->free(sp);
1032}
1033
1034int
1035qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
1036{
1037 srb_t *sp;
1038 struct srb_iocb *lio;
1039 int rval = QLA_FUNCTION_FAILED;
1040
1041 if (!vha->flags.online)
1042 return rval;
1043
1044 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
a5d42f4c
DG		 1045 fcport->fw_login_state == DSC_LS_PRLI_PEND)
1046 return rval;
1047
1048 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1049 if (!sp)
1050 return rval;
1051
1052 fcport->flags |= FCF_ASYNC_SENT;
1053 fcport->logout_completed = 0;
1054
1055 sp->type = SRB_PRLI_CMD;
1056 sp->name = "prli";
a5d42f4c
DG		 1057
1058 lio = &sp->u.iocb_cmd;
1059 lio->timeout = qla2x00_async_iocb_timeout;
e74e7d95
BH		 1060 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1061
a5d42f4c
DG		 1062 sp->done = qla2x00_async_prli_sp_done;
1063 lio->u.logio.flags = 0;
1064
1065 if (fcport->fc4f_nvme)
1066 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
1067
1068 rval = qla2x00_start_sp(sp);
1069 if (rval != QLA_SUCCESS) {
a5d42f4c
DG		 1070 fcport->flags |= FCF_LOGIN_NEEDED;
1071 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1072 goto done_free_sp;
1073 }
1074
1075 ql_dbg(ql_dbg_disc, vha, 0x211b,
8777e431
QT		 1076 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d %s.\n",
1077 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24,
1078 fcport->login_retry, fcport->fc4f_nvme ? "nvme" : "fc");
a5d42f4c
DG		 1079
1080 return rval;
1081
1082done_free_sp:
1083 sp->free(sp);
1084 fcport->flags &= ~FCF_ASYNC_SENT;
1085 return rval;
1086}
1087
a07fc0a4 1088int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
726b8548
QT		 1089{
1090 struct qla_work_evt *e;
1091
1092 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
1093 if (!e)
1094 return QLA_FUNCTION_FAILED;
1095
1096 e->u.fcport.fcport = fcport;
1097 e->u.fcport.opt = opt;
6d674927 1098 fcport->flags |= FCF_ASYNC_ACTIVE;
726b8548
QT		 1099 return qla2x00_post_work(vha, e);
1100}
1101
1102int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
1103{
1104 srb_t *sp;
1105 struct srb_iocb *mbx;
1106 int rval = QLA_FUNCTION_FAILED;
1107 u16 *mb;
1108 dma_addr_t pd_dma;
1109 struct port_database_24xx *pd;
1110 struct qla_hw_data *ha = vha->hw;
1111
3dbec59b
QT		 1112 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
1113 return rval;
726b8548 1114
726b8548
QT		 1115 fcport->disc_state = DSC_GPDB;
1116
1117 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1118 if (!sp)
1119 goto done;
1120
3dbec59b 1121 fcport->flags |= FCF_ASYNC_SENT;
e0824e69
JC		 1122 sp->type = SRB_MB_IOCB;
1123 sp->name = "gpdb";
1124 sp->gen1 = fcport->rscn_gen;
1125 sp->gen2 = fcport->login_gen;
e74e7d95
BH		 1126
1127 mbx = &sp->u.iocb_cmd;
1128 mbx->timeout = qla2x00_async_iocb_timeout;
e0824e69
JC		 1129 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1130
08eb7f45 1131 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
726b8548 1132 if (pd == NULL) {
83548fe2
QT		 1133 ql_log(ql_log_warn, vha, 0xd043,
1134 "Failed to allocate port database structure.\n");
726b8548
QT		 1135 goto done_free_sp;
1136 }
726b8548 1137
726b8548
QT		 1138 mb = sp->u.iocb_cmd.u.mbx.out_mb;
1139 mb[0] = MBC_GET_PORT_DATABASE;
1140 mb[1] = fcport->loop_id;
1141 mb[2] = MSW(pd_dma);
1142 mb[3] = LSW(pd_dma);
1143 mb[6] = MSW(MSD(pd_dma));
1144 mb[7] = LSW(MSD(pd_dma));
1145 mb[9] = vha->vp_idx;
1146 mb[10] = opt;
1147
726b8548
QT		 1148 mbx->u.mbx.in = (void *)pd;
1149 mbx->u.mbx.in_dma = pd_dma;
1150
1151 sp->done = qla24xx_async_gpdb_sp_done;
1152
1153 rval = qla2x00_start_sp(sp);
1154 if (rval != QLA_SUCCESS)
1155 goto done_free_sp;
1156
83548fe2
QT		 1157 ql_dbg(ql_dbg_disc, vha, 0x20dc,
1158 "Async-%s %8phC hndl %x opt %x\n",
1159 sp->name, fcport->port_name, sp->handle, opt);
726b8548
QT		 1160
1161 return rval;
1162
1163done_free_sp:
1164 if (pd)
1165 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1166
25ff6af1 1167 sp->free(sp);
726b8548 1168 fcport->flags &= ~FCF_ASYNC_SENT;
3dbec59b 1169done:
726b8548 1170 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 1171 return rval;
1172}
1173
726b8548 1174static
a4239945 1175void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1176{
726b8548
QT		 1177 unsigned long flags;
1178
726b8548 1179 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
f13515ac 1180 ea->fcport->login_gen++;
726b8548
QT		 1181 ea->fcport->deleted = 0;
1182 ea->fcport->logout_on_delete = 1;
1183
1184 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
1185 vha->fcport_count++;
1186 ea->fcport->login_succ = 1;
1187
cd4ed6b4 1188 qla24xx_sched_upd_fcport(ea->fcport);
414d9ff3
QT		 1189 } else if (ea->fcport->login_succ) {
1190 /*
1191 * We have an existing session. A late RSCN delivery
1192 * must have triggered the session to be re-validate.
a4239945 1193 * Session is still valid.
414d9ff3 1194 */
5ef696aa
QT		 1195 ql_dbg(ql_dbg_disc, vha, 0x20d6,
1196 "%s %d %8phC session revalidate success\n",
a4239945 1197 __func__, __LINE__, ea->fcport->port_name);
8a7eac2f 1198 ea->fcport->disc_state = DSC_LOGIN_COMPLETE;
726b8548
QT		 1199 }
1200 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
a4239945
QT		 1201}
1202
1203static
1204void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1205{
a4239945
QT		 1206 fc_port_t *fcport = ea->fcport;
1207 struct port_database_24xx *pd;
1208 struct srb *sp = ea->sp;
2b5b9647 1209 uint8_t ls;
a4239945
QT		 1210
1211 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
1212
1213 fcport->flags &= ~FCF_ASYNC_SENT;
1214
1215 ql_dbg(ql_dbg_disc, vha, 0x20d2,
8777e431
QT		 1216 "%s %8phC DS %d LS %d nvme %x rc %d\n", __func__, fcport->port_name,
1217 fcport->disc_state, pd->current_login_state, fcport->fc4f_nvme,
1218 ea->rc);
a4239945
QT		 1219
1220 if (fcport->disc_state == DSC_DELETE_PEND)
1221 return;
726b8548 1222
2b5b9647
DT		 1223 if (fcport->fc4f_nvme)
1224 ls = pd->current_login_state >> 4;
1225 else
1226 ls = pd->current_login_state & 0xf;
1227
1228 switch (ls) {
a4239945
QT		 1229 case PDS_PRLI_COMPLETE:
1230 __qla24xx_parse_gpdb(vha, fcport, pd);
1231 break;
1232 case PDS_PLOGI_PENDING:
1233 case PDS_PLOGI_COMPLETE:
1234 case PDS_PRLI_PENDING:
1235 case PDS_PRLI2_PENDING:
8fde6977
QT		 1236 /* Set discovery state back to GNL to Relogin attempt */
1237 if (qla_dual_mode_enabled(vha) ||
1238 qla_ini_mode_enabled(vha)) {
1239 fcport->disc_state = DSC_GNL;
1240 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1241 }
a4239945
QT		 1242 return;
1243 case PDS_LOGO_PENDING:
1244 case PDS_PORT_UNAVAILABLE:
1245 default:
1246 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
1247 __func__, __LINE__, fcport->port_name);
d8630bb9 1248 qlt_schedule_sess_for_deletion(fcport);
a4239945
QT		 1249 return;
1250 }
1251 __qla24xx_handle_gpdb_event(vha, ea);
1252} /* gpdb event */
9cd883f0
QT		 1253
1254static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1255{
1256 u8 login = 0;
040036bb 1257 int rc;
9cd883f0
QT		 1258
1259 if (qla_tgt_mode_enabled(vha))
1260 return;
1261
1262 if (qla_dual_mode_enabled(vha)) {
1263 if (N2N_TOPO(vha->hw)) {
1264 u64 mywwn, wwn;
1265
1266 mywwn = wwn_to_u64(vha->port_name);
1267 wwn = wwn_to_u64(fcport->port_name);
1268 if (mywwn > wwn)
1269 login = 1;
1270 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1271 && time_after_eq(jiffies,
1272 fcport->plogi_nack_done_deadline))
1273 login = 1;
1274 } else {
1275 login = 1;
1276 }
1277 } else {
1278 /* initiator mode */
1279 login = 1;
1280 }
1281
0754d5e0
QT		 1282 if (login && fcport->login_retry) {
1283 fcport->login_retry--;
040036bb
QT		 1284 if (fcport->loop_id == FC_NO_LOOP_ID) {
1285 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
1286 rc = qla2x00_find_new_loop_id(vha, fcport);
1287 if (rc) {
1288 ql_dbg(ql_dbg_disc, vha, 0x20e6,
1289 "%s %d %8phC post del sess - out of loopid\n",
1290 __func__, __LINE__, fcport->port_name);
1291 fcport->scan_state = 0;
94cff6e1 1292 qlt_schedule_sess_for_deletion(fcport);
040036bb
QT		 1293 return;
1294 }
1295 }
9cd883f0
QT		 1296 ql_dbg(ql_dbg_disc, vha, 0x20bf,
1297 "%s %d %8phC post login\n",
1298 __func__, __LINE__, fcport->port_name);
9cd883f0
QT		 1299 qla2x00_post_async_login_work(vha, fcport, NULL);
1300 }
1301}
1302
726b8548
QT		 1303int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1304{
f13515ac 1305 u16 data[2];
a4239945 1306 u64 wwn;
cd4ed6b4 1307 u16 sec;
726b8548 1308
0754d5e0
QT		 1309 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20d8,
1310 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d\n",
726b8548
QT		 1311 __func__, fcport->port_name, fcport->disc_state,
1312 fcport->fw_login_state, fcport->login_pause, fcport->flags,
1313 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
0754d5e0 1314 fcport->login_gen, fcport->loop_id, fcport->scan_state);
726b8548 1315
a4239945
QT		 1316 if (fcport->scan_state != QLA_FCPORT_FOUND)
1317 return 0;
726b8548 1318
07ea4b60
HR		 1319 if ((fcport->loop_id != FC_NO_LOOP_ID) &&
1320 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1321 (fcport->fw_login_state == DSC_LS_PRLI_PEND)))
726b8548
QT		 1322 return 0;
1323
5b33469a 1324 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1325 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1326 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1327 return 0;
9cd883f0 1328 }
5b33469a
QT		 1329 }
1330
726b8548
QT		 1331 /* for pure Target Mode. Login will not be initiated */
1332 if (vha->host->active_mode == MODE_TARGET)
1333 return 0;
1334
1335 if (fcport->flags & FCF_ASYNC_SENT) {
1336 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1337 return 0;
1338 }
1339
1340 switch (fcport->disc_state) {
1341 case DSC_DELETED:
a4239945 1342 wwn = wwn_to_u64(fcport->node_name);
8777e431
QT		 1343 switch (vha->hw->current_topology) {
1344 case ISP_CFG_N:
1345 if (fcport_is_smaller(fcport)) {
1346 /* this adapter is bigger */
1347 if (fcport->login_retry) {
1348 if (fcport->loop_id == FC_NO_LOOP_ID) {
1349 qla2x00_find_new_loop_id(vha,
1350 fcport);
1351 fcport->fw_login_state =
1352 DSC_LS_PORT_UNAVAIL;
1353 }
1354 fcport->login_retry--;
1355 qla_post_els_plogi_work(vha, fcport);
1356 } else {
1357 ql_log(ql_log_info, vha, 0x705d,
1358 "Unable to reach remote port %8phC",
1359 fcport->port_name);
1360 }
1361 } else {
1362 qla24xx_post_gnl_work(vha, fcport);
1363 }
1364 break;
1365 default:
1366 if (wwn == 0) {
1367 ql_dbg(ql_dbg_disc, vha, 0xffff,
1368 "%s %d %8phC post GNNID\n",
1369 __func__, __LINE__, fcport->port_name);
1370 qla24xx_post_gnnid_work(vha, fcport);
1371 } else if (fcport->loop_id == FC_NO_LOOP_ID) {
1372 ql_dbg(ql_dbg_disc, vha, 0x20bd,
1373 "%s %d %8phC post gnl\n",
1374 __func__, __LINE__, fcport->port_name);
1375 qla24xx_post_gnl_work(vha, fcport);
1376 } else {
1377 qla_chk_n2n_b4_login(vha, fcport);
1378 }
1379 break;
726b8548
QT		 1380 }
1381 break;
1382
1383 case DSC_GNL:
8777e431
QT		 1384 switch (vha->hw->current_topology) {
1385 case ISP_CFG_N:
1386 if ((fcport->current_login_state & 0xf) == 0x6) {
1387 ql_dbg(ql_dbg_disc, vha, 0x2118,
1388 "%s %d %8phC post GPDB work\n",
1389 __func__, __LINE__, fcport->port_name);
1390 fcport->chip_reset =
1391 vha->hw->base_qpair->chip_reset;
1392 qla24xx_post_gpdb_work(vha, fcport, 0);
1393 } else {
1394 ql_dbg(ql_dbg_disc, vha, 0x2118,
1395 "%s %d %8phC post NVMe PRLI\n",
1396 __func__, __LINE__, fcport->port_name);
1397 qla24xx_post_prli_work(vha, fcport);
1398 }
1399 break;
1400 default:
1401 if (fcport->login_pause) {
1402 fcport->last_rscn_gen = fcport->rscn_gen;
1403 fcport->last_login_gen = fcport->login_gen;
1404 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1405 break;
1406 }
1407 qla_chk_n2n_b4_login(vha, fcport);
726b8548
QT		 1408 break;
1409 }
726b8548
QT		 1410 break;
1411
1412 case DSC_LOGIN_FAILED:
9cd883f0
QT		 1413 if (N2N_TOPO(vha->hw))
1414 qla_chk_n2n_b4_login(vha, fcport);
1415 else
1416 qla24xx_post_gidpn_work(vha, fcport);
726b8548
QT		 1417 break;
1418
1419 case DSC_LOGIN_COMPLETE:
1420 /* recheck login state */
f13515ac
QT		 1421 data[0] = data[1] = 0;
1422 qla2x00_post_async_adisc_work(vha, fcport, data);
726b8548
QT		 1423 break;
1424
1cbc0efc
DT		 1425 case DSC_LOGIN_PEND:
1426 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1427 qla24xx_post_prli_work(vha, fcport);
1428 break;
1429
cd4ed6b4
QT		 1430 case DSC_UPD_FCPORT:
1431 sec = jiffies_to_msecs(jiffies -
1432 fcport->jiffies_at_registration)/1000;
1433 if (fcport->sec_since_registration < sec && sec &&
1434 !(sec % 60)) {
1435 fcport->sec_since_registration = sec;
1436 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
1437 "%s %8phC - Slow Rport registration(%d Sec)\n",
1438 __func__, fcport->port_name, sec);
1439 }
1440
1441 if (fcport->next_disc_state != DSC_DELETE_PEND)
1442 fcport->next_disc_state = DSC_ADISC;
1443 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1444 break;
1445
726b8548
QT		 1446 default:
1447 break;
1448 }
1449
1450 return 0;
1451}
1452
1453static
1454void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
1455{
1456 fcport->rscn_gen++;
1457
83548fe2
QT		 1458 ql_dbg(ql_dbg_disc, fcport->vha, 0x210c,
1459 "%s %8phC DS %d LS %d\n",
1460 __func__, fcport->port_name, fcport->disc_state,
1461 fcport->fw_login_state);
726b8548
QT		 1462
1463 if (fcport->flags & FCF_ASYNC_SENT)
1464 return;
1465
1466 switch (fcport->disc_state) {
1467 case DSC_DELETED:
1468 case DSC_LOGIN_COMPLETE:
5ef696aa 1469 qla24xx_post_gpnid_work(fcport->vha, &ea->id);
726b8548 1470 break;
726b8548
QT		 1471 default:
1472 break;
1473 }
1474}
1475
1476int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
a4239945 1477 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
726b8548
QT		 1478{
1479 struct qla_work_evt *e;
1480 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1481 if (!e)
1482 return QLA_FUNCTION_FAILED;
1483
1484 e->u.new_sess.id = *id;
1485 e->u.new_sess.pla = pla;
a4239945 1486 e->u.new_sess.fc4_type = fc4_type;
726b8548 1487 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
a4239945
QT		 1488 if (node_name)
1489 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
726b8548
QT		 1490
1491 return qla2x00_post_work(vha, e);
1492}
1493
726b8548
QT		 1494static
1495void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1496 struct event_arg *ea)
1497{
1498 fc_port_t *fcport = ea->fcport;
1499
83548fe2
QT		 1500 ql_dbg(ql_dbg_disc, vha, 0x2102,
1501 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1502 __func__, fcport->port_name, fcport->disc_state,
1503 fcport->fw_login_state, fcport->login_pause,
1504 fcport->deleted, fcport->conflict,
1505 fcport->last_rscn_gen, fcport->rscn_gen,
1506 fcport->last_login_gen, fcport->login_gen,
1507 fcport->flags);
726b8548
QT		 1508
1509 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1510 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1511 return;
1512
5b33469a 1513 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
9cd883f0
QT		 1514 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1515 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5b33469a 1516 return;
9cd883f0 1517 }
5b33469a
QT		 1518 }
1519
726b8548 1520 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 1521 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gidpn\n",
726b8548
QT		 1522 __func__, __LINE__, fcport->port_name);
1523
5d3300a9 1524 qla24xx_post_gidpn_work(vha, fcport);
726b8548
QT		 1525 return;
1526 }
1527
1528 qla24xx_fcport_handle_login(vha, fcport);
1529}
1530
8777e431
QT		 1531
1532void qla_handle_els_plogi_done(scsi_qla_host_t *vha, struct event_arg *ea)
1533{
1534 ql_dbg(ql_dbg_disc, vha, 0x2118,
1535 "%s %d %8phC post PRLI\n",
1536 __func__, __LINE__, ea->fcport->port_name);
1537 qla24xx_post_prli_work(vha, ea->fcport);
1538}
1539
41dc529a 1540void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1541{
f352eeb7 1542 fc_port_t *f, *tf;
41dc529a 1543 uint32_t id = 0, mask, rid;
f352eeb7 1544 unsigned long flags;
bee8b846 1545 fc_port_t *fcport;
726b8548
QT		 1546
1547 switch (ea->event) {
1548 case FCME_RELOGIN:
1549 if (test_bit(UNLOADING, &vha->dpc_flags))
1550 return;
5ff1d584 1551
726b8548
QT		 1552 qla24xx_handle_relogin_event(vha, ea);
1553 break;
1554 case FCME_RSCN:
1555 if (test_bit(UNLOADING, &vha->dpc_flags))
1556 return;
41dc529a
QT		 1557 switch (ea->id.b.rsvd_1) {
1558 case RSCN_PORT_ADDR:
bee8b846
QT		 1559 fcport = qla2x00_find_fcport_by_nportid
1560 (vha, &ea->id, 1);
cd4ed6b4 1561 if (fcport) {
cb873ba4 1562 fcport->scan_needed = 1;
cd4ed6b4
QT		 1563 fcport->rscn_gen++;
1564 }
bee8b846 1565
f352eeb7
QT		 1566 spin_lock_irqsave(&vha->work_lock, flags);
1567 if (vha->scan.scan_flags == 0) {
1568 ql_dbg(ql_dbg_disc, vha, 0xffff,
1569 "%s: schedule\n", __func__);
1570 vha->scan.scan_flags |= SF_QUEUED;
1571 schedule_delayed_work(&vha->scan.scan_work, 5);
41dc529a 1572 }
f352eeb7
QT		 1573 spin_unlock_irqrestore(&vha->work_lock, flags);
1574
41dc529a
QT		 1575 break;
1576 case RSCN_AREA_ADDR:
1577 case RSCN_DOM_ADDR:
1578 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1579 mask = 0xffff00;
83548fe2
QT		 1580 ql_dbg(ql_dbg_async, vha, 0x5044,
1581 "RSCN: Area 0x%06x was affected\n",
1582 ea->id.b24);
41dc529a
QT		 1583 } else {
1584 mask = 0xff0000;
83548fe2
QT		 1585 ql_dbg(ql_dbg_async, vha, 0x507a,
1586 "RSCN: Domain 0x%06x was affected\n",
1587 ea->id.b24);
41dc529a 1588 }
726b8548 1589
41dc529a
QT		 1590 rid = ea->id.b24 & mask;
1591 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1592 list) {
1593 id = f->d_id.b24 & mask;
1594 if (rid == id) {
1595 ea->fcport = f;
1596 qla24xx_handle_rscn_event(f, ea);
1597 }
726b8548 1598 }
41dc529a
QT		 1599 break;
1600 case RSCN_FAB_ADDR:
1601 default:
83548fe2
QT		 1602 ql_log(ql_log_warn, vha, 0xd045,
1603 "RSCN: Fabric was affected. Addr format %d\n",
1604 ea->id.b.rsvd_1);
41dc529a
QT		 1605 qla2x00_mark_all_devices_lost(vha, 1);
1606 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1607 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1608 }
1609 break;
1610 case FCME_GIDPN_DONE:
1611 qla24xx_handle_gidpn_event(vha, ea);
1612 break;
1613 case FCME_GNL_DONE:
1614 qla24xx_handle_gnl_done_event(vha, ea);
1615 break;
1616 case FCME_GPSC_DONE:
a4239945 1617 qla24xx_handle_gpsc_event(vha, ea);
726b8548
QT		 1618 break;
1619 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1620 qla24xx_handle_plogi_done_event(vha, ea);
1621 break;
a5d42f4c
DG		 1622 case FCME_PRLI_DONE:
1623 qla24xx_handle_prli_done_event(vha, ea);
1624 break;
726b8548
QT		 1625 case FCME_GPDB_DONE:
1626 qla24xx_handle_gpdb_event(vha, ea);
1627 break;
1628 case FCME_GPNID_DONE:
1629 qla24xx_handle_gpnid_event(vha, ea);
1630 break;
d3bae931
DG		 1631 case FCME_GFFID_DONE:
1632 qla24xx_handle_gffid_event(vha, ea);
1633 break;
f13515ac
QT		 1634 case FCME_ADISC_DONE:
1635 qla24xx_handle_adisc_event(vha, ea);
1636 break;
a4239945
QT		 1637 case FCME_GNNID_DONE:
1638 qla24xx_handle_gnnid_event(vha, ea);
1639 break;
1640 case FCME_GFPNID_DONE:
1641 qla24xx_handle_gfpnid_event(vha, ea);
1642 break;
8777e431
QT		 1643 case FCME_ELS_PLOGI_DONE:
1644 qla_handle_els_plogi_done(vha, ea);
1645 break;
726b8548
QT		 1646 default:
1647 BUG_ON(1);
1648 break;
1649 }
5ff1d584
AV		 1650}
1651
3822263e 1652static void
faef62d1 1653qla2x00_tmf_iocb_timeout(void *data)
3822263e 1654{
25ff6af1 1655 srb_t *sp = data;
faef62d1 1656 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1657
faef62d1
AB		 1658 tmf->u.tmf.comp_status = CS_TIMEOUT;
1659 complete(&tmf->u.tmf.comp);
1660}
9ba56b95 1661
faef62d1 1662static void
25ff6af1 1663qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1664{
25ff6af1 1665 srb_t *sp = ptr;
faef62d1 1666 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1667
faef62d1 1668 complete(&tmf->u.tmf.comp);
3822263e
MI		 1669}
1670
1671int
faef62d1 1672qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1673 uint32_t tag)
1674{
1675 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1676 struct srb_iocb *tm_iocb;
3822263e 1677 srb_t *sp;
faef62d1 1678 int rval = QLA_FUNCTION_FAILED;
3822263e 1679
9ba56b95 1680 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1681 if (!sp)
1682 goto done;
1683
faef62d1 1684 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1685 sp->type = SRB_TM_CMD;
1686 sp->name = "tmf";
e74e7d95
BH		 1687
1688 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1689 init_completion(&tm_iocb->u.tmf.comp);
faef62d1 1690 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
e74e7d95 1691
faef62d1
AB		 1692 tm_iocb->u.tmf.flags = flags;
1693 tm_iocb->u.tmf.lun = lun;
1694 tm_iocb->u.tmf.data = tag;
1695 sp->done = qla2x00_tmf_sp_done;
3822263e
MI		 1696
1697 rval = qla2x00_start_sp(sp);
1698 if (rval != QLA_SUCCESS)
1699 goto done_free_sp;
1700
7c3df132 1701 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1702 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1703 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1704 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1705
1706 wait_for_completion(&tm_iocb->u.tmf.comp);
1707
b4146c49 1708 rval = tm_iocb->u.tmf.data;
faef62d1 1709
b4146c49
AG		 1710 if (rval != QLA_SUCCESS) {
1711 ql_log(ql_log_warn, vha, 0x8030,
faef62d1
AB		 1712 "TM IOCB failed (%x).\n", rval);
1713 }
1714
1715 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1716 flags = tm_iocb->u.tmf.flags;
1717 lun = (uint16_t)tm_iocb->u.tmf.lun;
1718
1719 /* Issue Marker IOCB */
1720 qla2x00_marker(vha, vha->hw->req_q_map[0],
1721 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1722 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1723 }
3822263e
MI		 1724
1725done_free_sp:
25ff6af1 1726 sp->free(sp);
6d674927 1727 sp->fcport->flags &= ~FCF_ASYNC_SENT;
3822263e
MI		 1728done:
1729 return rval;
1730}
1731
4440e46d
AB		 1732static void
1733qla24xx_abort_iocb_timeout(void *data)
1734{
25ff6af1 1735 srb_t *sp = data;
4440e46d
AB		 1736 struct srb_iocb *abt = &sp->u.iocb_cmd;
1737
1738 abt->u.abt.comp_status = CS_TIMEOUT;
f6145e86 1739 sp->done(sp, QLA_FUNCTION_TIMEOUT);
4440e46d
AB		 1740}
1741
1742static void
25ff6af1 1743qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1744{
25ff6af1 1745 srb_t *sp = ptr;
4440e46d
AB		 1746 struct srb_iocb *abt = &sp->u.iocb_cmd;
1747
f6145e86
QT		 1748 if (del_timer(&sp->u.iocb_cmd.timer)) {
1749 if (sp->flags & SRB_WAKEUP_ON_COMP)
1750 complete(&abt->u.abt.comp);
1751 else
1752 sp->free(sp);
1753 }
4440e46d
AB		 1754}
1755
15f30a57 1756int
f6145e86 1757qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait)
4440e46d 1758{
25ff6af1 1759 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1760 struct srb_iocb *abt_iocb;
1761 srb_t *sp;
1762 int rval = QLA_FUNCTION_FAILED;
1763
6a629468
QT		 1764 sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport,
1765 GFP_KERNEL);
4440e46d
AB		 1766 if (!sp)
1767 goto done;
1768
1769 abt_iocb = &sp->u.iocb_cmd;
1770 sp->type = SRB_ABT_CMD;
1771 sp->name = "abort";
49cecca7 1772 sp->qpair = cmd_sp->qpair;
f6145e86
QT		 1773 if (wait)
1774 sp->flags = SRB_WAKEUP_ON_COMP;
e74e7d95
BH		 1775
1776 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1777 init_completion(&abt_iocb->u.abt.comp);
4440e46d 1778 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
e74e7d95 1779
4440e46d 1780 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
49cecca7 1781 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id);
b027a5ac 1782
4440e46d 1783 sp->done = qla24xx_abort_sp_done;
4440e46d
AB		 1784
1785 rval = qla2x00_start_sp(sp);
1786 if (rval != QLA_SUCCESS)
1787 goto done_free_sp;
1788
1789 ql_dbg(ql_dbg_async, vha, 0x507c,
49cecca7
QT		 1790 "Abort command issued - hdl=%x, type=%x\n",
1791 cmd_sp->handle, cmd_sp->type);
4440e46d 1792
f6145e86
QT		 1793 if (wait) {
1794 wait_for_completion(&abt_iocb->u.abt.comp);
1795 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1796 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1797 }
4440e46d
AB		 1798
1799done_free_sp:
25ff6af1 1800 sp->free(sp);
4440e46d
AB		 1801done:
1802 return rval;
1803}
1804
1805int
1806qla24xx_async_abort_command(srb_t *sp)
1807{
1808 unsigned long flags = 0;
1809
1810 uint32_t handle;
1811 fc_port_t *fcport = sp->fcport;
1812 struct scsi_qla_host *vha = fcport->vha;
1813 struct qla_hw_data *ha = vha->hw;
1814 struct req_que *req = vha->req;
1815
b027a5ac
DT		 1816 if (vha->flags.qpairs_available && sp->qpair)
1817 req = sp->qpair->req;
1818
4440e46d
AB		 1819 spin_lock_irqsave(&ha->hardware_lock, flags);
1820 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1821 if (req->outstanding_cmds[handle] == sp)
1822 break;
1823 }
1824 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1825 if (handle == req->num_outstanding_cmds) {
1826 /* Command not found. */
1827 return QLA_FUNCTION_FAILED;
1828 }
1829 if (sp->type == SRB_FXIOCB_DCMD)
1830 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1831 FXDISC_ABORT_IOCTL);
1832
f6145e86 1833 return qla24xx_async_abort_cmd(sp, true);
4440e46d
AB		 1834}
1835
a5d42f4c
DG		 1836static void
1837qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1838{
1839 switch (ea->data[0]) {
1840 case MBS_COMMAND_COMPLETE:
1841 ql_dbg(ql_dbg_disc, vha, 0x2118,
1842 "%s %d %8phC post gpdb\n",
1843 __func__, __LINE__, ea->fcport->port_name);
1844
1845 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1846 ea->fcport->logout_on_delete = 1;
1847 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1848 break;
1849 default:
1cbc0efc
DT		 1850 if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) &&
1851 (ea->iop[1] == 0x50000)) { /* reson 5=busy expl:0x0 */
1852 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1853 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP;
1854 break;
1855 }
1856
edd05de1
DG		 1857 if (ea->fcport->n2n_flag) {
1858 ql_dbg(ql_dbg_disc, vha, 0x2118,
1859 "%s %d %8phC post fc4 prli\n",
1860 __func__, __LINE__, ea->fcport->port_name);
1861 ea->fcport->fc4f_nvme = 0;
1862 ea->fcport->n2n_flag = 0;
1863 qla24xx_post_prli_work(vha, ea->fcport);
1864 }
a5d42f4c
DG		 1865 ql_dbg(ql_dbg_disc, vha, 0x2119,
1866 "%s %d %8phC unhandle event of %x\n",
1867 __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
1868 break;
1869 }
1870}
1871
726b8548
QT		 1872static void
1873qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1874{
726b8548 1875 port_id_t cid; /* conflict Nport id */
a084fd68
QT		 1876 u16 lid;
1877 struct fc_port *conflict_fcport;
82abdcaf 1878 unsigned long flags;
a4239945
QT		 1879 struct fc_port *fcport = ea->fcport;
1880
f352eeb7
QT		 1881 ql_dbg(ql_dbg_disc, vha, 0xffff,
1882 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
1883 __func__, fcport->port_name, fcport->disc_state,
1884 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
1885 ea->sp->gen2, fcport->rscn_gen|ea->sp->gen1,
1886 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
1887
a4239945
QT		 1888 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1889 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) {
1890 ql_dbg(ql_dbg_disc, vha, 0x20ea,
1891 "%s %d %8phC Remote is trying to login\n",
1892 __func__, __LINE__, fcport->port_name);
1893 return;
1894 }
1895
1896 if (fcport->disc_state == DSC_DELETE_PEND)
1897 return;
1898
1899 if (ea->sp->gen2 != fcport->login_gen) {
1900 /* target side must have changed it. */
1901 ql_dbg(ql_dbg_disc, vha, 0x20d3,
f352eeb7
QT		 1902 "%s %8phC generation changed\n",
1903 __func__, fcport->port_name);
1904 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
a4239945
QT		 1905 return;
1906 } else if (ea->sp->gen1 != fcport->rscn_gen) {
1907 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
1908 __func__, __LINE__, fcport->port_name);
1909 qla24xx_post_gidpn_work(vha, fcport);
1910 return;
1911 }
ac280b67 1912
726b8548 1913 switch (ea->data[0]) {
ac280b67 1914 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1915 /*
1916 * Driver must validate login state - If PRLI not complete,
1917 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1918 * requests.
1919 */
a5d42f4c
DG		 1920 if (ea->fcport->fc4f_nvme) {
1921 ql_dbg(ql_dbg_disc, vha, 0x2117,
1922 "%s %d %8phC post prli\n",
1923 __func__, __LINE__, ea->fcport->port_name);
1924 qla24xx_post_prli_work(vha, ea->fcport);
1925 } else {
1926 ql_dbg(ql_dbg_disc, vha, 0x20ea,
a084fd68
QT		 1927 "%s %d %8phC LoopID 0x%x in use with %06x. post gnl\n",
1928 __func__, __LINE__, ea->fcport->port_name,
1929 ea->fcport->loop_id, ea->fcport->d_id.b24);
1930
1931 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
82abdcaf 1932 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a5d42f4c
DG		 1933 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1934 ea->fcport->logout_on_delete = 1;
3515832c 1935 ea->fcport->send_els_logo = 0;
82abdcaf
QT		 1936 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP;
1937 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1938
a5d42f4c
DG		 1939 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1940 }
ac280b67
AV		 1941 break;
1942 case MBS_COMMAND_ERROR:
83548fe2 1943 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
726b8548
QT		 1944 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1945
1946 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1947 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1948 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1949 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1950 else
726b8548 1951 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1952 break;
1953 case MBS_LOOP_ID_USED:
726b8548
QT		 1954 /* data[1] = IO PARAM 1 = nport ID */
1955 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1956 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1957 cid.b.al_pa = ea->iop[1] & 0xff;
1958 cid.b.rsvd_1 = 0;
1959
83548fe2
QT		 1960 ql_dbg(ql_dbg_disc, vha, 0x20ec,
1961 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1962 __func__, __LINE__, ea->fcport->port_name,
1963 ea->fcport->loop_id);
726b8548
QT		 1964
1965 if (IS_SW_RESV_ADDR(cid)) {
1966 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1967 ea->fcport->loop_id = FC_NO_LOOP_ID;
1968 } else {
1969 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1970 }
726b8548
QT		 1971 qla24xx_post_gnl_work(vha, ea->fcport);
1972 break;
1973 case MBS_PORT_ID_USED:
83548fe2
QT		 1974 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1975 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1976 __func__, __LINE__, ea->fcport->port_name,
1977 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1978 ea->fcport->d_id.b.al_pa);
726b8548 1979
a084fd68
QT		 1980 lid = ea->iop[1] & 0xffff;
1981 qlt_find_sess_invalidate_other(vha,
1982 wwn_to_u64(ea->fcport->port_name),
1983 ea->fcport->d_id, lid, &conflict_fcport);
1984
1985 if (conflict_fcport) {
1986 /*
1987 * Another fcport share the same loop_id/nport id.
1988 * Conflict fcport needs to finish cleanup before this
1989 * fcport can proceed to login.
1990 */
1991 conflict_fcport->conflict = ea->fcport;
1992 ea->fcport->login_pause = 1;
1993
1994 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1995 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
1996 __func__, __LINE__, ea->fcport->port_name,
1997 ea->fcport->d_id.b24, lid);
1998 qla2x00_clear_loop_id(ea->fcport);
1999 qla24xx_post_gidpn_work(vha, ea->fcport);
2000 } else {
2001 ql_dbg(ql_dbg_disc, vha, 0x20ed,
2002 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
2003 __func__, __LINE__, ea->fcport->port_name,
2004 ea->fcport->d_id.b24, lid);
2005
2006 qla2x00_clear_loop_id(ea->fcport);
2007 set_bit(lid, vha->hw->loop_id_map);
2008 ea->fcport->loop_id = lid;
2009 ea->fcport->keep_nport_handle = 0;
94cff6e1 2010 qlt_schedule_sess_for_deletion(ea->fcport);
a084fd68 2011 }
ac280b67
AV		 2012 break;
2013 }
4916392b 2014 return;
ac280b67
AV		 2015}
2016
4916392b 2017void
ac280b67
AV		 2018qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
2019 uint16_t *data)
2020{
a6ca8878 2021 qlt_logo_completion_handler(fcport, data[0]);
726b8548 2022 fcport->login_gen++;
fa83e658 2023 fcport->flags &= ~FCF_ASYNC_ACTIVE;
4916392b 2024 return;
ac280b67
AV		 2025}
2026
4916392b 2027void
5ff1d584
AV		 2028qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
2029 uint16_t *data)
2030{
fa83e658 2031 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
5ff1d584
AV		 2032 if (data[0] == MBS_COMMAND_COMPLETE) {
2033 qla2x00_update_fcport(vha, fcport);
2034
4916392b 2035 return;
5ff1d584
AV		 2036 }
2037
2038 /* Retry login. */
5ff1d584
AV		 2039 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
2040 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2041 else
80d79440 2042 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 2043
4916392b 2044 return;
5ff1d584
AV		 2045}
2046
1da177e4
LT		 2047/****************************************************************************/
2048/* QLogic ISP2x00 Hardware Support Functions. */
2049/****************************************************************************/
2050
fa492630 2051static int
7d613ac6
SV		 2052qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
2053{
2054 int rval = QLA_SUCCESS;
2055 struct qla_hw_data *ha = vha->hw;
2056 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 2057 uint16_t config[4];
7d613ac6
SV		 2058
2059 qla83xx_idc_lock(vha, 0);
2060
2061 /* SV: TODO: Assign initialization timeout from
2062 * flash-info / other param
2063 */
2064 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
2065 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
2066
2067 /* Set our fcoe function presence */
2068 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
2069 ql_dbg(ql_dbg_p3p, vha, 0xb077,
2070 "Error while setting DRV-Presence.\n");
2071 rval = QLA_FUNCTION_FAILED;
2072 goto exit;
2073 }
2074
2075 /* Decide the reset ownership */
2076 qla83xx_reset_ownership(vha);
2077
2078 /*
2079 * On first protocol driver load:
2080 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
2081 * register.
2082 * Others: Check compatibility with current IDC Major version.
2083 */
2084 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
2085 if (ha->flags.nic_core_reset_owner) {
2086 /* Set IDC Major version */
2087 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
2088 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
2089
2090 /* Clearing IDC-Lock-Recovery register */
2091 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
2092 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
2093 /*
2094 * Clear further IDC participation if we are not compatible with
2095 * the current IDC Major Version.
2096 */
2097 ql_log(ql_log_warn, vha, 0xb07d,
2098 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
2099 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
2100 __qla83xx_clear_drv_presence(vha);
2101 rval = QLA_FUNCTION_FAILED;
2102 goto exit;
2103 }
2104 /* Each function sets its supported Minor version. */
2105 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
2106 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
2107 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
2108
711aa7f7
SK		 2109 if (ha->flags.nic_core_reset_owner) {
2110 memset(config, 0, sizeof(config));
2111 if (!qla81xx_get_port_config(vha, config))
2112 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
2113 QLA8XXX_DEV_READY);
2114 }
2115
7d613ac6
SV		 2116 rval = qla83xx_idc_state_handler(vha);
2117
2118exit:
2119 qla83xx_idc_unlock(vha, 0);
2120
2121 return rval;
2122}
2123
1da177e4
LT		 2124/*
2125* qla2x00_initialize_adapter
2126* Initialize board.
2127*
2128* Input:
2129* ha = adapter block pointer.
2130*
2131* Returns:
2132* 0 = success
2133*/
2134int
e315cd28 2135qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 2136{
2137 int rval;
e315cd28 2138 struct qla_hw_data *ha = vha->hw;
73208dfd 2139 struct req_que *req = ha->req_q_map[0];
2533cf67 2140
fc90adaf
JC		 2141 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
2142 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
2143
1da177e4 2144 /* Clear adapter flags. */
e315cd28 2145 vha->flags.online = 0;
2533cf67 2146 ha->flags.chip_reset_done = 0;
e315cd28 2147 vha->flags.reset_active = 0;
85880801
AV		 2148 ha->flags.pci_channel_io_perm_failure = 0;
2149 ha->flags.eeh_busy = 0;
fabbb8df 2150 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 2151 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2152 atomic_set(&vha->loop_state, LOOP_DOWN);
2153 vha->device_flags = DFLG_NO_CABLE;
2154 vha->dpc_flags = 0;
2155 vha->flags.management_server_logged_in = 0;
2156 vha->marker_needed = 0;
1da177e4
LT		 2157 ha->isp_abort_cnt = 0;
2158 ha->beacon_blink_led = 0;
2159
73208dfd
AC		 2160 set_bit(0, ha->req_qid_map);
2161 set_bit(0, ha->rsp_qid_map);
2162
cfb0919c 2163 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 2164 "Configuring PCI space...\n");
e315cd28 2165 rval = ha->isp_ops->pci_config(vha);
1da177e4 2166 if (rval) {
7c3df132
SK		 2167 ql_log(ql_log_warn, vha, 0x0044,
2168 "Unable to configure PCI space.\n");
1da177e4
LT		 2169 return (rval);
2170 }
2171
e315cd28 2172 ha->isp_ops->reset_chip(vha);
1da177e4 2173
e315cd28 2174 rval = qla2xxx_get_flash_info(vha);
c00d8994 2175 if (rval) {
7c3df132
SK		 2176 ql_log(ql_log_fatal, vha, 0x004f,
2177 "Unable to validate FLASH data.\n");
7ec0effd
AD		 2178 return rval;
2179 }
2180
2181 if (IS_QLA8044(ha)) {
2182 qla8044_read_reset_template(vha);
2183
2184 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
2185 * If DONRESET_BIT0 is set, drivers should not set dev_state
2186 * to NEED_RESET. But if NEED_RESET is set, drivers should
2187 * should honor the reset. */
2188 if (ql2xdontresethba == 1)
2189 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 2190 }
2191
73208dfd 2192 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 2193 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 2194 "Configure NVRAM parameters...\n");
0107109e 2195
e315cd28 2196 ha->isp_ops->nvram_config(vha);
1da177e4 2197
d4c760c2
AV		 2198 if (ha->flags.disable_serdes) {
2199 /* Mask HBA via NVRAM settings? */
7c3df132 2200 ql_log(ql_log_info, vha, 0x0077,
7b833558 2201 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 2202 return QLA_FUNCTION_FAILED;
2203 }
2204
cfb0919c 2205 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 2206 "Verifying loaded RISC code...\n");
1da177e4 2207
e315cd28
AC		 2208 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
2209 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 2210 if (rval)
2211 return (rval);
e315cd28 2212 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 2213 if (rval)
2214 return (rval);
1da177e4 2215 }
a9083016 2216
4d4df193 2217 if (IS_QLA84XX(ha)) {
e315cd28 2218 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 2219 if (!ha->cs84xx) {
7c3df132 2220 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 2221 "Unable to configure ISP84XX.\n");
2222 return QLA_FUNCTION_FAILED;
2223 }
2224 }
2d70c103 2225
ead03855 2226 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 2227 rval = qla2x00_init_rings(vha);
2228
2533cf67 2229 ha->flags.chip_reset_done = 1;
1da177e4 2230
9a069e19 2231 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 2232 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 2233 rval = qla84xx_init_chip(vha);
2234 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2235 ql_log(ql_log_warn, vha, 0x00d4,
2236 "Unable to initialize ISP84XX.\n");
8d2b21db 2237 qla84xx_put_chip(vha);
9a069e19
GM		 2238 }
2239 }
2240
7d613ac6
SV		 2241 /* Load the NIC Core f/w if we are the first protocol driver. */
2242 if (IS_QLA8031(ha)) {
2243 rval = qla83xx_nic_core_fw_load(vha);
2244 if (rval)
2245 ql_log(ql_log_warn, vha, 0x0124,
2246 "Error in initializing NIC Core f/w.\n");
2247 }
2248
2f0f3f4f
MI		 2249 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
2250 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 2251
c46e65c7
JC		 2252 if (IS_P3P_TYPE(ha))
2253 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
2254 else
2255 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
2256
1da177e4
LT		 2257 return (rval);
2258}
2259
2260/**
abbd8870 2261 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
2db6228d 2262 * @vha: HA context
1da177e4
LT		 2263 *
2264 * Returns 0 on success.
2265 */
abbd8870 2266int
e315cd28 2267qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 2268{
a157b101 2269 uint16_t w;
abbd8870 2270 unsigned long flags;
e315cd28 2271 struct qla_hw_data *ha = vha->hw;
3d71644c 2272 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2273
1da177e4 2274 pci_set_master(ha->pdev);
af6177d8 2275 pci_try_set_mwi(ha->pdev);
1da177e4 2276
1da177e4 2277 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2278 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 2279 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2280
737faece 2281 pci_disable_rom(ha->pdev);
1da177e4
LT		 2282
2283 /* Get PCI bus information. */
2284 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2285 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 2286 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2287
abbd8870
AV		 2288 return QLA_SUCCESS;
2289}
1da177e4 2290
abbd8870
AV		 2291/**
2292 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
2db6228d 2293 * @vha: HA context
abbd8870
AV		 2294 *
2295 * Returns 0 on success.
2296 */
2297int
e315cd28 2298qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 2299{
a157b101 2300 uint16_t w;
abbd8870
AV		 2301 unsigned long flags = 0;
2302 uint32_t cnt;
e315cd28 2303 struct qla_hw_data *ha = vha->hw;
3d71644c 2304 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2305
abbd8870 2306 pci_set_master(ha->pdev);
af6177d8 2307 pci_try_set_mwi(ha->pdev);
1da177e4 2308
abbd8870 2309 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2310 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 2311
abbd8870
AV		 2312 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2313 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 2314 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 2315
abbd8870
AV		 2316 /*
2317 * If this is a 2300 card and not 2312, reset the
2318 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
2319 * the 2310 also reports itself as a 2300 so we need to get the
2320 * fb revision level -- a 6 indicates it really is a 2300 and
2321 * not a 2310.
2322 */
2323 if (IS_QLA2300(ha)) {
2324 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 2325
abbd8870 2326 /* Pause RISC. */
3d71644c 2327 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 2328 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2329 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 2330 break;
1da177e4 2331
abbd8870
AV		 2332 udelay(10);
2333 }
1da177e4 2334
abbd8870 2335 /* Select FPM registers. */
3d71644c
AV		 2336 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2337 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2338
2339 /* Get the fb rev level */
3d71644c 2340 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 2341
2342 if (ha->fb_rev == FPM_2300)
a157b101 2343 pci_clear_mwi(ha->pdev);
abbd8870
AV		 2344
2345 /* Deselect FPM registers. */
3d71644c
AV		 2346 WRT_REG_WORD(&reg->ctrl_status, 0x0);
2347 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2348
2349 /* Release RISC module. */
3d71644c 2350 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 2351 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 2352 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 2353 break;
2354
2355 udelay(10);
1da177e4 2356 }
1da177e4 2357
abbd8870
AV		 2358 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2359 }
1da177e4 2360
abbd8870
AV		 2361 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2362
737faece 2363 pci_disable_rom(ha->pdev);
1da177e4 2364
abbd8870
AV		 2365 /* Get PCI bus information. */
2366 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 2367 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 2368 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2369
2370 return QLA_SUCCESS;
1da177e4
LT		 2371}
2372
0107109e
AV		 2373/**
2374 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
2db6228d 2375 * @vha: HA context
0107109e
AV		 2376 *
2377 * Returns 0 on success.
2378 */
2379int
e315cd28 2380qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 2381{
a157b101 2382 uint16_t w;
0107109e 2383 unsigned long flags = 0;
e315cd28 2384 struct qla_hw_data *ha = vha->hw;
0107109e 2385 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 2386
2387 pci_set_master(ha->pdev);
af6177d8 2388 pci_try_set_mwi(ha->pdev);
0107109e
AV		 2389
2390 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 2391 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 2392 w &= ~PCI_COMMAND_INTX_DISABLE;
2393 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2394
2395 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2396
2397 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 2398 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
2399 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 2400
2401 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2402 if (pci_is_pcie(ha->pdev))
5ffd3a52 2403 pcie_set_readrq(ha->pdev, 4096);
0107109e 2404
737faece 2405 pci_disable_rom(ha->pdev);
0107109e 2406
44c10138 2407 ha->chip_revision = ha->pdev->revision;
a8488abe 2408
0107109e
AV		 2409 /* Get PCI bus information. */
2410 spin_lock_irqsave(&ha->hardware_lock, flags);
2411 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
2412 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2413
2414 return QLA_SUCCESS;
2415}
2416
c3a2f0df
AV		 2417/**
2418 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
2db6228d 2419 * @vha: HA context
c3a2f0df
AV		 2420 *
2421 * Returns 0 on success.
2422 */
2423int
e315cd28 2424qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 2425{
2426 uint16_t w;
e315cd28 2427 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 2428
2429 pci_set_master(ha->pdev);
2430 pci_try_set_mwi(ha->pdev);
2431
2432 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2433 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2434 w &= ~PCI_COMMAND_INTX_DISABLE;
2435 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2436
2437 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 2438 if (pci_is_pcie(ha->pdev))
5ffd3a52 2439 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 2440
737faece 2441 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 2442
2443 ha->chip_revision = ha->pdev->revision;
2444
2445 return QLA_SUCCESS;
2446}
2447
1da177e4
LT		 2448/**
2449 * qla2x00_isp_firmware() - Choose firmware image.
2db6228d 2450 * @vha: HA context
1da177e4
LT		 2451 *
2452 * Returns 0 on success.
2453 */
2454static int
e315cd28 2455qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 2456{
2457 int rval;
42e421b1
AV		 2458 uint16_t loop_id, topo, sw_cap;
2459 uint8_t domain, area, al_pa;
e315cd28 2460 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2461
2462 /* Assume loading risc code */
fa2a1ce5 2463 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 2464
2465 if (ha->flags.disable_risc_code_load) {
7c3df132 2466 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 2467
2468 /* Verify checksum of loaded RISC code. */
e315cd28 2469 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 2470 if (rval == QLA_SUCCESS) {
2471 /* And, verify we are not in ROM code. */
e315cd28 2472 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 2473 &area, &domain, &topo, &sw_cap);
2474 }
1da177e4
LT		 2475 }
2476
7c3df132
SK		 2477 if (rval)
2478 ql_dbg(ql_dbg_init, vha, 0x007a,
2479 "**** Load RISC code ****.\n");
1da177e4
LT		 2480
2481 return (rval);
2482}
2483
2484/**
2485 * qla2x00_reset_chip() - Reset ISP chip.
2db6228d 2486 * @vha: HA context
1da177e4
LT		 2487 *
2488 * Returns 0 on success.
2489 */
abbd8870 2490void
e315cd28 2491qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 2492{
2493 unsigned long flags = 0;
e315cd28 2494 struct qla_hw_data *ha = vha->hw;
3d71644c 2495 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2496 uint32_t cnt;
1da177e4
LT		 2497 uint16_t cmd;
2498
85880801
AV		 2499 if (unlikely(pci_channel_offline(ha->pdev)))
2500 return;
2501
fd34f556 2502 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 2503
2504 spin_lock_irqsave(&ha->hardware_lock, flags);
2505
2506 /* Turn off master enable */
2507 cmd = 0;
2508 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2509 cmd &= ~PCI_COMMAND_MASTER;
2510 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2511
2512 if (!IS_QLA2100(ha)) {
2513 /* Pause RISC. */
2514 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2515 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2516 for (cnt = 0; cnt < 30000; cnt++) {
2517 if ((RD_REG_WORD(&reg->hccr) &
2518 HCCR_RISC_PAUSE) != 0)
2519 break;
2520 udelay(100);
2521 }
2522 } else {
2523 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2524 udelay(10);
2525 }
2526
2527 /* Select FPM registers. */
2528 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2529 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2530
2531 /* FPM Soft Reset. */
2532 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
2533 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2534
2535 /* Toggle Fpm Reset. */
2536 if (!IS_QLA2200(ha)) {
2537 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
2538 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2539 }
2540
2541 /* Select frame buffer registers. */
2542 WRT_REG_WORD(&reg->ctrl_status, 0x10);
2543 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2544
2545 /* Reset frame buffer FIFOs. */
2546 if (IS_QLA2200(ha)) {
2547 WRT_FB_CMD_REG(ha, reg, 0xa000);
2548 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2549 } else {
2550 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2551
2552 /* Read back fb_cmd until zero or 3 seconds max */
2553 for (cnt = 0; cnt < 3000; cnt++) {
2554 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2555 break;
2556 udelay(100);
2557 }
2558 }
2559
2560 /* Select RISC module registers. */
2561 WRT_REG_WORD(&reg->ctrl_status, 0);
2562 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2563
2564 /* Reset RISC processor. */
2565 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2566 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2567
2568 /* Release RISC processor. */
2569 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2570 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2571 }
2572
2573 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
2574 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
2575
2576 /* Reset ISP chip. */
2577 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2578
2579 /* Wait for RISC to recover from reset. */
2580 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2581 /*
2582 * It is necessary to for a delay here since the card doesn't
2583 * respond to PCI reads during a reset. On some architectures
2584 * this will result in an MCA.
2585 */
2586 udelay(20);
2587 for (cnt = 30000; cnt; cnt--) {
2588 if ((RD_REG_WORD(&reg->ctrl_status) &
2589 CSR_ISP_SOFT_RESET) == 0)
2590 break;
2591 udelay(100);
2592 }
2593 } else
2594 udelay(10);
2595
2596 /* Reset RISC processor. */
2597 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2598
2599 WRT_REG_WORD(&reg->semaphore, 0);
2600
2601 /* Release RISC processor. */
2602 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2603 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2604
2605 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2606 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 2607 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 2608 break;
1da177e4
LT		 2609
2610 udelay(100);
2611 }
2612 } else
2613 udelay(100);
2614
2615 /* Turn on master enable */
2616 cmd |= PCI_COMMAND_MASTER;
2617 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2618
2619 /* Disable RISC pause on FPM parity error. */
2620 if (!IS_QLA2100(ha)) {
2621 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2622 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2623 }
2624
2625 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2626}
2627
b1d46989
MI		 2628/**
2629 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2db6228d 2630 * @vha: HA context
b1d46989
MI		 2631 *
2632 * Returns 0 on success.
2633 */
fa492630 2634static int
b1d46989
MI		 2635qla81xx_reset_mpi(scsi_qla_host_t *vha)
2636{
2637 uint16_t mb[4] = {0x1010, 0, 1, 0};
2638
6246b8a1
GM		 2639 if (!IS_QLA81XX(vha->hw))
2640 return QLA_SUCCESS;
2641
b1d46989
MI		 2642 return qla81xx_write_mpi_register(vha, mb);
2643}
2644
0107109e 2645/**
88c26663 2646 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
2db6228d 2647 * @vha: HA context
0107109e
AV		 2648 *
2649 * Returns 0 on success.
2650 */
d14e72fb 2651static inline int
e315cd28 2652qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2653{
2654 unsigned long flags = 0;
e315cd28 2655 struct qla_hw_data *ha = vha->hw;
0107109e 2656 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2657 uint32_t cnt;
335a1cc9 2658 uint16_t wd;
b1d46989 2659 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2660 int rval = QLA_SUCCESS;
0107109e 2661
0107109e
AV		 2662 spin_lock_irqsave(&ha->hardware_lock, flags);
2663
2664 /* Reset RISC. */
2665 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2666 for (cnt = 0; cnt < 30000; cnt++) {
2667 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2668 break;
2669
2670 udelay(10);
2671 }
2672
d14e72fb
HM		 2673 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2674 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2675
2676 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2677 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2678 RD_REG_DWORD(&reg->hccr),
2679 RD_REG_DWORD(&reg->ctrl_status),
2680 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2681
0107109e
AV		 2682 WRT_REG_DWORD(&reg->ctrl_status,
2683 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2684 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2685
335a1cc9 2686 udelay(100);
d14e72fb 2687
88c26663 2688 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2689 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2690 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2691 rval == QLA_SUCCESS; cnt--) {
88c26663 2692 barrier();
d14e72fb
HM		 2693 if (cnt)
2694 udelay(5);
2695 else
2696 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2697 }
2698
d14e72fb
HM		 2699 if (rval == QLA_SUCCESS)
2700 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2701
2702 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2703 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2704 RD_REG_DWORD(&reg->hccr),
2705 RD_REG_DWORD(&reg->mailbox0));
2706
335a1cc9 2707 /* Wait for soft-reset to complete. */
52c82823 2708 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2709 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2710 barrier();
d14e72fb
HM		 2711 if ((RD_REG_DWORD(&reg->ctrl_status) &
2712 CSRX_ISP_SOFT_RESET) == 0)
2713 break;
2714
2715 udelay(5);
0107109e 2716 }
d14e72fb
HM		 2717 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2718 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2719
2720 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2721 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2722 RD_REG_DWORD(&reg->hccr),
2723 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2724
b1d46989
MI		 2725 /* If required, do an MPI FW reset now */
2726 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2727 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2728 if (++abts_cnt < 5) {
2729 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2730 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2731 } else {
2732 /*
2733 * We exhausted the ISP abort retries. We have to
2734 * set the board offline.
2735 */
2736 abts_cnt = 0;
2737 vha->flags.online = 0;
2738 }
2739 }
2740 }
2741
0107109e
AV		 2742 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2743 RD_REG_DWORD(&reg->hccr);
2744
2745 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2746 RD_REG_DWORD(&reg->hccr);
2747
2748 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2749 RD_REG_DWORD(&reg->hccr);
2750
52c82823 2751 RD_REG_WORD(&reg->mailbox0);
200ffb15 2752 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2753 rval == QLA_SUCCESS; cnt--) {
0107109e 2754 barrier();
d14e72fb
HM		 2755 if (cnt)
2756 udelay(5);
2757 else
2758 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2759 }
d14e72fb
HM		 2760 if (rval == QLA_SUCCESS)
2761 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2762
2763 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2764 "Host Risc 0x%x, mailbox0 0x%x\n",
2765 RD_REG_DWORD(&reg->hccr),
2766 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2767
2768 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2769
d14e72fb
HM		 2770 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2771 "Driver in %s mode\n",
2772 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2773
124f85e6
AV		 2774 if (IS_NOPOLLING_TYPE(ha))
2775 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2776
2777 return rval;
0107109e
AV		 2778}
2779
4ea2c9c7
JC		 2780static void
2781qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2782{
2783 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2784
2785 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2786 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2787
2788}
2789
2790static void
2791qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2792{
2793 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2794
2795 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2796 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2797}
2798
2799static void
2800qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2801{
4ea2c9c7
JC		 2802 uint32_t wd32 = 0;
2803 uint delta_msec = 100;
2804 uint elapsed_msec = 0;
2805 uint timeout_msec;
2806 ulong n;
2807
cc790764
JC		 2808 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2809 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2810 return;
2811
8dd7e3a5
JC		 2812 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2813 udelay(100);
2814
4ea2c9c7
JC		 2815attempt:
2816 timeout_msec = TIMEOUT_SEMAPHORE;
2817 n = timeout_msec / delta_msec;
2818 while (n--) {
2819 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2820 qla25xx_read_risc_sema_reg(vha, &wd32);
2821 if (wd32 & RISC_SEMAPHORE)
2822 break;
2823 msleep(delta_msec);
2824 elapsed_msec += delta_msec;
2825 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2826 goto force;
2827 }
2828
2829 if (!(wd32 & RISC_SEMAPHORE))
2830 goto force;
2831
2832 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2833 goto acquired;
2834
2835 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2836 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2837 n = timeout_msec / delta_msec;
2838 while (n--) {
2839 qla25xx_read_risc_sema_reg(vha, &wd32);
2840 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2841 break;
2842 msleep(delta_msec);
2843 elapsed_msec += delta_msec;
2844 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2845 goto force;
2846 }
2847
2848 if (wd32 & RISC_SEMAPHORE_FORCE)
2849 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2850
2851 goto attempt;
2852
2853force:
2854 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2855
2856acquired:
2857 return;
2858}
2859
88c26663
AV		 2860/**
2861 * qla24xx_reset_chip() - Reset ISP24xx chip.
2db6228d 2862 * @vha: HA context
88c26663
AV		 2863 *
2864 * Returns 0 on success.
2865 */
2866void
e315cd28 2867qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2868{
e315cd28 2869 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2870
2871 if (pci_channel_offline(ha->pdev) &&
2872 ha->flags.pci_channel_io_perm_failure) {
2873 return;
2874 }
2875
fd34f556 2876 ha->isp_ops->disable_intrs(ha);
88c26663 2877
4ea2c9c7
JC		 2878 qla25xx_manipulate_risc_semaphore(vha);
2879
88c26663 2880 /* Perform RISC reset. */
e315cd28 2881 qla24xx_reset_risc(vha);
88c26663
AV		 2882}
2883
1da177e4
LT		 2884/**
2885 * qla2x00_chip_diag() - Test chip for proper operation.
2db6228d 2886 * @vha: HA context
1da177e4
LT		 2887 *
2888 * Returns 0 on success.
2889 */
abbd8870 2890int
e315cd28 2891qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2892{
2893 int rval;
e315cd28 2894 struct qla_hw_data *ha = vha->hw;
3d71644c 2895 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2896 unsigned long flags = 0;
2897 uint16_t data;
2898 uint32_t cnt;
2899 uint16_t mb[5];
73208dfd 2900 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2901
2902 /* Assume a failed state */
2903 rval = QLA_FUNCTION_FAILED;
2904
da4704d9
BVA		 2905 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n",
2906 &reg->flash_address);
1da177e4
LT		 2907
2908 spin_lock_irqsave(&ha->hardware_lock, flags);
2909
2910 /* Reset ISP chip. */
2911 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2912
2913 /*
2914 * We need to have a delay here since the card will not respond while
2915 * in reset causing an MCA on some architectures.
2916 */
2917 udelay(20);
2918 data = qla2x00_debounce_register(&reg->ctrl_status);
2919 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2920 udelay(5);
2921 data = RD_REG_WORD(&reg->ctrl_status);
2922 barrier();
2923 }
2924
2925 if (!cnt)
2926 goto chip_diag_failed;
2927
7c3df132
SK		 2928 ql_dbg(ql_dbg_init, vha, 0x007c,
2929 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2930
2931 /* Reset RISC processor. */
2932 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2933 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2934
2935 /* Workaround for QLA2312 PCI parity error */
2936 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2937 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2938 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2939 udelay(5);
2940 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2941 barrier();
1da177e4
LT		 2942 }
2943 } else
2944 udelay(10);
2945
2946 if (!cnt)
2947 goto chip_diag_failed;
2948
2949 /* Check product ID of chip */
5a68a1c2 2950 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 2951
2952 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2953 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2954 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2955 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2956 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2957 mb[3] != PROD_ID_3) {
7c3df132
SK		 2958 ql_log(ql_log_warn, vha, 0x0062,
2959 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2960 mb[1], mb[2], mb[3]);
1da177e4
LT		 2961
2962 goto chip_diag_failed;
2963 }
2964 ha->product_id[0] = mb[1];
2965 ha->product_id[1] = mb[2];
2966 ha->product_id[2] = mb[3];
2967 ha->product_id[3] = mb[4];
2968
2969 /* Adjust fw RISC transfer size */
73208dfd 2970 if (req->length > 1024)
1da177e4
LT		 2971 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2972 else
2973 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2974 req->length;
1da177e4
LT		 2975
2976 if (IS_QLA2200(ha) &&
2977 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2978 /* Limit firmware transfer size with a 2200A */
7c3df132 2979 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2980
ea5b6382 2981 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2982 ha->fw_transfer_size = 128;
2983 }
2984
2985 /* Wrap Incoming Mailboxes Test. */
2986 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2987
7c3df132 2988 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2989 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2990 if (rval)
2991 ql_log(ql_log_warn, vha, 0x0080,
2992 "Failed mailbox send register test.\n");
2993 else
1da177e4
LT		 2994 /* Flag a successful rval */
2995 rval = QLA_SUCCESS;
1da177e4
LT		 2996 spin_lock_irqsave(&ha->hardware_lock, flags);
2997
2998chip_diag_failed:
2999 if (rval)
7c3df132
SK		 3000 ql_log(ql_log_info, vha, 0x0081,
3001 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 3002
3003 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3004
3005 return (rval);
3006}
3007
0107109e
AV		 3008/**
3009 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2db6228d 3010 * @vha: HA context
0107109e
AV		 3011 *
3012 * Returns 0 on success.
3013 */
3014int
e315cd28 3015qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 3016{
3017 int rval;
e315cd28 3018 struct qla_hw_data *ha = vha->hw;
73208dfd 3019 struct req_que *req = ha->req_q_map[0];
0107109e 3020
7ec0effd 3021 if (IS_P3P_TYPE(ha))
a9083016
GM		 3022 return QLA_SUCCESS;
3023
73208dfd 3024 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 3025
e315cd28 3026 rval = qla2x00_mbx_reg_test(vha);
0107109e 3027 if (rval) {
7c3df132
SK		 3028 ql_log(ql_log_warn, vha, 0x0082,
3029 "Failed mailbox send register test.\n");
0107109e
AV		 3030 } else {
3031 /* Flag a successful rval */
3032 rval = QLA_SUCCESS;
3033 }
3034
3035 return rval;
3036}
3037
ad0a0b01
QT		 3038static void
3039qla2x00_alloc_offload_mem(scsi_qla_host_t *vha)
0107109e 3040{
a7a167bf 3041 int rval;
df613b96
AV		 3042 dma_addr_t tc_dma;
3043 void *tc;
e315cd28 3044 struct qla_hw_data *ha = vha->hw;
a7a167bf 3045
ad0a0b01 3046 if (ha->eft) {
7c3df132 3047 ql_dbg(ql_dbg_init, vha, 0x00bd,
ad0a0b01
QT		 3048 "%s: Offload Mem is already allocated.\n",
3049 __func__);
a7a167bf
AV		 3050 return;
3051 }
d4e3e04d 3052
ad0a0b01 3053 if (IS_FWI2_CAPABLE(ha)) {
df613b96 3054 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 3055 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
3056 !IS_QLA27XX(ha))
436a7b11 3057 goto try_eft;
df613b96 3058
f73cb695
CD		 3059 if (ha->fce)
3060 dma_free_coherent(&ha->pdev->dev,
3061 FCE_SIZE, ha->fce, ha->fce_dma);
3062
3063 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 3064 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
3065 GFP_KERNEL);
df613b96 3066 if (!tc) {
7c3df132
SK		 3067 ql_log(ql_log_warn, vha, 0x00be,
3068 "Unable to allocate (%d KB) for FCE.\n",
3069 FCE_SIZE / 1024);
17d98630 3070 goto try_eft;
df613b96
AV		 3071 }
3072
e315cd28 3073 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 3074 ha->fce_mb, &ha->fce_bufs);
3075 if (rval) {
7c3df132
SK		 3076 ql_log(ql_log_warn, vha, 0x00bf,
3077 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 3078 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
3079 tc_dma);
3080 ha->flags.fce_enabled = 0;
17d98630 3081 goto try_eft;
df613b96 3082 }
cfb0919c 3083 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 3084 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 3085
df613b96
AV		 3086 ha->flags.fce_enabled = 1;
3087 ha->fce_dma = tc_dma;
3088 ha->fce = tc;
f73cb695 3089
436a7b11 3090try_eft:
f73cb695
CD		 3091 if (ha->eft)
3092 dma_free_coherent(&ha->pdev->dev,
3093 EFT_SIZE, ha->eft, ha->eft_dma);
3094
436a7b11 3095 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 3096 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
3097 GFP_KERNEL);
436a7b11 3098 if (!tc) {
7c3df132
SK		 3099 ql_log(ql_log_warn, vha, 0x00c1,
3100 "Unable to allocate (%d KB) for EFT.\n",
3101 EFT_SIZE / 1024);
ad0a0b01 3102 goto eft_err;
436a7b11
AV		 3103 }
3104
e315cd28 3105 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 3106 if (rval) {
7c3df132
SK		 3107 ql_log(ql_log_warn, vha, 0x00c2,
3108 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 3109 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
3110 tc_dma);
ad0a0b01 3111 goto eft_err;
436a7b11 3112 }
cfb0919c 3113 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 3114 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11 3115
436a7b11
AV		 3116 ha->eft_dma = tc_dma;
3117 ha->eft = tc;
d4e3e04d 3118 }
f73cb695 3119
ad0a0b01
QT		 3120eft_err:
3121 return;
3122}
3123
3124void
3125qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
3126{
3127 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
3128 eft_size, fce_size, mq_size;
3129 struct qla_hw_data *ha = vha->hw;
3130 struct req_que *req = ha->req_q_map[0];
3131 struct rsp_que *rsp = ha->rsp_q_map[0];
3132 struct qla2xxx_fw_dump *fw_dump;
3133
3134 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
3135 req_q_size = rsp_q_size = 0;
3136
3137 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3138 fixed_size = sizeof(struct qla2100_fw_dump);
3139 } else if (IS_QLA23XX(ha)) {
3140 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
3141 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
3142 sizeof(uint16_t);
3143 } else if (IS_FWI2_CAPABLE(ha)) {
3144 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3145 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
3146 else if (IS_QLA81XX(ha))
3147 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
3148 else if (IS_QLA25XX(ha))
3149 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
3150 else
3151 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
3152
3153 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
3154 sizeof(uint32_t);
3155 if (ha->mqenable) {
3156 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
3157 mq_size = sizeof(struct qla2xxx_mq_chain);
3158 /*
3159 * Allocate maximum buffer size for all queues.
3160 * Resizing must be done at end-of-dump processing.
3161 */
3162 mq_size += ha->max_req_queues *
3163 (req->length * sizeof(request_t));
3164 mq_size += ha->max_rsp_queues *
3165 (rsp->length * sizeof(response_t));
3166 }
3167 if (ha->tgt.atio_ring)
3168 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
3169 /* Allocate memory for Fibre Channel Event Buffer. */
3170 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
3171 !IS_QLA27XX(ha))
3172 goto try_eft;
3173
3174 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
3175try_eft:
3176 ql_dbg(ql_dbg_init, vha, 0x00c3,
3177 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
3178 eft_size = EFT_SIZE;
3179 }
3180
f73cb695
CD		 3181 if (IS_QLA27XX(ha)) {
3182 if (!ha->fw_dump_template) {
3183 ql_log(ql_log_warn, vha, 0x00ba,
3184 "Failed missing fwdump template\n");
3185 return;
3186 }
3187 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
3188 ql_dbg(ql_dbg_init, vha, 0x00fa,
3189 "-> allocating fwdump (%x bytes)...\n", dump_size);
3190 goto allocate;
3191 }
3192
73208dfd
AC		 3193 req_q_size = req->length * sizeof(request_t);
3194 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 3195 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 3196 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 3197 ha->chain_offset = dump_size;
3198 dump_size += mq_size + fce_size;
d4e3e04d 3199
b945e777
QT		 3200 if (ha->exchoffld_buf)
3201 dump_size += sizeof(struct qla2xxx_offld_chain) +
3202 ha->exchoffld_size;
3203 if (ha->exlogin_buf)
3204 dump_size += sizeof(struct qla2xxx_offld_chain) +
3205 ha->exlogin_size;
3206
f73cb695 3207allocate:
ad0a0b01
QT		 3208 if (!ha->fw_dump_len || dump_size != ha->fw_dump_len) {
3209 fw_dump = vmalloc(dump_size);
3210 if (!fw_dump) {
3211 ql_log(ql_log_warn, vha, 0x00c4,
3212 "Unable to allocate (%d KB) for firmware dump.\n",
3213 dump_size / 1024);
3214 } else {
3215 if (ha->fw_dump)
3216 vfree(ha->fw_dump);
3217 ha->fw_dump = fw_dump;
3218
3219 ha->fw_dump_len = dump_size;
3220 ql_dbg(ql_dbg_init, vha, 0x00c5,
3221 "Allocated (%d KB) for firmware dump.\n",
3222 dump_size / 1024);
3223
3224 if (IS_QLA27XX(ha))
3225 return;
3226
3227 ha->fw_dump->signature[0] = 'Q';
3228 ha->fw_dump->signature[1] = 'L';
3229 ha->fw_dump->signature[2] = 'G';
3230 ha->fw_dump->signature[3] = 'C';
3231 ha->fw_dump->version = htonl(1);
3232
3233 ha->fw_dump->fixed_size = htonl(fixed_size);
3234 ha->fw_dump->mem_size = htonl(mem_size);
3235 ha->fw_dump->req_q_size = htonl(req_q_size);
3236 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
3237
3238 ha->fw_dump->eft_size = htonl(eft_size);
3239 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
3240 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
3241
3242 ha->fw_dump->header_size =
3243 htonl(offsetof(struct qla2xxx_fw_dump, isp));
a7a167bf 3244 }
a7a167bf 3245 }
0107109e
AV		 3246}
3247
18e7555a
AV		 3248static int
3249qla81xx_mpi_sync(scsi_qla_host_t *vha)
3250{
3251#define MPS_MASK 0xe0
3252 int rval;
3253 uint16_t dc;
3254 uint32_t dw;
18e7555a
AV		 3255
3256 if (!IS_QLA81XX(vha->hw))
3257 return QLA_SUCCESS;
3258
3259 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
3260 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3261 ql_log(ql_log_warn, vha, 0x0105,
3262 "Unable to acquire semaphore.\n");
18e7555a
AV		 3263 goto done;
3264 }
3265
3266 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
3267 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
3268 if (rval != QLA_SUCCESS) {
7c3df132 3269 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 3270 goto done_release;
3271 }
3272
3273 dc &= MPS_MASK;
3274 if (dc == (dw & MPS_MASK))
3275 goto done_release;
3276
3277 dw &= ~MPS_MASK;
3278 dw |= dc;
3279 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
3280 if (rval != QLA_SUCCESS) {
7c3df132 3281 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 3282 }
3283
3284done_release:
3285 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
3286 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3287 ql_log(ql_log_warn, vha, 0x006d,
3288 "Unable to release semaphore.\n");
18e7555a
AV		 3289 }
3290
3291done:
3292 return rval;
3293}
3294
8d93f550
CD		 3295int
3296qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
3297{
3298 /* Don't try to reallocate the array */
3299 if (req->outstanding_cmds)
3300 return QLA_SUCCESS;
3301
d7459527 3302 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 3303 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
3304 else {
03e8c680
QT		 3305 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
3306 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 3307 else
03e8c680 3308 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 3309 }
3310
6396bb22
KC		 3311 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3312 sizeof(srb_t *),
3313 GFP_KERNEL);
8d93f550
CD		 3314
3315 if (!req->outstanding_cmds) {
3316 /*
3317 * Try to allocate a minimal size just so we can get through
3318 * initialization.
3319 */
3320 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
6396bb22
KC		 3321 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3322 sizeof(srb_t *),
3323 GFP_KERNEL);
8d93f550
CD		 3324
3325 if (!req->outstanding_cmds) {
3326 ql_log(ql_log_fatal, NULL, 0x0126,
3327 "Failed to allocate memory for "
3328 "outstanding_cmds for req_que %p.\n", req);
3329 req->num_outstanding_cmds = 0;
3330 return QLA_FUNCTION_FAILED;
3331 }
3332 }
3333
3334 return QLA_SUCCESS;
3335}
3336
e4e3a2ce
QT		 3337#define PRINT_FIELD(_field, _flag, _str) { \
3338 if (a0->_field & _flag) {\
3339 if (p) {\
3340 strcat(ptr, "|");\
3341 ptr++;\
3342 leftover--;\
3343 } \
3344 len = snprintf(ptr, leftover, "%s", _str); \
3345 p = 1;\
3346 leftover -= len;\
3347 ptr += len; \
3348 } \
3349}
3350
3351static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
3352{
3353#define STR_LEN 64
3354 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
3355 u8 str[STR_LEN], *ptr, p;
3356 int leftover, len;
3357
3358 memset(str, 0, STR_LEN);
3359 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
3360 ql_dbg(ql_dbg_init, vha, 0x015a,
3361 "SFP MFG Name: %s\n", str);
3362
3363 memset(str, 0, STR_LEN);
3364 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
3365 ql_dbg(ql_dbg_init, vha, 0x015c,
3366 "SFP Part Name: %s\n", str);
3367
3368 /* media */
3369 memset(str, 0, STR_LEN);
3370 ptr = str;
3371 leftover = STR_LEN;
3372 p = len = 0;
3373 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
3374 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
3375 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
3376 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
3377 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
3378 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
3379 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
3380 ql_dbg(ql_dbg_init, vha, 0x0160,
3381 "SFP Media: %s\n", str);
3382
3383 /* link length */
3384 memset(str, 0, STR_LEN);
3385 ptr = str;
3386 leftover = STR_LEN;
3387 p = len = 0;
3388 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
3389 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
3390 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
3391 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
3392 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
3393 ql_dbg(ql_dbg_init, vha, 0x0196,
3394 "SFP Link Length: %s\n", str);
3395
3396 memset(str, 0, STR_LEN);
3397 ptr = str;
3398 leftover = STR_LEN;
3399 p = len = 0;
3400 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
3401 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
3402 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
3403 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
3404 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
3405 ql_dbg(ql_dbg_init, vha, 0x016e,
3406 "SFP FC Link Tech: %s\n", str);
3407
3408 if (a0->length_km)
3409 ql_dbg(ql_dbg_init, vha, 0x016f,
3410 "SFP Distant: %d km\n", a0->length_km);
3411 if (a0->length_100m)
3412 ql_dbg(ql_dbg_init, vha, 0x0170,
3413 "SFP Distant: %d m\n", a0->length_100m*100);
3414 if (a0->length_50um_10m)
3415 ql_dbg(ql_dbg_init, vha, 0x0189,
3416 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
3417 if (a0->length_62um_10m)
3418 ql_dbg(ql_dbg_init, vha, 0x018a,
3419 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
3420 if (a0->length_om4_10m)
3421 ql_dbg(ql_dbg_init, vha, 0x0194,
3422 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
3423 if (a0->length_om3_10m)
3424 ql_dbg(ql_dbg_init, vha, 0x0195,
3425 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
3426}
3427
3428
3429/*
3430 * Return Code:
3431 * QLA_SUCCESS: no action
3432 * QLA_INTERFACE_ERROR: SFP is not there.
3433 * QLA_FUNCTION_FAILED: detected New SFP
3434 */
3435int
3436qla24xx_detect_sfp(scsi_qla_host_t *vha)
3437{
3438 int rc = QLA_SUCCESS;
3439 struct sff_8247_a0 *a;
3440 struct qla_hw_data *ha = vha->hw;
3441
3442 if (!AUTO_DETECT_SFP_SUPPORT(vha))
3443 goto out;
3444
3445 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
3446 if (rc)
3447 goto out;
3448
3449 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
3450 qla2xxx_print_sfp_info(vha);
3451
3452 if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
3453 /* long range */
3454 ha->flags.detected_lr_sfp = 1;
3455
3456 if (a->length_km > 5 || a->length_100m > 50)
3457 ha->long_range_distance = LR_DISTANCE_10K;
3458 else
3459 ha->long_range_distance = LR_DISTANCE_5K;
3460
3461 if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
3462 ql_dbg(ql_dbg_async, vha, 0x507b,
3463 "Detected Long Range SFP.\n");
3464 } else {
3465 /* short range */
3466 ha->flags.detected_lr_sfp = 0;
3467 if (ha->flags.using_lr_setting)
3468 ql_dbg(ql_dbg_async, vha, 0x5084,
3469 "Detected Short Range SFP.\n");
3470 }
3471
3472 if (!vha->flags.init_done)
3473 rc = QLA_SUCCESS;
3474out:
3475 return rc;
3476}
3477
1da177e4
LT		 3478/**
3479 * qla2x00_setup_chip() - Load and start RISC firmware.
2db6228d 3480 * @vha: HA context
1da177e4
LT		 3481 *
3482 * Returns 0 on success.
3483 */
3484static int
e315cd28 3485qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 3486{
0107109e
AV		 3487 int rval;
3488 uint32_t srisc_address = 0;
e315cd28 3489 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 3490 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3491 unsigned long flags;
dda772e8 3492 uint16_t fw_major_version;
3db0652e 3493
7ec0effd 3494 if (IS_P3P_TYPE(ha)) {
a9083016 3495 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 3496 if (rval == QLA_SUCCESS) {
3497 qla2x00_stop_firmware(vha);
a9083016 3498 goto enable_82xx_npiv;
14e303d9 3499 } else
b963752f 3500 goto failed;
a9083016
GM		 3501 }
3502
3db0652e
AV		 3503 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3504 /* Disable SRAM, Instruction RAM and GP RAM parity. */
3505 spin_lock_irqsave(&ha->hardware_lock, flags);
3506 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
3507 RD_REG_WORD(&reg->hccr);
3508 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3509 }
1da177e4 3510
18e7555a
AV		 3511 qla81xx_mpi_sync(vha);
3512
1da177e4 3513 /* Load firmware sequences */
e315cd28 3514 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 3515 if (rval == QLA_SUCCESS) {
7c3df132
SK		 3516 ql_dbg(ql_dbg_init, vha, 0x00c9,
3517 "Verifying Checksum of loaded RISC code.\n");
1da177e4 3518
e315cd28 3519 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 3520 if (rval == QLA_SUCCESS) {
3521 /* Start firmware execution. */
7c3df132
SK		 3522 ql_dbg(ql_dbg_init, vha, 0x00ca,
3523 "Starting firmware.\n");
1da177e4 3524
b0d6cabd
HM		 3525 if (ql2xexlogins)
3526 ha->flags.exlogins_enabled = 1;
3527
99e1b683 3528 if (qla_is_exch_offld_enabled(vha))
2f56a7f1
HM		 3529 ha->flags.exchoffld_enabled = 1;
3530
e315cd28 3531 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 3532 /* Retrieve firmware information. */
dda772e8 3533 if (rval == QLA_SUCCESS) {
e4e3a2ce
QT		 3534 qla24xx_detect_sfp(vha);
3535
8b4673ba
QT		 3536 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) &&
3537 (ha->zio_mode == QLA_ZIO_MODE_6))
3538 qla27xx_set_zio_threshold(vha,
3539 ha->last_zio_threshold);
3540
b0d6cabd
HM		 3541 rval = qla2x00_set_exlogins_buffer(vha);
3542 if (rval != QLA_SUCCESS)
3543 goto failed;
3544
2f56a7f1
HM		 3545 rval = qla2x00_set_exchoffld_buffer(vha);
3546 if (rval != QLA_SUCCESS)
3547 goto failed;
3548
a9083016 3549enable_82xx_npiv:
dda772e8 3550 fw_major_version = ha->fw_major_version;
7ec0effd 3551 if (IS_P3P_TYPE(ha))
3173167f 3552 qla82xx_check_md_needed(vha);
6246b8a1
GM		 3553 else
3554 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 3555 if (rval != QLA_SUCCESS)
3556 goto failed;
2c3dfe3f 3557 ha->flags.npiv_supported = 0;
e315cd28 3558 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 3559 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 3560 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 3561 if ((!ha->max_npiv_vports) ||
3562 ((ha->max_npiv_vports + 1) %
eb66dc60 3563 MIN_MULTI_ID_FABRIC))
4d0ea247 3564 ha->max_npiv_vports =
eb66dc60 3565 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 3566 }
03e8c680 3567 qla2x00_get_resource_cnts(vha);
d743de66 3568
8d93f550
CD		 3569 /*
3570 * Allocate the array of outstanding commands
3571 * now that we know the firmware resources.
3572 */
3573 rval = qla2x00_alloc_outstanding_cmds(ha,
3574 vha->req);
3575 if (rval != QLA_SUCCESS)
3576 goto failed;
3577
ad0a0b01
QT		 3578 if (!fw_major_version && !(IS_P3P_TYPE(ha)))
3579 qla2x00_alloc_offload_mem(vha);
3580
3581 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
08de2844 3582 qla2x00_alloc_fw_dump(vha);
ad0a0b01 3583
3b6e5b9d
CD		 3584 } else {
3585 goto failed;
1da177e4
LT		 3586 }
3587 } else {
7c3df132
SK		 3588 ql_log(ql_log_fatal, vha, 0x00cd,
3589 "ISP Firmware failed checksum.\n");
3590 goto failed;
1da177e4 3591 }
c74d88a4
AV		 3592 } else
3593 goto failed;
1da177e4 3594
3db0652e
AV		 3595 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3596 /* Enable proper parity. */
3597 spin_lock_irqsave(&ha->hardware_lock, flags);
3598 if (IS_QLA2300(ha))
3599 /* SRAM parity */
3600 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
3601 else
3602 /* SRAM, Instruction RAM and GP RAM parity */
3603 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
3604 RD_REG_WORD(&reg->hccr);
3605 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3606 }
3607
f3982d89
CD		 3608 if (IS_QLA27XX(ha))
3609 ha->flags.fac_supported = 1;
3610 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 3611 uint32_t size;
3612
3613 rval = qla81xx_fac_get_sector_size(vha, &size);
3614 if (rval == QLA_SUCCESS) {
3615 ha->flags.fac_supported = 1;
3616 ha->fdt_block_size = size << 2;
3617 } else {
7c3df132 3618 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 3619 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3620 ha->fw_major_version, ha->fw_minor_version,
3621 ha->fw_subminor_version);
1ca60e3b 3622
f73cb695 3623 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 3624 ha->flags.fac_supported = 0;
3625 rval = QLA_SUCCESS;
3626 }
1d2874de
JC		 3627 }
3628 }
ca9e9c3e 3629failed:
1da177e4 3630 if (rval) {
7c3df132
SK		 3631 ql_log(ql_log_fatal, vha, 0x00cf,
3632 "Setup chip ****FAILED****.\n");
1da177e4
LT		 3633 }
3634
3635 return (rval);
3636}
3637
3638/**
3639 * qla2x00_init_response_q_entries() - Initializes response queue entries.
2db6228d 3640 * @rsp: response queue
1da177e4
LT		 3641 *
3642 * Beginning of request ring has initialization control block already built
3643 * by nvram config routine.
3644 *
3645 * Returns 0 on success.
3646 */
73208dfd
AC		 3647void
3648qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 3649{
3650 uint16_t cnt;
3651 response_t *pkt;
3652
2afa19a9
AC		 3653 rsp->ring_ptr = rsp->ring;
3654 rsp->ring_index = 0;
3655 rsp->status_srb = NULL;
e315cd28
AC		 3656 pkt = rsp->ring_ptr;
3657 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 3658 pkt->signature = RESPONSE_PROCESSED;
3659 pkt++;
3660 }
1da177e4
LT		 3661}
3662
3663/**
3664 * qla2x00_update_fw_options() - Read and process firmware options.
2db6228d 3665 * @vha: HA context
1da177e4
LT		 3666 *
3667 * Returns 0 on success.
3668 */
abbd8870 3669void
e315cd28 3670qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 3671{
3672 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 3673 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3674
3675 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 3676 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 3677
3678 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3679 return;
3680
3681 /* Serial Link options. */
7c3df132
SK		 3682 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3683 "Serial link options.\n");
3684 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
3685 (uint8_t *)&ha->fw_seriallink_options,
3686 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 3687
3688 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3689 if (ha->fw_seriallink_options[3] & BIT_2) {
3690 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3691
3692 /* 1G settings */
3693 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3694 emphasis = (ha->fw_seriallink_options[2] &
3695 (BIT_4 | BIT_3)) >> 3;
3696 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 3697 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3698 rx_sens = (ha->fw_seriallink_options[0] &
3699 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3700 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3701 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3702 if (rx_sens == 0x0)
3703 rx_sens = 0x3;
3704 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3705 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3706 ha->fw_options[10] |= BIT_5 |
3707 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3708 (tx_sens & (BIT_1 | BIT_0));
3709
3710 /* 2G settings */
3711 swing = (ha->fw_seriallink_options[2] &
3712 (BIT_7 | BIT_6 | BIT_5)) >> 5;
3713 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
3714 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 3715 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3716 rx_sens = (ha->fw_seriallink_options[1] &
3717 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3718 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
3719 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3720 if (rx_sens == 0x0)
3721 rx_sens = 0x3;
3722 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
3723 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3724 ha->fw_options[11] |= BIT_5 |
3725 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3726 (tx_sens & (BIT_1 | BIT_0));
3727 }
3728
3729 /* FCP2 options. */
3730 /* Return command IOCBs without waiting for an ABTS to complete. */
3731 ha->fw_options[3] |= BIT_13;
3732
3733 /* LED scheme. */
3734 if (ha->flags.enable_led_scheme)
3735 ha->fw_options[2] |= BIT_12;
3736
48c02fde 3737 /* Detect ISP6312. */
3738 if (IS_QLA6312(ha))
3739 ha->fw_options[2] |= BIT_13;
3740
088d09d4
GM		 3741 /* Set Retry FLOGI in case of P2P connection */
3742 if (ha->operating_mode == P2P) {
3743 ha->fw_options[2] |= BIT_3;
3744 ql_dbg(ql_dbg_disc, vha, 0x2100,
3745 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3746 __func__, ha->fw_options[2]);
3747 }
3748
1da177e4 3749 /* Update firmware options. */
e315cd28 3750 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 3751}
3752
0107109e 3753void
e315cd28 3754qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 3755{
3756 int rval;
e315cd28 3757 struct qla_hw_data *ha = vha->hw;
0107109e 3758
7ec0effd 3759 if (IS_P3P_TYPE(ha))
a9083016
GM		 3760 return;
3761
f198cafa
HM		 3762 /* Hold status IOCBs until ABTS response received. */
3763 if (ql2xfwholdabts)
3764 ha->fw_options[3] |= BIT_12;
3765
088d09d4
GM		 3766 /* Set Retry FLOGI in case of P2P connection */
3767 if (ha->operating_mode == P2P) {
3768 ha->fw_options[2] |= BIT_3;
3769 ql_dbg(ql_dbg_disc, vha, 0x2101,
3770 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3771 __func__, ha->fw_options[2]);
3772 }
3773
41dc529a 3774 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff
QT		 3775 if (ql2xmvasynctoatio &&
3776 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
41dc529a
QT		 3777 if (qla_tgt_mode_enabled(vha) ||
3778 qla_dual_mode_enabled(vha))
3779 ha->fw_options[2] |= BIT_11;
3780 else
3781 ha->fw_options[2] &= ~BIT_11;
3782 }
3783
f7e761f5
QT		 3784 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3785 /*
3786 * Tell FW to track each exchange to prevent
3787 * driver from using stale exchange.
3788 */
3789 if (qla_tgt_mode_enabled(vha) ||
3790 qla_dual_mode_enabled(vha))
3791 ha->fw_options[2] |= BIT_4;
3792 else
3793 ha->fw_options[2] &= ~BIT_4;
9ecf0b0d
QT		 3794
3795 /* Reserve 1/2 of emergency exchanges for ELS.*/
3796 if (qla2xuseresexchforels)
3797 ha->fw_options[2] |= BIT_8;
3798 else
3799 ha->fw_options[2] &= ~BIT_8;
f7e761f5
QT		 3800 }
3801
83548fe2
QT		 3802 ql_dbg(ql_dbg_init, vha, 0x00e8,
3803 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3804 __func__, ha->fw_options[1], ha->fw_options[2],
3805 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 3806
3807 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
3808 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 3809
0107109e 3810 /* Update Serial Link options. */
f94097ed 3811 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3812 return;
3813
e315cd28 3814 rval = qla2x00_set_serdes_params(vha,
f94097ed 3815 le16_to_cpu(ha->fw_seriallink_options24[1]),
3816 le16_to_cpu(ha->fw_seriallink_options24[2]),
3817 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3818 if (rval != QLA_SUCCESS) {
7c3df132 3819 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3820 "Unable to update Serial Link options (%x).\n", rval);
3821 }
3822}
3823
abbd8870 3824void
e315cd28 3825qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3826{
e315cd28 3827 struct qla_hw_data *ha = vha->hw;
3d71644c 3828 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3829 struct req_que *req = ha->req_q_map[0];
3830 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3831
3832 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3833 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3834 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3835 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3836 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
3837 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3838 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3839 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3840 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 3841
3842 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3843 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3844 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3845 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3846 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3847}
3848
0107109e 3849void
e315cd28 3850qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3851{
e315cd28 3852 struct qla_hw_data *ha = vha->hw;
118e2ef9 3853 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3854 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3855 struct qla_msix_entry *msix;
0107109e 3856 struct init_cb_24xx *icb;
73208dfd
AC		 3857 uint16_t rid = 0;
3858 struct req_que *req = ha->req_q_map[0];
3859 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3860
6246b8a1 3861 /* Setup ring parameters in initialization control block. */
0107109e 3862 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3863 icb->request_q_outpointer = cpu_to_le16(0);
3864 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3865 icb->request_q_length = cpu_to_le16(req->length);
3866 icb->response_q_length = cpu_to_le16(rsp->length);
3867 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3868 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3869 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3870 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3871
2d70c103 3872 /* Setup ATIO queue dma pointers for target mode */
ad950360 3873 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3874 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3875 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3876 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3877
7c6300e3 3878 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3879 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3880
f73cb695 3881 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3882 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3883 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3884 if (ha->flags.msix_enabled) {
3885 msix = &ha->msix_entries[1];
83548fe2 3886 ql_dbg(ql_dbg_init, vha, 0x0019,
7c3df132
SK		 3887 "Registering vector 0x%x for base que.\n",
3888 msix->entry);
73208dfd
AC		 3889 icb->msix = cpu_to_le16(msix->entry);
3890 }
3891 /* Use alternate PCI bus number */
3892 if (MSB(rid))
ad950360 3893 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3894 /* Use alternate PCI devfn */
3895 if (LSB(rid))
ad950360 3896 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3897
3155754a 3898 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3899 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3900 (ha->flags.msix_enabled)) {
ad950360 3901 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3902 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3903 ql_dbg(ql_dbg_init, vha, 0x00fe,
3904 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3905 } else {
ad950360 3906 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3907 }
ad950360 3908 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3909
3910 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3911 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3912 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3913 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3914 } else {
3915 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3916 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3917 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3918 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3919 }
aa230bc5 3920 qlt_24xx_config_rings(vha);
2d70c103 3921
73208dfd
AC		 3922 /* PCI posting */
3923 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3924}
3925
1da177e4
LT		 3926/**
3927 * qla2x00_init_rings() - Initializes firmware.
2db6228d 3928 * @vha: HA context
1da177e4
LT		 3929 *
3930 * Beginning of request ring has initialization control block already built
3931 * by nvram config routine.
3932 *
3933 * Returns 0 on success.
3934 */
8ae6d9c7 3935int
e315cd28 3936qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3937{
3938 int rval;
3939 unsigned long flags = 0;
29bdccbe 3940 int cnt, que;
e315cd28 3941 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3942 struct req_que *req;
3943 struct rsp_que *rsp;
2c3dfe3f
SJ		 3944 struct mid_init_cb_24xx *mid_init_cb =
3945 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3946
3947 spin_lock_irqsave(&ha->hardware_lock, flags);
3948
3949 /* Clear outstanding commands array. */
2afa19a9 3950 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3951 req = ha->req_q_map[que];
cb43285f 3952 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3953 continue;
7c6300e3
JC		 3954 req->out_ptr = (void *)(req->ring + req->length);
3955 *req->out_ptr = 0;
8d93f550 3956 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3957 req->outstanding_cmds[cnt] = NULL;
1da177e4 3958
2afa19a9 3959 req->current_outstanding_cmd = 1;
1da177e4 3960
29bdccbe
AC		 3961 /* Initialize firmware. */
3962 req->ring_ptr = req->ring;
3963 req->ring_index = 0;
3964 req->cnt = req->length;
3965 }
1da177e4 3966
2afa19a9 3967 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3968 rsp = ha->rsp_q_map[que];
cb43285f 3969 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3970 continue;
7c6300e3
JC		 3971 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3972 *rsp->in_ptr = 0;
29bdccbe 3973 /* Initialize response queue entries */
8ae6d9c7
GM		 3974 if (IS_QLAFX00(ha))
3975 qlafx00_init_response_q_entries(rsp);
3976 else
3977 qla2x00_init_response_q_entries(rsp);
29bdccbe 3978 }
1da177e4 3979
2d70c103
NB		 3980 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3981 ha->tgt.atio_ring_index = 0;
3982 /* Initialize ATIO queue entries */
3983 qlt_init_atio_q_entries(vha);
3984
e315cd28 3985 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3986
3987 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3988
8ae6d9c7
GM		 3989 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3990
3991 if (IS_QLAFX00(ha)) {
3992 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3993 goto next_check;
3994 }
3995
1da177e4 3996 /* Update any ISP specific firmware options before initialization. */
e315cd28 3997 ha->isp_ops->update_fw_options(vha);
1da177e4 3998
605aa2bc 3999 if (ha->flags.npiv_supported) {
45980cc2 4000 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 4001 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 4002 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 4003 }
4004
24a08138 4005 if (IS_FWI2_CAPABLE(ha)) {
ad950360 4006 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 4007 mid_init_cb->init_cb.execution_throttle =
03e8c680 4008 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 4009 ha->flags.dport_enabled =
4010 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
4011 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
4012 (ha->flags.dport_enabled) ? "enabled" : "disabled");
4013 /* FA-WWPN Status */
2486c627 4014 ha->flags.fawwpn_enabled =
40f3862b 4015 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
83548fe2 4016 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
2486c627 4017 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 4018 }
2c3dfe3f 4019
e315cd28 4020 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 4021next_check:
1da177e4 4022 if (rval) {
7c3df132
SK		 4023 ql_log(ql_log_fatal, vha, 0x00d2,
4024 "Init Firmware **** FAILED ****.\n");
1da177e4 4025 } else {
7c3df132
SK		 4026 ql_dbg(ql_dbg_init, vha, 0x00d3,
4027 "Init Firmware -- success.\n");
4b60c827 4028 QLA_FW_STARTED(ha);
1da177e4
LT		 4029 }
4030
4031 return (rval);
4032}
4033
4034/**
4035 * qla2x00_fw_ready() - Waits for firmware ready.
2db6228d 4036 * @vha: HA context
1da177e4
LT		 4037 *
4038 * Returns 0 on success.
4039 */
4040static int
e315cd28 4041qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 4042{
4043 int rval;
4d4df193 4044 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 4045 uint16_t min_wait; /* Minimum wait time if loop is down */
4046 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 4047 uint16_t state[6];
e315cd28 4048 struct qla_hw_data *ha = vha->hw;
1da177e4 4049
8ae6d9c7
GM		 4050 if (IS_QLAFX00(vha->hw))
4051 return qlafx00_fw_ready(vha);
4052
1da177e4
LT		 4053 rval = QLA_SUCCESS;
4054
33461491
CD		 4055 /* Time to wait for loop down */
4056 if (IS_P3P_TYPE(ha))
4057 min_wait = 30;
4058 else
4059 min_wait = 20;
1da177e4
LT		 4060
4061 /*
4062 * Firmware should take at most one RATOV to login, plus 5 seconds for
4063 * our own processing.
4064 */
4065 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
4066 wait_time = min_wait;
4067 }
4068
4069 /* Min wait time if loop down */
4070 mtime = jiffies + (min_wait * HZ);
4071
4072 /* wait time before firmware ready */
4073 wtime = jiffies + (wait_time * HZ);
4074
4075 /* Wait for ISP to finish LIP */
e315cd28 4076 if (!vha->flags.init_done)
7c3df132
SK		 4077 ql_log(ql_log_info, vha, 0x801e,
4078 "Waiting for LIP to complete.\n");
1da177e4
LT		 4079
4080 do {
5b939038 4081 memset(state, -1, sizeof(state));
e315cd28 4082 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 4083 if (rval == QLA_SUCCESS) {
4d4df193 4084 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 4085 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 4086 }
4d4df193 4087 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 4088 ql_dbg(ql_dbg_taskm, vha, 0x801f,
4089 "fw_state=%x 84xx=%x.\n", state[0],
4090 state[2]);
4d4df193
HK		 4091 if ((state[2] & FSTATE_LOGGED_IN) &&
4092 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 4093 ql_dbg(ql_dbg_taskm, vha, 0x8028,
4094 "Sending verify iocb.\n");
4d4df193
HK		 4095
4096 cs84xx_time = jiffies;
e315cd28 4097 rval = qla84xx_init_chip(vha);
7c3df132
SK		 4098 if (rval != QLA_SUCCESS) {
4099 ql_log(ql_log_warn,
cfb0919c 4100 vha, 0x8007,
7c3df132 4101 "Init chip failed.\n");
4d4df193 4102 break;
7c3df132 4103 }
4d4df193
HK		 4104
4105 /* Add time taken to initialize. */
4106 cs84xx_time = jiffies - cs84xx_time;
4107 wtime += cs84xx_time;
4108 mtime += cs84xx_time;
cfb0919c 4109 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 4110 "Increasing wait time by %ld. "
4111 "New time %ld.\n", cs84xx_time,
4112 wtime);
4d4df193
HK		 4113 }
4114 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 4115 ql_dbg(ql_dbg_taskm, vha, 0x8037,
4116 "F/W Ready - OK.\n");
1da177e4 4117
e315cd28 4118 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 4119 &ha->login_timeout, &ha->r_a_tov);
4120
4121 rval = QLA_SUCCESS;
4122 break;
4123 }
4124
4125 rval = QLA_FUNCTION_FAILED;
4126
e315cd28 4127 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 4128 state[0] != FSTATE_READY) {
1da177e4 4129 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 4130 * other than Wait for Login.
4131 */
1da177e4 4132 if (time_after_eq(jiffies, mtime)) {
7c3df132 4133 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 4134 "Cable is unplugged...\n");
4135
e315cd28 4136 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 4137 break;
4138 }
4139 }
4140 } else {
4141 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 4142 if (time_after_eq(jiffies, mtime) ||
7190575f 4143 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 4144 break;
4145 }
4146
4147 if (time_after_eq(jiffies, wtime))
4148 break;
4149
4150 /* Delay for a while */
4151 msleep(500);
1da177e4
LT		 4152 } while (1);
4153
7c3df132 4154 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 4155 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
4156 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 4157
cfb0919c 4158 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 4159 ql_log(ql_log_warn, vha, 0x803b,
4160 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 4161 }
4162
4163 return (rval);
4164}
4165
4166/*
4167* qla2x00_configure_hba
4168* Setup adapter context.
4169*
4170* Input:
4171* ha = adapter state pointer.
4172*
4173* Returns:
4174* 0 = success
4175*
4176* Context:
4177* Kernel context.
4178*/
4179static int
e315cd28 4180qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 4181{
4182 int rval;
4183 uint16_t loop_id;
4184 uint16_t topo;
2c3dfe3f 4185 uint16_t sw_cap;
1da177e4
LT		 4186 uint8_t al_pa;
4187 uint8_t area;
4188 uint8_t domain;
4189 char connect_type[22];
e315cd28 4190 struct qla_hw_data *ha = vha->hw;
61e1b269 4191 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 4192 port_id_t id;
9d1aa4e1 4193 unsigned long flags;
1da177e4
LT		 4194
4195 /* Get host addresses. */
e315cd28 4196 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 4197 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 4198 if (rval != QLA_SUCCESS) {
e315cd28 4199 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 4200 IS_CNA_CAPABLE(ha) ||
33135aa2 4201 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 4202 ql_dbg(ql_dbg_disc, vha, 0x2008,
4203 "Loop is in a transition state.\n");
33135aa2 4204 } else {
7c3df132
SK		 4205 ql_log(ql_log_warn, vha, 0x2009,
4206 "Unable to get host loop ID.\n");
61e1b269
JC		 4207 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
4208 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
4209 ql_log(ql_log_warn, vha, 0x1151,
4210 "Doing link init.\n");
4211 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
4212 return rval;
4213 }
e315cd28 4214 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 4215 }
1da177e4
LT		 4216 return (rval);
4217 }
4218
4219 if (topo == 4) {
7c3df132
SK		 4220 ql_log(ql_log_info, vha, 0x200a,
4221 "Cannot get topology - retrying.\n");
1da177e4
LT		 4222 return (QLA_FUNCTION_FAILED);
4223 }
4224
e315cd28 4225 vha->loop_id = loop_id;
1da177e4
LT		 4226
4227 /* initialize */
4228 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
4229 ha->operating_mode = LOOP;
2c3dfe3f 4230 ha->switch_cap = 0;
1da177e4
LT		 4231
4232 switch (topo) {
4233 case 0:
7c3df132 4234 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 4235 ha->current_topology = ISP_CFG_NL;
4236 strcpy(connect_type, "(Loop)");
4237 break;
4238
4239 case 1:
7c3df132 4240 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 4241 ha->switch_cap = sw_cap;
1da177e4
LT		 4242 ha->current_topology = ISP_CFG_FL;
4243 strcpy(connect_type, "(FL_Port)");
4244 break;
4245
4246 case 2:
7c3df132 4247 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 4248 ha->operating_mode = P2P;
4249 ha->current_topology = ISP_CFG_N;
4250 strcpy(connect_type, "(N_Port-to-N_Port)");
4251 break;
4252
4253 case 3:
7c3df132 4254 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 4255 ha->switch_cap = sw_cap;
1da177e4
LT		 4256 ha->operating_mode = P2P;
4257 ha->current_topology = ISP_CFG_F;
4258 strcpy(connect_type, "(F_Port)");
4259 break;
4260
4261 default:
7c3df132
SK		 4262 ql_dbg(ql_dbg_disc, vha, 0x200f,
4263 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 4264 ha->current_topology = ISP_CFG_NL;
4265 strcpy(connect_type, "(Loop)");
4266 break;
4267 }
4268
4269 /* Save Host port and loop ID. */
4270 /* byte order - Big Endian */
482c9dc7
QT		 4271 id.b.domain = domain;
4272 id.b.area = area;
4273 id.b.al_pa = al_pa;
4274 id.b.rsvd_1 = 0;
9d1aa4e1 4275 spin_lock_irqsave(&ha->hardware_lock, flags);
8777e431
QT		 4276 if (!(topo == 2 && ha->flags.n2n_bigger))
4277 qlt_update_host_map(vha, id);
9d1aa4e1 4278 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2d70c103 4279
e315cd28 4280 if (!vha->flags.init_done)
7c3df132
SK		 4281 ql_log(ql_log_info, vha, 0x2010,
4282 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 4283 connect_type, vha->loop_id);
1da177e4 4284
1da177e4
LT		 4285 return(rval);
4286}
4287
a9083016 4288inline void
e315cd28
AC		 4289qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
4290 char *def)
9bb9fcf2
AV		 4291{
4292 char *st, *en;
4293 uint16_t index;
e315cd28 4294 struct qla_hw_data *ha = vha->hw;
ab671149 4295 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 4296 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 4297
4298 if (memcmp(model, BINZERO, len) != 0) {
4299 strncpy(ha->model_number, model, len);
4300 st = en = ha->model_number;
4301 en += len - 1;
4302 while (en > st) {
4303 if (*en != 0x20 && *en != 0x00)
4304 break;
4305 *en-- = '\0';
4306 }
4307
4308 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4309 if (use_tbl &&
4310 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 4311 index < QLA_MODEL_NAMES)
1ee27146
JC		 4312 strncpy(ha->model_desc,
4313 qla2x00_model_name[index * 2 + 1],
4314 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4315 } else {
4316 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 4317 if (use_tbl &&
4318 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 4319 index < QLA_MODEL_NAMES) {
4320 strcpy(ha->model_number,
4321 qla2x00_model_name[index * 2]);
1ee27146
JC		 4322 strncpy(ha->model_desc,
4323 qla2x00_model_name[index * 2 + 1],
4324 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 4325 } else {
4326 strcpy(ha->model_number, def);
4327 }
4328 }
1ee27146 4329 if (IS_FWI2_CAPABLE(ha))
e315cd28 4330 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 4331 sizeof(ha->model_desc));
9bb9fcf2
AV		 4332}
4333
4e08df3f
DM		 4334/* On sparc systems, obtain port and node WWN from firmware
4335 * properties.
4336 */
e315cd28 4337static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 4338{
4339#ifdef CONFIG_SPARC
e315cd28 4340 struct qla_hw_data *ha = vha->hw;
4e08df3f 4341 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4342 struct device_node *dp = pci_device_to_OF_node(pdev);
4343 const u8 *val;
4e08df3f
DM		 4344 int len;
4345
4346 val = of_get_property(dp, "port-wwn", &len);
4347 if (val && len >= WWN_SIZE)
4348 memcpy(nv->port_name, val, WWN_SIZE);
4349
4350 val = of_get_property(dp, "node-wwn", &len);
4351 if (val && len >= WWN_SIZE)
4352 memcpy(nv->node_name, val, WWN_SIZE);
4353#endif
4354}
4355
1da177e4
LT		 4356/*
4357* NVRAM configuration for ISP 2xxx
4358*
4359* Input:
4360* ha = adapter block pointer.
4361*
4362* Output:
4363* initialization control block in response_ring
4364* host adapters parameters in host adapter block
4365*
4366* Returns:
4367* 0 = success.
4368*/
abbd8870 4369int
e315cd28 4370qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 4371{
4e08df3f 4372 int rval;
0107109e
AV		 4373 uint8_t chksum = 0;
4374 uint16_t cnt;
4375 uint8_t *dptr1, *dptr2;
e315cd28 4376 struct qla_hw_data *ha = vha->hw;
0107109e 4377 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 4378 nvram_t *nv = ha->nvram;
4379 uint8_t *ptr = ha->nvram;
3d71644c 4380 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4381
4e08df3f
DM		 4382 rval = QLA_SUCCESS;
4383
1da177e4 4384 /* Determine NVRAM starting address. */
0107109e 4385 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 4386 ha->nvram_base = 0;
4387 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
4388 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
4389 ha->nvram_base = 0x80;
4390
4391 /* Get NVRAM data and calculate checksum. */
e315cd28 4392 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 4393 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
4394 chksum += *ptr++;
1da177e4 4395
7c3df132
SK		 4396 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
4397 "Contents of NVRAM.\n");
4398 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
4399 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 4400
4401 /* Bad NVRAM data, set defaults parameters. */
4402 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
4403 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
4404 /* Reset NVRAM data. */
7c3df132 4405 ql_log(ql_log_warn, vha, 0x0064,
9e336520 4406 "Inconsistent NVRAM "
7c3df132
SK		 4407 "detected: checksum=0x%x id=%c version=0x%x.\n",
4408 chksum, nv->id[0], nv->nvram_version);
4409 ql_log(ql_log_warn, vha, 0x0065,
4410 "Falling back to "
4411 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 4412
4413 /*
4414 * Set default initialization control block.
4415 */
4416 memset(nv, 0, ha->nvram_size);
4417 nv->parameter_block_version = ICB_VERSION;
4418
4419 if (IS_QLA23XX(ha)) {
4420 nv->firmware_options[0] = BIT_2 | BIT_1;
4421 nv->firmware_options[1] = BIT_7 | BIT_5;
4422 nv->add_firmware_options[0] = BIT_5;
4423 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4424 nv->frame_payload_size = 2048;
4e08df3f
DM		 4425 nv->special_options[1] = BIT_7;
4426 } else if (IS_QLA2200(ha)) {
4427 nv->firmware_options[0] = BIT_2 | BIT_1;
4428 nv->firmware_options[1] = BIT_7 | BIT_5;
4429 nv->add_firmware_options[0] = BIT_5;
4430 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 4431 nv->frame_payload_size = 1024;
4e08df3f
DM		 4432 } else if (IS_QLA2100(ha)) {
4433 nv->firmware_options[0] = BIT_3 | BIT_1;
4434 nv->firmware_options[1] = BIT_5;
98aee70d 4435 nv->frame_payload_size = 1024;
4e08df3f
DM		 4436 }
4437
ad950360
BVA		 4438 nv->max_iocb_allocation = cpu_to_le16(256);
4439 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 4440 nv->retry_count = 8;
4441 nv->retry_delay = 1;
4442
4443 nv->port_name[0] = 33;
4444 nv->port_name[3] = 224;
4445 nv->port_name[4] = 139;
4446
e315cd28 4447 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4448
4449 nv->login_timeout = 4;
4450
4451 /*
4452 * Set default host adapter parameters
4453 */
4454 nv->host_p[1] = BIT_2;
4455 nv->reset_delay = 5;
4456 nv->port_down_retry_count = 8;
ad950360 4457 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 4458 nv->link_down_timeout = 60;
4459
4460 rval = 1;
1da177e4
LT		 4461 }
4462
4463#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
4464 /*
4465 * The SN2 does not provide BIOS emulation which means you can't change
4466 * potentially bogus BIOS settings. Force the use of default settings
4467 * for link rate and frame size. Hope that the rest of the settings
4468 * are valid.
4469 */
4470 if (ia64_platform_is("sn2")) {
98aee70d 4471 nv->frame_payload_size = 2048;
1da177e4
LT		 4472 if (IS_QLA23XX(ha))
4473 nv->special_options[1] = BIT_7;
4474 }
4475#endif
4476
4477 /* Reset Initialization control block */
0107109e 4478 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 4479
4480 /*
4481 * Setup driver NVRAM options.
4482 */
4483 nv->firmware_options[0] |= (BIT_6 | BIT_1);
4484 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
4485 nv->firmware_options[1] |= (BIT_5 | BIT_0);
4486 nv->firmware_options[1] &= ~BIT_4;
4487
4488 if (IS_QLA23XX(ha)) {
4489 nv->firmware_options[0] |= BIT_2;
4490 nv->firmware_options[0] &= ~BIT_3;
2d70c103 4491 nv->special_options[0] &= ~BIT_6;
0107109e 4492 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 4493
4494 if (IS_QLA2300(ha)) {
4495 if (ha->fb_rev == FPM_2310) {
4496 strcpy(ha->model_number, "QLA2310");
4497 } else {
4498 strcpy(ha->model_number, "QLA2300");
4499 }
4500 } else {
e315cd28 4501 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 4502 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 4503 }
4504 } else if (IS_QLA2200(ha)) {
4505 nv->firmware_options[0] |= BIT_2;
4506 /*
4507 * 'Point-to-point preferred, else loop' is not a safe
4508 * connection mode setting.
4509 */
4510 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
4511 (BIT_5 | BIT_4)) {
4512 /* Force 'loop preferred, else point-to-point'. */
4513 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
4514 nv->add_firmware_options[0] |= BIT_5;
4515 }
4516 strcpy(ha->model_number, "QLA22xx");
4517 } else /*if (IS_QLA2100(ha))*/ {
4518 strcpy(ha->model_number, "QLA2100");
4519 }
4520
4521 /*
4522 * Copy over NVRAM RISC parameter block to initialization control block.
4523 */
4524 dptr1 = (uint8_t *)icb;
4525 dptr2 = (uint8_t *)&nv->parameter_block_version;
4526 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
4527 while (cnt--)
4528 *dptr1++ = *dptr2++;
4529
4530 /* Copy 2nd half. */
4531 dptr1 = (uint8_t *)icb->add_firmware_options;
4532 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4533 while (cnt--)
4534 *dptr1++ = *dptr2++;
0eaaca4c 4535 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
5341e868
AV		 4536 /* Use alternate WWN? */
4537 if (nv->host_p[1] & BIT_7) {
4538 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4539 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4540 }
4541
1da177e4
LT		 4542 /* Prepare nodename */
4543 if ((icb->firmware_options[1] & BIT_6) == 0) {
4544 /*
4545 * Firmware will apply the following mask if the nodename was
4546 * not provided.
4547 */
4548 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4549 icb->node_name[0] &= 0xF0;
4550 }
4551
4552 /*
4553 * Set host adapter parameters.
4554 */
3ce8866c
SK		 4555
4556 /*
4557 * BIT_7 in the host-parameters section allows for modification to
4558 * internal driver logging.
4559 */
0181944f 4560 if (nv->host_p[0] & BIT_7)
cfb0919c 4561 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 4562 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4563 /* Always load RISC code on non ISP2[12]00 chips. */
4564 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4565 ha->flags.disable_risc_code_load = 0;
4566 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4567 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4568 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 4569 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 4570 ha->flags.disable_serdes = 0;
1da177e4
LT		 4571
4572 ha->operating_mode =
4573 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4574
4575 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4576 sizeof(ha->fw_seriallink_options));
4577
4578 /* save HBA serial number */
4579 ha->serial0 = icb->port_name[5];
4580 ha->serial1 = icb->port_name[6];
4581 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4582 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4583 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 4584
ad950360 4585 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 4586
4587 ha->retry_count = nv->retry_count;
4588
4589 /* Set minimum login_timeout to 4 seconds. */
5b91490e 4590 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 4591 nv->login_timeout = ql2xlogintimeout;
4592 if (nv->login_timeout < 4)
4593 nv->login_timeout = 4;
4594 ha->login_timeout = nv->login_timeout;
1da177e4 4595
00a537b8
AV		 4596 /* Set minimum RATOV to 100 tenths of a second. */
4597 ha->r_a_tov = 100;
1da177e4 4598
1da177e4
LT		 4599 ha->loop_reset_delay = nv->reset_delay;
4600
1da177e4
LT		 4601 /* Link Down Timeout = 0:
4602 *
4603 * When Port Down timer expires we will start returning
4604 * I/O's to OS with "DID_NO_CONNECT".
4605 *
4606 * Link Down Timeout != 0:
4607 *
4608 * The driver waits for the link to come up after link down
4609 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 4610 */
1da177e4
LT		 4611 if (nv->link_down_timeout == 0) {
4612 ha->loop_down_abort_time =
354d6b21 4613 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 4614 } else {
4615 ha->link_down_timeout = nv->link_down_timeout;
4616 ha->loop_down_abort_time =
4617 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 4618 }
1da177e4 4619
1da177e4
LT		 4620 /*
4621 * Need enough time to try and get the port back.
4622 */
4623 ha->port_down_retry_count = nv->port_down_retry_count;
4624 if (qlport_down_retry)
4625 ha->port_down_retry_count = qlport_down_retry;
4626 /* Set login_retry_count */
4627 ha->login_retry_count = nv->retry_count;
4628 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4629 ha->port_down_retry_count > 3)
4630 ha->login_retry_count = ha->port_down_retry_count;
4631 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4632 ha->login_retry_count = ha->port_down_retry_count;
4633 if (ql2xloginretrycount)
4634 ha->login_retry_count = ql2xloginretrycount;
4635
ad950360 4636 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 4637 icb->command_resource_count = 0;
4638 icb->immediate_notify_resource_count = 0;
ad950360 4639 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 4640
4641 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4642 /* Enable RIO */
4643 icb->firmware_options[0] &= ~BIT_3;
4644 icb->add_firmware_options[0] &=
4645 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4646 icb->add_firmware_options[0] |= BIT_2;
4647 icb->response_accumulation_timer = 3;
4648 icb->interrupt_delay_timer = 5;
4649
e315cd28 4650 vha->flags.process_response_queue = 1;
1da177e4 4651 } else {
4fdfefe5 4652 /* Enable ZIO. */
e315cd28 4653 if (!vha->flags.init_done) {
4fdfefe5
AV		 4654 ha->zio_mode = icb->add_firmware_options[0] &
4655 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4656 ha->zio_timer = icb->interrupt_delay_timer ?
4657 icb->interrupt_delay_timer: 2;
4658 }
1da177e4
LT		 4659 icb->add_firmware_options[0] &=
4660 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 4661 vha->flags.process_response_queue = 0;
4fdfefe5 4662 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4663 ha->zio_mode = QLA_ZIO_MODE_6;
4664
7c3df132 4665 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 4666 "ZIO mode %d enabled; timer delay (%d us).\n",
4667 ha->zio_mode, ha->zio_timer * 100);
1da177e4 4668
4fdfefe5
AV		 4669 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4670 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 4671 vha->flags.process_response_queue = 1;
1da177e4
LT		 4672 }
4673 }
4674
4e08df3f 4675 if (rval) {
7c3df132
SK		 4676 ql_log(ql_log_warn, vha, 0x0069,
4677 "NVRAM configuration failed.\n");
4e08df3f
DM		 4678 }
4679 return (rval);
1da177e4
LT		 4680}
4681
19a7b4ae
JSEC		 4682static void
4683qla2x00_rport_del(void *data)
4684{
4685 fc_port_t *fcport = data;
d97994dc 4686 struct fc_rport *rport;
044d78e1 4687 unsigned long flags;
d97994dc 4688
044d78e1 4689 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 4690 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 4691 fcport->drport = NULL;
044d78e1 4692 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548 4693 if (rport) {
83548fe2
QT		 4694 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4695 "%s %8phN. rport %p roles %x\n",
4696 __func__, fcport->port_name, rport,
4697 rport->roles);
726b8548 4698
d97994dc 4699 fc_remote_port_delete(rport);
726b8548 4700 }
19a7b4ae
JSEC		 4701}
4702
1da177e4
LT		 4703/**
4704 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2db6228d 4705 * @vha: HA context
1da177e4
LT		 4706 * @flags: allocation flags
4707 *
4708 * Returns a pointer to the allocated fcport, or NULL, if none available.
4709 */
9a069e19 4710fc_port_t *
e315cd28 4711qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 4712{
4713 fc_port_t *fcport;
4714
bbfbbbc1
MK		 4715 fcport = kzalloc(sizeof(fc_port_t), flags);
4716 if (!fcport)
4717 return NULL;
1da177e4
LT		 4718
4719 /* Setup fcport template structure. */
e315cd28 4720 fcport->vha = vha;
1da177e4
LT		 4721 fcport->port_type = FCT_UNKNOWN;
4722 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 4723 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 4724 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 4725
726b8548
QT		 4726 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
4727 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 4728 flags);
726b8548
QT		 4729 fcport->disc_state = DSC_DELETED;
4730 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4731 fcport->deleted = QLA_SESS_DELETED;
4732 fcport->login_retry = vha->hw->login_retry_count;
726b8548
QT		 4733 fcport->logout_on_delete = 1;
4734
4735 if (!fcport->ct_desc.ct_sns) {
83548fe2 4736 ql_log(ql_log_warn, vha, 0xd049,
726b8548
QT		 4737 "Failed to allocate ct_sns request.\n");
4738 kfree(fcport);
4739 fcport = NULL;
4740 }
4741 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
cd4ed6b4 4742 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn);
726b8548
QT		 4743 INIT_LIST_HEAD(&fcport->gnl_entry);
4744 INIT_LIST_HEAD(&fcport->list);
4745
bbfbbbc1 4746 return fcport;
1da177e4
LT		 4747}
4748
726b8548
QT		 4749void
4750qla2x00_free_fcport(fc_port_t *fcport)
4751{
4752 if (fcport->ct_desc.ct_sns) {
4753 dma_free_coherent(&fcport->vha->hw->pdev->dev,
4754 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
4755 fcport->ct_desc.ct_sns_dma);
4756
4757 fcport->ct_desc.ct_sns = NULL;
4758 }
4759 kfree(fcport);
4760}
4761
1da177e4
LT		 4762/*
4763 * qla2x00_configure_loop
4764 * Updates Fibre Channel Device Database with what is actually on loop.
4765 *
4766 * Input:
4767 * ha = adapter block pointer.
4768 *
4769 * Returns:
4770 * 0 = success.
4771 * 1 = error.
4772 * 2 = database was full and device was not configured.
4773 */
4774static int
e315cd28 4775qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4776{
4777 int rval;
4778 unsigned long flags, save_flags;
e315cd28 4779 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4780 rval = QLA_SUCCESS;
4781
4782 /* Get Initiator ID */
e315cd28
AC		 4783 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
4784 rval = qla2x00_configure_hba(vha);
1da177e4 4785 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4786 ql_dbg(ql_dbg_disc, vha, 0x2013,
4787 "Unable to configure HBA.\n");
1da177e4
LT		 4788 return (rval);
4789 }
4790 }
4791
e315cd28 4792 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 4793 ql_dbg(ql_dbg_disc, vha, 0x2014,
4794 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 4795
4796 /*
4797 * If we have both an RSCN and PORT UPDATE pending then handle them
4798 * both at the same time.
4799 */
e315cd28
AC		 4800 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4801 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 4802
3064ff39
MH		 4803 qla2x00_get_data_rate(vha);
4804
1da177e4
LT		 4805 /* Determine what we need to do */
4806 if (ha->current_topology == ISP_CFG_FL &&
4807 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4808
1da177e4
LT		 4809 set_bit(RSCN_UPDATE, &flags);
4810
4811 } else if (ha->current_topology == ISP_CFG_F &&
4812 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4813
1da177e4
LT		 4814 set_bit(RSCN_UPDATE, &flags);
4815 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4816
4817 } else if (ha->current_topology == ISP_CFG_N) {
4818 clear_bit(RSCN_UPDATE, &flags);
48acad09
QT		 4819 if (qla_tgt_mode_enabled(vha)) {
4820 /* allow the other side to start the login */
9cd883f0
QT		 4821 clear_bit(LOCAL_LOOP_UPDATE, &flags);
4822 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
9cd883f0 4823 }
41dc529a
QT		 4824 } else if (ha->current_topology == ISP_CFG_NL) {
4825 clear_bit(RSCN_UPDATE, &flags);
4826 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4827 } else if (!vha->flags.online ||
1da177e4 4828 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 4829 set_bit(RSCN_UPDATE, &flags);
4830 set_bit(LOCAL_LOOP_UPDATE, &flags);
4831 }
4832
4833 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 4834 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
4835 ql_dbg(ql_dbg_disc, vha, 0x2015,
4836 "Loop resync needed, failing.\n");
1da177e4 4837 rval = QLA_FUNCTION_FAILED;
642ef983 4838 } else
e315cd28 4839 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 4840 }
4841
4842 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132 4843 if (LOOP_TRANSITION(vha)) {
83548fe2 4844 ql_dbg(ql_dbg_disc, vha, 0x2099,
7c3df132 4845 "Needs RSCN update and loop transition.\n");
1da177e4 4846 rval = QLA_FUNCTION_FAILED;
7c3df132 4847 }
e315cd28
AC		 4848 else
4849 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 4850 }
4851
4852 if (rval == QLA_SUCCESS) {
e315cd28
AC		 4853 if (atomic_read(&vha->loop_down_timer) ||
4854 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4855 rval = QLA_FUNCTION_FAILED;
4856 } else {
e315cd28 4857 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4858 ql_dbg(ql_dbg_disc, vha, 0x2069,
4859 "LOOP READY.\n");
ec7193e2 4860 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 4861
4862 /*
4863 * Process any ATIO queue entries that came in
4864 * while we weren't online.
4865 */
ead03855
QT		 4866 if (qla_tgt_mode_enabled(vha) ||
4867 qla_dual_mode_enabled(vha)) {
1073daa4
QT		 4868 spin_lock_irqsave(&ha->tgt.atio_lock, flags);
4869 qlt_24xx_process_atio_queue(vha, 0);
4870 spin_unlock_irqrestore(&ha->tgt.atio_lock,
4871 flags);
3bb67df5 4872 }
1da177e4
LT		 4873 }
4874 }
4875
4876 if (rval) {
7c3df132
SK		 4877 ql_dbg(ql_dbg_disc, vha, 0x206a,
4878 "%s *** FAILED ***.\n", __func__);
1da177e4 4879 } else {
7c3df132
SK		 4880 ql_dbg(ql_dbg_disc, vha, 0x206b,
4881 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4882 }
4883
cc3ef7bc 4884 /* Restore state if a resync event occurred during processing */
e315cd28 4885 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4886 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4887 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4888 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4889 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4890 }
1da177e4
LT		 4891 }
4892
4893 return (rval);
4894}
4895
1da177e4
LT		 4896/*
4897 * qla2x00_configure_local_loop
4898 * Updates Fibre Channel Device Database with local loop devices.
4899 *
4900 * Input:
4901 * ha = adapter block pointer.
4902 *
4903 * Returns:
4904 * 0 = success.
4905 */
4906static int
e315cd28 4907qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4908{
4909 int rval, rval2;
4910 int found_devs;
4911 int found;
4912 fc_port_t *fcport, *new_fcport;
4913
4914 uint16_t index;
4915 uint16_t entries;
4916 char *id_iter;
4917 uint16_t loop_id;
4918 uint8_t domain, area, al_pa;
e315cd28 4919 struct qla_hw_data *ha = vha->hw;
41dc529a 4920 unsigned long flags;
1da177e4 4921
8777e431
QT		 4922 /* Inititae N2N login. */
4923 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) {
4924 /* borrowing */
4925 u32 *bp, i, sz;
4926
4927 memset(ha->init_cb, 0, ha->init_cb_size);
4928 sz = min_t(int, sizeof(struct els_plogi_payload),
4929 ha->init_cb_size);
4930 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma,
4931 (void *)ha->init_cb, sz);
4932 if (rval == QLA_SUCCESS) {
4933 bp = (uint32_t *)ha->init_cb;
4934 for (i = 0; i < sz/4 ; i++, bp++)
4935 *bp = cpu_to_be32(*bp);
4936
4937 memcpy(&ha->plogi_els_payld.data, (void *)ha->init_cb,
4938 sizeof(ha->plogi_els_payld.data));
4939 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4940 } else {
4941 ql_dbg(ql_dbg_init, vha, 0x00d1,
4942 "PLOGI ELS param read fail.\n");
4943 }
4944 return QLA_SUCCESS;
4945 }
4946
1da177e4
LT		 4947 found_devs = 0;
4948 new_fcport = NULL;
642ef983 4949 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4950
1da177e4 4951 /* Get list of logged in devices. */
642ef983 4952 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4953 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4954 &entries);
4955 if (rval != QLA_SUCCESS)
4956 goto cleanup_allocation;
4957
83548fe2 4958 ql_dbg(ql_dbg_disc, vha, 0x2011,
7c3df132
SK		 4959 "Entries in ID list (%d).\n", entries);
4960 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4961 (uint8_t *)ha->gid_list,
4962 entries * sizeof(struct gid_list_info));
1da177e4 4963
9cd883f0
QT		 4964 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4965 fcport->scan_state = QLA_FCPORT_SCAN;
4966 }
4967
1da177e4 4968 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4969 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4970 if (new_fcport == NULL) {
83548fe2 4971 ql_log(ql_log_warn, vha, 0x2012,
7c3df132 4972 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4973 rval = QLA_MEMORY_ALLOC_FAILED;
4974 goto cleanup_allocation;
4975 }
4976 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4977
1da177e4
LT		 4978 /* Add devices to port list. */
4979 id_iter = (char *)ha->gid_list;
4980 for (index = 0; index < entries; index++) {
4981 domain = ((struct gid_list_info *)id_iter)->domain;
4982 area = ((struct gid_list_info *)id_iter)->area;
4983 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4984 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4985 loop_id = (uint16_t)
4986 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4987 else
1da177e4
LT		 4988 loop_id = le16_to_cpu(
4989 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4990 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4991
4992 /* Bypass reserved domain fields. */
4993 if ((domain & 0xf0) == 0xf0)
4994 continue;
4995
4996 /* Bypass if not same domain and area of adapter. */
f7d289f6 4997 if (area && domain &&
e315cd28 4998 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4999 continue;
5000
5001 /* Bypass invalid local loop ID. */
5002 if (loop_id > LAST_LOCAL_LOOP_ID)
5003 continue;
5004
41dc529a 5005 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 5006
1da177e4
LT		 5007 /* Fill in member data. */
5008 new_fcport->d_id.b.domain = domain;
5009 new_fcport->d_id.b.area = area;
5010 new_fcport->d_id.b.al_pa = al_pa;
5011 new_fcport->loop_id = loop_id;
9cd883f0 5012 new_fcport->scan_state = QLA_FCPORT_FOUND;
41dc529a 5013
e315cd28 5014 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 5015 if (rval2 != QLA_SUCCESS) {
83548fe2 5016 ql_dbg(ql_dbg_disc, vha, 0x2097,
7c3df132
SK		 5017 "Failed to retrieve fcport information "
5018 "-- get_port_database=%x, loop_id=0x%04x.\n",
5019 rval2, new_fcport->loop_id);
edd05de1
DG		 5020 /* Skip retry if N2N */
5021 if (ha->current_topology != ISP_CFG_N) {
5022 ql_dbg(ql_dbg_disc, vha, 0x2105,
5023 "Scheduling resync.\n");
5024 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5025 continue;
5026 }
1da177e4
LT		 5027 }
5028
41dc529a 5029 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 5030 /* Check for matching device in port list. */
5031 found = 0;
5032 fcport = NULL;
e315cd28 5033 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5034 if (memcmp(new_fcport->port_name, fcport->port_name,
5035 WWN_SIZE))
5036 continue;
5037
ddb9b126 5038 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 5039 fcport->loop_id = new_fcport->loop_id;
5040 fcport->port_type = new_fcport->port_type;
5041 fcport->d_id.b24 = new_fcport->d_id.b24;
5042 memcpy(fcport->node_name, new_fcport->node_name,
5043 WWN_SIZE);
9cd883f0 5044 fcport->scan_state = QLA_FCPORT_FOUND;
1da177e4
LT		 5045 found++;
5046 break;
5047 }
5048
5049 if (!found) {
5050 /* New device, add to fcports list. */
e315cd28 5051 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 5052
5053 /* Allocate a new replacement fcport. */
5054 fcport = new_fcport;
41dc529a
QT		 5055
5056 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5057
e315cd28 5058 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 5059
1da177e4 5060 if (new_fcport == NULL) {
83548fe2 5061 ql_log(ql_log_warn, vha, 0xd031,
7c3df132 5062 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5063 rval = QLA_MEMORY_ALLOC_FAILED;
5064 goto cleanup_allocation;
5065 }
41dc529a 5066 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 5067 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5068 }
5069
41dc529a
QT		 5070 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5071
d8b45213 5072 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 5073 fcport->fp_speed = ha->link_data_rate;
d8b45213 5074
1da177e4
LT		 5075 found_devs++;
5076 }
5077
9cd883f0
QT		 5078 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5079 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5080 break;
5081
5082 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5083 if ((qla_dual_mode_enabled(vha) ||
5084 qla_ini_mode_enabled(vha)) &&
5085 atomic_read(&fcport->state) == FCS_ONLINE) {
5086 qla2x00_mark_device_lost(vha, fcport,
5087 ql2xplogiabsentdevice, 0);
5088 if (fcport->loop_id != FC_NO_LOOP_ID &&
5089 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5090 fcport->port_type != FCT_INITIATOR &&
5091 fcport->port_type != FCT_BROADCAST) {
5092 ql_dbg(ql_dbg_disc, vha, 0x20f0,
5093 "%s %d %8phC post del sess\n",
5094 __func__, __LINE__,
5095 fcport->port_name);
5096
d8630bb9 5097 qlt_schedule_sess_for_deletion(fcport);
9cd883f0
QT		 5098 continue;
5099 }
5100 }
5101 }
5102
5103 if (fcport->scan_state == QLA_FCPORT_FOUND)
5104 qla24xx_fcport_handle_login(vha, fcport);
5105 }
5106
1da177e4 5107cleanup_allocation:
c9475cb0 5108 kfree(new_fcport);
1da177e4
LT		 5109
5110 if (rval != QLA_SUCCESS) {
83548fe2 5111 ql_dbg(ql_dbg_disc, vha, 0x2098,
7c3df132 5112 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 5113 }
5114
1da177e4
LT		 5115 return (rval);
5116}
5117
d8b45213 5118static void
e315cd28 5119qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 5120{
d8b45213 5121 int rval;
93f2bd67 5122 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5123 struct qla_hw_data *ha = vha->hw;
d8b45213 5124
c76f2c01 5125 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 5126 return;
5127
c9afb9a2
GM		 5128 if (atomic_read(&fcport->state) != FCS_ONLINE)
5129 return;
5130
39bd9622 5131 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
413c2f33
HM		 5132 fcport->fp_speed > ha->link_data_rate ||
5133 !ha->flags.gpsc_supported)
d8b45213
AV		 5134 return;
5135
e315cd28 5136 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 5137 mb);
d8b45213 5138 if (rval != QLA_SUCCESS) {
7c3df132 5139 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 5140 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
5141 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 5142 } else {
7c3df132 5143 ql_dbg(ql_dbg_disc, vha, 0x2005,
33b28357 5144 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n",
d0297c9a 5145 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
33b28357 5146 fcport->fp_speed, fcport->port_name);
d8b45213
AV		 5147 }
5148}
5149
cc28e0ac
QT		 5150void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5151{
5152 qla2x00_iidma_fcport(vha, fcport);
5153 qla24xx_update_fcport_fcp_prio(vha, fcport);
5154}
5155
5156int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5157{
5158 struct qla_work_evt *e;
5159
5160 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA);
5161 if (!e)
5162 return QLA_FUNCTION_FAILED;
5163
5164 e->u.fcport.fcport = fcport;
5165 return qla2x00_post_work(vha, e);
5166}
5167
726b8548 5168/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 5169static void
e315cd28 5170qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 5171{
5172 struct fc_rport_identifiers rport_ids;
bdf79621 5173 struct fc_rport *rport;
044d78e1 5174 unsigned long flags;
8482e118 5175
b63d8b89
QT		 5176 if (atomic_read(&fcport->state) == FCS_ONLINE)
5177 return;
5178
f8b02a85
AV		 5179 rport_ids.node_name = wwn_to_u64(fcport->node_name);
5180 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 5181 rport_ids.port_id = fcport->d_id.b.domain << 16 |
5182 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 5183 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 5184 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 5185 if (!rport) {
7c3df132
SK		 5186 ql_log(ql_log_warn, vha, 0x2006,
5187 "Unable to allocate fc remote port.\n");
77d74143
AV		 5188 return;
5189 }
2d70c103 5190
044d78e1 5191 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 5192 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 5193 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 5194
ad3e0eda 5195 rport->supported_classes = fcport->supported_classes;
77d74143 5196
8482e118 5197 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
5198 if (fcport->port_type == FCT_INITIATOR)
5199 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
5200 if (fcport->port_type == FCT_TARGET)
5201 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548 5202
83548fe2
QT		 5203 ql_dbg(ql_dbg_disc, vha, 0x20ee,
5204 "%s %8phN. rport %p is %s mode\n",
5205 __func__, fcport->port_name, rport,
5206 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
726b8548 5207
77d74143 5208 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 5209}
5210
23be331d
AB		 5211/*
5212 * qla2x00_update_fcport
5213 * Updates device on list.
5214 *
5215 * Input:
5216 * ha = adapter block pointer.
5217 * fcport = port structure pointer.
5218 *
5219 * Return:
5220 * 0 - Success
5221 * BIT_0 - error
5222 *
5223 * Context:
5224 * Kernel context.
5225 */
5226void
e315cd28 5227qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 5228{
726b8548
QT		 5229 if (IS_SW_RESV_ADDR(fcport->d_id))
5230 return;
5231
cd4ed6b4
QT		 5232 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
5233 __func__, fcport->port_name);
5234
5235 fcport->disc_state = DSC_UPD_FCPORT;
5236 fcport->login_retry = vha->hw->login_retry_count;
b63d8b89 5237 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
b63d8b89
QT		 5238 fcport->deleted = 0;
5239 fcport->logout_on_delete = 1;
5240 fcport->login_retry = vha->hw->login_retry_count;
8777e431 5241 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0;
23be331d 5242
dbe18018
DT		 5243 qla2x00_iidma_fcport(vha, fcport);
5244
8777e431
QT		 5245 switch (vha->hw->current_topology) {
5246 case ISP_CFG_N:
5247 case ISP_CFG_NL:
5248 fcport->keep_nport_handle = 1;
5249 break;
5250 default:
5251 break;
5252 }
5253
e84067d7
DG		 5254 if (fcport->fc4f_nvme) {
5255 qla_nvme_register_remote(vha, fcport);
b63d8b89
QT		 5256 fcport->disc_state = DSC_LOGIN_COMPLETE;
5257 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e84067d7
DG		 5258 return;
5259 }
5260
21090cbe 5261 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b 5262
726b8548
QT		 5263 switch (vha->host->active_mode) {
5264 case MODE_INITIATOR:
d20ed91b 5265 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5266 break;
5267 case MODE_TARGET:
5268 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5269 !vha->vha_tgt.qla_tgt->tgt_stopped)
5270 qlt_fc_port_added(vha, fcport);
5271 break;
5272 case MODE_DUAL:
d20ed91b 5273 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 5274 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5275 !vha->vha_tgt.qla_tgt->tgt_stopped)
5276 qlt_fc_port_added(vha, fcport);
5277 break;
5278 default:
5279 break;
d20ed91b 5280 }
cc28e0ac
QT		 5281
5282 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) {
5283 if (fcport->id_changed) {
5284 fcport->id_changed = 0;
5285 ql_dbg(ql_dbg_disc, vha, 0x20d7,
5286 "%s %d %8phC post gfpnid fcp_cnt %d\n",
5287 __func__, __LINE__, fcport->port_name,
5288 vha->fcport_count);
5289 qla24xx_post_gfpnid_work(vha, fcport);
5290 } else {
5291 ql_dbg(ql_dbg_disc, vha, 0x20d7,
5292 "%s %d %8phC post gpsc fcp_cnt %d\n",
5293 __func__, __LINE__, fcport->port_name,
5294 vha->fcport_count);
5295 qla24xx_post_gpsc_work(vha, fcport);
5296 }
5297 }
b63d8b89 5298 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
cd4ed6b4
QT		 5299
5300 fcport->disc_state = DSC_LOGIN_COMPLETE;
5301}
5302
5303void qla_register_fcport_fn(struct work_struct *work)
5304{
5305 fc_port_t *fcport = container_of(work, struct fc_port, reg_work);
5306 u32 rscn_gen = fcport->rscn_gen;
5307 u16 data[2];
5308
5309 if (IS_SW_RESV_ADDR(fcport->d_id))
5310 return;
5311
5312 qla2x00_update_fcport(fcport->vha, fcport);
5313
5314 if (rscn_gen != fcport->rscn_gen) {
5315 /* RSCN(s) came in while registration */
5316 switch (fcport->next_disc_state) {
5317 case DSC_DELETE_PEND:
5318 qlt_schedule_sess_for_deletion(fcport);
5319 break;
5320 case DSC_ADISC:
5321 data[0] = data[1] = 0;
5322 qla2x00_post_async_adisc_work(fcport->vha, fcport,
5323 data);
5324 break;
5325 default:
5326 break;
5327 }
5328 }
23be331d
AB		 5329}
5330
1da177e4
LT		 5331/*
5332 * qla2x00_configure_fabric
5333 * Setup SNS devices with loop ID's.
5334 *
5335 * Input:
5336 * ha = adapter block pointer.
5337 *
5338 * Returns:
5339 * 0 = success.
5340 * BIT_0 = error
5341 */
5342static int
e315cd28 5343qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 5344{
b3b02e6e 5345 int rval;
726b8548 5346 fc_port_t *fcport;
1da177e4 5347 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 5348 uint16_t loop_id;
1da177e4 5349 LIST_HEAD(new_fcports);
e315cd28 5350 struct qla_hw_data *ha = vha->hw;
df673274 5351 int discovery_gen;
1da177e4
LT		 5352
5353 /* If FL port exists, then SNS is present */
e428924c 5354 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 5355 loop_id = NPH_F_PORT;
5356 else
5357 loop_id = SNS_FL_PORT;
e315cd28 5358 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 5359 if (rval != QLA_SUCCESS) {
83548fe2 5360 ql_dbg(ql_dbg_disc, vha, 0x20a0,
7c3df132 5361 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 5362
e315cd28 5363 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 5364 return (QLA_SUCCESS);
5365 }
e315cd28 5366 vha->device_flags |= SWITCH_FOUND;
1da177e4 5367
41dc529a
QT		 5368
5369 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
5370 rval = qla2x00_send_change_request(vha, 0x3, 0);
5371 if (rval != QLA_SUCCESS)
5372 ql_log(ql_log_warn, vha, 0x121,
5373 "Failed to enable receiving of RSCN requests: 0x%x.\n",
5374 rval);
5375 }
5376
5377
1da177e4 5378 do {
726b8548
QT		 5379 qla2x00_mgmt_svr_login(vha);
5380
cca5335c
AV		 5381 /* FDMI support. */
5382 if (ql2xfdmienable &&
e315cd28
AC		 5383 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
5384 qla2x00_fdmi_register(vha);
cca5335c 5385
1da177e4 5386 /* Ensure we are logged into the SNS. */
a14c7711 5387 loop_id = NPH_SNS_LID(ha);
0b91d116
CD		 5388 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
5389 0xfc, mb, BIT_1|BIT_0);
a14c7711
JC		 5390 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5391 ql_dbg(ql_dbg_disc, vha, 0x20a1,
5392 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
5393 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
0b91d116 5394 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 5395 return rval;
0b91d116 5396 }
e315cd28
AC		 5397 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
5398 if (qla2x00_rft_id(vha)) {
1da177e4 5399 /* EMPTY */
83548fe2 5400 ql_dbg(ql_dbg_disc, vha, 0x20a2,
7c3df132 5401 "Register FC-4 TYPE failed.\n");
b98ae0d7
QT		 5402 if (test_bit(LOOP_RESYNC_NEEDED,
5403 &vha->dpc_flags))
5404 break;
1da177e4 5405 }
d3bae931 5406 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
1da177e4 5407 /* EMPTY */
83548fe2 5408 ql_dbg(ql_dbg_disc, vha, 0x209a,
7c3df132 5409 "Register FC-4 Features failed.\n");
b98ae0d7
QT		 5410 if (test_bit(LOOP_RESYNC_NEEDED,
5411 &vha->dpc_flags))
5412 break;
1da177e4 5413 }
d3bae931
DG		 5414 if (vha->flags.nvme_enabled) {
5415 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
5416 ql_dbg(ql_dbg_disc, vha, 0x2049,
5417 "Register NVME FC Type Features failed.\n");
5418 }
5419 }
e315cd28 5420 if (qla2x00_rnn_id(vha)) {
1da177e4 5421 /* EMPTY */
83548fe2 5422 ql_dbg(ql_dbg_disc, vha, 0x2104,
7c3df132 5423 "Register Node Name failed.\n");
b98ae0d7
QT		 5424 if (test_bit(LOOP_RESYNC_NEEDED,
5425 &vha->dpc_flags))
5426 break;
e315cd28 5427 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 5428 /* EMPTY */
83548fe2 5429 ql_dbg(ql_dbg_disc, vha, 0x209b,
0bf0efa1 5430 "Register Symbolic Node Name failed.\n");
b98ae0d7
QT		 5431 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5432 break;
1da177e4
LT		 5433 }
5434 }
5435
827210ba 5436
df673274
AP		 5437 /* Mark the time right before querying FW for connected ports.
5438 * This process is long, asynchronous and by the time it's done,
5439 * collected information might not be accurate anymore. E.g.
5440 * disconnected port might have re-connected and a brand new
5441 * session has been created. In this case session's generation
5442 * will be newer than discovery_gen. */
5443 qlt_do_generation_tick(vha, &discovery_gen);
5444
a4239945 5445 if (USE_ASYNC_SCAN(ha)) {
33b28357
QT		 5446 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI,
5447 NULL);
a4239945
QT		 5448 if (rval)
5449 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5450 } else {
f352eeb7
QT		 5451 list_for_each_entry(fcport, &vha->vp_fcports, list)
5452 fcport->scan_state = QLA_FCPORT_SCAN;
5453
a4239945
QT		 5454 rval = qla2x00_find_all_fabric_devs(vha);
5455 }
1da177e4
LT		 5456 if (rval != QLA_SUCCESS)
5457 break;
1da177e4
LT		 5458 } while (0);
5459
e84067d7
DG		 5460 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
5461 qla_nvme_register_hba(vha);
5462
726b8548 5463 if (rval)
7c3df132
SK		 5464 ql_dbg(ql_dbg_disc, vha, 0x2068,
5465 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 5466
5467 return (rval);
5468}
5469
1da177e4
LT		 5470/*
5471 * qla2x00_find_all_fabric_devs
5472 *
5473 * Input:
5474 * ha = adapter block pointer.
5475 * dev = database device entry pointer.
5476 *
5477 * Returns:
5478 * 0 = success.
5479 *
5480 * Context:
5481 * Kernel context.
5482 */
5483static int
726b8548 5484qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 5485{
5486 int rval;
5487 uint16_t loop_id;
726b8548 5488 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 5489 int found;
5490
5491 sw_info_t *swl;
5492 int swl_idx;
5493 int first_dev, last_dev;
1516ef44 5494 port_id_t wrap = {}, nxt_d_id;
e315cd28 5495 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 5496 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 5497 unsigned long flags;
1da177e4
LT		 5498
5499 rval = QLA_SUCCESS;
5500
5501 /* Try GID_PT to get device list, else GAN. */
7a67735b 5502 if (!ha->swl)
642ef983 5503 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 5504 GFP_KERNEL);
5505 swl = ha->swl;
bbfbbbc1 5506 if (!swl) {
1da177e4 5507 /*EMPTY*/
83548fe2 5508 ql_dbg(ql_dbg_disc, vha, 0x209c,
7c3df132 5509 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 5510 } else {
642ef983 5511 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 5512 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 5513 swl = NULL;
b98ae0d7
QT		 5514 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5515 return rval;
e315cd28 5516 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5517 swl = NULL;
b98ae0d7
QT		 5518 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5519 return rval;
e315cd28 5520 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5521 swl = NULL;
b98ae0d7
QT		 5522 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5523 return rval;
726b8548
QT		 5524 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
5525 swl = NULL;
b98ae0d7
QT		 5526 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5527 return rval;
1da177e4 5528 }
e8c72ba5
CD		 5529
5530 /* If other queries succeeded probe for FC-4 type */
b98ae0d7 5531 if (swl) {
e8c72ba5 5532 qla2x00_gff_id(vha, swl);
b98ae0d7
QT		 5533 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5534 return rval;
5535 }
1da177e4
LT		 5536 }
5537 swl_idx = 0;
5538
5539 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 5540 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5541 if (new_fcport == NULL) {
83548fe2 5542 ql_log(ql_log_warn, vha, 0x209d,
7c3df132 5543 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5544 return (QLA_MEMORY_ALLOC_FAILED);
5545 }
5546 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 5547 /* Set start port ID scan at adapter ID. */
5548 first_dev = 1;
5549 last_dev = 0;
5550
5551 /* Starting free loop ID. */
e315cd28
AC		 5552 loop_id = ha->min_external_loopid;
5553 for (; loop_id <= ha->max_loop_id; loop_id++) {
5554 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 5555 continue;
5556
3a6478df
GM		 5557 if (ha->current_topology == ISP_CFG_FL &&
5558 (atomic_read(&vha->loop_down_timer) ||
5559 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 5560 atomic_set(&vha->loop_down_timer, 0);
5561 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5562 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 5563 break;
bb2d52b2 5564 }
1da177e4
LT		 5565
5566 if (swl != NULL) {
5567 if (last_dev) {
5568 wrap.b24 = new_fcport->d_id.b24;
5569 } else {
5570 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
5571 memcpy(new_fcport->node_name,
5572 swl[swl_idx].node_name, WWN_SIZE);
5573 memcpy(new_fcport->port_name,
5574 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 5575 memcpy(new_fcport->fabric_port_name,
5576 swl[swl_idx].fabric_port_name, WWN_SIZE);
5577 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 5578 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4 5579
a5d42f4c 5580 new_fcport->nvme_flag = 0;
1a28faa0 5581 new_fcport->fc4f_nvme = 0;
a5d42f4c
DG		 5582 if (vha->flags.nvme_enabled &&
5583 swl[swl_idx].fc4f_nvme) {
5584 new_fcport->fc4f_nvme =
5585 swl[swl_idx].fc4f_nvme;
5586 ql_log(ql_log_info, vha, 0x2131,
5587 "FOUND: NVME port %8phC as FC Type 28h\n",
5588 new_fcport->port_name);
5589 }
5590
1da177e4
LT		 5591 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
5592 last_dev = 1;
5593 }
5594 swl_idx++;
5595 }
5596 } else {
5597 /* Send GA_NXT to the switch */
e315cd28 5598 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 5599 if (rval != QLA_SUCCESS) {
83548fe2 5600 ql_log(ql_log_warn, vha, 0x209e,
7c3df132
SK		 5601 "SNS scan failed -- assuming "
5602 "zero-entry result.\n");
1da177e4
LT		 5603 rval = QLA_SUCCESS;
5604 break;
5605 }
5606 }
5607
5608 /* If wrap on switch device list, exit. */
5609 if (first_dev) {
5610 wrap.b24 = new_fcport->d_id.b24;
5611 first_dev = 0;
5612 } else if (new_fcport->d_id.b24 == wrap.b24) {
83548fe2 5613 ql_dbg(ql_dbg_disc, vha, 0x209f,
7c3df132
SK		 5614 "Device wrap (%02x%02x%02x).\n",
5615 new_fcport->d_id.b.domain,
5616 new_fcport->d_id.b.area,
5617 new_fcport->d_id.b.al_pa);
1da177e4
LT		 5618 break;
5619 }
5620
2c3dfe3f 5621 /* Bypass if same physical adapter. */
e315cd28 5622 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 5623 continue;
5624
2c3dfe3f 5625 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 5626 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
5627 continue;
2c3dfe3f 5628
f7d289f6
AV		 5629 /* Bypass if same domain and area of adapter. */
5630 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 5631 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 5632 ISP_CFG_FL)
5633 continue;
5634
1da177e4
LT		 5635 /* Bypass reserved domain fields. */
5636 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
5637 continue;
5638
e8c72ba5 5639 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 5640 if (ql2xgffidenable &&
5641 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
5642 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 5643 continue;
5644
726b8548
QT		 5645 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5646
1da177e4
LT		 5647 /* Locate matching device in database. */
5648 found = 0;
e315cd28 5649 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5650 if (memcmp(new_fcport->port_name, fcport->port_name,
5651 WWN_SIZE))
5652 continue;
5653
827210ba 5654 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 5655
1da177e4
LT		 5656 found++;
5657
d8b45213
AV		 5658 /* Update port state. */
5659 memcpy(fcport->fabric_port_name,
5660 new_fcport->fabric_port_name, WWN_SIZE);
5661 fcport->fp_speed = new_fcport->fp_speed;
5662
1da177e4 5663 /*
b2032fd5
RD		 5664 * If address the same and state FCS_ONLINE
5665 * (or in target mode), nothing changed.
1da177e4
LT		 5666 */
5667 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 5668 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 5669 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 5670 break;
5671 }
5672
5673 /*
5674 * If device was not a fabric device before.
5675 */
5676 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
5677 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 5678 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 5679 fcport->flags |= (FCF_FABRIC_DEVICE |
5680 FCF_LOGIN_NEEDED);
1da177e4
LT		 5681 break;
5682 }
5683
5684 /*
5685 * Port ID changed or device was marked to be updated;
5686 * Log it out if still logged in and mark it for
5687 * relogin later.
5688 */
726b8548 5689 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 5690 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
5691 "port changed FC ID, %8phC"
5692 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
5693 fcport->port_name,
5694 fcport->d_id.b.domain,
5695 fcport->d_id.b.area,
5696 fcport->d_id.b.al_pa,
5697 fcport->loop_id,
5698 new_fcport->d_id.b.domain,
5699 new_fcport->d_id.b.area,
5700 new_fcport->d_id.b.al_pa);
5701 fcport->d_id.b24 = new_fcport->d_id.b24;
5702 break;
5703 }
5704
1da177e4
LT		 5705 fcport->d_id.b24 = new_fcport->d_id.b24;
5706 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 5707 break;
5708 }
5709
9dd9686b
DT		 5710 if (fcport->fc4f_nvme) {
5711 if (fcport->disc_state == DSC_DELETE_PEND) {
5712 fcport->disc_state = DSC_GNL;
5713 vha->fcport_count--;
5714 fcport->login_succ = 0;
5715 }
5716 }
5717
726b8548
QT		 5718 if (found) {
5719 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 5720 continue;
726b8548 5721 }
1da177e4 5722 /* If device was not in our fcports list, then add it. */
b2032fd5 5723 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 5724 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5725
5726 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5727
1da177e4
LT		 5728
5729 /* Allocate a new replacement fcport. */
5730 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 5731 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5732 if (new_fcport == NULL) {
83548fe2 5733 ql_log(ql_log_warn, vha, 0xd032,
7c3df132 5734 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5735 return (QLA_MEMORY_ALLOC_FAILED);
5736 }
5737 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5738 new_fcport->d_id.b24 = nxt_d_id.b24;
5739 }
5740
726b8548
QT		 5741 qla2x00_free_fcport(new_fcport);
5742
5743 /*
5744 * Logout all previous fabric dev marked lost, except FCP2 devices.
5745 */
5746 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5747 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5748 break;
5749
5750 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
5751 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
5752 continue;
5753
5754 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5755 if ((qla_dual_mode_enabled(vha) ||
5756 qla_ini_mode_enabled(vha)) &&
5757 atomic_read(&fcport->state) == FCS_ONLINE) {
5758 qla2x00_mark_device_lost(vha, fcport,
5759 ql2xplogiabsentdevice, 0);
5760 if (fcport->loop_id != FC_NO_LOOP_ID &&
5761 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5762 fcport->port_type != FCT_INITIATOR &&
5763 fcport->port_type != FCT_BROADCAST) {
83548fe2 5764 ql_dbg(ql_dbg_disc, vha, 0x20f0,
726b8548
QT		 5765 "%s %d %8phC post del sess\n",
5766 __func__, __LINE__,
5767 fcport->port_name);
d8630bb9 5768 qlt_schedule_sess_for_deletion(fcport);
726b8548
QT		 5769 continue;
5770 }
5771 }
5772 }
1da177e4 5773
726b8548
QT		 5774 if (fcport->scan_state == QLA_FCPORT_FOUND)
5775 qla24xx_fcport_handle_login(vha, fcport);
5776 }
1da177e4
LT		 5777 return (rval);
5778}
5779
5780/*
5781 * qla2x00_find_new_loop_id
5782 * Scan through our port list and find a new usable loop ID.
5783 *
5784 * Input:
5785 * ha: adapter state pointer.
5786 * dev: port structure pointer.
5787 *
5788 * Returns:
5789 * qla2x00 local function return status code.
5790 *
5791 * Context:
5792 * Kernel context.
5793 */
03bcfb57 5794int
e315cd28 5795qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 5796{
5797 int rval;
e315cd28 5798 struct qla_hw_data *ha = vha->hw;
feafb7b1 5799 unsigned long flags = 0;
1da177e4
LT		 5800
5801 rval = QLA_SUCCESS;
5802
5f16b331 5803 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 5804
5f16b331
CD		 5805 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
5806 LOOPID_MAP_SIZE);
5807 if (dev->loop_id >= LOOPID_MAP_SIZE ||
5808 qla2x00_is_reserved_id(vha, dev->loop_id)) {
5809 dev->loop_id = FC_NO_LOOP_ID;
5810 rval = QLA_FUNCTION_FAILED;
5811 } else
5812 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 5813
5f16b331 5814 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 5815
5f16b331
CD		 5816 if (rval == QLA_SUCCESS)
5817 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
5818 "Assigning new loopid=%x, portid=%x.\n",
5819 dev->loop_id, dev->d_id.b24);
5820 else
5821 ql_log(ql_log_warn, dev->vha, 0x2087,
5822 "No loop_id's available, portid=%x.\n",
5823 dev->d_id.b24);
1da177e4
LT		 5824
5825 return (rval);
5826}
5827
1da177e4 5828
f6602f3b
QT		 5829/* FW does not set aside Loop id for MGMT Server/FFFFFAh */
5830int
5831qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha)
5832{
5833 int loop_id = FC_NO_LOOP_ID;
5834 int lid = NPH_MGMT_SERVER - vha->vp_idx;
5835 unsigned long flags;
5836 struct qla_hw_data *ha = vha->hw;
5837
5838 if (vha->vp_idx == 0) {
5839 set_bit(NPH_MGMT_SERVER, ha->loop_id_map);
5840 return NPH_MGMT_SERVER;
5841 }
5842
5843 /* pick id from high and work down to low */
5844 spin_lock_irqsave(&ha->vport_slock, flags);
5845 for (; lid > 0; lid--) {
5846 if (!test_bit(lid, vha->hw->loop_id_map)) {
5847 set_bit(lid, vha->hw->loop_id_map);
5848 loop_id = lid;
5849 break;
5850 }
5851 }
5852 spin_unlock_irqrestore(&ha->vport_slock, flags);
5853
5854 return loop_id;
5855}
5856
1da177e4
LT		 5857/*
5858 * qla2x00_fabric_login
5859 * Issue fabric login command.
5860 *
5861 * Input:
5862 * ha = adapter block pointer.
5863 * device = pointer to FC device type structure.
5864 *
5865 * Returns:
5866 * 0 - Login successfully
5867 * 1 - Login failed
5868 * 2 - Initiator device
5869 * 3 - Fatal error
5870 */
5871int
e315cd28 5872qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 5873 uint16_t *next_loopid)
5874{
5875 int rval;
5876 int retry;
5877 uint16_t tmp_loopid;
5878 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5879 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 5880
5881 retry = 0;
5882 tmp_loopid = 0;
5883
5884 for (;;) {
7c3df132
SK		 5885 ql_dbg(ql_dbg_disc, vha, 0x2000,
5886 "Trying Fabric Login w/loop id 0x%04x for port "
5887 "%02x%02x%02x.\n",
5888 fcport->loop_id, fcport->d_id.b.domain,
5889 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5890
5891 /* Login fcport on switch. */
0b91d116 5892 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 5893 fcport->d_id.b.domain, fcport->d_id.b.area,
5894 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 5895 if (rval != QLA_SUCCESS) {
5896 return rval;
5897 }
1da177e4
LT		 5898 if (mb[0] == MBS_PORT_ID_USED) {
5899 /*
5900 * Device has another loop ID. The firmware team
0107109e
AV		 5901 * recommends the driver perform an implicit login with
5902 * the specified ID again. The ID we just used is save
5903 * here so we return with an ID that can be tried by
5904 * the next login.
1da177e4
LT		 5905 */
5906 retry++;
5907 tmp_loopid = fcport->loop_id;
5908 fcport->loop_id = mb[1];
5909
7c3df132
SK		 5910 ql_dbg(ql_dbg_disc, vha, 0x2001,
5911 "Fabric Login: port in use - next loop "
5912 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 5913 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 5914 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5915
5916 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
5917 /*
5918 * Login succeeded.
5919 */
5920 if (retry) {
5921 /* A retry occurred before. */
5922 *next_loopid = tmp_loopid;
5923 } else {
5924 /*
5925 * No retry occurred before. Just increment the
5926 * ID value for next login.
5927 */
5928 *next_loopid = (fcport->loop_id + 1);
5929 }
5930
5931 if (mb[1] & BIT_0) {
5932 fcport->port_type = FCT_INITIATOR;
5933 } else {
5934 fcport->port_type = FCT_TARGET;
5935 if (mb[1] & BIT_1) {
8474f3a0 5936 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 5937 }
5938 }
5939
ad3e0eda
AV		 5940 if (mb[10] & BIT_0)
5941 fcport->supported_classes |= FC_COS_CLASS2;
5942 if (mb[10] & BIT_1)
5943 fcport->supported_classes |= FC_COS_CLASS3;
5944
2d70c103
NB		 5945 if (IS_FWI2_CAPABLE(ha)) {
5946 if (mb[10] & BIT_7)
5947 fcport->flags |=
5948 FCF_CONF_COMP_SUPPORTED;
5949 }
5950
1da177e4
LT		 5951 rval = QLA_SUCCESS;
5952 break;
5953 } else if (mb[0] == MBS_LOOP_ID_USED) {
5954 /*
5955 * Loop ID already used, try next loop ID.
5956 */
5957 fcport->loop_id++;
e315cd28 5958 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 5959 if (rval != QLA_SUCCESS) {
5960 /* Ran out of loop IDs to use */
5961 break;
5962 }
5963 } else if (mb[0] == MBS_COMMAND_ERROR) {
5964 /*
5965 * Firmware possibly timed out during login. If NO
5966 * retries are left to do then the device is declared
5967 * dead.
5968 */
5969 *next_loopid = fcport->loop_id;
e315cd28 5970 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5971 fcport->d_id.b.domain, fcport->d_id.b.area,
5972 fcport->d_id.b.al_pa);
e315cd28 5973 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 5974
5975 rval = 1;
5976 break;
5977 } else {
5978 /*
5979 * unrecoverable / not handled error
5980 */
7c3df132
SK		 5981 ql_dbg(ql_dbg_disc, vha, 0x2002,
5982 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
5983 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
5984 fcport->d_id.b.area, fcport->d_id.b.al_pa,
5985 fcport->loop_id, jiffies);
1da177e4
LT		 5986
5987 *next_loopid = fcport->loop_id;
e315cd28 5988 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5989 fcport->d_id.b.domain, fcport->d_id.b.area,
5990 fcport->d_id.b.al_pa);
5f16b331 5991 qla2x00_clear_loop_id(fcport);
0eedfcf0 5992 fcport->login_retry = 0;
1da177e4
LT		 5993
5994 rval = 3;
5995 break;
5996 }
5997 }
5998
5999 return (rval);
6000}
6001
6002/*
6003 * qla2x00_local_device_login
6004 * Issue local device login command.
6005 *
6006 * Input:
6007 * ha = adapter block pointer.
6008 * loop_id = loop id of device to login to.
6009 *
6010 * Returns (Where's the #define!!!!):
6011 * 0 - Login successfully
6012 * 1 - Login failed
6013 * 3 - Fatal error
6014 */
6015int
e315cd28 6016qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 6017{
6018 int rval;
6019 uint16_t mb[MAILBOX_REGISTER_COUNT];
6020
6021 memset(mb, 0, sizeof(mb));
e315cd28 6022 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 6023 if (rval == QLA_SUCCESS) {
6024 /* Interrogate mailbox registers for any errors */
6025 if (mb[0] == MBS_COMMAND_ERROR)
6026 rval = 1;
6027 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
6028 /* device not in PCB table */
6029 rval = 3;
6030 }
6031
6032 return (rval);
6033}
6034
6035/*
6036 * qla2x00_loop_resync
6037 * Resync with fibre channel devices.
6038 *
6039 * Input:
6040 * ha = adapter block pointer.
6041 *
6042 * Returns:
6043 * 0 = success
6044 */
6045int
e315cd28 6046qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 6047{
73208dfd 6048 int rval = QLA_SUCCESS;
1da177e4 6049 uint32_t wait_time;
67c2e93a
AC		 6050 struct req_que *req;
6051 struct rsp_que *rsp;
6052
d7459527 6053 req = vha->req;
67c2e93a 6054 rsp = req->rsp;
1da177e4 6055
e315cd28
AC		 6056 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6057 if (vha->flags.online) {
6058 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 6059 /* Wait at most MAX_TARGET RSCNs for a stable link. */
6060 wait_time = 256;
6061 do {
8ae6d9c7
GM		 6062 if (!IS_QLAFX00(vha->hw)) {
6063 /*
6064 * Issue a marker after FW becomes
6065 * ready.
6066 */
6067 qla2x00_marker(vha, req, rsp, 0, 0,
6068 MK_SYNC_ALL);
6069 vha->marker_needed = 0;
6070 }
1da177e4
LT		 6071
6072 /* Remap devices on Loop. */
e315cd28 6073 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 6074
8ae6d9c7
GM		 6075 if (IS_QLAFX00(vha->hw))
6076 qlafx00_configure_devices(vha);
6077 else
6078 qla2x00_configure_loop(vha);
6079
1da177e4 6080 wait_time--;
e315cd28
AC		 6081 } while (!atomic_read(&vha->loop_down_timer) &&
6082 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
6083 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
6084 &vha->dpc_flags)));
1da177e4 6085 }
1da177e4
LT		 6086 }
6087
e315cd28 6088 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 6089 return (QLA_FUNCTION_FAILED);
1da177e4 6090
e315cd28 6091 if (rval)
7c3df132
SK		 6092 ql_dbg(ql_dbg_disc, vha, 0x206c,
6093 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 6094
6095 return (rval);
6096}
6097
579d12b5
SK		 6098/*
6099* qla2x00_perform_loop_resync
6100* Description: This function will set the appropriate flags and call
6101* qla2x00_loop_resync. If successful loop will be resynced
6102* Arguments : scsi_qla_host_t pointer
6103* returm : Success or Failure
6104*/
6105
6106int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
6107{
6108 int32_t rval = 0;
6109
6110 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
6111 /*Configure the flags so that resync happens properly*/
6112 atomic_set(&ha->loop_down_timer, 0);
6113 if (!(ha->device_flags & DFLG_NO_CABLE)) {
6114 atomic_set(&ha->loop_state, LOOP_UP);
6115 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
6116 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
6117 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
6118
6119 rval = qla2x00_loop_resync(ha);
6120 } else
6121 atomic_set(&ha->loop_state, LOOP_DEAD);
6122
6123 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
6124 }
6125
6126 return rval;
6127}
6128
d97994dc 6129void
67becc00 6130qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 6131{
6132 fc_port_t *fcport;
feafb7b1
AE		 6133 struct scsi_qla_host *vha;
6134 struct qla_hw_data *ha = base_vha->hw;
6135 unsigned long flags;
d97994dc 6136
feafb7b1 6137 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 6138 /* Go with deferred removal of rport references. */
feafb7b1
AE		 6139 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
6140 atomic_inc(&vha->vref_count);
6141 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 6142 if (fcport->drport &&
feafb7b1
AE		 6143 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
6144 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 6145 qla2x00_rport_del(fcport);
df673274 6146
feafb7b1
AE		 6147 spin_lock_irqsave(&ha->vport_slock, flags);
6148 }
6149 }
6150 atomic_dec(&vha->vref_count);
c4a9b538 6151 wake_up(&vha->vref_waitq);
feafb7b1
AE		 6152 }
6153 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 6154}
6155
7d613ac6
SV		 6156/* Assumes idc_lock always held on entry */
6157void
6158qla83xx_reset_ownership(scsi_qla_host_t *vha)
6159{
6160 struct qla_hw_data *ha = vha->hw;
6161 uint32_t drv_presence, drv_presence_mask;
6162 uint32_t dev_part_info1, dev_part_info2, class_type;
6163 uint32_t class_type_mask = 0x3;
6164 uint16_t fcoe_other_function = 0xffff, i;
6165
7ec0effd
AD		 6166 if (IS_QLA8044(ha)) {
6167 drv_presence = qla8044_rd_direct(vha,
6168 QLA8044_CRB_DRV_ACTIVE_INDEX);
6169 dev_part_info1 = qla8044_rd_direct(vha,
6170 QLA8044_CRB_DEV_PART_INFO_INDEX);
6171 dev_part_info2 = qla8044_rd_direct(vha,
6172 QLA8044_CRB_DEV_PART_INFO2);
6173 } else {
6174 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6175 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
6176 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
6177 }
7d613ac6
SV		 6178 for (i = 0; i < 8; i++) {
6179 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
6180 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6181 (i != ha->portnum)) {
6182 fcoe_other_function = i;
6183 break;
6184 }
6185 }
6186 if (fcoe_other_function == 0xffff) {
6187 for (i = 0; i < 8; i++) {
6188 class_type = ((dev_part_info2 >> (i * 4)) &
6189 class_type_mask);
6190 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6191 ((i + 8) != ha->portnum)) {
6192 fcoe_other_function = i + 8;
6193 break;
6194 }
6195 }
6196 }
6197 /*
6198 * Prepare drv-presence mask based on fcoe functions present.
6199 * However consider only valid physical fcoe function numbers (0-15).
6200 */
6201 drv_presence_mask = ~((1 << (ha->portnum)) |
6202 ((fcoe_other_function == 0xffff) ?
6203 0 : (1 << (fcoe_other_function))));
6204
6205 /* We are the reset owner iff:
6206 * - No other protocol drivers present.
6207 * - This is the lowest among fcoe functions. */
6208 if (!(drv_presence & drv_presence_mask) &&
6209 (ha->portnum < fcoe_other_function)) {
6210 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
6211 "This host is Reset owner.\n");
6212 ha->flags.nic_core_reset_owner = 1;
6213 }
6214}
6215
fa492630 6216static int
7d613ac6
SV		 6217__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
6218{
6219 int rval = QLA_SUCCESS;
6220 struct qla_hw_data *ha = vha->hw;
6221 uint32_t drv_ack;
6222
6223 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6224 if (rval == QLA_SUCCESS) {
6225 drv_ack |= (1 << ha->portnum);
6226 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6227 }
6228
6229 return rval;
6230}
6231
fa492630 6232static int
7d613ac6
SV		 6233__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
6234{
6235 int rval = QLA_SUCCESS;
6236 struct qla_hw_data *ha = vha->hw;
6237 uint32_t drv_ack;
6238
6239 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6240 if (rval == QLA_SUCCESS) {
6241 drv_ack &= ~(1 << ha->portnum);
6242 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6243 }
6244
6245 return rval;
6246}
6247
fa492630 6248static const char *
7d613ac6
SV		 6249qla83xx_dev_state_to_string(uint32_t dev_state)
6250{
6251 switch (dev_state) {
6252 case QLA8XXX_DEV_COLD:
6253 return "COLD/RE-INIT";
6254 case QLA8XXX_DEV_INITIALIZING:
6255 return "INITIALIZING";
6256 case QLA8XXX_DEV_READY:
6257 return "READY";
6258 case QLA8XXX_DEV_NEED_RESET:
6259 return "NEED RESET";
6260 case QLA8XXX_DEV_NEED_QUIESCENT:
6261 return "NEED QUIESCENT";
6262 case QLA8XXX_DEV_FAILED:
6263 return "FAILED";
6264 case QLA8XXX_DEV_QUIESCENT:
6265 return "QUIESCENT";
6266 default:
6267 return "Unknown";
6268 }
6269}
6270
6271/* Assumes idc-lock always held on entry */
6272void
6273qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
6274{
6275 struct qla_hw_data *ha = vha->hw;
6276 uint32_t idc_audit_reg = 0, duration_secs = 0;
6277
6278 switch (audit_type) {
6279 case IDC_AUDIT_TIMESTAMP:
6280 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
6281 idc_audit_reg = (ha->portnum) |
6282 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
6283 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6284 break;
6285
6286 case IDC_AUDIT_COMPLETION:
6287 duration_secs = ((jiffies_to_msecs(jiffies) -
6288 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
6289 idc_audit_reg = (ha->portnum) |
6290 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
6291 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6292 break;
6293
6294 default:
6295 ql_log(ql_log_warn, vha, 0xb078,
6296 "Invalid audit type specified.\n");
6297 break;
6298 }
6299}
6300
6301/* Assumes idc_lock always held on entry */
fa492630 6302static int
7d613ac6
SV		 6303qla83xx_initiating_reset(scsi_qla_host_t *vha)
6304{
6305 struct qla_hw_data *ha = vha->hw;
6306 uint32_t idc_control, dev_state;
6307
6308 __qla83xx_get_idc_control(vha, &idc_control);
6309 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
6310 ql_log(ql_log_info, vha, 0xb080,
6311 "NIC Core reset has been disabled. idc-control=0x%x\n",
6312 idc_control);
6313 return QLA_FUNCTION_FAILED;
6314 }
6315
6316 /* Set NEED-RESET iff in READY state and we are the reset-owner */
6317 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6318 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
6319 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
6320 QLA8XXX_DEV_NEED_RESET);
6321 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
6322 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
6323 } else {
6324 const char *state = qla83xx_dev_state_to_string(dev_state);
6325 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
6326
6327 /* SV: XXX: Is timeout required here? */
6328 /* Wait for IDC state change READY -> NEED_RESET */
6329 while (dev_state == QLA8XXX_DEV_READY) {
6330 qla83xx_idc_unlock(vha, 0);
6331 msleep(200);
6332 qla83xx_idc_lock(vha, 0);
6333 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6334 }
6335 }
6336
6337 /* Send IDC ack by writing to drv-ack register */
6338 __qla83xx_set_drv_ack(vha);
6339
6340 return QLA_SUCCESS;
6341}
6342
6343int
6344__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
6345{
6346 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6347}
6348
7d613ac6
SV		 6349int
6350__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
6351{
6352 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6353}
6354
fa492630 6355static int
7d613ac6
SV		 6356qla83xx_check_driver_presence(scsi_qla_host_t *vha)
6357{
6358 uint32_t drv_presence = 0;
6359 struct qla_hw_data *ha = vha->hw;
6360
6361 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6362 if (drv_presence & (1 << ha->portnum))
6363 return QLA_SUCCESS;
6364 else
6365 return QLA_TEST_FAILED;
6366}
6367
6368int
6369qla83xx_nic_core_reset(scsi_qla_host_t *vha)
6370{
6371 int rval = QLA_SUCCESS;
6372 struct qla_hw_data *ha = vha->hw;
6373
6374 ql_dbg(ql_dbg_p3p, vha, 0xb058,
6375 "Entered %s().\n", __func__);
6376
6377 if (vha->device_flags & DFLG_DEV_FAILED) {
6378 ql_log(ql_log_warn, vha, 0xb059,
6379 "Device in unrecoverable FAILED state.\n");
6380 return QLA_FUNCTION_FAILED;
6381 }
6382
6383 qla83xx_idc_lock(vha, 0);
6384
6385 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
6386 ql_log(ql_log_warn, vha, 0xb05a,
6387 "Function=0x%x has been removed from IDC participation.\n",
6388 ha->portnum);
6389 rval = QLA_FUNCTION_FAILED;
6390 goto exit;
6391 }
6392
6393 qla83xx_reset_ownership(vha);
6394
6395 rval = qla83xx_initiating_reset(vha);
6396
6397 /*
6398 * Perform reset if we are the reset-owner,
6399 * else wait till IDC state changes to READY/FAILED.
6400 */
6401 if (rval == QLA_SUCCESS) {
6402 rval = qla83xx_idc_state_handler(vha);
6403
6404 if (rval == QLA_SUCCESS)
6405 ha->flags.nic_core_hung = 0;
6406 __qla83xx_clear_drv_ack(vha);
6407 }
6408
6409exit:
6410 qla83xx_idc_unlock(vha, 0);
6411
6412 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
6413
6414 return rval;
6415}
6416
81178772
SK		 6417int
6418qla2xxx_mctp_dump(scsi_qla_host_t *vha)
6419{
6420 struct qla_hw_data *ha = vha->hw;
6421 int rval = QLA_FUNCTION_FAILED;
6422
6423 if (!IS_MCTP_CAPABLE(ha)) {
6424 /* This message can be removed from the final version */
6425 ql_log(ql_log_info, vha, 0x506d,
6426 "This board is not MCTP capable\n");
6427 return rval;
6428 }
6429
6430 if (!ha->mctp_dump) {
6431 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
6432 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
6433
6434 if (!ha->mctp_dump) {
6435 ql_log(ql_log_warn, vha, 0x506e,
6436 "Failed to allocate memory for mctp dump\n");
6437 return rval;
6438 }
6439 }
6440
6441#define MCTP_DUMP_STR_ADDR 0x00000000
6442 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
6443 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
6444 if (rval != QLA_SUCCESS) {
6445 ql_log(ql_log_warn, vha, 0x506f,
6446 "Failed to capture mctp dump\n");
6447 } else {
6448 ql_log(ql_log_info, vha, 0x5070,
6449 "Mctp dump capture for host (%ld/%p).\n",
6450 vha->host_no, ha->mctp_dump);
6451 ha->mctp_dumped = 1;
6452 }
6453
409ee0fe 6454 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 6455 ha->flags.nic_core_reset_hdlr_active = 1;
6456 rval = qla83xx_restart_nic_firmware(vha);
6457 if (rval)
6458 /* NIC Core reset failed. */
6459 ql_log(ql_log_warn, vha, 0x5071,
6460 "Failed to restart nic firmware\n");
6461 else
6462 ql_dbg(ql_dbg_p3p, vha, 0xb084,
6463 "Restarted NIC firmware successfully.\n");
6464 ha->flags.nic_core_reset_hdlr_active = 0;
6465 }
6466
6467 return rval;
6468
6469}
6470
579d12b5 6471/*
8fcd6b8b 6472* qla2x00_quiesce_io
579d12b5
SK		 6473* Description: This function will block the new I/Os
6474* Its not aborting any I/Os as context
6475* is not destroyed during quiescence
6476* Arguments: scsi_qla_host_t
6477* return : void
6478*/
6479void
8fcd6b8b 6480qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 6481{
6482 struct qla_hw_data *ha = vha->hw;
6483 struct scsi_qla_host *vp;
6484
8fcd6b8b
CD		 6485 ql_dbg(ql_dbg_dpc, vha, 0x401d,
6486 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 6487
6488 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
6489 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6490 atomic_set(&vha->loop_state, LOOP_DOWN);
6491 qla2x00_mark_all_devices_lost(vha, 0);
6492 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 6493 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 6494 } else {
6495 if (!atomic_read(&vha->loop_down_timer))
6496 atomic_set(&vha->loop_down_timer,
6497 LOOP_DOWN_TIME);
6498 }
6499 /* Wait for pending cmds to complete */
6500 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
6501}
6502
a9083016
GM		 6503void
6504qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
6505{
6506 struct qla_hw_data *ha = vha->hw;
579d12b5 6507 struct scsi_qla_host *vp;
feafb7b1 6508 unsigned long flags;
6aef87be 6509 fc_port_t *fcport;
7c3f8fd1 6510 u16 i;
a9083016 6511
e46ef004
SK		 6512 /* For ISP82XX, driver waits for completion of the commands.
6513 * online flag should be set.
6514 */
7ec0effd 6515 if (!(IS_P3P_TYPE(ha)))
e46ef004 6516 vha->flags.online = 0;
a9083016
GM		 6517 ha->flags.chip_reset_done = 0;
6518 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 6519 vha->qla_stats.total_isp_aborts++;
a9083016 6520
7c3df132
SK		 6521 ql_log(ql_log_info, vha, 0x00af,
6522 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 6523
b2000805 6524 ha->flags.purge_mbox = 1;
e46ef004
SK		 6525 /* For ISP82XX, reset_chip is just disabling interrupts.
6526 * Driver waits for the completion of the commands.
6527 * the interrupts need to be enabled.
6528 */
7ec0effd 6529 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 6530 ha->isp_ops->reset_chip(vha);
6531
9cd883f0
QT		 6532 SAVE_TOPO(ha);
6533 ha->flags.rida_fmt2 = 0;
ec7193e2
QT		 6534 ha->flags.n2n_ae = 0;
6535 ha->flags.lip_ae = 0;
6536 ha->current_topology = 0;
6537 ha->flags.fw_started = 0;
6538 ha->flags.fw_init_done = 0;
b2000805
QT		 6539 ha->chip_reset++;
6540 ha->base_qpair->chip_reset = ha->chip_reset;
7c3f8fd1
QT		 6541 for (i = 0; i < ha->max_qpairs; i++) {
6542 if (ha->queue_pair_map[i])
6543 ha->queue_pair_map[i]->chip_reset =
6544 ha->base_qpair->chip_reset;
6545 }
726b8548 6546
b2000805
QT		 6547 /* purge MBox commands */
6548 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6549 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6550 complete(&ha->mbx_intr_comp);
6551 }
6552
6553 i = 0;
6554 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6555 atomic_read(&ha->num_pend_mbx_stage2) ||
6556 atomic_read(&ha->num_pend_mbx_stage1)) {
6557 msleep(20);
6558 i++;
6559 if (i > 50)
6560 break;
6561 }
6562 ha->flags.purge_mbox = 0;
6563
a9083016
GM		 6564 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
6565 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6566 atomic_set(&vha->loop_state, LOOP_DOWN);
6567 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 6568
6569 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 6570 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 6571 atomic_inc(&vp->vref_count);
6572 spin_unlock_irqrestore(&ha->vport_slock, flags);
6573
a9083016 6574 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 6575
6576 spin_lock_irqsave(&ha->vport_slock, flags);
6577 atomic_dec(&vp->vref_count);
6578 }
6579 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 6580 } else {
6581 if (!atomic_read(&vha->loop_down_timer))
6582 atomic_set(&vha->loop_down_timer,
6583 LOOP_DOWN_TIME);
6584 }
6585
6aef87be
AV		 6586 /* Clear all async request states across all VPs. */
6587 list_for_each_entry(fcport, &vha->vp_fcports, list)
6588 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6589 spin_lock_irqsave(&ha->vport_slock, flags);
6590 list_for_each_entry(vp, &ha->vp_list, list) {
6591 atomic_inc(&vp->vref_count);
6592 spin_unlock_irqrestore(&ha->vport_slock, flags);
6593
6594 list_for_each_entry(fcport, &vp->vp_fcports, list)
6595 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6596
6597 spin_lock_irqsave(&ha->vport_slock, flags);
6598 atomic_dec(&vp->vref_count);
6599 }
6600 spin_unlock_irqrestore(&ha->vport_slock, flags);
6601
bddd2d65
LC		 6602 if (!ha->flags.eeh_busy) {
6603 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 6604 if (IS_P3P_TYPE(ha)) {
7190575f 6605 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 6606 ql_log(ql_log_info, vha, 0x00b4,
6607 "Done chip reset cleanup.\n");
a9083016 6608
e46ef004
SK		 6609 /* Done waiting for pending commands.
6610 * Reset the online flag.
6611 */
6612 vha->flags.online = 0;
4d78c973 6613 }
a9083016 6614
bddd2d65
LC		 6615 /* Requeue all commands in outstanding command list. */
6616 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6617 }
b6a029e1
AE		 6618 /* memory barrier */
6619 wmb();
a9083016
GM		 6620}
6621
1da177e4
LT		 6622/*
6623* qla2x00_abort_isp
6624* Resets ISP and aborts all outstanding commands.
6625*
6626* Input:
6627* ha = adapter block pointer.
6628*
6629* Returns:
6630* 0 = success
6631*/
6632int
e315cd28 6633qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 6634{
476e8978 6635 int rval;
1da177e4 6636 uint8_t status = 0;
e315cd28
AC		 6637 struct qla_hw_data *ha = vha->hw;
6638 struct scsi_qla_host *vp;
73208dfd 6639 struct req_que *req = ha->req_q_map[0];
feafb7b1 6640 unsigned long flags;
1da177e4 6641
e315cd28 6642 if (vha->flags.online) {
a9083016 6643 qla2x00_abort_isp_cleanup(vha);
1da177e4 6644
a6171297
SV		 6645 if (IS_QLA8031(ha)) {
6646 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
6647 "Clearing fcoe driver presence.\n");
6648 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
6649 ql_dbg(ql_dbg_p3p, vha, 0xb073,
6650 "Error while clearing DRV-Presence.\n");
6651 }
6652
85880801
AV		 6653 if (unlikely(pci_channel_offline(ha->pdev) &&
6654 ha->flags.pci_channel_io_perm_failure)) {
6655 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6656 status = 0;
6657 return status;
6658 }
6659
73208dfd 6660 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 6661
e315cd28 6662 ha->isp_ops->nvram_config(vha);
1da177e4 6663
e315cd28
AC		 6664 if (!qla2x00_restart_isp(vha)) {
6665 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 6666
e315cd28 6667 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 6668 /*
6669 * Issue marker command only when we are going
6670 * to start the I/O .
6671 */
e315cd28 6672 vha->marker_needed = 1;
1da177e4
LT		 6673 }
6674
e315cd28 6675 vha->flags.online = 1;
1da177e4 6676
fd34f556 6677 ha->isp_ops->enable_intrs(ha);
1da177e4 6678
fa2a1ce5 6679 ha->isp_abort_cnt = 0;
e315cd28 6680 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 6681
6246b8a1
GM		 6682 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
6683 qla2x00_get_fw_version(vha);
df613b96
AV		 6684 if (ha->fce) {
6685 ha->flags.fce_enabled = 1;
6686 memset(ha->fce, 0,
6687 fce_calc_size(ha->fce_bufs));
e315cd28 6688 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 6689 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6690 &ha->fce_bufs);
6691 if (rval) {
7c3df132 6692 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 6693 "Unable to reinitialize FCE "
6694 "(%d).\n", rval);
6695 ha->flags.fce_enabled = 0;
6696 }
6697 }
436a7b11
AV		 6698
6699 if (ha->eft) {
6700 memset(ha->eft, 0, EFT_SIZE);
e315cd28 6701 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 6702 ha->eft_dma, EFT_NUM_BUFFERS);
6703 if (rval) {
7c3df132 6704 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 6705 "Unable to reinitialize EFT "
6706 "(%d).\n", rval);
6707 }
6708 }
1da177e4 6709 } else { /* failed the ISP abort */
e315cd28
AC		 6710 vha->flags.online = 1;
6711 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 6712 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 6713 ql_log(ql_log_fatal, vha, 0x8035,
6714 "ISP error recover failed - "
6715 "board disabled.\n");
fa2a1ce5 6716 /*
1da177e4
LT		 6717 * The next call disables the board
6718 * completely.
6719 */
e315cd28
AC		 6720 ha->isp_ops->reset_adapter(vha);
6721 vha->flags.online = 0;
1da177e4 6722 clear_bit(ISP_ABORT_RETRY,
e315cd28 6723 &vha->dpc_flags);
1da177e4
LT		 6724 status = 0;
6725 } else { /* schedule another ISP abort */
6726 ha->isp_abort_cnt--;
7c3df132
SK		 6727 ql_dbg(ql_dbg_taskm, vha, 0x8020,
6728 "ISP abort - retry remaining %d.\n",
6729 ha->isp_abort_cnt);
1da177e4
LT		 6730 status = 1;
6731 }
6732 } else {
6733 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 6734 ql_dbg(ql_dbg_taskm, vha, 0x8021,
6735 "ISP error recovery - retrying (%d) "
6736 "more times.\n", ha->isp_abort_cnt);
e315cd28 6737 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 6738 status = 1;
6739 }
6740 }
fa2a1ce5 6741
1da177e4
LT		 6742 }
6743
e315cd28 6744 if (!status) {
7c3df132 6745 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
1608cc4a 6746 qla2x00_configure_hba(vha);
feafb7b1
AE		 6747 spin_lock_irqsave(&ha->vport_slock, flags);
6748 list_for_each_entry(vp, &ha->vp_list, list) {
6749 if (vp->vp_idx) {
6750 atomic_inc(&vp->vref_count);
6751 spin_unlock_irqrestore(&ha->vport_slock, flags);
6752
e315cd28 6753 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6754
6755 spin_lock_irqsave(&ha->vport_slock, flags);
6756 atomic_dec(&vp->vref_count);
6757 }
e315cd28 6758 }
feafb7b1
AE		 6759 spin_unlock_irqrestore(&ha->vport_slock, flags);
6760
7d613ac6
SV		 6761 if (IS_QLA8031(ha)) {
6762 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
6763 "Setting back fcoe driver presence.\n");
6764 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
6765 ql_dbg(ql_dbg_p3p, vha, 0xb074,
6766 "Error while setting DRV-Presence.\n");
6767 }
e315cd28 6768 } else {
d8424f68
JP		 6769 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
6770 __func__);
1da177e4
LT		 6771 }
6772
6773 return(status);
6774}
6775
6776/*
6777* qla2x00_restart_isp
6778* restarts the ISP after a reset
6779*
6780* Input:
6781* ha = adapter block pointer.
6782*
6783* Returns:
6784* 0 = success
6785*/
6786static int
e315cd28 6787qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 6788{
c6b2fca8 6789 int status = 0;
e315cd28 6790 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 6791 struct req_que *req = ha->req_q_map[0];
6792 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 6793
6794 /* If firmware needs to be loaded */
e315cd28
AC		 6795 if (qla2x00_isp_firmware(vha)) {
6796 vha->flags.online = 0;
6797 status = ha->isp_ops->chip_diag(vha);
6798 if (!status)
6799 status = qla2x00_setup_chip(vha);
1da177e4
LT		 6800 }
6801
e315cd28
AC		 6802 if (!status && !(status = qla2x00_init_rings(vha))) {
6803 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 6804 ha->flags.chip_reset_done = 1;
7108b76e 6805
73208dfd
AC		 6806 /* Initialize the queues in use */
6807 qla25xx_init_queues(ha);
6808
e315cd28
AC		 6809 status = qla2x00_fw_ready(vha);
6810 if (!status) {
0107109e 6811 /* Issue a marker after FW becomes ready. */
73208dfd 6812 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 6813 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6814 }
6815
6816 /* if no cable then assume it's good */
e315cd28 6817 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 6818 status = 0;
1da177e4
LT		 6819 }
6820 return (status);
6821}
6822
73208dfd
AC		 6823static int
6824qla25xx_init_queues(struct qla_hw_data *ha)
6825{
6826 struct rsp_que *rsp = NULL;
6827 struct req_que *req = NULL;
6828 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6829 int ret = -1;
6830 int i;
6831
2afa19a9 6832 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 6833 rsp = ha->rsp_q_map[i];
cb43285f 6834 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 6835 rsp->options &= ~BIT_0;
618a7523 6836 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 6837 if (ret != QLA_SUCCESS)
7c3df132
SK		 6838 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
6839 "%s Rsp que: %d init failed.\n",
6840 __func__, rsp->id);
73208dfd 6841 else
7c3df132
SK		 6842 ql_dbg(ql_dbg_init, base_vha, 0x0100,
6843 "%s Rsp que: %d inited.\n",
6844 __func__, rsp->id);
73208dfd 6845 }
2afa19a9
AC		 6846 }
6847 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 6848 req = ha->req_q_map[i];
cb43285f
QT		 6849 if (req && test_bit(i, ha->req_qid_map)) {
6850 /* Clear outstanding commands array. */
73208dfd 6851 req->options &= ~BIT_0;
618a7523 6852 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 6853 if (ret != QLA_SUCCESS)
7c3df132
SK		 6854 ql_dbg(ql_dbg_init, base_vha, 0x0101,
6855 "%s Req que: %d init failed.\n",
6856 __func__, req->id);
73208dfd 6857 else
7c3df132
SK		 6858 ql_dbg(ql_dbg_init, base_vha, 0x0102,
6859 "%s Req que: %d inited.\n",
6860 __func__, req->id);
73208dfd
AC		 6861 }
6862 }
6863 return ret;
6864}
6865
1da177e4
LT		 6866/*
6867* qla2x00_reset_adapter
6868* Reset adapter.
6869*
6870* Input:
6871* ha = adapter block pointer.
6872*/
abbd8870 6873void
e315cd28 6874qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 6875{
6876 unsigned long flags = 0;
e315cd28 6877 struct qla_hw_data *ha = vha->hw;
3d71644c 6878 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 6879
e315cd28 6880 vha->flags.online = 0;
fd34f556 6881 ha->isp_ops->disable_intrs(ha);
1da177e4 6882
1da177e4
LT		 6883 spin_lock_irqsave(&ha->hardware_lock, flags);
6884 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
6885 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6886 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
6887 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6888 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6889}
0107109e
AV		 6890
6891void
e315cd28 6892qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 6893{
6894 unsigned long flags = 0;
e315cd28 6895 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 6896 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
6897
7ec0effd 6898 if (IS_P3P_TYPE(ha))
a9083016
GM		 6899 return;
6900
e315cd28 6901 vha->flags.online = 0;
fd34f556 6902 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 6903
6904 spin_lock_irqsave(&ha->hardware_lock, flags);
6905 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
6906 RD_REG_DWORD(&reg->hccr);
6907 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
6908 RD_REG_DWORD(&reg->hccr);
6909 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 6910
6911 if (IS_NOPOLLING_TYPE(ha))
6912 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 6913}
6914
4e08df3f
DM		 6915/* On sparc systems, obtain port and node WWN from firmware
6916 * properties.
6917 */
e315cd28
AC		 6918static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
6919 struct nvram_24xx *nv)
4e08df3f
DM		 6920{
6921#ifdef CONFIG_SPARC
e315cd28 6922 struct qla_hw_data *ha = vha->hw;
4e08df3f 6923 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 6924 struct device_node *dp = pci_device_to_OF_node(pdev);
6925 const u8 *val;
4e08df3f
DM		 6926 int len;
6927
6928 val = of_get_property(dp, "port-wwn", &len);
6929 if (val && len >= WWN_SIZE)
6930 memcpy(nv->port_name, val, WWN_SIZE);
6931
6932 val = of_get_property(dp, "node-wwn", &len);
6933 if (val && len >= WWN_SIZE)
6934 memcpy(nv->node_name, val, WWN_SIZE);
6935#endif
6936}
6937
0107109e 6938int
e315cd28 6939qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 6940{
4e08df3f 6941 int rval;
0107109e
AV		 6942 struct init_cb_24xx *icb;
6943 struct nvram_24xx *nv;
6944 uint32_t *dptr;
6945 uint8_t *dptr1, *dptr2;
6946 uint32_t chksum;
6947 uint16_t cnt;
e315cd28 6948 struct qla_hw_data *ha = vha->hw;
0107109e 6949
4e08df3f 6950 rval = QLA_SUCCESS;
0107109e 6951 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 6952 nv = ha->nvram;
0107109e
AV		 6953
6954 /* Determine NVRAM starting address. */
f73cb695 6955 if (ha->port_no == 0) {
e5b68a61
AC		 6956 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
6957 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
6958 } else {
0107109e 6959 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 6960 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
6961 }
f73cb695 6962
e5b68a61
AC		 6963 ha->nvram_size = sizeof(struct nvram_24xx);
6964 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 6965
281afe19
SJ		 6966 /* Get VPD data into cache */
6967 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 6968 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 6969 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
6970
6971 /* Get NVRAM data into cache and calculate checksum. */
0107109e 6972 dptr = (uint32_t *)nv;
e315cd28 6973 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 6974 ha->nvram_size);
da08ef5c
JC		 6975 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6976 chksum += le32_to_cpu(*dptr);
0107109e 6977
7c3df132
SK		 6978 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
6979 "Contents of NVRAM\n");
6980 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
6981 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 6982
6983 /* Bad NVRAM data, set defaults parameters. */
6984 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6985 || nv->id[3] != ' ' ||
ad950360 6986 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 6987 /* Reset NVRAM data. */
7c3df132 6988 ql_log(ql_log_warn, vha, 0x006b,
9e336520 6989 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 6990 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
6991 ql_log(ql_log_warn, vha, 0x006c,
6992 "Falling back to functioning (yet invalid -- WWPN) "
6993 "defaults.\n");
4e08df3f
DM		 6994
6995 /*
6996 * Set default initialization control block.
6997 */
6998 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6999 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7000 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7001 nv->frame_payload_size = 2048;
ad950360
BVA		 7002 nv->execution_throttle = cpu_to_le16(0xFFFF);
7003 nv->exchange_count = cpu_to_le16(0);
7004 nv->hard_address = cpu_to_le16(124);
4e08df3f 7005 nv->port_name[0] = 0x21;
f73cb695 7006 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 7007 nv->port_name[2] = 0x00;
7008 nv->port_name[3] = 0xe0;
7009 nv->port_name[4] = 0x8b;
7010 nv->port_name[5] = 0x1c;
7011 nv->port_name[6] = 0x55;
7012 nv->port_name[7] = 0x86;
7013 nv->node_name[0] = 0x20;
7014 nv->node_name[1] = 0x00;
7015 nv->node_name[2] = 0x00;
7016 nv->node_name[3] = 0xe0;
7017 nv->node_name[4] = 0x8b;
7018 nv->node_name[5] = 0x1c;
7019 nv->node_name[6] = 0x55;
7020 nv->node_name[7] = 0x86;
e315cd28 7021 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 7022 nv->login_retry_count = cpu_to_le16(8);
7023 nv->interrupt_delay_timer = cpu_to_le16(0);
7024 nv->login_timeout = cpu_to_le16(0);
4e08df3f 7025 nv->firmware_options_1 =
ad950360
BVA		 7026 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7027 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7028 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7029 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7030 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7031 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 7032 nv->reset_delay = 5;
ad950360
BVA		 7033 nv->max_luns_per_target = cpu_to_le16(128);
7034 nv->port_down_retry_count = cpu_to_le16(30);
7035 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 7036
7037 rval = 1;
0107109e
AV		 7038 }
7039
726b8548 7040 if (qla_tgt_mode_enabled(vha)) {
2d70c103 7041 /* Don't enable full login after initial LIP */
ad950360 7042 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 7043 /* Don't enable LIP full login for initiator */
ad950360 7044 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 7045 }
7046
7047 qlt_24xx_config_nvram_stage1(vha, nv);
7048
0107109e 7049 /* Reset Initialization control block */
e315cd28 7050 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 7051
7052 /* Copy 1st segment. */
7053 dptr1 = (uint8_t *)icb;
7054 dptr2 = (uint8_t *)&nv->version;
7055 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7056 while (cnt--)
7057 *dptr1++ = *dptr2++;
7058
7059 icb->login_retry_count = nv->login_retry_count;
3ea66e28 7060 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 7061
7062 /* Copy 2nd segment. */
7063 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7064 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7065 cnt = (uint8_t *)&icb->reserved_3 -
7066 (uint8_t *)&icb->interrupt_delay_timer;
7067 while (cnt--)
7068 *dptr1++ = *dptr2++;
0eaaca4c 7069 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
0107109e
AV		 7070 /*
7071 * Setup driver NVRAM options.
7072 */
e315cd28 7073 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 7074 "QLA2462");
0107109e 7075
2d70c103
NB		 7076 qlt_24xx_config_nvram_stage2(vha, icb);
7077
ad950360 7078 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 7079 /* Use alternate WWN? */
5341e868
AV		 7080 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7081 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7082 }
7083
0107109e 7084 /* Prepare nodename */
ad950360 7085 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 7086 /*
7087 * Firmware will apply the following mask if the nodename was
7088 * not provided.
7089 */
7090 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7091 icb->node_name[0] &= 0xF0;
7092 }
7093
7094 /* Set host adapter parameters. */
7095 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 7096 ha->flags.enable_lip_reset = 0;
7097 ha->flags.enable_lip_full_login =
7098 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7099 ha->flags.enable_target_reset =
7100 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 7101 ha->flags.enable_led_scheme = 0;
d4c760c2 7102 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 7103
fd0e7e4d
AV		 7104 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7105 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 7106
7107 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
7108 sizeof(ha->fw_seriallink_options24));
7109
7110 /* save HBA serial number */
7111 ha->serial0 = icb->port_name[5];
7112 ha->serial1 = icb->port_name[6];
7113 ha->serial2 = icb->port_name[7];
e315cd28
AC		 7114 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7115 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 7116
ad950360 7117 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 7118
0107109e
AV		 7119 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7120
7121 /* Set minimum login_timeout to 4 seconds. */
7122 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7123 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7124 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7125 nv->login_timeout = cpu_to_le16(4);
0107109e 7126 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 7127
00a537b8
AV		 7128 /* Set minimum RATOV to 100 tenths of a second. */
7129 ha->r_a_tov = 100;
0107109e
AV		 7130
7131 ha->loop_reset_delay = nv->reset_delay;
7132
7133 /* Link Down Timeout = 0:
7134 *
7135 * When Port Down timer expires we will start returning
7136 * I/O's to OS with "DID_NO_CONNECT".
7137 *
7138 * Link Down Timeout != 0:
7139 *
7140 * The driver waits for the link to come up after link down
7141 * before returning I/Os to OS with "DID_NO_CONNECT".
7142 */
7143 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7144 ha->loop_down_abort_time =
7145 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7146 } else {
7147 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7148 ha->loop_down_abort_time =
7149 (LOOP_DOWN_TIME - ha->link_down_timeout);
7150 }
7151
7152 /* Need enough time to try and get the port back. */
7153 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7154 if (qlport_down_retry)
7155 ha->port_down_retry_count = qlport_down_retry;
7156
7157 /* Set login_retry_count */
7158 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7159 if (ha->port_down_retry_count ==
7160 le16_to_cpu(nv->port_down_retry_count) &&
7161 ha->port_down_retry_count > 3)
7162 ha->login_retry_count = ha->port_down_retry_count;
7163 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7164 ha->login_retry_count = ha->port_down_retry_count;
7165 if (ql2xloginretrycount)
7166 ha->login_retry_count = ql2xloginretrycount;
7167
8777e431
QT		 7168 /* N2N: driver will initiate Login instead of FW */
7169 icb->firmware_options_3 |= BIT_8;
7170
4fdfefe5 7171 /* Enable ZIO. */
e315cd28 7172 if (!vha->flags.init_done) {
4fdfefe5
AV		 7173 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7174 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7175 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7176 le16_to_cpu(icb->interrupt_delay_timer): 2;
7177 }
ad950360 7178 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 7179 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
4fdfefe5 7180 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 7181 ha->zio_mode = QLA_ZIO_MODE_6;
7182
7c3df132 7183 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 7184 "ZIO mode %d enabled; timer delay (%d us).\n",
7185 ha->zio_mode, ha->zio_timer * 100);
7186
7187 icb->firmware_options_2 |= cpu_to_le32(
7188 (uint32_t)ha->zio_mode);
7189 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
4fdfefe5
AV		 7190 }
7191
4e08df3f 7192 if (rval) {
7c3df132
SK		 7193 ql_log(ql_log_warn, vha, 0x0070,
7194 "NVRAM configuration failed.\n");
4e08df3f
DM		 7195 }
7196 return (rval);
0107109e
AV		 7197}
7198
4243c115
SC		 7199uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
7200{
7201 struct qla27xx_image_status pri_image_status, sec_image_status;
7202 uint8_t valid_pri_image, valid_sec_image;
7203 uint32_t *wptr;
7204 uint32_t cnt, chksum, size;
7205 struct qla_hw_data *ha = vha->hw;
7206
7207 valid_pri_image = valid_sec_image = 1;
7208 ha->active_image = 0;
7209 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
7210
7211 if (!ha->flt_region_img_status_pri) {
7212 valid_pri_image = 0;
7213 goto check_sec_image;
7214 }
7215
7216 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
7217 ha->flt_region_img_status_pri, size);
7218
7219 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
7220 ql_dbg(ql_dbg_init, vha, 0x018b,
7221 "Primary image signature (0x%x) not valid\n",
7222 pri_image_status.signature);
7223 valid_pri_image = 0;
7224 goto check_sec_image;
7225 }
7226
7227 wptr = (uint32_t *)(&pri_image_status);
7228 cnt = size;
7229
da08ef5c
JC		 7230 for (chksum = 0; cnt--; wptr++)
7231 chksum += le32_to_cpu(*wptr);
41dc529a 7232
4243c115
SC		 7233 if (chksum) {
7234 ql_dbg(ql_dbg_init, vha, 0x018c,
7235 "Checksum validation failed for primary image (0x%x)\n",
7236 chksum);
7237 valid_pri_image = 0;
7238 }
7239
7240check_sec_image:
7241 if (!ha->flt_region_img_status_sec) {
7242 valid_sec_image = 0;
7243 goto check_valid_image;
7244 }
7245
7246 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
7247 ha->flt_region_img_status_sec, size);
7248
7249 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
7250 ql_dbg(ql_dbg_init, vha, 0x018d,
7251 "Secondary image signature(0x%x) not valid\n",
7252 sec_image_status.signature);
7253 valid_sec_image = 0;
7254 goto check_valid_image;
7255 }
7256
7257 wptr = (uint32_t *)(&sec_image_status);
7258 cnt = size;
da08ef5c
JC		 7259 for (chksum = 0; cnt--; wptr++)
7260 chksum += le32_to_cpu(*wptr);
4243c115
SC		 7261 if (chksum) {
7262 ql_dbg(ql_dbg_init, vha, 0x018e,
7263 "Checksum validation failed for secondary image (0x%x)\n",
7264 chksum);
7265 valid_sec_image = 0;
7266 }
7267
7268check_valid_image:
7269 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
7270 ha->active_image = QLA27XX_PRIMARY_IMAGE;
7271 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
7272 if (!ha->active_image ||
7273 pri_image_status.generation_number <
7274 sec_image_status.generation_number)
7275 ha->active_image = QLA27XX_SECONDARY_IMAGE;
7276 }
7277
22ebde16 7278 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x018f, "%s image\n",
4243c115
SC		 7279 ha->active_image == 0 ? "default bootld and fw" :
7280 ha->active_image == 1 ? "primary" :
7281 ha->active_image == 2 ? "secondary" :
7282 "Invalid");
7283
7284 return ha->active_image;
7285}
7286
413975a0 7287static int
cbc8eb67
AV		 7288qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
7289 uint32_t faddr)
d1c61909 7290{
73208dfd 7291 int rval = QLA_SUCCESS;
d1c61909 7292 int segments, fragment;
d1c61909
AV		 7293 uint32_t *dcode, dlen;
7294 uint32_t risc_addr;
7295 uint32_t risc_size;
7296 uint32_t i;
e315cd28 7297 struct qla_hw_data *ha = vha->hw;
73208dfd 7298 struct req_que *req = ha->req_q_map[0];
eaac30be 7299
7c3df132 7300 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 7301 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 7302
d1c61909
AV		 7303 rval = QLA_SUCCESS;
7304
7305 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7306 dcode = (uint32_t *)req->ring;
d1c61909
AV		 7307 *srisc_addr = 0;
7308
4243c115
SC		 7309 if (IS_QLA27XX(ha) &&
7310 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
7311 faddr = ha->flt_region_fw_sec;
7312
d1c61909 7313 /* Validate firmware image by checking version. */
e315cd28 7314 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 7315 for (i = 0; i < 4; i++)
7316 dcode[i] = be32_to_cpu(dcode[i]);
7317 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7318 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7319 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7320 dcode[3] == 0)) {
7c3df132
SK		 7321 ql_log(ql_log_fatal, vha, 0x008c,
7322 "Unable to verify the integrity of flash firmware "
7323 "image.\n");
7324 ql_log(ql_log_fatal, vha, 0x008d,
7325 "Firmware data: %08x %08x %08x %08x.\n",
7326 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 7327
7328 return QLA_FUNCTION_FAILED;
7329 }
7330
7331 while (segments && rval == QLA_SUCCESS) {
7332 /* Read segment's load information. */
e315cd28 7333 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 7334
7335 risc_addr = be32_to_cpu(dcode[2]);
7336 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7337 risc_size = be32_to_cpu(dcode[3]);
7338
7339 fragment = 0;
7340 while (risc_size > 0 && rval == QLA_SUCCESS) {
7341 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7342 if (dlen > risc_size)
7343 dlen = risc_size;
7344
7c3df132
SK		 7345 ql_dbg(ql_dbg_init, vha, 0x008e,
7346 "Loading risc segment@ risc addr %x "
7347 "number of dwords 0x%x offset 0x%x.\n",
7348 risc_addr, dlen, faddr);
d1c61909 7349
e315cd28 7350 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 7351 for (i = 0; i < dlen; i++)
7352 dcode[i] = swab32(dcode[i]);
7353
73208dfd 7354 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 7355 dlen);
7356 if (rval) {
7c3df132
SK		 7357 ql_log(ql_log_fatal, vha, 0x008f,
7358 "Failed to load segment %d of firmware.\n",
7359 fragment);
f261f7af 7360 return QLA_FUNCTION_FAILED;
d1c61909
AV		 7361 }
7362
7363 faddr += dlen;
7364 risc_addr += dlen;
7365 risc_size -= dlen;
7366 fragment++;
7367 }
7368
7369 /* Next segment. */
7370 segments--;
7371 }
7372
f73cb695
CD		 7373 if (!IS_QLA27XX(ha))
7374 return rval;
7375
7376 if (ha->fw_dump_template)
7377 vfree(ha->fw_dump_template);
7378 ha->fw_dump_template = NULL;
7379 ha->fw_dump_template_len = 0;
7380
7381 ql_dbg(ql_dbg_init, vha, 0x0161,
7382 "Loading fwdump template from %x\n", faddr);
7383 qla24xx_read_flash_data(vha, dcode, faddr, 7);
7384 risc_size = be32_to_cpu(dcode[2]);
7385 ql_dbg(ql_dbg_init, vha, 0x0162,
7386 "-> array size %x dwords\n", risc_size);
7387 if (risc_size == 0 || risc_size == ~0)
7388 goto default_template;
7389
7390 dlen = (risc_size - 8) * sizeof(*dcode);
7391 ql_dbg(ql_dbg_init, vha, 0x0163,
7392 "-> template allocating %x bytes...\n", dlen);
7393 ha->fw_dump_template = vmalloc(dlen);
7394 if (!ha->fw_dump_template) {
7395 ql_log(ql_log_warn, vha, 0x0164,
7396 "Failed fwdump template allocate %x bytes.\n", risc_size);
7397 goto default_template;
7398 }
7399
7400 faddr += 7;
7401 risc_size -= 8;
7402 dcode = ha->fw_dump_template;
7403 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
7404 for (i = 0; i < risc_size; i++)
7405 dcode[i] = le32_to_cpu(dcode[i]);
7406
7407 if (!qla27xx_fwdt_template_valid(dcode)) {
7408 ql_log(ql_log_warn, vha, 0x0165,
7409 "Failed fwdump template validate\n");
7410 goto default_template;
7411 }
7412
7413 dlen = qla27xx_fwdt_template_size(dcode);
7414 ql_dbg(ql_dbg_init, vha, 0x0166,
7415 "-> template size %x bytes\n", dlen);
7416 if (dlen > risc_size * sizeof(*dcode)) {
7417 ql_log(ql_log_warn, vha, 0x0167,
4fae52b5 7418 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7419 (size_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 7420 goto default_template;
7421 }
7422 ha->fw_dump_template_len = dlen;
7423 return rval;
7424
7425default_template:
7426 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
7427 if (ha->fw_dump_template)
7428 vfree(ha->fw_dump_template);
7429 ha->fw_dump_template = NULL;
7430 ha->fw_dump_template_len = 0;
7431
7432 dlen = qla27xx_fwdt_template_default_size();
7433 ql_dbg(ql_dbg_init, vha, 0x0169,
7434 "-> template allocating %x bytes...\n", dlen);
7435 ha->fw_dump_template = vmalloc(dlen);
7436 if (!ha->fw_dump_template) {
7437 ql_log(ql_log_warn, vha, 0x016a,
7438 "Failed fwdump template allocate %x bytes.\n", risc_size);
7439 goto failed_template;
7440 }
7441
7442 dcode = ha->fw_dump_template;
7443 risc_size = dlen / sizeof(*dcode);
7444 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
7445 for (i = 0; i < risc_size; i++)
7446 dcode[i] = be32_to_cpu(dcode[i]);
7447
7448 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7449 ql_log(ql_log_warn, vha, 0x016b,
7450 "Failed fwdump template validate\n");
7451 goto failed_template;
7452 }
7453
7454 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7455 ql_dbg(ql_dbg_init, vha, 0x016c,
7456 "-> template size %x bytes\n", dlen);
7457 ha->fw_dump_template_len = dlen;
7458 return rval;
7459
7460failed_template:
7461 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
7462 if (ha->fw_dump_template)
7463 vfree(ha->fw_dump_template);
7464 ha->fw_dump_template = NULL;
7465 ha->fw_dump_template_len = 0;
d1c61909
AV		 7466 return rval;
7467}
7468
e9454a88 7469#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 7470
0107109e 7471int
e315cd28 7472qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 7473{
7474 int rval;
7475 int i, fragment;
7476 uint16_t *wcode, *fwcode;
7477 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
7478 struct fw_blob *blob;
e315cd28 7479 struct qla_hw_data *ha = vha->hw;
73208dfd 7480 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 7481
7482 /* Load firmware blob. */
e315cd28 7483 blob = qla2x00_request_firmware(vha);
5433383e 7484 if (!blob) {
7c3df132 7485 ql_log(ql_log_info, vha, 0x0083,
94bcf830 7486 "Firmware image unavailable.\n");
7c3df132
SK		 7487 ql_log(ql_log_info, vha, 0x0084,
7488 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 7489 return QLA_FUNCTION_FAILED;
7490 }
7491
7492 rval = QLA_SUCCESS;
7493
73208dfd 7494 wcode = (uint16_t *)req->ring;
5433383e
AV		 7495 *srisc_addr = 0;
7496 fwcode = (uint16_t *)blob->fw->data;
7497 fwclen = 0;
7498
7499 /* Validate firmware image by checking version. */
7500 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 7501 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 7502 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 7503 blob->fw->size);
7504 goto fail_fw_integrity;
7505 }
7506 for (i = 0; i < 4; i++)
7507 wcode[i] = be16_to_cpu(fwcode[i + 4]);
7508 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
7509 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
7510 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 7511 ql_log(ql_log_fatal, vha, 0x0086,
7512 "Unable to verify integrity of firmware image.\n");
7513 ql_log(ql_log_fatal, vha, 0x0087,
7514 "Firmware data: %04x %04x %04x %04x.\n",
7515 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 7516 goto fail_fw_integrity;
7517 }
7518
7519 seg = blob->segs;
7520 while (*seg && rval == QLA_SUCCESS) {
7521 risc_addr = *seg;
7522 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
7523 risc_size = be16_to_cpu(fwcode[3]);
7524
7525 /* Validate firmware image size. */
7526 fwclen += risc_size * sizeof(uint16_t);
7527 if (blob->fw->size < fwclen) {
7c3df132 7528 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 7529 "Unable to verify integrity of firmware image "
5b5e0928 7530 "(%zd).\n", blob->fw->size);
5433383e
AV		 7531 goto fail_fw_integrity;
7532 }
7533
7534 fragment = 0;
7535 while (risc_size > 0 && rval == QLA_SUCCESS) {
7536 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
7537 if (wlen > risc_size)
7538 wlen = risc_size;
7c3df132
SK		 7539 ql_dbg(ql_dbg_init, vha, 0x0089,
7540 "Loading risc segment@ risc addr %x number of "
7541 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 7542
7543 for (i = 0; i < wlen; i++)
7544 wcode[i] = swab16(fwcode[i]);
7545
73208dfd 7546 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 7547 wlen);
7548 if (rval) {
7c3df132
SK		 7549 ql_log(ql_log_fatal, vha, 0x008a,
7550 "Failed to load segment %d of firmware.\n",
7551 fragment);
5433383e
AV		 7552 break;
7553 }
7554
7555 fwcode += wlen;
7556 risc_addr += wlen;
7557 risc_size -= wlen;
7558 fragment++;
7559 }
7560
7561 /* Next segment. */
7562 seg++;
7563 }
7564 return rval;
7565
7566fail_fw_integrity:
7567 return QLA_FUNCTION_FAILED;
7568}
7569
eaac30be
AV		 7570static int
7571qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 7572{
7573 int rval;
7574 int segments, fragment;
7575 uint32_t *dcode, dlen;
7576 uint32_t risc_addr;
7577 uint32_t risc_size;
7578 uint32_t i;
5433383e 7579 struct fw_blob *blob;
f73cb695
CD		 7580 const uint32_t *fwcode;
7581 uint32_t fwclen;
e315cd28 7582 struct qla_hw_data *ha = vha->hw;
73208dfd 7583 struct req_que *req = ha->req_q_map[0];
0107109e 7584
5433383e 7585 /* Load firmware blob. */
e315cd28 7586 blob = qla2x00_request_firmware(vha);
5433383e 7587 if (!blob) {
7c3df132 7588 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 7589 "Firmware image unavailable.\n");
7c3df132
SK		 7590 ql_log(ql_log_warn, vha, 0x0091,
7591 "Firmware images can be retrieved from: "
7592 QLA_FW_URL ".\n");
d1c61909 7593
eaac30be 7594 return QLA_FUNCTION_FAILED;
0107109e
AV		 7595 }
7596
cfb0919c
CD		 7597 ql_dbg(ql_dbg_init, vha, 0x0092,
7598 "FW: Loading via request-firmware.\n");
eaac30be 7599
0107109e
AV		 7600 rval = QLA_SUCCESS;
7601
7602 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7603 dcode = (uint32_t *)req->ring;
0107109e 7604 *srisc_addr = 0;
5433383e 7605 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 7606 fwclen = 0;
7607
7608 /* Validate firmware image by checking version. */
5433383e 7609 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 7610 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 7611 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 7612 blob->fw->size);
f73cb695 7613 return QLA_FUNCTION_FAILED;
0107109e
AV		 7614 }
7615 for (i = 0; i < 4; i++)
7616 dcode[i] = be32_to_cpu(fwcode[i + 4]);
7617 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7618 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7619 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7620 dcode[3] == 0)) {
7c3df132 7621 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 7622 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 7623 blob->fw->size);
7624 ql_log(ql_log_fatal, vha, 0x0095,
7625 "Firmware data: %08x %08x %08x %08x.\n",
7626 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 7627 return QLA_FUNCTION_FAILED;
0107109e
AV		 7628 }
7629
7630 while (segments && rval == QLA_SUCCESS) {
7631 risc_addr = be32_to_cpu(fwcode[2]);
7632 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7633 risc_size = be32_to_cpu(fwcode[3]);
7634
7635 /* Validate firmware image size. */
7636 fwclen += risc_size * sizeof(uint32_t);
5433383e 7637 if (blob->fw->size < fwclen) {
7c3df132 7638 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 7639 "Unable to verify integrity of firmware image "
5b5e0928 7640 "(%zd).\n", blob->fw->size);
f73cb695 7641 return QLA_FUNCTION_FAILED;
0107109e
AV		 7642 }
7643
7644 fragment = 0;
7645 while (risc_size > 0 && rval == QLA_SUCCESS) {
7646 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7647 if (dlen > risc_size)
7648 dlen = risc_size;
7649
7c3df132
SK		 7650 ql_dbg(ql_dbg_init, vha, 0x0097,
7651 "Loading risc segment@ risc addr %x "
7652 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 7653
7654 for (i = 0; i < dlen; i++)
7655 dcode[i] = swab32(fwcode[i]);
7656
73208dfd 7657 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 7658 dlen);
0107109e 7659 if (rval) {
7c3df132
SK		 7660 ql_log(ql_log_fatal, vha, 0x0098,
7661 "Failed to load segment %d of firmware.\n",
7662 fragment);
f261f7af 7663 return QLA_FUNCTION_FAILED;
0107109e
AV		 7664 }
7665
7666 fwcode += dlen;
7667 risc_addr += dlen;
7668 risc_size -= dlen;
7669 fragment++;
7670 }
7671
7672 /* Next segment. */
7673 segments--;
7674 }
f73cb695
CD		 7675
7676 if (!IS_QLA27XX(ha))
7677 return rval;
7678
7679 if (ha->fw_dump_template)
7680 vfree(ha->fw_dump_template);
7681 ha->fw_dump_template = NULL;
7682 ha->fw_dump_template_len = 0;
7683
7684 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 7685 "Loading fwdump template from %x\n",
7686 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 7687 risc_size = be32_to_cpu(fwcode[2]);
7688 ql_dbg(ql_dbg_init, vha, 0x172,
7689 "-> array size %x dwords\n", risc_size);
7690 if (risc_size == 0 || risc_size == ~0)
7691 goto default_template;
7692
7693 dlen = (risc_size - 8) * sizeof(*fwcode);
7694 ql_dbg(ql_dbg_init, vha, 0x0173,
7695 "-> template allocating %x bytes...\n", dlen);
7696 ha->fw_dump_template = vmalloc(dlen);
7697 if (!ha->fw_dump_template) {
7698 ql_log(ql_log_warn, vha, 0x0174,
7699 "Failed fwdump template allocate %x bytes.\n", risc_size);
7700 goto default_template;
7701 }
7702
7703 fwcode += 7;
7704 risc_size -= 8;
7705 dcode = ha->fw_dump_template;
7706 for (i = 0; i < risc_size; i++)
7707 dcode[i] = le32_to_cpu(fwcode[i]);
7708
7709 if (!qla27xx_fwdt_template_valid(dcode)) {
7710 ql_log(ql_log_warn, vha, 0x0175,
7711 "Failed fwdump template validate\n");
7712 goto default_template;
7713 }
7714
7715 dlen = qla27xx_fwdt_template_size(dcode);
7716 ql_dbg(ql_dbg_init, vha, 0x0176,
7717 "-> template size %x bytes\n", dlen);
7718 if (dlen > risc_size * sizeof(*fwcode)) {
7719 ql_log(ql_log_warn, vha, 0x0177,
4fae52b5 7720 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7721 (size_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 7722 goto default_template;
7723 }
7724 ha->fw_dump_template_len = dlen;
0107109e
AV		 7725 return rval;
7726
f73cb695
CD		 7727default_template:
7728 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
7729 if (ha->fw_dump_template)
7730 vfree(ha->fw_dump_template);
7731 ha->fw_dump_template = NULL;
7732 ha->fw_dump_template_len = 0;
7733
7734 dlen = qla27xx_fwdt_template_default_size();
7735 ql_dbg(ql_dbg_init, vha, 0x0179,
7736 "-> template allocating %x bytes...\n", dlen);
7737 ha->fw_dump_template = vmalloc(dlen);
7738 if (!ha->fw_dump_template) {
7739 ql_log(ql_log_warn, vha, 0x017a,
7740 "Failed fwdump template allocate %x bytes.\n", risc_size);
7741 goto failed_template;
7742 }
7743
7744 dcode = ha->fw_dump_template;
7745 risc_size = dlen / sizeof(*fwcode);
7746 fwcode = qla27xx_fwdt_template_default();
7747 for (i = 0; i < risc_size; i++)
7748 dcode[i] = be32_to_cpu(fwcode[i]);
7749
7750 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7751 ql_log(ql_log_warn, vha, 0x017b,
7752 "Failed fwdump template validate\n");
7753 goto failed_template;
7754 }
7755
7756 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7757 ql_dbg(ql_dbg_init, vha, 0x017c,
7758 "-> template size %x bytes\n", dlen);
7759 ha->fw_dump_template_len = dlen;
7760 return rval;
7761
7762failed_template:
7763 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
7764 if (ha->fw_dump_template)
7765 vfree(ha->fw_dump_template);
7766 ha->fw_dump_template = NULL;
7767 ha->fw_dump_template_len = 0;
7768 return rval;
0107109e 7769}
18c6c127 7770
eaac30be
AV		 7771int
7772qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7773{
7774 int rval;
7775
e337d907
AV		 7776 if (ql2xfwloadbin == 1)
7777 return qla81xx_load_risc(vha, srisc_addr);
7778
eaac30be
AV		 7779 /*
7780 * FW Load priority:
7781 * 1) Firmware via request-firmware interface (.bin file).
7782 * 2) Firmware residing in flash.
7783 */
7784 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7785 if (rval == QLA_SUCCESS)
7786 return rval;
7787
cbc8eb67
AV		 7788 return qla24xx_load_risc_flash(vha, srisc_addr,
7789 vha->hw->flt_region_fw);
eaac30be
AV		 7790}
7791
7792int
7793qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7794{
7795 int rval;
cbc8eb67 7796 struct qla_hw_data *ha = vha->hw;
eaac30be 7797
e337d907 7798 if (ql2xfwloadbin == 2)
cbc8eb67 7799 goto try_blob_fw;
e337d907 7800
eaac30be
AV		 7801 /*
7802 * FW Load priority:
7803 * 1) Firmware residing in flash.
7804 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 7805 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 7806 */
cbc8eb67 7807 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 7808 if (rval == QLA_SUCCESS)
7809 return rval;
7810
cbc8eb67
AV		 7811try_blob_fw:
7812 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7813 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
7814 return rval;
7815
7c3df132
SK		 7816 ql_log(ql_log_info, vha, 0x0099,
7817 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 7818 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
7819 if (rval != QLA_SUCCESS)
7820 return rval;
7821
7c3df132 7822 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 7823 ha->flags.running_gold_fw = 1;
cbc8eb67 7824 return rval;
eaac30be
AV		 7825}
7826
18c6c127 7827void
e315cd28 7828qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 7829{
7830 int ret, retries;
e315cd28 7831 struct qla_hw_data *ha = vha->hw;
18c6c127 7832
85880801
AV		 7833 if (ha->flags.pci_channel_io_perm_failure)
7834 return;
e428924c 7835 if (!IS_FWI2_CAPABLE(ha))
18c6c127 7836 return;
75edf81d
AV		 7837 if (!ha->fw_major_version)
7838 return;
ec7193e2
QT		 7839 if (!ha->flags.fw_started)
7840 return;
18c6c127 7841
e315cd28 7842 ret = qla2x00_stop_firmware(vha);
7c7f1f29 7843 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 7844 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 7845 ha->isp_ops->reset_chip(vha);
7846 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 7847 continue;
e315cd28 7848 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 7849 continue;
7c3df132
SK		 7850 ql_log(ql_log_info, vha, 0x8015,
7851 "Attempting retry of stop-firmware command.\n");
e315cd28 7852 ret = qla2x00_stop_firmware(vha);
18c6c127 7853 }
ec7193e2 7854
4b60c827 7855 QLA_FW_STOPPED(ha);
ec7193e2 7856 ha->flags.fw_init_done = 0;
18c6c127 7857}
2c3dfe3f
SJ		 7858
7859int
e315cd28 7860qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 7861{
7862 int rval = QLA_SUCCESS;
0b91d116 7863 int rval2;
2c3dfe3f 7864 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 7865 struct qla_hw_data *ha = vha->hw;
7866 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 7867 struct req_que *req;
7868 struct rsp_que *rsp;
2c3dfe3f 7869
e315cd28 7870 if (!vha->vp_idx)
2c3dfe3f
SJ		 7871 return -EINVAL;
7872
e315cd28 7873 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 7874 if (vha->qpair)
7875 req = vha->qpair->req;
67c2e93a 7876 else
d7459527 7877 req = ha->req_q_map[0];
67c2e93a
AC		 7878 rsp = req->rsp;
7879
2c3dfe3f 7880 if (rval == QLA_SUCCESS) {
e315cd28 7881 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 7882 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 7883 }
7884
e315cd28 7885 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 7886
7887 /* Login to SNS first */
0b91d116
CD		 7888 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
7889 BIT_1);
7890 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
7891 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
7892 ql_dbg(ql_dbg_init, vha, 0x0120,
7893 "Failed SNS login: loop_id=%x, rval2=%d\n",
7894 NPH_SNS, rval2);
7895 else
7896 ql_dbg(ql_dbg_init, vha, 0x0103,
7897 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
7898 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
7899 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 7900 return (QLA_FUNCTION_FAILED);
7901 }
7902
e315cd28
AC		 7903 atomic_set(&vha->loop_down_timer, 0);
7904 atomic_set(&vha->loop_state, LOOP_UP);
7905 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7906 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
7907 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 7908
7909 return rval;
7910}
4d4df193
HK		 7911
7912/* 84XX Support **************************************************************/
7913
7914static LIST_HEAD(qla_cs84xx_list);
7915static DEFINE_MUTEX(qla_cs84xx_mutex);
7916
7917static struct qla_chip_state_84xx *
e315cd28 7918qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 7919{
7920 struct qla_chip_state_84xx *cs84xx;
e315cd28 7921 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7922
7923 mutex_lock(&qla_cs84xx_mutex);
7924
7925 /* Find any shared 84xx chip. */
7926 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
7927 if (cs84xx->bus == ha->pdev->bus) {
7928 kref_get(&cs84xx->kref);
7929 goto done;
7930 }
7931 }
7932
7933 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
7934 if (!cs84xx)
7935 goto done;
7936
7937 kref_init(&cs84xx->kref);
7938 spin_lock_init(&cs84xx->access_lock);
7939 mutex_init(&cs84xx->fw_update_mutex);
7940 cs84xx->bus = ha->pdev->bus;
7941
7942 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
7943done:
7944 mutex_unlock(&qla_cs84xx_mutex);
7945 return cs84xx;
7946}
7947
7948static void
7949__qla84xx_chip_release(struct kref *kref)
7950{
7951 struct qla_chip_state_84xx *cs84xx =
7952 container_of(kref, struct qla_chip_state_84xx, kref);
7953
7954 mutex_lock(&qla_cs84xx_mutex);
7955 list_del(&cs84xx->list);
7956 mutex_unlock(&qla_cs84xx_mutex);
7957 kfree(cs84xx);
7958}
7959
7960void
e315cd28 7961qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 7962{
e315cd28 7963 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7964 if (ha->cs84xx)
7965 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
7966}
7967
7968static int
e315cd28 7969qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 7970{
7971 int rval;
7972 uint16_t status[2];
e315cd28 7973 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7974
7975 mutex_lock(&ha->cs84xx->fw_update_mutex);
7976
e315cd28 7977 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 7978
7979 mutex_unlock(&ha->cs84xx->fw_update_mutex);
7980
7981 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
7982 QLA_SUCCESS;
7983}
3a03eb79
AV		 7984
7985/* 81XX Support **************************************************************/
7986
7987int
7988qla81xx_nvram_config(scsi_qla_host_t *vha)
7989{
7990 int rval;
7991 struct init_cb_81xx *icb;
7992 struct nvram_81xx *nv;
7993 uint32_t *dptr;
7994 uint8_t *dptr1, *dptr2;
7995 uint32_t chksum;
7996 uint16_t cnt;
7997 struct qla_hw_data *ha = vha->hw;
7998
7999 rval = QLA_SUCCESS;
8000 icb = (struct init_cb_81xx *)ha->init_cb;
8001 nv = ha->nvram;
8002
8003 /* Determine NVRAM starting address. */
8004 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 8005 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 8006 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
8007 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 8008
8009 /* Get VPD data into cache */
8010 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 8011 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
8012 ha->vpd_size);
3a03eb79
AV		 8013
8014 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 8015 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 8016 ha->nvram_size);
3d79038f 8017 dptr = (uint32_t *)nv;
da08ef5c
JC		 8018 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
8019 chksum += le32_to_cpu(*dptr);
3a03eb79 8020
7c3df132
SK		 8021 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
8022 "Contents of NVRAM:\n");
8023 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
8024 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 8025
8026 /* Bad NVRAM data, set defaults parameters. */
8027 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
8028 || nv->id[3] != ' ' ||
ad950360 8029 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 8030 /* Reset NVRAM data. */
7c3df132 8031 ql_log(ql_log_info, vha, 0x0073,
9e336520 8032 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 8033 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 8034 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 8035 ql_log(ql_log_info, vha, 0x0074,
8036 "Falling back to functioning (yet invalid -- WWPN) "
8037 "defaults.\n");
3a03eb79
AV		 8038
8039 /*
8040 * Set default initialization control block.
8041 */
8042 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 8043 nv->nvram_version = cpu_to_le16(ICB_VERSION);
8044 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 8045 nv->frame_payload_size = 2048;
ad950360
BVA		 8046 nv->execution_throttle = cpu_to_le16(0xFFFF);
8047 nv->exchange_count = cpu_to_le16(0);
3a03eb79 8048 nv->port_name[0] = 0x21;
f73cb695 8049 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 8050 nv->port_name[2] = 0x00;
8051 nv->port_name[3] = 0xe0;
8052 nv->port_name[4] = 0x8b;
8053 nv->port_name[5] = 0x1c;
8054 nv->port_name[6] = 0x55;
8055 nv->port_name[7] = 0x86;
8056 nv->node_name[0] = 0x20;
8057 nv->node_name[1] = 0x00;
8058 nv->node_name[2] = 0x00;
8059 nv->node_name[3] = 0xe0;
8060 nv->node_name[4] = 0x8b;
8061 nv->node_name[5] = 0x1c;
8062 nv->node_name[6] = 0x55;
8063 nv->node_name[7] = 0x86;
ad950360
BVA		 8064 nv->login_retry_count = cpu_to_le16(8);
8065 nv->interrupt_delay_timer = cpu_to_le16(0);
8066 nv->login_timeout = cpu_to_le16(0);
3a03eb79 8067 nv->firmware_options_1 =
ad950360
BVA		 8068 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
8069 nv->firmware_options_2 = cpu_to_le32(2 << 4);
8070 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
8071 nv->firmware_options_3 = cpu_to_le32(2 << 13);
8072 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
8073 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 8074 nv->reset_delay = 5;
ad950360
BVA		 8075 nv->max_luns_per_target = cpu_to_le16(128);
8076 nv->port_down_retry_count = cpu_to_le16(30);
8077 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 8078 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 8079 nv->enode_mac[1] = 0xC0;
8080 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 8081 nv->enode_mac[3] = 0x04;
8082 nv->enode_mac[4] = 0x05;
f73cb695 8083 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 8084
8085 rval = 1;
8086 }
8087
9e522cd8
AE		 8088 if (IS_T10_PI_CAPABLE(ha))
8089 nv->frame_payload_size &= ~7;
8090
aa230bc5
AE		 8091 qlt_81xx_config_nvram_stage1(vha, nv);
8092
3a03eb79 8093 /* Reset Initialization control block */
773120e4 8094 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 8095
8096 /* Copy 1st segment. */
8097 dptr1 = (uint8_t *)icb;
8098 dptr2 = (uint8_t *)&nv->version;
8099 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
8100 while (cnt--)
8101 *dptr1++ = *dptr2++;
8102
8103 icb->login_retry_count = nv->login_retry_count;
8104
8105 /* Copy 2nd segment. */
8106 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
8107 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
8108 cnt = (uint8_t *)&icb->reserved_5 -
8109 (uint8_t *)&icb->interrupt_delay_timer;
8110 while (cnt--)
8111 *dptr1++ = *dptr2++;
8112
8113 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
8114 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
8115 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 8116 icb->enode_mac[0] = 0x00;
8117 icb->enode_mac[1] = 0xC0;
8118 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 8119 icb->enode_mac[3] = 0x04;
8120 icb->enode_mac[4] = 0x05;
f73cb695 8121 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 8122 }
8123
b64b0e8f
AV		 8124 /* Use extended-initialization control block. */
8125 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
0eaaca4c 8126 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
3a03eb79
AV		 8127 /*
8128 * Setup driver NVRAM options.
8129 */
8130 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 8131 "QLE8XXX");
3a03eb79 8132
aa230bc5
AE		 8133 qlt_81xx_config_nvram_stage2(vha, icb);
8134
3a03eb79 8135 /* Use alternate WWN? */
ad950360 8136 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 8137 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
8138 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
8139 }
8140
8141 /* Prepare nodename */
ad950360 8142 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 8143 /*
8144 * Firmware will apply the following mask if the nodename was
8145 * not provided.
8146 */
8147 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
8148 icb->node_name[0] &= 0xF0;
8149 }
8150
8151 /* Set host adapter parameters. */
8152 ha->flags.disable_risc_code_load = 0;
8153 ha->flags.enable_lip_reset = 0;
8154 ha->flags.enable_lip_full_login =
8155 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
8156 ha->flags.enable_target_reset =
8157 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
8158 ha->flags.enable_led_scheme = 0;
8159 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
8160
8161 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
8162 (BIT_6 | BIT_5 | BIT_4)) >> 4;
8163
8164 /* save HBA serial number */
8165 ha->serial0 = icb->port_name[5];
8166 ha->serial1 = icb->port_name[6];
8167 ha->serial2 = icb->port_name[7];
8168 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
8169 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
8170
ad950360 8171 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 8172
8173 ha->retry_count = le16_to_cpu(nv->login_retry_count);
8174
8175 /* Set minimum login_timeout to 4 seconds. */
8176 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
8177 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
8178 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 8179 nv->login_timeout = cpu_to_le16(4);
3a03eb79 8180 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 8181
8182 /* Set minimum RATOV to 100 tenths of a second. */
8183 ha->r_a_tov = 100;
8184
8185 ha->loop_reset_delay = nv->reset_delay;
8186
8187 /* Link Down Timeout = 0:
8188 *
7ec0effd 8189 * When Port Down timer expires we will start returning
3a03eb79
AV		 8190 * I/O's to OS with "DID_NO_CONNECT".
8191 *
8192 * Link Down Timeout != 0:
8193 *
8194 * The driver waits for the link to come up after link down
8195 * before returning I/Os to OS with "DID_NO_CONNECT".
8196 */
8197 if (le16_to_cpu(nv->link_down_timeout) == 0) {
8198 ha->loop_down_abort_time =
8199 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
8200 } else {
8201 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
8202 ha->loop_down_abort_time =
8203 (LOOP_DOWN_TIME - ha->link_down_timeout);
8204 }
8205
8206 /* Need enough time to try and get the port back. */
8207 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
8208 if (qlport_down_retry)
8209 ha->port_down_retry_count = qlport_down_retry;
8210
8211 /* Set login_retry_count */
8212 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
8213 if (ha->port_down_retry_count ==
8214 le16_to_cpu(nv->port_down_retry_count) &&
8215 ha->port_down_retry_count > 3)
8216 ha->login_retry_count = ha->port_down_retry_count;
8217 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
8218 ha->login_retry_count = ha->port_down_retry_count;
8219 if (ql2xloginretrycount)
8220 ha->login_retry_count = ql2xloginretrycount;
8221
6246b8a1 8222 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 8223 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 8224 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 8225
3a03eb79
AV		 8226 /* Enable ZIO. */
8227 if (!vha->flags.init_done) {
8228 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
8229 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
8230 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
8231 le16_to_cpu(icb->interrupt_delay_timer): 2;
8232 }
ad950360 8233 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 8234 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
8235 vha->flags.process_response_queue = 0;
8236 if (ha->zio_mode != QLA_ZIO_DISABLED) {
8237 ha->zio_mode = QLA_ZIO_MODE_6;
8238
7c3df132 8239 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 8240 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 8241 ha->zio_mode,
8242 ha->zio_timer * 100);
3a03eb79
AV		 8243
8244 icb->firmware_options_2 |= cpu_to_le32(
8245 (uint32_t)ha->zio_mode);
8246 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
8247 vha->flags.process_response_queue = 1;
8248 }
8249
41dc529a 8250 /* enable RIDA Format2 */
48acad09 8251 icb->firmware_options_3 |= BIT_0;
41dc529a 8252
8777e431
QT		 8253 /* N2N: driver will initiate Login instead of FW */
8254 icb->firmware_options_3 |= BIT_8;
41dc529a 8255
edd05de1
DG		 8256 if (IS_QLA27XX(ha)) {
8257 icb->firmware_options_3 |= BIT_8;
8258 ql_dbg(ql_log_info, vha, 0x0075,
8259 "Enabling direct connection.\n");
8260 }
8261
3a03eb79 8262 if (rval) {
7c3df132
SK		 8263 ql_log(ql_log_warn, vha, 0x0076,
8264 "NVRAM configuration failed.\n");
3a03eb79
AV		 8265 }
8266 return (rval);
8267}
8268
a9083016
GM		 8269int
8270qla82xx_restart_isp(scsi_qla_host_t *vha)
8271{
8272 int status, rval;
a9083016
GM		 8273 struct qla_hw_data *ha = vha->hw;
8274 struct req_que *req = ha->req_q_map[0];
8275 struct rsp_que *rsp = ha->rsp_q_map[0];
8276 struct scsi_qla_host *vp;
feafb7b1 8277 unsigned long flags;
a9083016
GM		 8278
8279 status = qla2x00_init_rings(vha);
8280 if (!status) {
8281 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8282 ha->flags.chip_reset_done = 1;
8283
8284 status = qla2x00_fw_ready(vha);
8285 if (!status) {
a9083016
GM		 8286 /* Issue a marker after FW becomes ready. */
8287 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 8288 vha->flags.online = 1;
7108b76e 8289 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 8290 }
8291
8292 /* if no cable then assume it's good */
8293 if ((vha->device_flags & DFLG_NO_CABLE))
8294 status = 0;
a9083016
GM		 8295 }
8296
8297 if (!status) {
8298 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8299
8300 if (!atomic_read(&vha->loop_down_timer)) {
8301 /*
8302 * Issue marker command only when we are going
8303 * to start the I/O .
8304 */
8305 vha->marker_needed = 1;
8306 }
8307
a9083016
GM		 8308 ha->isp_ops->enable_intrs(ha);
8309
8310 ha->isp_abort_cnt = 0;
8311 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
8312
53296788 8313 /* Update the firmware version */
3173167f 8314 status = qla82xx_check_md_needed(vha);
53296788 8315
a9083016
GM		 8316 if (ha->fce) {
8317 ha->flags.fce_enabled = 1;
8318 memset(ha->fce, 0,
8319 fce_calc_size(ha->fce_bufs));
8320 rval = qla2x00_enable_fce_trace(vha,
8321 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
8322 &ha->fce_bufs);
8323 if (rval) {
cfb0919c 8324 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 8325 "Unable to reinitialize FCE (%d).\n",
8326 rval);
a9083016
GM		 8327 ha->flags.fce_enabled = 0;
8328 }
8329 }
8330
8331 if (ha->eft) {
8332 memset(ha->eft, 0, EFT_SIZE);
8333 rval = qla2x00_enable_eft_trace(vha,
8334 ha->eft_dma, EFT_NUM_BUFFERS);
8335 if (rval) {
cfb0919c 8336 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 8337 "Unable to reinitialize EFT (%d).\n",
8338 rval);
a9083016
GM		 8339 }
8340 }
a9083016
GM		 8341 }
8342
8343 if (!status) {
cfb0919c 8344 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 8345 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 8346
8347 spin_lock_irqsave(&ha->vport_slock, flags);
8348 list_for_each_entry(vp, &ha->vp_list, list) {
8349 if (vp->vp_idx) {
8350 atomic_inc(&vp->vref_count);
8351 spin_unlock_irqrestore(&ha->vport_slock, flags);
8352
a9083016 8353 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 8354
8355 spin_lock_irqsave(&ha->vport_slock, flags);
8356 atomic_dec(&vp->vref_count);
8357 }
a9083016 8358 }
feafb7b1
AE		 8359 spin_unlock_irqrestore(&ha->vport_slock, flags);
8360
a9083016 8361 } else {
cfb0919c 8362 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 8363 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 8364 }
8365
8366 return status;
8367}
8368
3a03eb79 8369void
ae97c91e 8370qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 8371{
ae97c91e
AV		 8372 struct qla_hw_data *ha = vha->hw;
8373
f198cafa
HM		 8374 /* Hold status IOCBs until ABTS response received. */
8375 if (ql2xfwholdabts)
8376 ha->fw_options[3] |= BIT_12;
8377
088d09d4
GM		 8378 /* Set Retry FLOGI in case of P2P connection */
8379 if (ha->operating_mode == P2P) {
8380 ha->fw_options[2] |= BIT_3;
8381 ql_dbg(ql_dbg_disc, vha, 0x2103,
8382 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
8383 __func__, ha->fw_options[2]);
8384 }
8385
41dc529a
QT		 8386 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
8387 if (ql2xmvasynctoatio) {
8388 if (qla_tgt_mode_enabled(vha) ||
8389 qla_dual_mode_enabled(vha))
8390 ha->fw_options[2] |= BIT_11;
8391 else
8392 ha->fw_options[2] &= ~BIT_11;
8393 }
8394
f7e761f5 8395 if (qla_tgt_mode_enabled(vha) ||
2da52737
QT		 8396 qla_dual_mode_enabled(vha)) {
8397 /* FW auto send SCSI status during */
8398 ha->fw_options[1] |= BIT_8;
8399 ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
8400
8401 /* FW perform Exchange validation */
f7e761f5 8402 ha->fw_options[2] |= BIT_4;
2da52737
QT		 8403 } else {
8404 ha->fw_options[1] &= ~BIT_8;
8405 ha->fw_options[10] &= 0x00ff;
8406
f7e761f5 8407 ha->fw_options[2] &= ~BIT_4;
2da52737 8408 }
f7e761f5 8409
41dc529a
QT		 8410 if (ql2xetsenable) {
8411 /* Enable ETS Burst. */
8412 memset(ha->fw_options, 0, sizeof(ha->fw_options));
8413 ha->fw_options[2] |= BIT_9;
8414 }
8415
83548fe2
QT		 8416 ql_dbg(ql_dbg_init, vha, 0x00e9,
8417 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
8418 __func__, ha->fw_options[1], ha->fw_options[2],
8419 ha->fw_options[3], vha->host->active_mode);
ae97c91e 8420
ae97c91e 8421 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 8422}
09ff701a
SR		 8423
8424/*
8425 * qla24xx_get_fcp_prio
8426 * Gets the fcp cmd priority value for the logged in port.
8427 * Looks for a match of the port descriptors within
8428 * each of the fcp prio config entries. If a match is found,
8429 * the tag (priority) value is returned.
8430 *
8431 * Input:
21090cbe 8432 * vha = scsi host structure pointer.
09ff701a
SR		 8433 * fcport = port structure pointer.
8434 *
8435 * Return:
6c452a45 8436 * non-zero (if found)
f28a0a96 8437 * -1 (if not found)
09ff701a
SR		 8438 *
8439 * Context:
8440 * Kernel context
8441 */
f28a0a96 8442static int
09ff701a
SR		 8443qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
8444{
8445 int i, entries;
8446 uint8_t pid_match, wwn_match;
f28a0a96 8447 int priority;
09ff701a
SR		 8448 uint32_t pid1, pid2;
8449 uint64_t wwn1, wwn2;
8450 struct qla_fcp_prio_entry *pri_entry;
8451 struct qla_hw_data *ha = vha->hw;
8452
8453 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 8454 return -1;
09ff701a 8455
f28a0a96 8456 priority = -1;
09ff701a
SR		 8457 entries = ha->fcp_prio_cfg->num_entries;
8458 pri_entry = &ha->fcp_prio_cfg->entry[0];
8459
8460 for (i = 0; i < entries; i++) {
8461 pid_match = wwn_match = 0;
8462
8463 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
8464 pri_entry++;
8465 continue;
8466 }
8467
8468 /* check source pid for a match */
8469 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
8470 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
8471 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
8472 if (pid1 == INVALID_PORT_ID)
8473 pid_match++;
8474 else if (pid1 == pid2)
8475 pid_match++;
8476 }
8477
8478 /* check destination pid for a match */
8479 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
8480 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
8481 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
8482 if (pid1 == INVALID_PORT_ID)
8483 pid_match++;
8484 else if (pid1 == pid2)
8485 pid_match++;
8486 }
8487
8488 /* check source WWN for a match */
8489 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
8490 wwn1 = wwn_to_u64(vha->port_name);
8491 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
8492 if (wwn2 == (uint64_t)-1)
8493 wwn_match++;
8494 else if (wwn1 == wwn2)
8495 wwn_match++;
8496 }
8497
8498 /* check destination WWN for a match */
8499 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
8500 wwn1 = wwn_to_u64(fcport->port_name);
8501 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
8502 if (wwn2 == (uint64_t)-1)
8503 wwn_match++;
8504 else if (wwn1 == wwn2)
8505 wwn_match++;
8506 }
8507
8508 if (pid_match == 2 || wwn_match == 2) {
8509 /* Found a matching entry */
8510 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
8511 priority = pri_entry->tag;
8512 break;
8513 }
8514
8515 pri_entry++;
8516 }
8517
8518 return priority;
8519}
8520
8521/*
8522 * qla24xx_update_fcport_fcp_prio
8523 * Activates fcp priority for the logged in fc port
8524 *
8525 * Input:
21090cbe 8526 * vha = scsi host structure pointer.
09ff701a
SR		 8527 * fcp = port structure pointer.
8528 *
8529 * Return:
8530 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8531 *
8532 * Context:
8533 * Kernel context.
8534 */
8535int
21090cbe 8536qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 8537{
8538 int ret;
f28a0a96 8539 int priority;
09ff701a
SR		 8540 uint16_t mb[5];
8541
21090cbe
MI		 8542 if (fcport->port_type != FCT_TARGET ||
8543 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 8544 return QLA_FUNCTION_FAILED;
8545
21090cbe 8546 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 8547 if (priority < 0)
8548 return QLA_FUNCTION_FAILED;
8549
7ec0effd 8550 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 8551 fcport->fcp_prio = priority & 0xf;
8552 return QLA_SUCCESS;
8553 }
8554
21090cbe 8555 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 8556 if (ret == QLA_SUCCESS) {
8557 if (fcport->fcp_prio != priority)
8558 ql_dbg(ql_dbg_user, vha, 0x709e,
8559 "Updated FCP_CMND priority - value=%d loop_id=%d "
8560 "port_id=%02x%02x%02x.\n", priority,
8561 fcport->loop_id, fcport->d_id.b.domain,
8562 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 8563 fcport->fcp_prio = priority & 0xf;
cfb0919c 8564 } else
7c3df132 8565 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 8566 "Unable to update FCP_CMND priority - ret=0x%x for "
8567 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
8568 fcport->d_id.b.domain, fcport->d_id.b.area,
8569 fcport->d_id.b.al_pa);
09ff701a
SR		 8570 return ret;
8571}
8572
8573/*
8574 * qla24xx_update_all_fcp_prio
8575 * Activates fcp priority for all the logged in ports
8576 *
8577 * Input:
8578 * ha = adapter block pointer.
8579 *
8580 * Return:
8581 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8582 *
8583 * Context:
8584 * Kernel context.
8585 */
8586int
8587qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
8588{
8589 int ret;
8590 fc_port_t *fcport;
8591
8592 ret = QLA_FUNCTION_FAILED;
8593 /* We need to set priority for all logged in ports */
8594 list_for_each_entry(fcport, &vha->vp_fcports, list)
8595 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
8596
8597 return ret;
8598}
d7459527 8599
82de802a
QT		 8600struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
8601 int vp_idx, bool startqp)
d7459527
MH		 8602{
8603 int rsp_id = 0;
8604 int req_id = 0;
8605 int i;
8606 struct qla_hw_data *ha = vha->hw;
8607 uint16_t qpair_id = 0;
8608 struct qla_qpair *qpair = NULL;
8609 struct qla_msix_entry *msix;
8610
8611 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
8612 ql_log(ql_log_warn, vha, 0x00181,
8613 "FW/Driver is not multi-queue capable.\n");
8614 return NULL;
8615 }
8616
c38d1baf 8617 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 8618 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
8619 if (qpair == NULL) {
8620 ql_log(ql_log_warn, vha, 0x0182,
8621 "Failed to allocate memory for queue pair.\n");
8622 return NULL;
8623 }
8624 memset(qpair, 0, sizeof(struct qla_qpair));
8625
8626 qpair->hw = vha->hw;
25ff6af1 8627 qpair->vha = vha;
82de802a
QT		 8628 qpair->qp_lock_ptr = &qpair->qp_lock;
8629 spin_lock_init(&qpair->qp_lock);
af7bb382 8630 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d7459527
MH		 8631
8632 /* Assign available que pair id */
8633 mutex_lock(&ha->mq_lock);
8634 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 8635 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 8636 mutex_unlock(&ha->mq_lock);
8637 ql_log(ql_log_warn, vha, 0x0183,
8638 "No resources to create additional q pair.\n");
8639 goto fail_qid_map;
8640 }
b95b9452 8641 ha->num_qpairs++;
d7459527
MH		 8642 set_bit(qpair_id, ha->qpair_qid_map);
8643 ha->queue_pair_map[qpair_id] = qpair;
8644 qpair->id = qpair_id;
8645 qpair->vp_idx = vp_idx;
e6373f33 8646 qpair->fw_started = ha->flags.fw_started;
e326d22a 8647 INIT_LIST_HEAD(&qpair->hints_list);
7c3f8fd1
QT		 8648 qpair->chip_reset = ha->base_qpair->chip_reset;
8649 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
8650 qpair->enable_explicit_conf =
8651 ha->base_qpair->enable_explicit_conf;
d7459527
MH		 8652
8653 for (i = 0; i < ha->msix_count; i++) {
093df737 8654 msix = &ha->msix_entries[i];
d7459527
MH		 8655 if (msix->in_use)
8656 continue;
8657 qpair->msix = msix;
83548fe2 8658 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
d7459527
MH		 8659 "Vector %x selected for qpair\n", msix->vector);
8660 break;
8661 }
8662 if (!qpair->msix) {
8663 ql_log(ql_log_warn, vha, 0x0184,
8664 "Out of MSI-X vectors!.\n");
8665 goto fail_msix;
8666 }
8667
8668 qpair->msix->in_use = 1;
8669 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
8abfa9e2
QT		 8670 qpair->pdev = ha->pdev;
8671 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
8672 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
d7459527
MH		 8673
8674 mutex_unlock(&ha->mq_lock);
8675
8676 /* Create response queue first */
82de802a 8677 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
d7459527
MH		 8678 if (!rsp_id) {
8679 ql_log(ql_log_warn, vha, 0x0185,
8680 "Failed to create response queue.\n");
8681 goto fail_rsp;
8682 }
8683
8684 qpair->rsp = ha->rsp_q_map[rsp_id];
8685
8686 /* Create request queue */
82de802a
QT		 8687 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
8688 startqp);
d7459527
MH		 8689 if (!req_id) {
8690 ql_log(ql_log_warn, vha, 0x0186,
8691 "Failed to create request queue.\n");
8692 goto fail_req;
8693 }
8694
8695 qpair->req = ha->req_q_map[req_id];
8696 qpair->rsp->req = qpair->req;
82de802a 8697 qpair->rsp->qpair = qpair;
e326d22a
QT		 8698 /* init qpair to this cpu. Will adjust at run time. */
8699 qla_cpu_update(qpair, smp_processor_id());
d7459527
MH		 8700
8701 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
8702 if (ha->fw_attributes & BIT_4)
8703 qpair->difdix_supported = 1;
8704 }
8705
8706 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
8707 if (!qpair->srb_mempool) {
83548fe2 8708 ql_log(ql_log_warn, vha, 0xd036,
d7459527
MH		 8709 "Failed to create srb mempool for qpair %d\n",
8710 qpair->id);
8711 goto fail_mempool;
8712 }
8713
8714 /* Mark as online */
8715 qpair->online = 1;
8716
8717 if (!vha->flags.qpairs_available)
8718 vha->flags.qpairs_available = 1;
8719
8720 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
8721 "Request/Response queue pair created, id %d\n",
8722 qpair->id);
8723 ql_dbg(ql_dbg_init, vha, 0x0187,
8724 "Request/Response queue pair created, id %d\n",
8725 qpair->id);
8726 }
8727 return qpair;
8728
8729fail_mempool:
8730fail_req:
8731 qla25xx_delete_rsp_que(vha, qpair->rsp);
8732fail_rsp:
8733 mutex_lock(&ha->mq_lock);
8734 qpair->msix->in_use = 0;
8735 list_del(&qpair->qp_list_elem);
8736 if (list_empty(&vha->qp_list))
8737 vha->flags.qpairs_available = 0;
8738fail_msix:
8739 ha->queue_pair_map[qpair_id] = NULL;
8740 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 8741 ha->num_qpairs--;
d7459527
MH		 8742 mutex_unlock(&ha->mq_lock);
8743fail_qid_map:
8744 kfree(qpair);
8745 return NULL;
8746}
8747
8748int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
8749{
d65237c7 8750 int ret = QLA_FUNCTION_FAILED;
d7459527
MH		 8751 struct qla_hw_data *ha = qpair->hw;
8752
8753 qpair->delete_in_progress = 1;
8754 while (atomic_read(&qpair->ref_count))
8755 msleep(500);
8756
8757 ret = qla25xx_delete_req_que(vha, qpair->req);
8758 if (ret != QLA_SUCCESS)
8759 goto fail;
7867b98d 8760
d7459527
MH		 8761 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
8762 if (ret != QLA_SUCCESS)
8763 goto fail;
8764
8765 mutex_lock(&ha->mq_lock);
8766 ha->queue_pair_map[qpair->id] = NULL;
8767 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 8768 ha->num_qpairs--;
d7459527 8769 list_del(&qpair->qp_list_elem);
d65237c7 8770 if (list_empty(&vha->qp_list)) {
d7459527 8771 vha->flags.qpairs_available = 0;
d65237c7
SC		 8772 vha->flags.qpairs_req_created = 0;
8773 vha->flags.qpairs_rsp_created = 0;
8774 }
d7459527
MH		 8775 mempool_destroy(qpair->srb_mempool);
8776 kfree(qpair);
8777 mutex_unlock(&ha->mq_lock);
8778
8779 return QLA_SUCCESS;
8780fail:
8781 return ret;
8782}
Linux 6.x block layer and io_uring tree(s)