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qla2xxx: Comment out unreachable code
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
faef62d1 274qla2x00_tmf_iocb_timeout(void *data)
3822263e 275{
faef62d1
AB		 276 srb_t *sp = (srb_t *)data;
277 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 278
faef62d1
AB		 279 tmf->u.tmf.comp_status = CS_TIMEOUT;
280 complete(&tmf->u.tmf.comp);
281}
9ba56b95 282
faef62d1
AB		 283static void
284qla2x00_tmf_sp_done(void *data, void *ptr, int res)
285{
286 srb_t *sp = (srb_t *)ptr;
287 struct srb_iocb *tmf = &sp->u.iocb_cmd;
288 complete(&tmf->u.tmf.comp);
3822263e
MI		 289}
290
291int
faef62d1 292qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 293 uint32_t tag)
294{
295 struct scsi_qla_host *vha = fcport->vha;
faef62d1 296 struct srb_iocb *tm_iocb;
3822263e 297 srb_t *sp;
faef62d1 298 int rval = QLA_FUNCTION_FAILED;
3822263e 299
9ba56b95 300 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 301 if (!sp)
302 goto done;
303
faef62d1 304 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 305 sp->type = SRB_TM_CMD;
306 sp->name = "tmf";
faef62d1
AB		 307 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
308 tm_iocb->u.tmf.flags = flags;
309 tm_iocb->u.tmf.lun = lun;
310 tm_iocb->u.tmf.data = tag;
311 sp->done = qla2x00_tmf_sp_done;
312 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
313 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 314
315 rval = qla2x00_start_sp(sp);
316 if (rval != QLA_SUCCESS)
317 goto done_free_sp;
318
7c3df132 319 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 320 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
321 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
322 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 323
324 wait_for_completion(&tm_iocb->u.tmf.comp);
325
326 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
327 QLA_SUCCESS : QLA_FUNCTION_FAILED;
328
329 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
330 ql_dbg(ql_dbg_taskm, vha, 0x8030,
331 "TM IOCB failed (%x).\n", rval);
332 }
333
334 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
335 flags = tm_iocb->u.tmf.flags;
336 lun = (uint16_t)tm_iocb->u.tmf.lun;
337
338 /* Issue Marker IOCB */
339 qla2x00_marker(vha, vha->hw->req_q_map[0],
340 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
341 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
342 }
3822263e
MI		 343
344done_free_sp:
faef62d1 345 sp->free(vha, sp);
3822263e
MI		 346done:
347 return rval;
348}
349
4440e46d
AB		 350static void
351qla24xx_abort_iocb_timeout(void *data)
352{
353 srb_t *sp = (srb_t *)data;
354 struct srb_iocb *abt = &sp->u.iocb_cmd;
355
356 abt->u.abt.comp_status = CS_TIMEOUT;
357 complete(&abt->u.abt.comp);
358}
359
360static void
361qla24xx_abort_sp_done(void *data, void *ptr, int res)
362{
363 srb_t *sp = (srb_t *)ptr;
364 struct srb_iocb *abt = &sp->u.iocb_cmd;
365
366 complete(&abt->u.abt.comp);
367}
368
369static int
370qla24xx_async_abort_cmd(srb_t *cmd_sp)
371{
372 scsi_qla_host_t *vha = cmd_sp->fcport->vha;
373 fc_port_t *fcport = cmd_sp->fcport;
374 struct srb_iocb *abt_iocb;
375 srb_t *sp;
376 int rval = QLA_FUNCTION_FAILED;
377
378 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
379 if (!sp)
380 goto done;
381
382 abt_iocb = &sp->u.iocb_cmd;
383 sp->type = SRB_ABT_CMD;
384 sp->name = "abort";
385 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
386 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
387 sp->done = qla24xx_abort_sp_done;
388 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
389 init_completion(&abt_iocb->u.abt.comp);
390
391 rval = qla2x00_start_sp(sp);
392 if (rval != QLA_SUCCESS)
393 goto done_free_sp;
394
395 ql_dbg(ql_dbg_async, vha, 0x507c,
396 "Abort command issued - hdl=%x, target_id=%x\n",
397 cmd_sp->handle, fcport->tgt_id);
398
399 wait_for_completion(&abt_iocb->u.abt.comp);
400
401 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
402 QLA_SUCCESS : QLA_FUNCTION_FAILED;
403
404done_free_sp:
405 sp->free(vha, sp);
406done:
407 return rval;
408}
409
410int
411qla24xx_async_abort_command(srb_t *sp)
412{
413 unsigned long flags = 0;
414
415 uint32_t handle;
416 fc_port_t *fcport = sp->fcport;
417 struct scsi_qla_host *vha = fcport->vha;
418 struct qla_hw_data *ha = vha->hw;
419 struct req_que *req = vha->req;
420
421 spin_lock_irqsave(&ha->hardware_lock, flags);
422 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
423 if (req->outstanding_cmds[handle] == sp)
424 break;
425 }
426 spin_unlock_irqrestore(&ha->hardware_lock, flags);
427 if (handle == req->num_outstanding_cmds) {
428 /* Command not found. */
429 return QLA_FUNCTION_FAILED;
430 }
431 if (sp->type == SRB_FXIOCB_DCMD)
432 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
433 FXDISC_ABORT_IOCTL);
434
435 return qla24xx_async_abort_cmd(sp);
436}
437
4916392b 438void
ac280b67
AV		 439qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
440 uint16_t *data)
441{
442 int rval;
ac280b67
AV		 443
444 switch (data[0]) {
445 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 446 /*
447 * Driver must validate login state - If PRLI not complete,
448 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
449 * requests.
450 */
451 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 452 if (rval == QLA_NOT_LOGGED_IN) {
453 fcport->flags &= ~FCF_ASYNC_SENT;
454 fcport->flags |= FCF_LOGIN_NEEDED;
455 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
456 break;
457 }
458
a4f92a32
AV		 459 if (rval != QLA_SUCCESS) {
460 qla2x00_post_async_logout_work(vha, fcport, NULL);
461 qla2x00_post_async_login_work(vha, fcport, NULL);
462 break;
463 }
99b0bec7 464 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 465 qla2x00_post_async_adisc_work(vha, fcport, data);
466 break;
99b0bec7
AV		 467 }
468 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 469 break;
470 case MBS_COMMAND_ERROR:
5ff1d584 471 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 472 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
474 else
80d79440 475 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 476 break;
477 case MBS_PORT_ID_USED:
478 fcport->loop_id = data[1];
6ac52608 479 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 480 qla2x00_post_async_login_work(vha, fcport, NULL);
481 break;
482 case MBS_LOOP_ID_USED:
483 fcport->loop_id++;
484 rval = qla2x00_find_new_loop_id(vha, fcport);
485 if (rval != QLA_SUCCESS) {
5ff1d584 486 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 487 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 488 break;
489 }
490 qla2x00_post_async_login_work(vha, fcport, NULL);
491 break;
492 }
4916392b 493 return;
ac280b67
AV		 494}
495
4916392b 496void
ac280b67
AV		 497qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
498 uint16_t *data)
499{
500 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 501 return;
ac280b67
AV		 502}
503
4916392b 504void
5ff1d584
AV		 505qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
506 uint16_t *data)
507{
508 if (data[0] == MBS_COMMAND_COMPLETE) {
509 qla2x00_update_fcport(vha, fcport);
510
4916392b 511 return;
5ff1d584
AV		 512 }
513
514 /* Retry login. */
515 fcport->flags &= ~FCF_ASYNC_SENT;
516 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
517 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
518 else
80d79440 519 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 520
4916392b 521 return;
5ff1d584
AV		 522}
523
1da177e4
LT		 524/****************************************************************************/
525/* QLogic ISP2x00 Hardware Support Functions. */
526/****************************************************************************/
527
fa492630 528static int
7d613ac6
SV		 529qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
530{
531 int rval = QLA_SUCCESS;
532 struct qla_hw_data *ha = vha->hw;
533 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 534 uint16_t config[4];
7d613ac6
SV		 535
536 qla83xx_idc_lock(vha, 0);
537
538 /* SV: TODO: Assign initialization timeout from
539 * flash-info / other param
540 */
541 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
542 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
543
544 /* Set our fcoe function presence */
545 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
546 ql_dbg(ql_dbg_p3p, vha, 0xb077,
547 "Error while setting DRV-Presence.\n");
548 rval = QLA_FUNCTION_FAILED;
549 goto exit;
550 }
551
552 /* Decide the reset ownership */
553 qla83xx_reset_ownership(vha);
554
555 /*
556 * On first protocol driver load:
557 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
558 * register.
559 * Others: Check compatibility with current IDC Major version.
560 */
561 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
562 if (ha->flags.nic_core_reset_owner) {
563 /* Set IDC Major version */
564 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
565 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
566
567 /* Clearing IDC-Lock-Recovery register */
568 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
569 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
570 /*
571 * Clear further IDC participation if we are not compatible with
572 * the current IDC Major Version.
573 */
574 ql_log(ql_log_warn, vha, 0xb07d,
575 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
576 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
577 __qla83xx_clear_drv_presence(vha);
578 rval = QLA_FUNCTION_FAILED;
579 goto exit;
580 }
581 /* Each function sets its supported Minor version. */
582 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
583 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
584 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
585
711aa7f7
SK		 586 if (ha->flags.nic_core_reset_owner) {
587 memset(config, 0, sizeof(config));
588 if (!qla81xx_get_port_config(vha, config))
589 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
590 QLA8XXX_DEV_READY);
591 }
592
7d613ac6
SV		 593 rval = qla83xx_idc_state_handler(vha);
594
595exit:
596 qla83xx_idc_unlock(vha, 0);
597
598 return rval;
599}
600
1da177e4
LT		 601/*
602* qla2x00_initialize_adapter
603* Initialize board.
604*
605* Input:
606* ha = adapter block pointer.
607*
608* Returns:
609* 0 = success
610*/
611int
e315cd28 612qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 613{
614 int rval;
e315cd28 615 struct qla_hw_data *ha = vha->hw;
73208dfd 616 struct req_que *req = ha->req_q_map[0];
2533cf67 617
1da177e4 618 /* Clear adapter flags. */
e315cd28 619 vha->flags.online = 0;
2533cf67 620 ha->flags.chip_reset_done = 0;
e315cd28 621 vha->flags.reset_active = 0;
85880801
AV		 622 ha->flags.pci_channel_io_perm_failure = 0;
623 ha->flags.eeh_busy = 0;
fabbb8df 624 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 625 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
626 atomic_set(&vha->loop_state, LOOP_DOWN);
627 vha->device_flags = DFLG_NO_CABLE;
628 vha->dpc_flags = 0;
629 vha->flags.management_server_logged_in = 0;
630 vha->marker_needed = 0;
1da177e4
LT		 631 ha->isp_abort_cnt = 0;
632 ha->beacon_blink_led = 0;
633
73208dfd
AC		 634 set_bit(0, ha->req_qid_map);
635 set_bit(0, ha->rsp_qid_map);
636
cfb0919c 637 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 638 "Configuring PCI space...\n");
e315cd28 639 rval = ha->isp_ops->pci_config(vha);
1da177e4 640 if (rval) {
7c3df132
SK		 641 ql_log(ql_log_warn, vha, 0x0044,
642 "Unable to configure PCI space.\n");
1da177e4
LT		 643 return (rval);
644 }
645
e315cd28 646 ha->isp_ops->reset_chip(vha);
1da177e4 647
e315cd28 648 rval = qla2xxx_get_flash_info(vha);
c00d8994 649 if (rval) {
7c3df132
SK		 650 ql_log(ql_log_fatal, vha, 0x004f,
651 "Unable to validate FLASH data.\n");
7ec0effd
AD		 652 return rval;
653 }
654
655 if (IS_QLA8044(ha)) {
656 qla8044_read_reset_template(vha);
657
658 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
659 * If DONRESET_BIT0 is set, drivers should not set dev_state
660 * to NEED_RESET. But if NEED_RESET is set, drivers should
661 * should honor the reset. */
662 if (ql2xdontresethba == 1)
663 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 664 }
665
73208dfd 666 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 667 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 668 "Configure NVRAM parameters...\n");
0107109e 669
e315cd28 670 ha->isp_ops->nvram_config(vha);
1da177e4 671
d4c760c2
AV		 672 if (ha->flags.disable_serdes) {
673 /* Mask HBA via NVRAM settings? */
7c3df132 674 ql_log(ql_log_info, vha, 0x0077,
7b833558 675 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 676 return QLA_FUNCTION_FAILED;
677 }
678
cfb0919c 679 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 680 "Verifying loaded RISC code...\n");
1da177e4 681
e315cd28
AC		 682 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
683 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 684 if (rval)
685 return (rval);
e315cd28 686 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 687 if (rval)
688 return (rval);
1da177e4 689 }
a9083016 690
4d4df193 691 if (IS_QLA84XX(ha)) {
e315cd28 692 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 693 if (!ha->cs84xx) {
7c3df132 694 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 695 "Unable to configure ISP84XX.\n");
696 return QLA_FUNCTION_FAILED;
697 }
698 }
2d70c103
NB		 699
700 if (qla_ini_mode_enabled(vha))
701 rval = qla2x00_init_rings(vha);
702
2533cf67 703 ha->flags.chip_reset_done = 1;
1da177e4 704
9a069e19 705 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 706 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 707 rval = qla84xx_init_chip(vha);
708 if (rval != QLA_SUCCESS) {
7c3df132
SK		 709 ql_log(ql_log_warn, vha, 0x00d4,
710 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 711 qla84xx_put_chip(vha);
712 }
713 }
714
7d613ac6
SV		 715 /* Load the NIC Core f/w if we are the first protocol driver. */
716 if (IS_QLA8031(ha)) {
717 rval = qla83xx_nic_core_fw_load(vha);
718 if (rval)
719 ql_log(ql_log_warn, vha, 0x0124,
720 "Error in initializing NIC Core f/w.\n");
721 }
722
2f0f3f4f
MI		 723 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
724 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 725
c46e65c7
JC		 726 if (IS_P3P_TYPE(ha))
727 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
728 else
729 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
730
1da177e4
LT		 731 return (rval);
732}
733
734/**
abbd8870 735 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 736 * @ha: HA context
737 *
738 * Returns 0 on success.
739 */
abbd8870 740int
e315cd28 741qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 742{
a157b101 743 uint16_t w;
abbd8870 744 unsigned long flags;
e315cd28 745 struct qla_hw_data *ha = vha->hw;
3d71644c 746 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 747
1da177e4 748 pci_set_master(ha->pdev);
af6177d8 749 pci_try_set_mwi(ha->pdev);
1da177e4 750
1da177e4 751 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 752 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 753 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
754
737faece 755 pci_disable_rom(ha->pdev);
1da177e4
LT		 756
757 /* Get PCI bus information. */
758 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 759 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 760 spin_unlock_irqrestore(&ha->hardware_lock, flags);
761
abbd8870
AV		 762 return QLA_SUCCESS;
763}
1da177e4 764
abbd8870
AV		 765/**
766 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
767 * @ha: HA context
768 *
769 * Returns 0 on success.
770 */
771int
e315cd28 772qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 773{
a157b101 774 uint16_t w;
abbd8870
AV		 775 unsigned long flags = 0;
776 uint32_t cnt;
e315cd28 777 struct qla_hw_data *ha = vha->hw;
3d71644c 778 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 779
abbd8870 780 pci_set_master(ha->pdev);
af6177d8 781 pci_try_set_mwi(ha->pdev);
1da177e4 782
abbd8870 783 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 784 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 785
abbd8870
AV		 786 if (IS_QLA2322(ha) || IS_QLA6322(ha))
787 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 788 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 789
abbd8870
AV		 790 /*
791 * If this is a 2300 card and not 2312, reset the
792 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
793 * the 2310 also reports itself as a 2300 so we need to get the
794 * fb revision level -- a 6 indicates it really is a 2300 and
795 * not a 2310.
796 */
797 if (IS_QLA2300(ha)) {
798 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 799
abbd8870 800 /* Pause RISC. */
3d71644c 801 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 802 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 803 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 804 break;
1da177e4 805
abbd8870
AV		 806 udelay(10);
807 }
1da177e4 808
abbd8870 809 /* Select FPM registers. */
3d71644c
AV		 810 WRT_REG_WORD(&reg->ctrl_status, 0x20);
811 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 812
813 /* Get the fb rev level */
3d71644c 814 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 815
816 if (ha->fb_rev == FPM_2300)
a157b101 817 pci_clear_mwi(ha->pdev);
abbd8870
AV		 818
819 /* Deselect FPM registers. */
3d71644c
AV		 820 WRT_REG_WORD(&reg->ctrl_status, 0x0);
821 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 822
823 /* Release RISC module. */
3d71644c 824 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 825 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 826 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 827 break;
828
829 udelay(10);
1da177e4 830 }
1da177e4 831
abbd8870
AV		 832 spin_unlock_irqrestore(&ha->hardware_lock, flags);
833 }
1da177e4 834
abbd8870
AV		 835 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
836
737faece 837 pci_disable_rom(ha->pdev);
1da177e4 838
abbd8870
AV		 839 /* Get PCI bus information. */
840 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 841 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 842 spin_unlock_irqrestore(&ha->hardware_lock, flags);
843
844 return QLA_SUCCESS;
1da177e4
LT		 845}
846
0107109e
AV		 847/**
848 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
849 * @ha: HA context
850 *
851 * Returns 0 on success.
852 */
853int
e315cd28 854qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 855{
a157b101 856 uint16_t w;
0107109e 857 unsigned long flags = 0;
e315cd28 858 struct qla_hw_data *ha = vha->hw;
0107109e 859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 860
861 pci_set_master(ha->pdev);
af6177d8 862 pci_try_set_mwi(ha->pdev);
0107109e
AV		 863
864 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 865 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 866 w &= ~PCI_COMMAND_INTX_DISABLE;
867 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
868
869 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
870
871 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 872 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
873 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 874
875 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 876 if (pci_is_pcie(ha->pdev))
5ffd3a52 877 pcie_set_readrq(ha->pdev, 4096);
0107109e 878
737faece 879 pci_disable_rom(ha->pdev);
0107109e 880
44c10138 881 ha->chip_revision = ha->pdev->revision;
a8488abe 882
0107109e
AV		 883 /* Get PCI bus information. */
884 spin_lock_irqsave(&ha->hardware_lock, flags);
885 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
887
888 return QLA_SUCCESS;
889}
890
c3a2f0df
AV		 891/**
892 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
893 * @ha: HA context
894 *
895 * Returns 0 on success.
896 */
897int
e315cd28 898qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 899{
900 uint16_t w;
e315cd28 901 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 902
903 pci_set_master(ha->pdev);
904 pci_try_set_mwi(ha->pdev);
905
906 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
907 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
908 w &= ~PCI_COMMAND_INTX_DISABLE;
909 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
910
911 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 912 if (pci_is_pcie(ha->pdev))
5ffd3a52 913 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 914
737faece 915 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 916
917 ha->chip_revision = ha->pdev->revision;
918
919 return QLA_SUCCESS;
920}
921
1da177e4
LT		 922/**
923 * qla2x00_isp_firmware() - Choose firmware image.
924 * @ha: HA context
925 *
926 * Returns 0 on success.
927 */
928static int
e315cd28 929qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 930{
931 int rval;
42e421b1
AV		 932 uint16_t loop_id, topo, sw_cap;
933 uint8_t domain, area, al_pa;
e315cd28 934 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 935
936 /* Assume loading risc code */
fa2a1ce5 937 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 938
939 if (ha->flags.disable_risc_code_load) {
7c3df132 940 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 941
942 /* Verify checksum of loaded RISC code. */
e315cd28 943 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 944 if (rval == QLA_SUCCESS) {
945 /* And, verify we are not in ROM code. */
e315cd28 946 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 947 &area, &domain, &topo, &sw_cap);
948 }
1da177e4
LT		 949 }
950
7c3df132
SK		 951 if (rval)
952 ql_dbg(ql_dbg_init, vha, 0x007a,
953 "**** Load RISC code ****.\n");
1da177e4
LT		 954
955 return (rval);
956}
957
958/**
959 * qla2x00_reset_chip() - Reset ISP chip.
960 * @ha: HA context
961 *
962 * Returns 0 on success.
963 */
abbd8870 964void
e315cd28 965qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 966{
967 unsigned long flags = 0;
e315cd28 968 struct qla_hw_data *ha = vha->hw;
3d71644c 969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 970 uint32_t cnt;
1da177e4
LT		 971 uint16_t cmd;
972
85880801
AV		 973 if (unlikely(pci_channel_offline(ha->pdev)))
974 return;
975
fd34f556 976 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 977
978 spin_lock_irqsave(&ha->hardware_lock, flags);
979
980 /* Turn off master enable */
981 cmd = 0;
982 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
983 cmd &= ~PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 if (!IS_QLA2100(ha)) {
987 /* Pause RISC. */
988 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
989 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
990 for (cnt = 0; cnt < 30000; cnt++) {
991 if ((RD_REG_WORD(&reg->hccr) &
992 HCCR_RISC_PAUSE) != 0)
993 break;
994 udelay(100);
995 }
996 } else {
997 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
998 udelay(10);
999 }
1000
1001 /* Select FPM registers. */
1002 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1003 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1004
1005 /* FPM Soft Reset. */
1006 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1007 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1008
1009 /* Toggle Fpm Reset. */
1010 if (!IS_QLA2200(ha)) {
1011 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1012 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1013 }
1014
1015 /* Select frame buffer registers. */
1016 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1017 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1018
1019 /* Reset frame buffer FIFOs. */
1020 if (IS_QLA2200(ha)) {
1021 WRT_FB_CMD_REG(ha, reg, 0xa000);
1022 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1023 } else {
1024 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1025
1026 /* Read back fb_cmd until zero or 3 seconds max */
1027 for (cnt = 0; cnt < 3000; cnt++) {
1028 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1029 break;
1030 udelay(100);
1031 }
1032 }
1033
1034 /* Select RISC module registers. */
1035 WRT_REG_WORD(&reg->ctrl_status, 0);
1036 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1037
1038 /* Reset RISC processor. */
1039 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1040 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1041
1042 /* Release RISC processor. */
1043 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1044 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1045 }
1046
1047 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1048 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1049
1050 /* Reset ISP chip. */
1051 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1052
1053 /* Wait for RISC to recover from reset. */
1054 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1055 /*
1056 * It is necessary to for a delay here since the card doesn't
1057 * respond to PCI reads during a reset. On some architectures
1058 * this will result in an MCA.
1059 */
1060 udelay(20);
1061 for (cnt = 30000; cnt; cnt--) {
1062 if ((RD_REG_WORD(&reg->ctrl_status) &
1063 CSR_ISP_SOFT_RESET) == 0)
1064 break;
1065 udelay(100);
1066 }
1067 } else
1068 udelay(10);
1069
1070 /* Reset RISC processor. */
1071 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1072
1073 WRT_REG_WORD(&reg->semaphore, 0);
1074
1075 /* Release RISC processor. */
1076 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1077 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1078
1079 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1080 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1081 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1082 break;
1da177e4
LT		 1083
1084 udelay(100);
1085 }
1086 } else
1087 udelay(100);
1088
1089 /* Turn on master enable */
1090 cmd |= PCI_COMMAND_MASTER;
1091 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1092
1093 /* Disable RISC pause on FPM parity error. */
1094 if (!IS_QLA2100(ha)) {
1095 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1096 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1097 }
1098
1099 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1100}
1101
b1d46989
MI		 1102/**
1103 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1104 *
1105 * Returns 0 on success.
1106 */
fa492630 1107static int
b1d46989
MI		 1108qla81xx_reset_mpi(scsi_qla_host_t *vha)
1109{
1110 uint16_t mb[4] = {0x1010, 0, 1, 0};
1111
6246b8a1
GM		 1112 if (!IS_QLA81XX(vha->hw))
1113 return QLA_SUCCESS;
1114
b1d46989
MI		 1115 return qla81xx_write_mpi_register(vha, mb);
1116}
1117
0107109e 1118/**
88c26663 1119 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1120 * @ha: HA context
1121 *
1122 * Returns 0 on success.
1123 */
d14e72fb 1124static inline int
e315cd28 1125qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1126{
1127 unsigned long flags = 0;
e315cd28 1128 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1129 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1130 uint32_t cnt, d2;
335a1cc9 1131 uint16_t wd;
b1d46989 1132 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 1133 int rval = QLA_SUCCESS;
0107109e 1134
0107109e
AV		 1135 spin_lock_irqsave(&ha->hardware_lock, flags);
1136
1137 /* Reset RISC. */
1138 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1139 for (cnt = 0; cnt < 30000; cnt++) {
1140 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1141 break;
1142
1143 udelay(10);
1144 }
1145
d14e72fb
HM		 1146 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
1147 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
1148
1149 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
1150 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
1151 RD_REG_DWORD(&reg->hccr),
1152 RD_REG_DWORD(&reg->ctrl_status),
1153 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
1154
0107109e
AV		 1155 WRT_REG_DWORD(&reg->ctrl_status,
1156 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1157 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1158
335a1cc9 1159 udelay(100);
d14e72fb 1160
88c26663 1161 /* Wait for firmware to complete NVRAM accesses. */
88c26663 1162 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 1163 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1164 rval == QLA_SUCCESS; cnt--) {
88c26663 1165 barrier();
d14e72fb
HM		 1166 if (cnt)
1167 udelay(5);
1168 else
1169 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 1170 }
1171
d14e72fb
HM		 1172 if (rval == QLA_SUCCESS)
1173 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
1174
1175 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
1176 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
1177 RD_REG_DWORD(&reg->hccr),
1178 RD_REG_DWORD(&reg->mailbox0));
1179
335a1cc9 1180 /* Wait for soft-reset to complete. */
0107109e 1181 d2 = RD_REG_DWORD(&reg->ctrl_status);
d14e72fb 1182 for (cnt = 0; cnt < 6000000; cnt++) {
0107109e 1183 barrier();
d14e72fb
HM		 1184 if ((RD_REG_DWORD(&reg->ctrl_status) &
1185 CSRX_ISP_SOFT_RESET) == 0)
1186 break;
1187
1188 udelay(5);
0107109e 1189 }
d14e72fb
HM		 1190 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
1191 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
1192
1193 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
1194 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
1195 RD_REG_DWORD(&reg->hccr),
1196 RD_REG_DWORD(&reg->ctrl_status));
0107109e 1197
b1d46989
MI		 1198 /* If required, do an MPI FW reset now */
1199 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1200 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1201 if (++abts_cnt < 5) {
1202 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1203 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1204 } else {
1205 /*
1206 * We exhausted the ISP abort retries. We have to
1207 * set the board offline.
1208 */
1209 abts_cnt = 0;
1210 vha->flags.online = 0;
1211 }
1212 }
1213 }
1214
0107109e
AV		 1215 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1216 RD_REG_DWORD(&reg->hccr);
1217
1218 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1219 RD_REG_DWORD(&reg->hccr);
1220
1221 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1222 RD_REG_DWORD(&reg->hccr);
1223
1224 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 1225 for (cnt = 6000000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1226 rval == QLA_SUCCESS; cnt--) {
0107109e 1227 barrier();
d14e72fb
HM		 1228 if (cnt)
1229 udelay(5);
1230 else
1231 rval = QLA_FUNCTION_TIMEOUT;
0107109e 1232 }
d14e72fb
HM		 1233 if (rval == QLA_SUCCESS)
1234 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
1235
1236 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
1237 "Host Risc 0x%x, mailbox0 0x%x\n",
1238 RD_REG_DWORD(&reg->hccr),
1239 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 1240
1241 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 1242
d14e72fb
HM		 1243 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
1244 "Driver in %s mode\n",
1245 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
1246
124f85e6
AV		 1247 if (IS_NOPOLLING_TYPE(ha))
1248 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 1249
1250 return rval;
0107109e
AV		 1251}
1252
4ea2c9c7
JC		 1253static void
1254qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1255{
1256 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1257
1258 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1259 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1260
1261}
1262
1263static void
1264qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1265{
1266 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1267
1268 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1269 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1270}
1271
1272static void
1273qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1274{
1275 struct qla_hw_data *ha = vha->hw;
1276 uint32_t wd32 = 0;
1277 uint delta_msec = 100;
1278 uint elapsed_msec = 0;
1279 uint timeout_msec;
1280 ulong n;
1281
1282 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1283 return;
1284
1285attempt:
1286 timeout_msec = TIMEOUT_SEMAPHORE;
1287 n = timeout_msec / delta_msec;
1288 while (n--) {
1289 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1290 qla25xx_read_risc_sema_reg(vha, &wd32);
1291 if (wd32 & RISC_SEMAPHORE)
1292 break;
1293 msleep(delta_msec);
1294 elapsed_msec += delta_msec;
1295 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1296 goto force;
1297 }
1298
1299 if (!(wd32 & RISC_SEMAPHORE))
1300 goto force;
1301
1302 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1303 goto acquired;
1304
1305 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1306 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1307 n = timeout_msec / delta_msec;
1308 while (n--) {
1309 qla25xx_read_risc_sema_reg(vha, &wd32);
1310 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1311 break;
1312 msleep(delta_msec);
1313 elapsed_msec += delta_msec;
1314 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1315 goto force;
1316 }
1317
1318 if (wd32 & RISC_SEMAPHORE_FORCE)
1319 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1320
1321 goto attempt;
1322
1323force:
1324 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1325
1326acquired:
1327 return;
1328}
1329
88c26663
AV		 1330/**
1331 * qla24xx_reset_chip() - Reset ISP24xx chip.
1332 * @ha: HA context
1333 *
1334 * Returns 0 on success.
1335 */
1336void
e315cd28 1337qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1338{
e315cd28 1339 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1340
1341 if (pci_channel_offline(ha->pdev) &&
1342 ha->flags.pci_channel_io_perm_failure) {
1343 return;
1344 }
1345
fd34f556 1346 ha->isp_ops->disable_intrs(ha);
88c26663 1347
4ea2c9c7
JC		 1348 qla25xx_manipulate_risc_semaphore(vha);
1349
88c26663 1350 /* Perform RISC reset. */
e315cd28 1351 qla24xx_reset_risc(vha);
88c26663
AV		 1352}
1353
1da177e4
LT		 1354/**
1355 * qla2x00_chip_diag() - Test chip for proper operation.
1356 * @ha: HA context
1357 *
1358 * Returns 0 on success.
1359 */
abbd8870 1360int
e315cd28 1361qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1362{
1363 int rval;
e315cd28 1364 struct qla_hw_data *ha = vha->hw;
3d71644c 1365 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1366 unsigned long flags = 0;
1367 uint16_t data;
1368 uint32_t cnt;
1369 uint16_t mb[5];
73208dfd 1370 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1371
1372 /* Assume a failed state */
1373 rval = QLA_FUNCTION_FAILED;
1374
7c3df132
SK		 1375 ql_dbg(ql_dbg_init, vha, 0x007b,
1376 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1377
1378 spin_lock_irqsave(&ha->hardware_lock, flags);
1379
1380 /* Reset ISP chip. */
1381 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1382
1383 /*
1384 * We need to have a delay here since the card will not respond while
1385 * in reset causing an MCA on some architectures.
1386 */
1387 udelay(20);
1388 data = qla2x00_debounce_register(&reg->ctrl_status);
1389 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1390 udelay(5);
1391 data = RD_REG_WORD(&reg->ctrl_status);
1392 barrier();
1393 }
1394
1395 if (!cnt)
1396 goto chip_diag_failed;
1397
7c3df132
SK		 1398 ql_dbg(ql_dbg_init, vha, 0x007c,
1399 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1400
1401 /* Reset RISC processor. */
1402 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1403 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1404
1405 /* Workaround for QLA2312 PCI parity error */
1406 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1407 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1408 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1409 udelay(5);
1410 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1411 barrier();
1da177e4
LT		 1412 }
1413 } else
1414 udelay(10);
1415
1416 if (!cnt)
1417 goto chip_diag_failed;
1418
1419 /* Check product ID of chip */
7c3df132 1420 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1421
1422 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1423 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1424 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1425 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1426 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1427 mb[3] != PROD_ID_3) {
7c3df132
SK		 1428 ql_log(ql_log_warn, vha, 0x0062,
1429 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1430 mb[1], mb[2], mb[3]);
1da177e4
LT		 1431
1432 goto chip_diag_failed;
1433 }
1434 ha->product_id[0] = mb[1];
1435 ha->product_id[1] = mb[2];
1436 ha->product_id[2] = mb[3];
1437 ha->product_id[3] = mb[4];
1438
1439 /* Adjust fw RISC transfer size */
73208dfd 1440 if (req->length > 1024)
1da177e4
LT		 1441 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1442 else
1443 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1444 req->length;
1da177e4
LT		 1445
1446 if (IS_QLA2200(ha) &&
1447 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1448 /* Limit firmware transfer size with a 2200A */
7c3df132 1449 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1450
ea5b6382 1451 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1452 ha->fw_transfer_size = 128;
1453 }
1454
1455 /* Wrap Incoming Mailboxes Test. */
1456 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1457
7c3df132 1458 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1459 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1460 if (rval)
1461 ql_log(ql_log_warn, vha, 0x0080,
1462 "Failed mailbox send register test.\n");
1463 else
1da177e4
LT		 1464 /* Flag a successful rval */
1465 rval = QLA_SUCCESS;
1da177e4
LT		 1466 spin_lock_irqsave(&ha->hardware_lock, flags);
1467
1468chip_diag_failed:
1469 if (rval)
7c3df132
SK		 1470 ql_log(ql_log_info, vha, 0x0081,
1471 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1472
1473 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1474
1475 return (rval);
1476}
1477
0107109e
AV		 1478/**
1479 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1480 * @ha: HA context
1481 *
1482 * Returns 0 on success.
1483 */
1484int
e315cd28 1485qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1486{
1487 int rval;
e315cd28 1488 struct qla_hw_data *ha = vha->hw;
73208dfd 1489 struct req_que *req = ha->req_q_map[0];
0107109e 1490
7ec0effd 1491 if (IS_P3P_TYPE(ha))
a9083016
GM		 1492 return QLA_SUCCESS;
1493
73208dfd 1494 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1495
e315cd28 1496 rval = qla2x00_mbx_reg_test(vha);
0107109e 1497 if (rval) {
7c3df132
SK		 1498 ql_log(ql_log_warn, vha, 0x0082,
1499 "Failed mailbox send register test.\n");
0107109e
AV		 1500 } else {
1501 /* Flag a successful rval */
1502 rval = QLA_SUCCESS;
1503 }
1504
1505 return rval;
1506}
1507
a7a167bf 1508void
e315cd28 1509qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1510{
a7a167bf
AV		 1511 int rval;
1512 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1513 eft_size, fce_size, mq_size;
df613b96
AV		 1514 dma_addr_t tc_dma;
1515 void *tc;
e315cd28 1516 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1517 struct req_que *req = ha->req_q_map[0];
1518 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1519
1520 if (ha->fw_dump) {
7c3df132
SK		 1521 ql_dbg(ql_dbg_init, vha, 0x00bd,
1522 "Firmware dump already allocated.\n");
a7a167bf
AV		 1523 return;
1524 }
d4e3e04d 1525
0107109e 1526 ha->fw_dumped = 0;
61f098dd 1527 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 1528 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1529 req_q_size = rsp_q_size = 0;
1530
1531 if (IS_QLA27XX(ha))
1532 goto try_fce;
1533
d4e3e04d 1534 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1535 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1536 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1537 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1538 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1539 sizeof(uint16_t);
e428924c 1540 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1541 if (IS_QLA83XX(ha))
1542 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1543 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1544 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1545 else if (IS_QLA25XX(ha))
1546 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1547 else
1548 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1549
a7a167bf
AV		 1550 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1551 sizeof(uint32_t);
050c9bb1 1552 if (ha->mqenable) {
6246b8a1
GM		 1553 if (!IS_QLA83XX(ha))
1554 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1555 /*
1556 * Allocate maximum buffer size for all queues.
1557 * Resizing must be done at end-of-dump processing.
1558 */
1559 mq_size += ha->max_req_queues *
1560 (req->length * sizeof(request_t));
1561 mq_size += ha->max_rsp_queues *
1562 (rsp->length * sizeof(response_t));
1563 }
00876ae8 1564 if (ha->tgt.atio_ring)
2d70c103 1565 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1566 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1567 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1568 !IS_QLA27XX(ha))
436a7b11 1569 goto try_eft;
df613b96 1570
f73cb695
CD		 1571try_fce:
1572 if (ha->fce)
1573 dma_free_coherent(&ha->pdev->dev,
1574 FCE_SIZE, ha->fce, ha->fce_dma);
1575
1576 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 1577 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1578 GFP_KERNEL);
df613b96 1579 if (!tc) {
7c3df132
SK		 1580 ql_log(ql_log_warn, vha, 0x00be,
1581 "Unable to allocate (%d KB) for FCE.\n",
1582 FCE_SIZE / 1024);
17d98630 1583 goto try_eft;
df613b96
AV		 1584 }
1585
e315cd28 1586 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1587 ha->fce_mb, &ha->fce_bufs);
1588 if (rval) {
7c3df132
SK		 1589 ql_log(ql_log_warn, vha, 0x00bf,
1590 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1591 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1592 tc_dma);
1593 ha->flags.fce_enabled = 0;
17d98630 1594 goto try_eft;
df613b96 1595 }
cfb0919c 1596 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1597 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1598
7d9dade3 1599 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1600 ha->flags.fce_enabled = 1;
1601 ha->fce_dma = tc_dma;
1602 ha->fce = tc;
f73cb695 1603
436a7b11 1604try_eft:
f73cb695
CD		 1605 if (ha->eft)
1606 dma_free_coherent(&ha->pdev->dev,
1607 EFT_SIZE, ha->eft, ha->eft_dma);
1608
436a7b11 1609 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 1610 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1611 GFP_KERNEL);
436a7b11 1612 if (!tc) {
7c3df132
SK		 1613 ql_log(ql_log_warn, vha, 0x00c1,
1614 "Unable to allocate (%d KB) for EFT.\n",
1615 EFT_SIZE / 1024);
436a7b11
AV		 1616 goto cont_alloc;
1617 }
1618
e315cd28 1619 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1620 if (rval) {
7c3df132
SK		 1621 ql_log(ql_log_warn, vha, 0x00c2,
1622 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1623 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1624 tc_dma);
1625 goto cont_alloc;
1626 }
cfb0919c 1627 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1628 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1629
1630 eft_size = EFT_SIZE;
1631 ha->eft_dma = tc_dma;
1632 ha->eft = tc;
d4e3e04d 1633 }
f73cb695 1634
a7a167bf 1635cont_alloc:
f73cb695
CD		 1636 if (IS_QLA27XX(ha)) {
1637 if (!ha->fw_dump_template) {
1638 ql_log(ql_log_warn, vha, 0x00ba,
1639 "Failed missing fwdump template\n");
1640 return;
1641 }
1642 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1643 ql_dbg(ql_dbg_init, vha, 0x00fa,
1644 "-> allocating fwdump (%x bytes)...\n", dump_size);
1645 goto allocate;
1646 }
1647
73208dfd
AC		 1648 req_q_size = req->length * sizeof(request_t);
1649 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1650 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1651 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1652 ha->chain_offset = dump_size;
1653 dump_size += mq_size + fce_size;
d4e3e04d 1654
f73cb695 1655allocate:
d4e3e04d 1656 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1657 if (!ha->fw_dump) {
7c3df132
SK		 1658 ql_log(ql_log_warn, vha, 0x00c4,
1659 "Unable to allocate (%d KB) for firmware dump.\n",
1660 dump_size / 1024);
a7a167bf 1661
e30d1756
MI		 1662 if (ha->fce) {
1663 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1664 ha->fce_dma);
1665 ha->fce = NULL;
1666 ha->fce_dma = 0;
1667 }
1668
a7a167bf
AV		 1669 if (ha->eft) {
1670 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1671 ha->eft_dma);
1672 ha->eft = NULL;
1673 ha->eft_dma = 0;
1674 }
1675 return;
1676 }
f73cb695 1677 ha->fw_dump_len = dump_size;
cfb0919c 1678 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1679 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1680
f73cb695
CD		 1681 if (IS_QLA27XX(ha))
1682 return;
1683
a7a167bf
AV		 1684 ha->fw_dump->signature[0] = 'Q';
1685 ha->fw_dump->signature[1] = 'L';
1686 ha->fw_dump->signature[2] = 'G';
1687 ha->fw_dump->signature[3] = 'C';
1688 ha->fw_dump->version = __constant_htonl(1);
1689
1690 ha->fw_dump->fixed_size = htonl(fixed_size);
1691 ha->fw_dump->mem_size = htonl(mem_size);
1692 ha->fw_dump->req_q_size = htonl(req_q_size);
1693 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1694
1695 ha->fw_dump->eft_size = htonl(eft_size);
1696 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1697 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1698
1699 ha->fw_dump->header_size =
1700 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1701}
1702
18e7555a
AV		 1703static int
1704qla81xx_mpi_sync(scsi_qla_host_t *vha)
1705{
1706#define MPS_MASK 0xe0
1707 int rval;
1708 uint16_t dc;
1709 uint32_t dw;
18e7555a
AV		 1710
1711 if (!IS_QLA81XX(vha->hw))
1712 return QLA_SUCCESS;
1713
1714 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1715 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1716 ql_log(ql_log_warn, vha, 0x0105,
1717 "Unable to acquire semaphore.\n");
18e7555a
AV		 1718 goto done;
1719 }
1720
1721 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1722 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1723 if (rval != QLA_SUCCESS) {
7c3df132 1724 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1725 goto done_release;
1726 }
1727
1728 dc &= MPS_MASK;
1729 if (dc == (dw & MPS_MASK))
1730 goto done_release;
1731
1732 dw &= ~MPS_MASK;
1733 dw |= dc;
1734 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1735 if (rval != QLA_SUCCESS) {
7c3df132 1736 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1737 }
1738
1739done_release:
1740 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1741 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1742 ql_log(ql_log_warn, vha, 0x006d,
1743 "Unable to release semaphore.\n");
18e7555a
AV		 1744 }
1745
1746done:
1747 return rval;
1748}
1749
8d93f550
CD		 1750int
1751qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1752{
1753 /* Don't try to reallocate the array */
1754 if (req->outstanding_cmds)
1755 return QLA_SUCCESS;
1756
1757 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1758 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1759 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1760 else {
1761 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1762 req->num_outstanding_cmds = ha->fw_xcb_count;
1763 else
1764 req->num_outstanding_cmds = ha->fw_iocb_count;
1765 }
1766
1767 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1768 req->num_outstanding_cmds, GFP_KERNEL);
1769
1770 if (!req->outstanding_cmds) {
1771 /*
1772 * Try to allocate a minimal size just so we can get through
1773 * initialization.
1774 */
1775 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1776 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1777 req->num_outstanding_cmds, GFP_KERNEL);
1778
1779 if (!req->outstanding_cmds) {
1780 ql_log(ql_log_fatal, NULL, 0x0126,
1781 "Failed to allocate memory for "
1782 "outstanding_cmds for req_que %p.\n", req);
1783 req->num_outstanding_cmds = 0;
1784 return QLA_FUNCTION_FAILED;
1785 }
1786 }
1787
1788 return QLA_SUCCESS;
1789}
1790
1da177e4
LT		 1791/**
1792 * qla2x00_setup_chip() - Load and start RISC firmware.
1793 * @ha: HA context
1794 *
1795 * Returns 0 on success.
1796 */
1797static int
e315cd28 1798qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1799{
0107109e
AV		 1800 int rval;
1801 uint32_t srisc_address = 0;
e315cd28 1802 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1803 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1804 unsigned long flags;
dda772e8 1805 uint16_t fw_major_version;
3db0652e 1806
7ec0effd 1807 if (IS_P3P_TYPE(ha)) {
a9083016 1808 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1809 if (rval == QLA_SUCCESS) {
1810 qla2x00_stop_firmware(vha);
a9083016 1811 goto enable_82xx_npiv;
14e303d9 1812 } else
b963752f 1813 goto failed;
a9083016
GM		 1814 }
1815
3db0652e
AV		 1816 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1817 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1818 spin_lock_irqsave(&ha->hardware_lock, flags);
1819 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1820 RD_REG_WORD(&reg->hccr);
1821 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1822 }
1da177e4 1823
18e7555a
AV		 1824 qla81xx_mpi_sync(vha);
1825
1da177e4 1826 /* Load firmware sequences */
e315cd28 1827 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1828 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1829 ql_dbg(ql_dbg_init, vha, 0x00c9,
1830 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1831
e315cd28 1832 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1833 if (rval == QLA_SUCCESS) {
1834 /* Start firmware execution. */
7c3df132
SK		 1835 ql_dbg(ql_dbg_init, vha, 0x00ca,
1836 "Starting firmware.\n");
1da177e4 1837
e315cd28 1838 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1839 /* Retrieve firmware information. */
dda772e8 1840 if (rval == QLA_SUCCESS) {
a9083016 1841enable_82xx_npiv:
dda772e8 1842 fw_major_version = ha->fw_major_version;
7ec0effd 1843 if (IS_P3P_TYPE(ha))
3173167f 1844 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1845 else
1846 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1847 if (rval != QLA_SUCCESS)
1848 goto failed;
2c3dfe3f 1849 ha->flags.npiv_supported = 0;
e315cd28 1850 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1851 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1852 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1853 if ((!ha->max_npiv_vports) ||
1854 ((ha->max_npiv_vports + 1) %
eb66dc60 1855 MIN_MULTI_ID_FABRIC))
4d0ea247 1856 ha->max_npiv_vports =
eb66dc60 1857 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1858 }
24a08138 1859 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1860 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1861 &ha->max_npiv_vports, NULL);
d743de66 1862
8d93f550
CD		 1863 /*
1864 * Allocate the array of outstanding commands
1865 * now that we know the firmware resources.
1866 */
1867 rval = qla2x00_alloc_outstanding_cmds(ha,
1868 vha->req);
1869 if (rval != QLA_SUCCESS)
1870 goto failed;
1871
be5ea3cf 1872 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1873 && !(IS_P3P_TYPE(ha)))
08de2844 1874 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1875 } else {
1876 goto failed;
1da177e4
LT		 1877 }
1878 } else {
7c3df132
SK		 1879 ql_log(ql_log_fatal, vha, 0x00cd,
1880 "ISP Firmware failed checksum.\n");
1881 goto failed;
1da177e4 1882 }
c74d88a4
AV		 1883 } else
1884 goto failed;
1da177e4 1885
3db0652e
AV		 1886 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1887 /* Enable proper parity. */
1888 spin_lock_irqsave(&ha->hardware_lock, flags);
1889 if (IS_QLA2300(ha))
1890 /* SRAM parity */
1891 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1892 else
1893 /* SRAM, Instruction RAM and GP RAM parity */
1894 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1895 RD_REG_WORD(&reg->hccr);
1896 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1897 }
1898
f3982d89
CD		 1899 if (IS_QLA27XX(ha))
1900 ha->flags.fac_supported = 1;
1901 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 1902 uint32_t size;
1903
1904 rval = qla81xx_fac_get_sector_size(vha, &size);
1905 if (rval == QLA_SUCCESS) {
1906 ha->flags.fac_supported = 1;
1907 ha->fdt_block_size = size << 2;
1908 } else {
7c3df132 1909 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1910 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1911 ha->fw_major_version, ha->fw_minor_version,
1912 ha->fw_subminor_version);
1ca60e3b 1913
f73cb695 1914 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1915 ha->flags.fac_supported = 0;
1916 rval = QLA_SUCCESS;
1917 }
1d2874de
JC		 1918 }
1919 }
ca9e9c3e 1920failed:
1da177e4 1921 if (rval) {
7c3df132
SK		 1922 ql_log(ql_log_fatal, vha, 0x00cf,
1923 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1924 }
1925
1926 return (rval);
1927}
1928
1929/**
1930 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1931 * @ha: HA context
1932 *
1933 * Beginning of request ring has initialization control block already built
1934 * by nvram config routine.
1935 *
1936 * Returns 0 on success.
1937 */
73208dfd
AC		 1938void
1939qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1940{
1941 uint16_t cnt;
1942 response_t *pkt;
1943
2afa19a9
AC		 1944 rsp->ring_ptr = rsp->ring;
1945 rsp->ring_index = 0;
1946 rsp->status_srb = NULL;
e315cd28
AC		 1947 pkt = rsp->ring_ptr;
1948 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1949 pkt->signature = RESPONSE_PROCESSED;
1950 pkt++;
1951 }
1da177e4
LT		 1952}
1953
1954/**
1955 * qla2x00_update_fw_options() - Read and process firmware options.
1956 * @ha: HA context
1957 *
1958 * Returns 0 on success.
1959 */
abbd8870 1960void
e315cd28 1961qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1962{
1963 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1964 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1965
1966 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1967 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1968
1969 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1970 return;
1971
1972 /* Serial Link options. */
7c3df132
SK		 1973 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1974 "Serial link options.\n");
1975 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1976 (uint8_t *)&ha->fw_seriallink_options,
1977 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1978
1979 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1980 if (ha->fw_seriallink_options[3] & BIT_2) {
1981 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1982
1983 /* 1G settings */
1984 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1985 emphasis = (ha->fw_seriallink_options[2] &
1986 (BIT_4 | BIT_3)) >> 3;
1987 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1988 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1989 rx_sens = (ha->fw_seriallink_options[0] &
1990 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1991 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1992 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1993 if (rx_sens == 0x0)
1994 rx_sens = 0x3;
1995 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1996 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1997 ha->fw_options[10] |= BIT_5 |
1998 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1999 (tx_sens & (BIT_1 | BIT_0));
2000
2001 /* 2G settings */
2002 swing = (ha->fw_seriallink_options[2] &
2003 (BIT_7 | BIT_6 | BIT_5)) >> 5;
2004 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
2005 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 2006 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2007 rx_sens = (ha->fw_seriallink_options[1] &
2008 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2009 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
2010 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2011 if (rx_sens == 0x0)
2012 rx_sens = 0x3;
2013 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
2014 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2015 ha->fw_options[11] |= BIT_5 |
2016 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2017 (tx_sens & (BIT_1 | BIT_0));
2018 }
2019
2020 /* FCP2 options. */
2021 /* Return command IOCBs without waiting for an ABTS to complete. */
2022 ha->fw_options[3] |= BIT_13;
2023
2024 /* LED scheme. */
2025 if (ha->flags.enable_led_scheme)
2026 ha->fw_options[2] |= BIT_12;
2027
48c02fde 2028 /* Detect ISP6312. */
2029 if (IS_QLA6312(ha))
2030 ha->fw_options[2] |= BIT_13;
2031
1da177e4 2032 /* Update firmware options. */
e315cd28 2033 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 2034}
2035
0107109e 2036void
e315cd28 2037qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 2038{
2039 int rval;
e315cd28 2040 struct qla_hw_data *ha = vha->hw;
0107109e 2041
7ec0effd 2042 if (IS_P3P_TYPE(ha))
a9083016
GM		 2043 return;
2044
0107109e 2045 /* Update Serial Link options. */
f94097ed 2046 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 2047 return;
2048
e315cd28 2049 rval = qla2x00_set_serdes_params(vha,
f94097ed 2050 le16_to_cpu(ha->fw_seriallink_options24[1]),
2051 le16_to_cpu(ha->fw_seriallink_options24[2]),
2052 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2053 if (rval != QLA_SUCCESS) {
7c3df132 2054 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2055 "Unable to update Serial Link options (%x).\n", rval);
2056 }
2057}
2058
abbd8870 2059void
e315cd28 2060qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2061{
e315cd28 2062 struct qla_hw_data *ha = vha->hw;
3d71644c 2063 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2064 struct req_que *req = ha->req_q_map[0];
2065 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2066
2067 /* Setup ring parameters in initialization control block. */
2068 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
2069 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2070 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2071 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2072 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2073 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2074 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2075 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2076
2077 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2078 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2079 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2080 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2081 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
2082}
2083
0107109e 2084void
e315cd28 2085qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 2086{
e315cd28 2087 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2088 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
2089 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2090 struct qla_msix_entry *msix;
0107109e 2091 struct init_cb_24xx *icb;
73208dfd
AC		 2092 uint16_t rid = 0;
2093 struct req_que *req = ha->req_q_map[0];
2094 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 2095
6246b8a1 2096 /* Setup ring parameters in initialization control block. */
0107109e
AV		 2097 icb = (struct init_cb_24xx *)ha->init_cb;
2098 icb->request_q_outpointer = __constant_cpu_to_le16(0);
2099 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2100 icb->request_q_length = cpu_to_le16(req->length);
2101 icb->response_q_length = cpu_to_le16(rsp->length);
2102 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2103 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2104 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2105 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 2106
2d70c103
NB		 2107 /* Setup ATIO queue dma pointers for target mode */
2108 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
2109 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2110 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2111 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2112
7c6300e3
JC		 2113 if (IS_SHADOW_REG_CAPABLE(ha))
2114 icb->firmware_options_2 |=
2115 __constant_cpu_to_le32(BIT_30|BIT_29);
2116
f73cb695 2117 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
73208dfd
AC		 2118 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2119 icb->rid = __constant_cpu_to_le16(rid);
2120 if (ha->flags.msix_enabled) {
2121 msix = &ha->msix_entries[1];
7c3df132
SK		 2122 ql_dbg(ql_dbg_init, vha, 0x00fd,
2123 "Registering vector 0x%x for base que.\n",
2124 msix->entry);
73208dfd
AC		 2125 icb->msix = cpu_to_le16(msix->entry);
2126 }
2127 /* Use alternate PCI bus number */
2128 if (MSB(rid))
2129 icb->firmware_options_2 |=
2130 __constant_cpu_to_le32(BIT_19);
2131 /* Use alternate PCI devfn */
2132 if (LSB(rid))
2133 icb->firmware_options_2 |=
2134 __constant_cpu_to_le32(BIT_18);
2135
3155754a 2136 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 2137 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2138 (ha->flags.msix_enabled)) {
3155754a
AC		 2139 icb->firmware_options_2 &=
2140 __constant_cpu_to_le32(~BIT_22);
2141 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 2142 ql_dbg(ql_dbg_init, vha, 0x00fe,
2143 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 2144 } else {
2145 icb->firmware_options_2 |=
2146 __constant_cpu_to_le32(BIT_22);
2147 }
73208dfd 2148 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 2149
2150 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2151 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2152 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2153 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2154 } else {
2155 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2156 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2157 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2158 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2159 }
aa230bc5 2160 qlt_24xx_config_rings(vha);
2d70c103 2161
73208dfd
AC		 2162 /* PCI posting */
2163 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2164}
2165
1da177e4
LT		 2166/**
2167 * qla2x00_init_rings() - Initializes firmware.
2168 * @ha: HA context
2169 *
2170 * Beginning of request ring has initialization control block already built
2171 * by nvram config routine.
2172 *
2173 * Returns 0 on success.
2174 */
8ae6d9c7 2175int
e315cd28 2176qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2177{
2178 int rval;
2179 unsigned long flags = 0;
29bdccbe 2180 int cnt, que;
e315cd28 2181 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2182 struct req_que *req;
2183 struct rsp_que *rsp;
2c3dfe3f
SJ		 2184 struct mid_init_cb_24xx *mid_init_cb =
2185 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2186
2187 spin_lock_irqsave(&ha->hardware_lock, flags);
2188
2189 /* Clear outstanding commands array. */
2afa19a9 2190 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2191 req = ha->req_q_map[que];
2192 if (!req)
2193 continue;
7c6300e3
JC		 2194 req->out_ptr = (void *)(req->ring + req->length);
2195 *req->out_ptr = 0;
8d93f550 2196 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2197 req->outstanding_cmds[cnt] = NULL;
1da177e4 2198
2afa19a9 2199 req->current_outstanding_cmd = 1;
1da177e4 2200
29bdccbe
AC		 2201 /* Initialize firmware. */
2202 req->ring_ptr = req->ring;
2203 req->ring_index = 0;
2204 req->cnt = req->length;
2205 }
1da177e4 2206
2afa19a9 2207 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2208 rsp = ha->rsp_q_map[que];
2209 if (!rsp)
2210 continue;
7c6300e3
JC		 2211 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
2212 *rsp->in_ptr = 0;
29bdccbe 2213 /* Initialize response queue entries */
8ae6d9c7
GM		 2214 if (IS_QLAFX00(ha))
2215 qlafx00_init_response_q_entries(rsp);
2216 else
2217 qla2x00_init_response_q_entries(rsp);
29bdccbe 2218 }
1da177e4 2219
2d70c103
NB		 2220 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2221 ha->tgt.atio_ring_index = 0;
2222 /* Initialize ATIO queue entries */
2223 qlt_init_atio_q_entries(vha);
2224
e315cd28 2225 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2226
2227 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2228
8ae6d9c7
GM		 2229 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2230
2231 if (IS_QLAFX00(ha)) {
2232 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2233 goto next_check;
2234 }
2235
1da177e4 2236 /* Update any ISP specific firmware options before initialization. */
e315cd28 2237 ha->isp_ops->update_fw_options(vha);
1da177e4 2238
605aa2bc 2239 if (ha->flags.npiv_supported) {
45980cc2 2240 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2241 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2242 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2243 }
2244
24a08138
AV		 2245 if (IS_FWI2_CAPABLE(ha)) {
2246 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2247 mid_init_cb->init_cb.execution_throttle =
2248 cpu_to_le16(ha->fw_xcb_count);
25232cc9
HM		 2249 /* D-Port Status */
2250 if (IS_DPORT_CAPABLE(ha))
2251 mid_init_cb->init_cb.firmware_options_1 |=
2252 cpu_to_le16(BIT_7);
2486c627
HM		 2253 /* Enable FA-WWPN */
2254 ha->flags.fawwpn_enabled =
2255 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) ? 1 : 0;
2256 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n",
2257 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 2258 }
2c3dfe3f 2259
e315cd28 2260 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2261next_check:
1da177e4 2262 if (rval) {
7c3df132
SK		 2263 ql_log(ql_log_fatal, vha, 0x00d2,
2264 "Init Firmware **** FAILED ****.\n");
1da177e4 2265 } else {
7c3df132
SK		 2266 ql_dbg(ql_dbg_init, vha, 0x00d3,
2267 "Init Firmware -- success.\n");
1da177e4
LT		 2268 }
2269
2270 return (rval);
2271}
2272
2273/**
2274 * qla2x00_fw_ready() - Waits for firmware ready.
2275 * @ha: HA context
2276 *
2277 * Returns 0 on success.
2278 */
2279static int
e315cd28 2280qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2281{
2282 int rval;
4d4df193 2283 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2284 uint16_t min_wait; /* Minimum wait time if loop is down */
2285 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 2286 uint16_t state[6];
e315cd28 2287 struct qla_hw_data *ha = vha->hw;
1da177e4 2288
8ae6d9c7
GM		 2289 if (IS_QLAFX00(vha->hw))
2290 return qlafx00_fw_ready(vha);
2291
1da177e4
LT		 2292 rval = QLA_SUCCESS;
2293
33461491
CD		 2294 /* Time to wait for loop down */
2295 if (IS_P3P_TYPE(ha))
2296 min_wait = 30;
2297 else
2298 min_wait = 20;
1da177e4
LT		 2299
2300 /*
2301 * Firmware should take at most one RATOV to login, plus 5 seconds for
2302 * our own processing.
2303 */
2304 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2305 wait_time = min_wait;
2306 }
2307
2308 /* Min wait time if loop down */
2309 mtime = jiffies + (min_wait * HZ);
2310
2311 /* wait time before firmware ready */
2312 wtime = jiffies + (wait_time * HZ);
2313
2314 /* Wait for ISP to finish LIP */
e315cd28 2315 if (!vha->flags.init_done)
7c3df132
SK		 2316 ql_log(ql_log_info, vha, 0x801e,
2317 "Waiting for LIP to complete.\n");
1da177e4
LT		 2318
2319 do {
5b939038 2320 memset(state, -1, sizeof(state));
e315cd28 2321 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2322 if (rval == QLA_SUCCESS) {
4d4df193 2323 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2324 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2325 }
4d4df193 2326 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2327 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2328 "fw_state=%x 84xx=%x.\n", state[0],
2329 state[2]);
4d4df193
HK		 2330 if ((state[2] & FSTATE_LOGGED_IN) &&
2331 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2332 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2333 "Sending verify iocb.\n");
4d4df193
HK		 2334
2335 cs84xx_time = jiffies;
e315cd28 2336 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2337 if (rval != QLA_SUCCESS) {
2338 ql_log(ql_log_warn,
cfb0919c 2339 vha, 0x8007,
7c3df132 2340 "Init chip failed.\n");
4d4df193 2341 break;
7c3df132 2342 }
4d4df193
HK		 2343
2344 /* Add time taken to initialize. */
2345 cs84xx_time = jiffies - cs84xx_time;
2346 wtime += cs84xx_time;
2347 mtime += cs84xx_time;
cfb0919c 2348 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2349 "Increasing wait time by %ld. "
2350 "New time %ld.\n", cs84xx_time,
2351 wtime);
4d4df193
HK		 2352 }
2353 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2354 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2355 "F/W Ready - OK.\n");
1da177e4 2356
e315cd28 2357 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2358 &ha->login_timeout, &ha->r_a_tov);
2359
2360 rval = QLA_SUCCESS;
2361 break;
2362 }
2363
2364 rval = QLA_FUNCTION_FAILED;
2365
e315cd28 2366 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2367 state[0] != FSTATE_READY) {
1da177e4 2368 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2369 * other than Wait for Login.
2370 */
1da177e4 2371 if (time_after_eq(jiffies, mtime)) {
7c3df132 2372 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2373 "Cable is unplugged...\n");
2374
e315cd28 2375 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2376 break;
2377 }
2378 }
2379 } else {
2380 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2381 if (time_after_eq(jiffies, mtime) ||
7190575f 2382 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2383 break;
2384 }
2385
2386 if (time_after_eq(jiffies, wtime))
2387 break;
2388
2389 /* Delay for a while */
2390 msleep(500);
1da177e4
LT		 2391 } while (1);
2392
7c3df132 2393 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 2394 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
2395 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 2396
cfb0919c 2397 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2398 ql_log(ql_log_warn, vha, 0x803b,
2399 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2400 }
2401
2402 return (rval);
2403}
2404
2405/*
2406* qla2x00_configure_hba
2407* Setup adapter context.
2408*
2409* Input:
2410* ha = adapter state pointer.
2411*
2412* Returns:
2413* 0 = success
2414*
2415* Context:
2416* Kernel context.
2417*/
2418static int
e315cd28 2419qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2420{
2421 int rval;
2422 uint16_t loop_id;
2423 uint16_t topo;
2c3dfe3f 2424 uint16_t sw_cap;
1da177e4
LT		 2425 uint8_t al_pa;
2426 uint8_t area;
2427 uint8_t domain;
2428 char connect_type[22];
e315cd28 2429 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2430 unsigned long flags;
61e1b269 2431 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2432
2433 /* Get host addresses. */
e315cd28 2434 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2435 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2436 if (rval != QLA_SUCCESS) {
e315cd28 2437 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2438 IS_CNA_CAPABLE(ha) ||
33135aa2 2439 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2440 ql_dbg(ql_dbg_disc, vha, 0x2008,
2441 "Loop is in a transition state.\n");
33135aa2 2442 } else {
7c3df132
SK		 2443 ql_log(ql_log_warn, vha, 0x2009,
2444 "Unable to get host loop ID.\n");
61e1b269
JC		 2445 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2446 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2447 ql_log(ql_log_warn, vha, 0x1151,
2448 "Doing link init.\n");
2449 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2450 return rval;
2451 }
e315cd28 2452 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2453 }
1da177e4
LT		 2454 return (rval);
2455 }
2456
2457 if (topo == 4) {
7c3df132
SK		 2458 ql_log(ql_log_info, vha, 0x200a,
2459 "Cannot get topology - retrying.\n");
1da177e4
LT		 2460 return (QLA_FUNCTION_FAILED);
2461 }
2462
e315cd28 2463 vha->loop_id = loop_id;
1da177e4
LT		 2464
2465 /* initialize */
2466 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2467 ha->operating_mode = LOOP;
2c3dfe3f 2468 ha->switch_cap = 0;
1da177e4
LT		 2469
2470 switch (topo) {
2471 case 0:
7c3df132 2472 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2473 ha->current_topology = ISP_CFG_NL;
2474 strcpy(connect_type, "(Loop)");
2475 break;
2476
2477 case 1:
7c3df132 2478 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2479 ha->switch_cap = sw_cap;
1da177e4
LT		 2480 ha->current_topology = ISP_CFG_FL;
2481 strcpy(connect_type, "(FL_Port)");
2482 break;
2483
2484 case 2:
7c3df132 2485 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2486 ha->operating_mode = P2P;
2487 ha->current_topology = ISP_CFG_N;
2488 strcpy(connect_type, "(N_Port-to-N_Port)");
2489 break;
2490
2491 case 3:
7c3df132 2492 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2493 ha->switch_cap = sw_cap;
1da177e4
LT		 2494 ha->operating_mode = P2P;
2495 ha->current_topology = ISP_CFG_F;
2496 strcpy(connect_type, "(F_Port)");
2497 break;
2498
2499 default:
7c3df132
SK		 2500 ql_dbg(ql_dbg_disc, vha, 0x200f,
2501 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2502 ha->current_topology = ISP_CFG_NL;
2503 strcpy(connect_type, "(Loop)");
2504 break;
2505 }
2506
2507 /* Save Host port and loop ID. */
2508 /* byte order - Big Endian */
e315cd28
AC		 2509 vha->d_id.b.domain = domain;
2510 vha->d_id.b.area = area;
2511 vha->d_id.b.al_pa = al_pa;
1da177e4 2512
f24b5cb8 2513 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2514 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2515 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2516
e315cd28 2517 if (!vha->flags.init_done)
7c3df132
SK		 2518 ql_log(ql_log_info, vha, 0x2010,
2519 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2520 connect_type, vha->loop_id);
1da177e4 2521
1da177e4
LT		 2522 return(rval);
2523}
2524
a9083016 2525inline void
e315cd28
AC		 2526qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2527 char *def)
9bb9fcf2
AV		 2528{
2529 char *st, *en;
2530 uint16_t index;
e315cd28 2531 struct qla_hw_data *ha = vha->hw;
ab671149 2532 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2533 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2534
2535 if (memcmp(model, BINZERO, len) != 0) {
2536 strncpy(ha->model_number, model, len);
2537 st = en = ha->model_number;
2538 en += len - 1;
2539 while (en > st) {
2540 if (*en != 0x20 && *en != 0x00)
2541 break;
2542 *en-- = '\0';
2543 }
2544
2545 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2546 if (use_tbl &&
2547 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2548 index < QLA_MODEL_NAMES)
1ee27146
JC		 2549 strncpy(ha->model_desc,
2550 qla2x00_model_name[index * 2 + 1],
2551 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2552 } else {
2553 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2554 if (use_tbl &&
2555 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2556 index < QLA_MODEL_NAMES) {
2557 strcpy(ha->model_number,
2558 qla2x00_model_name[index * 2]);
1ee27146
JC		 2559 strncpy(ha->model_desc,
2560 qla2x00_model_name[index * 2 + 1],
2561 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2562 } else {
2563 strcpy(ha->model_number, def);
2564 }
2565 }
1ee27146 2566 if (IS_FWI2_CAPABLE(ha))
e315cd28 2567 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2568 sizeof(ha->model_desc));
9bb9fcf2
AV		 2569}
2570
4e08df3f
DM		 2571/* On sparc systems, obtain port and node WWN from firmware
2572 * properties.
2573 */
e315cd28 2574static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2575{
2576#ifdef CONFIG_SPARC
e315cd28 2577 struct qla_hw_data *ha = vha->hw;
4e08df3f 2578 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2579 struct device_node *dp = pci_device_to_OF_node(pdev);
2580 const u8 *val;
4e08df3f
DM		 2581 int len;
2582
2583 val = of_get_property(dp, "port-wwn", &len);
2584 if (val && len >= WWN_SIZE)
2585 memcpy(nv->port_name, val, WWN_SIZE);
2586
2587 val = of_get_property(dp, "node-wwn", &len);
2588 if (val && len >= WWN_SIZE)
2589 memcpy(nv->node_name, val, WWN_SIZE);
2590#endif
2591}
2592
1da177e4
LT		 2593/*
2594* NVRAM configuration for ISP 2xxx
2595*
2596* Input:
2597* ha = adapter block pointer.
2598*
2599* Output:
2600* initialization control block in response_ring
2601* host adapters parameters in host adapter block
2602*
2603* Returns:
2604* 0 = success.
2605*/
abbd8870 2606int
e315cd28 2607qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2608{
4e08df3f 2609 int rval;
0107109e
AV		 2610 uint8_t chksum = 0;
2611 uint16_t cnt;
2612 uint8_t *dptr1, *dptr2;
e315cd28 2613 struct qla_hw_data *ha = vha->hw;
0107109e 2614 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2615 nvram_t *nv = ha->nvram;
2616 uint8_t *ptr = ha->nvram;
3d71644c 2617 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2618
4e08df3f
DM		 2619 rval = QLA_SUCCESS;
2620
1da177e4 2621 /* Determine NVRAM starting address. */
0107109e 2622 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2623 ha->nvram_base = 0;
2624 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2625 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2626 ha->nvram_base = 0x80;
2627
2628 /* Get NVRAM data and calculate checksum. */
e315cd28 2629 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2630 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2631 chksum += *ptr++;
1da177e4 2632
7c3df132
SK		 2633 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2634 "Contents of NVRAM.\n");
2635 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2636 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2637
2638 /* Bad NVRAM data, set defaults parameters. */
2639 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2640 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2641 /* Reset NVRAM data. */
7c3df132 2642 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2643 "Inconsistent NVRAM "
7c3df132
SK		 2644 "detected: checksum=0x%x id=%c version=0x%x.\n",
2645 chksum, nv->id[0], nv->nvram_version);
2646 ql_log(ql_log_warn, vha, 0x0065,
2647 "Falling back to "
2648 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2649
2650 /*
2651 * Set default initialization control block.
2652 */
2653 memset(nv, 0, ha->nvram_size);
2654 nv->parameter_block_version = ICB_VERSION;
2655
2656 if (IS_QLA23XX(ha)) {
2657 nv->firmware_options[0] = BIT_2 | BIT_1;
2658 nv->firmware_options[1] = BIT_7 | BIT_5;
2659 nv->add_firmware_options[0] = BIT_5;
2660 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2661 nv->frame_payload_size = 2048;
4e08df3f
DM		 2662 nv->special_options[1] = BIT_7;
2663 } else if (IS_QLA2200(ha)) {
2664 nv->firmware_options[0] = BIT_2 | BIT_1;
2665 nv->firmware_options[1] = BIT_7 | BIT_5;
2666 nv->add_firmware_options[0] = BIT_5;
2667 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2668 nv->frame_payload_size = 1024;
4e08df3f
DM		 2669 } else if (IS_QLA2100(ha)) {
2670 nv->firmware_options[0] = BIT_3 | BIT_1;
2671 nv->firmware_options[1] = BIT_5;
98aee70d 2672 nv->frame_payload_size = 1024;
4e08df3f
DM		 2673 }
2674
2675 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2676 nv->execution_throttle = __constant_cpu_to_le16(16);
2677 nv->retry_count = 8;
2678 nv->retry_delay = 1;
2679
2680 nv->port_name[0] = 33;
2681 nv->port_name[3] = 224;
2682 nv->port_name[4] = 139;
2683
e315cd28 2684 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2685
2686 nv->login_timeout = 4;
2687
2688 /*
2689 * Set default host adapter parameters
2690 */
2691 nv->host_p[1] = BIT_2;
2692 nv->reset_delay = 5;
2693 nv->port_down_retry_count = 8;
2694 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2695 nv->link_down_timeout = 60;
2696
2697 rval = 1;
1da177e4
LT		 2698 }
2699
2700#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2701 /*
2702 * The SN2 does not provide BIOS emulation which means you can't change
2703 * potentially bogus BIOS settings. Force the use of default settings
2704 * for link rate and frame size. Hope that the rest of the settings
2705 * are valid.
2706 */
2707 if (ia64_platform_is("sn2")) {
98aee70d 2708 nv->frame_payload_size = 2048;
1da177e4
LT		 2709 if (IS_QLA23XX(ha))
2710 nv->special_options[1] = BIT_7;
2711 }
2712#endif
2713
2714 /* Reset Initialization control block */
0107109e 2715 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2716
2717 /*
2718 * Setup driver NVRAM options.
2719 */
2720 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2721 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2722 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2723 nv->firmware_options[1] &= ~BIT_4;
2724
2725 if (IS_QLA23XX(ha)) {
2726 nv->firmware_options[0] |= BIT_2;
2727 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2728 nv->special_options[0] &= ~BIT_6;
0107109e 2729 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2730
2731 if (IS_QLA2300(ha)) {
2732 if (ha->fb_rev == FPM_2310) {
2733 strcpy(ha->model_number, "QLA2310");
2734 } else {
2735 strcpy(ha->model_number, "QLA2300");
2736 }
2737 } else {
e315cd28 2738 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2739 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2740 }
2741 } else if (IS_QLA2200(ha)) {
2742 nv->firmware_options[0] |= BIT_2;
2743 /*
2744 * 'Point-to-point preferred, else loop' is not a safe
2745 * connection mode setting.
2746 */
2747 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2748 (BIT_5 | BIT_4)) {
2749 /* Force 'loop preferred, else point-to-point'. */
2750 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2751 nv->add_firmware_options[0] |= BIT_5;
2752 }
2753 strcpy(ha->model_number, "QLA22xx");
2754 } else /*if (IS_QLA2100(ha))*/ {
2755 strcpy(ha->model_number, "QLA2100");
2756 }
2757
2758 /*
2759 * Copy over NVRAM RISC parameter block to initialization control block.
2760 */
2761 dptr1 = (uint8_t *)icb;
2762 dptr2 = (uint8_t *)&nv->parameter_block_version;
2763 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2764 while (cnt--)
2765 *dptr1++ = *dptr2++;
2766
2767 /* Copy 2nd half. */
2768 dptr1 = (uint8_t *)icb->add_firmware_options;
2769 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2770 while (cnt--)
2771 *dptr1++ = *dptr2++;
2772
5341e868
AV		 2773 /* Use alternate WWN? */
2774 if (nv->host_p[1] & BIT_7) {
2775 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2776 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2777 }
2778
1da177e4
LT		 2779 /* Prepare nodename */
2780 if ((icb->firmware_options[1] & BIT_6) == 0) {
2781 /*
2782 * Firmware will apply the following mask if the nodename was
2783 * not provided.
2784 */
2785 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2786 icb->node_name[0] &= 0xF0;
2787 }
2788
2789 /*
2790 * Set host adapter parameters.
2791 */
3ce8866c
SK		 2792
2793 /*
2794 * BIT_7 in the host-parameters section allows for modification to
2795 * internal driver logging.
2796 */
0181944f 2797 if (nv->host_p[0] & BIT_7)
cfb0919c 2798 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2799 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2800 /* Always load RISC code on non ISP2[12]00 chips. */
2801 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2802 ha->flags.disable_risc_code_load = 0;
2803 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2804 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2805 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2806 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2807 ha->flags.disable_serdes = 0;
1da177e4
LT		 2808
2809 ha->operating_mode =
2810 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2811
2812 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2813 sizeof(ha->fw_seriallink_options));
2814
2815 /* save HBA serial number */
2816 ha->serial0 = icb->port_name[5];
2817 ha->serial1 = icb->port_name[6];
2818 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2819 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2820 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2821
2822 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2823
2824 ha->retry_count = nv->retry_count;
2825
2826 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2827 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2828 nv->login_timeout = ql2xlogintimeout;
2829 if (nv->login_timeout < 4)
2830 nv->login_timeout = 4;
2831 ha->login_timeout = nv->login_timeout;
2832 icb->login_timeout = nv->login_timeout;
2833
00a537b8
AV		 2834 /* Set minimum RATOV to 100 tenths of a second. */
2835 ha->r_a_tov = 100;
1da177e4 2836
1da177e4
LT		 2837 ha->loop_reset_delay = nv->reset_delay;
2838
1da177e4
LT		 2839 /* Link Down Timeout = 0:
2840 *
2841 * When Port Down timer expires we will start returning
2842 * I/O's to OS with "DID_NO_CONNECT".
2843 *
2844 * Link Down Timeout != 0:
2845 *
2846 * The driver waits for the link to come up after link down
2847 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2848 */
1da177e4
LT		 2849 if (nv->link_down_timeout == 0) {
2850 ha->loop_down_abort_time =
354d6b21 2851 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2852 } else {
2853 ha->link_down_timeout = nv->link_down_timeout;
2854 ha->loop_down_abort_time =
2855 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2856 }
1da177e4 2857
1da177e4
LT		 2858 /*
2859 * Need enough time to try and get the port back.
2860 */
2861 ha->port_down_retry_count = nv->port_down_retry_count;
2862 if (qlport_down_retry)
2863 ha->port_down_retry_count = qlport_down_retry;
2864 /* Set login_retry_count */
2865 ha->login_retry_count = nv->retry_count;
2866 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2867 ha->port_down_retry_count > 3)
2868 ha->login_retry_count = ha->port_down_retry_count;
2869 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2870 ha->login_retry_count = ha->port_down_retry_count;
2871 if (ql2xloginretrycount)
2872 ha->login_retry_count = ql2xloginretrycount;
2873
1da177e4
LT		 2874 icb->lun_enables = __constant_cpu_to_le16(0);
2875 icb->command_resource_count = 0;
2876 icb->immediate_notify_resource_count = 0;
2877 icb->timeout = __constant_cpu_to_le16(0);
2878
2879 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2880 /* Enable RIO */
2881 icb->firmware_options[0] &= ~BIT_3;
2882 icb->add_firmware_options[0] &=
2883 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2884 icb->add_firmware_options[0] |= BIT_2;
2885 icb->response_accumulation_timer = 3;
2886 icb->interrupt_delay_timer = 5;
2887
e315cd28 2888 vha->flags.process_response_queue = 1;
1da177e4 2889 } else {
4fdfefe5 2890 /* Enable ZIO. */
e315cd28 2891 if (!vha->flags.init_done) {
4fdfefe5
AV		 2892 ha->zio_mode = icb->add_firmware_options[0] &
2893 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2894 ha->zio_timer = icb->interrupt_delay_timer ?
2895 icb->interrupt_delay_timer: 2;
2896 }
1da177e4
LT		 2897 icb->add_firmware_options[0] &=
2898 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2899 vha->flags.process_response_queue = 0;
4fdfefe5 2900 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 2901 ha->zio_mode = QLA_ZIO_MODE_6;
2902
7c3df132 2903 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2904 "ZIO mode %d enabled; timer delay (%d us).\n",
2905 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2906
4fdfefe5
AV		 2907 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2908 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2909 vha->flags.process_response_queue = 1;
1da177e4
LT		 2910 }
2911 }
2912
4e08df3f 2913 if (rval) {
7c3df132
SK		 2914 ql_log(ql_log_warn, vha, 0x0069,
2915 "NVRAM configuration failed.\n");
4e08df3f
DM		 2916 }
2917 return (rval);
1da177e4
LT		 2918}
2919
19a7b4ae
JSEC		 2920static void
2921qla2x00_rport_del(void *data)
2922{
2923 fc_port_t *fcport = data;
d97994dc 2924 struct fc_rport *rport;
2d70c103 2925 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2926 unsigned long flags;
d97994dc 2927
044d78e1 2928 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2929 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2930 fcport->drport = NULL;
044d78e1 2931 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2932 if (rport) {
d97994dc 2933 fc_remote_port_delete(rport);
2d70c103
NB		 2934 /*
2935 * Release the target mode FC NEXUS in qla_target.c code
2936 * if target mod is enabled.
2937 */
2938 qlt_fc_port_deleted(vha, fcport);
2939 }
19a7b4ae
JSEC		 2940}
2941
1da177e4
LT		 2942/**
2943 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2944 * @ha: HA context
2945 * @flags: allocation flags
2946 *
2947 * Returns a pointer to the allocated fcport, or NULL, if none available.
2948 */
9a069e19 2949fc_port_t *
e315cd28 2950qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2951{
2952 fc_port_t *fcport;
2953
bbfbbbc1
MK		 2954 fcport = kzalloc(sizeof(fc_port_t), flags);
2955 if (!fcport)
2956 return NULL;
1da177e4
LT		 2957
2958 /* Setup fcport template structure. */
e315cd28 2959 fcport->vha = vha;
1da177e4
LT		 2960 fcport->port_type = FCT_UNKNOWN;
2961 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2962 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2963 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2964
bbfbbbc1 2965 return fcport;
1da177e4
LT		 2966}
2967
2968/*
2969 * qla2x00_configure_loop
2970 * Updates Fibre Channel Device Database with what is actually on loop.
2971 *
2972 * Input:
2973 * ha = adapter block pointer.
2974 *
2975 * Returns:
2976 * 0 = success.
2977 * 1 = error.
2978 * 2 = database was full and device was not configured.
2979 */
2980static int
e315cd28 2981qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2982{
2983 int rval;
2984 unsigned long flags, save_flags;
e315cd28 2985 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2986 rval = QLA_SUCCESS;
2987
2988 /* Get Initiator ID */
e315cd28
AC		 2989 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2990 rval = qla2x00_configure_hba(vha);
1da177e4 2991 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2992 ql_dbg(ql_dbg_disc, vha, 0x2013,
2993 "Unable to configure HBA.\n");
1da177e4
LT		 2994 return (rval);
2995 }
2996 }
2997
e315cd28 2998 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2999 ql_dbg(ql_dbg_disc, vha, 0x2014,
3000 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 3001
3002 /*
3003 * If we have both an RSCN and PORT UPDATE pending then handle them
3004 * both at the same time.
3005 */
e315cd28
AC		 3006 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3007 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 3008
3064ff39
MH		 3009 qla2x00_get_data_rate(vha);
3010
1da177e4
LT		 3011 /* Determine what we need to do */
3012 if (ha->current_topology == ISP_CFG_FL &&
3013 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3014
1da177e4
LT		 3015 set_bit(RSCN_UPDATE, &flags);
3016
3017 } else if (ha->current_topology == ISP_CFG_F &&
3018 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3019
1da177e4
LT		 3020 set_bit(RSCN_UPDATE, &flags);
3021 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 3022
3023 } else if (ha->current_topology == ISP_CFG_N) {
3024 clear_bit(RSCN_UPDATE, &flags);
1da177e4 3025
e315cd28 3026 } else if (!vha->flags.online ||
1da177e4
LT		 3027 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
3028
1da177e4
LT		 3029 set_bit(RSCN_UPDATE, &flags);
3030 set_bit(LOCAL_LOOP_UPDATE, &flags);
3031 }
3032
3033 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 3034 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
3035 ql_dbg(ql_dbg_disc, vha, 0x2015,
3036 "Loop resync needed, failing.\n");
1da177e4 3037 rval = QLA_FUNCTION_FAILED;
642ef983 3038 } else
e315cd28 3039 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 3040 }
3041
3042 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 3043 if (LOOP_TRANSITION(vha)) {
3044 ql_dbg(ql_dbg_disc, vha, 0x201e,
3045 "Needs RSCN update and loop transition.\n");
1da177e4 3046 rval = QLA_FUNCTION_FAILED;
7c3df132 3047 }
e315cd28
AC		 3048 else
3049 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 3050 }
3051
3052 if (rval == QLA_SUCCESS) {
e315cd28
AC		 3053 if (atomic_read(&vha->loop_down_timer) ||
3054 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 3055 rval = QLA_FUNCTION_FAILED;
3056 } else {
e315cd28 3057 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 3058 ql_dbg(ql_dbg_disc, vha, 0x2069,
3059 "LOOP READY.\n");
1da177e4
LT		 3060 }
3061 }
3062
3063 if (rval) {
7c3df132
SK		 3064 ql_dbg(ql_dbg_disc, vha, 0x206a,
3065 "%s *** FAILED ***.\n", __func__);
1da177e4 3066 } else {
7c3df132
SK		 3067 ql_dbg(ql_dbg_disc, vha, 0x206b,
3068 "%s: exiting normally.\n", __func__);
1da177e4
LT		 3069 }
3070
cc3ef7bc 3071 /* Restore state if a resync event occurred during processing */
e315cd28 3072 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 3073 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 3074 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 3075 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 3076 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 3077 }
1da177e4
LT		 3078 }
3079
3080 return (rval);
3081}
3082
3083
3084
3085/*
3086 * qla2x00_configure_local_loop
3087 * Updates Fibre Channel Device Database with local loop devices.
3088 *
3089 * Input:
3090 * ha = adapter block pointer.
3091 *
3092 * Returns:
3093 * 0 = success.
3094 */
3095static int
e315cd28 3096qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3097{
3098 int rval, rval2;
3099 int found_devs;
3100 int found;
3101 fc_port_t *fcport, *new_fcport;
3102
3103 uint16_t index;
3104 uint16_t entries;
3105 char *id_iter;
3106 uint16_t loop_id;
3107 uint8_t domain, area, al_pa;
e315cd28 3108 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3109
3110 found_devs = 0;
3111 new_fcport = NULL;
642ef983 3112 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 3113
1da177e4 3114 /* Get list of logged in devices. */
642ef983 3115 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 3116 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 3117 &entries);
3118 if (rval != QLA_SUCCESS)
3119 goto cleanup_allocation;
3120
7c3df132
SK		 3121 ql_dbg(ql_dbg_disc, vha, 0x2017,
3122 "Entries in ID list (%d).\n", entries);
3123 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
3124 (uint8_t *)ha->gid_list,
3125 entries * sizeof(struct gid_list_info));
1da177e4
LT		 3126
3127 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3128 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3129 if (new_fcport == NULL) {
7c3df132
SK		 3130 ql_log(ql_log_warn, vha, 0x2018,
3131 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3132 rval = QLA_MEMORY_ALLOC_FAILED;
3133 goto cleanup_allocation;
3134 }
3135 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3136
3137 /*
3138 * Mark local devices that were present with FCF_DEVICE_LOST for now.
3139 */
e315cd28 3140 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3141 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3142 fcport->port_type != FCT_BROADCAST &&
3143 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3144
7c3df132
SK		 3145 ql_dbg(ql_dbg_disc, vha, 0x2019,
3146 "Marking port lost loop_id=0x%04x.\n",
3147 fcport->loop_id);
1da177e4 3148
ec426e10 3149 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3150 }
3151 }
3152
3153 /* Add devices to port list. */
3154 id_iter = (char *)ha->gid_list;
3155 for (index = 0; index < entries; index++) {
3156 domain = ((struct gid_list_info *)id_iter)->domain;
3157 area = ((struct gid_list_info *)id_iter)->area;
3158 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 3159 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 3160 loop_id = (uint16_t)
3161 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 3162 else
1da177e4
LT		 3163 loop_id = le16_to_cpu(
3164 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 3165 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3166
3167 /* Bypass reserved domain fields. */
3168 if ((domain & 0xf0) == 0xf0)
3169 continue;
3170
3171 /* Bypass if not same domain and area of adapter. */
f7d289f6 3172 if (area && domain &&
e315cd28 3173 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3174 continue;
3175
3176 /* Bypass invalid local loop ID. */
3177 if (loop_id > LAST_LOCAL_LOOP_ID)
3178 continue;
3179
370d550e
AE		 3180 memset(new_fcport, 0, sizeof(fc_port_t));
3181
1da177e4
LT		 3182 /* Fill in member data. */
3183 new_fcport->d_id.b.domain = domain;
3184 new_fcport->d_id.b.area = area;
3185 new_fcport->d_id.b.al_pa = al_pa;
3186 new_fcport->loop_id = loop_id;
e315cd28 3187 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3188 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3189 ql_dbg(ql_dbg_disc, vha, 0x201a,
3190 "Failed to retrieve fcport information "
3191 "-- get_port_database=%x, loop_id=0x%04x.\n",
3192 rval2, new_fcport->loop_id);
3193 ql_dbg(ql_dbg_disc, vha, 0x201b,
3194 "Scheduling resync.\n");
e315cd28 3195 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3196 continue;
3197 }
3198
3199 /* Check for matching device in port list. */
3200 found = 0;
3201 fcport = NULL;
e315cd28 3202 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3203 if (memcmp(new_fcport->port_name, fcport->port_name,
3204 WWN_SIZE))
3205 continue;
3206
ddb9b126 3207 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3208 fcport->loop_id = new_fcport->loop_id;
3209 fcport->port_type = new_fcport->port_type;
3210 fcport->d_id.b24 = new_fcport->d_id.b24;
3211 memcpy(fcport->node_name, new_fcport->node_name,
3212 WWN_SIZE);
3213
3214 found++;
3215 break;
3216 }
3217
3218 if (!found) {
3219 /* New device, add to fcports list. */
e315cd28 3220 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3221
3222 /* Allocate a new replacement fcport. */
3223 fcport = new_fcport;
e315cd28 3224 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3225 if (new_fcport == NULL) {
7c3df132
SK		 3226 ql_log(ql_log_warn, vha, 0x201c,
3227 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3228 rval = QLA_MEMORY_ALLOC_FAILED;
3229 goto cleanup_allocation;
3230 }
3231 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3232 }
3233
d8b45213 3234 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3235 fcport->fp_speed = ha->link_data_rate;
d8b45213 3236
e315cd28 3237 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3238
3239 found_devs++;
3240 }
3241
3242cleanup_allocation:
c9475cb0 3243 kfree(new_fcport);
1da177e4
LT		 3244
3245 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3246 ql_dbg(ql_dbg_disc, vha, 0x201d,
3247 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3248 }
3249
1da177e4
LT		 3250 return (rval);
3251}
3252
d8b45213 3253static void
e315cd28 3254qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3255{
d8b45213 3256 int rval;
93f2bd67 3257 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3258 struct qla_hw_data *ha = vha->hw;
d8b45213 3259
c76f2c01 3260 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3261 return;
3262
c9afb9a2
GM		 3263 if (atomic_read(&fcport->state) != FCS_ONLINE)
3264 return;
3265
39bd9622
AV		 3266 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3267 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3268 return;
3269
e315cd28 3270 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3271 mb);
d8b45213 3272 if (rval != QLA_SUCCESS) {
7c3df132 3273 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3274 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3275 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3276 } else {
7c3df132 3277 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3278 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3279 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3280 fcport->port_name);
d8b45213
AV		 3281 }
3282}
3283
23be331d 3284static void
e315cd28 3285qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 3286{
3287 struct fc_rport_identifiers rport_ids;
bdf79621 3288 struct fc_rport *rport;
044d78e1 3289 unsigned long flags;
8482e118 3290
f8b02a85
AV		 3291 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3292 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 3293 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3294 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3295 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3296 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3297 if (!rport) {
7c3df132
SK		 3298 ql_log(ql_log_warn, vha, 0x2006,
3299 "Unable to allocate fc remote port.\n");
77d74143
AV		 3300 return;
3301 }
2d70c103
NB		 3302 /*
3303 * Create target mode FC NEXUS in qla_target.c if target mode is
3304 * enabled..
3305 */
3306 qlt_fc_port_added(vha, fcport);
3307
044d78e1 3308 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3309 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3310 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3311
ad3e0eda 3312 rport->supported_classes = fcport->supported_classes;
77d74143 3313
8482e118 3314 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3315 if (fcport->port_type == FCT_INITIATOR)
3316 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3317 if (fcport->port_type == FCT_TARGET)
3318 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3319 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3320}
3321
23be331d
AB		 3322/*
3323 * qla2x00_update_fcport
3324 * Updates device on list.
3325 *
3326 * Input:
3327 * ha = adapter block pointer.
3328 * fcport = port structure pointer.
3329 *
3330 * Return:
3331 * 0 - Success
3332 * BIT_0 - error
3333 *
3334 * Context:
3335 * Kernel context.
3336 */
3337void
e315cd28 3338qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3339{
e315cd28 3340 fcport->vha = vha;
8ae6d9c7
GM		 3341
3342 if (IS_QLAFX00(vha->hw)) {
3343 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3344 qla2x00_reg_remote_port(vha, fcport);
3345 return;
3346 }
23be331d 3347 fcport->login_retry = 0;
5ff1d584 3348 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3349
1f93da52 3350 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3351 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3352 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3353 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3354}
3355
1da177e4
LT		 3356/*
3357 * qla2x00_configure_fabric
3358 * Setup SNS devices with loop ID's.
3359 *
3360 * Input:
3361 * ha = adapter block pointer.
3362 *
3363 * Returns:
3364 * 0 = success.
3365 * BIT_0 = error
3366 */
3367static int
e315cd28 3368qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3369{
b3b02e6e 3370 int rval;
e452ceb6 3371 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3372 uint16_t next_loopid;
3373 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3374 uint16_t loop_id;
1da177e4 3375 LIST_HEAD(new_fcports);
e315cd28
AC		 3376 struct qla_hw_data *ha = vha->hw;
3377 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3378
3379 /* If FL port exists, then SNS is present */
e428924c 3380 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3381 loop_id = NPH_F_PORT;
3382 else
3383 loop_id = SNS_FL_PORT;
e315cd28 3384 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3385 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3386 ql_dbg(ql_dbg_disc, vha, 0x201f,
3387 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3388
e315cd28 3389 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3390 return (QLA_SUCCESS);
3391 }
e315cd28 3392 vha->device_flags |= SWITCH_FOUND;
1da177e4 3393
1da177e4 3394 do {
cca5335c
AV		 3395 /* FDMI support. */
3396 if (ql2xfdmienable &&
e315cd28
AC		 3397 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3398 qla2x00_fdmi_register(vha);
cca5335c 3399
1da177e4 3400 /* Ensure we are logged into the SNS. */
e428924c 3401 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3402 loop_id = NPH_SNS;
3403 else
3404 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3405 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3406 0xfc, mb, BIT_1|BIT_0);
3407 if (rval != QLA_SUCCESS) {
3408 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3409 return rval;
0b91d116 3410 }
1da177e4 3411 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3412 ql_dbg(ql_dbg_disc, vha, 0x2042,
3413 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3414 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3415 mb[2], mb[6], mb[7]);
1da177e4
LT		 3416 return (QLA_SUCCESS);
3417 }
3418
e315cd28
AC		 3419 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3420 if (qla2x00_rft_id(vha)) {
1da177e4 3421 /* EMPTY */
7c3df132
SK		 3422 ql_dbg(ql_dbg_disc, vha, 0x2045,
3423 "Register FC-4 TYPE failed.\n");
1da177e4 3424 }
e315cd28 3425 if (qla2x00_rff_id(vha)) {
1da177e4 3426 /* EMPTY */
7c3df132
SK		 3427 ql_dbg(ql_dbg_disc, vha, 0x2049,
3428 "Register FC-4 Features failed.\n");
1da177e4 3429 }
e315cd28 3430 if (qla2x00_rnn_id(vha)) {
1da177e4 3431 /* EMPTY */
7c3df132
SK		 3432 ql_dbg(ql_dbg_disc, vha, 0x204f,
3433 "Register Node Name failed.\n");
e315cd28 3434 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3435 /* EMPTY */
7c3df132
SK		 3436 ql_dbg(ql_dbg_disc, vha, 0x2053,
3437 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3438 }
3439 }
3440
827210ba
JC		 3441#define QLA_FCPORT_SCAN 1
3442#define QLA_FCPORT_FOUND 2
3443
3444 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3445 fcport->scan_state = QLA_FCPORT_SCAN;
3446 }
3447
e315cd28 3448 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3449 if (rval != QLA_SUCCESS)
3450 break;
3451
e452ceb6
JC		 3452 /*
3453 * Logout all previous fabric devices marked lost, except
3454 * FCP2 devices.
3455 */
e315cd28
AC		 3456 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3457 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3458 break;
3459
3460 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3461 continue;
3462
827210ba 3463 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3464 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3465 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3466 ql2xplogiabsentdevice, 0);
1da177e4 3467 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3468 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3469 fcport->port_type != FCT_INITIATOR &&
3470 fcport->port_type != FCT_BROADCAST) {
e315cd28 3471 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3472 fcport->loop_id,
3473 fcport->d_id.b.domain,
3474 fcport->d_id.b.area,
3475 fcport->d_id.b.al_pa);
1a5c69bf 3476 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3477 }
3478 }
e452ceb6 3479 }
1da177e4 3480
e452ceb6
JC		 3481 /* Starting free loop ID. */
3482 next_loopid = ha->min_external_loopid;
3483
3484 /*
3485 * Scan through our port list and login entries that need to be
3486 * logged in.
3487 */
3488 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3489 if (atomic_read(&vha->loop_down_timer) ||
3490 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3491 break;
3492
3493 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3494 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3495 continue;
3496
3497 if (fcport->loop_id == FC_NO_LOOP_ID) {
3498 fcport->loop_id = next_loopid;
3499 rval = qla2x00_find_new_loop_id(
3500 base_vha, fcport);
3501 if (rval != QLA_SUCCESS) {
3502 /* Ran out of IDs to use */
3503 break;
1da177e4
LT		 3504 }
3505 }
e452ceb6
JC		 3506 /* Login and update database */
3507 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3508 }
3509
3510 /* Exit if out of loop IDs. */
3511 if (rval != QLA_SUCCESS) {
3512 break;
3513 }
3514
3515 /*
3516 * Login and add the new devices to our port list.
3517 */
3518 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3519 if (atomic_read(&vha->loop_down_timer) ||
3520 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3521 break;
3522
3523 /* Find a new loop ID to use. */
3524 fcport->loop_id = next_loopid;
3525 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3526 if (rval != QLA_SUCCESS) {
3527 /* Ran out of IDs to use */
3528 break;
3529 }
1da177e4 3530
bdf79621 3531 /* Login and update database */
e315cd28 3532 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3533
3534 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3535 }
3536 } while (0);
3537
e452ceb6
JC		 3538 /* Free all new device structures not processed. */
3539 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3540 list_del(&fcport->list);
3541 kfree(fcport);
3542 }
3543
1da177e4 3544 if (rval) {
7c3df132
SK		 3545 ql_dbg(ql_dbg_disc, vha, 0x2068,
3546 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3547 }
3548
3549 return (rval);
3550}
3551
1da177e4
LT		 3552/*
3553 * qla2x00_find_all_fabric_devs
3554 *
3555 * Input:
3556 * ha = adapter block pointer.
3557 * dev = database device entry pointer.
3558 *
3559 * Returns:
3560 * 0 = success.
3561 *
3562 * Context:
3563 * Kernel context.
3564 */
3565static int
e315cd28
AC		 3566qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3567 struct list_head *new_fcports)
1da177e4
LT		 3568{
3569 int rval;
3570 uint16_t loop_id;
3571 fc_port_t *fcport, *new_fcport, *fcptemp;
3572 int found;
3573
3574 sw_info_t *swl;
3575 int swl_idx;
3576 int first_dev, last_dev;
1516ef44 3577 port_id_t wrap = {}, nxt_d_id;
e315cd28 3578 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3579 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3580
3581 rval = QLA_SUCCESS;
3582
3583 /* Try GID_PT to get device list, else GAN. */
7a67735b 3584 if (!ha->swl)
642ef983 3585 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3586 GFP_KERNEL);
3587 swl = ha->swl;
bbfbbbc1 3588 if (!swl) {
1da177e4 3589 /*EMPTY*/
7c3df132
SK		 3590 ql_dbg(ql_dbg_disc, vha, 0x2054,
3591 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3592 } else {
642ef983 3593 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3594 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3595 swl = NULL;
e315cd28 3596 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3597 swl = NULL;
e315cd28 3598 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3599 swl = NULL;
e5896bd5 3600 } else if (ql2xiidmaenable &&
e315cd28
AC		 3601 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3602 qla2x00_gpsc(vha, swl);
1da177e4 3603 }
e8c72ba5
CD		 3604
3605 /* If other queries succeeded probe for FC-4 type */
3606 if (swl)
3607 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3608 }
3609 swl_idx = 0;
3610
3611 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3612 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3613 if (new_fcport == NULL) {
7c3df132
SK		 3614 ql_log(ql_log_warn, vha, 0x205e,
3615 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3616 return (QLA_MEMORY_ALLOC_FAILED);
3617 }
3618 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3619 /* Set start port ID scan at adapter ID. */
3620 first_dev = 1;
3621 last_dev = 0;
3622
3623 /* Starting free loop ID. */
e315cd28
AC		 3624 loop_id = ha->min_external_loopid;
3625 for (; loop_id <= ha->max_loop_id; loop_id++) {
3626 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3627 continue;
3628
3a6478df
GM		 3629 if (ha->current_topology == ISP_CFG_FL &&
3630 (atomic_read(&vha->loop_down_timer) ||
3631 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3632 atomic_set(&vha->loop_down_timer, 0);
3633 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3634 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3635 break;
bb2d52b2 3636 }
1da177e4
LT		 3637
3638 if (swl != NULL) {
3639 if (last_dev) {
3640 wrap.b24 = new_fcport->d_id.b24;
3641 } else {
3642 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3643 memcpy(new_fcport->node_name,
3644 swl[swl_idx].node_name, WWN_SIZE);
3645 memcpy(new_fcport->port_name,
3646 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3647 memcpy(new_fcport->fabric_port_name,
3648 swl[swl_idx].fabric_port_name, WWN_SIZE);
3649 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3650 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3651
3652 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3653 last_dev = 1;
3654 }
3655 swl_idx++;
3656 }
3657 } else {
3658 /* Send GA_NXT to the switch */
e315cd28 3659 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3660 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3661 ql_log(ql_log_warn, vha, 0x2064,
3662 "SNS scan failed -- assuming "
3663 "zero-entry result.\n");
1da177e4
LT		 3664 list_for_each_entry_safe(fcport, fcptemp,
3665 new_fcports, list) {
3666 list_del(&fcport->list);
3667 kfree(fcport);
3668 }
3669 rval = QLA_SUCCESS;
3670 break;
3671 }
3672 }
3673
3674 /* If wrap on switch device list, exit. */
3675 if (first_dev) {
3676 wrap.b24 = new_fcport->d_id.b24;
3677 first_dev = 0;
3678 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3679 ql_dbg(ql_dbg_disc, vha, 0x2065,
3680 "Device wrap (%02x%02x%02x).\n",
3681 new_fcport->d_id.b.domain,
3682 new_fcport->d_id.b.area,
3683 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3684 break;
3685 }
3686
2c3dfe3f 3687 /* Bypass if same physical adapter. */
e315cd28 3688 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3689 continue;
3690
2c3dfe3f 3691 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3692 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3693 continue;
2c3dfe3f 3694
f7d289f6
AV		 3695 /* Bypass if same domain and area of adapter. */
3696 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3697 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3698 ISP_CFG_FL)
3699 continue;
3700
1da177e4
LT		 3701 /* Bypass reserved domain fields. */
3702 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3703 continue;
3704
e8c72ba5 3705 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3706 if (ql2xgffidenable &&
3707 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3708 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3709 continue;
3710
1da177e4
LT		 3711 /* Locate matching device in database. */
3712 found = 0;
e315cd28 3713 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3714 if (memcmp(new_fcport->port_name, fcport->port_name,
3715 WWN_SIZE))
3716 continue;
3717
827210ba 3718 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3719
1da177e4
LT		 3720 found++;
3721
d8b45213
AV		 3722 /* Update port state. */
3723 memcpy(fcport->fabric_port_name,
3724 new_fcport->fabric_port_name, WWN_SIZE);
3725 fcport->fp_speed = new_fcport->fp_speed;
3726
1da177e4
LT		 3727 /*
3728 * If address the same and state FCS_ONLINE, nothing
3729 * changed.
3730 */
3731 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3732 atomic_read(&fcport->state) == FCS_ONLINE) {
3733 break;
3734 }
3735
3736 /*
3737 * If device was not a fabric device before.
3738 */
3739 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3740 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3741 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3742 fcport->flags |= (FCF_FABRIC_DEVICE |
3743 FCF_LOGIN_NEEDED);
1da177e4
LT		 3744 break;
3745 }
3746
3747 /*
3748 * Port ID changed or device was marked to be updated;
3749 * Log it out if still logged in and mark it for
3750 * relogin later.
3751 */
3752 fcport->d_id.b24 = new_fcport->d_id.b24;
3753 fcport->flags |= FCF_LOGIN_NEEDED;
3754 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3755 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3756 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3757 fcport->port_type != FCT_INITIATOR &&
3758 fcport->port_type != FCT_BROADCAST) {
e315cd28 3759 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3760 fcport->d_id.b.domain, fcport->d_id.b.area,
3761 fcport->d_id.b.al_pa);
5f16b331 3762 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3763 }
3764
3765 break;
3766 }
3767
3768 if (found)
3769 continue;
1da177e4
LT		 3770 /* If device was not in our fcports list, then add it. */
3771 list_add_tail(&new_fcport->list, new_fcports);
3772
3773 /* Allocate a new replacement fcport. */
3774 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3775 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3776 if (new_fcport == NULL) {
7c3df132
SK		 3777 ql_log(ql_log_warn, vha, 0x2066,
3778 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3779 return (QLA_MEMORY_ALLOC_FAILED);
3780 }
3781 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3782 new_fcport->d_id.b24 = nxt_d_id.b24;
3783 }
3784
c9475cb0 3785 kfree(new_fcport);
1da177e4 3786
1da177e4
LT		 3787 return (rval);
3788}
3789
3790/*
3791 * qla2x00_find_new_loop_id
3792 * Scan through our port list and find a new usable loop ID.
3793 *
3794 * Input:
3795 * ha: adapter state pointer.
3796 * dev: port structure pointer.
3797 *
3798 * Returns:
3799 * qla2x00 local function return status code.
3800 *
3801 * Context:
3802 * Kernel context.
3803 */
03bcfb57 3804int
e315cd28 3805qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3806{
3807 int rval;
e315cd28 3808 struct qla_hw_data *ha = vha->hw;
feafb7b1 3809 unsigned long flags = 0;
1da177e4
LT		 3810
3811 rval = QLA_SUCCESS;
3812
5f16b331 3813 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3814
5f16b331
CD		 3815 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3816 LOOPID_MAP_SIZE);
3817 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3818 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3819 dev->loop_id = FC_NO_LOOP_ID;
3820 rval = QLA_FUNCTION_FAILED;
3821 } else
3822 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3823
5f16b331 3824 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3825
5f16b331
CD		 3826 if (rval == QLA_SUCCESS)
3827 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3828 "Assigning new loopid=%x, portid=%x.\n",
3829 dev->loop_id, dev->d_id.b24);
3830 else
3831 ql_log(ql_log_warn, dev->vha, 0x2087,
3832 "No loop_id's available, portid=%x.\n",
3833 dev->d_id.b24);
1da177e4
LT		 3834
3835 return (rval);
3836}
3837
1da177e4
LT		 3838/*
3839 * qla2x00_fabric_dev_login
3840 * Login fabric target device and update FC port database.
3841 *
3842 * Input:
3843 * ha: adapter state pointer.
3844 * fcport: port structure list pointer.
3845 * next_loopid: contains value of a new loop ID that can be used
3846 * by the next login attempt.
3847 *
3848 * Returns:
3849 * qla2x00 local function return status code.
3850 *
3851 * Context:
3852 * Kernel context.
3853 */
3854static int
e315cd28 3855qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3856 uint16_t *next_loopid)
3857{
3858 int rval;
3859 int retry;
0107109e 3860 uint8_t opts;
e315cd28 3861 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3862
3863 rval = QLA_SUCCESS;
3864 retry = 0;
3865
ac280b67 3866 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3867 if (fcport->flags & FCF_ASYNC_SENT)
3868 return rval;
3869 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3870 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3871 if (!rval)
3872 return rval;
3873 }
3874
5ff1d584 3875 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3876 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3877 if (rval == QLA_SUCCESS) {
f08b7251 3878 /* Send an ADISC to FCP2 devices.*/
0107109e 3879 opts = 0;
f08b7251 3880 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3881 opts |= BIT_1;
e315cd28 3882 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3883 if (rval != QLA_SUCCESS) {
e315cd28 3884 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3885 fcport->d_id.b.domain, fcport->d_id.b.area,
3886 fcport->d_id.b.al_pa);
e315cd28 3887 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3888 } else {
e315cd28 3889 qla2x00_update_fcport(vha, fcport);
1da177e4 3890 }
0b91d116
CD		 3891 } else {
3892 /* Retry Login. */
3893 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3894 }
3895
3896 return (rval);
3897}
3898
3899/*
3900 * qla2x00_fabric_login
3901 * Issue fabric login command.
3902 *
3903 * Input:
3904 * ha = adapter block pointer.
3905 * device = pointer to FC device type structure.
3906 *
3907 * Returns:
3908 * 0 - Login successfully
3909 * 1 - Login failed
3910 * 2 - Initiator device
3911 * 3 - Fatal error
3912 */
3913int
e315cd28 3914qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3915 uint16_t *next_loopid)
3916{
3917 int rval;
3918 int retry;
3919 uint16_t tmp_loopid;
3920 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3921 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3922
3923 retry = 0;
3924 tmp_loopid = 0;
3925
3926 for (;;) {
7c3df132
SK		 3927 ql_dbg(ql_dbg_disc, vha, 0x2000,
3928 "Trying Fabric Login w/loop id 0x%04x for port "
3929 "%02x%02x%02x.\n",
3930 fcport->loop_id, fcport->d_id.b.domain,
3931 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3932
3933 /* Login fcport on switch. */
0b91d116 3934 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3935 fcport->d_id.b.domain, fcport->d_id.b.area,
3936 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3937 if (rval != QLA_SUCCESS) {
3938 return rval;
3939 }
1da177e4
LT		 3940 if (mb[0] == MBS_PORT_ID_USED) {
3941 /*
3942 * Device has another loop ID. The firmware team
0107109e
AV		 3943 * recommends the driver perform an implicit login with
3944 * the specified ID again. The ID we just used is save
3945 * here so we return with an ID that can be tried by
3946 * the next login.
1da177e4
LT		 3947 */
3948 retry++;
3949 tmp_loopid = fcport->loop_id;
3950 fcport->loop_id = mb[1];
3951
7c3df132
SK		 3952 ql_dbg(ql_dbg_disc, vha, 0x2001,
3953 "Fabric Login: port in use - next loop "
3954 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3955 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3956 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3957
3958 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3959 /*
3960 * Login succeeded.
3961 */
3962 if (retry) {
3963 /* A retry occurred before. */
3964 *next_loopid = tmp_loopid;
3965 } else {
3966 /*
3967 * No retry occurred before. Just increment the
3968 * ID value for next login.
3969 */
3970 *next_loopid = (fcport->loop_id + 1);
3971 }
3972
3973 if (mb[1] & BIT_0) {
3974 fcport->port_type = FCT_INITIATOR;
3975 } else {
3976 fcport->port_type = FCT_TARGET;
3977 if (mb[1] & BIT_1) {
8474f3a0 3978 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3979 }
3980 }
3981
ad3e0eda
AV		 3982 if (mb[10] & BIT_0)
3983 fcport->supported_classes |= FC_COS_CLASS2;
3984 if (mb[10] & BIT_1)
3985 fcport->supported_classes |= FC_COS_CLASS3;
3986
2d70c103
NB		 3987 if (IS_FWI2_CAPABLE(ha)) {
3988 if (mb[10] & BIT_7)
3989 fcport->flags |=
3990 FCF_CONF_COMP_SUPPORTED;
3991 }
3992
1da177e4
LT		 3993 rval = QLA_SUCCESS;
3994 break;
3995 } else if (mb[0] == MBS_LOOP_ID_USED) {
3996 /*
3997 * Loop ID already used, try next loop ID.
3998 */
3999 fcport->loop_id++;
e315cd28 4000 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 4001 if (rval != QLA_SUCCESS) {
4002 /* Ran out of loop IDs to use */
4003 break;
4004 }
4005 } else if (mb[0] == MBS_COMMAND_ERROR) {
4006 /*
4007 * Firmware possibly timed out during login. If NO
4008 * retries are left to do then the device is declared
4009 * dead.
4010 */
4011 *next_loopid = fcport->loop_id;
e315cd28 4012 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4013 fcport->d_id.b.domain, fcport->d_id.b.area,
4014 fcport->d_id.b.al_pa);
e315cd28 4015 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 4016
4017 rval = 1;
4018 break;
4019 } else {
4020 /*
4021 * unrecoverable / not handled error
4022 */
7c3df132
SK		 4023 ql_dbg(ql_dbg_disc, vha, 0x2002,
4024 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
4025 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
4026 fcport->d_id.b.area, fcport->d_id.b.al_pa,
4027 fcport->loop_id, jiffies);
1da177e4
LT		 4028
4029 *next_loopid = fcport->loop_id;
e315cd28 4030 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4031 fcport->d_id.b.domain, fcport->d_id.b.area,
4032 fcport->d_id.b.al_pa);
5f16b331 4033 qla2x00_clear_loop_id(fcport);
0eedfcf0 4034 fcport->login_retry = 0;
1da177e4
LT		 4035
4036 rval = 3;
4037 break;
4038 }
4039 }
4040
4041 return (rval);
4042}
4043
4044/*
4045 * qla2x00_local_device_login
4046 * Issue local device login command.
4047 *
4048 * Input:
4049 * ha = adapter block pointer.
4050 * loop_id = loop id of device to login to.
4051 *
4052 * Returns (Where's the #define!!!!):
4053 * 0 - Login successfully
4054 * 1 - Login failed
4055 * 3 - Fatal error
4056 */
4057int
e315cd28 4058qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 4059{
4060 int rval;
4061 uint16_t mb[MAILBOX_REGISTER_COUNT];
4062
4063 memset(mb, 0, sizeof(mb));
e315cd28 4064 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 4065 if (rval == QLA_SUCCESS) {
4066 /* Interrogate mailbox registers for any errors */
4067 if (mb[0] == MBS_COMMAND_ERROR)
4068 rval = 1;
4069 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4070 /* device not in PCB table */
4071 rval = 3;
4072 }
4073
4074 return (rval);
4075}
4076
4077/*
4078 * qla2x00_loop_resync
4079 * Resync with fibre channel devices.
4080 *
4081 * Input:
4082 * ha = adapter block pointer.
4083 *
4084 * Returns:
4085 * 0 = success
4086 */
4087int
e315cd28 4088qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 4089{
73208dfd 4090 int rval = QLA_SUCCESS;
1da177e4 4091 uint32_t wait_time;
67c2e93a
AC		 4092 struct req_que *req;
4093 struct rsp_que *rsp;
4094
7163ea81 4095 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 4096 req = vha->hw->req_q_map[0];
4097 else
4098 req = vha->req;
4099 rsp = req->rsp;
1da177e4 4100
e315cd28
AC		 4101 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4102 if (vha->flags.online) {
4103 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 4104 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4105 wait_time = 256;
4106 do {
8ae6d9c7
GM		 4107 if (!IS_QLAFX00(vha->hw)) {
4108 /*
4109 * Issue a marker after FW becomes
4110 * ready.
4111 */
4112 qla2x00_marker(vha, req, rsp, 0, 0,
4113 MK_SYNC_ALL);
4114 vha->marker_needed = 0;
4115 }
1da177e4
LT		 4116
4117 /* Remap devices on Loop. */
e315cd28 4118 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 4119
8ae6d9c7
GM		 4120 if (IS_QLAFX00(vha->hw))
4121 qlafx00_configure_devices(vha);
4122 else
4123 qla2x00_configure_loop(vha);
4124
1da177e4 4125 wait_time--;
e315cd28
AC		 4126 } while (!atomic_read(&vha->loop_down_timer) &&
4127 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4128 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4129 &vha->dpc_flags)));
1da177e4 4130 }
1da177e4
LT		 4131 }
4132
e315cd28 4133 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 4134 return (QLA_FUNCTION_FAILED);
1da177e4 4135
e315cd28 4136 if (rval)
7c3df132
SK		 4137 ql_dbg(ql_dbg_disc, vha, 0x206c,
4138 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 4139
4140 return (rval);
4141}
4142
579d12b5
SK		 4143/*
4144* qla2x00_perform_loop_resync
4145* Description: This function will set the appropriate flags and call
4146* qla2x00_loop_resync. If successful loop will be resynced
4147* Arguments : scsi_qla_host_t pointer
4148* returm : Success or Failure
4149*/
4150
4151int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
4152{
4153 int32_t rval = 0;
4154
4155 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4156 /*Configure the flags so that resync happens properly*/
4157 atomic_set(&ha->loop_down_timer, 0);
4158 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4159 atomic_set(&ha->loop_state, LOOP_UP);
4160 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4161 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4162 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4163
4164 rval = qla2x00_loop_resync(ha);
4165 } else
4166 atomic_set(&ha->loop_state, LOOP_DEAD);
4167
4168 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4169 }
4170
4171 return rval;
4172}
4173
d97994dc 4174void
67becc00 4175qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 4176{
4177 fc_port_t *fcport;
feafb7b1
AE		 4178 struct scsi_qla_host *vha;
4179 struct qla_hw_data *ha = base_vha->hw;
4180 unsigned long flags;
d97994dc 4181
feafb7b1 4182 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4183 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4184 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4185 atomic_inc(&vha->vref_count);
4186 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4187 if (fcport->drport &&
feafb7b1
AE		 4188 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4189 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4190 qla2x00_rport_del(fcport);
feafb7b1
AE		 4191 spin_lock_irqsave(&ha->vport_slock, flags);
4192 }
4193 }
4194 atomic_dec(&vha->vref_count);
4195 }
4196 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 4197}
4198
7d613ac6
SV		 4199/* Assumes idc_lock always held on entry */
4200void
4201qla83xx_reset_ownership(scsi_qla_host_t *vha)
4202{
4203 struct qla_hw_data *ha = vha->hw;
4204 uint32_t drv_presence, drv_presence_mask;
4205 uint32_t dev_part_info1, dev_part_info2, class_type;
4206 uint32_t class_type_mask = 0x3;
4207 uint16_t fcoe_other_function = 0xffff, i;
4208
7ec0effd
AD		 4209 if (IS_QLA8044(ha)) {
4210 drv_presence = qla8044_rd_direct(vha,
4211 QLA8044_CRB_DRV_ACTIVE_INDEX);
4212 dev_part_info1 = qla8044_rd_direct(vha,
4213 QLA8044_CRB_DEV_PART_INFO_INDEX);
4214 dev_part_info2 = qla8044_rd_direct(vha,
4215 QLA8044_CRB_DEV_PART_INFO2);
4216 } else {
4217 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4218 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4219 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4220 }
7d613ac6
SV		 4221 for (i = 0; i < 8; i++) {
4222 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4223 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4224 (i != ha->portnum)) {
4225 fcoe_other_function = i;
4226 break;
4227 }
4228 }
4229 if (fcoe_other_function == 0xffff) {
4230 for (i = 0; i < 8; i++) {
4231 class_type = ((dev_part_info2 >> (i * 4)) &
4232 class_type_mask);
4233 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4234 ((i + 8) != ha->portnum)) {
4235 fcoe_other_function = i + 8;
4236 break;
4237 }
4238 }
4239 }
4240 /*
4241 * Prepare drv-presence mask based on fcoe functions present.
4242 * However consider only valid physical fcoe function numbers (0-15).
4243 */
4244 drv_presence_mask = ~((1 << (ha->portnum)) |
4245 ((fcoe_other_function == 0xffff) ?
4246 0 : (1 << (fcoe_other_function))));
4247
4248 /* We are the reset owner iff:
4249 * - No other protocol drivers present.
4250 * - This is the lowest among fcoe functions. */
4251 if (!(drv_presence & drv_presence_mask) &&
4252 (ha->portnum < fcoe_other_function)) {
4253 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4254 "This host is Reset owner.\n");
4255 ha->flags.nic_core_reset_owner = 1;
4256 }
4257}
4258
fa492630 4259static int
7d613ac6
SV		 4260__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4261{
4262 int rval = QLA_SUCCESS;
4263 struct qla_hw_data *ha = vha->hw;
4264 uint32_t drv_ack;
4265
4266 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4267 if (rval == QLA_SUCCESS) {
4268 drv_ack |= (1 << ha->portnum);
4269 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4270 }
4271
4272 return rval;
4273}
4274
fa492630 4275static int
7d613ac6
SV		 4276__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4277{
4278 int rval = QLA_SUCCESS;
4279 struct qla_hw_data *ha = vha->hw;
4280 uint32_t drv_ack;
4281
4282 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4283 if (rval == QLA_SUCCESS) {
4284 drv_ack &= ~(1 << ha->portnum);
4285 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4286 }
4287
4288 return rval;
4289}
4290
fa492630 4291static const char *
7d613ac6
SV		 4292qla83xx_dev_state_to_string(uint32_t dev_state)
4293{
4294 switch (dev_state) {
4295 case QLA8XXX_DEV_COLD:
4296 return "COLD/RE-INIT";
4297 case QLA8XXX_DEV_INITIALIZING:
4298 return "INITIALIZING";
4299 case QLA8XXX_DEV_READY:
4300 return "READY";
4301 case QLA8XXX_DEV_NEED_RESET:
4302 return "NEED RESET";
4303 case QLA8XXX_DEV_NEED_QUIESCENT:
4304 return "NEED QUIESCENT";
4305 case QLA8XXX_DEV_FAILED:
4306 return "FAILED";
4307 case QLA8XXX_DEV_QUIESCENT:
4308 return "QUIESCENT";
4309 default:
4310 return "Unknown";
4311 }
4312}
4313
4314/* Assumes idc-lock always held on entry */
4315void
4316qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4317{
4318 struct qla_hw_data *ha = vha->hw;
4319 uint32_t idc_audit_reg = 0, duration_secs = 0;
4320
4321 switch (audit_type) {
4322 case IDC_AUDIT_TIMESTAMP:
4323 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4324 idc_audit_reg = (ha->portnum) |
4325 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4326 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4327 break;
4328
4329 case IDC_AUDIT_COMPLETION:
4330 duration_secs = ((jiffies_to_msecs(jiffies) -
4331 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4332 idc_audit_reg = (ha->portnum) |
4333 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4334 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4335 break;
4336
4337 default:
4338 ql_log(ql_log_warn, vha, 0xb078,
4339 "Invalid audit type specified.\n");
4340 break;
4341 }
4342}
4343
4344/* Assumes idc_lock always held on entry */
fa492630 4345static int
7d613ac6
SV		 4346qla83xx_initiating_reset(scsi_qla_host_t *vha)
4347{
4348 struct qla_hw_data *ha = vha->hw;
4349 uint32_t idc_control, dev_state;
4350
4351 __qla83xx_get_idc_control(vha, &idc_control);
4352 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4353 ql_log(ql_log_info, vha, 0xb080,
4354 "NIC Core reset has been disabled. idc-control=0x%x\n",
4355 idc_control);
4356 return QLA_FUNCTION_FAILED;
4357 }
4358
4359 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4360 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4361 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4362 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4363 QLA8XXX_DEV_NEED_RESET);
4364 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4365 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4366 } else {
4367 const char *state = qla83xx_dev_state_to_string(dev_state);
4368 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4369
4370 /* SV: XXX: Is timeout required here? */
4371 /* Wait for IDC state change READY -> NEED_RESET */
4372 while (dev_state == QLA8XXX_DEV_READY) {
4373 qla83xx_idc_unlock(vha, 0);
4374 msleep(200);
4375 qla83xx_idc_lock(vha, 0);
4376 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4377 }
4378 }
4379
4380 /* Send IDC ack by writing to drv-ack register */
4381 __qla83xx_set_drv_ack(vha);
4382
4383 return QLA_SUCCESS;
4384}
4385
4386int
4387__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4388{
4389 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4390}
4391
7d613ac6
SV		 4392int
4393__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4394{
4395 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4396}
4397
fa492630 4398static int
7d613ac6
SV		 4399qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4400{
4401 uint32_t drv_presence = 0;
4402 struct qla_hw_data *ha = vha->hw;
4403
4404 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4405 if (drv_presence & (1 << ha->portnum))
4406 return QLA_SUCCESS;
4407 else
4408 return QLA_TEST_FAILED;
4409}
4410
4411int
4412qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4413{
4414 int rval = QLA_SUCCESS;
4415 struct qla_hw_data *ha = vha->hw;
4416
4417 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4418 "Entered %s().\n", __func__);
4419
4420 if (vha->device_flags & DFLG_DEV_FAILED) {
4421 ql_log(ql_log_warn, vha, 0xb059,
4422 "Device in unrecoverable FAILED state.\n");
4423 return QLA_FUNCTION_FAILED;
4424 }
4425
4426 qla83xx_idc_lock(vha, 0);
4427
4428 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4429 ql_log(ql_log_warn, vha, 0xb05a,
4430 "Function=0x%x has been removed from IDC participation.\n",
4431 ha->portnum);
4432 rval = QLA_FUNCTION_FAILED;
4433 goto exit;
4434 }
4435
4436 qla83xx_reset_ownership(vha);
4437
4438 rval = qla83xx_initiating_reset(vha);
4439
4440 /*
4441 * Perform reset if we are the reset-owner,
4442 * else wait till IDC state changes to READY/FAILED.
4443 */
4444 if (rval == QLA_SUCCESS) {
4445 rval = qla83xx_idc_state_handler(vha);
4446
4447 if (rval == QLA_SUCCESS)
4448 ha->flags.nic_core_hung = 0;
4449 __qla83xx_clear_drv_ack(vha);
4450 }
4451
4452exit:
4453 qla83xx_idc_unlock(vha, 0);
4454
4455 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4456
4457 return rval;
4458}
4459
81178772
SK		 4460int
4461qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4462{
4463 struct qla_hw_data *ha = vha->hw;
4464 int rval = QLA_FUNCTION_FAILED;
4465
4466 if (!IS_MCTP_CAPABLE(ha)) {
4467 /* This message can be removed from the final version */
4468 ql_log(ql_log_info, vha, 0x506d,
4469 "This board is not MCTP capable\n");
4470 return rval;
4471 }
4472
4473 if (!ha->mctp_dump) {
4474 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4475 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4476
4477 if (!ha->mctp_dump) {
4478 ql_log(ql_log_warn, vha, 0x506e,
4479 "Failed to allocate memory for mctp dump\n");
4480 return rval;
4481 }
4482 }
4483
4484#define MCTP_DUMP_STR_ADDR 0x00000000
4485 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4486 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4487 if (rval != QLA_SUCCESS) {
4488 ql_log(ql_log_warn, vha, 0x506f,
4489 "Failed to capture mctp dump\n");
4490 } else {
4491 ql_log(ql_log_info, vha, 0x5070,
4492 "Mctp dump capture for host (%ld/%p).\n",
4493 vha->host_no, ha->mctp_dump);
4494 ha->mctp_dumped = 1;
4495 }
4496
409ee0fe 4497 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4498 ha->flags.nic_core_reset_hdlr_active = 1;
4499 rval = qla83xx_restart_nic_firmware(vha);
4500 if (rval)
4501 /* NIC Core reset failed. */
4502 ql_log(ql_log_warn, vha, 0x5071,
4503 "Failed to restart nic firmware\n");
4504 else
4505 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4506 "Restarted NIC firmware successfully.\n");
4507 ha->flags.nic_core_reset_hdlr_active = 0;
4508 }
4509
4510 return rval;
4511
4512}
4513
579d12b5 4514/*
8fcd6b8b 4515* qla2x00_quiesce_io
579d12b5
SK		 4516* Description: This function will block the new I/Os
4517* Its not aborting any I/Os as context
4518* is not destroyed during quiescence
4519* Arguments: scsi_qla_host_t
4520* return : void
4521*/
4522void
8fcd6b8b 4523qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4524{
4525 struct qla_hw_data *ha = vha->hw;
4526 struct scsi_qla_host *vp;
4527
8fcd6b8b
CD		 4528 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4529 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4530
4531 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4532 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4533 atomic_set(&vha->loop_state, LOOP_DOWN);
4534 qla2x00_mark_all_devices_lost(vha, 0);
4535 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4536 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4537 } else {
4538 if (!atomic_read(&vha->loop_down_timer))
4539 atomic_set(&vha->loop_down_timer,
4540 LOOP_DOWN_TIME);
4541 }
4542 /* Wait for pending cmds to complete */
4543 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4544}
4545
a9083016
GM		 4546void
4547qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4548{
4549 struct qla_hw_data *ha = vha->hw;
579d12b5 4550 struct scsi_qla_host *vp;
feafb7b1 4551 unsigned long flags;
6aef87be 4552 fc_port_t *fcport;
a9083016 4553
e46ef004
SK		 4554 /* For ISP82XX, driver waits for completion of the commands.
4555 * online flag should be set.
4556 */
7ec0effd 4557 if (!(IS_P3P_TYPE(ha)))
e46ef004 4558 vha->flags.online = 0;
a9083016
GM		 4559 ha->flags.chip_reset_done = 0;
4560 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4561 vha->qla_stats.total_isp_aborts++;
a9083016 4562
7c3df132
SK		 4563 ql_log(ql_log_info, vha, 0x00af,
4564 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4565
e46ef004
SK		 4566 /* For ISP82XX, reset_chip is just disabling interrupts.
4567 * Driver waits for the completion of the commands.
4568 * the interrupts need to be enabled.
4569 */
7ec0effd 4570 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4571 ha->isp_ops->reset_chip(vha);
4572
4573 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4574 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4575 atomic_set(&vha->loop_state, LOOP_DOWN);
4576 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4577
4578 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4579 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4580 atomic_inc(&vp->vref_count);
4581 spin_unlock_irqrestore(&ha->vport_slock, flags);
4582
a9083016 4583 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4584
4585 spin_lock_irqsave(&ha->vport_slock, flags);
4586 atomic_dec(&vp->vref_count);
4587 }
4588 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4589 } else {
4590 if (!atomic_read(&vha->loop_down_timer))
4591 atomic_set(&vha->loop_down_timer,
4592 LOOP_DOWN_TIME);
4593 }
4594
6aef87be
AV		 4595 /* Clear all async request states across all VPs. */
4596 list_for_each_entry(fcport, &vha->vp_fcports, list)
4597 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4598 spin_lock_irqsave(&ha->vport_slock, flags);
4599 list_for_each_entry(vp, &ha->vp_list, list) {
4600 atomic_inc(&vp->vref_count);
4601 spin_unlock_irqrestore(&ha->vport_slock, flags);
4602
4603 list_for_each_entry(fcport, &vp->vp_fcports, list)
4604 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4605
4606 spin_lock_irqsave(&ha->vport_slock, flags);
4607 atomic_dec(&vp->vref_count);
4608 }
4609 spin_unlock_irqrestore(&ha->vport_slock, flags);
4610
bddd2d65
LC		 4611 if (!ha->flags.eeh_busy) {
4612 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4613 if (IS_P3P_TYPE(ha)) {
7190575f 4614 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4615 ql_log(ql_log_info, vha, 0x00b4,
4616 "Done chip reset cleanup.\n");
a9083016 4617
e46ef004
SK		 4618 /* Done waiting for pending commands.
4619 * Reset the online flag.
4620 */
4621 vha->flags.online = 0;
4d78c973 4622 }
a9083016 4623
bddd2d65
LC		 4624 /* Requeue all commands in outstanding command list. */
4625 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4626 }
b6a029e1
AE		 4627
4628 ha->chip_reset++;
4629 /* memory barrier */
4630 wmb();
a9083016
GM		 4631}
4632
1da177e4
LT		 4633/*
4634* qla2x00_abort_isp
4635* Resets ISP and aborts all outstanding commands.
4636*
4637* Input:
4638* ha = adapter block pointer.
4639*
4640* Returns:
4641* 0 = success
4642*/
4643int
e315cd28 4644qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4645{
476e8978 4646 int rval;
1da177e4 4647 uint8_t status = 0;
e315cd28
AC		 4648 struct qla_hw_data *ha = vha->hw;
4649 struct scsi_qla_host *vp;
73208dfd 4650 struct req_que *req = ha->req_q_map[0];
feafb7b1 4651 unsigned long flags;
1da177e4 4652
e315cd28 4653 if (vha->flags.online) {
a9083016 4654 qla2x00_abort_isp_cleanup(vha);
1da177e4 4655
a6171297
SV		 4656 if (IS_QLA8031(ha)) {
4657 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4658 "Clearing fcoe driver presence.\n");
4659 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4660 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4661 "Error while clearing DRV-Presence.\n");
4662 }
4663
85880801
AV		 4664 if (unlikely(pci_channel_offline(ha->pdev) &&
4665 ha->flags.pci_channel_io_perm_failure)) {
4666 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4667 status = 0;
4668 return status;
4669 }
4670
73208dfd 4671 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4672
e315cd28 4673 ha->isp_ops->nvram_config(vha);
1da177e4 4674
e315cd28
AC		 4675 if (!qla2x00_restart_isp(vha)) {
4676 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4677
e315cd28 4678 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4679 /*
4680 * Issue marker command only when we are going
4681 * to start the I/O .
4682 */
e315cd28 4683 vha->marker_needed = 1;
1da177e4
LT		 4684 }
4685
e315cd28 4686 vha->flags.online = 1;
1da177e4 4687
fd34f556 4688 ha->isp_ops->enable_intrs(ha);
1da177e4 4689
fa2a1ce5 4690 ha->isp_abort_cnt = 0;
e315cd28 4691 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4692
6246b8a1
GM		 4693 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4694 qla2x00_get_fw_version(vha);
df613b96
AV		 4695 if (ha->fce) {
4696 ha->flags.fce_enabled = 1;
4697 memset(ha->fce, 0,
4698 fce_calc_size(ha->fce_bufs));
e315cd28 4699 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4700 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4701 &ha->fce_bufs);
4702 if (rval) {
7c3df132 4703 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4704 "Unable to reinitialize FCE "
4705 "(%d).\n", rval);
4706 ha->flags.fce_enabled = 0;
4707 }
4708 }
436a7b11
AV		 4709
4710 if (ha->eft) {
4711 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4712 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4713 ha->eft_dma, EFT_NUM_BUFFERS);
4714 if (rval) {
7c3df132 4715 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4716 "Unable to reinitialize EFT "
4717 "(%d).\n", rval);
4718 }
4719 }
1da177e4 4720 } else { /* failed the ISP abort */
e315cd28
AC		 4721 vha->flags.online = 1;
4722 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4723 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4724 ql_log(ql_log_fatal, vha, 0x8035,
4725 "ISP error recover failed - "
4726 "board disabled.\n");
fa2a1ce5 4727 /*
1da177e4
LT		 4728 * The next call disables the board
4729 * completely.
4730 */
e315cd28
AC		 4731 ha->isp_ops->reset_adapter(vha);
4732 vha->flags.online = 0;
1da177e4 4733 clear_bit(ISP_ABORT_RETRY,
e315cd28 4734 &vha->dpc_flags);
1da177e4
LT		 4735 status = 0;
4736 } else { /* schedule another ISP abort */
4737 ha->isp_abort_cnt--;
7c3df132
SK		 4738 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4739 "ISP abort - retry remaining %d.\n",
4740 ha->isp_abort_cnt);
1da177e4
LT		 4741 status = 1;
4742 }
4743 } else {
4744 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4745 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4746 "ISP error recovery - retrying (%d) "
4747 "more times.\n", ha->isp_abort_cnt);
e315cd28 4748 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4749 status = 1;
4750 }
4751 }
fa2a1ce5 4752
1da177e4
LT		 4753 }
4754
e315cd28 4755 if (!status) {
7c3df132 4756 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4757
4758 spin_lock_irqsave(&ha->vport_slock, flags);
4759 list_for_each_entry(vp, &ha->vp_list, list) {
4760 if (vp->vp_idx) {
4761 atomic_inc(&vp->vref_count);
4762 spin_unlock_irqrestore(&ha->vport_slock, flags);
4763
e315cd28 4764 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4765
4766 spin_lock_irqsave(&ha->vport_slock, flags);
4767 atomic_dec(&vp->vref_count);
4768 }
e315cd28 4769 }
feafb7b1
AE		 4770 spin_unlock_irqrestore(&ha->vport_slock, flags);
4771
7d613ac6
SV		 4772 if (IS_QLA8031(ha)) {
4773 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4774 "Setting back fcoe driver presence.\n");
4775 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4776 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4777 "Error while setting DRV-Presence.\n");
4778 }
e315cd28 4779 } else {
d8424f68
JP		 4780 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4781 __func__);
1da177e4
LT		 4782 }
4783
4784 return(status);
4785}
4786
4787/*
4788* qla2x00_restart_isp
4789* restarts the ISP after a reset
4790*
4791* Input:
4792* ha = adapter block pointer.
4793*
4794* Returns:
4795* 0 = success
4796*/
4797static int
e315cd28 4798qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4799{
c6b2fca8 4800 int status = 0;
e315cd28 4801 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4802 struct req_que *req = ha->req_q_map[0];
4803 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4804 unsigned long flags;
1da177e4
LT		 4805
4806 /* If firmware needs to be loaded */
e315cd28
AC		 4807 if (qla2x00_isp_firmware(vha)) {
4808 vha->flags.online = 0;
4809 status = ha->isp_ops->chip_diag(vha);
4810 if (!status)
4811 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4812 }
4813
e315cd28
AC		 4814 if (!status && !(status = qla2x00_init_rings(vha))) {
4815 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4816 ha->flags.chip_reset_done = 1;
7108b76e 4817
73208dfd
AC		 4818 /* Initialize the queues in use */
4819 qla25xx_init_queues(ha);
4820
e315cd28
AC		 4821 status = qla2x00_fw_ready(vha);
4822 if (!status) {
0107109e 4823 /* Issue a marker after FW becomes ready. */
73208dfd 4824 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4825
e315cd28 4826 vha->flags.online = 1;
2d70c103
NB		 4827
4828 /*
4829 * Process any ATIO queue entries that came in
4830 * while we weren't online.
4831 */
4832 spin_lock_irqsave(&ha->hardware_lock, flags);
4833 if (qla_tgt_mode_enabled(vha))
4834 qlt_24xx_process_atio_queue(vha);
4835 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4836
7108b76e 4837 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4838 }
4839
4840 /* if no cable then assume it's good */
e315cd28 4841 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 4842 status = 0;
1da177e4
LT		 4843 }
4844 return (status);
4845}
4846
73208dfd
AC		 4847static int
4848qla25xx_init_queues(struct qla_hw_data *ha)
4849{
4850 struct rsp_que *rsp = NULL;
4851 struct req_que *req = NULL;
4852 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4853 int ret = -1;
4854 int i;
4855
2afa19a9 4856 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4857 rsp = ha->rsp_q_map[i];
4858 if (rsp) {
4859 rsp->options &= ~BIT_0;
618a7523 4860 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4861 if (ret != QLA_SUCCESS)
7c3df132
SK		 4862 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4863 "%s Rsp que: %d init failed.\n",
4864 __func__, rsp->id);
73208dfd 4865 else
7c3df132
SK		 4866 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4867 "%s Rsp que: %d inited.\n",
4868 __func__, rsp->id);
73208dfd 4869 }
2afa19a9
AC		 4870 }
4871 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4872 req = ha->req_q_map[i];
4873 if (req) {
29bdccbe 4874 /* Clear outstanding commands array. */
73208dfd 4875 req->options &= ~BIT_0;
618a7523 4876 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4877 if (ret != QLA_SUCCESS)
7c3df132
SK		 4878 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4879 "%s Req que: %d init failed.\n",
4880 __func__, req->id);
73208dfd 4881 else
7c3df132
SK		 4882 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4883 "%s Req que: %d inited.\n",
4884 __func__, req->id);
73208dfd
AC		 4885 }
4886 }
4887 return ret;
4888}
4889
1da177e4
LT		 4890/*
4891* qla2x00_reset_adapter
4892* Reset adapter.
4893*
4894* Input:
4895* ha = adapter block pointer.
4896*/
abbd8870 4897void
e315cd28 4898qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4899{
4900 unsigned long flags = 0;
e315cd28 4901 struct qla_hw_data *ha = vha->hw;
3d71644c 4902 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4903
e315cd28 4904 vha->flags.online = 0;
fd34f556 4905 ha->isp_ops->disable_intrs(ha);
1da177e4 4906
1da177e4
LT		 4907 spin_lock_irqsave(&ha->hardware_lock, flags);
4908 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4909 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4910 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4911 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4912 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4913}
0107109e
AV		 4914
4915void
e315cd28 4916qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4917{
4918 unsigned long flags = 0;
e315cd28 4919 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4920 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4921
7ec0effd 4922 if (IS_P3P_TYPE(ha))
a9083016
GM		 4923 return;
4924
e315cd28 4925 vha->flags.online = 0;
fd34f556 4926 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4927
4928 spin_lock_irqsave(&ha->hardware_lock, flags);
4929 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4930 RD_REG_DWORD(&reg->hccr);
4931 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4932 RD_REG_DWORD(&reg->hccr);
4933 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4934
4935 if (IS_NOPOLLING_TYPE(ha))
4936 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4937}
4938
4e08df3f
DM		 4939/* On sparc systems, obtain port and node WWN from firmware
4940 * properties.
4941 */
e315cd28
AC		 4942static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4943 struct nvram_24xx *nv)
4e08df3f
DM		 4944{
4945#ifdef CONFIG_SPARC
e315cd28 4946 struct qla_hw_data *ha = vha->hw;
4e08df3f 4947 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4948 struct device_node *dp = pci_device_to_OF_node(pdev);
4949 const u8 *val;
4e08df3f
DM		 4950 int len;
4951
4952 val = of_get_property(dp, "port-wwn", &len);
4953 if (val && len >= WWN_SIZE)
4954 memcpy(nv->port_name, val, WWN_SIZE);
4955
4956 val = of_get_property(dp, "node-wwn", &len);
4957 if (val && len >= WWN_SIZE)
4958 memcpy(nv->node_name, val, WWN_SIZE);
4959#endif
4960}
4961
0107109e 4962int
e315cd28 4963qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4964{
4e08df3f 4965 int rval;
0107109e
AV		 4966 struct init_cb_24xx *icb;
4967 struct nvram_24xx *nv;
4968 uint32_t *dptr;
4969 uint8_t *dptr1, *dptr2;
4970 uint32_t chksum;
4971 uint16_t cnt;
e315cd28 4972 struct qla_hw_data *ha = vha->hw;
0107109e 4973
4e08df3f 4974 rval = QLA_SUCCESS;
0107109e 4975 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4976 nv = ha->nvram;
0107109e
AV		 4977
4978 /* Determine NVRAM starting address. */
f73cb695 4979 if (ha->port_no == 0) {
e5b68a61
AC		 4980 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4981 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4982 } else {
0107109e 4983 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 4984 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4985 }
f73cb695 4986
e5b68a61
AC		 4987 ha->nvram_size = sizeof(struct nvram_24xx);
4988 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4989
281afe19
SJ		 4990 /* Get VPD data into cache */
4991 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4992 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4993 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4994
4995 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4996 dptr = (uint32_t *)nv;
e315cd28 4997 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4998 ha->nvram_size);
4999 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5000 chksum += le32_to_cpu(*dptr++);
5001
7c3df132
SK		 5002 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
5003 "Contents of NVRAM\n");
5004 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
5005 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 5006
5007 /* Bad NVRAM data, set defaults parameters. */
5008 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5009 || nv->id[3] != ' ' ||
5010 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5011 /* Reset NVRAM data. */
7c3df132 5012 ql_log(ql_log_warn, vha, 0x006b,
9e336520 5013 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 5014 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
5015 ql_log(ql_log_warn, vha, 0x006c,
5016 "Falling back to functioning (yet invalid -- WWPN) "
5017 "defaults.\n");
4e08df3f
DM		 5018
5019 /*
5020 * Set default initialization control block.
5021 */
5022 memset(nv, 0, ha->nvram_size);
5023 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5024 nv->version = __constant_cpu_to_le16(ICB_VERSION);
98aee70d 5025 nv->frame_payload_size = 2048;
4e08df3f
DM		 5026 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5027 nv->exchange_count = __constant_cpu_to_le16(0);
5028 nv->hard_address = __constant_cpu_to_le16(124);
5029 nv->port_name[0] = 0x21;
f73cb695 5030 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 5031 nv->port_name[2] = 0x00;
5032 nv->port_name[3] = 0xe0;
5033 nv->port_name[4] = 0x8b;
5034 nv->port_name[5] = 0x1c;
5035 nv->port_name[6] = 0x55;
5036 nv->port_name[7] = 0x86;
5037 nv->node_name[0] = 0x20;
5038 nv->node_name[1] = 0x00;
5039 nv->node_name[2] = 0x00;
5040 nv->node_name[3] = 0xe0;
5041 nv->node_name[4] = 0x8b;
5042 nv->node_name[5] = 0x1c;
5043 nv->node_name[6] = 0x55;
5044 nv->node_name[7] = 0x86;
e315cd28 5045 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 5046 nv->login_retry_count = __constant_cpu_to_le16(8);
5047 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5048 nv->login_timeout = __constant_cpu_to_le16(0);
5049 nv->firmware_options_1 =
5050 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5051 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5052 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5053 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5054 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5055 nv->efi_parameters = __constant_cpu_to_le32(0);
5056 nv->reset_delay = 5;
5057 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5058 nv->port_down_retry_count = __constant_cpu_to_le16(30);
5059 nv->link_down_timeout = __constant_cpu_to_le16(30);
5060
5061 rval = 1;
0107109e
AV		 5062 }
5063
2d70c103
NB		 5064 if (!qla_ini_mode_enabled(vha)) {
5065 /* Don't enable full login after initial LIP */
5066 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
5067 /* Don't enable LIP full login for initiator */
5068 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
5069 }
5070
5071 qlt_24xx_config_nvram_stage1(vha, nv);
5072
0107109e 5073 /* Reset Initialization control block */
e315cd28 5074 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5075
5076 /* Copy 1st segment. */
5077 dptr1 = (uint8_t *)icb;
5078 dptr2 = (uint8_t *)&nv->version;
5079 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5080 while (cnt--)
5081 *dptr1++ = *dptr2++;
5082
5083 icb->login_retry_count = nv->login_retry_count;
3ea66e28 5084 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 5085
5086 /* Copy 2nd segment. */
5087 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5088 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5089 cnt = (uint8_t *)&icb->reserved_3 -
5090 (uint8_t *)&icb->interrupt_delay_timer;
5091 while (cnt--)
5092 *dptr1++ = *dptr2++;
5093
5094 /*
5095 * Setup driver NVRAM options.
5096 */
e315cd28 5097 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 5098 "QLA2462");
0107109e 5099
2d70c103
NB		 5100 qlt_24xx_config_nvram_stage2(vha, icb);
5101
5341e868 5102 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 5103 /* Use alternate WWN? */
5341e868
AV		 5104 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5105 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5106 }
5107
0107109e 5108 /* Prepare nodename */
fd0e7e4d 5109 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 5110 /*
5111 * Firmware will apply the following mask if the nodename was
5112 * not provided.
5113 */
5114 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5115 icb->node_name[0] &= 0xF0;
5116 }
5117
5118 /* Set host adapter parameters. */
5119 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 5120 ha->flags.enable_lip_reset = 0;
5121 ha->flags.enable_lip_full_login =
5122 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5123 ha->flags.enable_target_reset =
5124 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 5125 ha->flags.enable_led_scheme = 0;
d4c760c2 5126 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 5127
fd0e7e4d
AV		 5128 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5129 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 5130
5131 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
5132 sizeof(ha->fw_seriallink_options24));
5133
5134 /* save HBA serial number */
5135 ha->serial0 = icb->port_name[5];
5136 ha->serial1 = icb->port_name[6];
5137 ha->serial2 = icb->port_name[7];
e315cd28
AC		 5138 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5139 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 5140
bc8fb3cb 5141 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5142
0107109e
AV		 5143 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5144
5145 /* Set minimum login_timeout to 4 seconds. */
5146 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5147 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5148 if (le16_to_cpu(nv->login_timeout) < 4)
5149 nv->login_timeout = __constant_cpu_to_le16(4);
5150 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 5151 icb->login_timeout = nv->login_timeout;
0107109e 5152
00a537b8
AV		 5153 /* Set minimum RATOV to 100 tenths of a second. */
5154 ha->r_a_tov = 100;
0107109e
AV		 5155
5156 ha->loop_reset_delay = nv->reset_delay;
5157
5158 /* Link Down Timeout = 0:
5159 *
5160 * When Port Down timer expires we will start returning
5161 * I/O's to OS with "DID_NO_CONNECT".
5162 *
5163 * Link Down Timeout != 0:
5164 *
5165 * The driver waits for the link to come up after link down
5166 * before returning I/Os to OS with "DID_NO_CONNECT".
5167 */
5168 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5169 ha->loop_down_abort_time =
5170 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5171 } else {
5172 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5173 ha->loop_down_abort_time =
5174 (LOOP_DOWN_TIME - ha->link_down_timeout);
5175 }
5176
5177 /* Need enough time to try and get the port back. */
5178 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5179 if (qlport_down_retry)
5180 ha->port_down_retry_count = qlport_down_retry;
5181
5182 /* Set login_retry_count */
5183 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5184 if (ha->port_down_retry_count ==
5185 le16_to_cpu(nv->port_down_retry_count) &&
5186 ha->port_down_retry_count > 3)
5187 ha->login_retry_count = ha->port_down_retry_count;
5188 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5189 ha->login_retry_count = ha->port_down_retry_count;
5190 if (ql2xloginretrycount)
5191 ha->login_retry_count = ql2xloginretrycount;
5192
4fdfefe5 5193 /* Enable ZIO. */
e315cd28 5194 if (!vha->flags.init_done) {
4fdfefe5
AV		 5195 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5196 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5197 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5198 le16_to_cpu(icb->interrupt_delay_timer): 2;
5199 }
5200 icb->firmware_options_2 &= __constant_cpu_to_le32(
5201 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5202 vha->flags.process_response_queue = 0;
4fdfefe5 5203 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 5204 ha->zio_mode = QLA_ZIO_MODE_6;
5205
7c3df132 5206 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5207 "ZIO mode %d enabled; timer delay (%d us).\n",
5208 ha->zio_mode, ha->zio_timer * 100);
5209
5210 icb->firmware_options_2 |= cpu_to_le32(
5211 (uint32_t)ha->zio_mode);
5212 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5213 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5214 }
5215
4e08df3f 5216 if (rval) {
7c3df132
SK		 5217 ql_log(ql_log_warn, vha, 0x0070,
5218 "NVRAM configuration failed.\n");
4e08df3f
DM		 5219 }
5220 return (rval);
0107109e
AV		 5221}
5222
413975a0 5223static int
cbc8eb67
AV		 5224qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5225 uint32_t faddr)
d1c61909 5226{
73208dfd 5227 int rval = QLA_SUCCESS;
d1c61909 5228 int segments, fragment;
d1c61909
AV		 5229 uint32_t *dcode, dlen;
5230 uint32_t risc_addr;
5231 uint32_t risc_size;
5232 uint32_t i;
e315cd28 5233 struct qla_hw_data *ha = vha->hw;
73208dfd 5234 struct req_que *req = ha->req_q_map[0];
eaac30be 5235
7c3df132 5236 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5237 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5238
d1c61909
AV		 5239 rval = QLA_SUCCESS;
5240
5241 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5242 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5243 *srisc_addr = 0;
5244
5245 /* Validate firmware image by checking version. */
e315cd28 5246 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5247 for (i = 0; i < 4; i++)
5248 dcode[i] = be32_to_cpu(dcode[i]);
5249 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5250 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5251 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5252 dcode[3] == 0)) {
7c3df132
SK		 5253 ql_log(ql_log_fatal, vha, 0x008c,
5254 "Unable to verify the integrity of flash firmware "
5255 "image.\n");
5256 ql_log(ql_log_fatal, vha, 0x008d,
5257 "Firmware data: %08x %08x %08x %08x.\n",
5258 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5259
5260 return QLA_FUNCTION_FAILED;
5261 }
5262
5263 while (segments && rval == QLA_SUCCESS) {
5264 /* Read segment's load information. */
e315cd28 5265 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5266
5267 risc_addr = be32_to_cpu(dcode[2]);
5268 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5269 risc_size = be32_to_cpu(dcode[3]);
5270
5271 fragment = 0;
5272 while (risc_size > 0 && rval == QLA_SUCCESS) {
5273 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5274 if (dlen > risc_size)
5275 dlen = risc_size;
5276
7c3df132
SK		 5277 ql_dbg(ql_dbg_init, vha, 0x008e,
5278 "Loading risc segment@ risc addr %x "
5279 "number of dwords 0x%x offset 0x%x.\n",
5280 risc_addr, dlen, faddr);
d1c61909 5281
e315cd28 5282 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5283 for (i = 0; i < dlen; i++)
5284 dcode[i] = swab32(dcode[i]);
5285
73208dfd 5286 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5287 dlen);
5288 if (rval) {
7c3df132
SK		 5289 ql_log(ql_log_fatal, vha, 0x008f,
5290 "Failed to load segment %d of firmware.\n",
5291 fragment);
f261f7af 5292 return QLA_FUNCTION_FAILED;
d1c61909
AV		 5293 }
5294
5295 faddr += dlen;
5296 risc_addr += dlen;
5297 risc_size -= dlen;
5298 fragment++;
5299 }
5300
5301 /* Next segment. */
5302 segments--;
5303 }
5304
f73cb695
CD		 5305 if (!IS_QLA27XX(ha))
5306 return rval;
5307
5308 if (ha->fw_dump_template)
5309 vfree(ha->fw_dump_template);
5310 ha->fw_dump_template = NULL;
5311 ha->fw_dump_template_len = 0;
5312
5313 ql_dbg(ql_dbg_init, vha, 0x0161,
5314 "Loading fwdump template from %x\n", faddr);
5315 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5316 risc_size = be32_to_cpu(dcode[2]);
5317 ql_dbg(ql_dbg_init, vha, 0x0162,
5318 "-> array size %x dwords\n", risc_size);
5319 if (risc_size == 0 || risc_size == ~0)
5320 goto default_template;
5321
5322 dlen = (risc_size - 8) * sizeof(*dcode);
5323 ql_dbg(ql_dbg_init, vha, 0x0163,
5324 "-> template allocating %x bytes...\n", dlen);
5325 ha->fw_dump_template = vmalloc(dlen);
5326 if (!ha->fw_dump_template) {
5327 ql_log(ql_log_warn, vha, 0x0164,
5328 "Failed fwdump template allocate %x bytes.\n", risc_size);
5329 goto default_template;
5330 }
5331
5332 faddr += 7;
5333 risc_size -= 8;
5334 dcode = ha->fw_dump_template;
5335 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5336 for (i = 0; i < risc_size; i++)
5337 dcode[i] = le32_to_cpu(dcode[i]);
5338
5339 if (!qla27xx_fwdt_template_valid(dcode)) {
5340 ql_log(ql_log_warn, vha, 0x0165,
5341 "Failed fwdump template validate\n");
5342 goto default_template;
5343 }
5344
5345 dlen = qla27xx_fwdt_template_size(dcode);
5346 ql_dbg(ql_dbg_init, vha, 0x0166,
5347 "-> template size %x bytes\n", dlen);
5348 if (dlen > risc_size * sizeof(*dcode)) {
5349 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 5350 "Failed fwdump template exceeds array by %x bytes\n",
5351 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 5352 goto default_template;
5353 }
5354 ha->fw_dump_template_len = dlen;
5355 return rval;
5356
5357default_template:
5358 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5359 if (ha->fw_dump_template)
5360 vfree(ha->fw_dump_template);
5361 ha->fw_dump_template = NULL;
5362 ha->fw_dump_template_len = 0;
5363
5364 dlen = qla27xx_fwdt_template_default_size();
5365 ql_dbg(ql_dbg_init, vha, 0x0169,
5366 "-> template allocating %x bytes...\n", dlen);
5367 ha->fw_dump_template = vmalloc(dlen);
5368 if (!ha->fw_dump_template) {
5369 ql_log(ql_log_warn, vha, 0x016a,
5370 "Failed fwdump template allocate %x bytes.\n", risc_size);
5371 goto failed_template;
5372 }
5373
5374 dcode = ha->fw_dump_template;
5375 risc_size = dlen / sizeof(*dcode);
5376 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5377 for (i = 0; i < risc_size; i++)
5378 dcode[i] = be32_to_cpu(dcode[i]);
5379
5380 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5381 ql_log(ql_log_warn, vha, 0x016b,
5382 "Failed fwdump template validate\n");
5383 goto failed_template;
5384 }
5385
5386 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5387 ql_dbg(ql_dbg_init, vha, 0x016c,
5388 "-> template size %x bytes\n", dlen);
5389 ha->fw_dump_template_len = dlen;
5390 return rval;
5391
5392failed_template:
5393 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5394 if (ha->fw_dump_template)
5395 vfree(ha->fw_dump_template);
5396 ha->fw_dump_template = NULL;
5397 ha->fw_dump_template_len = 0;
d1c61909
AV		 5398 return rval;
5399}
5400
e9454a88 5401#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5402
0107109e 5403int
e315cd28 5404qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5405{
5406 int rval;
5407 int i, fragment;
5408 uint16_t *wcode, *fwcode;
5409 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5410 struct fw_blob *blob;
e315cd28 5411 struct qla_hw_data *ha = vha->hw;
73208dfd 5412 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5413
5414 /* Load firmware blob. */
e315cd28 5415 blob = qla2x00_request_firmware(vha);
5433383e 5416 if (!blob) {
7c3df132 5417 ql_log(ql_log_info, vha, 0x0083,
94bcf830 5418 "Firmware image unavailable.\n");
7c3df132
SK		 5419 ql_log(ql_log_info, vha, 0x0084,
5420 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5421 return QLA_FUNCTION_FAILED;
5422 }
5423
5424 rval = QLA_SUCCESS;
5425
73208dfd 5426 wcode = (uint16_t *)req->ring;
5433383e
AV		 5427 *srisc_addr = 0;
5428 fwcode = (uint16_t *)blob->fw->data;
5429 fwclen = 0;
5430
5431 /* Validate firmware image by checking version. */
5432 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5433 ql_log(ql_log_fatal, vha, 0x0085,
5434 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5435 blob->fw->size);
5436 goto fail_fw_integrity;
5437 }
5438 for (i = 0; i < 4; i++)
5439 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5440 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5441 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5442 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5443 ql_log(ql_log_fatal, vha, 0x0086,
5444 "Unable to verify integrity of firmware image.\n");
5445 ql_log(ql_log_fatal, vha, 0x0087,
5446 "Firmware data: %04x %04x %04x %04x.\n",
5447 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5448 goto fail_fw_integrity;
5449 }
5450
5451 seg = blob->segs;
5452 while (*seg && rval == QLA_SUCCESS) {
5453 risc_addr = *seg;
5454 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5455 risc_size = be16_to_cpu(fwcode[3]);
5456
5457 /* Validate firmware image size. */
5458 fwclen += risc_size * sizeof(uint16_t);
5459 if (blob->fw->size < fwclen) {
7c3df132 5460 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5461 "Unable to verify integrity of firmware image "
7c3df132 5462 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5463 goto fail_fw_integrity;
5464 }
5465
5466 fragment = 0;
5467 while (risc_size > 0 && rval == QLA_SUCCESS) {
5468 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5469 if (wlen > risc_size)
5470 wlen = risc_size;
7c3df132
SK		 5471 ql_dbg(ql_dbg_init, vha, 0x0089,
5472 "Loading risc segment@ risc addr %x number of "
5473 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5474
5475 for (i = 0; i < wlen; i++)
5476 wcode[i] = swab16(fwcode[i]);
5477
73208dfd 5478 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5479 wlen);
5480 if (rval) {
7c3df132
SK		 5481 ql_log(ql_log_fatal, vha, 0x008a,
5482 "Failed to load segment %d of firmware.\n",
5483 fragment);
5433383e
AV		 5484 break;
5485 }
5486
5487 fwcode += wlen;
5488 risc_addr += wlen;
5489 risc_size -= wlen;
5490 fragment++;
5491 }
5492
5493 /* Next segment. */
5494 seg++;
5495 }
5496 return rval;
5497
5498fail_fw_integrity:
5499 return QLA_FUNCTION_FAILED;
5500}
5501
eaac30be
AV		 5502static int
5503qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5504{
5505 int rval;
5506 int segments, fragment;
5507 uint32_t *dcode, dlen;
5508 uint32_t risc_addr;
5509 uint32_t risc_size;
5510 uint32_t i;
5433383e 5511 struct fw_blob *blob;
f73cb695
CD		 5512 const uint32_t *fwcode;
5513 uint32_t fwclen;
e315cd28 5514 struct qla_hw_data *ha = vha->hw;
73208dfd 5515 struct req_que *req = ha->req_q_map[0];
0107109e 5516
5433383e 5517 /* Load firmware blob. */
e315cd28 5518 blob = qla2x00_request_firmware(vha);
5433383e 5519 if (!blob) {
7c3df132 5520 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 5521 "Firmware image unavailable.\n");
7c3df132
SK		 5522 ql_log(ql_log_warn, vha, 0x0091,
5523 "Firmware images can be retrieved from: "
5524 QLA_FW_URL ".\n");
d1c61909 5525
eaac30be 5526 return QLA_FUNCTION_FAILED;
0107109e
AV		 5527 }
5528
cfb0919c
CD		 5529 ql_dbg(ql_dbg_init, vha, 0x0092,
5530 "FW: Loading via request-firmware.\n");
eaac30be 5531
0107109e
AV		 5532 rval = QLA_SUCCESS;
5533
5534 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5535 dcode = (uint32_t *)req->ring;
0107109e 5536 *srisc_addr = 0;
5433383e 5537 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5538 fwclen = 0;
5539
5540 /* Validate firmware image by checking version. */
5433383e 5541 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5542 ql_log(ql_log_fatal, vha, 0x0093,
5543 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5544 blob->fw->size);
f73cb695 5545 return QLA_FUNCTION_FAILED;
0107109e
AV		 5546 }
5547 for (i = 0; i < 4; i++)
5548 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5549 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5550 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5551 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5552 dcode[3] == 0)) {
7c3df132
SK		 5553 ql_log(ql_log_fatal, vha, 0x0094,
5554 "Unable to verify integrity of firmware image (%Zd).\n",
5555 blob->fw->size);
5556 ql_log(ql_log_fatal, vha, 0x0095,
5557 "Firmware data: %08x %08x %08x %08x.\n",
5558 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5559 return QLA_FUNCTION_FAILED;
0107109e
AV		 5560 }
5561
5562 while (segments && rval == QLA_SUCCESS) {
5563 risc_addr = be32_to_cpu(fwcode[2]);
5564 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5565 risc_size = be32_to_cpu(fwcode[3]);
5566
5567 /* Validate firmware image size. */
5568 fwclen += risc_size * sizeof(uint32_t);
5433383e 5569 if (blob->fw->size < fwclen) {
7c3df132 5570 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5571 "Unable to verify integrity of firmware image "
7c3df132 5572 "(%Zd).\n", blob->fw->size);
f73cb695 5573 return QLA_FUNCTION_FAILED;
0107109e
AV		 5574 }
5575
5576 fragment = 0;
5577 while (risc_size > 0 && rval == QLA_SUCCESS) {
5578 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5579 if (dlen > risc_size)
5580 dlen = risc_size;
5581
7c3df132
SK		 5582 ql_dbg(ql_dbg_init, vha, 0x0097,
5583 "Loading risc segment@ risc addr %x "
5584 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5585
5586 for (i = 0; i < dlen; i++)
5587 dcode[i] = swab32(fwcode[i]);
5588
73208dfd 5589 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5590 dlen);
0107109e 5591 if (rval) {
7c3df132
SK		 5592 ql_log(ql_log_fatal, vha, 0x0098,
5593 "Failed to load segment %d of firmware.\n",
5594 fragment);
f261f7af 5595 return QLA_FUNCTION_FAILED;
0107109e
AV		 5596 }
5597
5598 fwcode += dlen;
5599 risc_addr += dlen;
5600 risc_size -= dlen;
5601 fragment++;
5602 }
5603
5604 /* Next segment. */
5605 segments--;
5606 }
f73cb695
CD		 5607
5608 if (!IS_QLA27XX(ha))
5609 return rval;
5610
5611 if (ha->fw_dump_template)
5612 vfree(ha->fw_dump_template);
5613 ha->fw_dump_template = NULL;
5614 ha->fw_dump_template_len = 0;
5615
5616 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 5617 "Loading fwdump template from %x\n",
5618 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 5619 risc_size = be32_to_cpu(fwcode[2]);
5620 ql_dbg(ql_dbg_init, vha, 0x172,
5621 "-> array size %x dwords\n", risc_size);
5622 if (risc_size == 0 || risc_size == ~0)
5623 goto default_template;
5624
5625 dlen = (risc_size - 8) * sizeof(*fwcode);
5626 ql_dbg(ql_dbg_init, vha, 0x0173,
5627 "-> template allocating %x bytes...\n", dlen);
5628 ha->fw_dump_template = vmalloc(dlen);
5629 if (!ha->fw_dump_template) {
5630 ql_log(ql_log_warn, vha, 0x0174,
5631 "Failed fwdump template allocate %x bytes.\n", risc_size);
5632 goto default_template;
5633 }
5634
5635 fwcode += 7;
5636 risc_size -= 8;
5637 dcode = ha->fw_dump_template;
5638 for (i = 0; i < risc_size; i++)
5639 dcode[i] = le32_to_cpu(fwcode[i]);
5640
5641 if (!qla27xx_fwdt_template_valid(dcode)) {
5642 ql_log(ql_log_warn, vha, 0x0175,
5643 "Failed fwdump template validate\n");
5644 goto default_template;
5645 }
5646
5647 dlen = qla27xx_fwdt_template_size(dcode);
5648 ql_dbg(ql_dbg_init, vha, 0x0176,
5649 "-> template size %x bytes\n", dlen);
5650 if (dlen > risc_size * sizeof(*fwcode)) {
5651 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 5652 "Failed fwdump template exceeds array by %x bytes\n",
5653 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 5654 goto default_template;
5655 }
5656 ha->fw_dump_template_len = dlen;
0107109e
AV		 5657 return rval;
5658
f73cb695
CD		 5659default_template:
5660 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5661 if (ha->fw_dump_template)
5662 vfree(ha->fw_dump_template);
5663 ha->fw_dump_template = NULL;
5664 ha->fw_dump_template_len = 0;
5665
5666 dlen = qla27xx_fwdt_template_default_size();
5667 ql_dbg(ql_dbg_init, vha, 0x0179,
5668 "-> template allocating %x bytes...\n", dlen);
5669 ha->fw_dump_template = vmalloc(dlen);
5670 if (!ha->fw_dump_template) {
5671 ql_log(ql_log_warn, vha, 0x017a,
5672 "Failed fwdump template allocate %x bytes.\n", risc_size);
5673 goto failed_template;
5674 }
5675
5676 dcode = ha->fw_dump_template;
5677 risc_size = dlen / sizeof(*fwcode);
5678 fwcode = qla27xx_fwdt_template_default();
5679 for (i = 0; i < risc_size; i++)
5680 dcode[i] = be32_to_cpu(fwcode[i]);
5681
5682 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5683 ql_log(ql_log_warn, vha, 0x017b,
5684 "Failed fwdump template validate\n");
5685 goto failed_template;
5686 }
5687
5688 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5689 ql_dbg(ql_dbg_init, vha, 0x017c,
5690 "-> template size %x bytes\n", dlen);
5691 ha->fw_dump_template_len = dlen;
5692 return rval;
5693
5694failed_template:
5695 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5696 if (ha->fw_dump_template)
5697 vfree(ha->fw_dump_template);
5698 ha->fw_dump_template = NULL;
5699 ha->fw_dump_template_len = 0;
5700 return rval;
0107109e 5701}
18c6c127 5702
eaac30be
AV		 5703int
5704qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5705{
5706 int rval;
5707
e337d907
AV		 5708 if (ql2xfwloadbin == 1)
5709 return qla81xx_load_risc(vha, srisc_addr);
5710
eaac30be
AV		 5711 /*
5712 * FW Load priority:
5713 * 1) Firmware via request-firmware interface (.bin file).
5714 * 2) Firmware residing in flash.
5715 */
5716 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5717 if (rval == QLA_SUCCESS)
5718 return rval;
5719
cbc8eb67
AV		 5720 return qla24xx_load_risc_flash(vha, srisc_addr,
5721 vha->hw->flt_region_fw);
eaac30be
AV		 5722}
5723
5724int
5725qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5726{
5727 int rval;
cbc8eb67 5728 struct qla_hw_data *ha = vha->hw;
eaac30be 5729
e337d907 5730 if (ql2xfwloadbin == 2)
cbc8eb67 5731 goto try_blob_fw;
e337d907 5732
eaac30be
AV		 5733 /*
5734 * FW Load priority:
5735 * 1) Firmware residing in flash.
5736 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5737 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5738 */
cbc8eb67 5739 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5740 if (rval == QLA_SUCCESS)
5741 return rval;
5742
cbc8eb67
AV		 5743try_blob_fw:
5744 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5745 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5746 return rval;
5747
7c3df132
SK		 5748 ql_log(ql_log_info, vha, 0x0099,
5749 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5750 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5751 if (rval != QLA_SUCCESS)
5752 return rval;
5753
7c3df132 5754 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5755 ha->flags.running_gold_fw = 1;
cbc8eb67 5756 return rval;
eaac30be
AV		 5757}
5758
18c6c127 5759void
e315cd28 5760qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5761{
5762 int ret, retries;
e315cd28 5763 struct qla_hw_data *ha = vha->hw;
18c6c127 5764
85880801
AV		 5765 if (ha->flags.pci_channel_io_perm_failure)
5766 return;
e428924c 5767 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5768 return;
75edf81d
AV		 5769 if (!ha->fw_major_version)
5770 return;
18c6c127 5771
e315cd28 5772 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5773 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5774 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5775 ha->isp_ops->reset_chip(vha);
5776 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5777 continue;
e315cd28 5778 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5779 continue;
7c3df132
SK		 5780 ql_log(ql_log_info, vha, 0x8015,
5781 "Attempting retry of stop-firmware command.\n");
e315cd28 5782 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5783 }
5784}
2c3dfe3f
SJ		 5785
5786int
e315cd28 5787qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5788{
5789 int rval = QLA_SUCCESS;
0b91d116 5790 int rval2;
2c3dfe3f 5791 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5792 struct qla_hw_data *ha = vha->hw;
5793 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5794 struct req_que *req;
5795 struct rsp_que *rsp;
2c3dfe3f 5796
e315cd28 5797 if (!vha->vp_idx)
2c3dfe3f
SJ		 5798 return -EINVAL;
5799
e315cd28 5800 rval = qla2x00_fw_ready(base_vha);
7163ea81 5801 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5802 req = ha->req_q_map[0];
5803 else
5804 req = vha->req;
5805 rsp = req->rsp;
5806
2c3dfe3f 5807 if (rval == QLA_SUCCESS) {
e315cd28 5808 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5809 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5810 }
5811
e315cd28 5812 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5813
5814 /* Login to SNS first */
0b91d116
CD		 5815 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5816 BIT_1);
5817 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5818 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5819 ql_dbg(ql_dbg_init, vha, 0x0120,
5820 "Failed SNS login: loop_id=%x, rval2=%d\n",
5821 NPH_SNS, rval2);
5822 else
5823 ql_dbg(ql_dbg_init, vha, 0x0103,
5824 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5825 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5826 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5827 return (QLA_FUNCTION_FAILED);
5828 }
5829
e315cd28
AC		 5830 atomic_set(&vha->loop_down_timer, 0);
5831 atomic_set(&vha->loop_state, LOOP_UP);
5832 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5833 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5834 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5835
5836 return rval;
5837}
4d4df193
HK		 5838
5839/* 84XX Support **************************************************************/
5840
5841static LIST_HEAD(qla_cs84xx_list);
5842static DEFINE_MUTEX(qla_cs84xx_mutex);
5843
5844static struct qla_chip_state_84xx *
e315cd28 5845qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5846{
5847 struct qla_chip_state_84xx *cs84xx;
e315cd28 5848 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5849
5850 mutex_lock(&qla_cs84xx_mutex);
5851
5852 /* Find any shared 84xx chip. */
5853 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5854 if (cs84xx->bus == ha->pdev->bus) {
5855 kref_get(&cs84xx->kref);
5856 goto done;
5857 }
5858 }
5859
5860 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5861 if (!cs84xx)
5862 goto done;
5863
5864 kref_init(&cs84xx->kref);
5865 spin_lock_init(&cs84xx->access_lock);
5866 mutex_init(&cs84xx->fw_update_mutex);
5867 cs84xx->bus = ha->pdev->bus;
5868
5869 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5870done:
5871 mutex_unlock(&qla_cs84xx_mutex);
5872 return cs84xx;
5873}
5874
5875static void
5876__qla84xx_chip_release(struct kref *kref)
5877{
5878 struct qla_chip_state_84xx *cs84xx =
5879 container_of(kref, struct qla_chip_state_84xx, kref);
5880
5881 mutex_lock(&qla_cs84xx_mutex);
5882 list_del(&cs84xx->list);
5883 mutex_unlock(&qla_cs84xx_mutex);
5884 kfree(cs84xx);
5885}
5886
5887void
e315cd28 5888qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5889{
e315cd28 5890 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5891 if (ha->cs84xx)
5892 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5893}
5894
5895static int
e315cd28 5896qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5897{
5898 int rval;
5899 uint16_t status[2];
e315cd28 5900 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5901
5902 mutex_lock(&ha->cs84xx->fw_update_mutex);
5903
e315cd28 5904 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5905
5906 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5907
5908 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5909 QLA_SUCCESS;
5910}
3a03eb79
AV		 5911
5912/* 81XX Support **************************************************************/
5913
5914int
5915qla81xx_nvram_config(scsi_qla_host_t *vha)
5916{
5917 int rval;
5918 struct init_cb_81xx *icb;
5919 struct nvram_81xx *nv;
5920 uint32_t *dptr;
5921 uint8_t *dptr1, *dptr2;
5922 uint32_t chksum;
5923 uint16_t cnt;
5924 struct qla_hw_data *ha = vha->hw;
5925
5926 rval = QLA_SUCCESS;
5927 icb = (struct init_cb_81xx *)ha->init_cb;
5928 nv = ha->nvram;
5929
5930 /* Determine NVRAM starting address. */
5931 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5932 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5933 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5934 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5935
5936 /* Get VPD data into cache */
5937 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5938 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5939 ha->vpd_size);
3a03eb79
AV		 5940
5941 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5942 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5943 ha->nvram_size);
3d79038f 5944 dptr = (uint32_t *)nv;
3a03eb79
AV		 5945 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5946 chksum += le32_to_cpu(*dptr++);
5947
7c3df132
SK		 5948 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5949 "Contents of NVRAM:\n");
5950 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5951 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5952
5953 /* Bad NVRAM data, set defaults parameters. */
5954 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5955 || nv->id[3] != ' ' ||
5956 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5957 /* Reset NVRAM data. */
7c3df132 5958 ql_log(ql_log_info, vha, 0x0073,
9e336520 5959 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5960 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5961 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5962 ql_log(ql_log_info, vha, 0x0074,
5963 "Falling back to functioning (yet invalid -- WWPN) "
5964 "defaults.\n");
3a03eb79
AV		 5965
5966 /*
5967 * Set default initialization control block.
5968 */
5969 memset(nv, 0, ha->nvram_size);
5970 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5971 nv->version = __constant_cpu_to_le16(ICB_VERSION);
98aee70d 5972 nv->frame_payload_size = 2048;
3a03eb79
AV		 5973 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5974 nv->exchange_count = __constant_cpu_to_le16(0);
5975 nv->port_name[0] = 0x21;
f73cb695 5976 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 5977 nv->port_name[2] = 0x00;
5978 nv->port_name[3] = 0xe0;
5979 nv->port_name[4] = 0x8b;
5980 nv->port_name[5] = 0x1c;
5981 nv->port_name[6] = 0x55;
5982 nv->port_name[7] = 0x86;
5983 nv->node_name[0] = 0x20;
5984 nv->node_name[1] = 0x00;
5985 nv->node_name[2] = 0x00;
5986 nv->node_name[3] = 0xe0;
5987 nv->node_name[4] = 0x8b;
5988 nv->node_name[5] = 0x1c;
5989 nv->node_name[6] = 0x55;
5990 nv->node_name[7] = 0x86;
5991 nv->login_retry_count = __constant_cpu_to_le16(8);
5992 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5993 nv->login_timeout = __constant_cpu_to_le16(0);
5994 nv->firmware_options_1 =
5995 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5996 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5997 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5998 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5999 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
6000 nv->efi_parameters = __constant_cpu_to_le32(0);
6001 nv->reset_delay = 5;
6002 nv->max_luns_per_target = __constant_cpu_to_le16(128);
6003 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 6004 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 6005 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 6006 nv->enode_mac[1] = 0xC0;
6007 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 6008 nv->enode_mac[3] = 0x04;
6009 nv->enode_mac[4] = 0x05;
f73cb695 6010 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 6011
6012 rval = 1;
6013 }
6014
9e522cd8
AE		 6015 if (IS_T10_PI_CAPABLE(ha))
6016 nv->frame_payload_size &= ~7;
6017
aa230bc5
AE		 6018 qlt_81xx_config_nvram_stage1(vha, nv);
6019
3a03eb79 6020 /* Reset Initialization control block */
773120e4 6021 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 6022
6023 /* Copy 1st segment. */
6024 dptr1 = (uint8_t *)icb;
6025 dptr2 = (uint8_t *)&nv->version;
6026 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6027 while (cnt--)
6028 *dptr1++ = *dptr2++;
6029
6030 icb->login_retry_count = nv->login_retry_count;
6031
6032 /* Copy 2nd segment. */
6033 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6034 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6035 cnt = (uint8_t *)&icb->reserved_5 -
6036 (uint8_t *)&icb->interrupt_delay_timer;
6037 while (cnt--)
6038 *dptr1++ = *dptr2++;
6039
6040 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
6041 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
6042 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 6043 icb->enode_mac[0] = 0x00;
6044 icb->enode_mac[1] = 0xC0;
6045 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 6046 icb->enode_mac[3] = 0x04;
6047 icb->enode_mac[4] = 0x05;
f73cb695 6048 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 6049 }
6050
b64b0e8f
AV		 6051 /* Use extended-initialization control block. */
6052 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
6053
3a03eb79
AV		 6054 /*
6055 * Setup driver NVRAM options.
6056 */
6057 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 6058 "QLE8XXX");
3a03eb79 6059
aa230bc5
AE		 6060 qlt_81xx_config_nvram_stage2(vha, icb);
6061
3a03eb79
AV		 6062 /* Use alternate WWN? */
6063 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
6064 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6065 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6066 }
6067
6068 /* Prepare nodename */
6069 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
6070 /*
6071 * Firmware will apply the following mask if the nodename was
6072 * not provided.
6073 */
6074 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6075 icb->node_name[0] &= 0xF0;
6076 }
6077
6078 /* Set host adapter parameters. */
6079 ha->flags.disable_risc_code_load = 0;
6080 ha->flags.enable_lip_reset = 0;
6081 ha->flags.enable_lip_full_login =
6082 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6083 ha->flags.enable_target_reset =
6084 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
6085 ha->flags.enable_led_scheme = 0;
6086 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
6087
6088 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6089 (BIT_6 | BIT_5 | BIT_4)) >> 4;
6090
6091 /* save HBA serial number */
6092 ha->serial0 = icb->port_name[5];
6093 ha->serial1 = icb->port_name[6];
6094 ha->serial2 = icb->port_name[7];
6095 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6096 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
6097
6098 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
6099
6100 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6101
6102 /* Set minimum login_timeout to 4 seconds. */
6103 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6104 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6105 if (le16_to_cpu(nv->login_timeout) < 4)
6106 nv->login_timeout = __constant_cpu_to_le16(4);
6107 ha->login_timeout = le16_to_cpu(nv->login_timeout);
6108 icb->login_timeout = nv->login_timeout;
6109
6110 /* Set minimum RATOV to 100 tenths of a second. */
6111 ha->r_a_tov = 100;
6112
6113 ha->loop_reset_delay = nv->reset_delay;
6114
6115 /* Link Down Timeout = 0:
6116 *
7ec0effd 6117 * When Port Down timer expires we will start returning
3a03eb79
AV		 6118 * I/O's to OS with "DID_NO_CONNECT".
6119 *
6120 * Link Down Timeout != 0:
6121 *
6122 * The driver waits for the link to come up after link down
6123 * before returning I/Os to OS with "DID_NO_CONNECT".
6124 */
6125 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6126 ha->loop_down_abort_time =
6127 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6128 } else {
6129 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6130 ha->loop_down_abort_time =
6131 (LOOP_DOWN_TIME - ha->link_down_timeout);
6132 }
6133
6134 /* Need enough time to try and get the port back. */
6135 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6136 if (qlport_down_retry)
6137 ha->port_down_retry_count = qlport_down_retry;
6138
6139 /* Set login_retry_count */
6140 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6141 if (ha->port_down_retry_count ==
6142 le16_to_cpu(nv->port_down_retry_count) &&
6143 ha->port_down_retry_count > 3)
6144 ha->login_retry_count = ha->port_down_retry_count;
6145 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6146 ha->login_retry_count = ha->port_down_retry_count;
6147 if (ql2xloginretrycount)
6148 ha->login_retry_count = ql2xloginretrycount;
6149
6246b8a1 6150 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 6151 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
6246b8a1
GM		 6152 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
6153
3a03eb79
AV		 6154 /* Enable ZIO. */
6155 if (!vha->flags.init_done) {
6156 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6157 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6158 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6159 le16_to_cpu(icb->interrupt_delay_timer): 2;
6160 }
6161 icb->firmware_options_2 &= __constant_cpu_to_le32(
6162 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6163 vha->flags.process_response_queue = 0;
6164 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6165 ha->zio_mode = QLA_ZIO_MODE_6;
6166
7c3df132 6167 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6168 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6169 ha->zio_mode,
6170 ha->zio_timer * 100);
3a03eb79
AV		 6171
6172 icb->firmware_options_2 |= cpu_to_le32(
6173 (uint32_t)ha->zio_mode);
6174 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6175 vha->flags.process_response_queue = 1;
6176 }
6177
6178 if (rval) {
7c3df132
SK		 6179 ql_log(ql_log_warn, vha, 0x0076,
6180 "NVRAM configuration failed.\n");
3a03eb79
AV		 6181 }
6182 return (rval);
6183}
6184
a9083016
GM		 6185int
6186qla82xx_restart_isp(scsi_qla_host_t *vha)
6187{
6188 int status, rval;
a9083016
GM		 6189 struct qla_hw_data *ha = vha->hw;
6190 struct req_que *req = ha->req_q_map[0];
6191 struct rsp_que *rsp = ha->rsp_q_map[0];
6192 struct scsi_qla_host *vp;
feafb7b1 6193 unsigned long flags;
a9083016
GM		 6194
6195 status = qla2x00_init_rings(vha);
6196 if (!status) {
6197 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6198 ha->flags.chip_reset_done = 1;
6199
6200 status = qla2x00_fw_ready(vha);
6201 if (!status) {
a9083016
GM		 6202 /* Issue a marker after FW becomes ready. */
6203 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 6204 vha->flags.online = 1;
7108b76e 6205 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 6206 }
6207
6208 /* if no cable then assume it's good */
6209 if ((vha->device_flags & DFLG_NO_CABLE))
6210 status = 0;
a9083016
GM		 6211 }
6212
6213 if (!status) {
6214 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6215
6216 if (!atomic_read(&vha->loop_down_timer)) {
6217 /*
6218 * Issue marker command only when we are going
6219 * to start the I/O .
6220 */
6221 vha->marker_needed = 1;
6222 }
6223
a9083016
GM		 6224 ha->isp_ops->enable_intrs(ha);
6225
6226 ha->isp_abort_cnt = 0;
6227 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6228
53296788 6229 /* Update the firmware version */
3173167f 6230 status = qla82xx_check_md_needed(vha);
53296788 6231
a9083016
GM		 6232 if (ha->fce) {
6233 ha->flags.fce_enabled = 1;
6234 memset(ha->fce, 0,
6235 fce_calc_size(ha->fce_bufs));
6236 rval = qla2x00_enable_fce_trace(vha,
6237 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6238 &ha->fce_bufs);
6239 if (rval) {
cfb0919c 6240 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6241 "Unable to reinitialize FCE (%d).\n",
6242 rval);
a9083016
GM		 6243 ha->flags.fce_enabled = 0;
6244 }
6245 }
6246
6247 if (ha->eft) {
6248 memset(ha->eft, 0, EFT_SIZE);
6249 rval = qla2x00_enable_eft_trace(vha,
6250 ha->eft_dma, EFT_NUM_BUFFERS);
6251 if (rval) {
cfb0919c 6252 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6253 "Unable to reinitialize EFT (%d).\n",
6254 rval);
a9083016
GM		 6255 }
6256 }
a9083016
GM		 6257 }
6258
6259 if (!status) {
cfb0919c 6260 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6261 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6262
6263 spin_lock_irqsave(&ha->vport_slock, flags);
6264 list_for_each_entry(vp, &ha->vp_list, list) {
6265 if (vp->vp_idx) {
6266 atomic_inc(&vp->vref_count);
6267 spin_unlock_irqrestore(&ha->vport_slock, flags);
6268
a9083016 6269 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6270
6271 spin_lock_irqsave(&ha->vport_slock, flags);
6272 atomic_dec(&vp->vref_count);
6273 }
a9083016 6274 }
feafb7b1
AE		 6275 spin_unlock_irqrestore(&ha->vport_slock, flags);
6276
a9083016 6277 } else {
cfb0919c 6278 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6279 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6280 }
6281
6282 return status;
6283}
6284
3a03eb79 6285void
ae97c91e 6286qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6287{
ae97c91e
AV		 6288 struct qla_hw_data *ha = vha->hw;
6289
6290 if (!ql2xetsenable)
6291 return;
6292
6293 /* Enable ETS Burst. */
6294 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6295 ha->fw_options[2] |= BIT_9;
6296 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6297}
09ff701a
SR		 6298
6299/*
6300 * qla24xx_get_fcp_prio
6301 * Gets the fcp cmd priority value for the logged in port.
6302 * Looks for a match of the port descriptors within
6303 * each of the fcp prio config entries. If a match is found,
6304 * the tag (priority) value is returned.
6305 *
6306 * Input:
21090cbe 6307 * vha = scsi host structure pointer.
09ff701a
SR		 6308 * fcport = port structure pointer.
6309 *
6310 * Return:
6c452a45 6311 * non-zero (if found)
f28a0a96 6312 * -1 (if not found)
09ff701a
SR		 6313 *
6314 * Context:
6315 * Kernel context
6316 */
f28a0a96 6317static int
09ff701a
SR		 6318qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6319{
6320 int i, entries;
6321 uint8_t pid_match, wwn_match;
f28a0a96 6322 int priority;
09ff701a
SR		 6323 uint32_t pid1, pid2;
6324 uint64_t wwn1, wwn2;
6325 struct qla_fcp_prio_entry *pri_entry;
6326 struct qla_hw_data *ha = vha->hw;
6327
6328 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6329 return -1;
09ff701a 6330
f28a0a96 6331 priority = -1;
09ff701a
SR		 6332 entries = ha->fcp_prio_cfg->num_entries;
6333 pri_entry = &ha->fcp_prio_cfg->entry[0];
6334
6335 for (i = 0; i < entries; i++) {
6336 pid_match = wwn_match = 0;
6337
6338 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6339 pri_entry++;
6340 continue;
6341 }
6342
6343 /* check source pid for a match */
6344 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6345 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6346 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6347 if (pid1 == INVALID_PORT_ID)
6348 pid_match++;
6349 else if (pid1 == pid2)
6350 pid_match++;
6351 }
6352
6353 /* check destination pid for a match */
6354 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6355 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6356 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6357 if (pid1 == INVALID_PORT_ID)
6358 pid_match++;
6359 else if (pid1 == pid2)
6360 pid_match++;
6361 }
6362
6363 /* check source WWN for a match */
6364 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6365 wwn1 = wwn_to_u64(vha->port_name);
6366 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6367 if (wwn2 == (uint64_t)-1)
6368 wwn_match++;
6369 else if (wwn1 == wwn2)
6370 wwn_match++;
6371 }
6372
6373 /* check destination WWN for a match */
6374 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6375 wwn1 = wwn_to_u64(fcport->port_name);
6376 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6377 if (wwn2 == (uint64_t)-1)
6378 wwn_match++;
6379 else if (wwn1 == wwn2)
6380 wwn_match++;
6381 }
6382
6383 if (pid_match == 2 || wwn_match == 2) {
6384 /* Found a matching entry */
6385 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6386 priority = pri_entry->tag;
6387 break;
6388 }
6389
6390 pri_entry++;
6391 }
6392
6393 return priority;
6394}
6395
6396/*
6397 * qla24xx_update_fcport_fcp_prio
6398 * Activates fcp priority for the logged in fc port
6399 *
6400 * Input:
21090cbe 6401 * vha = scsi host structure pointer.
09ff701a
SR		 6402 * fcp = port structure pointer.
6403 *
6404 * Return:
6405 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6406 *
6407 * Context:
6408 * Kernel context.
6409 */
6410int
21090cbe 6411qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6412{
6413 int ret;
f28a0a96 6414 int priority;
09ff701a
SR		 6415 uint16_t mb[5];
6416
21090cbe
MI		 6417 if (fcport->port_type != FCT_TARGET ||
6418 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6419 return QLA_FUNCTION_FAILED;
6420
21090cbe 6421 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6422 if (priority < 0)
6423 return QLA_FUNCTION_FAILED;
6424
7ec0effd 6425 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6426 fcport->fcp_prio = priority & 0xf;
6427 return QLA_SUCCESS;
6428 }
6429
21090cbe 6430 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6431 if (ret == QLA_SUCCESS) {
6432 if (fcport->fcp_prio != priority)
6433 ql_dbg(ql_dbg_user, vha, 0x709e,
6434 "Updated FCP_CMND priority - value=%d loop_id=%d "
6435 "port_id=%02x%02x%02x.\n", priority,
6436 fcport->loop_id, fcport->d_id.b.domain,
6437 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6438 fcport->fcp_prio = priority & 0xf;
cfb0919c 6439 } else
7c3df132 6440 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6441 "Unable to update FCP_CMND priority - ret=0x%x for "
6442 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6443 fcport->d_id.b.domain, fcport->d_id.b.area,
6444 fcport->d_id.b.al_pa);
09ff701a
SR		 6445 return ret;
6446}
6447
6448/*
6449 * qla24xx_update_all_fcp_prio
6450 * Activates fcp priority for all the logged in ports
6451 *
6452 * Input:
6453 * ha = adapter block pointer.
6454 *
6455 * Return:
6456 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6457 *
6458 * Context:
6459 * Kernel context.
6460 */
6461int
6462qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6463{
6464 int ret;
6465 fc_port_t *fcport;
6466
6467 ret = QLA_FUNCTION_FAILED;
6468 /* We need to set priority for all logged in ports */
6469 list_for_each_entry(fcport, &vha->vp_fcports, list)
6470 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6471
6472 return ret;
6473}
Linux 6.x block layer and io_uring tree(s)