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scsi: qla2xxx: Serialize GPNID for multiple RSCN
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
a5d42f4c 39static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
726b8548
QT		 40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
a5d42f4c
DG		 42static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
43 struct event_arg *);
4d4df193 44
ac280b67
AV		 45/* SRB Extensions ---------------------------------------------------------- */
46
9ba56b95 47void
8e5f4ba0 48qla2x00_sp_timeout(struct timer_list *t)
ac280b67 49{
8e5f4ba0 50 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
4916392b 51 struct srb_iocb *iocb;
25ff6af1 52 scsi_qla_host_t *vha = sp->vha;
ac280b67
AV		 53 struct req_que *req;
54 unsigned long flags;
55
25ff6af1
JC		 56 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
57 req = vha->hw->req_q_map[0];
ac280b67 58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
25ff6af1
JC		 61 sp->free(sp);
62 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95 65void
25ff6af1 66qla2x00_sp_free(void *ptr)
ac280b67 67{
25ff6af1 68 srb_t *sp = ptr;
9ba56b95 69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
25ff6af1 72 qla2x00_rel_sp(sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67 96
726b8548 97void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
25ff6af1 100 srb_t *sp = data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
726b8548
QT		 102 struct srb_iocb *lio = &sp->u.iocb_cmd;
103 struct event_arg ea;
ac280b67 104
7c3df132 105 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
726b8548
QT		 106 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
107 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
ac280b67 108
5ff1d584 109 fcport->flags &= ~FCF_ASYNC_SENT;
726b8548
QT		 110
111 switch (sp->type) {
112 case SRB_LOGIN_CMD:
6ac52608
AV		 113 /* Retry as needed. */
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
726b8548
QT		 117 memset(&ea, 0, sizeof(ea));
118 ea.event = FCME_PLOGI_DONE;
119 ea.fcport = sp->fcport;
120 ea.data[0] = lio->u.logio.data[0];
121 ea.data[1] = lio->u.logio.data[1];
122 ea.sp = sp;
123 qla24xx_handle_plogi_done_event(fcport->vha, &ea);
124 break;
125 case SRB_LOGOUT_CMD:
a6ca8878 126 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
726b8548
QT		 127 break;
128 case SRB_CT_PTHRU_CMD:
129 case SRB_MB_IOCB:
130 case SRB_NACK_PLOGI:
131 case SRB_NACK_PRLI:
132 case SRB_NACK_LOGO:
25ff6af1 133 sp->done(sp, QLA_FUNCTION_TIMEOUT);
726b8548 134 break;
6ac52608 135 }
ac280b67
AV		 136}
137
99b0bec7 138static void
25ff6af1 139qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 140{
25ff6af1
JC		 141 srb_t *sp = ptr;
142 struct scsi_qla_host *vha = sp->vha;
9ba56b95 143 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 144 struct event_arg ea;
9ba56b95 145
83548fe2 146 ql_dbg(ql_dbg_disc, vha, 0x20dd,
25ff6af1 147 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548
QT		 148
149 sp->fcport->flags &= ~FCF_ASYNC_SENT;
150 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
151 memset(&ea, 0, sizeof(ea));
152 ea.event = FCME_PLOGI_DONE;
153 ea.fcport = sp->fcport;
154 ea.data[0] = lio->u.logio.data[0];
155 ea.data[1] = lio->u.logio.data[1];
156 ea.iop[0] = lio->u.logio.iop[0];
157 ea.iop[1] = lio->u.logio.iop[1];
158 ea.sp = sp;
159 qla2x00_fcport_event_handler(vha, &ea);
160 }
9ba56b95 161
25ff6af1 162 sp->free(sp);
99b0bec7
AV		 163}
164
ac280b67
AV		 165int
166qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
167 uint16_t *data)
168{
ac280b67 169 srb_t *sp;
4916392b 170 struct srb_iocb *lio;
726b8548
QT		 171 int rval = QLA_FUNCTION_FAILED;
172
173 if (!vha->flags.online)
174 goto done;
175
176 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
177 (fcport->fw_login_state == DSC_LS_PLOGI_COMP) ||
178 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
179 goto done;
ac280b67 180
9ba56b95 181 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 182 if (!sp)
183 goto done;
184
726b8548
QT		 185 fcport->flags |= FCF_ASYNC_SENT;
186 fcport->logout_completed = 0;
187
9ba56b95
GM		 188 sp->type = SRB_LOGIN_CMD;
189 sp->name = "login";
190 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
191
192 lio = &sp->u.iocb_cmd;
3822263e 193 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 194 sp->done = qla2x00_async_login_sp_done;
4916392b 195 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
a5d42f4c
DG		 196
197 if (fcport->fc4f_nvme)
198 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
199
ac280b67 200 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 201 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 202 rval = qla2x00_start_sp(sp);
080c9517
CD		 203 if (rval != QLA_SUCCESS) {
204 fcport->flags &= ~FCF_ASYNC_SENT;
205 fcport->flags |= FCF_LOGIN_NEEDED;
206 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 207 goto done_free_sp;
080c9517 208 }
ac280b67 209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 211 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
212 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 213 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
214 fcport->login_retry);
ac280b67
AV		 215 return rval;
216
217done_free_sp:
25ff6af1 218 sp->free(sp);
ac280b67 219done:
726b8548 220 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 221 return rval;
222}
223
99b0bec7 224static void
25ff6af1 225qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 226{
25ff6af1 227 srb_t *sp = ptr;
9ba56b95 228 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95 229
726b8548 230 sp->fcport->flags &= ~FCF_ASYNC_SENT;
25ff6af1
JC		 231 if (!test_bit(UNLOADING, &sp->vha->dpc_flags))
232 qla2x00_post_async_logout_done_work(sp->vha, sp->fcport,
9ba56b95 233 lio->u.logio.data);
25ff6af1 234 sp->free(sp);
99b0bec7
AV		 235}
236
ac280b67
AV		 237int
238qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
239{
ac280b67 240 srb_t *sp;
4916392b 241 struct srb_iocb *lio;
ac280b67
AV		 242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
726b8548 245 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 246 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 247 if (!sp)
248 goto done;
249
9ba56b95
GM		 250 sp->type = SRB_LOGOUT_CMD;
251 sp->name = "logout";
252 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
253
254 lio = &sp->u.iocb_cmd;
3822263e 255 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 256 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 262 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 264 fcport->d_id.b.area, fcport->d_id.b.al_pa,
265 fcport->port_name);
ac280b67
AV		 266 return rval;
267
268done_free_sp:
25ff6af1 269 sp->free(sp);
ac280b67 270done:
726b8548 271 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 272 return rval;
273}
274
5ff1d584 275static void
25ff6af1 276qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 277{
25ff6af1
JC		 278 srb_t *sp = ptr;
279 struct scsi_qla_host *vha = sp->vha;
9ba56b95 280 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95
GM		 281
282 if (!test_bit(UNLOADING, &vha->dpc_flags))
25ff6af1 283 qla2x00_post_async_adisc_done_work(sp->vha, sp->fcport,
9ba56b95 284 lio->u.logio.data);
25ff6af1 285 sp->free(sp);
5ff1d584
AV		 286}
287
288int
289qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
290 uint16_t *data)
291{
5ff1d584 292 srb_t *sp;
4916392b 293 struct srb_iocb *lio;
5ff1d584
AV		 294 int rval;
295
296 rval = QLA_FUNCTION_FAILED;
726b8548 297 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 298 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 299 if (!sp)
300 goto done;
301
9ba56b95
GM		 302 sp->type = SRB_ADISC_CMD;
303 sp->name = "adisc";
304 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
305
306 lio = &sp->u.iocb_cmd;
3822263e 307 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 308 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 309 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 310 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 311 rval = qla2x00_start_sp(sp);
312 if (rval != QLA_SUCCESS)
313 goto done_free_sp;
314
7c3df132 315 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 316 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
317 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
318 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 319 return rval;
320
321done_free_sp:
25ff6af1 322 sp->free(sp);
5ff1d584 323done:
726b8548
QT		 324 fcport->flags &= ~FCF_ASYNC_SENT;
325 return rval;
326}
327
328static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
329 struct event_arg *ea)
330{
331 fc_port_t *fcport, *conflict_fcport;
332 struct get_name_list_extended *e;
333 u16 i, n, found = 0, loop_id;
334 port_id_t id;
335 u64 wwn;
a5d42f4c 336 u8 opt = 0, current_login_state;
726b8548
QT		 337
338 fcport = ea->fcport;
339
340 if (ea->rc) { /* rval */
341 if (fcport->login_retry == 0) {
342 fcport->login_retry = vha->hw->login_retry_count;
83548fe2
QT		 343 ql_dbg(ql_dbg_disc, vha, 0x20de,
344 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
345 fcport->port_name, fcport->login_retry);
726b8548
QT		 346 }
347 return;
348 }
349
350 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 351 ql_dbg(ql_dbg_disc, vha, 0x20df,
726b8548
QT		 352 "%s %8phC rscn gen changed rscn %d|%d \n",
353 __func__, fcport->port_name,
354 fcport->last_rscn_gen, fcport->rscn_gen);
355 qla24xx_post_gidpn_work(vha, fcport);
356 return;
357 } else if (fcport->last_login_gen != fcport->login_gen) {
83548fe2
QT		 358 ql_dbg(ql_dbg_disc, vha, 0x20e0,
359 "%s %8phC login gen changed login %d|%d\n",
360 __func__, fcport->port_name,
361 fcport->last_login_gen, fcport->login_gen);
726b8548
QT		 362 return;
363 }
364
365 n = ea->data[0] / sizeof(struct get_name_list_extended);
366
83548fe2 367 ql_dbg(ql_dbg_disc, vha, 0x20e1,
726b8548
QT		 368 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
369 __func__, __LINE__, fcport->port_name, n,
370 fcport->d_id.b.domain, fcport->d_id.b.area,
371 fcport->d_id.b.al_pa, fcport->loop_id);
372
373 for (i = 0; i < n; i++) {
374 e = &vha->gnl.l[i];
375 wwn = wwn_to_u64(e->port_name);
376
377 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
378 continue;
379
380 found = 1;
381 id.b.domain = e->port_id[2];
382 id.b.area = e->port_id[1];
383 id.b.al_pa = e->port_id[0];
384 id.b.rsvd_1 = 0;
385
386 loop_id = le16_to_cpu(e->nport_handle);
387 loop_id = (loop_id & 0x7fff);
388
83548fe2
QT		 389 ql_dbg(ql_dbg_disc, vha, 0x20e2,
390 "%s found %8phC CLS [%d|%d] ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
391 __func__, fcport->port_name,
392 e->current_login_state, fcport->fw_login_state,
393 id.b.domain, id.b.area, id.b.al_pa,
394 fcport->d_id.b.domain, fcport->d_id.b.area,
395 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
726b8548
QT		 396
397 if ((id.b24 != fcport->d_id.b24) ||
398 ((fcport->loop_id != FC_NO_LOOP_ID) &&
399 (fcport->loop_id != loop_id))) {
83548fe2
QT		 400 ql_dbg(ql_dbg_disc, vha, 0x20e3,
401 "%s %d %8phC post del sess\n",
402 __func__, __LINE__, fcport->port_name);
726b8548
QT		 403 qlt_schedule_sess_for_deletion(fcport, 1);
404 return;
405 }
406
407 fcport->loop_id = loop_id;
408
409 wwn = wwn_to_u64(fcport->port_name);
410 qlt_find_sess_invalidate_other(vha, wwn,
411 id, loop_id, &conflict_fcport);
412
413 if (conflict_fcport) {
414 /*
415 * Another share fcport share the same loop_id &
416 * nport id. Conflict fcport needs to finish
417 * cleanup before this fcport can proceed to login.
418 */
419 conflict_fcport->conflict = fcport;
420 fcport->login_pause = 1;
421 }
422
a5d42f4c
DG		 423 if (fcport->fc4f_nvme)
424 current_login_state = e->current_login_state >> 4;
425 else
426 current_login_state = e->current_login_state & 0xf;
427
428 switch (current_login_state) {
726b8548 429 case DSC_LS_PRLI_COMP:
83548fe2
QT		 430 ql_dbg(ql_dbg_disc, vha, 0x20e4,
431 "%s %d %8phC post gpdb\n",
432 __func__, __LINE__, fcport->port_name);
726b8548
QT		 433 opt = PDO_FORCE_ADISC;
434 qla24xx_post_gpdb_work(vha, fcport, opt);
435 break;
726b8548
QT		 436 case DSC_LS_PORT_UNAVAIL:
437 default:
438 if (fcport->loop_id == FC_NO_LOOP_ID) {
439 qla2x00_find_new_loop_id(vha, fcport);
440 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
441 }
83548fe2
QT		 442 ql_dbg(ql_dbg_disc, vha, 0x20e5,
443 "%s %d %8phC\n",
444 __func__, __LINE__, fcport->port_name);
726b8548
QT		 445 qla24xx_fcport_handle_login(vha, fcport);
446 break;
447 }
448 }
449
450 if (!found) {
451 /* fw has no record of this port */
452 if (fcport->loop_id == FC_NO_LOOP_ID) {
453 qla2x00_find_new_loop_id(vha, fcport);
454 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
455 } else {
456 for (i = 0; i < n; i++) {
457 e = &vha->gnl.l[i];
458 id.b.domain = e->port_id[0];
459 id.b.area = e->port_id[1];
460 id.b.al_pa = e->port_id[2];
461 id.b.rsvd_1 = 0;
462 loop_id = le16_to_cpu(e->nport_handle);
463
464 if (fcport->d_id.b24 == id.b24) {
465 conflict_fcport =
466 qla2x00_find_fcport_by_wwpn(vha,
467 e->port_name, 0);
468
83548fe2 469 ql_dbg(ql_dbg_disc, vha, 0x20e6,
726b8548
QT		 470 "%s %d %8phC post del sess\n",
471 __func__, __LINE__,
472 conflict_fcport->port_name);
473 qlt_schedule_sess_for_deletion
474 (conflict_fcport, 1);
475 }
476
477 if (fcport->loop_id == loop_id) {
478 /* FW already picked this loop id for another fcport */
479 qla2x00_find_new_loop_id(vha, fcport);
480 }
481 }
482 }
483 qla24xx_fcport_handle_login(vha, fcport);
484 }
485} /* gnl_event */
486
487static void
25ff6af1 488qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 489{
25ff6af1
JC		 490 struct srb *sp = s;
491 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 492 unsigned long flags;
493 struct fc_port *fcport = NULL, *tf;
494 u16 i, n = 0, loop_id;
495 struct event_arg ea;
496 struct get_name_list_extended *e;
497 u64 wwn;
498 struct list_head h;
499
83548fe2 500 ql_dbg(ql_dbg_disc, vha, 0x20e7,
726b8548
QT		 501 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
502 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
503 sp->u.iocb_cmd.u.mbx.in_mb[2]);
504
505 memset(&ea, 0, sizeof(ea));
506 ea.sp = sp;
507 ea.rc = res;
508 ea.event = FCME_GNL_DONE;
509
510 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
511 sizeof(struct get_name_list_extended)) {
512 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
513 sizeof(struct get_name_list_extended);
514 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
515 }
516
517 for (i = 0; i < n; i++) {
518 e = &vha->gnl.l[i];
519 loop_id = le16_to_cpu(e->nport_handle);
520 /* mask out reserve bit */
521 loop_id = (loop_id & 0x7fff);
522 set_bit(loop_id, vha->hw->loop_id_map);
523 wwn = wwn_to_u64(e->port_name);
524
83548fe2 525 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
726b8548
QT		 526 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
527 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
528 e->port_id[0], e->current_login_state, e->last_login_state,
529 (loop_id & 0x7fff));
530 }
531
532 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
533 vha->gnl.sent = 0;
534
535 INIT_LIST_HEAD(&h);
536 fcport = tf = NULL;
537 if (!list_empty(&vha->gnl.fcports))
538 list_splice_init(&vha->gnl.fcports, &h);
539
540 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
541 list_del_init(&fcport->gnl_entry);
542 fcport->flags &= ~FCF_ASYNC_SENT;
543 ea.fcport = fcport;
544
545 qla2x00_fcport_event_handler(vha, &ea);
546 }
547
548 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
549
25ff6af1 550 sp->free(sp);
726b8548
QT		 551}
552
553int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
554{
555 srb_t *sp;
556 struct srb_iocb *mbx;
557 int rval = QLA_FUNCTION_FAILED;
558 unsigned long flags;
559 u16 *mb;
560
561 if (!vha->flags.online)
562 goto done;
563
83548fe2 564 ql_dbg(ql_dbg_disc, vha, 0x20d9,
726b8548
QT		 565 "Async-gnlist WWPN %8phC \n", fcport->port_name);
566
567 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
568 fcport->flags |= FCF_ASYNC_SENT;
569 fcport->disc_state = DSC_GNL;
570 fcport->last_rscn_gen = fcport->rscn_gen;
571 fcport->last_login_gen = fcport->login_gen;
572
573 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
574 if (vha->gnl.sent) {
575 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
576 rval = QLA_SUCCESS;
577 goto done;
578 }
579 vha->gnl.sent = 1;
580 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
581
582 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
583 if (!sp)
584 goto done;
585 sp->type = SRB_MB_IOCB;
586 sp->name = "gnlist";
587 sp->gen1 = fcport->rscn_gen;
588 sp->gen2 = fcport->login_gen;
589
590 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
591
592 mb = sp->u.iocb_cmd.u.mbx.out_mb;
593 mb[0] = MBC_PORT_NODE_NAME_LIST;
594 mb[1] = BIT_2 | BIT_3;
595 mb[2] = MSW(vha->gnl.ldma);
596 mb[3] = LSW(vha->gnl.ldma);
597 mb[6] = MSW(MSD(vha->gnl.ldma));
598 mb[7] = LSW(MSD(vha->gnl.ldma));
599 mb[8] = vha->gnl.size;
600 mb[9] = vha->vp_idx;
601
602 mbx = &sp->u.iocb_cmd;
603 mbx->timeout = qla2x00_async_iocb_timeout;
604
605 sp->done = qla24xx_async_gnl_sp_done;
606
607 rval = qla2x00_start_sp(sp);
608 if (rval != QLA_SUCCESS)
609 goto done_free_sp;
610
83548fe2
QT		 611 ql_dbg(ql_dbg_disc, vha, 0x20da,
612 "Async-%s - OUT WWPN %8phC hndl %x\n",
613 sp->name, fcport->port_name, sp->handle);
726b8548
QT		 614
615 return rval;
616
617done_free_sp:
25ff6af1 618 sp->free(sp);
726b8548
QT		 619done:
620 fcport->flags &= ~FCF_ASYNC_SENT;
621 return rval;
622}
623
624int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
625{
626 struct qla_work_evt *e;
627
628 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
629 if (!e)
630 return QLA_FUNCTION_FAILED;
631
632 e->u.fcport.fcport = fcport;
633 return qla2x00_post_work(vha, e);
634}
635
636static
25ff6af1 637void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 638{
25ff6af1
JC		 639 struct srb *sp = s;
640 struct scsi_qla_host *vha = sp->vha;
726b8548 641 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 642 struct port_database_24xx *pd;
643 fc_port_t *fcport = sp->fcport;
644 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
645 int rval = QLA_SUCCESS;
646 struct event_arg ea;
647
83548fe2 648 ql_dbg(ql_dbg_disc, vha, 0x20db,
726b8548
QT		 649 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
650 sp->name, res, fcport->port_name, mb[1], mb[2]);
651
652 fcport->flags &= ~FCF_ASYNC_SENT;
653
654 if (res) {
655 rval = res;
656 goto gpd_error_out;
657 }
658
659 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
660
15f30a57 661 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
726b8548
QT		 662
663gpd_error_out:
664 memset(&ea, 0, sizeof(ea));
665 ea.event = FCME_GPDB_DONE;
666 ea.rc = rval;
667 ea.fcport = fcport;
668 ea.sp = sp;
669
670 qla2x00_fcport_event_handler(vha, &ea);
671
672 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
673 sp->u.iocb_cmd.u.mbx.in_dma);
674
25ff6af1 675 sp->free(sp);
726b8548
QT		 676}
677
a5d42f4c
DG		 678static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
679{
680 struct qla_work_evt *e;
681
682 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
683 if (!e)
684 return QLA_FUNCTION_FAILED;
685
686 e->u.fcport.fcport = fcport;
687
688 return qla2x00_post_work(vha, e);
689}
690
691static void
692qla2x00_async_prli_sp_done(void *ptr, int res)
693{
694 srb_t *sp = ptr;
695 struct scsi_qla_host *vha = sp->vha;
696 struct srb_iocb *lio = &sp->u.iocb_cmd;
697 struct event_arg ea;
698
699 ql_dbg(ql_dbg_disc, vha, 0x2129,
700 "%s %8phC res %d \n", __func__,
701 sp->fcport->port_name, res);
702
703 sp->fcport->flags &= ~FCF_ASYNC_SENT;
704
705 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
706 memset(&ea, 0, sizeof(ea));
707 ea.event = FCME_PRLI_DONE;
708 ea.fcport = sp->fcport;
709 ea.data[0] = lio->u.logio.data[0];
710 ea.data[1] = lio->u.logio.data[1];
711 ea.iop[0] = lio->u.logio.iop[0];
712 ea.iop[1] = lio->u.logio.iop[1];
713 ea.sp = sp;
714
715 qla2x00_fcport_event_handler(vha, &ea);
716 }
717
718 sp->free(sp);
719}
720
721int
722qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
723{
724 srb_t *sp;
725 struct srb_iocb *lio;
726 int rval = QLA_FUNCTION_FAILED;
727
728 if (!vha->flags.online)
729 return rval;
730
731 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
732 fcport->fw_login_state == DSC_LS_PLOGI_COMP ||
733 fcport->fw_login_state == DSC_LS_PRLI_PEND)
734 return rval;
735
736 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
737 if (!sp)
738 return rval;
739
740 fcport->flags |= FCF_ASYNC_SENT;
741 fcport->logout_completed = 0;
742
743 sp->type = SRB_PRLI_CMD;
744 sp->name = "prli";
745 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
746
747 lio = &sp->u.iocb_cmd;
748 lio->timeout = qla2x00_async_iocb_timeout;
749 sp->done = qla2x00_async_prli_sp_done;
750 lio->u.logio.flags = 0;
751
752 if (fcport->fc4f_nvme)
753 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
754
755 rval = qla2x00_start_sp(sp);
756 if (rval != QLA_SUCCESS) {
757 fcport->flags &= ~FCF_ASYNC_SENT;
758 fcport->flags |= FCF_LOGIN_NEEDED;
759 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
760 goto done_free_sp;
761 }
762
763 ql_dbg(ql_dbg_disc, vha, 0x211b,
764 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d.\n",
765 fcport->port_name, sp->handle, fcport->loop_id,
766 fcport->d_id.b24, fcport->login_retry);
767
768 return rval;
769
770done_free_sp:
771 sp->free(sp);
772 fcport->flags &= ~FCF_ASYNC_SENT;
773 return rval;
774}
775
a07fc0a4 776int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
726b8548
QT		 777{
778 struct qla_work_evt *e;
779
780 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
781 if (!e)
782 return QLA_FUNCTION_FAILED;
783
784 e->u.fcport.fcport = fcport;
785 e->u.fcport.opt = opt;
786 return qla2x00_post_work(vha, e);
787}
788
789int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
790{
791 srb_t *sp;
792 struct srb_iocb *mbx;
793 int rval = QLA_FUNCTION_FAILED;
794 u16 *mb;
795 dma_addr_t pd_dma;
796 struct port_database_24xx *pd;
797 struct qla_hw_data *ha = vha->hw;
798
799 if (!vha->flags.online)
800 goto done;
801
802 fcport->flags |= FCF_ASYNC_SENT;
803 fcport->disc_state = DSC_GPDB;
804
805 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
806 if (!sp)
807 goto done;
808
e0824e69
JC		 809 sp->type = SRB_MB_IOCB;
810 sp->name = "gpdb";
811 sp->gen1 = fcport->rscn_gen;
812 sp->gen2 = fcport->login_gen;
813 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
814
08eb7f45 815 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
726b8548 816 if (pd == NULL) {
83548fe2
QT		 817 ql_log(ql_log_warn, vha, 0xd043,
818 "Failed to allocate port database structure.\n");
726b8548
QT		 819 goto done_free_sp;
820 }
726b8548 821
726b8548
QT		 822 mb = sp->u.iocb_cmd.u.mbx.out_mb;
823 mb[0] = MBC_GET_PORT_DATABASE;
824 mb[1] = fcport->loop_id;
825 mb[2] = MSW(pd_dma);
826 mb[3] = LSW(pd_dma);
827 mb[6] = MSW(MSD(pd_dma));
828 mb[7] = LSW(MSD(pd_dma));
829 mb[9] = vha->vp_idx;
830 mb[10] = opt;
831
832 mbx = &sp->u.iocb_cmd;
833 mbx->timeout = qla2x00_async_iocb_timeout;
834 mbx->u.mbx.in = (void *)pd;
835 mbx->u.mbx.in_dma = pd_dma;
836
837 sp->done = qla24xx_async_gpdb_sp_done;
838
839 rval = qla2x00_start_sp(sp);
840 if (rval != QLA_SUCCESS)
841 goto done_free_sp;
842
83548fe2
QT		 843 ql_dbg(ql_dbg_disc, vha, 0x20dc,
844 "Async-%s %8phC hndl %x opt %x\n",
845 sp->name, fcport->port_name, sp->handle, opt);
726b8548
QT		 846
847 return rval;
848
849done_free_sp:
850 if (pd)
851 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
852
25ff6af1 853 sp->free(sp);
726b8548
QT		 854done:
855 fcport->flags &= ~FCF_ASYNC_SENT;
856 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 857 return rval;
858}
859
726b8548
QT		 860static
861void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
862{
863 int rval = ea->rc;
864 fc_port_t *fcport = ea->fcport;
865 unsigned long flags;
866
867 fcport->flags &= ~FCF_ASYNC_SENT;
868
83548fe2 869 ql_dbg(ql_dbg_disc, vha, 0x20d2,
726b8548
QT		 870 "%s %8phC DS %d LS %d rval %d\n", __func__, fcport->port_name,
871 fcport->disc_state, fcport->fw_login_state, rval);
872
873 if (ea->sp->gen2 != fcport->login_gen) {
874 /* target side must have changed it. */
83548fe2 875 ql_dbg(ql_dbg_disc, vha, 0x20d3,
726b8548
QT		 876 "%s %8phC generation changed rscn %d|%d login %d|%d \n",
877 __func__, fcport->port_name, fcport->last_rscn_gen,
878 fcport->rscn_gen, fcport->last_login_gen,
879 fcport->login_gen);
880 return;
881 } else if (ea->sp->gen1 != fcport->rscn_gen) {
83548fe2 882 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
726b8548
QT		 883 __func__, __LINE__, fcport->port_name);
884 qla24xx_post_gidpn_work(vha, fcport);
885 return;
886 }
887
888 if (rval != QLA_SUCCESS) {
83548fe2 889 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
726b8548
QT		 890 __func__, __LINE__, fcport->port_name);
891 qlt_schedule_sess_for_deletion_lock(fcport);
892 return;
893 }
894
895 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
896 ea->fcport->login_gen++;
897 ea->fcport->deleted = 0;
898 ea->fcport->logout_on_delete = 1;
899
900 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
901 vha->fcport_count++;
902 ea->fcport->login_succ = 1;
903
904 if (!IS_IIDMA_CAPABLE(vha->hw) ||
905 !vha->hw->flags.gpsc_supported) {
83548fe2 906 ql_dbg(ql_dbg_disc, vha, 0x20d6,
726b8548
QT		 907 "%s %d %8phC post upd_fcport fcp_cnt %d\n",
908 __func__, __LINE__, fcport->port_name,
909 vha->fcport_count);
910
911 qla24xx_post_upd_fcport_work(vha, fcport);
912 } else {
83548fe2 913 ql_dbg(ql_dbg_disc, vha, 0x20d7,
726b8548
QT		 914 "%s %d %8phC post gpsc fcp_cnt %d\n",
915 __func__, __LINE__, fcport->port_name,
916 vha->fcport_count);
917
918 qla24xx_post_gpsc_work(vha, fcport);
919 }
920 }
921 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
922} /* gpdb event */
923
924int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
925{
926 if (fcport->login_retry == 0)
927 return 0;
928
929 if (fcport->scan_state != QLA_FCPORT_FOUND)
930 return 0;
931
83548fe2 932 ql_dbg(ql_dbg_disc, vha, 0x20d8,
726b8548
QT		 933 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d|%d retry %d lid %d\n",
934 __func__, fcport->port_name, fcport->disc_state,
935 fcport->fw_login_state, fcport->login_pause, fcport->flags,
936 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
937 fcport->last_login_gen, fcport->login_gen, fcport->login_retry,
938 fcport->loop_id);
939
940 fcport->login_retry--;
941
942 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 943 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
944 return 0;
945
5b33469a
QT		 946 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
947 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
948 return 0;
949 }
950
726b8548
QT		 951 /* for pure Target Mode. Login will not be initiated */
952 if (vha->host->active_mode == MODE_TARGET)
953 return 0;
954
955 if (fcport->flags & FCF_ASYNC_SENT) {
956 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
957 return 0;
958 }
959
960 switch (fcport->disc_state) {
961 case DSC_DELETED:
962 if (fcport->loop_id == FC_NO_LOOP_ID) {
83548fe2
QT		 963 ql_dbg(ql_dbg_disc, vha, 0x20bd,
964 "%s %d %8phC post gnl\n",
965 __func__, __LINE__, fcport->port_name);
726b8548
QT		 966 qla24xx_async_gnl(vha, fcport);
967 } else {
83548fe2
QT		 968 ql_dbg(ql_dbg_disc, vha, 0x20bf,
969 "%s %d %8phC post login\n",
970 __func__, __LINE__, fcport->port_name);
726b8548
QT		 971 fcport->disc_state = DSC_LOGIN_PEND;
972 qla2x00_post_async_login_work(vha, fcport, NULL);
973 }
974 break;
975
976 case DSC_GNL:
977 if (fcport->login_pause) {
978 fcport->last_rscn_gen = fcport->rscn_gen;
979 fcport->last_login_gen = fcport->login_gen;
980 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
981 break;
982 }
983
984 if (fcport->flags & FCF_FCP2_DEVICE) {
985 u8 opt = PDO_FORCE_ADISC;
986
83548fe2
QT		 987 ql_dbg(ql_dbg_disc, vha, 0x20c9,
988 "%s %d %8phC post gpdb\n",
989 __func__, __LINE__, fcport->port_name);
726b8548
QT		 990
991 fcport->disc_state = DSC_GPDB;
992 qla24xx_post_gpdb_work(vha, fcport, opt);
993 } else {
83548fe2
QT		 994 ql_dbg(ql_dbg_disc, vha, 0x20cf,
995 "%s %d %8phC post login\n",
996 __func__, __LINE__, fcport->port_name);
726b8548
QT		 997 fcport->disc_state = DSC_LOGIN_PEND;
998 qla2x00_post_async_login_work(vha, fcport, NULL);
999 }
1000
1001 break;
1002
1003 case DSC_LOGIN_FAILED:
83548fe2
QT		 1004 ql_dbg(ql_dbg_disc, vha, 0x20d0,
1005 "%s %d %8phC post gidpn\n",
1006 __func__, __LINE__, fcport->port_name);
726b8548
QT		 1007
1008 qla24xx_post_gidpn_work(vha, fcport);
1009 break;
1010
1011 case DSC_LOGIN_COMPLETE:
1012 /* recheck login state */
83548fe2
QT		 1013 ql_dbg(ql_dbg_disc, vha, 0x20d1,
1014 "%s %d %8phC post gpdb\n",
1015 __func__, __LINE__, fcport->port_name);
726b8548
QT		 1016
1017 qla24xx_post_gpdb_work(vha, fcport, PDO_FORCE_ADISC);
1018 break;
1019
1020 default:
1021 break;
1022 }
1023
1024 return 0;
1025}
1026
1027static
1028void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
1029{
1030 fcport->rscn_gen++;
1031
83548fe2
QT		 1032 ql_dbg(ql_dbg_disc, fcport->vha, 0x210c,
1033 "%s %8phC DS %d LS %d\n",
1034 __func__, fcport->port_name, fcport->disc_state,
1035 fcport->fw_login_state);
726b8548
QT		 1036
1037 if (fcport->flags & FCF_ASYNC_SENT)
1038 return;
1039
1040 switch (fcport->disc_state) {
1041 case DSC_DELETED:
1042 case DSC_LOGIN_COMPLETE:
1043 qla24xx_post_gidpn_work(fcport->vha, fcport);
1044 break;
1045
1046 default:
1047 break;
1048 }
1049}
1050
1051int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
1052 u8 *port_name, void *pla)
1053{
1054 struct qla_work_evt *e;
1055 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1056 if (!e)
1057 return QLA_FUNCTION_FAILED;
1058
1059 e->u.new_sess.id = *id;
1060 e->u.new_sess.pla = pla;
1061 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
1062
1063 return qla2x00_post_work(vha, e);
1064}
1065
1066static
1067int qla24xx_handle_delete_done_event(scsi_qla_host_t *vha,
1068 struct event_arg *ea)
1069{
1070 fc_port_t *fcport = ea->fcport;
1071
1072 if (test_bit(UNLOADING, &vha->dpc_flags))
1073 return 0;
1074
1075 switch (vha->host->active_mode) {
1076 case MODE_INITIATOR:
1077 case MODE_DUAL:
1078 if (fcport->scan_state == QLA_FCPORT_FOUND)
1079 qla24xx_fcport_handle_login(vha, fcport);
1080 break;
1081
1082 case MODE_TARGET:
1083 default:
1084 /* no-op */
1085 break;
1086 }
1087
1088 return 0;
1089}
1090
1091static
1092void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1093 struct event_arg *ea)
1094{
1095 fc_port_t *fcport = ea->fcport;
1096
1097 if (fcport->scan_state != QLA_FCPORT_FOUND) {
1098 fcport->login_retry++;
1099 return;
1100 }
1101
83548fe2
QT		 1102 ql_dbg(ql_dbg_disc, vha, 0x2102,
1103 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1104 __func__, fcport->port_name, fcport->disc_state,
1105 fcport->fw_login_state, fcport->login_pause,
1106 fcport->deleted, fcport->conflict,
1107 fcport->last_rscn_gen, fcport->rscn_gen,
1108 fcport->last_login_gen, fcport->login_gen,
1109 fcport->flags);
726b8548
QT		 1110
1111 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1112 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1113 return;
1114
5b33469a
QT		 1115 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
1116 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
1117 return;
1118 }
1119
726b8548
QT		 1120 if (fcport->flags & FCF_ASYNC_SENT) {
1121 fcport->login_retry++;
1122 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1123 return;
1124 }
1125
1126 if (fcport->disc_state == DSC_DELETE_PEND) {
1127 fcport->login_retry++;
1128 return;
1129 }
1130
1131 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 1132 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gidpn\n",
726b8548
QT		 1133 __func__, __LINE__, fcport->port_name);
1134
1135 qla24xx_async_gidpn(vha, fcport);
1136 return;
1137 }
1138
1139 qla24xx_fcport_handle_login(vha, fcport);
1140}
1141
41dc529a 1142void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1143{
41dc529a
QT		 1144 fc_port_t *fcport, *f, *tf;
1145 uint32_t id = 0, mask, rid;
726b8548
QT		 1146 int rc;
1147
b98ae0d7
QT		 1148 switch (ea->event) {
1149 case FCME_RELOGIN:
1150 case FCME_RSCN:
1151 case FCME_GIDPN_DONE:
1152 case FCME_GPSC_DONE:
1153 case FCME_GPNID_DONE:
1154 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
1155 test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1156 return;
1157 break;
1158 default:
1159 break;
1160 }
1161
726b8548
QT		 1162 switch (ea->event) {
1163 case FCME_RELOGIN:
1164 if (test_bit(UNLOADING, &vha->dpc_flags))
1165 return;
5ff1d584 1166
726b8548
QT		 1167 qla24xx_handle_relogin_event(vha, ea);
1168 break;
1169 case FCME_RSCN:
1170 if (test_bit(UNLOADING, &vha->dpc_flags))
1171 return;
41dc529a
QT		 1172 switch (ea->id.b.rsvd_1) {
1173 case RSCN_PORT_ADDR:
1174 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1);
1175 if (!fcport) {
1176 /* cable moved */
1177 rc = qla24xx_post_gpnid_work(vha, &ea->id);
1178 if (rc) {
83548fe2
QT		 1179 ql_log(ql_log_warn, vha, 0xd044,
1180 "RSCN GPNID work failed %02x%02x%02x\n",
1181 ea->id.b.domain, ea->id.b.area,
1182 ea->id.b.al_pa);
41dc529a
QT		 1183 }
1184 } else {
1185 ea->fcport = fcport;
1186 qla24xx_handle_rscn_event(fcport, ea);
1187 }
1188 break;
1189 case RSCN_AREA_ADDR:
1190 case RSCN_DOM_ADDR:
1191 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1192 mask = 0xffff00;
83548fe2
QT		 1193 ql_dbg(ql_dbg_async, vha, 0x5044,
1194 "RSCN: Area 0x%06x was affected\n",
1195 ea->id.b24);
41dc529a
QT		 1196 } else {
1197 mask = 0xff0000;
83548fe2
QT		 1198 ql_dbg(ql_dbg_async, vha, 0x507a,
1199 "RSCN: Domain 0x%06x was affected\n",
1200 ea->id.b24);
41dc529a 1201 }
726b8548 1202
41dc529a
QT		 1203 rid = ea->id.b24 & mask;
1204 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1205 list) {
1206 id = f->d_id.b24 & mask;
1207 if (rid == id) {
1208 ea->fcport = f;
1209 qla24xx_handle_rscn_event(f, ea);
1210 }
726b8548 1211 }
41dc529a
QT		 1212 break;
1213 case RSCN_FAB_ADDR:
1214 default:
83548fe2
QT		 1215 ql_log(ql_log_warn, vha, 0xd045,
1216 "RSCN: Fabric was affected. Addr format %d\n",
1217 ea->id.b.rsvd_1);
41dc529a
QT		 1218 qla2x00_mark_all_devices_lost(vha, 1);
1219 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1220 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1221 }
1222 break;
1223 case FCME_GIDPN_DONE:
1224 qla24xx_handle_gidpn_event(vha, ea);
1225 break;
1226 case FCME_GNL_DONE:
1227 qla24xx_handle_gnl_done_event(vha, ea);
1228 break;
1229 case FCME_GPSC_DONE:
1230 qla24xx_post_upd_fcport_work(vha, ea->fcport);
1231 break;
1232 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1233 qla24xx_handle_plogi_done_event(vha, ea);
1234 break;
a5d42f4c
DG		 1235 case FCME_PRLI_DONE:
1236 qla24xx_handle_prli_done_event(vha, ea);
1237 break;
726b8548
QT		 1238 case FCME_GPDB_DONE:
1239 qla24xx_handle_gpdb_event(vha, ea);
1240 break;
1241 case FCME_GPNID_DONE:
1242 qla24xx_handle_gpnid_event(vha, ea);
1243 break;
d3bae931
DG		 1244 case FCME_GFFID_DONE:
1245 qla24xx_handle_gffid_event(vha, ea);
1246 break;
726b8548
QT		 1247 case FCME_DELETE_DONE:
1248 qla24xx_handle_delete_done_event(vha, ea);
1249 break;
1250 default:
1251 BUG_ON(1);
1252 break;
1253 }
5ff1d584
AV		 1254}
1255
3822263e 1256static void
faef62d1 1257qla2x00_tmf_iocb_timeout(void *data)
3822263e 1258{
25ff6af1 1259 srb_t *sp = data;
faef62d1 1260 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1261
faef62d1
AB		 1262 tmf->u.tmf.comp_status = CS_TIMEOUT;
1263 complete(&tmf->u.tmf.comp);
1264}
9ba56b95 1265
faef62d1 1266static void
25ff6af1 1267qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1268{
25ff6af1 1269 srb_t *sp = ptr;
faef62d1 1270 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1271
faef62d1 1272 complete(&tmf->u.tmf.comp);
3822263e
MI		 1273}
1274
1275int
faef62d1 1276qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1277 uint32_t tag)
1278{
1279 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1280 struct srb_iocb *tm_iocb;
3822263e 1281 srb_t *sp;
faef62d1 1282 int rval = QLA_FUNCTION_FAILED;
3822263e 1283
9ba56b95 1284 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1285 if (!sp)
1286 goto done;
1287
faef62d1 1288 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1289 sp->type = SRB_TM_CMD;
1290 sp->name = "tmf";
faef62d1
AB		 1291 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1292 tm_iocb->u.tmf.flags = flags;
1293 tm_iocb->u.tmf.lun = lun;
1294 tm_iocb->u.tmf.data = tag;
1295 sp->done = qla2x00_tmf_sp_done;
1296 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1297 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 1298
1299 rval = qla2x00_start_sp(sp);
1300 if (rval != QLA_SUCCESS)
1301 goto done_free_sp;
1302
7c3df132 1303 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1304 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1305 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1306 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1307
1308 wait_for_completion(&tm_iocb->u.tmf.comp);
1309
1310 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
1311 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1312
1313 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
1314 ql_dbg(ql_dbg_taskm, vha, 0x8030,
1315 "TM IOCB failed (%x).\n", rval);
1316 }
1317
1318 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1319 flags = tm_iocb->u.tmf.flags;
1320 lun = (uint16_t)tm_iocb->u.tmf.lun;
1321
1322 /* Issue Marker IOCB */
1323 qla2x00_marker(vha, vha->hw->req_q_map[0],
1324 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1325 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1326 }
3822263e
MI		 1327
1328done_free_sp:
25ff6af1 1329 sp->free(sp);
3822263e
MI		 1330done:
1331 return rval;
1332}
1333
4440e46d
AB		 1334static void
1335qla24xx_abort_iocb_timeout(void *data)
1336{
25ff6af1 1337 srb_t *sp = data;
4440e46d
AB		 1338 struct srb_iocb *abt = &sp->u.iocb_cmd;
1339
1340 abt->u.abt.comp_status = CS_TIMEOUT;
1341 complete(&abt->u.abt.comp);
1342}
1343
1344static void
25ff6af1 1345qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1346{
25ff6af1 1347 srb_t *sp = ptr;
4440e46d
AB		 1348 struct srb_iocb *abt = &sp->u.iocb_cmd;
1349
1350 complete(&abt->u.abt.comp);
1351}
1352
15f30a57 1353int
4440e46d
AB		 1354qla24xx_async_abort_cmd(srb_t *cmd_sp)
1355{
25ff6af1 1356 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1357 fc_port_t *fcport = cmd_sp->fcport;
1358 struct srb_iocb *abt_iocb;
1359 srb_t *sp;
1360 int rval = QLA_FUNCTION_FAILED;
1361
1362 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1363 if (!sp)
1364 goto done;
1365
1366 abt_iocb = &sp->u.iocb_cmd;
1367 sp->type = SRB_ABT_CMD;
1368 sp->name = "abort";
1369 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1370 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
1371 sp->done = qla24xx_abort_sp_done;
1372 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1373 init_completion(&abt_iocb->u.abt.comp);
1374
1375 rval = qla2x00_start_sp(sp);
1376 if (rval != QLA_SUCCESS)
1377 goto done_free_sp;
1378
1379 ql_dbg(ql_dbg_async, vha, 0x507c,
1380 "Abort command issued - hdl=%x, target_id=%x\n",
1381 cmd_sp->handle, fcport->tgt_id);
1382
1383 wait_for_completion(&abt_iocb->u.abt.comp);
1384
1385 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1386 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1387
1388done_free_sp:
25ff6af1 1389 sp->free(sp);
4440e46d
AB		 1390done:
1391 return rval;
1392}
1393
1394int
1395qla24xx_async_abort_command(srb_t *sp)
1396{
1397 unsigned long flags = 0;
1398
1399 uint32_t handle;
1400 fc_port_t *fcport = sp->fcport;
1401 struct scsi_qla_host *vha = fcport->vha;
1402 struct qla_hw_data *ha = vha->hw;
1403 struct req_que *req = vha->req;
1404
1405 spin_lock_irqsave(&ha->hardware_lock, flags);
1406 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1407 if (req->outstanding_cmds[handle] == sp)
1408 break;
1409 }
1410 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1411 if (handle == req->num_outstanding_cmds) {
1412 /* Command not found. */
1413 return QLA_FUNCTION_FAILED;
1414 }
1415 if (sp->type == SRB_FXIOCB_DCMD)
1416 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1417 FXDISC_ABORT_IOCTL);
1418
1419 return qla24xx_async_abort_cmd(sp);
1420}
1421
a5d42f4c
DG		 1422static void
1423qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1424{
1425 switch (ea->data[0]) {
1426 case MBS_COMMAND_COMPLETE:
1427 ql_dbg(ql_dbg_disc, vha, 0x2118,
1428 "%s %d %8phC post gpdb\n",
1429 __func__, __LINE__, ea->fcport->port_name);
1430
1431 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1432 ea->fcport->logout_on_delete = 1;
1433 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1434 break;
1435 default:
edd05de1
DG		 1436 if (ea->fcport->n2n_flag) {
1437 ql_dbg(ql_dbg_disc, vha, 0x2118,
1438 "%s %d %8phC post fc4 prli\n",
1439 __func__, __LINE__, ea->fcport->port_name);
1440 ea->fcport->fc4f_nvme = 0;
1441 ea->fcport->n2n_flag = 0;
1442 qla24xx_post_prli_work(vha, ea->fcport);
1443 }
a5d42f4c
DG		 1444 ql_dbg(ql_dbg_disc, vha, 0x2119,
1445 "%s %d %8phC unhandle event of %x\n",
1446 __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
1447 break;
1448 }
1449}
1450
726b8548
QT		 1451static void
1452qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1453{
726b8548 1454 port_id_t cid; /* conflict Nport id */
a084fd68
QT		 1455 u16 lid;
1456 struct fc_port *conflict_fcport;
ac280b67 1457
726b8548 1458 switch (ea->data[0]) {
ac280b67 1459 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1460 /*
1461 * Driver must validate login state - If PRLI not complete,
1462 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1463 * requests.
1464 */
a5d42f4c
DG		 1465 if (ea->fcport->fc4f_nvme) {
1466 ql_dbg(ql_dbg_disc, vha, 0x2117,
1467 "%s %d %8phC post prli\n",
1468 __func__, __LINE__, ea->fcport->port_name);
1469 qla24xx_post_prli_work(vha, ea->fcport);
1470 } else {
1471 ql_dbg(ql_dbg_disc, vha, 0x20ea,
a084fd68
QT		 1472 "%s %d %8phC LoopID 0x%x in use with %06x. post gnl\n",
1473 __func__, __LINE__, ea->fcport->port_name,
1474 ea->fcport->loop_id, ea->fcport->d_id.b24);
1475
1476 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1477 ea->fcport->loop_id = FC_NO_LOOP_ID;
a5d42f4c
DG		 1478 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1479 ea->fcport->logout_on_delete = 1;
3515832c 1480 ea->fcport->send_els_logo = 0;
a5d42f4c
DG		 1481 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1482 }
ac280b67
AV		 1483 break;
1484 case MBS_COMMAND_ERROR:
83548fe2 1485 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
726b8548
QT		 1486 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1487
1488 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1489 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1490 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1491 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1492 else
726b8548 1493 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1494 break;
1495 case MBS_LOOP_ID_USED:
726b8548
QT		 1496 /* data[1] = IO PARAM 1 = nport ID */
1497 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1498 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1499 cid.b.al_pa = ea->iop[1] & 0xff;
1500 cid.b.rsvd_1 = 0;
1501
83548fe2
QT		 1502 ql_dbg(ql_dbg_disc, vha, 0x20ec,
1503 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1504 __func__, __LINE__, ea->fcport->port_name,
1505 ea->fcport->loop_id);
726b8548
QT		 1506
1507 if (IS_SW_RESV_ADDR(cid)) {
1508 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1509 ea->fcport->loop_id = FC_NO_LOOP_ID;
1510 } else {
1511 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1512 }
726b8548
QT		 1513 qla24xx_post_gnl_work(vha, ea->fcport);
1514 break;
1515 case MBS_PORT_ID_USED:
83548fe2
QT		 1516 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1517 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1518 __func__, __LINE__, ea->fcport->port_name,
1519 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1520 ea->fcport->d_id.b.al_pa);
726b8548 1521
a084fd68
QT		 1522 lid = ea->iop[1] & 0xffff;
1523 qlt_find_sess_invalidate_other(vha,
1524 wwn_to_u64(ea->fcport->port_name),
1525 ea->fcport->d_id, lid, &conflict_fcport);
1526
1527 if (conflict_fcport) {
1528 /*
1529 * Another fcport share the same loop_id/nport id.
1530 * Conflict fcport needs to finish cleanup before this
1531 * fcport can proceed to login.
1532 */
1533 conflict_fcport->conflict = ea->fcport;
1534 ea->fcport->login_pause = 1;
1535
1536 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1537 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
1538 __func__, __LINE__, ea->fcport->port_name,
1539 ea->fcport->d_id.b24, lid);
1540 qla2x00_clear_loop_id(ea->fcport);
1541 qla24xx_post_gidpn_work(vha, ea->fcport);
1542 } else {
1543 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1544 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
1545 __func__, __LINE__, ea->fcport->port_name,
1546 ea->fcport->d_id.b24, lid);
1547
1548 qla2x00_clear_loop_id(ea->fcport);
1549 set_bit(lid, vha->hw->loop_id_map);
1550 ea->fcport->loop_id = lid;
1551 ea->fcport->keep_nport_handle = 0;
1552 qlt_schedule_sess_for_deletion(ea->fcport, false);
1553 }
ac280b67
AV		 1554 break;
1555 }
4916392b 1556 return;
ac280b67
AV		 1557}
1558
4916392b 1559void
ac280b67
AV		 1560qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1561 uint16_t *data)
1562{
726b8548 1563 qla2x00_mark_device_lost(vha, fcport, 1, 0);
a6ca8878 1564 qlt_logo_completion_handler(fcport, data[0]);
726b8548 1565 fcport->login_gen++;
4916392b 1566 return;
ac280b67
AV		 1567}
1568
4916392b 1569void
5ff1d584
AV		 1570qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1571 uint16_t *data)
1572{
1573 if (data[0] == MBS_COMMAND_COMPLETE) {
1574 qla2x00_update_fcport(vha, fcport);
1575
4916392b 1576 return;
5ff1d584
AV		 1577 }
1578
1579 /* Retry login. */
1580 fcport->flags &= ~FCF_ASYNC_SENT;
1581 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
1582 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1583 else
80d79440 1584 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 1585
4916392b 1586 return;
5ff1d584
AV		 1587}
1588
1da177e4
LT		 1589/****************************************************************************/
1590/* QLogic ISP2x00 Hardware Support Functions. */
1591/****************************************************************************/
1592
fa492630 1593static int
7d613ac6
SV		 1594qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
1595{
1596 int rval = QLA_SUCCESS;
1597 struct qla_hw_data *ha = vha->hw;
1598 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 1599 uint16_t config[4];
7d613ac6
SV		 1600
1601 qla83xx_idc_lock(vha, 0);
1602
1603 /* SV: TODO: Assign initialization timeout from
1604 * flash-info / other param
1605 */
1606 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
1607 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
1608
1609 /* Set our fcoe function presence */
1610 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
1611 ql_dbg(ql_dbg_p3p, vha, 0xb077,
1612 "Error while setting DRV-Presence.\n");
1613 rval = QLA_FUNCTION_FAILED;
1614 goto exit;
1615 }
1616
1617 /* Decide the reset ownership */
1618 qla83xx_reset_ownership(vha);
1619
1620 /*
1621 * On first protocol driver load:
1622 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
1623 * register.
1624 * Others: Check compatibility with current IDC Major version.
1625 */
1626 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
1627 if (ha->flags.nic_core_reset_owner) {
1628 /* Set IDC Major version */
1629 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
1630 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
1631
1632 /* Clearing IDC-Lock-Recovery register */
1633 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
1634 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
1635 /*
1636 * Clear further IDC participation if we are not compatible with
1637 * the current IDC Major Version.
1638 */
1639 ql_log(ql_log_warn, vha, 0xb07d,
1640 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
1641 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
1642 __qla83xx_clear_drv_presence(vha);
1643 rval = QLA_FUNCTION_FAILED;
1644 goto exit;
1645 }
1646 /* Each function sets its supported Minor version. */
1647 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
1648 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
1649 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
1650
711aa7f7
SK		 1651 if (ha->flags.nic_core_reset_owner) {
1652 memset(config, 0, sizeof(config));
1653 if (!qla81xx_get_port_config(vha, config))
1654 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
1655 QLA8XXX_DEV_READY);
1656 }
1657
7d613ac6
SV		 1658 rval = qla83xx_idc_state_handler(vha);
1659
1660exit:
1661 qla83xx_idc_unlock(vha, 0);
1662
1663 return rval;
1664}
1665
1da177e4
LT		 1666/*
1667* qla2x00_initialize_adapter
1668* Initialize board.
1669*
1670* Input:
1671* ha = adapter block pointer.
1672*
1673* Returns:
1674* 0 = success
1675*/
1676int
e315cd28 1677qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 1678{
1679 int rval;
e315cd28 1680 struct qla_hw_data *ha = vha->hw;
73208dfd 1681 struct req_que *req = ha->req_q_map[0];
2533cf67 1682
fc90adaf
JC		 1683 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
1684 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
1685
1da177e4 1686 /* Clear adapter flags. */
e315cd28 1687 vha->flags.online = 0;
2533cf67 1688 ha->flags.chip_reset_done = 0;
e315cd28 1689 vha->flags.reset_active = 0;
85880801
AV		 1690 ha->flags.pci_channel_io_perm_failure = 0;
1691 ha->flags.eeh_busy = 0;
fabbb8df 1692 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 1693 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1694 atomic_set(&vha->loop_state, LOOP_DOWN);
1695 vha->device_flags = DFLG_NO_CABLE;
1696 vha->dpc_flags = 0;
1697 vha->flags.management_server_logged_in = 0;
1698 vha->marker_needed = 0;
1da177e4
LT		 1699 ha->isp_abort_cnt = 0;
1700 ha->beacon_blink_led = 0;
1701
73208dfd
AC		 1702 set_bit(0, ha->req_qid_map);
1703 set_bit(0, ha->rsp_qid_map);
1704
cfb0919c 1705 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 1706 "Configuring PCI space...\n");
e315cd28 1707 rval = ha->isp_ops->pci_config(vha);
1da177e4 1708 if (rval) {
7c3df132
SK		 1709 ql_log(ql_log_warn, vha, 0x0044,
1710 "Unable to configure PCI space.\n");
1da177e4
LT		 1711 return (rval);
1712 }
1713
e315cd28 1714 ha->isp_ops->reset_chip(vha);
1da177e4 1715
e315cd28 1716 rval = qla2xxx_get_flash_info(vha);
c00d8994 1717 if (rval) {
7c3df132
SK		 1718 ql_log(ql_log_fatal, vha, 0x004f,
1719 "Unable to validate FLASH data.\n");
7ec0effd
AD		 1720 return rval;
1721 }
1722
1723 if (IS_QLA8044(ha)) {
1724 qla8044_read_reset_template(vha);
1725
1726 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
1727 * If DONRESET_BIT0 is set, drivers should not set dev_state
1728 * to NEED_RESET. But if NEED_RESET is set, drivers should
1729 * should honor the reset. */
1730 if (ql2xdontresethba == 1)
1731 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 1732 }
1733
73208dfd 1734 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 1735 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 1736 "Configure NVRAM parameters...\n");
0107109e 1737
e315cd28 1738 ha->isp_ops->nvram_config(vha);
1da177e4 1739
d4c760c2
AV		 1740 if (ha->flags.disable_serdes) {
1741 /* Mask HBA via NVRAM settings? */
7c3df132 1742 ql_log(ql_log_info, vha, 0x0077,
7b833558 1743 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 1744 return QLA_FUNCTION_FAILED;
1745 }
1746
cfb0919c 1747 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 1748 "Verifying loaded RISC code...\n");
1da177e4 1749
e315cd28
AC		 1750 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
1751 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 1752 if (rval)
1753 return (rval);
e315cd28 1754 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 1755 if (rval)
1756 return (rval);
1da177e4 1757 }
a9083016 1758
4d4df193 1759 if (IS_QLA84XX(ha)) {
e315cd28 1760 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 1761 if (!ha->cs84xx) {
7c3df132 1762 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 1763 "Unable to configure ISP84XX.\n");
1764 return QLA_FUNCTION_FAILED;
1765 }
1766 }
2d70c103 1767
ead03855 1768 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 1769 rval = qla2x00_init_rings(vha);
1770
2533cf67 1771 ha->flags.chip_reset_done = 1;
1da177e4 1772
9a069e19 1773 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 1774 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 1775 rval = qla84xx_init_chip(vha);
1776 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1777 ql_log(ql_log_warn, vha, 0x00d4,
1778 "Unable to initialize ISP84XX.\n");
8d2b21db 1779 qla84xx_put_chip(vha);
9a069e19
GM		 1780 }
1781 }
1782
7d613ac6
SV		 1783 /* Load the NIC Core f/w if we are the first protocol driver. */
1784 if (IS_QLA8031(ha)) {
1785 rval = qla83xx_nic_core_fw_load(vha);
1786 if (rval)
1787 ql_log(ql_log_warn, vha, 0x0124,
1788 "Error in initializing NIC Core f/w.\n");
1789 }
1790
2f0f3f4f
MI		 1791 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
1792 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 1793
c46e65c7
JC		 1794 if (IS_P3P_TYPE(ha))
1795 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
1796 else
1797 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
1798
1da177e4
LT		 1799 return (rval);
1800}
1801
1802/**
abbd8870 1803 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 1804 * @ha: HA context
1805 *
1806 * Returns 0 on success.
1807 */
abbd8870 1808int
e315cd28 1809qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 1810{
a157b101 1811 uint16_t w;
abbd8870 1812 unsigned long flags;
e315cd28 1813 struct qla_hw_data *ha = vha->hw;
3d71644c 1814 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1815
1da177e4 1816 pci_set_master(ha->pdev);
af6177d8 1817 pci_try_set_mwi(ha->pdev);
1da177e4 1818
1da177e4 1819 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1820 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 1821 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1822
737faece 1823 pci_disable_rom(ha->pdev);
1da177e4
LT		 1824
1825 /* Get PCI bus information. */
1826 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1827 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 1828 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1829
abbd8870
AV		 1830 return QLA_SUCCESS;
1831}
1da177e4 1832
abbd8870
AV		 1833/**
1834 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
1835 * @ha: HA context
1836 *
1837 * Returns 0 on success.
1838 */
1839int
e315cd28 1840qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 1841{
a157b101 1842 uint16_t w;
abbd8870
AV		 1843 unsigned long flags = 0;
1844 uint32_t cnt;
e315cd28 1845 struct qla_hw_data *ha = vha->hw;
3d71644c 1846 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1847
abbd8870 1848 pci_set_master(ha->pdev);
af6177d8 1849 pci_try_set_mwi(ha->pdev);
1da177e4 1850
abbd8870 1851 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1852 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 1853
abbd8870
AV		 1854 if (IS_QLA2322(ha) || IS_QLA6322(ha))
1855 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 1856 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 1857
abbd8870
AV		 1858 /*
1859 * If this is a 2300 card and not 2312, reset the
1860 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
1861 * the 2310 also reports itself as a 2300 so we need to get the
1862 * fb revision level -- a 6 indicates it really is a 2300 and
1863 * not a 2310.
1864 */
1865 if (IS_QLA2300(ha)) {
1866 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1867
abbd8870 1868 /* Pause RISC. */
3d71644c 1869 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 1870 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1871 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 1872 break;
1da177e4 1873
abbd8870
AV		 1874 udelay(10);
1875 }
1da177e4 1876
abbd8870 1877 /* Select FPM registers. */
3d71644c
AV		 1878 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1879 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1880
1881 /* Get the fb rev level */
3d71644c 1882 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 1883
1884 if (ha->fb_rev == FPM_2300)
a157b101 1885 pci_clear_mwi(ha->pdev);
abbd8870
AV		 1886
1887 /* Deselect FPM registers. */
3d71644c
AV		 1888 WRT_REG_WORD(&reg->ctrl_status, 0x0);
1889 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1890
1891 /* Release RISC module. */
3d71644c 1892 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 1893 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1894 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 1895 break;
1896
1897 udelay(10);
1da177e4 1898 }
1da177e4 1899
abbd8870
AV		 1900 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1901 }
1da177e4 1902
abbd8870
AV		 1903 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1904
737faece 1905 pci_disable_rom(ha->pdev);
1da177e4 1906
abbd8870
AV		 1907 /* Get PCI bus information. */
1908 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1909 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1910 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1911
1912 return QLA_SUCCESS;
1da177e4
LT		 1913}
1914
0107109e
AV		 1915/**
1916 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
1917 * @ha: HA context
1918 *
1919 * Returns 0 on success.
1920 */
1921int
e315cd28 1922qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 1923{
a157b101 1924 uint16_t w;
0107109e 1925 unsigned long flags = 0;
e315cd28 1926 struct qla_hw_data *ha = vha->hw;
0107109e 1927 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 1928
1929 pci_set_master(ha->pdev);
af6177d8 1930 pci_try_set_mwi(ha->pdev);
0107109e
AV		 1931
1932 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1933 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 1934 w &= ~PCI_COMMAND_INTX_DISABLE;
1935 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1936
1937 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1938
1939 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 1940 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
1941 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 1942
1943 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1944 if (pci_is_pcie(ha->pdev))
5ffd3a52 1945 pcie_set_readrq(ha->pdev, 4096);
0107109e 1946
737faece 1947 pci_disable_rom(ha->pdev);
0107109e 1948
44c10138 1949 ha->chip_revision = ha->pdev->revision;
a8488abe 1950
0107109e
AV		 1951 /* Get PCI bus information. */
1952 spin_lock_irqsave(&ha->hardware_lock, flags);
1953 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
1954 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1955
1956 return QLA_SUCCESS;
1957}
1958
c3a2f0df
AV		 1959/**
1960 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
1961 * @ha: HA context
1962 *
1963 * Returns 0 on success.
1964 */
1965int
e315cd28 1966qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 1967{
1968 uint16_t w;
e315cd28 1969 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1970
1971 pci_set_master(ha->pdev);
1972 pci_try_set_mwi(ha->pdev);
1973
1974 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
1975 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1976 w &= ~PCI_COMMAND_INTX_DISABLE;
1977 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1978
1979 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1980 if (pci_is_pcie(ha->pdev))
5ffd3a52 1981 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 1982
737faece 1983 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 1984
1985 ha->chip_revision = ha->pdev->revision;
1986
1987 return QLA_SUCCESS;
1988}
1989
1da177e4
LT		 1990/**
1991 * qla2x00_isp_firmware() - Choose firmware image.
1992 * @ha: HA context
1993 *
1994 * Returns 0 on success.
1995 */
1996static int
e315cd28 1997qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 1998{
1999 int rval;
42e421b1
AV		 2000 uint16_t loop_id, topo, sw_cap;
2001 uint8_t domain, area, al_pa;
e315cd28 2002 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2003
2004 /* Assume loading risc code */
fa2a1ce5 2005 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 2006
2007 if (ha->flags.disable_risc_code_load) {
7c3df132 2008 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 2009
2010 /* Verify checksum of loaded RISC code. */
e315cd28 2011 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 2012 if (rval == QLA_SUCCESS) {
2013 /* And, verify we are not in ROM code. */
e315cd28 2014 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 2015 &area, &domain, &topo, &sw_cap);
2016 }
1da177e4
LT		 2017 }
2018
7c3df132
SK		 2019 if (rval)
2020 ql_dbg(ql_dbg_init, vha, 0x007a,
2021 "**** Load RISC code ****.\n");
1da177e4
LT		 2022
2023 return (rval);
2024}
2025
2026/**
2027 * qla2x00_reset_chip() - Reset ISP chip.
2028 * @ha: HA context
2029 *
2030 * Returns 0 on success.
2031 */
abbd8870 2032void
e315cd28 2033qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 2034{
2035 unsigned long flags = 0;
e315cd28 2036 struct qla_hw_data *ha = vha->hw;
3d71644c 2037 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2038 uint32_t cnt;
1da177e4
LT		 2039 uint16_t cmd;
2040
85880801
AV		 2041 if (unlikely(pci_channel_offline(ha->pdev)))
2042 return;
2043
fd34f556 2044 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 2045
2046 spin_lock_irqsave(&ha->hardware_lock, flags);
2047
2048 /* Turn off master enable */
2049 cmd = 0;
2050 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2051 cmd &= ~PCI_COMMAND_MASTER;
2052 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2053
2054 if (!IS_QLA2100(ha)) {
2055 /* Pause RISC. */
2056 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2057 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2058 for (cnt = 0; cnt < 30000; cnt++) {
2059 if ((RD_REG_WORD(&reg->hccr) &
2060 HCCR_RISC_PAUSE) != 0)
2061 break;
2062 udelay(100);
2063 }
2064 } else {
2065 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2066 udelay(10);
2067 }
2068
2069 /* Select FPM registers. */
2070 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2071 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2072
2073 /* FPM Soft Reset. */
2074 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
2075 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2076
2077 /* Toggle Fpm Reset. */
2078 if (!IS_QLA2200(ha)) {
2079 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
2080 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2081 }
2082
2083 /* Select frame buffer registers. */
2084 WRT_REG_WORD(&reg->ctrl_status, 0x10);
2085 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2086
2087 /* Reset frame buffer FIFOs. */
2088 if (IS_QLA2200(ha)) {
2089 WRT_FB_CMD_REG(ha, reg, 0xa000);
2090 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2091 } else {
2092 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2093
2094 /* Read back fb_cmd until zero or 3 seconds max */
2095 for (cnt = 0; cnt < 3000; cnt++) {
2096 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2097 break;
2098 udelay(100);
2099 }
2100 }
2101
2102 /* Select RISC module registers. */
2103 WRT_REG_WORD(&reg->ctrl_status, 0);
2104 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2105
2106 /* Reset RISC processor. */
2107 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2108 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2109
2110 /* Release RISC processor. */
2111 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2112 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2113 }
2114
2115 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
2116 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
2117
2118 /* Reset ISP chip. */
2119 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2120
2121 /* Wait for RISC to recover from reset. */
2122 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2123 /*
2124 * It is necessary to for a delay here since the card doesn't
2125 * respond to PCI reads during a reset. On some architectures
2126 * this will result in an MCA.
2127 */
2128 udelay(20);
2129 for (cnt = 30000; cnt; cnt--) {
2130 if ((RD_REG_WORD(&reg->ctrl_status) &
2131 CSR_ISP_SOFT_RESET) == 0)
2132 break;
2133 udelay(100);
2134 }
2135 } else
2136 udelay(10);
2137
2138 /* Reset RISC processor. */
2139 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2140
2141 WRT_REG_WORD(&reg->semaphore, 0);
2142
2143 /* Release RISC processor. */
2144 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2145 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2146
2147 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2148 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 2149 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 2150 break;
1da177e4
LT		 2151
2152 udelay(100);
2153 }
2154 } else
2155 udelay(100);
2156
2157 /* Turn on master enable */
2158 cmd |= PCI_COMMAND_MASTER;
2159 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2160
2161 /* Disable RISC pause on FPM parity error. */
2162 if (!IS_QLA2100(ha)) {
2163 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2164 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2165 }
2166
2167 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2168}
2169
b1d46989
MI		 2170/**
2171 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2172 *
2173 * Returns 0 on success.
2174 */
fa492630 2175static int
b1d46989
MI		 2176qla81xx_reset_mpi(scsi_qla_host_t *vha)
2177{
2178 uint16_t mb[4] = {0x1010, 0, 1, 0};
2179
6246b8a1
GM		 2180 if (!IS_QLA81XX(vha->hw))
2181 return QLA_SUCCESS;
2182
b1d46989
MI		 2183 return qla81xx_write_mpi_register(vha, mb);
2184}
2185
0107109e 2186/**
88c26663 2187 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 2188 * @ha: HA context
2189 *
2190 * Returns 0 on success.
2191 */
d14e72fb 2192static inline int
e315cd28 2193qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2194{
2195 unsigned long flags = 0;
e315cd28 2196 struct qla_hw_data *ha = vha->hw;
0107109e 2197 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2198 uint32_t cnt;
335a1cc9 2199 uint16_t wd;
b1d46989 2200 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2201 int rval = QLA_SUCCESS;
0107109e 2202
0107109e
AV		 2203 spin_lock_irqsave(&ha->hardware_lock, flags);
2204
2205 /* Reset RISC. */
2206 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2207 for (cnt = 0; cnt < 30000; cnt++) {
2208 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2209 break;
2210
2211 udelay(10);
2212 }
2213
d14e72fb
HM		 2214 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2215 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2216
2217 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2218 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2219 RD_REG_DWORD(&reg->hccr),
2220 RD_REG_DWORD(&reg->ctrl_status),
2221 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2222
0107109e
AV		 2223 WRT_REG_DWORD(&reg->ctrl_status,
2224 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2225 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2226
335a1cc9 2227 udelay(100);
d14e72fb 2228
88c26663 2229 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2230 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2231 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2232 rval == QLA_SUCCESS; cnt--) {
88c26663 2233 barrier();
d14e72fb
HM		 2234 if (cnt)
2235 udelay(5);
2236 else
2237 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2238 }
2239
d14e72fb
HM		 2240 if (rval == QLA_SUCCESS)
2241 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2242
2243 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2244 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2245 RD_REG_DWORD(&reg->hccr),
2246 RD_REG_DWORD(&reg->mailbox0));
2247
335a1cc9 2248 /* Wait for soft-reset to complete. */
52c82823 2249 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2250 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2251 barrier();
d14e72fb
HM		 2252 if ((RD_REG_DWORD(&reg->ctrl_status) &
2253 CSRX_ISP_SOFT_RESET) == 0)
2254 break;
2255
2256 udelay(5);
0107109e 2257 }
d14e72fb
HM		 2258 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2259 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2260
2261 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2262 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2263 RD_REG_DWORD(&reg->hccr),
2264 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2265
b1d46989
MI		 2266 /* If required, do an MPI FW reset now */
2267 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2268 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2269 if (++abts_cnt < 5) {
2270 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2271 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2272 } else {
2273 /*
2274 * We exhausted the ISP abort retries. We have to
2275 * set the board offline.
2276 */
2277 abts_cnt = 0;
2278 vha->flags.online = 0;
2279 }
2280 }
2281 }
2282
0107109e
AV		 2283 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2284 RD_REG_DWORD(&reg->hccr);
2285
2286 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2287 RD_REG_DWORD(&reg->hccr);
2288
2289 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2290 RD_REG_DWORD(&reg->hccr);
2291
52c82823 2292 RD_REG_WORD(&reg->mailbox0);
200ffb15 2293 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2294 rval == QLA_SUCCESS; cnt--) {
0107109e 2295 barrier();
d14e72fb
HM		 2296 if (cnt)
2297 udelay(5);
2298 else
2299 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2300 }
d14e72fb
HM		 2301 if (rval == QLA_SUCCESS)
2302 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2303
2304 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2305 "Host Risc 0x%x, mailbox0 0x%x\n",
2306 RD_REG_DWORD(&reg->hccr),
2307 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2308
2309 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2310
d14e72fb
HM		 2311 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2312 "Driver in %s mode\n",
2313 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2314
124f85e6
AV		 2315 if (IS_NOPOLLING_TYPE(ha))
2316 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2317
2318 return rval;
0107109e
AV		 2319}
2320
4ea2c9c7
JC		 2321static void
2322qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2323{
2324 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2325
2326 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2327 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2328
2329}
2330
2331static void
2332qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2333{
2334 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2335
2336 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2337 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2338}
2339
2340static void
2341qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2342{
4ea2c9c7
JC		 2343 uint32_t wd32 = 0;
2344 uint delta_msec = 100;
2345 uint elapsed_msec = 0;
2346 uint timeout_msec;
2347 ulong n;
2348
cc790764
JC		 2349 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2350 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2351 return;
2352
8dd7e3a5
JC		 2353 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2354 udelay(100);
2355
4ea2c9c7
JC		 2356attempt:
2357 timeout_msec = TIMEOUT_SEMAPHORE;
2358 n = timeout_msec / delta_msec;
2359 while (n--) {
2360 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2361 qla25xx_read_risc_sema_reg(vha, &wd32);
2362 if (wd32 & RISC_SEMAPHORE)
2363 break;
2364 msleep(delta_msec);
2365 elapsed_msec += delta_msec;
2366 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2367 goto force;
2368 }
2369
2370 if (!(wd32 & RISC_SEMAPHORE))
2371 goto force;
2372
2373 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2374 goto acquired;
2375
2376 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2377 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2378 n = timeout_msec / delta_msec;
2379 while (n--) {
2380 qla25xx_read_risc_sema_reg(vha, &wd32);
2381 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2382 break;
2383 msleep(delta_msec);
2384 elapsed_msec += delta_msec;
2385 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2386 goto force;
2387 }
2388
2389 if (wd32 & RISC_SEMAPHORE_FORCE)
2390 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2391
2392 goto attempt;
2393
2394force:
2395 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2396
2397acquired:
2398 return;
2399}
2400
88c26663
AV		 2401/**
2402 * qla24xx_reset_chip() - Reset ISP24xx chip.
2403 * @ha: HA context
2404 *
2405 * Returns 0 on success.
2406 */
2407void
e315cd28 2408qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2409{
e315cd28 2410 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2411
2412 if (pci_channel_offline(ha->pdev) &&
2413 ha->flags.pci_channel_io_perm_failure) {
2414 return;
2415 }
2416
fd34f556 2417 ha->isp_ops->disable_intrs(ha);
88c26663 2418
4ea2c9c7
JC		 2419 qla25xx_manipulate_risc_semaphore(vha);
2420
88c26663 2421 /* Perform RISC reset. */
e315cd28 2422 qla24xx_reset_risc(vha);
88c26663
AV		 2423}
2424
1da177e4
LT		 2425/**
2426 * qla2x00_chip_diag() - Test chip for proper operation.
2427 * @ha: HA context
2428 *
2429 * Returns 0 on success.
2430 */
abbd8870 2431int
e315cd28 2432qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2433{
2434 int rval;
e315cd28 2435 struct qla_hw_data *ha = vha->hw;
3d71644c 2436 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2437 unsigned long flags = 0;
2438 uint16_t data;
2439 uint32_t cnt;
2440 uint16_t mb[5];
73208dfd 2441 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2442
2443 /* Assume a failed state */
2444 rval = QLA_FUNCTION_FAILED;
2445
7c3df132
SK		 2446 ql_dbg(ql_dbg_init, vha, 0x007b,
2447 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 2448
2449 spin_lock_irqsave(&ha->hardware_lock, flags);
2450
2451 /* Reset ISP chip. */
2452 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2453
2454 /*
2455 * We need to have a delay here since the card will not respond while
2456 * in reset causing an MCA on some architectures.
2457 */
2458 udelay(20);
2459 data = qla2x00_debounce_register(&reg->ctrl_status);
2460 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2461 udelay(5);
2462 data = RD_REG_WORD(&reg->ctrl_status);
2463 barrier();
2464 }
2465
2466 if (!cnt)
2467 goto chip_diag_failed;
2468
7c3df132
SK		 2469 ql_dbg(ql_dbg_init, vha, 0x007c,
2470 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2471
2472 /* Reset RISC processor. */
2473 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2474 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2475
2476 /* Workaround for QLA2312 PCI parity error */
2477 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2478 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2479 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2480 udelay(5);
2481 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2482 barrier();
1da177e4
LT		 2483 }
2484 } else
2485 udelay(10);
2486
2487 if (!cnt)
2488 goto chip_diag_failed;
2489
2490 /* Check product ID of chip */
5a68a1c2 2491 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 2492
2493 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2494 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2495 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2496 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2497 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2498 mb[3] != PROD_ID_3) {
7c3df132
SK		 2499 ql_log(ql_log_warn, vha, 0x0062,
2500 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2501 mb[1], mb[2], mb[3]);
1da177e4
LT		 2502
2503 goto chip_diag_failed;
2504 }
2505 ha->product_id[0] = mb[1];
2506 ha->product_id[1] = mb[2];
2507 ha->product_id[2] = mb[3];
2508 ha->product_id[3] = mb[4];
2509
2510 /* Adjust fw RISC transfer size */
73208dfd 2511 if (req->length > 1024)
1da177e4
LT		 2512 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2513 else
2514 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2515 req->length;
1da177e4
LT		 2516
2517 if (IS_QLA2200(ha) &&
2518 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2519 /* Limit firmware transfer size with a 2200A */
7c3df132 2520 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2521
ea5b6382 2522 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2523 ha->fw_transfer_size = 128;
2524 }
2525
2526 /* Wrap Incoming Mailboxes Test. */
2527 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2528
7c3df132 2529 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2530 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2531 if (rval)
2532 ql_log(ql_log_warn, vha, 0x0080,
2533 "Failed mailbox send register test.\n");
2534 else
1da177e4
LT		 2535 /* Flag a successful rval */
2536 rval = QLA_SUCCESS;
1da177e4
LT		 2537 spin_lock_irqsave(&ha->hardware_lock, flags);
2538
2539chip_diag_failed:
2540 if (rval)
7c3df132
SK		 2541 ql_log(ql_log_info, vha, 0x0081,
2542 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 2543
2544 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2545
2546 return (rval);
2547}
2548
0107109e
AV		 2549/**
2550 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2551 * @ha: HA context
2552 *
2553 * Returns 0 on success.
2554 */
2555int
e315cd28 2556qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 2557{
2558 int rval;
e315cd28 2559 struct qla_hw_data *ha = vha->hw;
73208dfd 2560 struct req_que *req = ha->req_q_map[0];
0107109e 2561
7ec0effd 2562 if (IS_P3P_TYPE(ha))
a9083016
GM		 2563 return QLA_SUCCESS;
2564
73208dfd 2565 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 2566
e315cd28 2567 rval = qla2x00_mbx_reg_test(vha);
0107109e 2568 if (rval) {
7c3df132
SK		 2569 ql_log(ql_log_warn, vha, 0x0082,
2570 "Failed mailbox send register test.\n");
0107109e
AV		 2571 } else {
2572 /* Flag a successful rval */
2573 rval = QLA_SUCCESS;
2574 }
2575
2576 return rval;
2577}
2578
a7a167bf 2579void
e315cd28 2580qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 2581{
a7a167bf
AV		 2582 int rval;
2583 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 2584 eft_size, fce_size, mq_size;
df613b96
AV		 2585 dma_addr_t tc_dma;
2586 void *tc;
e315cd28 2587 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2588 struct req_que *req = ha->req_q_map[0];
2589 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 2590
2591 if (ha->fw_dump) {
7c3df132
SK		 2592 ql_dbg(ql_dbg_init, vha, 0x00bd,
2593 "Firmware dump already allocated.\n");
a7a167bf
AV		 2594 return;
2595 }
d4e3e04d 2596
0107109e 2597 ha->fw_dumped = 0;
61f098dd 2598 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 2599 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
2600 req_q_size = rsp_q_size = 0;
2601
2602 if (IS_QLA27XX(ha))
2603 goto try_fce;
2604
d4e3e04d 2605 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 2606 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 2607 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 2608 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
2609 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
2610 sizeof(uint16_t);
e428924c 2611 } else if (IS_FWI2_CAPABLE(ha)) {
b20f02e1 2612 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 2613 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
2614 else if (IS_QLA81XX(ha))
3a03eb79
AV		 2615 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
2616 else if (IS_QLA25XX(ha))
2617 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
2618 else
2619 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 2620
a7a167bf
AV		 2621 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
2622 sizeof(uint32_t);
050c9bb1 2623 if (ha->mqenable) {
b20f02e1 2624 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1 2625 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 2626 /*
2627 * Allocate maximum buffer size for all queues.
2628 * Resizing must be done at end-of-dump processing.
2629 */
2630 mq_size += ha->max_req_queues *
2631 (req->length * sizeof(request_t));
2632 mq_size += ha->max_rsp_queues *
2633 (rsp->length * sizeof(response_t));
2634 }
00876ae8 2635 if (ha->tgt.atio_ring)
2d70c103 2636 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 2637 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 2638 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2639 !IS_QLA27XX(ha))
436a7b11 2640 goto try_eft;
df613b96 2641
f73cb695
CD		 2642try_fce:
2643 if (ha->fce)
2644 dma_free_coherent(&ha->pdev->dev,
2645 FCE_SIZE, ha->fce, ha->fce_dma);
2646
2647 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 2648 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
2649 GFP_KERNEL);
df613b96 2650 if (!tc) {
7c3df132
SK		 2651 ql_log(ql_log_warn, vha, 0x00be,
2652 "Unable to allocate (%d KB) for FCE.\n",
2653 FCE_SIZE / 1024);
17d98630 2654 goto try_eft;
df613b96
AV		 2655 }
2656
e315cd28 2657 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 2658 ha->fce_mb, &ha->fce_bufs);
2659 if (rval) {
7c3df132
SK		 2660 ql_log(ql_log_warn, vha, 0x00bf,
2661 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 2662 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
2663 tc_dma);
2664 ha->flags.fce_enabled = 0;
17d98630 2665 goto try_eft;
df613b96 2666 }
cfb0919c 2667 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 2668 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 2669
7d9dade3 2670 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 2671 ha->flags.fce_enabled = 1;
2672 ha->fce_dma = tc_dma;
2673 ha->fce = tc;
f73cb695 2674
436a7b11 2675try_eft:
f73cb695
CD		 2676 if (ha->eft)
2677 dma_free_coherent(&ha->pdev->dev,
2678 EFT_SIZE, ha->eft, ha->eft_dma);
2679
436a7b11 2680 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 2681 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
2682 GFP_KERNEL);
436a7b11 2683 if (!tc) {
7c3df132
SK		 2684 ql_log(ql_log_warn, vha, 0x00c1,
2685 "Unable to allocate (%d KB) for EFT.\n",
2686 EFT_SIZE / 1024);
436a7b11
AV		 2687 goto cont_alloc;
2688 }
2689
e315cd28 2690 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 2691 if (rval) {
7c3df132
SK		 2692 ql_log(ql_log_warn, vha, 0x00c2,
2693 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 2694 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
2695 tc_dma);
2696 goto cont_alloc;
2697 }
cfb0919c 2698 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 2699 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 2700
2701 eft_size = EFT_SIZE;
2702 ha->eft_dma = tc_dma;
2703 ha->eft = tc;
d4e3e04d 2704 }
f73cb695 2705
a7a167bf 2706cont_alloc:
f73cb695
CD		 2707 if (IS_QLA27XX(ha)) {
2708 if (!ha->fw_dump_template) {
2709 ql_log(ql_log_warn, vha, 0x00ba,
2710 "Failed missing fwdump template\n");
2711 return;
2712 }
2713 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
2714 ql_dbg(ql_dbg_init, vha, 0x00fa,
2715 "-> allocating fwdump (%x bytes)...\n", dump_size);
2716 goto allocate;
2717 }
2718
73208dfd
AC		 2719 req_q_size = req->length * sizeof(request_t);
2720 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 2721 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 2722 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 2723 ha->chain_offset = dump_size;
2724 dump_size += mq_size + fce_size;
d4e3e04d 2725
b945e777
QT		 2726 if (ha->exchoffld_buf)
2727 dump_size += sizeof(struct qla2xxx_offld_chain) +
2728 ha->exchoffld_size;
2729 if (ha->exlogin_buf)
2730 dump_size += sizeof(struct qla2xxx_offld_chain) +
2731 ha->exlogin_size;
2732
f73cb695 2733allocate:
d4e3e04d 2734 ha->fw_dump = vmalloc(dump_size);
a7a167bf 2735 if (!ha->fw_dump) {
7c3df132
SK		 2736 ql_log(ql_log_warn, vha, 0x00c4,
2737 "Unable to allocate (%d KB) for firmware dump.\n",
2738 dump_size / 1024);
a7a167bf 2739
e30d1756
MI		 2740 if (ha->fce) {
2741 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
2742 ha->fce_dma);
2743 ha->fce = NULL;
2744 ha->fce_dma = 0;
2745 }
2746
a7a167bf
AV		 2747 if (ha->eft) {
2748 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
2749 ha->eft_dma);
2750 ha->eft = NULL;
2751 ha->eft_dma = 0;
2752 }
2753 return;
2754 }
f73cb695 2755 ha->fw_dump_len = dump_size;
cfb0919c 2756 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 2757 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 2758
f73cb695
CD		 2759 if (IS_QLA27XX(ha))
2760 return;
2761
a7a167bf
AV		 2762 ha->fw_dump->signature[0] = 'Q';
2763 ha->fw_dump->signature[1] = 'L';
2764 ha->fw_dump->signature[2] = 'G';
2765 ha->fw_dump->signature[3] = 'C';
ad950360 2766 ha->fw_dump->version = htonl(1);
a7a167bf
AV		 2767
2768 ha->fw_dump->fixed_size = htonl(fixed_size);
2769 ha->fw_dump->mem_size = htonl(mem_size);
2770 ha->fw_dump->req_q_size = htonl(req_q_size);
2771 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
2772
2773 ha->fw_dump->eft_size = htonl(eft_size);
2774 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
2775 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
2776
2777 ha->fw_dump->header_size =
2778 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 2779}
2780
18e7555a
AV		 2781static int
2782qla81xx_mpi_sync(scsi_qla_host_t *vha)
2783{
2784#define MPS_MASK 0xe0
2785 int rval;
2786 uint16_t dc;
2787 uint32_t dw;
18e7555a
AV		 2788
2789 if (!IS_QLA81XX(vha->hw))
2790 return QLA_SUCCESS;
2791
2792 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
2793 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2794 ql_log(ql_log_warn, vha, 0x0105,
2795 "Unable to acquire semaphore.\n");
18e7555a
AV		 2796 goto done;
2797 }
2798
2799 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
2800 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
2801 if (rval != QLA_SUCCESS) {
7c3df132 2802 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 2803 goto done_release;
2804 }
2805
2806 dc &= MPS_MASK;
2807 if (dc == (dw & MPS_MASK))
2808 goto done_release;
2809
2810 dw &= ~MPS_MASK;
2811 dw |= dc;
2812 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
2813 if (rval != QLA_SUCCESS) {
7c3df132 2814 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 2815 }
2816
2817done_release:
2818 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
2819 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2820 ql_log(ql_log_warn, vha, 0x006d,
2821 "Unable to release semaphore.\n");
18e7555a
AV		 2822 }
2823
2824done:
2825 return rval;
2826}
2827
8d93f550
CD		 2828int
2829qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
2830{
2831 /* Don't try to reallocate the array */
2832 if (req->outstanding_cmds)
2833 return QLA_SUCCESS;
2834
d7459527 2835 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 2836 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
2837 else {
03e8c680
QT		 2838 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
2839 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 2840 else
03e8c680 2841 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 2842 }
2843
2844 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2845 req->num_outstanding_cmds, GFP_KERNEL);
2846
2847 if (!req->outstanding_cmds) {
2848 /*
2849 * Try to allocate a minimal size just so we can get through
2850 * initialization.
2851 */
2852 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
2853 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2854 req->num_outstanding_cmds, GFP_KERNEL);
2855
2856 if (!req->outstanding_cmds) {
2857 ql_log(ql_log_fatal, NULL, 0x0126,
2858 "Failed to allocate memory for "
2859 "outstanding_cmds for req_que %p.\n", req);
2860 req->num_outstanding_cmds = 0;
2861 return QLA_FUNCTION_FAILED;
2862 }
2863 }
2864
2865 return QLA_SUCCESS;
2866}
2867
e4e3a2ce
QT		 2868#define PRINT_FIELD(_field, _flag, _str) { \
2869 if (a0->_field & _flag) {\
2870 if (p) {\
2871 strcat(ptr, "|");\
2872 ptr++;\
2873 leftover--;\
2874 } \
2875 len = snprintf(ptr, leftover, "%s", _str); \
2876 p = 1;\
2877 leftover -= len;\
2878 ptr += len; \
2879 } \
2880}
2881
2882static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
2883{
2884#define STR_LEN 64
2885 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
2886 u8 str[STR_LEN], *ptr, p;
2887 int leftover, len;
2888
2889 memset(str, 0, STR_LEN);
2890 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
2891 ql_dbg(ql_dbg_init, vha, 0x015a,
2892 "SFP MFG Name: %s\n", str);
2893
2894 memset(str, 0, STR_LEN);
2895 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
2896 ql_dbg(ql_dbg_init, vha, 0x015c,
2897 "SFP Part Name: %s\n", str);
2898
2899 /* media */
2900 memset(str, 0, STR_LEN);
2901 ptr = str;
2902 leftover = STR_LEN;
2903 p = len = 0;
2904 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
2905 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
2906 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
2907 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
2908 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
2909 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
2910 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
2911 ql_dbg(ql_dbg_init, vha, 0x0160,
2912 "SFP Media: %s\n", str);
2913
2914 /* link length */
2915 memset(str, 0, STR_LEN);
2916 ptr = str;
2917 leftover = STR_LEN;
2918 p = len = 0;
2919 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
2920 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
2921 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
2922 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
2923 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
2924 ql_dbg(ql_dbg_init, vha, 0x0196,
2925 "SFP Link Length: %s\n", str);
2926
2927 memset(str, 0, STR_LEN);
2928 ptr = str;
2929 leftover = STR_LEN;
2930 p = len = 0;
2931 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
2932 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
2933 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
2934 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
2935 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
2936 ql_dbg(ql_dbg_init, vha, 0x016e,
2937 "SFP FC Link Tech: %s\n", str);
2938
2939 if (a0->length_km)
2940 ql_dbg(ql_dbg_init, vha, 0x016f,
2941 "SFP Distant: %d km\n", a0->length_km);
2942 if (a0->length_100m)
2943 ql_dbg(ql_dbg_init, vha, 0x0170,
2944 "SFP Distant: %d m\n", a0->length_100m*100);
2945 if (a0->length_50um_10m)
2946 ql_dbg(ql_dbg_init, vha, 0x0189,
2947 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
2948 if (a0->length_62um_10m)
2949 ql_dbg(ql_dbg_init, vha, 0x018a,
2950 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
2951 if (a0->length_om4_10m)
2952 ql_dbg(ql_dbg_init, vha, 0x0194,
2953 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
2954 if (a0->length_om3_10m)
2955 ql_dbg(ql_dbg_init, vha, 0x0195,
2956 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
2957}
2958
2959
2960/*
2961 * Return Code:
2962 * QLA_SUCCESS: no action
2963 * QLA_INTERFACE_ERROR: SFP is not there.
2964 * QLA_FUNCTION_FAILED: detected New SFP
2965 */
2966int
2967qla24xx_detect_sfp(scsi_qla_host_t *vha)
2968{
2969 int rc = QLA_SUCCESS;
2970 struct sff_8247_a0 *a;
2971 struct qla_hw_data *ha = vha->hw;
2972
2973 if (!AUTO_DETECT_SFP_SUPPORT(vha))
2974 goto out;
2975
2976 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
2977 if (rc)
2978 goto out;
2979
2980 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
2981 qla2xxx_print_sfp_info(vha);
2982
2983 if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
2984 /* long range */
2985 ha->flags.detected_lr_sfp = 1;
2986
2987 if (a->length_km > 5 || a->length_100m > 50)
2988 ha->long_range_distance = LR_DISTANCE_10K;
2989 else
2990 ha->long_range_distance = LR_DISTANCE_5K;
2991
2992 if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
2993 ql_dbg(ql_dbg_async, vha, 0x507b,
2994 "Detected Long Range SFP.\n");
2995 } else {
2996 /* short range */
2997 ha->flags.detected_lr_sfp = 0;
2998 if (ha->flags.using_lr_setting)
2999 ql_dbg(ql_dbg_async, vha, 0x5084,
3000 "Detected Short Range SFP.\n");
3001 }
3002
3003 if (!vha->flags.init_done)
3004 rc = QLA_SUCCESS;
3005out:
3006 return rc;
3007}
3008
1da177e4
LT		 3009/**
3010 * qla2x00_setup_chip() - Load and start RISC firmware.
3011 * @ha: HA context
3012 *
3013 * Returns 0 on success.
3014 */
3015static int
e315cd28 3016qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 3017{
0107109e
AV		 3018 int rval;
3019 uint32_t srisc_address = 0;
e315cd28 3020 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 3021 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3022 unsigned long flags;
dda772e8 3023 uint16_t fw_major_version;
3db0652e 3024
7ec0effd 3025 if (IS_P3P_TYPE(ha)) {
a9083016 3026 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 3027 if (rval == QLA_SUCCESS) {
3028 qla2x00_stop_firmware(vha);
a9083016 3029 goto enable_82xx_npiv;
14e303d9 3030 } else
b963752f 3031 goto failed;
a9083016
GM		 3032 }
3033
3db0652e
AV		 3034 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3035 /* Disable SRAM, Instruction RAM and GP RAM parity. */
3036 spin_lock_irqsave(&ha->hardware_lock, flags);
3037 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
3038 RD_REG_WORD(&reg->hccr);
3039 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3040 }
1da177e4 3041
18e7555a
AV		 3042 qla81xx_mpi_sync(vha);
3043
1da177e4 3044 /* Load firmware sequences */
e315cd28 3045 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 3046 if (rval == QLA_SUCCESS) {
7c3df132
SK		 3047 ql_dbg(ql_dbg_init, vha, 0x00c9,
3048 "Verifying Checksum of loaded RISC code.\n");
1da177e4 3049
e315cd28 3050 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 3051 if (rval == QLA_SUCCESS) {
3052 /* Start firmware execution. */
7c3df132
SK		 3053 ql_dbg(ql_dbg_init, vha, 0x00ca,
3054 "Starting firmware.\n");
1da177e4 3055
b0d6cabd
HM		 3056 if (ql2xexlogins)
3057 ha->flags.exlogins_enabled = 1;
3058
99e1b683 3059 if (qla_is_exch_offld_enabled(vha))
2f56a7f1
HM		 3060 ha->flags.exchoffld_enabled = 1;
3061
e315cd28 3062 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 3063 /* Retrieve firmware information. */
dda772e8 3064 if (rval == QLA_SUCCESS) {
e4e3a2ce
QT		 3065 qla24xx_detect_sfp(vha);
3066
b0d6cabd
HM		 3067 rval = qla2x00_set_exlogins_buffer(vha);
3068 if (rval != QLA_SUCCESS)
3069 goto failed;
3070
2f56a7f1
HM		 3071 rval = qla2x00_set_exchoffld_buffer(vha);
3072 if (rval != QLA_SUCCESS)
3073 goto failed;
3074
a9083016 3075enable_82xx_npiv:
dda772e8 3076 fw_major_version = ha->fw_major_version;
7ec0effd 3077 if (IS_P3P_TYPE(ha))
3173167f 3078 qla82xx_check_md_needed(vha);
6246b8a1
GM		 3079 else
3080 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 3081 if (rval != QLA_SUCCESS)
3082 goto failed;
2c3dfe3f 3083 ha->flags.npiv_supported = 0;
e315cd28 3084 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 3085 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 3086 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 3087 if ((!ha->max_npiv_vports) ||
3088 ((ha->max_npiv_vports + 1) %
eb66dc60 3089 MIN_MULTI_ID_FABRIC))
4d0ea247 3090 ha->max_npiv_vports =
eb66dc60 3091 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 3092 }
03e8c680 3093 qla2x00_get_resource_cnts(vha);
d743de66 3094
8d93f550
CD		 3095 /*
3096 * Allocate the array of outstanding commands
3097 * now that we know the firmware resources.
3098 */
3099 rval = qla2x00_alloc_outstanding_cmds(ha,
3100 vha->req);
3101 if (rval != QLA_SUCCESS)
3102 goto failed;
3103
be5ea3cf 3104 if (!fw_major_version && ql2xallocfwdump
7ec0effd 3105 && !(IS_P3P_TYPE(ha)))
08de2844 3106 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 3107 } else {
3108 goto failed;
1da177e4
LT		 3109 }
3110 } else {
7c3df132
SK		 3111 ql_log(ql_log_fatal, vha, 0x00cd,
3112 "ISP Firmware failed checksum.\n");
3113 goto failed;
1da177e4 3114 }
c74d88a4
AV		 3115 } else
3116 goto failed;
1da177e4 3117
3db0652e
AV		 3118 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3119 /* Enable proper parity. */
3120 spin_lock_irqsave(&ha->hardware_lock, flags);
3121 if (IS_QLA2300(ha))
3122 /* SRAM parity */
3123 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
3124 else
3125 /* SRAM, Instruction RAM and GP RAM parity */
3126 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
3127 RD_REG_WORD(&reg->hccr);
3128 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3129 }
3130
f3982d89
CD		 3131 if (IS_QLA27XX(ha))
3132 ha->flags.fac_supported = 1;
3133 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 3134 uint32_t size;
3135
3136 rval = qla81xx_fac_get_sector_size(vha, &size);
3137 if (rval == QLA_SUCCESS) {
3138 ha->flags.fac_supported = 1;
3139 ha->fdt_block_size = size << 2;
3140 } else {
7c3df132 3141 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 3142 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3143 ha->fw_major_version, ha->fw_minor_version,
3144 ha->fw_subminor_version);
1ca60e3b 3145
f73cb695 3146 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 3147 ha->flags.fac_supported = 0;
3148 rval = QLA_SUCCESS;
3149 }
1d2874de
JC		 3150 }
3151 }
ca9e9c3e 3152failed:
1da177e4 3153 if (rval) {
7c3df132
SK		 3154 ql_log(ql_log_fatal, vha, 0x00cf,
3155 "Setup chip ****FAILED****.\n");
1da177e4
LT		 3156 }
3157
3158 return (rval);
3159}
3160
3161/**
3162 * qla2x00_init_response_q_entries() - Initializes response queue entries.
3163 * @ha: HA context
3164 *
3165 * Beginning of request ring has initialization control block already built
3166 * by nvram config routine.
3167 *
3168 * Returns 0 on success.
3169 */
73208dfd
AC		 3170void
3171qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 3172{
3173 uint16_t cnt;
3174 response_t *pkt;
3175
2afa19a9
AC		 3176 rsp->ring_ptr = rsp->ring;
3177 rsp->ring_index = 0;
3178 rsp->status_srb = NULL;
e315cd28
AC		 3179 pkt = rsp->ring_ptr;
3180 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 3181 pkt->signature = RESPONSE_PROCESSED;
3182 pkt++;
3183 }
1da177e4
LT		 3184}
3185
3186/**
3187 * qla2x00_update_fw_options() - Read and process firmware options.
3188 * @ha: HA context
3189 *
3190 * Returns 0 on success.
3191 */
abbd8870 3192void
e315cd28 3193qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 3194{
3195 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 3196 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3197
3198 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 3199 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 3200
3201 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3202 return;
3203
3204 /* Serial Link options. */
7c3df132
SK		 3205 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3206 "Serial link options.\n");
3207 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
3208 (uint8_t *)&ha->fw_seriallink_options,
3209 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 3210
3211 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3212 if (ha->fw_seriallink_options[3] & BIT_2) {
3213 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3214
3215 /* 1G settings */
3216 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3217 emphasis = (ha->fw_seriallink_options[2] &
3218 (BIT_4 | BIT_3)) >> 3;
3219 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 3220 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3221 rx_sens = (ha->fw_seriallink_options[0] &
3222 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3223 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3224 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3225 if (rx_sens == 0x0)
3226 rx_sens = 0x3;
3227 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3228 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3229 ha->fw_options[10] |= BIT_5 |
3230 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3231 (tx_sens & (BIT_1 | BIT_0));
3232
3233 /* 2G settings */
3234 swing = (ha->fw_seriallink_options[2] &
3235 (BIT_7 | BIT_6 | BIT_5)) >> 5;
3236 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
3237 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 3238 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3239 rx_sens = (ha->fw_seriallink_options[1] &
3240 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3241 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
3242 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3243 if (rx_sens == 0x0)
3244 rx_sens = 0x3;
3245 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
3246 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3247 ha->fw_options[11] |= BIT_5 |
3248 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3249 (tx_sens & (BIT_1 | BIT_0));
3250 }
3251
3252 /* FCP2 options. */
3253 /* Return command IOCBs without waiting for an ABTS to complete. */
3254 ha->fw_options[3] |= BIT_13;
3255
3256 /* LED scheme. */
3257 if (ha->flags.enable_led_scheme)
3258 ha->fw_options[2] |= BIT_12;
3259
48c02fde 3260 /* Detect ISP6312. */
3261 if (IS_QLA6312(ha))
3262 ha->fw_options[2] |= BIT_13;
3263
088d09d4
GM		 3264 /* Set Retry FLOGI in case of P2P connection */
3265 if (ha->operating_mode == P2P) {
3266 ha->fw_options[2] |= BIT_3;
3267 ql_dbg(ql_dbg_disc, vha, 0x2100,
3268 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3269 __func__, ha->fw_options[2]);
3270 }
3271
1da177e4 3272 /* Update firmware options. */
e315cd28 3273 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 3274}
3275
0107109e 3276void
e315cd28 3277qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 3278{
3279 int rval;
e315cd28 3280 struct qla_hw_data *ha = vha->hw;
0107109e 3281
7ec0effd 3282 if (IS_P3P_TYPE(ha))
a9083016
GM		 3283 return;
3284
f198cafa
HM		 3285 /* Hold status IOCBs until ABTS response received. */
3286 if (ql2xfwholdabts)
3287 ha->fw_options[3] |= BIT_12;
3288
088d09d4
GM		 3289 /* Set Retry FLOGI in case of P2P connection */
3290 if (ha->operating_mode == P2P) {
3291 ha->fw_options[2] |= BIT_3;
3292 ql_dbg(ql_dbg_disc, vha, 0x2101,
3293 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3294 __func__, ha->fw_options[2]);
3295 }
3296
41dc529a 3297 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff
QT		 3298 if (ql2xmvasynctoatio &&
3299 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
41dc529a
QT		 3300 if (qla_tgt_mode_enabled(vha) ||
3301 qla_dual_mode_enabled(vha))
3302 ha->fw_options[2] |= BIT_11;
3303 else
3304 ha->fw_options[2] &= ~BIT_11;
3305 }
3306
f7e761f5
QT		 3307 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3308 /*
3309 * Tell FW to track each exchange to prevent
3310 * driver from using stale exchange.
3311 */
3312 if (qla_tgt_mode_enabled(vha) ||
3313 qla_dual_mode_enabled(vha))
3314 ha->fw_options[2] |= BIT_4;
3315 else
3316 ha->fw_options[2] &= ~BIT_4;
3317 }
3318
83548fe2
QT		 3319 ql_dbg(ql_dbg_init, vha, 0x00e8,
3320 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3321 __func__, ha->fw_options[1], ha->fw_options[2],
3322 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 3323
3324 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
3325 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 3326
0107109e 3327 /* Update Serial Link options. */
f94097ed 3328 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3329 return;
3330
e315cd28 3331 rval = qla2x00_set_serdes_params(vha,
f94097ed 3332 le16_to_cpu(ha->fw_seriallink_options24[1]),
3333 le16_to_cpu(ha->fw_seriallink_options24[2]),
3334 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3335 if (rval != QLA_SUCCESS) {
7c3df132 3336 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3337 "Unable to update Serial Link options (%x).\n", rval);
3338 }
3339}
3340
abbd8870 3341void
e315cd28 3342qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3343{
e315cd28 3344 struct qla_hw_data *ha = vha->hw;
3d71644c 3345 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3346 struct req_que *req = ha->req_q_map[0];
3347 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3348
3349 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3350 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3351 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3352 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3353 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
3354 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3355 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3356 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3357 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 3358
3359 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3360 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3361 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3362 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3363 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3364}
3365
0107109e 3366void
e315cd28 3367qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3368{
e315cd28 3369 struct qla_hw_data *ha = vha->hw;
118e2ef9 3370 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3371 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3372 struct qla_msix_entry *msix;
0107109e 3373 struct init_cb_24xx *icb;
73208dfd
AC		 3374 uint16_t rid = 0;
3375 struct req_que *req = ha->req_q_map[0];
3376 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3377
6246b8a1 3378 /* Setup ring parameters in initialization control block. */
0107109e 3379 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3380 icb->request_q_outpointer = cpu_to_le16(0);
3381 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3382 icb->request_q_length = cpu_to_le16(req->length);
3383 icb->response_q_length = cpu_to_le16(rsp->length);
3384 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3385 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3386 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3387 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3388
2d70c103 3389 /* Setup ATIO queue dma pointers for target mode */
ad950360 3390 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3391 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3392 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3393 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3394
7c6300e3 3395 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3396 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3397
f73cb695 3398 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3399 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3400 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3401 if (ha->flags.msix_enabled) {
3402 msix = &ha->msix_entries[1];
83548fe2 3403 ql_dbg(ql_dbg_init, vha, 0x0019,
7c3df132
SK		 3404 "Registering vector 0x%x for base que.\n",
3405 msix->entry);
73208dfd
AC		 3406 icb->msix = cpu_to_le16(msix->entry);
3407 }
3408 /* Use alternate PCI bus number */
3409 if (MSB(rid))
ad950360 3410 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3411 /* Use alternate PCI devfn */
3412 if (LSB(rid))
ad950360 3413 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3414
3155754a 3415 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3416 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3417 (ha->flags.msix_enabled)) {
ad950360 3418 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3419 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3420 ql_dbg(ql_dbg_init, vha, 0x00fe,
3421 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3422 } else {
ad950360 3423 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3424 }
ad950360 3425 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3426
3427 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3428 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3429 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3430 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3431 } else {
3432 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3433 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3434 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3435 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3436 }
aa230bc5 3437 qlt_24xx_config_rings(vha);
2d70c103 3438
73208dfd
AC		 3439 /* PCI posting */
3440 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3441}
3442
1da177e4
LT		 3443/**
3444 * qla2x00_init_rings() - Initializes firmware.
3445 * @ha: HA context
3446 *
3447 * Beginning of request ring has initialization control block already built
3448 * by nvram config routine.
3449 *
3450 * Returns 0 on success.
3451 */
8ae6d9c7 3452int
e315cd28 3453qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3454{
3455 int rval;
3456 unsigned long flags = 0;
29bdccbe 3457 int cnt, que;
e315cd28 3458 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3459 struct req_que *req;
3460 struct rsp_que *rsp;
2c3dfe3f
SJ		 3461 struct mid_init_cb_24xx *mid_init_cb =
3462 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3463
3464 spin_lock_irqsave(&ha->hardware_lock, flags);
3465
3466 /* Clear outstanding commands array. */
2afa19a9 3467 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3468 req = ha->req_q_map[que];
cb43285f 3469 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3470 continue;
7c6300e3
JC		 3471 req->out_ptr = (void *)(req->ring + req->length);
3472 *req->out_ptr = 0;
8d93f550 3473 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3474 req->outstanding_cmds[cnt] = NULL;
1da177e4 3475
2afa19a9 3476 req->current_outstanding_cmd = 1;
1da177e4 3477
29bdccbe
AC		 3478 /* Initialize firmware. */
3479 req->ring_ptr = req->ring;
3480 req->ring_index = 0;
3481 req->cnt = req->length;
3482 }
1da177e4 3483
2afa19a9 3484 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3485 rsp = ha->rsp_q_map[que];
cb43285f 3486 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3487 continue;
7c6300e3
JC		 3488 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3489 *rsp->in_ptr = 0;
29bdccbe 3490 /* Initialize response queue entries */
8ae6d9c7
GM		 3491 if (IS_QLAFX00(ha))
3492 qlafx00_init_response_q_entries(rsp);
3493 else
3494 qla2x00_init_response_q_entries(rsp);
29bdccbe 3495 }
1da177e4 3496
2d70c103
NB		 3497 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3498 ha->tgt.atio_ring_index = 0;
3499 /* Initialize ATIO queue entries */
3500 qlt_init_atio_q_entries(vha);
3501
e315cd28 3502 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3503
3504 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3505
8ae6d9c7
GM		 3506 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3507
3508 if (IS_QLAFX00(ha)) {
3509 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3510 goto next_check;
3511 }
3512
1da177e4 3513 /* Update any ISP specific firmware options before initialization. */
e315cd28 3514 ha->isp_ops->update_fw_options(vha);
1da177e4 3515
605aa2bc 3516 if (ha->flags.npiv_supported) {
45980cc2 3517 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 3518 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 3519 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 3520 }
3521
24a08138 3522 if (IS_FWI2_CAPABLE(ha)) {
ad950360 3523 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 3524 mid_init_cb->init_cb.execution_throttle =
03e8c680 3525 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 3526 ha->flags.dport_enabled =
3527 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
3528 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
3529 (ha->flags.dport_enabled) ? "enabled" : "disabled");
3530 /* FA-WWPN Status */
2486c627 3531 ha->flags.fawwpn_enabled =
40f3862b 3532 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
83548fe2 3533 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
2486c627 3534 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 3535 }
2c3dfe3f 3536
e315cd28 3537 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 3538next_check:
1da177e4 3539 if (rval) {
7c3df132
SK		 3540 ql_log(ql_log_fatal, vha, 0x00d2,
3541 "Init Firmware **** FAILED ****.\n");
1da177e4 3542 } else {
7c3df132
SK		 3543 ql_dbg(ql_dbg_init, vha, 0x00d3,
3544 "Init Firmware -- success.\n");
4b60c827 3545 QLA_FW_STARTED(ha);
1da177e4
LT		 3546 }
3547
3548 return (rval);
3549}
3550
3551/**
3552 * qla2x00_fw_ready() - Waits for firmware ready.
3553 * @ha: HA context
3554 *
3555 * Returns 0 on success.
3556 */
3557static int
e315cd28 3558qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 3559{
3560 int rval;
4d4df193 3561 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 3562 uint16_t min_wait; /* Minimum wait time if loop is down */
3563 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 3564 uint16_t state[6];
e315cd28 3565 struct qla_hw_data *ha = vha->hw;
1da177e4 3566
8ae6d9c7
GM		 3567 if (IS_QLAFX00(vha->hw))
3568 return qlafx00_fw_ready(vha);
3569
1da177e4
LT		 3570 rval = QLA_SUCCESS;
3571
33461491
CD		 3572 /* Time to wait for loop down */
3573 if (IS_P3P_TYPE(ha))
3574 min_wait = 30;
3575 else
3576 min_wait = 20;
1da177e4
LT		 3577
3578 /*
3579 * Firmware should take at most one RATOV to login, plus 5 seconds for
3580 * our own processing.
3581 */
3582 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
3583 wait_time = min_wait;
3584 }
3585
3586 /* Min wait time if loop down */
3587 mtime = jiffies + (min_wait * HZ);
3588
3589 /* wait time before firmware ready */
3590 wtime = jiffies + (wait_time * HZ);
3591
3592 /* Wait for ISP to finish LIP */
e315cd28 3593 if (!vha->flags.init_done)
7c3df132
SK		 3594 ql_log(ql_log_info, vha, 0x801e,
3595 "Waiting for LIP to complete.\n");
1da177e4
LT		 3596
3597 do {
5b939038 3598 memset(state, -1, sizeof(state));
e315cd28 3599 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 3600 if (rval == QLA_SUCCESS) {
4d4df193 3601 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 3602 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 3603 }
4d4df193 3604 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 3605 ql_dbg(ql_dbg_taskm, vha, 0x801f,
3606 "fw_state=%x 84xx=%x.\n", state[0],
3607 state[2]);
4d4df193
HK		 3608 if ((state[2] & FSTATE_LOGGED_IN) &&
3609 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 3610 ql_dbg(ql_dbg_taskm, vha, 0x8028,
3611 "Sending verify iocb.\n");
4d4df193
HK		 3612
3613 cs84xx_time = jiffies;
e315cd28 3614 rval = qla84xx_init_chip(vha);
7c3df132
SK		 3615 if (rval != QLA_SUCCESS) {
3616 ql_log(ql_log_warn,
cfb0919c 3617 vha, 0x8007,
7c3df132 3618 "Init chip failed.\n");
4d4df193 3619 break;
7c3df132 3620 }
4d4df193
HK		 3621
3622 /* Add time taken to initialize. */
3623 cs84xx_time = jiffies - cs84xx_time;
3624 wtime += cs84xx_time;
3625 mtime += cs84xx_time;
cfb0919c 3626 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 3627 "Increasing wait time by %ld. "
3628 "New time %ld.\n", cs84xx_time,
3629 wtime);
4d4df193
HK		 3630 }
3631 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 3632 ql_dbg(ql_dbg_taskm, vha, 0x8037,
3633 "F/W Ready - OK.\n");
1da177e4 3634
e315cd28 3635 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 3636 &ha->login_timeout, &ha->r_a_tov);
3637
3638 rval = QLA_SUCCESS;
3639 break;
3640 }
3641
3642 rval = QLA_FUNCTION_FAILED;
3643
e315cd28 3644 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 3645 state[0] != FSTATE_READY) {
1da177e4 3646 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 3647 * other than Wait for Login.
3648 */
1da177e4 3649 if (time_after_eq(jiffies, mtime)) {
7c3df132 3650 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 3651 "Cable is unplugged...\n");
3652
e315cd28 3653 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 3654 break;
3655 }
3656 }
3657 } else {
3658 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 3659 if (time_after_eq(jiffies, mtime) ||
7190575f 3660 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 3661 break;
3662 }
3663
3664 if (time_after_eq(jiffies, wtime))
3665 break;
3666
3667 /* Delay for a while */
3668 msleep(500);
1da177e4
LT		 3669 } while (1);
3670
7c3df132 3671 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 3672 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
3673 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 3674
cfb0919c 3675 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 3676 ql_log(ql_log_warn, vha, 0x803b,
3677 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 3678 }
3679
3680 return (rval);
3681}
3682
3683/*
3684* qla2x00_configure_hba
3685* Setup adapter context.
3686*
3687* Input:
3688* ha = adapter state pointer.
3689*
3690* Returns:
3691* 0 = success
3692*
3693* Context:
3694* Kernel context.
3695*/
3696static int
e315cd28 3697qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 3698{
3699 int rval;
3700 uint16_t loop_id;
3701 uint16_t topo;
2c3dfe3f 3702 uint16_t sw_cap;
1da177e4
LT		 3703 uint8_t al_pa;
3704 uint8_t area;
3705 uint8_t domain;
3706 char connect_type[22];
e315cd28 3707 struct qla_hw_data *ha = vha->hw;
61e1b269 3708 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 3709 port_id_t id;
1da177e4
LT		 3710
3711 /* Get host addresses. */
e315cd28 3712 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 3713 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 3714 if (rval != QLA_SUCCESS) {
e315cd28 3715 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 3716 IS_CNA_CAPABLE(ha) ||
33135aa2 3717 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 3718 ql_dbg(ql_dbg_disc, vha, 0x2008,
3719 "Loop is in a transition state.\n");
33135aa2 3720 } else {
7c3df132
SK		 3721 ql_log(ql_log_warn, vha, 0x2009,
3722 "Unable to get host loop ID.\n");
61e1b269
JC		 3723 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
3724 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
3725 ql_log(ql_log_warn, vha, 0x1151,
3726 "Doing link init.\n");
3727 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
3728 return rval;
3729 }
e315cd28 3730 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 3731 }
1da177e4
LT		 3732 return (rval);
3733 }
3734
3735 if (topo == 4) {
7c3df132
SK		 3736 ql_log(ql_log_info, vha, 0x200a,
3737 "Cannot get topology - retrying.\n");
1da177e4
LT		 3738 return (QLA_FUNCTION_FAILED);
3739 }
3740
e315cd28 3741 vha->loop_id = loop_id;
1da177e4
LT		 3742
3743 /* initialize */
3744 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
3745 ha->operating_mode = LOOP;
2c3dfe3f 3746 ha->switch_cap = 0;
1da177e4
LT		 3747
3748 switch (topo) {
3749 case 0:
7c3df132 3750 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 3751 ha->current_topology = ISP_CFG_NL;
3752 strcpy(connect_type, "(Loop)");
3753 break;
3754
3755 case 1:
7c3df132 3756 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 3757 ha->switch_cap = sw_cap;
1da177e4
LT		 3758 ha->current_topology = ISP_CFG_FL;
3759 strcpy(connect_type, "(FL_Port)");
3760 break;
3761
3762 case 2:
7c3df132 3763 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 3764 ha->operating_mode = P2P;
3765 ha->current_topology = ISP_CFG_N;
3766 strcpy(connect_type, "(N_Port-to-N_Port)");
3767 break;
3768
3769 case 3:
7c3df132 3770 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 3771 ha->switch_cap = sw_cap;
1da177e4
LT		 3772 ha->operating_mode = P2P;
3773 ha->current_topology = ISP_CFG_F;
3774 strcpy(connect_type, "(F_Port)");
3775 break;
3776
3777 default:
7c3df132
SK		 3778 ql_dbg(ql_dbg_disc, vha, 0x200f,
3779 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 3780 ha->current_topology = ISP_CFG_NL;
3781 strcpy(connect_type, "(Loop)");
3782 break;
3783 }
3784
3785 /* Save Host port and loop ID. */
3786 /* byte order - Big Endian */
482c9dc7
QT		 3787 id.b.domain = domain;
3788 id.b.area = area;
3789 id.b.al_pa = al_pa;
3790 id.b.rsvd_1 = 0;
3791 qlt_update_host_map(vha, id);
2d70c103 3792
e315cd28 3793 if (!vha->flags.init_done)
7c3df132
SK		 3794 ql_log(ql_log_info, vha, 0x2010,
3795 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 3796 connect_type, vha->loop_id);
1da177e4 3797
1da177e4
LT		 3798 return(rval);
3799}
3800
a9083016 3801inline void
e315cd28
AC		 3802qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
3803 char *def)
9bb9fcf2
AV		 3804{
3805 char *st, *en;
3806 uint16_t index;
e315cd28 3807 struct qla_hw_data *ha = vha->hw;
ab671149 3808 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 3809 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 3810
3811 if (memcmp(model, BINZERO, len) != 0) {
3812 strncpy(ha->model_number, model, len);
3813 st = en = ha->model_number;
3814 en += len - 1;
3815 while (en > st) {
3816 if (*en != 0x20 && *en != 0x00)
3817 break;
3818 *en-- = '\0';
3819 }
3820
3821 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3822 if (use_tbl &&
3823 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 3824 index < QLA_MODEL_NAMES)
1ee27146
JC		 3825 strncpy(ha->model_desc,
3826 qla2x00_model_name[index * 2 + 1],
3827 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3828 } else {
3829 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3830 if (use_tbl &&
3831 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 3832 index < QLA_MODEL_NAMES) {
3833 strcpy(ha->model_number,
3834 qla2x00_model_name[index * 2]);
1ee27146
JC		 3835 strncpy(ha->model_desc,
3836 qla2x00_model_name[index * 2 + 1],
3837 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3838 } else {
3839 strcpy(ha->model_number, def);
3840 }
3841 }
1ee27146 3842 if (IS_FWI2_CAPABLE(ha))
e315cd28 3843 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 3844 sizeof(ha->model_desc));
9bb9fcf2
AV		 3845}
3846
4e08df3f
DM		 3847/* On sparc systems, obtain port and node WWN from firmware
3848 * properties.
3849 */
e315cd28 3850static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 3851{
3852#ifdef CONFIG_SPARC
e315cd28 3853 struct qla_hw_data *ha = vha->hw;
4e08df3f 3854 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 3855 struct device_node *dp = pci_device_to_OF_node(pdev);
3856 const u8 *val;
4e08df3f
DM		 3857 int len;
3858
3859 val = of_get_property(dp, "port-wwn", &len);
3860 if (val && len >= WWN_SIZE)
3861 memcpy(nv->port_name, val, WWN_SIZE);
3862
3863 val = of_get_property(dp, "node-wwn", &len);
3864 if (val && len >= WWN_SIZE)
3865 memcpy(nv->node_name, val, WWN_SIZE);
3866#endif
3867}
3868
1da177e4
LT		 3869/*
3870* NVRAM configuration for ISP 2xxx
3871*
3872* Input:
3873* ha = adapter block pointer.
3874*
3875* Output:
3876* initialization control block in response_ring
3877* host adapters parameters in host adapter block
3878*
3879* Returns:
3880* 0 = success.
3881*/
abbd8870 3882int
e315cd28 3883qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 3884{
4e08df3f 3885 int rval;
0107109e
AV		 3886 uint8_t chksum = 0;
3887 uint16_t cnt;
3888 uint8_t *dptr1, *dptr2;
e315cd28 3889 struct qla_hw_data *ha = vha->hw;
0107109e 3890 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 3891 nvram_t *nv = ha->nvram;
3892 uint8_t *ptr = ha->nvram;
3d71644c 3893 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 3894
4e08df3f
DM		 3895 rval = QLA_SUCCESS;
3896
1da177e4 3897 /* Determine NVRAM starting address. */
0107109e 3898 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 3899 ha->nvram_base = 0;
3900 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
3901 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
3902 ha->nvram_base = 0x80;
3903
3904 /* Get NVRAM data and calculate checksum. */
e315cd28 3905 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 3906 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
3907 chksum += *ptr++;
1da177e4 3908
7c3df132
SK		 3909 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
3910 "Contents of NVRAM.\n");
3911 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
3912 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 3913
3914 /* Bad NVRAM data, set defaults parameters. */
3915 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
3916 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
3917 /* Reset NVRAM data. */
7c3df132 3918 ql_log(ql_log_warn, vha, 0x0064,
9e336520 3919 "Inconsistent NVRAM "
7c3df132
SK		 3920 "detected: checksum=0x%x id=%c version=0x%x.\n",
3921 chksum, nv->id[0], nv->nvram_version);
3922 ql_log(ql_log_warn, vha, 0x0065,
3923 "Falling back to "
3924 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 3925
3926 /*
3927 * Set default initialization control block.
3928 */
3929 memset(nv, 0, ha->nvram_size);
3930 nv->parameter_block_version = ICB_VERSION;
3931
3932 if (IS_QLA23XX(ha)) {
3933 nv->firmware_options[0] = BIT_2 | BIT_1;
3934 nv->firmware_options[1] = BIT_7 | BIT_5;
3935 nv->add_firmware_options[0] = BIT_5;
3936 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3937 nv->frame_payload_size = 2048;
4e08df3f
DM		 3938 nv->special_options[1] = BIT_7;
3939 } else if (IS_QLA2200(ha)) {
3940 nv->firmware_options[0] = BIT_2 | BIT_1;
3941 nv->firmware_options[1] = BIT_7 | BIT_5;
3942 nv->add_firmware_options[0] = BIT_5;
3943 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3944 nv->frame_payload_size = 1024;
4e08df3f
DM		 3945 } else if (IS_QLA2100(ha)) {
3946 nv->firmware_options[0] = BIT_3 | BIT_1;
3947 nv->firmware_options[1] = BIT_5;
98aee70d 3948 nv->frame_payload_size = 1024;
4e08df3f
DM		 3949 }
3950
ad950360
BVA		 3951 nv->max_iocb_allocation = cpu_to_le16(256);
3952 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 3953 nv->retry_count = 8;
3954 nv->retry_delay = 1;
3955
3956 nv->port_name[0] = 33;
3957 nv->port_name[3] = 224;
3958 nv->port_name[4] = 139;
3959
e315cd28 3960 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 3961
3962 nv->login_timeout = 4;
3963
3964 /*
3965 * Set default host adapter parameters
3966 */
3967 nv->host_p[1] = BIT_2;
3968 nv->reset_delay = 5;
3969 nv->port_down_retry_count = 8;
ad950360 3970 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 3971 nv->link_down_timeout = 60;
3972
3973 rval = 1;
1da177e4
LT		 3974 }
3975
3976#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
3977 /*
3978 * The SN2 does not provide BIOS emulation which means you can't change
3979 * potentially bogus BIOS settings. Force the use of default settings
3980 * for link rate and frame size. Hope that the rest of the settings
3981 * are valid.
3982 */
3983 if (ia64_platform_is("sn2")) {
98aee70d 3984 nv->frame_payload_size = 2048;
1da177e4
LT		 3985 if (IS_QLA23XX(ha))
3986 nv->special_options[1] = BIT_7;
3987 }
3988#endif
3989
3990 /* Reset Initialization control block */
0107109e 3991 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 3992
3993 /*
3994 * Setup driver NVRAM options.
3995 */
3996 nv->firmware_options[0] |= (BIT_6 | BIT_1);
3997 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
3998 nv->firmware_options[1] |= (BIT_5 | BIT_0);
3999 nv->firmware_options[1] &= ~BIT_4;
4000
4001 if (IS_QLA23XX(ha)) {
4002 nv->firmware_options[0] |= BIT_2;
4003 nv->firmware_options[0] &= ~BIT_3;
2d70c103 4004 nv->special_options[0] &= ~BIT_6;
0107109e 4005 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 4006
4007 if (IS_QLA2300(ha)) {
4008 if (ha->fb_rev == FPM_2310) {
4009 strcpy(ha->model_number, "QLA2310");
4010 } else {
4011 strcpy(ha->model_number, "QLA2300");
4012 }
4013 } else {
e315cd28 4014 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 4015 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 4016 }
4017 } else if (IS_QLA2200(ha)) {
4018 nv->firmware_options[0] |= BIT_2;
4019 /*
4020 * 'Point-to-point preferred, else loop' is not a safe
4021 * connection mode setting.
4022 */
4023 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
4024 (BIT_5 | BIT_4)) {
4025 /* Force 'loop preferred, else point-to-point'. */
4026 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
4027 nv->add_firmware_options[0] |= BIT_5;
4028 }
4029 strcpy(ha->model_number, "QLA22xx");
4030 } else /*if (IS_QLA2100(ha))*/ {
4031 strcpy(ha->model_number, "QLA2100");
4032 }
4033
4034 /*
4035 * Copy over NVRAM RISC parameter block to initialization control block.
4036 */
4037 dptr1 = (uint8_t *)icb;
4038 dptr2 = (uint8_t *)&nv->parameter_block_version;
4039 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
4040 while (cnt--)
4041 *dptr1++ = *dptr2++;
4042
4043 /* Copy 2nd half. */
4044 dptr1 = (uint8_t *)icb->add_firmware_options;
4045 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4046 while (cnt--)
4047 *dptr1++ = *dptr2++;
4048
5341e868
AV		 4049 /* Use alternate WWN? */
4050 if (nv->host_p[1] & BIT_7) {
4051 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4052 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4053 }
4054
1da177e4
LT		 4055 /* Prepare nodename */
4056 if ((icb->firmware_options[1] & BIT_6) == 0) {
4057 /*
4058 * Firmware will apply the following mask if the nodename was
4059 * not provided.
4060 */
4061 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4062 icb->node_name[0] &= 0xF0;
4063 }
4064
4065 /*
4066 * Set host adapter parameters.
4067 */
3ce8866c
SK		 4068
4069 /*
4070 * BIT_7 in the host-parameters section allows for modification to
4071 * internal driver logging.
4072 */
0181944f 4073 if (nv->host_p[0] & BIT_7)
cfb0919c 4074 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 4075 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4076 /* Always load RISC code on non ISP2[12]00 chips. */
4077 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4078 ha->flags.disable_risc_code_load = 0;
4079 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4080 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4081 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 4082 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 4083 ha->flags.disable_serdes = 0;
1da177e4
LT		 4084
4085 ha->operating_mode =
4086 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4087
4088 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4089 sizeof(ha->fw_seriallink_options));
4090
4091 /* save HBA serial number */
4092 ha->serial0 = icb->port_name[5];
4093 ha->serial1 = icb->port_name[6];
4094 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4095 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4096 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 4097
ad950360 4098 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 4099
4100 ha->retry_count = nv->retry_count;
4101
4102 /* Set minimum login_timeout to 4 seconds. */
5b91490e 4103 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 4104 nv->login_timeout = ql2xlogintimeout;
4105 if (nv->login_timeout < 4)
4106 nv->login_timeout = 4;
4107 ha->login_timeout = nv->login_timeout;
1da177e4 4108
00a537b8
AV		 4109 /* Set minimum RATOV to 100 tenths of a second. */
4110 ha->r_a_tov = 100;
1da177e4 4111
1da177e4
LT		 4112 ha->loop_reset_delay = nv->reset_delay;
4113
1da177e4
LT		 4114 /* Link Down Timeout = 0:
4115 *
4116 * When Port Down timer expires we will start returning
4117 * I/O's to OS with "DID_NO_CONNECT".
4118 *
4119 * Link Down Timeout != 0:
4120 *
4121 * The driver waits for the link to come up after link down
4122 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 4123 */
1da177e4
LT		 4124 if (nv->link_down_timeout == 0) {
4125 ha->loop_down_abort_time =
354d6b21 4126 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 4127 } else {
4128 ha->link_down_timeout = nv->link_down_timeout;
4129 ha->loop_down_abort_time =
4130 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 4131 }
1da177e4 4132
1da177e4
LT		 4133 /*
4134 * Need enough time to try and get the port back.
4135 */
4136 ha->port_down_retry_count = nv->port_down_retry_count;
4137 if (qlport_down_retry)
4138 ha->port_down_retry_count = qlport_down_retry;
4139 /* Set login_retry_count */
4140 ha->login_retry_count = nv->retry_count;
4141 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4142 ha->port_down_retry_count > 3)
4143 ha->login_retry_count = ha->port_down_retry_count;
4144 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4145 ha->login_retry_count = ha->port_down_retry_count;
4146 if (ql2xloginretrycount)
4147 ha->login_retry_count = ql2xloginretrycount;
4148
ad950360 4149 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 4150 icb->command_resource_count = 0;
4151 icb->immediate_notify_resource_count = 0;
ad950360 4152 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 4153
4154 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4155 /* Enable RIO */
4156 icb->firmware_options[0] &= ~BIT_3;
4157 icb->add_firmware_options[0] &=
4158 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4159 icb->add_firmware_options[0] |= BIT_2;
4160 icb->response_accumulation_timer = 3;
4161 icb->interrupt_delay_timer = 5;
4162
e315cd28 4163 vha->flags.process_response_queue = 1;
1da177e4 4164 } else {
4fdfefe5 4165 /* Enable ZIO. */
e315cd28 4166 if (!vha->flags.init_done) {
4fdfefe5
AV		 4167 ha->zio_mode = icb->add_firmware_options[0] &
4168 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4169 ha->zio_timer = icb->interrupt_delay_timer ?
4170 icb->interrupt_delay_timer: 2;
4171 }
1da177e4
LT		 4172 icb->add_firmware_options[0] &=
4173 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 4174 vha->flags.process_response_queue = 0;
4fdfefe5 4175 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4176 ha->zio_mode = QLA_ZIO_MODE_6;
4177
7c3df132 4178 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 4179 "ZIO mode %d enabled; timer delay (%d us).\n",
4180 ha->zio_mode, ha->zio_timer * 100);
1da177e4 4181
4fdfefe5
AV		 4182 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4183 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 4184 vha->flags.process_response_queue = 1;
1da177e4
LT		 4185 }
4186 }
4187
4e08df3f 4188 if (rval) {
7c3df132
SK		 4189 ql_log(ql_log_warn, vha, 0x0069,
4190 "NVRAM configuration failed.\n");
4e08df3f
DM		 4191 }
4192 return (rval);
1da177e4
LT		 4193}
4194
19a7b4ae
JSEC		 4195static void
4196qla2x00_rport_del(void *data)
4197{
4198 fc_port_t *fcport = data;
d97994dc 4199 struct fc_rport *rport;
044d78e1 4200 unsigned long flags;
d97994dc 4201
044d78e1 4202 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 4203 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 4204 fcport->drport = NULL;
044d78e1 4205 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548 4206 if (rport) {
83548fe2
QT		 4207 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4208 "%s %8phN. rport %p roles %x\n",
4209 __func__, fcport->port_name, rport,
4210 rport->roles);
726b8548 4211
d97994dc 4212 fc_remote_port_delete(rport);
726b8548 4213 }
19a7b4ae
JSEC		 4214}
4215
1da177e4
LT		 4216/**
4217 * qla2x00_alloc_fcport() - Allocate a generic fcport.
4218 * @ha: HA context
4219 * @flags: allocation flags
4220 *
4221 * Returns a pointer to the allocated fcport, or NULL, if none available.
4222 */
9a069e19 4223fc_port_t *
e315cd28 4224qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 4225{
4226 fc_port_t *fcport;
4227
bbfbbbc1
MK		 4228 fcport = kzalloc(sizeof(fc_port_t), flags);
4229 if (!fcport)
4230 return NULL;
1da177e4
LT		 4231
4232 /* Setup fcport template structure. */
e315cd28 4233 fcport->vha = vha;
1da177e4
LT		 4234 fcport->port_type = FCT_UNKNOWN;
4235 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 4236 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 4237 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 4238
726b8548
QT		 4239 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
4240 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 4241 flags);
726b8548
QT		 4242 fcport->disc_state = DSC_DELETED;
4243 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4244 fcport->deleted = QLA_SESS_DELETED;
4245 fcport->login_retry = vha->hw->login_retry_count;
4246 fcport->login_retry = 5;
4247 fcport->logout_on_delete = 1;
4248
4249 if (!fcport->ct_desc.ct_sns) {
83548fe2 4250 ql_log(ql_log_warn, vha, 0xd049,
726b8548
QT		 4251 "Failed to allocate ct_sns request.\n");
4252 kfree(fcport);
4253 fcport = NULL;
4254 }
4255 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
4256 INIT_LIST_HEAD(&fcport->gnl_entry);
4257 INIT_LIST_HEAD(&fcport->list);
4258
bbfbbbc1 4259 return fcport;
1da177e4
LT		 4260}
4261
726b8548
QT		 4262void
4263qla2x00_free_fcport(fc_port_t *fcport)
4264{
4265 if (fcport->ct_desc.ct_sns) {
4266 dma_free_coherent(&fcport->vha->hw->pdev->dev,
4267 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
4268 fcport->ct_desc.ct_sns_dma);
4269
4270 fcport->ct_desc.ct_sns = NULL;
4271 }
4272 kfree(fcport);
4273}
4274
1da177e4
LT		 4275/*
4276 * qla2x00_configure_loop
4277 * Updates Fibre Channel Device Database with what is actually on loop.
4278 *
4279 * Input:
4280 * ha = adapter block pointer.
4281 *
4282 * Returns:
4283 * 0 = success.
4284 * 1 = error.
4285 * 2 = database was full and device was not configured.
4286 */
4287static int
e315cd28 4288qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4289{
4290 int rval;
4291 unsigned long flags, save_flags;
e315cd28 4292 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4293 rval = QLA_SUCCESS;
4294
4295 /* Get Initiator ID */
e315cd28
AC		 4296 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
4297 rval = qla2x00_configure_hba(vha);
1da177e4 4298 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4299 ql_dbg(ql_dbg_disc, vha, 0x2013,
4300 "Unable to configure HBA.\n");
1da177e4
LT		 4301 return (rval);
4302 }
4303 }
4304
e315cd28 4305 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 4306 ql_dbg(ql_dbg_disc, vha, 0x2014,
4307 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 4308
4309 /*
4310 * If we have both an RSCN and PORT UPDATE pending then handle them
4311 * both at the same time.
4312 */
e315cd28
AC		 4313 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4314 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 4315
3064ff39
MH		 4316 qla2x00_get_data_rate(vha);
4317
1da177e4
LT		 4318 /* Determine what we need to do */
4319 if (ha->current_topology == ISP_CFG_FL &&
4320 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4321
1da177e4
LT		 4322 set_bit(RSCN_UPDATE, &flags);
4323
4324 } else if (ha->current_topology == ISP_CFG_F &&
4325 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4326
1da177e4
LT		 4327 set_bit(RSCN_UPDATE, &flags);
4328 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4329
4330 } else if (ha->current_topology == ISP_CFG_N) {
4331 clear_bit(RSCN_UPDATE, &flags);
41dc529a
QT		 4332 } else if (ha->current_topology == ISP_CFG_NL) {
4333 clear_bit(RSCN_UPDATE, &flags);
4334 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4335 } else if (!vha->flags.online ||
1da177e4 4336 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 4337 set_bit(RSCN_UPDATE, &flags);
4338 set_bit(LOCAL_LOOP_UPDATE, &flags);
4339 }
4340
4341 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 4342 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
4343 ql_dbg(ql_dbg_disc, vha, 0x2015,
4344 "Loop resync needed, failing.\n");
1da177e4 4345 rval = QLA_FUNCTION_FAILED;
642ef983 4346 } else
e315cd28 4347 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 4348 }
4349
4350 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132 4351 if (LOOP_TRANSITION(vha)) {
83548fe2 4352 ql_dbg(ql_dbg_disc, vha, 0x2099,
7c3df132 4353 "Needs RSCN update and loop transition.\n");
1da177e4 4354 rval = QLA_FUNCTION_FAILED;
7c3df132 4355 }
e315cd28
AC		 4356 else
4357 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 4358 }
4359
4360 if (rval == QLA_SUCCESS) {
e315cd28
AC		 4361 if (atomic_read(&vha->loop_down_timer) ||
4362 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4363 rval = QLA_FUNCTION_FAILED;
4364 } else {
e315cd28 4365 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4366 ql_dbg(ql_dbg_disc, vha, 0x2069,
4367 "LOOP READY.\n");
ec7193e2 4368 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 4369
4370 /*
4371 * Process any ATIO queue entries that came in
4372 * while we weren't online.
4373 */
ead03855
QT		 4374 if (qla_tgt_mode_enabled(vha) ||
4375 qla_dual_mode_enabled(vha)) {
3bb67df5
DKU		 4376 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
4377 spin_lock_irqsave(&ha->tgt.atio_lock,
4378 flags);
4379 qlt_24xx_process_atio_queue(vha, 0);
4380 spin_unlock_irqrestore(
4381 &ha->tgt.atio_lock, flags);
4382 } else {
4383 spin_lock_irqsave(&ha->hardware_lock,
4384 flags);
4385 qlt_24xx_process_atio_queue(vha, 1);
4386 spin_unlock_irqrestore(
4387 &ha->hardware_lock, flags);
4388 }
4389 }
1da177e4
LT		 4390 }
4391 }
4392
4393 if (rval) {
7c3df132
SK		 4394 ql_dbg(ql_dbg_disc, vha, 0x206a,
4395 "%s *** FAILED ***.\n", __func__);
1da177e4 4396 } else {
7c3df132
SK		 4397 ql_dbg(ql_dbg_disc, vha, 0x206b,
4398 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4399 }
4400
cc3ef7bc 4401 /* Restore state if a resync event occurred during processing */
e315cd28 4402 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4403 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4404 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4405 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4406 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4407 }
1da177e4
LT		 4408 }
4409
4410 return (rval);
4411}
4412
edd05de1
DG		 4413/*
4414 * N2N Login
4415 * Updates Fibre Channel Device Database with local loop devices.
4416 *
4417 * Input:
4418 * ha = adapter block pointer.
4419 *
4420 * Returns:
4421 */
4422static int qla24xx_n2n_handle_login(struct scsi_qla_host *vha,
4423 fc_port_t *fcport)
4424{
4425 struct qla_hw_data *ha = vha->hw;
4426 int res = QLA_SUCCESS, rval;
4427 int greater_wwpn = 0;
4428 int logged_in = 0;
4429
4430 if (ha->current_topology != ISP_CFG_N)
4431 return res;
4432
4433 if (wwn_to_u64(vha->port_name) >
4434 wwn_to_u64(vha->n2n_port_name)) {
4435 ql_dbg(ql_dbg_disc, vha, 0x2002,
4436 "HBA WWPN is greater %llx > target %llx\n",
4437 wwn_to_u64(vha->port_name),
4438 wwn_to_u64(vha->n2n_port_name));
4439 greater_wwpn = 1;
4440 fcport->d_id.b24 = vha->n2n_id;
4441 }
4442
4443 fcport->loop_id = vha->loop_id;
4444 fcport->fc4f_nvme = 0;
4445 fcport->query = 1;
4446
4447 ql_dbg(ql_dbg_disc, vha, 0x4001,
4448 "Initiate N2N login handler: HBA port_id=%06x loopid=%d\n",
4449 fcport->d_id.b24, vha->loop_id);
4450
4451 /* Fill in member data. */
4452 if (!greater_wwpn) {
4453 rval = qla2x00_get_port_database(vha, fcport, 0);
4454 ql_dbg(ql_dbg_disc, vha, 0x1051,
4455 "Remote login-state (%x/%x) port_id=%06x loop_id=%x, rval=%d\n",
4456 fcport->current_login_state, fcport->last_login_state,
4457 fcport->d_id.b24, fcport->loop_id, rval);
4458
4459 if (((fcport->current_login_state & 0xf) == 0x4) ||
4460 ((fcport->current_login_state & 0xf) == 0x6))
4461 logged_in = 1;
4462 }
4463
4464 if (logged_in || greater_wwpn) {
4465 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
4466 qla_nvme_register_hba(vha);
4467
4468 /* Set connected N_Port d_id */
4469 if (vha->flags.nvme_enabled)
4470 fcport->fc4f_nvme = 1;
4471
4472 fcport->scan_state = QLA_FCPORT_FOUND;
4473 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4474 fcport->disc_state = DSC_GNL;
4475 fcport->n2n_flag = 1;
4476 fcport->flags = 3;
4477 vha->hw->flags.gpsc_supported = 0;
4478
4479 if (greater_wwpn) {
4480 ql_dbg(ql_dbg_disc, vha, 0x20e5,
4481 "%s %d PLOGI ELS %8phC\n",
4482 __func__, __LINE__, fcport->port_name);
4483
4484 res = qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
4485 fcport, fcport->d_id);
4486 }
4487
4488 if (res != QLA_SUCCESS) {
4489 ql_log(ql_log_info, vha, 0xd04d,
4490 "PLOGI Failed: portid=%06x - retrying\n",
4491 fcport->d_id.b24);
4492 res = QLA_SUCCESS;
4493 } else {
4494 /* State 0x6 means FCP PRLI complete */
4495 if ((fcport->current_login_state & 0xf) == 0x6) {
4496 ql_dbg(ql_dbg_disc, vha, 0x2118,
4497 "%s %d %8phC post GPDB work\n",
4498 __func__, __LINE__, fcport->port_name);
4499 fcport->chip_reset =
4500 vha->hw->base_qpair->chip_reset;
4501 qla24xx_post_gpdb_work(vha, fcport, 0);
4502 } else {
4503 ql_dbg(ql_dbg_disc, vha, 0x2118,
4504 "%s %d %8phC post NVMe PRLI\n",
4505 __func__, __LINE__, fcport->port_name);
4506 qla24xx_post_prli_work(vha, fcport);
4507 }
4508 }
4509 } else {
4510 /* Wait for next database change */
4511 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
4512 }
1da177e4 4513
edd05de1
DG		 4514 return res;
4515}
1da177e4
LT		 4516
4517/*
4518 * qla2x00_configure_local_loop
4519 * Updates Fibre Channel Device Database with local loop devices.
4520 *
4521 * Input:
4522 * ha = adapter block pointer.
4523 *
4524 * Returns:
4525 * 0 = success.
4526 */
4527static int
e315cd28 4528qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4529{
4530 int rval, rval2;
4531 int found_devs;
4532 int found;
4533 fc_port_t *fcport, *new_fcport;
4534
4535 uint16_t index;
4536 uint16_t entries;
4537 char *id_iter;
4538 uint16_t loop_id;
4539 uint8_t domain, area, al_pa;
e315cd28 4540 struct qla_hw_data *ha = vha->hw;
41dc529a 4541 unsigned long flags;
1da177e4
LT		 4542
4543 found_devs = 0;
4544 new_fcport = NULL;
642ef983 4545 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4546
1da177e4 4547 /* Get list of logged in devices. */
642ef983 4548 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4549 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4550 &entries);
4551 if (rval != QLA_SUCCESS)
4552 goto cleanup_allocation;
4553
83548fe2 4554 ql_dbg(ql_dbg_disc, vha, 0x2011,
7c3df132
SK		 4555 "Entries in ID list (%d).\n", entries);
4556 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4557 (uint8_t *)ha->gid_list,
4558 entries * sizeof(struct gid_list_info));
1da177e4
LT		 4559
4560 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4561 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4562 if (new_fcport == NULL) {
83548fe2 4563 ql_log(ql_log_warn, vha, 0x2012,
7c3df132 4564 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4565 rval = QLA_MEMORY_ALLOC_FAILED;
4566 goto cleanup_allocation;
4567 }
4568 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4569
4570 /*
4571 * Mark local devices that were present with FCF_DEVICE_LOST for now.
4572 */
e315cd28 4573 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4574 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4575 fcport->port_type != FCT_BROADCAST &&
4576 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
4577
83548fe2 4578 ql_dbg(ql_dbg_disc, vha, 0x2096,
7c3df132
SK		 4579 "Marking port lost loop_id=0x%04x.\n",
4580 fcport->loop_id);
1da177e4 4581
41dc529a 4582 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1da177e4
LT		 4583 }
4584 }
4585
edd05de1
DG		 4586 /* Inititae N2N login. */
4587 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) {
4588 rval = qla24xx_n2n_handle_login(vha, new_fcport);
4589 if (rval != QLA_SUCCESS)
4590 goto cleanup_allocation;
4591 return QLA_SUCCESS;
4592 }
4593
1da177e4
LT		 4594 /* Add devices to port list. */
4595 id_iter = (char *)ha->gid_list;
4596 for (index = 0; index < entries; index++) {
4597 domain = ((struct gid_list_info *)id_iter)->domain;
4598 area = ((struct gid_list_info *)id_iter)->area;
4599 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4600 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4601 loop_id = (uint16_t)
4602 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4603 else
1da177e4
LT		 4604 loop_id = le16_to_cpu(
4605 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4606 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4607
4608 /* Bypass reserved domain fields. */
4609 if ((domain & 0xf0) == 0xf0)
4610 continue;
4611
4612 /* Bypass if not same domain and area of adapter. */
f7d289f6 4613 if (area && domain &&
e315cd28 4614 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4615 continue;
4616
4617 /* Bypass invalid local loop ID. */
4618 if (loop_id > LAST_LOCAL_LOOP_ID)
4619 continue;
4620
41dc529a 4621 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 4622
1da177e4
LT		 4623 /* Fill in member data. */
4624 new_fcport->d_id.b.domain = domain;
4625 new_fcport->d_id.b.area = area;
4626 new_fcport->d_id.b.al_pa = al_pa;
4627 new_fcport->loop_id = loop_id;
41dc529a 4628
e315cd28 4629 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 4630 if (rval2 != QLA_SUCCESS) {
83548fe2 4631 ql_dbg(ql_dbg_disc, vha, 0x2097,
7c3df132
SK		 4632 "Failed to retrieve fcport information "
4633 "-- get_port_database=%x, loop_id=0x%04x.\n",
4634 rval2, new_fcport->loop_id);
edd05de1
DG		 4635 /* Skip retry if N2N */
4636 if (ha->current_topology != ISP_CFG_N) {
4637 ql_dbg(ql_dbg_disc, vha, 0x2105,
4638 "Scheduling resync.\n");
4639 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4640 continue;
4641 }
1da177e4
LT		 4642 }
4643
41dc529a 4644 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4645 /* Check for matching device in port list. */
4646 found = 0;
4647 fcport = NULL;
e315cd28 4648 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4649 if (memcmp(new_fcport->port_name, fcport->port_name,
4650 WWN_SIZE))
4651 continue;
4652
ddb9b126 4653 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 4654 fcport->loop_id = new_fcport->loop_id;
4655 fcport->port_type = new_fcport->port_type;
4656 fcport->d_id.b24 = new_fcport->d_id.b24;
4657 memcpy(fcport->node_name, new_fcport->node_name,
4658 WWN_SIZE);
4659
41dc529a
QT		 4660 if (!fcport->login_succ) {
4661 vha->fcport_count++;
4662 fcport->login_succ = 1;
4663 fcport->disc_state = DSC_LOGIN_COMPLETE;
4664 }
4665
1da177e4
LT		 4666 found++;
4667 break;
4668 }
4669
4670 if (!found) {
4671 /* New device, add to fcports list. */
e315cd28 4672 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 4673
4674 /* Allocate a new replacement fcport. */
4675 fcport = new_fcport;
41dc529a
QT		 4676 if (!fcport->login_succ) {
4677 vha->fcport_count++;
4678 fcport->login_succ = 1;
4679 fcport->disc_state = DSC_LOGIN_COMPLETE;
4680 }
4681
4682 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4683
e315cd28 4684 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 4685
1da177e4 4686 if (new_fcport == NULL) {
83548fe2 4687 ql_log(ql_log_warn, vha, 0xd031,
7c3df132 4688 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4689 rval = QLA_MEMORY_ALLOC_FAILED;
4690 goto cleanup_allocation;
4691 }
41dc529a 4692 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4693 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4694 }
4695
41dc529a
QT		 4696 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4697
d8b45213 4698 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 4699 fcport->fp_speed = ha->link_data_rate;
d8b45213 4700
e315cd28 4701 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 4702
4703 found_devs++;
4704 }
4705
4706cleanup_allocation:
c9475cb0 4707 kfree(new_fcport);
1da177e4
LT		 4708
4709 if (rval != QLA_SUCCESS) {
83548fe2 4710 ql_dbg(ql_dbg_disc, vha, 0x2098,
7c3df132 4711 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 4712 }
4713
1da177e4
LT		 4714 return (rval);
4715}
4716
d8b45213 4717static void
e315cd28 4718qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 4719{
d8b45213 4720 int rval;
93f2bd67 4721 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4722 struct qla_hw_data *ha = vha->hw;
d8b45213 4723
c76f2c01 4724 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 4725 return;
4726
c9afb9a2
GM		 4727 if (atomic_read(&fcport->state) != FCS_ONLINE)
4728 return;
4729
39bd9622
AV		 4730 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
4731 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 4732 return;
4733
e315cd28 4734 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 4735 mb);
d8b45213 4736 if (rval != QLA_SUCCESS) {
7c3df132 4737 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 4738 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
4739 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 4740 } else {
7c3df132 4741 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 4742 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 4743 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 4744 fcport->port_name);
d8b45213
AV		 4745 }
4746}
4747
726b8548 4748/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 4749static void
e315cd28 4750qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 4751{
4752 struct fc_rport_identifiers rport_ids;
bdf79621 4753 struct fc_rport *rport;
044d78e1 4754 unsigned long flags;
8482e118 4755
f8b02a85
AV		 4756 rport_ids.node_name = wwn_to_u64(fcport->node_name);
4757 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 4758 rport_ids.port_id = fcport->d_id.b.domain << 16 |
4759 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 4760 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 4761 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 4762 if (!rport) {
7c3df132
SK		 4763 ql_log(ql_log_warn, vha, 0x2006,
4764 "Unable to allocate fc remote port.\n");
77d74143
AV		 4765 return;
4766 }
2d70c103 4767
044d78e1 4768 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 4769 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 4770 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 4771
ad3e0eda 4772 rport->supported_classes = fcport->supported_classes;
77d74143 4773
8482e118 4774 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
4775 if (fcport->port_type == FCT_INITIATOR)
4776 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
4777 if (fcport->port_type == FCT_TARGET)
4778 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548 4779
83548fe2
QT		 4780 ql_dbg(ql_dbg_disc, vha, 0x20ee,
4781 "%s %8phN. rport %p is %s mode\n",
4782 __func__, fcport->port_name, rport,
4783 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
726b8548 4784
77d74143 4785 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 4786}
4787
23be331d
AB		 4788/*
4789 * qla2x00_update_fcport
4790 * Updates device on list.
4791 *
4792 * Input:
4793 * ha = adapter block pointer.
4794 * fcport = port structure pointer.
4795 *
4796 * Return:
4797 * 0 - Success
4798 * BIT_0 - error
4799 *
4800 * Context:
4801 * Kernel context.
4802 */
4803void
e315cd28 4804qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 4805{
e315cd28 4806 fcport->vha = vha;
8ae6d9c7 4807
726b8548
QT		 4808 if (IS_SW_RESV_ADDR(fcport->d_id))
4809 return;
4810
83548fe2 4811 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
726b8548
QT		 4812 __func__, fcport->port_name);
4813
8ae6d9c7
GM		 4814 if (IS_QLAFX00(vha->hw)) {
4815 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 4816 goto reg_port;
8ae6d9c7 4817 }
23be331d 4818 fcport->login_retry = 0;
5ff1d584 4819 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
726b8548
QT		 4820 fcport->disc_state = DSC_LOGIN_COMPLETE;
4821 fcport->deleted = 0;
4822 fcport->logout_on_delete = 1;
23be331d 4823
e84067d7
DG		 4824 if (fcport->fc4f_nvme) {
4825 qla_nvme_register_remote(vha, fcport);
4826 return;
4827 }
4828
1f93da52 4829 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 4830 qla2x00_iidma_fcport(vha, fcport);
21090cbe 4831 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 4832
4833reg_port:
726b8548
QT		 4834 switch (vha->host->active_mode) {
4835 case MODE_INITIATOR:
d20ed91b 4836 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4837 break;
4838 case MODE_TARGET:
4839 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4840 !vha->vha_tgt.qla_tgt->tgt_stopped)
4841 qlt_fc_port_added(vha, fcport);
4842 break;
4843 case MODE_DUAL:
d20ed91b 4844 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4845 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4846 !vha->vha_tgt.qla_tgt->tgt_stopped)
4847 qlt_fc_port_added(vha, fcport);
4848 break;
4849 default:
4850 break;
d20ed91b 4851 }
23be331d
AB		 4852}
4853
1da177e4
LT		 4854/*
4855 * qla2x00_configure_fabric
4856 * Setup SNS devices with loop ID's.
4857 *
4858 * Input:
4859 * ha = adapter block pointer.
4860 *
4861 * Returns:
4862 * 0 = success.
4863 * BIT_0 = error
4864 */
4865static int
e315cd28 4866qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 4867{
b3b02e6e 4868 int rval;
726b8548 4869 fc_port_t *fcport;
1da177e4 4870 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 4871 uint16_t loop_id;
1da177e4 4872 LIST_HEAD(new_fcports);
e315cd28 4873 struct qla_hw_data *ha = vha->hw;
df673274 4874 int discovery_gen;
1da177e4
LT		 4875
4876 /* If FL port exists, then SNS is present */
e428924c 4877 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 4878 loop_id = NPH_F_PORT;
4879 else
4880 loop_id = SNS_FL_PORT;
e315cd28 4881 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 4882 if (rval != QLA_SUCCESS) {
83548fe2 4883 ql_dbg(ql_dbg_disc, vha, 0x20a0,
7c3df132 4884 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 4885
e315cd28 4886 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 4887 return (QLA_SUCCESS);
4888 }
e315cd28 4889 vha->device_flags |= SWITCH_FOUND;
1da177e4 4890
41dc529a
QT		 4891
4892 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
4893 rval = qla2x00_send_change_request(vha, 0x3, 0);
4894 if (rval != QLA_SUCCESS)
4895 ql_log(ql_log_warn, vha, 0x121,
4896 "Failed to enable receiving of RSCN requests: 0x%x.\n",
4897 rval);
4898 }
4899
4900
1da177e4 4901 do {
726b8548
QT		 4902 qla2x00_mgmt_svr_login(vha);
4903
cca5335c
AV		 4904 /* FDMI support. */
4905 if (ql2xfdmienable &&
e315cd28
AC		 4906 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
4907 qla2x00_fdmi_register(vha);
cca5335c 4908
1da177e4 4909 /* Ensure we are logged into the SNS. */
a14c7711 4910 loop_id = NPH_SNS_LID(ha);
0b91d116
CD		 4911 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
4912 0xfc, mb, BIT_1|BIT_0);
a14c7711
JC		 4913 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
4914 ql_dbg(ql_dbg_disc, vha, 0x20a1,
4915 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
4916 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
0b91d116 4917 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 4918 return rval;
0b91d116 4919 }
e315cd28
AC		 4920 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
4921 if (qla2x00_rft_id(vha)) {
1da177e4 4922 /* EMPTY */
83548fe2 4923 ql_dbg(ql_dbg_disc, vha, 0x20a2,
7c3df132 4924 "Register FC-4 TYPE failed.\n");
b98ae0d7
QT		 4925 if (test_bit(LOOP_RESYNC_NEEDED,
4926 &vha->dpc_flags))
4927 break;
1da177e4 4928 }
d3bae931 4929 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
1da177e4 4930 /* EMPTY */
83548fe2 4931 ql_dbg(ql_dbg_disc, vha, 0x209a,
7c3df132 4932 "Register FC-4 Features failed.\n");
b98ae0d7
QT		 4933 if (test_bit(LOOP_RESYNC_NEEDED,
4934 &vha->dpc_flags))
4935 break;
1da177e4 4936 }
d3bae931
DG		 4937 if (vha->flags.nvme_enabled) {
4938 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
4939 ql_dbg(ql_dbg_disc, vha, 0x2049,
4940 "Register NVME FC Type Features failed.\n");
4941 }
4942 }
e315cd28 4943 if (qla2x00_rnn_id(vha)) {
1da177e4 4944 /* EMPTY */
83548fe2 4945 ql_dbg(ql_dbg_disc, vha, 0x2104,
7c3df132 4946 "Register Node Name failed.\n");
b98ae0d7
QT		 4947 if (test_bit(LOOP_RESYNC_NEEDED,
4948 &vha->dpc_flags))
4949 break;
e315cd28 4950 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 4951 /* EMPTY */
83548fe2 4952 ql_dbg(ql_dbg_disc, vha, 0x209b,
0bf0efa1 4953 "Register Symbolic Node Name failed.\n");
b98ae0d7
QT		 4954 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4955 break;
1da177e4
LT		 4956 }
4957 }
4958
827210ba
JC		 4959 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4960 fcport->scan_state = QLA_FCPORT_SCAN;
4961 }
4962
df673274
AP		 4963 /* Mark the time right before querying FW for connected ports.
4964 * This process is long, asynchronous and by the time it's done,
4965 * collected information might not be accurate anymore. E.g.
4966 * disconnected port might have re-connected and a brand new
4967 * session has been created. In this case session's generation
4968 * will be newer than discovery_gen. */
4969 qlt_do_generation_tick(vha, &discovery_gen);
4970
726b8548 4971 rval = qla2x00_find_all_fabric_devs(vha);
1da177e4
LT		 4972 if (rval != QLA_SUCCESS)
4973 break;
1da177e4
LT		 4974 } while (0);
4975
e84067d7
DG		 4976 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
4977 qla_nvme_register_hba(vha);
4978
726b8548 4979 if (rval)
7c3df132
SK		 4980 ql_dbg(ql_dbg_disc, vha, 0x2068,
4981 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 4982
4983 return (rval);
4984}
4985
1da177e4
LT		 4986/*
4987 * qla2x00_find_all_fabric_devs
4988 *
4989 * Input:
4990 * ha = adapter block pointer.
4991 * dev = database device entry pointer.
4992 *
4993 * Returns:
4994 * 0 = success.
4995 *
4996 * Context:
4997 * Kernel context.
4998 */
4999static int
726b8548 5000qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 5001{
5002 int rval;
5003 uint16_t loop_id;
726b8548 5004 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 5005 int found;
5006
5007 sw_info_t *swl;
5008 int swl_idx;
5009 int first_dev, last_dev;
1516ef44 5010 port_id_t wrap = {}, nxt_d_id;
e315cd28 5011 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 5012 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 5013 unsigned long flags;
1da177e4
LT		 5014
5015 rval = QLA_SUCCESS;
5016
5017 /* Try GID_PT to get device list, else GAN. */
7a67735b 5018 if (!ha->swl)
642ef983 5019 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 5020 GFP_KERNEL);
5021 swl = ha->swl;
bbfbbbc1 5022 if (!swl) {
1da177e4 5023 /*EMPTY*/
83548fe2 5024 ql_dbg(ql_dbg_disc, vha, 0x209c,
7c3df132 5025 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 5026 } else {
642ef983 5027 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 5028 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 5029 swl = NULL;
b98ae0d7
QT		 5030 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5031 return rval;
e315cd28 5032 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5033 swl = NULL;
b98ae0d7
QT		 5034 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5035 return rval;
e315cd28 5036 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 5037 swl = NULL;
b98ae0d7
QT		 5038 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5039 return rval;
726b8548
QT		 5040 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
5041 swl = NULL;
b98ae0d7
QT		 5042 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5043 return rval;
1da177e4 5044 }
e8c72ba5
CD		 5045
5046 /* If other queries succeeded probe for FC-4 type */
b98ae0d7 5047 if (swl) {
e8c72ba5 5048 qla2x00_gff_id(vha, swl);
b98ae0d7
QT		 5049 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5050 return rval;
5051 }
1da177e4
LT		 5052 }
5053 swl_idx = 0;
5054
5055 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 5056 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5057 if (new_fcport == NULL) {
83548fe2 5058 ql_log(ql_log_warn, vha, 0x209d,
7c3df132 5059 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 5060 return (QLA_MEMORY_ALLOC_FAILED);
5061 }
5062 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 5063 /* Set start port ID scan at adapter ID. */
5064 first_dev = 1;
5065 last_dev = 0;
5066
5067 /* Starting free loop ID. */
e315cd28
AC		 5068 loop_id = ha->min_external_loopid;
5069 for (; loop_id <= ha->max_loop_id; loop_id++) {
5070 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 5071 continue;
5072
3a6478df
GM		 5073 if (ha->current_topology == ISP_CFG_FL &&
5074 (atomic_read(&vha->loop_down_timer) ||
5075 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 5076 atomic_set(&vha->loop_down_timer, 0);
5077 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5078 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 5079 break;
bb2d52b2 5080 }
1da177e4
LT		 5081
5082 if (swl != NULL) {
5083 if (last_dev) {
5084 wrap.b24 = new_fcport->d_id.b24;
5085 } else {
5086 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
5087 memcpy(new_fcport->node_name,
5088 swl[swl_idx].node_name, WWN_SIZE);
5089 memcpy(new_fcport->port_name,
5090 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 5091 memcpy(new_fcport->fabric_port_name,
5092 swl[swl_idx].fabric_port_name, WWN_SIZE);
5093 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 5094 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4 5095
a5d42f4c 5096 new_fcport->nvme_flag = 0;
1a28faa0 5097 new_fcport->fc4f_nvme = 0;
a5d42f4c
DG		 5098 if (vha->flags.nvme_enabled &&
5099 swl[swl_idx].fc4f_nvme) {
5100 new_fcport->fc4f_nvme =
5101 swl[swl_idx].fc4f_nvme;
5102 ql_log(ql_log_info, vha, 0x2131,
5103 "FOUND: NVME port %8phC as FC Type 28h\n",
5104 new_fcport->port_name);
5105 }
5106
1da177e4
LT		 5107 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
5108 last_dev = 1;
5109 }
5110 swl_idx++;
5111 }
5112 } else {
5113 /* Send GA_NXT to the switch */
e315cd28 5114 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 5115 if (rval != QLA_SUCCESS) {
83548fe2 5116 ql_log(ql_log_warn, vha, 0x209e,
7c3df132
SK		 5117 "SNS scan failed -- assuming "
5118 "zero-entry result.\n");
1da177e4
LT		 5119 rval = QLA_SUCCESS;
5120 break;
5121 }
5122 }
5123
5124 /* If wrap on switch device list, exit. */
5125 if (first_dev) {
5126 wrap.b24 = new_fcport->d_id.b24;
5127 first_dev = 0;
5128 } else if (new_fcport->d_id.b24 == wrap.b24) {
83548fe2 5129 ql_dbg(ql_dbg_disc, vha, 0x209f,
7c3df132
SK		 5130 "Device wrap (%02x%02x%02x).\n",
5131 new_fcport->d_id.b.domain,
5132 new_fcport->d_id.b.area,
5133 new_fcport->d_id.b.al_pa);
1da177e4
LT		 5134 break;
5135 }
5136
2c3dfe3f 5137 /* Bypass if same physical adapter. */
e315cd28 5138 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 5139 continue;
5140
2c3dfe3f 5141 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 5142 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
5143 continue;
2c3dfe3f 5144
f7d289f6
AV		 5145 /* Bypass if same domain and area of adapter. */
5146 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 5147 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 5148 ISP_CFG_FL)
5149 continue;
5150
1da177e4
LT		 5151 /* Bypass reserved domain fields. */
5152 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
5153 continue;
5154
e8c72ba5 5155 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 5156 if (ql2xgffidenable &&
5157 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
5158 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 5159 continue;
5160
726b8548
QT		 5161 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5162
1da177e4
LT		 5163 /* Locate matching device in database. */
5164 found = 0;
e315cd28 5165 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5166 if (memcmp(new_fcport->port_name, fcport->port_name,
5167 WWN_SIZE))
5168 continue;
5169
827210ba 5170 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 5171
1da177e4
LT		 5172 found++;
5173
d8b45213
AV		 5174 /* Update port state. */
5175 memcpy(fcport->fabric_port_name,
5176 new_fcport->fabric_port_name, WWN_SIZE);
5177 fcport->fp_speed = new_fcport->fp_speed;
5178
1da177e4 5179 /*
b2032fd5
RD		 5180 * If address the same and state FCS_ONLINE
5181 * (or in target mode), nothing changed.
1da177e4
LT		 5182 */
5183 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 5184 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 5185 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 5186 break;
5187 }
5188
5189 /*
5190 * If device was not a fabric device before.
5191 */
5192 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
5193 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 5194 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 5195 fcport->flags |= (FCF_FABRIC_DEVICE |
5196 FCF_LOGIN_NEEDED);
1da177e4
LT		 5197 break;
5198 }
5199
5200 /*
5201 * Port ID changed or device was marked to be updated;
5202 * Log it out if still logged in and mark it for
5203 * relogin later.
5204 */
726b8548 5205 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 5206 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
5207 "port changed FC ID, %8phC"
5208 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
5209 fcport->port_name,
5210 fcport->d_id.b.domain,
5211 fcport->d_id.b.area,
5212 fcport->d_id.b.al_pa,
5213 fcport->loop_id,
5214 new_fcport->d_id.b.domain,
5215 new_fcport->d_id.b.area,
5216 new_fcport->d_id.b.al_pa);
5217 fcport->d_id.b24 = new_fcport->d_id.b24;
5218 break;
5219 }
5220
1da177e4
LT		 5221 fcport->d_id.b24 = new_fcport->d_id.b24;
5222 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 5223 break;
5224 }
5225
726b8548
QT		 5226 if (found) {
5227 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 5228 continue;
726b8548 5229 }
1da177e4 5230 /* If device was not in our fcports list, then add it. */
b2032fd5 5231 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 5232 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5233
5234 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5235
1da177e4
LT		 5236
5237 /* Allocate a new replacement fcport. */
5238 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 5239 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5240 if (new_fcport == NULL) {
83548fe2 5241 ql_log(ql_log_warn, vha, 0xd032,
7c3df132 5242 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5243 return (QLA_MEMORY_ALLOC_FAILED);
5244 }
5245 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5246 new_fcport->d_id.b24 = nxt_d_id.b24;
5247 }
5248
726b8548
QT		 5249 qla2x00_free_fcport(new_fcport);
5250
5251 /*
5252 * Logout all previous fabric dev marked lost, except FCP2 devices.
5253 */
5254 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5255 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5256 break;
5257
5258 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
5259 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
5260 continue;
5261
5262 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5263 if ((qla_dual_mode_enabled(vha) ||
5264 qla_ini_mode_enabled(vha)) &&
5265 atomic_read(&fcport->state) == FCS_ONLINE) {
5266 qla2x00_mark_device_lost(vha, fcport,
5267 ql2xplogiabsentdevice, 0);
5268 if (fcport->loop_id != FC_NO_LOOP_ID &&
5269 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5270 fcport->port_type != FCT_INITIATOR &&
5271 fcport->port_type != FCT_BROADCAST) {
83548fe2 5272 ql_dbg(ql_dbg_disc, vha, 0x20f0,
726b8548
QT		 5273 "%s %d %8phC post del sess\n",
5274 __func__, __LINE__,
5275 fcport->port_name);
5276
5277 qlt_schedule_sess_for_deletion_lock
5278 (fcport);
5279 continue;
5280 }
5281 }
5282 }
1da177e4 5283
726b8548
QT		 5284 if (fcport->scan_state == QLA_FCPORT_FOUND)
5285 qla24xx_fcport_handle_login(vha, fcport);
5286 }
1da177e4
LT		 5287 return (rval);
5288}
5289
5290/*
5291 * qla2x00_find_new_loop_id
5292 * Scan through our port list and find a new usable loop ID.
5293 *
5294 * Input:
5295 * ha: adapter state pointer.
5296 * dev: port structure pointer.
5297 *
5298 * Returns:
5299 * qla2x00 local function return status code.
5300 *
5301 * Context:
5302 * Kernel context.
5303 */
03bcfb57 5304int
e315cd28 5305qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 5306{
5307 int rval;
e315cd28 5308 struct qla_hw_data *ha = vha->hw;
feafb7b1 5309 unsigned long flags = 0;
1da177e4
LT		 5310
5311 rval = QLA_SUCCESS;
5312
5f16b331 5313 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 5314
5f16b331
CD		 5315 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
5316 LOOPID_MAP_SIZE);
5317 if (dev->loop_id >= LOOPID_MAP_SIZE ||
5318 qla2x00_is_reserved_id(vha, dev->loop_id)) {
5319 dev->loop_id = FC_NO_LOOP_ID;
5320 rval = QLA_FUNCTION_FAILED;
5321 } else
5322 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 5323
5f16b331 5324 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 5325
5f16b331
CD		 5326 if (rval == QLA_SUCCESS)
5327 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
5328 "Assigning new loopid=%x, portid=%x.\n",
5329 dev->loop_id, dev->d_id.b24);
5330 else
5331 ql_log(ql_log_warn, dev->vha, 0x2087,
5332 "No loop_id's available, portid=%x.\n",
5333 dev->d_id.b24);
1da177e4
LT		 5334
5335 return (rval);
5336}
5337
1da177e4
LT		 5338
5339/*
5340 * qla2x00_fabric_login
5341 * Issue fabric login command.
5342 *
5343 * Input:
5344 * ha = adapter block pointer.
5345 * device = pointer to FC device type structure.
5346 *
5347 * Returns:
5348 * 0 - Login successfully
5349 * 1 - Login failed
5350 * 2 - Initiator device
5351 * 3 - Fatal error
5352 */
5353int
e315cd28 5354qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 5355 uint16_t *next_loopid)
5356{
5357 int rval;
5358 int retry;
5359 uint16_t tmp_loopid;
5360 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5361 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 5362
5363 retry = 0;
5364 tmp_loopid = 0;
5365
5366 for (;;) {
7c3df132
SK		 5367 ql_dbg(ql_dbg_disc, vha, 0x2000,
5368 "Trying Fabric Login w/loop id 0x%04x for port "
5369 "%02x%02x%02x.\n",
5370 fcport->loop_id, fcport->d_id.b.domain,
5371 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5372
5373 /* Login fcport on switch. */
0b91d116 5374 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 5375 fcport->d_id.b.domain, fcport->d_id.b.area,
5376 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 5377 if (rval != QLA_SUCCESS) {
5378 return rval;
5379 }
1da177e4
LT		 5380 if (mb[0] == MBS_PORT_ID_USED) {
5381 /*
5382 * Device has another loop ID. The firmware team
0107109e
AV		 5383 * recommends the driver perform an implicit login with
5384 * the specified ID again. The ID we just used is save
5385 * here so we return with an ID that can be tried by
5386 * the next login.
1da177e4
LT		 5387 */
5388 retry++;
5389 tmp_loopid = fcport->loop_id;
5390 fcport->loop_id = mb[1];
5391
7c3df132
SK		 5392 ql_dbg(ql_dbg_disc, vha, 0x2001,
5393 "Fabric Login: port in use - next loop "
5394 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 5395 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 5396 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5397
5398 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
5399 /*
5400 * Login succeeded.
5401 */
5402 if (retry) {
5403 /* A retry occurred before. */
5404 *next_loopid = tmp_loopid;
5405 } else {
5406 /*
5407 * No retry occurred before. Just increment the
5408 * ID value for next login.
5409 */
5410 *next_loopid = (fcport->loop_id + 1);
5411 }
5412
5413 if (mb[1] & BIT_0) {
5414 fcport->port_type = FCT_INITIATOR;
5415 } else {
5416 fcport->port_type = FCT_TARGET;
5417 if (mb[1] & BIT_1) {
8474f3a0 5418 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 5419 }
5420 }
5421
ad3e0eda
AV		 5422 if (mb[10] & BIT_0)
5423 fcport->supported_classes |= FC_COS_CLASS2;
5424 if (mb[10] & BIT_1)
5425 fcport->supported_classes |= FC_COS_CLASS3;
5426
2d70c103
NB		 5427 if (IS_FWI2_CAPABLE(ha)) {
5428 if (mb[10] & BIT_7)
5429 fcport->flags |=
5430 FCF_CONF_COMP_SUPPORTED;
5431 }
5432
1da177e4
LT		 5433 rval = QLA_SUCCESS;
5434 break;
5435 } else if (mb[0] == MBS_LOOP_ID_USED) {
5436 /*
5437 * Loop ID already used, try next loop ID.
5438 */
5439 fcport->loop_id++;
e315cd28 5440 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 5441 if (rval != QLA_SUCCESS) {
5442 /* Ran out of loop IDs to use */
5443 break;
5444 }
5445 } else if (mb[0] == MBS_COMMAND_ERROR) {
5446 /*
5447 * Firmware possibly timed out during login. If NO
5448 * retries are left to do then the device is declared
5449 * dead.
5450 */
5451 *next_loopid = fcport->loop_id;
e315cd28 5452 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5453 fcport->d_id.b.domain, fcport->d_id.b.area,
5454 fcport->d_id.b.al_pa);
e315cd28 5455 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 5456
5457 rval = 1;
5458 break;
5459 } else {
5460 /*
5461 * unrecoverable / not handled error
5462 */
7c3df132
SK		 5463 ql_dbg(ql_dbg_disc, vha, 0x2002,
5464 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
5465 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
5466 fcport->d_id.b.area, fcport->d_id.b.al_pa,
5467 fcport->loop_id, jiffies);
1da177e4
LT		 5468
5469 *next_loopid = fcport->loop_id;
e315cd28 5470 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5471 fcport->d_id.b.domain, fcport->d_id.b.area,
5472 fcport->d_id.b.al_pa);
5f16b331 5473 qla2x00_clear_loop_id(fcport);
0eedfcf0 5474 fcport->login_retry = 0;
1da177e4
LT		 5475
5476 rval = 3;
5477 break;
5478 }
5479 }
5480
5481 return (rval);
5482}
5483
5484/*
5485 * qla2x00_local_device_login
5486 * Issue local device login command.
5487 *
5488 * Input:
5489 * ha = adapter block pointer.
5490 * loop_id = loop id of device to login to.
5491 *
5492 * Returns (Where's the #define!!!!):
5493 * 0 - Login successfully
5494 * 1 - Login failed
5495 * 3 - Fatal error
5496 */
5497int
e315cd28 5498qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 5499{
5500 int rval;
5501 uint16_t mb[MAILBOX_REGISTER_COUNT];
5502
5503 memset(mb, 0, sizeof(mb));
e315cd28 5504 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 5505 if (rval == QLA_SUCCESS) {
5506 /* Interrogate mailbox registers for any errors */
5507 if (mb[0] == MBS_COMMAND_ERROR)
5508 rval = 1;
5509 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
5510 /* device not in PCB table */
5511 rval = 3;
5512 }
5513
5514 return (rval);
5515}
5516
5517/*
5518 * qla2x00_loop_resync
5519 * Resync with fibre channel devices.
5520 *
5521 * Input:
5522 * ha = adapter block pointer.
5523 *
5524 * Returns:
5525 * 0 = success
5526 */
5527int
e315cd28 5528qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 5529{
73208dfd 5530 int rval = QLA_SUCCESS;
1da177e4 5531 uint32_t wait_time;
67c2e93a
AC		 5532 struct req_que *req;
5533 struct rsp_que *rsp;
5534
d7459527 5535 req = vha->req;
67c2e93a 5536 rsp = req->rsp;
1da177e4 5537
e315cd28
AC		 5538 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5539 if (vha->flags.online) {
5540 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 5541 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5542 wait_time = 256;
5543 do {
8ae6d9c7
GM		 5544 if (!IS_QLAFX00(vha->hw)) {
5545 /*
5546 * Issue a marker after FW becomes
5547 * ready.
5548 */
5549 qla2x00_marker(vha, req, rsp, 0, 0,
5550 MK_SYNC_ALL);
5551 vha->marker_needed = 0;
5552 }
1da177e4
LT		 5553
5554 /* Remap devices on Loop. */
e315cd28 5555 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 5556
8ae6d9c7
GM		 5557 if (IS_QLAFX00(vha->hw))
5558 qlafx00_configure_devices(vha);
5559 else
5560 qla2x00_configure_loop(vha);
5561
1da177e4 5562 wait_time--;
e315cd28
AC		 5563 } while (!atomic_read(&vha->loop_down_timer) &&
5564 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
5565 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
5566 &vha->dpc_flags)));
1da177e4 5567 }
1da177e4
LT		 5568 }
5569
e315cd28 5570 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 5571 return (QLA_FUNCTION_FAILED);
1da177e4 5572
e315cd28 5573 if (rval)
7c3df132
SK		 5574 ql_dbg(ql_dbg_disc, vha, 0x206c,
5575 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 5576
5577 return (rval);
5578}
5579
579d12b5
SK		 5580/*
5581* qla2x00_perform_loop_resync
5582* Description: This function will set the appropriate flags and call
5583* qla2x00_loop_resync. If successful loop will be resynced
5584* Arguments : scsi_qla_host_t pointer
5585* returm : Success or Failure
5586*/
5587
5588int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
5589{
5590 int32_t rval = 0;
5591
5592 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
5593 /*Configure the flags so that resync happens properly*/
5594 atomic_set(&ha->loop_down_timer, 0);
5595 if (!(ha->device_flags & DFLG_NO_CABLE)) {
5596 atomic_set(&ha->loop_state, LOOP_UP);
5597 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
5598 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
5599 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
5600
5601 rval = qla2x00_loop_resync(ha);
5602 } else
5603 atomic_set(&ha->loop_state, LOOP_DEAD);
5604
5605 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
5606 }
5607
5608 return rval;
5609}
5610
d97994dc 5611void
67becc00 5612qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 5613{
5614 fc_port_t *fcport;
feafb7b1
AE		 5615 struct scsi_qla_host *vha;
5616 struct qla_hw_data *ha = base_vha->hw;
5617 unsigned long flags;
d97994dc 5618
feafb7b1 5619 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 5620 /* Go with deferred removal of rport references. */
feafb7b1
AE		 5621 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
5622 atomic_inc(&vha->vref_count);
5623 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 5624 if (fcport->drport &&
feafb7b1
AE		 5625 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
5626 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 5627 qla2x00_rport_del(fcport);
df673274 5628
feafb7b1
AE		 5629 spin_lock_irqsave(&ha->vport_slock, flags);
5630 }
5631 }
5632 atomic_dec(&vha->vref_count);
c4a9b538 5633 wake_up(&vha->vref_waitq);
feafb7b1
AE		 5634 }
5635 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 5636}
5637
7d613ac6
SV		 5638/* Assumes idc_lock always held on entry */
5639void
5640qla83xx_reset_ownership(scsi_qla_host_t *vha)
5641{
5642 struct qla_hw_data *ha = vha->hw;
5643 uint32_t drv_presence, drv_presence_mask;
5644 uint32_t dev_part_info1, dev_part_info2, class_type;
5645 uint32_t class_type_mask = 0x3;
5646 uint16_t fcoe_other_function = 0xffff, i;
5647
7ec0effd
AD		 5648 if (IS_QLA8044(ha)) {
5649 drv_presence = qla8044_rd_direct(vha,
5650 QLA8044_CRB_DRV_ACTIVE_INDEX);
5651 dev_part_info1 = qla8044_rd_direct(vha,
5652 QLA8044_CRB_DEV_PART_INFO_INDEX);
5653 dev_part_info2 = qla8044_rd_direct(vha,
5654 QLA8044_CRB_DEV_PART_INFO2);
5655 } else {
5656 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5657 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
5658 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
5659 }
7d613ac6
SV		 5660 for (i = 0; i < 8; i++) {
5661 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
5662 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5663 (i != ha->portnum)) {
5664 fcoe_other_function = i;
5665 break;
5666 }
5667 }
5668 if (fcoe_other_function == 0xffff) {
5669 for (i = 0; i < 8; i++) {
5670 class_type = ((dev_part_info2 >> (i * 4)) &
5671 class_type_mask);
5672 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5673 ((i + 8) != ha->portnum)) {
5674 fcoe_other_function = i + 8;
5675 break;
5676 }
5677 }
5678 }
5679 /*
5680 * Prepare drv-presence mask based on fcoe functions present.
5681 * However consider only valid physical fcoe function numbers (0-15).
5682 */
5683 drv_presence_mask = ~((1 << (ha->portnum)) |
5684 ((fcoe_other_function == 0xffff) ?
5685 0 : (1 << (fcoe_other_function))));
5686
5687 /* We are the reset owner iff:
5688 * - No other protocol drivers present.
5689 * - This is the lowest among fcoe functions. */
5690 if (!(drv_presence & drv_presence_mask) &&
5691 (ha->portnum < fcoe_other_function)) {
5692 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
5693 "This host is Reset owner.\n");
5694 ha->flags.nic_core_reset_owner = 1;
5695 }
5696}
5697
fa492630 5698static int
7d613ac6
SV		 5699__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
5700{
5701 int rval = QLA_SUCCESS;
5702 struct qla_hw_data *ha = vha->hw;
5703 uint32_t drv_ack;
5704
5705 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5706 if (rval == QLA_SUCCESS) {
5707 drv_ack |= (1 << ha->portnum);
5708 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5709 }
5710
5711 return rval;
5712}
5713
fa492630 5714static int
7d613ac6
SV		 5715__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
5716{
5717 int rval = QLA_SUCCESS;
5718 struct qla_hw_data *ha = vha->hw;
5719 uint32_t drv_ack;
5720
5721 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5722 if (rval == QLA_SUCCESS) {
5723 drv_ack &= ~(1 << ha->portnum);
5724 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5725 }
5726
5727 return rval;
5728}
5729
fa492630 5730static const char *
7d613ac6
SV		 5731qla83xx_dev_state_to_string(uint32_t dev_state)
5732{
5733 switch (dev_state) {
5734 case QLA8XXX_DEV_COLD:
5735 return "COLD/RE-INIT";
5736 case QLA8XXX_DEV_INITIALIZING:
5737 return "INITIALIZING";
5738 case QLA8XXX_DEV_READY:
5739 return "READY";
5740 case QLA8XXX_DEV_NEED_RESET:
5741 return "NEED RESET";
5742 case QLA8XXX_DEV_NEED_QUIESCENT:
5743 return "NEED QUIESCENT";
5744 case QLA8XXX_DEV_FAILED:
5745 return "FAILED";
5746 case QLA8XXX_DEV_QUIESCENT:
5747 return "QUIESCENT";
5748 default:
5749 return "Unknown";
5750 }
5751}
5752
5753/* Assumes idc-lock always held on entry */
5754void
5755qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
5756{
5757 struct qla_hw_data *ha = vha->hw;
5758 uint32_t idc_audit_reg = 0, duration_secs = 0;
5759
5760 switch (audit_type) {
5761 case IDC_AUDIT_TIMESTAMP:
5762 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
5763 idc_audit_reg = (ha->portnum) |
5764 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
5765 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5766 break;
5767
5768 case IDC_AUDIT_COMPLETION:
5769 duration_secs = ((jiffies_to_msecs(jiffies) -
5770 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
5771 idc_audit_reg = (ha->portnum) |
5772 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
5773 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5774 break;
5775
5776 default:
5777 ql_log(ql_log_warn, vha, 0xb078,
5778 "Invalid audit type specified.\n");
5779 break;
5780 }
5781}
5782
5783/* Assumes idc_lock always held on entry */
fa492630 5784static int
7d613ac6
SV		 5785qla83xx_initiating_reset(scsi_qla_host_t *vha)
5786{
5787 struct qla_hw_data *ha = vha->hw;
5788 uint32_t idc_control, dev_state;
5789
5790 __qla83xx_get_idc_control(vha, &idc_control);
5791 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
5792 ql_log(ql_log_info, vha, 0xb080,
5793 "NIC Core reset has been disabled. idc-control=0x%x\n",
5794 idc_control);
5795 return QLA_FUNCTION_FAILED;
5796 }
5797
5798 /* Set NEED-RESET iff in READY state and we are the reset-owner */
5799 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5800 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
5801 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
5802 QLA8XXX_DEV_NEED_RESET);
5803 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
5804 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
5805 } else {
5806 const char *state = qla83xx_dev_state_to_string(dev_state);
5807 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
5808
5809 /* SV: XXX: Is timeout required here? */
5810 /* Wait for IDC state change READY -> NEED_RESET */
5811 while (dev_state == QLA8XXX_DEV_READY) {
5812 qla83xx_idc_unlock(vha, 0);
5813 msleep(200);
5814 qla83xx_idc_lock(vha, 0);
5815 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5816 }
5817 }
5818
5819 /* Send IDC ack by writing to drv-ack register */
5820 __qla83xx_set_drv_ack(vha);
5821
5822 return QLA_SUCCESS;
5823}
5824
5825int
5826__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
5827{
5828 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5829}
5830
7d613ac6
SV		 5831int
5832__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
5833{
5834 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5835}
5836
fa492630 5837static int
7d613ac6
SV		 5838qla83xx_check_driver_presence(scsi_qla_host_t *vha)
5839{
5840 uint32_t drv_presence = 0;
5841 struct qla_hw_data *ha = vha->hw;
5842
5843 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5844 if (drv_presence & (1 << ha->portnum))
5845 return QLA_SUCCESS;
5846 else
5847 return QLA_TEST_FAILED;
5848}
5849
5850int
5851qla83xx_nic_core_reset(scsi_qla_host_t *vha)
5852{
5853 int rval = QLA_SUCCESS;
5854 struct qla_hw_data *ha = vha->hw;
5855
5856 ql_dbg(ql_dbg_p3p, vha, 0xb058,
5857 "Entered %s().\n", __func__);
5858
5859 if (vha->device_flags & DFLG_DEV_FAILED) {
5860 ql_log(ql_log_warn, vha, 0xb059,
5861 "Device in unrecoverable FAILED state.\n");
5862 return QLA_FUNCTION_FAILED;
5863 }
5864
5865 qla83xx_idc_lock(vha, 0);
5866
5867 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
5868 ql_log(ql_log_warn, vha, 0xb05a,
5869 "Function=0x%x has been removed from IDC participation.\n",
5870 ha->portnum);
5871 rval = QLA_FUNCTION_FAILED;
5872 goto exit;
5873 }
5874
5875 qla83xx_reset_ownership(vha);
5876
5877 rval = qla83xx_initiating_reset(vha);
5878
5879 /*
5880 * Perform reset if we are the reset-owner,
5881 * else wait till IDC state changes to READY/FAILED.
5882 */
5883 if (rval == QLA_SUCCESS) {
5884 rval = qla83xx_idc_state_handler(vha);
5885
5886 if (rval == QLA_SUCCESS)
5887 ha->flags.nic_core_hung = 0;
5888 __qla83xx_clear_drv_ack(vha);
5889 }
5890
5891exit:
5892 qla83xx_idc_unlock(vha, 0);
5893
5894 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
5895
5896 return rval;
5897}
5898
81178772
SK		 5899int
5900qla2xxx_mctp_dump(scsi_qla_host_t *vha)
5901{
5902 struct qla_hw_data *ha = vha->hw;
5903 int rval = QLA_FUNCTION_FAILED;
5904
5905 if (!IS_MCTP_CAPABLE(ha)) {
5906 /* This message can be removed from the final version */
5907 ql_log(ql_log_info, vha, 0x506d,
5908 "This board is not MCTP capable\n");
5909 return rval;
5910 }
5911
5912 if (!ha->mctp_dump) {
5913 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
5914 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
5915
5916 if (!ha->mctp_dump) {
5917 ql_log(ql_log_warn, vha, 0x506e,
5918 "Failed to allocate memory for mctp dump\n");
5919 return rval;
5920 }
5921 }
5922
5923#define MCTP_DUMP_STR_ADDR 0x00000000
5924 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
5925 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
5926 if (rval != QLA_SUCCESS) {
5927 ql_log(ql_log_warn, vha, 0x506f,
5928 "Failed to capture mctp dump\n");
5929 } else {
5930 ql_log(ql_log_info, vha, 0x5070,
5931 "Mctp dump capture for host (%ld/%p).\n",
5932 vha->host_no, ha->mctp_dump);
5933 ha->mctp_dumped = 1;
5934 }
5935
409ee0fe 5936 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 5937 ha->flags.nic_core_reset_hdlr_active = 1;
5938 rval = qla83xx_restart_nic_firmware(vha);
5939 if (rval)
5940 /* NIC Core reset failed. */
5941 ql_log(ql_log_warn, vha, 0x5071,
5942 "Failed to restart nic firmware\n");
5943 else
5944 ql_dbg(ql_dbg_p3p, vha, 0xb084,
5945 "Restarted NIC firmware successfully.\n");
5946 ha->flags.nic_core_reset_hdlr_active = 0;
5947 }
5948
5949 return rval;
5950
5951}
5952
579d12b5 5953/*
8fcd6b8b 5954* qla2x00_quiesce_io
579d12b5
SK		 5955* Description: This function will block the new I/Os
5956* Its not aborting any I/Os as context
5957* is not destroyed during quiescence
5958* Arguments: scsi_qla_host_t
5959* return : void
5960*/
5961void
8fcd6b8b 5962qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 5963{
5964 struct qla_hw_data *ha = vha->hw;
5965 struct scsi_qla_host *vp;
5966
8fcd6b8b
CD		 5967 ql_dbg(ql_dbg_dpc, vha, 0x401d,
5968 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 5969
5970 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
5971 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5972 atomic_set(&vha->loop_state, LOOP_DOWN);
5973 qla2x00_mark_all_devices_lost(vha, 0);
5974 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 5975 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 5976 } else {
5977 if (!atomic_read(&vha->loop_down_timer))
5978 atomic_set(&vha->loop_down_timer,
5979 LOOP_DOWN_TIME);
5980 }
5981 /* Wait for pending cmds to complete */
5982 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
5983}
5984
a9083016
GM		 5985void
5986qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
5987{
5988 struct qla_hw_data *ha = vha->hw;
579d12b5 5989 struct scsi_qla_host *vp;
feafb7b1 5990 unsigned long flags;
6aef87be 5991 fc_port_t *fcport;
7c3f8fd1 5992 u16 i;
a9083016 5993
e46ef004
SK		 5994 /* For ISP82XX, driver waits for completion of the commands.
5995 * online flag should be set.
5996 */
7ec0effd 5997 if (!(IS_P3P_TYPE(ha)))
e46ef004 5998 vha->flags.online = 0;
a9083016
GM		 5999 ha->flags.chip_reset_done = 0;
6000 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 6001 vha->qla_stats.total_isp_aborts++;
a9083016 6002
7c3df132
SK		 6003 ql_log(ql_log_info, vha, 0x00af,
6004 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 6005
e46ef004
SK		 6006 /* For ISP82XX, reset_chip is just disabling interrupts.
6007 * Driver waits for the completion of the commands.
6008 * the interrupts need to be enabled.
6009 */
7ec0effd 6010 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 6011 ha->isp_ops->reset_chip(vha);
6012
ec7193e2
QT		 6013 ha->flags.n2n_ae = 0;
6014 ha->flags.lip_ae = 0;
6015 ha->current_topology = 0;
6016 ha->flags.fw_started = 0;
6017 ha->flags.fw_init_done = 0;
7c3f8fd1
QT		 6018 ha->base_qpair->chip_reset++;
6019 for (i = 0; i < ha->max_qpairs; i++) {
6020 if (ha->queue_pair_map[i])
6021 ha->queue_pair_map[i]->chip_reset =
6022 ha->base_qpair->chip_reset;
6023 }
726b8548 6024
a9083016
GM		 6025 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
6026 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6027 atomic_set(&vha->loop_state, LOOP_DOWN);
6028 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 6029
6030 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 6031 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 6032 atomic_inc(&vp->vref_count);
6033 spin_unlock_irqrestore(&ha->vport_slock, flags);
6034
a9083016 6035 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 6036
6037 spin_lock_irqsave(&ha->vport_slock, flags);
6038 atomic_dec(&vp->vref_count);
6039 }
6040 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 6041 } else {
6042 if (!atomic_read(&vha->loop_down_timer))
6043 atomic_set(&vha->loop_down_timer,
6044 LOOP_DOWN_TIME);
6045 }
6046
6aef87be
AV		 6047 /* Clear all async request states across all VPs. */
6048 list_for_each_entry(fcport, &vha->vp_fcports, list)
6049 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6050 spin_lock_irqsave(&ha->vport_slock, flags);
6051 list_for_each_entry(vp, &ha->vp_list, list) {
6052 atomic_inc(&vp->vref_count);
6053 spin_unlock_irqrestore(&ha->vport_slock, flags);
6054
6055 list_for_each_entry(fcport, &vp->vp_fcports, list)
6056 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6057
6058 spin_lock_irqsave(&ha->vport_slock, flags);
6059 atomic_dec(&vp->vref_count);
6060 }
6061 spin_unlock_irqrestore(&ha->vport_slock, flags);
6062
bddd2d65
LC		 6063 if (!ha->flags.eeh_busy) {
6064 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 6065 if (IS_P3P_TYPE(ha)) {
7190575f 6066 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 6067 ql_log(ql_log_info, vha, 0x00b4,
6068 "Done chip reset cleanup.\n");
a9083016 6069
e46ef004
SK		 6070 /* Done waiting for pending commands.
6071 * Reset the online flag.
6072 */
6073 vha->flags.online = 0;
4d78c973 6074 }
a9083016 6075
bddd2d65
LC		 6076 /* Requeue all commands in outstanding command list. */
6077 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6078 }
b6a029e1
AE		 6079 /* memory barrier */
6080 wmb();
a9083016
GM		 6081}
6082
1da177e4
LT		 6083/*
6084* qla2x00_abort_isp
6085* Resets ISP and aborts all outstanding commands.
6086*
6087* Input:
6088* ha = adapter block pointer.
6089*
6090* Returns:
6091* 0 = success
6092*/
6093int
e315cd28 6094qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 6095{
476e8978 6096 int rval;
1da177e4 6097 uint8_t status = 0;
e315cd28
AC		 6098 struct qla_hw_data *ha = vha->hw;
6099 struct scsi_qla_host *vp;
73208dfd 6100 struct req_que *req = ha->req_q_map[0];
feafb7b1 6101 unsigned long flags;
1da177e4 6102
e315cd28 6103 if (vha->flags.online) {
a9083016 6104 qla2x00_abort_isp_cleanup(vha);
1da177e4 6105
a6171297
SV		 6106 if (IS_QLA8031(ha)) {
6107 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
6108 "Clearing fcoe driver presence.\n");
6109 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
6110 ql_dbg(ql_dbg_p3p, vha, 0xb073,
6111 "Error while clearing DRV-Presence.\n");
6112 }
6113
85880801
AV		 6114 if (unlikely(pci_channel_offline(ha->pdev) &&
6115 ha->flags.pci_channel_io_perm_failure)) {
6116 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6117 status = 0;
6118 return status;
6119 }
6120
73208dfd 6121 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 6122
e315cd28 6123 ha->isp_ops->nvram_config(vha);
1da177e4 6124
e315cd28
AC		 6125 if (!qla2x00_restart_isp(vha)) {
6126 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 6127
e315cd28 6128 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 6129 /*
6130 * Issue marker command only when we are going
6131 * to start the I/O .
6132 */
e315cd28 6133 vha->marker_needed = 1;
1da177e4
LT		 6134 }
6135
e315cd28 6136 vha->flags.online = 1;
1da177e4 6137
fd34f556 6138 ha->isp_ops->enable_intrs(ha);
1da177e4 6139
fa2a1ce5 6140 ha->isp_abort_cnt = 0;
e315cd28 6141 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 6142
6246b8a1
GM		 6143 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
6144 qla2x00_get_fw_version(vha);
df613b96
AV		 6145 if (ha->fce) {
6146 ha->flags.fce_enabled = 1;
6147 memset(ha->fce, 0,
6148 fce_calc_size(ha->fce_bufs));
e315cd28 6149 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 6150 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6151 &ha->fce_bufs);
6152 if (rval) {
7c3df132 6153 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 6154 "Unable to reinitialize FCE "
6155 "(%d).\n", rval);
6156 ha->flags.fce_enabled = 0;
6157 }
6158 }
436a7b11
AV		 6159
6160 if (ha->eft) {
6161 memset(ha->eft, 0, EFT_SIZE);
e315cd28 6162 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 6163 ha->eft_dma, EFT_NUM_BUFFERS);
6164 if (rval) {
7c3df132 6165 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 6166 "Unable to reinitialize EFT "
6167 "(%d).\n", rval);
6168 }
6169 }
1da177e4 6170 } else { /* failed the ISP abort */
e315cd28
AC		 6171 vha->flags.online = 1;
6172 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 6173 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 6174 ql_log(ql_log_fatal, vha, 0x8035,
6175 "ISP error recover failed - "
6176 "board disabled.\n");
fa2a1ce5 6177 /*
1da177e4
LT		 6178 * The next call disables the board
6179 * completely.
6180 */
e315cd28
AC		 6181 ha->isp_ops->reset_adapter(vha);
6182 vha->flags.online = 0;
1da177e4 6183 clear_bit(ISP_ABORT_RETRY,
e315cd28 6184 &vha->dpc_flags);
1da177e4
LT		 6185 status = 0;
6186 } else { /* schedule another ISP abort */
6187 ha->isp_abort_cnt--;
7c3df132
SK		 6188 ql_dbg(ql_dbg_taskm, vha, 0x8020,
6189 "ISP abort - retry remaining %d.\n",
6190 ha->isp_abort_cnt);
1da177e4
LT		 6191 status = 1;
6192 }
6193 } else {
6194 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 6195 ql_dbg(ql_dbg_taskm, vha, 0x8021,
6196 "ISP error recovery - retrying (%d) "
6197 "more times.\n", ha->isp_abort_cnt);
e315cd28 6198 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 6199 status = 1;
6200 }
6201 }
fa2a1ce5 6202
1da177e4
LT		 6203 }
6204
e315cd28 6205 if (!status) {
7c3df132 6206 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
1608cc4a 6207 qla2x00_configure_hba(vha);
feafb7b1
AE		 6208 spin_lock_irqsave(&ha->vport_slock, flags);
6209 list_for_each_entry(vp, &ha->vp_list, list) {
6210 if (vp->vp_idx) {
6211 atomic_inc(&vp->vref_count);
6212 spin_unlock_irqrestore(&ha->vport_slock, flags);
6213
e315cd28 6214 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6215
6216 spin_lock_irqsave(&ha->vport_slock, flags);
6217 atomic_dec(&vp->vref_count);
6218 }
e315cd28 6219 }
feafb7b1
AE		 6220 spin_unlock_irqrestore(&ha->vport_slock, flags);
6221
7d613ac6
SV		 6222 if (IS_QLA8031(ha)) {
6223 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
6224 "Setting back fcoe driver presence.\n");
6225 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
6226 ql_dbg(ql_dbg_p3p, vha, 0xb074,
6227 "Error while setting DRV-Presence.\n");
6228 }
e315cd28 6229 } else {
d8424f68
JP		 6230 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
6231 __func__);
1da177e4
LT		 6232 }
6233
6234 return(status);
6235}
6236
6237/*
6238* qla2x00_restart_isp
6239* restarts the ISP after a reset
6240*
6241* Input:
6242* ha = adapter block pointer.
6243*
6244* Returns:
6245* 0 = success
6246*/
6247static int
e315cd28 6248qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 6249{
c6b2fca8 6250 int status = 0;
e315cd28 6251 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 6252 struct req_que *req = ha->req_q_map[0];
6253 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 6254
6255 /* If firmware needs to be loaded */
e315cd28
AC		 6256 if (qla2x00_isp_firmware(vha)) {
6257 vha->flags.online = 0;
6258 status = ha->isp_ops->chip_diag(vha);
6259 if (!status)
6260 status = qla2x00_setup_chip(vha);
1da177e4
LT		 6261 }
6262
e315cd28
AC		 6263 if (!status && !(status = qla2x00_init_rings(vha))) {
6264 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 6265 ha->flags.chip_reset_done = 1;
7108b76e 6266
73208dfd
AC		 6267 /* Initialize the queues in use */
6268 qla25xx_init_queues(ha);
6269
e315cd28
AC		 6270 status = qla2x00_fw_ready(vha);
6271 if (!status) {
0107109e 6272 /* Issue a marker after FW becomes ready. */
73208dfd 6273 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 6274 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6275 }
6276
6277 /* if no cable then assume it's good */
e315cd28 6278 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 6279 status = 0;
1da177e4
LT		 6280 }
6281 return (status);
6282}
6283
73208dfd
AC		 6284static int
6285qla25xx_init_queues(struct qla_hw_data *ha)
6286{
6287 struct rsp_que *rsp = NULL;
6288 struct req_que *req = NULL;
6289 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6290 int ret = -1;
6291 int i;
6292
2afa19a9 6293 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 6294 rsp = ha->rsp_q_map[i];
cb43285f 6295 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 6296 rsp->options &= ~BIT_0;
618a7523 6297 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 6298 if (ret != QLA_SUCCESS)
7c3df132
SK		 6299 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
6300 "%s Rsp que: %d init failed.\n",
6301 __func__, rsp->id);
73208dfd 6302 else
7c3df132
SK		 6303 ql_dbg(ql_dbg_init, base_vha, 0x0100,
6304 "%s Rsp que: %d inited.\n",
6305 __func__, rsp->id);
73208dfd 6306 }
2afa19a9
AC		 6307 }
6308 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 6309 req = ha->req_q_map[i];
cb43285f
QT		 6310 if (req && test_bit(i, ha->req_qid_map)) {
6311 /* Clear outstanding commands array. */
73208dfd 6312 req->options &= ~BIT_0;
618a7523 6313 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 6314 if (ret != QLA_SUCCESS)
7c3df132
SK		 6315 ql_dbg(ql_dbg_init, base_vha, 0x0101,
6316 "%s Req que: %d init failed.\n",
6317 __func__, req->id);
73208dfd 6318 else
7c3df132
SK		 6319 ql_dbg(ql_dbg_init, base_vha, 0x0102,
6320 "%s Req que: %d inited.\n",
6321 __func__, req->id);
73208dfd
AC		 6322 }
6323 }
6324 return ret;
6325}
6326
1da177e4
LT		 6327/*
6328* qla2x00_reset_adapter
6329* Reset adapter.
6330*
6331* Input:
6332* ha = adapter block pointer.
6333*/
abbd8870 6334void
e315cd28 6335qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 6336{
6337 unsigned long flags = 0;
e315cd28 6338 struct qla_hw_data *ha = vha->hw;
3d71644c 6339 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 6340
e315cd28 6341 vha->flags.online = 0;
fd34f556 6342 ha->isp_ops->disable_intrs(ha);
1da177e4 6343
1da177e4
LT		 6344 spin_lock_irqsave(&ha->hardware_lock, flags);
6345 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
6346 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6347 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
6348 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6349 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6350}
0107109e
AV		 6351
6352void
e315cd28 6353qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 6354{
6355 unsigned long flags = 0;
e315cd28 6356 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 6357 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
6358
7ec0effd 6359 if (IS_P3P_TYPE(ha))
a9083016
GM		 6360 return;
6361
e315cd28 6362 vha->flags.online = 0;
fd34f556 6363 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 6364
6365 spin_lock_irqsave(&ha->hardware_lock, flags);
6366 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
6367 RD_REG_DWORD(&reg->hccr);
6368 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
6369 RD_REG_DWORD(&reg->hccr);
6370 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 6371
6372 if (IS_NOPOLLING_TYPE(ha))
6373 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 6374}
6375
4e08df3f
DM		 6376/* On sparc systems, obtain port and node WWN from firmware
6377 * properties.
6378 */
e315cd28
AC		 6379static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
6380 struct nvram_24xx *nv)
4e08df3f
DM		 6381{
6382#ifdef CONFIG_SPARC
e315cd28 6383 struct qla_hw_data *ha = vha->hw;
4e08df3f 6384 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 6385 struct device_node *dp = pci_device_to_OF_node(pdev);
6386 const u8 *val;
4e08df3f
DM		 6387 int len;
6388
6389 val = of_get_property(dp, "port-wwn", &len);
6390 if (val && len >= WWN_SIZE)
6391 memcpy(nv->port_name, val, WWN_SIZE);
6392
6393 val = of_get_property(dp, "node-wwn", &len);
6394 if (val && len >= WWN_SIZE)
6395 memcpy(nv->node_name, val, WWN_SIZE);
6396#endif
6397}
6398
0107109e 6399int
e315cd28 6400qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 6401{
4e08df3f 6402 int rval;
0107109e
AV		 6403 struct init_cb_24xx *icb;
6404 struct nvram_24xx *nv;
6405 uint32_t *dptr;
6406 uint8_t *dptr1, *dptr2;
6407 uint32_t chksum;
6408 uint16_t cnt;
e315cd28 6409 struct qla_hw_data *ha = vha->hw;
0107109e 6410
4e08df3f 6411 rval = QLA_SUCCESS;
0107109e 6412 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 6413 nv = ha->nvram;
0107109e
AV		 6414
6415 /* Determine NVRAM starting address. */
f73cb695 6416 if (ha->port_no == 0) {
e5b68a61
AC		 6417 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
6418 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
6419 } else {
0107109e 6420 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 6421 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
6422 }
f73cb695 6423
e5b68a61
AC		 6424 ha->nvram_size = sizeof(struct nvram_24xx);
6425 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 6426
281afe19
SJ		 6427 /* Get VPD data into cache */
6428 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 6429 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 6430 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
6431
6432 /* Get NVRAM data into cache and calculate checksum. */
0107109e 6433 dptr = (uint32_t *)nv;
e315cd28 6434 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 6435 ha->nvram_size);
da08ef5c
JC		 6436 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6437 chksum += le32_to_cpu(*dptr);
0107109e 6438
7c3df132
SK		 6439 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
6440 "Contents of NVRAM\n");
6441 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
6442 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 6443
6444 /* Bad NVRAM data, set defaults parameters. */
6445 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6446 || nv->id[3] != ' ' ||
ad950360 6447 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 6448 /* Reset NVRAM data. */
7c3df132 6449 ql_log(ql_log_warn, vha, 0x006b,
9e336520 6450 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 6451 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
6452 ql_log(ql_log_warn, vha, 0x006c,
6453 "Falling back to functioning (yet invalid -- WWPN) "
6454 "defaults.\n");
4e08df3f
DM		 6455
6456 /*
6457 * Set default initialization control block.
6458 */
6459 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6460 nv->nvram_version = cpu_to_le16(ICB_VERSION);
6461 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 6462 nv->frame_payload_size = 2048;
ad950360
BVA		 6463 nv->execution_throttle = cpu_to_le16(0xFFFF);
6464 nv->exchange_count = cpu_to_le16(0);
6465 nv->hard_address = cpu_to_le16(124);
4e08df3f 6466 nv->port_name[0] = 0x21;
f73cb695 6467 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 6468 nv->port_name[2] = 0x00;
6469 nv->port_name[3] = 0xe0;
6470 nv->port_name[4] = 0x8b;
6471 nv->port_name[5] = 0x1c;
6472 nv->port_name[6] = 0x55;
6473 nv->port_name[7] = 0x86;
6474 nv->node_name[0] = 0x20;
6475 nv->node_name[1] = 0x00;
6476 nv->node_name[2] = 0x00;
6477 nv->node_name[3] = 0xe0;
6478 nv->node_name[4] = 0x8b;
6479 nv->node_name[5] = 0x1c;
6480 nv->node_name[6] = 0x55;
6481 nv->node_name[7] = 0x86;
e315cd28 6482 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 6483 nv->login_retry_count = cpu_to_le16(8);
6484 nv->interrupt_delay_timer = cpu_to_le16(0);
6485 nv->login_timeout = cpu_to_le16(0);
4e08df3f 6486 nv->firmware_options_1 =
ad950360
BVA		 6487 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
6488 nv->firmware_options_2 = cpu_to_le32(2 << 4);
6489 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
6490 nv->firmware_options_3 = cpu_to_le32(2 << 13);
6491 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
6492 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 6493 nv->reset_delay = 5;
ad950360
BVA		 6494 nv->max_luns_per_target = cpu_to_le16(128);
6495 nv->port_down_retry_count = cpu_to_le16(30);
6496 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 6497
6498 rval = 1;
0107109e
AV		 6499 }
6500
726b8548 6501 if (qla_tgt_mode_enabled(vha)) {
2d70c103 6502 /* Don't enable full login after initial LIP */
ad950360 6503 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 6504 /* Don't enable LIP full login for initiator */
ad950360 6505 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 6506 }
6507
6508 qlt_24xx_config_nvram_stage1(vha, nv);
6509
0107109e 6510 /* Reset Initialization control block */
e315cd28 6511 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 6512
6513 /* Copy 1st segment. */
6514 dptr1 = (uint8_t *)icb;
6515 dptr2 = (uint8_t *)&nv->version;
6516 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6517 while (cnt--)
6518 *dptr1++ = *dptr2++;
6519
6520 icb->login_retry_count = nv->login_retry_count;
3ea66e28 6521 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 6522
6523 /* Copy 2nd segment. */
6524 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6525 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6526 cnt = (uint8_t *)&icb->reserved_3 -
6527 (uint8_t *)&icb->interrupt_delay_timer;
6528 while (cnt--)
6529 *dptr1++ = *dptr2++;
6530
6531 /*
6532 * Setup driver NVRAM options.
6533 */
e315cd28 6534 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 6535 "QLA2462");
0107109e 6536
2d70c103
NB		 6537 qlt_24xx_config_nvram_stage2(vha, icb);
6538
ad950360 6539 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 6540 /* Use alternate WWN? */
5341e868
AV		 6541 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6542 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6543 }
6544
0107109e 6545 /* Prepare nodename */
ad950360 6546 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 6547 /*
6548 * Firmware will apply the following mask if the nodename was
6549 * not provided.
6550 */
6551 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6552 icb->node_name[0] &= 0xF0;
6553 }
6554
6555 /* Set host adapter parameters. */
6556 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 6557 ha->flags.enable_lip_reset = 0;
6558 ha->flags.enable_lip_full_login =
6559 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6560 ha->flags.enable_target_reset =
6561 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 6562 ha->flags.enable_led_scheme = 0;
d4c760c2 6563 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 6564
fd0e7e4d
AV		 6565 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6566 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 6567
6568 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
6569 sizeof(ha->fw_seriallink_options24));
6570
6571 /* save HBA serial number */
6572 ha->serial0 = icb->port_name[5];
6573 ha->serial1 = icb->port_name[6];
6574 ha->serial2 = icb->port_name[7];
e315cd28
AC		 6575 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6576 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 6577
ad950360 6578 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 6579
0107109e
AV		 6580 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6581
6582 /* Set minimum login_timeout to 4 seconds. */
6583 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6584 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6585 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6586 nv->login_timeout = cpu_to_le16(4);
0107109e 6587 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 6588
00a537b8
AV		 6589 /* Set minimum RATOV to 100 tenths of a second. */
6590 ha->r_a_tov = 100;
0107109e
AV		 6591
6592 ha->loop_reset_delay = nv->reset_delay;
6593
6594 /* Link Down Timeout = 0:
6595 *
6596 * When Port Down timer expires we will start returning
6597 * I/O's to OS with "DID_NO_CONNECT".
6598 *
6599 * Link Down Timeout != 0:
6600 *
6601 * The driver waits for the link to come up after link down
6602 * before returning I/Os to OS with "DID_NO_CONNECT".
6603 */
6604 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6605 ha->loop_down_abort_time =
6606 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6607 } else {
6608 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6609 ha->loop_down_abort_time =
6610 (LOOP_DOWN_TIME - ha->link_down_timeout);
6611 }
6612
6613 /* Need enough time to try and get the port back. */
6614 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6615 if (qlport_down_retry)
6616 ha->port_down_retry_count = qlport_down_retry;
6617
6618 /* Set login_retry_count */
6619 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6620 if (ha->port_down_retry_count ==
6621 le16_to_cpu(nv->port_down_retry_count) &&
6622 ha->port_down_retry_count > 3)
6623 ha->login_retry_count = ha->port_down_retry_count;
6624 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6625 ha->login_retry_count = ha->port_down_retry_count;
6626 if (ql2xloginretrycount)
6627 ha->login_retry_count = ql2xloginretrycount;
6628
4fdfefe5 6629 /* Enable ZIO. */
e315cd28 6630 if (!vha->flags.init_done) {
4fdfefe5
AV		 6631 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6632 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6633 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6634 le16_to_cpu(icb->interrupt_delay_timer): 2;
6635 }
ad950360 6636 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 6637 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 6638 vha->flags.process_response_queue = 0;
4fdfefe5 6639 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 6640 ha->zio_mode = QLA_ZIO_MODE_6;
6641
7c3df132 6642 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 6643 "ZIO mode %d enabled; timer delay (%d us).\n",
6644 ha->zio_mode, ha->zio_timer * 100);
6645
6646 icb->firmware_options_2 |= cpu_to_le32(
6647 (uint32_t)ha->zio_mode);
6648 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 6649 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 6650 }
6651
4e08df3f 6652 if (rval) {
7c3df132
SK		 6653 ql_log(ql_log_warn, vha, 0x0070,
6654 "NVRAM configuration failed.\n");
4e08df3f
DM		 6655 }
6656 return (rval);
0107109e
AV		 6657}
6658
4243c115
SC		 6659uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
6660{
6661 struct qla27xx_image_status pri_image_status, sec_image_status;
6662 uint8_t valid_pri_image, valid_sec_image;
6663 uint32_t *wptr;
6664 uint32_t cnt, chksum, size;
6665 struct qla_hw_data *ha = vha->hw;
6666
6667 valid_pri_image = valid_sec_image = 1;
6668 ha->active_image = 0;
6669 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
6670
6671 if (!ha->flt_region_img_status_pri) {
6672 valid_pri_image = 0;
6673 goto check_sec_image;
6674 }
6675
6676 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
6677 ha->flt_region_img_status_pri, size);
6678
6679 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6680 ql_dbg(ql_dbg_init, vha, 0x018b,
6681 "Primary image signature (0x%x) not valid\n",
6682 pri_image_status.signature);
6683 valid_pri_image = 0;
6684 goto check_sec_image;
6685 }
6686
6687 wptr = (uint32_t *)(&pri_image_status);
6688 cnt = size;
6689
da08ef5c
JC		 6690 for (chksum = 0; cnt--; wptr++)
6691 chksum += le32_to_cpu(*wptr);
41dc529a 6692
4243c115
SC		 6693 if (chksum) {
6694 ql_dbg(ql_dbg_init, vha, 0x018c,
6695 "Checksum validation failed for primary image (0x%x)\n",
6696 chksum);
6697 valid_pri_image = 0;
6698 }
6699
6700check_sec_image:
6701 if (!ha->flt_region_img_status_sec) {
6702 valid_sec_image = 0;
6703 goto check_valid_image;
6704 }
6705
6706 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
6707 ha->flt_region_img_status_sec, size);
6708
6709 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6710 ql_dbg(ql_dbg_init, vha, 0x018d,
6711 "Secondary image signature(0x%x) not valid\n",
6712 sec_image_status.signature);
6713 valid_sec_image = 0;
6714 goto check_valid_image;
6715 }
6716
6717 wptr = (uint32_t *)(&sec_image_status);
6718 cnt = size;
da08ef5c
JC		 6719 for (chksum = 0; cnt--; wptr++)
6720 chksum += le32_to_cpu(*wptr);
4243c115
SC		 6721 if (chksum) {
6722 ql_dbg(ql_dbg_init, vha, 0x018e,
6723 "Checksum validation failed for secondary image (0x%x)\n",
6724 chksum);
6725 valid_sec_image = 0;
6726 }
6727
6728check_valid_image:
6729 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
6730 ha->active_image = QLA27XX_PRIMARY_IMAGE;
6731 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
6732 if (!ha->active_image ||
6733 pri_image_status.generation_number <
6734 sec_image_status.generation_number)
6735 ha->active_image = QLA27XX_SECONDARY_IMAGE;
6736 }
6737
6738 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
6739 ha->active_image == 0 ? "default bootld and fw" :
6740 ha->active_image == 1 ? "primary" :
6741 ha->active_image == 2 ? "secondary" :
6742 "Invalid");
6743
6744 return ha->active_image;
6745}
6746
413975a0 6747static int
cbc8eb67
AV		 6748qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
6749 uint32_t faddr)
d1c61909 6750{
73208dfd 6751 int rval = QLA_SUCCESS;
d1c61909 6752 int segments, fragment;
d1c61909
AV		 6753 uint32_t *dcode, dlen;
6754 uint32_t risc_addr;
6755 uint32_t risc_size;
6756 uint32_t i;
e315cd28 6757 struct qla_hw_data *ha = vha->hw;
73208dfd 6758 struct req_que *req = ha->req_q_map[0];
eaac30be 6759
7c3df132 6760 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 6761 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 6762
d1c61909
AV		 6763 rval = QLA_SUCCESS;
6764
6765 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6766 dcode = (uint32_t *)req->ring;
d1c61909
AV		 6767 *srisc_addr = 0;
6768
4243c115
SC		 6769 if (IS_QLA27XX(ha) &&
6770 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
6771 faddr = ha->flt_region_fw_sec;
6772
d1c61909 6773 /* Validate firmware image by checking version. */
e315cd28 6774 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 6775 for (i = 0; i < 4; i++)
6776 dcode[i] = be32_to_cpu(dcode[i]);
6777 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6778 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6779 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6780 dcode[3] == 0)) {
7c3df132
SK		 6781 ql_log(ql_log_fatal, vha, 0x008c,
6782 "Unable to verify the integrity of flash firmware "
6783 "image.\n");
6784 ql_log(ql_log_fatal, vha, 0x008d,
6785 "Firmware data: %08x %08x %08x %08x.\n",
6786 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 6787
6788 return QLA_FUNCTION_FAILED;
6789 }
6790
6791 while (segments && rval == QLA_SUCCESS) {
6792 /* Read segment's load information. */
e315cd28 6793 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 6794
6795 risc_addr = be32_to_cpu(dcode[2]);
6796 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6797 risc_size = be32_to_cpu(dcode[3]);
6798
6799 fragment = 0;
6800 while (risc_size > 0 && rval == QLA_SUCCESS) {
6801 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6802 if (dlen > risc_size)
6803 dlen = risc_size;
6804
7c3df132
SK		 6805 ql_dbg(ql_dbg_init, vha, 0x008e,
6806 "Loading risc segment@ risc addr %x "
6807 "number of dwords 0x%x offset 0x%x.\n",
6808 risc_addr, dlen, faddr);
d1c61909 6809
e315cd28 6810 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 6811 for (i = 0; i < dlen; i++)
6812 dcode[i] = swab32(dcode[i]);
6813
73208dfd 6814 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 6815 dlen);
6816 if (rval) {
7c3df132
SK		 6817 ql_log(ql_log_fatal, vha, 0x008f,
6818 "Failed to load segment %d of firmware.\n",
6819 fragment);
f261f7af 6820 return QLA_FUNCTION_FAILED;
d1c61909
AV		 6821 }
6822
6823 faddr += dlen;
6824 risc_addr += dlen;
6825 risc_size -= dlen;
6826 fragment++;
6827 }
6828
6829 /* Next segment. */
6830 segments--;
6831 }
6832
f73cb695
CD		 6833 if (!IS_QLA27XX(ha))
6834 return rval;
6835
6836 if (ha->fw_dump_template)
6837 vfree(ha->fw_dump_template);
6838 ha->fw_dump_template = NULL;
6839 ha->fw_dump_template_len = 0;
6840
6841 ql_dbg(ql_dbg_init, vha, 0x0161,
6842 "Loading fwdump template from %x\n", faddr);
6843 qla24xx_read_flash_data(vha, dcode, faddr, 7);
6844 risc_size = be32_to_cpu(dcode[2]);
6845 ql_dbg(ql_dbg_init, vha, 0x0162,
6846 "-> array size %x dwords\n", risc_size);
6847 if (risc_size == 0 || risc_size == ~0)
6848 goto default_template;
6849
6850 dlen = (risc_size - 8) * sizeof(*dcode);
6851 ql_dbg(ql_dbg_init, vha, 0x0163,
6852 "-> template allocating %x bytes...\n", dlen);
6853 ha->fw_dump_template = vmalloc(dlen);
6854 if (!ha->fw_dump_template) {
6855 ql_log(ql_log_warn, vha, 0x0164,
6856 "Failed fwdump template allocate %x bytes.\n", risc_size);
6857 goto default_template;
6858 }
6859
6860 faddr += 7;
6861 risc_size -= 8;
6862 dcode = ha->fw_dump_template;
6863 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
6864 for (i = 0; i < risc_size; i++)
6865 dcode[i] = le32_to_cpu(dcode[i]);
6866
6867 if (!qla27xx_fwdt_template_valid(dcode)) {
6868 ql_log(ql_log_warn, vha, 0x0165,
6869 "Failed fwdump template validate\n");
6870 goto default_template;
6871 }
6872
6873 dlen = qla27xx_fwdt_template_size(dcode);
6874 ql_dbg(ql_dbg_init, vha, 0x0166,
6875 "-> template size %x bytes\n", dlen);
6876 if (dlen > risc_size * sizeof(*dcode)) {
6877 ql_log(ql_log_warn, vha, 0x0167,
4fae52b5 6878 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 6879 (size_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 6880 goto default_template;
6881 }
6882 ha->fw_dump_template_len = dlen;
6883 return rval;
6884
6885default_template:
6886 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
6887 if (ha->fw_dump_template)
6888 vfree(ha->fw_dump_template);
6889 ha->fw_dump_template = NULL;
6890 ha->fw_dump_template_len = 0;
6891
6892 dlen = qla27xx_fwdt_template_default_size();
6893 ql_dbg(ql_dbg_init, vha, 0x0169,
6894 "-> template allocating %x bytes...\n", dlen);
6895 ha->fw_dump_template = vmalloc(dlen);
6896 if (!ha->fw_dump_template) {
6897 ql_log(ql_log_warn, vha, 0x016a,
6898 "Failed fwdump template allocate %x bytes.\n", risc_size);
6899 goto failed_template;
6900 }
6901
6902 dcode = ha->fw_dump_template;
6903 risc_size = dlen / sizeof(*dcode);
6904 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
6905 for (i = 0; i < risc_size; i++)
6906 dcode[i] = be32_to_cpu(dcode[i]);
6907
6908 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
6909 ql_log(ql_log_warn, vha, 0x016b,
6910 "Failed fwdump template validate\n");
6911 goto failed_template;
6912 }
6913
6914 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
6915 ql_dbg(ql_dbg_init, vha, 0x016c,
6916 "-> template size %x bytes\n", dlen);
6917 ha->fw_dump_template_len = dlen;
6918 return rval;
6919
6920failed_template:
6921 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
6922 if (ha->fw_dump_template)
6923 vfree(ha->fw_dump_template);
6924 ha->fw_dump_template = NULL;
6925 ha->fw_dump_template_len = 0;
d1c61909
AV		 6926 return rval;
6927}
6928
e9454a88 6929#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 6930
0107109e 6931int
e315cd28 6932qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 6933{
6934 int rval;
6935 int i, fragment;
6936 uint16_t *wcode, *fwcode;
6937 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
6938 struct fw_blob *blob;
e315cd28 6939 struct qla_hw_data *ha = vha->hw;
73208dfd 6940 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 6941
6942 /* Load firmware blob. */
e315cd28 6943 blob = qla2x00_request_firmware(vha);
5433383e 6944 if (!blob) {
7c3df132 6945 ql_log(ql_log_info, vha, 0x0083,
94bcf830 6946 "Firmware image unavailable.\n");
7c3df132
SK		 6947 ql_log(ql_log_info, vha, 0x0084,
6948 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 6949 return QLA_FUNCTION_FAILED;
6950 }
6951
6952 rval = QLA_SUCCESS;
6953
73208dfd 6954 wcode = (uint16_t *)req->ring;
5433383e
AV		 6955 *srisc_addr = 0;
6956 fwcode = (uint16_t *)blob->fw->data;
6957 fwclen = 0;
6958
6959 /* Validate firmware image by checking version. */
6960 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 6961 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 6962 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 6963 blob->fw->size);
6964 goto fail_fw_integrity;
6965 }
6966 for (i = 0; i < 4; i++)
6967 wcode[i] = be16_to_cpu(fwcode[i + 4]);
6968 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
6969 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
6970 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 6971 ql_log(ql_log_fatal, vha, 0x0086,
6972 "Unable to verify integrity of firmware image.\n");
6973 ql_log(ql_log_fatal, vha, 0x0087,
6974 "Firmware data: %04x %04x %04x %04x.\n",
6975 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 6976 goto fail_fw_integrity;
6977 }
6978
6979 seg = blob->segs;
6980 while (*seg && rval == QLA_SUCCESS) {
6981 risc_addr = *seg;
6982 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
6983 risc_size = be16_to_cpu(fwcode[3]);
6984
6985 /* Validate firmware image size. */
6986 fwclen += risc_size * sizeof(uint16_t);
6987 if (blob->fw->size < fwclen) {
7c3df132 6988 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 6989 "Unable to verify integrity of firmware image "
5b5e0928 6990 "(%zd).\n", blob->fw->size);
5433383e
AV		 6991 goto fail_fw_integrity;
6992 }
6993
6994 fragment = 0;
6995 while (risc_size > 0 && rval == QLA_SUCCESS) {
6996 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
6997 if (wlen > risc_size)
6998 wlen = risc_size;
7c3df132
SK		 6999 ql_dbg(ql_dbg_init, vha, 0x0089,
7000 "Loading risc segment@ risc addr %x number of "
7001 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 7002
7003 for (i = 0; i < wlen; i++)
7004 wcode[i] = swab16(fwcode[i]);
7005
73208dfd 7006 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 7007 wlen);
7008 if (rval) {
7c3df132
SK		 7009 ql_log(ql_log_fatal, vha, 0x008a,
7010 "Failed to load segment %d of firmware.\n",
7011 fragment);
5433383e
AV		 7012 break;
7013 }
7014
7015 fwcode += wlen;
7016 risc_addr += wlen;
7017 risc_size -= wlen;
7018 fragment++;
7019 }
7020
7021 /* Next segment. */
7022 seg++;
7023 }
7024 return rval;
7025
7026fail_fw_integrity:
7027 return QLA_FUNCTION_FAILED;
7028}
7029
eaac30be
AV		 7030static int
7031qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 7032{
7033 int rval;
7034 int segments, fragment;
7035 uint32_t *dcode, dlen;
7036 uint32_t risc_addr;
7037 uint32_t risc_size;
7038 uint32_t i;
5433383e 7039 struct fw_blob *blob;
f73cb695
CD		 7040 const uint32_t *fwcode;
7041 uint32_t fwclen;
e315cd28 7042 struct qla_hw_data *ha = vha->hw;
73208dfd 7043 struct req_que *req = ha->req_q_map[0];
0107109e 7044
5433383e 7045 /* Load firmware blob. */
e315cd28 7046 blob = qla2x00_request_firmware(vha);
5433383e 7047 if (!blob) {
7c3df132 7048 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 7049 "Firmware image unavailable.\n");
7c3df132
SK		 7050 ql_log(ql_log_warn, vha, 0x0091,
7051 "Firmware images can be retrieved from: "
7052 QLA_FW_URL ".\n");
d1c61909 7053
eaac30be 7054 return QLA_FUNCTION_FAILED;
0107109e
AV		 7055 }
7056
cfb0919c
CD		 7057 ql_dbg(ql_dbg_init, vha, 0x0092,
7058 "FW: Loading via request-firmware.\n");
eaac30be 7059
0107109e
AV		 7060 rval = QLA_SUCCESS;
7061
7062 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 7063 dcode = (uint32_t *)req->ring;
0107109e 7064 *srisc_addr = 0;
5433383e 7065 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 7066 fwclen = 0;
7067
7068 /* Validate firmware image by checking version. */
5433383e 7069 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 7070 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 7071 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 7072 blob->fw->size);
f73cb695 7073 return QLA_FUNCTION_FAILED;
0107109e
AV		 7074 }
7075 for (i = 0; i < 4; i++)
7076 dcode[i] = be32_to_cpu(fwcode[i + 4]);
7077 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
7078 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
7079 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
7080 dcode[3] == 0)) {
7c3df132 7081 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 7082 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 7083 blob->fw->size);
7084 ql_log(ql_log_fatal, vha, 0x0095,
7085 "Firmware data: %08x %08x %08x %08x.\n",
7086 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 7087 return QLA_FUNCTION_FAILED;
0107109e
AV		 7088 }
7089
7090 while (segments && rval == QLA_SUCCESS) {
7091 risc_addr = be32_to_cpu(fwcode[2]);
7092 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
7093 risc_size = be32_to_cpu(fwcode[3]);
7094
7095 /* Validate firmware image size. */
7096 fwclen += risc_size * sizeof(uint32_t);
5433383e 7097 if (blob->fw->size < fwclen) {
7c3df132 7098 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 7099 "Unable to verify integrity of firmware image "
5b5e0928 7100 "(%zd).\n", blob->fw->size);
f73cb695 7101 return QLA_FUNCTION_FAILED;
0107109e
AV		 7102 }
7103
7104 fragment = 0;
7105 while (risc_size > 0 && rval == QLA_SUCCESS) {
7106 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
7107 if (dlen > risc_size)
7108 dlen = risc_size;
7109
7c3df132
SK		 7110 ql_dbg(ql_dbg_init, vha, 0x0097,
7111 "Loading risc segment@ risc addr %x "
7112 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 7113
7114 for (i = 0; i < dlen; i++)
7115 dcode[i] = swab32(fwcode[i]);
7116
73208dfd 7117 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 7118 dlen);
0107109e 7119 if (rval) {
7c3df132
SK		 7120 ql_log(ql_log_fatal, vha, 0x0098,
7121 "Failed to load segment %d of firmware.\n",
7122 fragment);
f261f7af 7123 return QLA_FUNCTION_FAILED;
0107109e
AV		 7124 }
7125
7126 fwcode += dlen;
7127 risc_addr += dlen;
7128 risc_size -= dlen;
7129 fragment++;
7130 }
7131
7132 /* Next segment. */
7133 segments--;
7134 }
f73cb695
CD		 7135
7136 if (!IS_QLA27XX(ha))
7137 return rval;
7138
7139 if (ha->fw_dump_template)
7140 vfree(ha->fw_dump_template);
7141 ha->fw_dump_template = NULL;
7142 ha->fw_dump_template_len = 0;
7143
7144 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 7145 "Loading fwdump template from %x\n",
7146 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 7147 risc_size = be32_to_cpu(fwcode[2]);
7148 ql_dbg(ql_dbg_init, vha, 0x172,
7149 "-> array size %x dwords\n", risc_size);
7150 if (risc_size == 0 || risc_size == ~0)
7151 goto default_template;
7152
7153 dlen = (risc_size - 8) * sizeof(*fwcode);
7154 ql_dbg(ql_dbg_init, vha, 0x0173,
7155 "-> template allocating %x bytes...\n", dlen);
7156 ha->fw_dump_template = vmalloc(dlen);
7157 if (!ha->fw_dump_template) {
7158 ql_log(ql_log_warn, vha, 0x0174,
7159 "Failed fwdump template allocate %x bytes.\n", risc_size);
7160 goto default_template;
7161 }
7162
7163 fwcode += 7;
7164 risc_size -= 8;
7165 dcode = ha->fw_dump_template;
7166 for (i = 0; i < risc_size; i++)
7167 dcode[i] = le32_to_cpu(fwcode[i]);
7168
7169 if (!qla27xx_fwdt_template_valid(dcode)) {
7170 ql_log(ql_log_warn, vha, 0x0175,
7171 "Failed fwdump template validate\n");
7172 goto default_template;
7173 }
7174
7175 dlen = qla27xx_fwdt_template_size(dcode);
7176 ql_dbg(ql_dbg_init, vha, 0x0176,
7177 "-> template size %x bytes\n", dlen);
7178 if (dlen > risc_size * sizeof(*fwcode)) {
7179 ql_log(ql_log_warn, vha, 0x0177,
4fae52b5 7180 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7181 (size_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 7182 goto default_template;
7183 }
7184 ha->fw_dump_template_len = dlen;
0107109e
AV		 7185 return rval;
7186
f73cb695
CD		 7187default_template:
7188 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
7189 if (ha->fw_dump_template)
7190 vfree(ha->fw_dump_template);
7191 ha->fw_dump_template = NULL;
7192 ha->fw_dump_template_len = 0;
7193
7194 dlen = qla27xx_fwdt_template_default_size();
7195 ql_dbg(ql_dbg_init, vha, 0x0179,
7196 "-> template allocating %x bytes...\n", dlen);
7197 ha->fw_dump_template = vmalloc(dlen);
7198 if (!ha->fw_dump_template) {
7199 ql_log(ql_log_warn, vha, 0x017a,
7200 "Failed fwdump template allocate %x bytes.\n", risc_size);
7201 goto failed_template;
7202 }
7203
7204 dcode = ha->fw_dump_template;
7205 risc_size = dlen / sizeof(*fwcode);
7206 fwcode = qla27xx_fwdt_template_default();
7207 for (i = 0; i < risc_size; i++)
7208 dcode[i] = be32_to_cpu(fwcode[i]);
7209
7210 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7211 ql_log(ql_log_warn, vha, 0x017b,
7212 "Failed fwdump template validate\n");
7213 goto failed_template;
7214 }
7215
7216 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7217 ql_dbg(ql_dbg_init, vha, 0x017c,
7218 "-> template size %x bytes\n", dlen);
7219 ha->fw_dump_template_len = dlen;
7220 return rval;
7221
7222failed_template:
7223 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
7224 if (ha->fw_dump_template)
7225 vfree(ha->fw_dump_template);
7226 ha->fw_dump_template = NULL;
7227 ha->fw_dump_template_len = 0;
7228 return rval;
0107109e 7229}
18c6c127 7230
eaac30be
AV		 7231int
7232qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7233{
7234 int rval;
7235
e337d907
AV		 7236 if (ql2xfwloadbin == 1)
7237 return qla81xx_load_risc(vha, srisc_addr);
7238
eaac30be
AV		 7239 /*
7240 * FW Load priority:
7241 * 1) Firmware via request-firmware interface (.bin file).
7242 * 2) Firmware residing in flash.
7243 */
7244 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7245 if (rval == QLA_SUCCESS)
7246 return rval;
7247
cbc8eb67
AV		 7248 return qla24xx_load_risc_flash(vha, srisc_addr,
7249 vha->hw->flt_region_fw);
eaac30be
AV		 7250}
7251
7252int
7253qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7254{
7255 int rval;
cbc8eb67 7256 struct qla_hw_data *ha = vha->hw;
eaac30be 7257
e337d907 7258 if (ql2xfwloadbin == 2)
cbc8eb67 7259 goto try_blob_fw;
e337d907 7260
eaac30be
AV		 7261 /*
7262 * FW Load priority:
7263 * 1) Firmware residing in flash.
7264 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 7265 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 7266 */
cbc8eb67 7267 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 7268 if (rval == QLA_SUCCESS)
7269 return rval;
7270
cbc8eb67
AV		 7271try_blob_fw:
7272 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7273 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
7274 return rval;
7275
7c3df132
SK		 7276 ql_log(ql_log_info, vha, 0x0099,
7277 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 7278 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
7279 if (rval != QLA_SUCCESS)
7280 return rval;
7281
7c3df132 7282 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 7283 ha->flags.running_gold_fw = 1;
cbc8eb67 7284 return rval;
eaac30be
AV		 7285}
7286
18c6c127 7287void
e315cd28 7288qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 7289{
7290 int ret, retries;
e315cd28 7291 struct qla_hw_data *ha = vha->hw;
18c6c127 7292
85880801
AV		 7293 if (ha->flags.pci_channel_io_perm_failure)
7294 return;
e428924c 7295 if (!IS_FWI2_CAPABLE(ha))
18c6c127 7296 return;
75edf81d
AV		 7297 if (!ha->fw_major_version)
7298 return;
ec7193e2
QT		 7299 if (!ha->flags.fw_started)
7300 return;
18c6c127 7301
e315cd28 7302 ret = qla2x00_stop_firmware(vha);
7c7f1f29 7303 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 7304 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 7305 ha->isp_ops->reset_chip(vha);
7306 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 7307 continue;
e315cd28 7308 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 7309 continue;
7c3df132
SK		 7310 ql_log(ql_log_info, vha, 0x8015,
7311 "Attempting retry of stop-firmware command.\n");
e315cd28 7312 ret = qla2x00_stop_firmware(vha);
18c6c127 7313 }
ec7193e2 7314
4b60c827 7315 QLA_FW_STOPPED(ha);
ec7193e2 7316 ha->flags.fw_init_done = 0;
18c6c127 7317}
2c3dfe3f
SJ		 7318
7319int
e315cd28 7320qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 7321{
7322 int rval = QLA_SUCCESS;
0b91d116 7323 int rval2;
2c3dfe3f 7324 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 7325 struct qla_hw_data *ha = vha->hw;
7326 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 7327 struct req_que *req;
7328 struct rsp_que *rsp;
2c3dfe3f 7329
e315cd28 7330 if (!vha->vp_idx)
2c3dfe3f
SJ		 7331 return -EINVAL;
7332
e315cd28 7333 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 7334 if (vha->qpair)
7335 req = vha->qpair->req;
67c2e93a 7336 else
d7459527 7337 req = ha->req_q_map[0];
67c2e93a
AC		 7338 rsp = req->rsp;
7339
2c3dfe3f 7340 if (rval == QLA_SUCCESS) {
e315cd28 7341 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 7342 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 7343 }
7344
e315cd28 7345 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 7346
7347 /* Login to SNS first */
0b91d116
CD		 7348 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
7349 BIT_1);
7350 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
7351 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
7352 ql_dbg(ql_dbg_init, vha, 0x0120,
7353 "Failed SNS login: loop_id=%x, rval2=%d\n",
7354 NPH_SNS, rval2);
7355 else
7356 ql_dbg(ql_dbg_init, vha, 0x0103,
7357 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
7358 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
7359 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 7360 return (QLA_FUNCTION_FAILED);
7361 }
7362
e315cd28
AC		 7363 atomic_set(&vha->loop_down_timer, 0);
7364 atomic_set(&vha->loop_state, LOOP_UP);
7365 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7366 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
7367 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 7368
7369 return rval;
7370}
4d4df193
HK		 7371
7372/* 84XX Support **************************************************************/
7373
7374static LIST_HEAD(qla_cs84xx_list);
7375static DEFINE_MUTEX(qla_cs84xx_mutex);
7376
7377static struct qla_chip_state_84xx *
e315cd28 7378qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 7379{
7380 struct qla_chip_state_84xx *cs84xx;
e315cd28 7381 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7382
7383 mutex_lock(&qla_cs84xx_mutex);
7384
7385 /* Find any shared 84xx chip. */
7386 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
7387 if (cs84xx->bus == ha->pdev->bus) {
7388 kref_get(&cs84xx->kref);
7389 goto done;
7390 }
7391 }
7392
7393 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
7394 if (!cs84xx)
7395 goto done;
7396
7397 kref_init(&cs84xx->kref);
7398 spin_lock_init(&cs84xx->access_lock);
7399 mutex_init(&cs84xx->fw_update_mutex);
7400 cs84xx->bus = ha->pdev->bus;
7401
7402 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
7403done:
7404 mutex_unlock(&qla_cs84xx_mutex);
7405 return cs84xx;
7406}
7407
7408static void
7409__qla84xx_chip_release(struct kref *kref)
7410{
7411 struct qla_chip_state_84xx *cs84xx =
7412 container_of(kref, struct qla_chip_state_84xx, kref);
7413
7414 mutex_lock(&qla_cs84xx_mutex);
7415 list_del(&cs84xx->list);
7416 mutex_unlock(&qla_cs84xx_mutex);
7417 kfree(cs84xx);
7418}
7419
7420void
e315cd28 7421qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 7422{
e315cd28 7423 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7424 if (ha->cs84xx)
7425 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
7426}
7427
7428static int
e315cd28 7429qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 7430{
7431 int rval;
7432 uint16_t status[2];
e315cd28 7433 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7434
7435 mutex_lock(&ha->cs84xx->fw_update_mutex);
7436
e315cd28 7437 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 7438
7439 mutex_unlock(&ha->cs84xx->fw_update_mutex);
7440
7441 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
7442 QLA_SUCCESS;
7443}
3a03eb79
AV		 7444
7445/* 81XX Support **************************************************************/
7446
7447int
7448qla81xx_nvram_config(scsi_qla_host_t *vha)
7449{
7450 int rval;
7451 struct init_cb_81xx *icb;
7452 struct nvram_81xx *nv;
7453 uint32_t *dptr;
7454 uint8_t *dptr1, *dptr2;
7455 uint32_t chksum;
7456 uint16_t cnt;
7457 struct qla_hw_data *ha = vha->hw;
7458
7459 rval = QLA_SUCCESS;
7460 icb = (struct init_cb_81xx *)ha->init_cb;
7461 nv = ha->nvram;
7462
7463 /* Determine NVRAM starting address. */
7464 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 7465 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 7466 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
7467 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 7468
7469 /* Get VPD data into cache */
7470 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 7471 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
7472 ha->vpd_size);
3a03eb79
AV		 7473
7474 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 7475 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 7476 ha->nvram_size);
3d79038f 7477 dptr = (uint32_t *)nv;
da08ef5c
JC		 7478 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7479 chksum += le32_to_cpu(*dptr);
3a03eb79 7480
7c3df132
SK		 7481 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
7482 "Contents of NVRAM:\n");
7483 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
7484 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 7485
7486 /* Bad NVRAM data, set defaults parameters. */
7487 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
7488 || nv->id[3] != ' ' ||
ad950360 7489 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 7490 /* Reset NVRAM data. */
7c3df132 7491 ql_log(ql_log_info, vha, 0x0073,
9e336520 7492 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 7493 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 7494 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 7495 ql_log(ql_log_info, vha, 0x0074,
7496 "Falling back to functioning (yet invalid -- WWPN) "
7497 "defaults.\n");
3a03eb79
AV		 7498
7499 /*
7500 * Set default initialization control block.
7501 */
7502 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 7503 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7504 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7505 nv->frame_payload_size = 2048;
ad950360
BVA		 7506 nv->execution_throttle = cpu_to_le16(0xFFFF);
7507 nv->exchange_count = cpu_to_le16(0);
3a03eb79 7508 nv->port_name[0] = 0x21;
f73cb695 7509 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 7510 nv->port_name[2] = 0x00;
7511 nv->port_name[3] = 0xe0;
7512 nv->port_name[4] = 0x8b;
7513 nv->port_name[5] = 0x1c;
7514 nv->port_name[6] = 0x55;
7515 nv->port_name[7] = 0x86;
7516 nv->node_name[0] = 0x20;
7517 nv->node_name[1] = 0x00;
7518 nv->node_name[2] = 0x00;
7519 nv->node_name[3] = 0xe0;
7520 nv->node_name[4] = 0x8b;
7521 nv->node_name[5] = 0x1c;
7522 nv->node_name[6] = 0x55;
7523 nv->node_name[7] = 0x86;
ad950360
BVA		 7524 nv->login_retry_count = cpu_to_le16(8);
7525 nv->interrupt_delay_timer = cpu_to_le16(0);
7526 nv->login_timeout = cpu_to_le16(0);
3a03eb79 7527 nv->firmware_options_1 =
ad950360
BVA		 7528 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7529 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7530 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7531 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7532 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7533 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 7534 nv->reset_delay = 5;
ad950360
BVA		 7535 nv->max_luns_per_target = cpu_to_le16(128);
7536 nv->port_down_retry_count = cpu_to_le16(30);
7537 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 7538 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 7539 nv->enode_mac[1] = 0xC0;
7540 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 7541 nv->enode_mac[3] = 0x04;
7542 nv->enode_mac[4] = 0x05;
f73cb695 7543 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7544
7545 rval = 1;
7546 }
7547
9e522cd8
AE		 7548 if (IS_T10_PI_CAPABLE(ha))
7549 nv->frame_payload_size &= ~7;
7550
aa230bc5
AE		 7551 qlt_81xx_config_nvram_stage1(vha, nv);
7552
3a03eb79 7553 /* Reset Initialization control block */
773120e4 7554 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 7555
7556 /* Copy 1st segment. */
7557 dptr1 = (uint8_t *)icb;
7558 dptr2 = (uint8_t *)&nv->version;
7559 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7560 while (cnt--)
7561 *dptr1++ = *dptr2++;
7562
7563 icb->login_retry_count = nv->login_retry_count;
7564
7565 /* Copy 2nd segment. */
7566 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7567 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7568 cnt = (uint8_t *)&icb->reserved_5 -
7569 (uint8_t *)&icb->interrupt_delay_timer;
7570 while (cnt--)
7571 *dptr1++ = *dptr2++;
7572
7573 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
7574 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
7575 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 7576 icb->enode_mac[0] = 0x00;
7577 icb->enode_mac[1] = 0xC0;
7578 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 7579 icb->enode_mac[3] = 0x04;
7580 icb->enode_mac[4] = 0x05;
f73cb695 7581 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7582 }
7583
b64b0e8f
AV		 7584 /* Use extended-initialization control block. */
7585 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
7586
3a03eb79
AV		 7587 /*
7588 * Setup driver NVRAM options.
7589 */
7590 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 7591 "QLE8XXX");
3a03eb79 7592
aa230bc5
AE		 7593 qlt_81xx_config_nvram_stage2(vha, icb);
7594
3a03eb79 7595 /* Use alternate WWN? */
ad950360 7596 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 7597 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7598 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7599 }
7600
7601 /* Prepare nodename */
ad950360 7602 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 7603 /*
7604 * Firmware will apply the following mask if the nodename was
7605 * not provided.
7606 */
7607 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7608 icb->node_name[0] &= 0xF0;
7609 }
7610
7611 /* Set host adapter parameters. */
7612 ha->flags.disable_risc_code_load = 0;
7613 ha->flags.enable_lip_reset = 0;
7614 ha->flags.enable_lip_full_login =
7615 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7616 ha->flags.enable_target_reset =
7617 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
7618 ha->flags.enable_led_scheme = 0;
7619 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
7620
7621 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7622 (BIT_6 | BIT_5 | BIT_4)) >> 4;
7623
7624 /* save HBA serial number */
7625 ha->serial0 = icb->port_name[5];
7626 ha->serial1 = icb->port_name[6];
7627 ha->serial2 = icb->port_name[7];
7628 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7629 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7630
ad950360 7631 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 7632
7633 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7634
7635 /* Set minimum login_timeout to 4 seconds. */
7636 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7637 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7638 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7639 nv->login_timeout = cpu_to_le16(4);
3a03eb79 7640 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 7641
7642 /* Set minimum RATOV to 100 tenths of a second. */
7643 ha->r_a_tov = 100;
7644
7645 ha->loop_reset_delay = nv->reset_delay;
7646
7647 /* Link Down Timeout = 0:
7648 *
7ec0effd 7649 * When Port Down timer expires we will start returning
3a03eb79
AV		 7650 * I/O's to OS with "DID_NO_CONNECT".
7651 *
7652 * Link Down Timeout != 0:
7653 *
7654 * The driver waits for the link to come up after link down
7655 * before returning I/Os to OS with "DID_NO_CONNECT".
7656 */
7657 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7658 ha->loop_down_abort_time =
7659 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7660 } else {
7661 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7662 ha->loop_down_abort_time =
7663 (LOOP_DOWN_TIME - ha->link_down_timeout);
7664 }
7665
7666 /* Need enough time to try and get the port back. */
7667 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7668 if (qlport_down_retry)
7669 ha->port_down_retry_count = qlport_down_retry;
7670
7671 /* Set login_retry_count */
7672 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7673 if (ha->port_down_retry_count ==
7674 le16_to_cpu(nv->port_down_retry_count) &&
7675 ha->port_down_retry_count > 3)
7676 ha->login_retry_count = ha->port_down_retry_count;
7677 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7678 ha->login_retry_count = ha->port_down_retry_count;
7679 if (ql2xloginretrycount)
7680 ha->login_retry_count = ql2xloginretrycount;
7681
6246b8a1 7682 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 7683 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 7684 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 7685
3a03eb79
AV		 7686 /* Enable ZIO. */
7687 if (!vha->flags.init_done) {
7688 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7689 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7690 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7691 le16_to_cpu(icb->interrupt_delay_timer): 2;
7692 }
ad950360 7693 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 7694 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
7695 vha->flags.process_response_queue = 0;
7696 if (ha->zio_mode != QLA_ZIO_DISABLED) {
7697 ha->zio_mode = QLA_ZIO_MODE_6;
7698
7c3df132 7699 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 7700 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 7701 ha->zio_mode,
7702 ha->zio_timer * 100);
3a03eb79
AV		 7703
7704 icb->firmware_options_2 |= cpu_to_le32(
7705 (uint32_t)ha->zio_mode);
7706 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
7707 vha->flags.process_response_queue = 1;
7708 }
7709
41dc529a
QT		 7710 /* enable RIDA Format2 */
7711 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha))
7712 icb->firmware_options_3 |= BIT_0;
7713
edd05de1
DG		 7714 if (IS_QLA27XX(ha)) {
7715 icb->firmware_options_3 |= BIT_8;
7716 ql_dbg(ql_log_info, vha, 0x0075,
7717 "Enabling direct connection.\n");
7718 }
7719
3a03eb79 7720 if (rval) {
7c3df132
SK		 7721 ql_log(ql_log_warn, vha, 0x0076,
7722 "NVRAM configuration failed.\n");
3a03eb79
AV		 7723 }
7724 return (rval);
7725}
7726
a9083016
GM		 7727int
7728qla82xx_restart_isp(scsi_qla_host_t *vha)
7729{
7730 int status, rval;
a9083016
GM		 7731 struct qla_hw_data *ha = vha->hw;
7732 struct req_que *req = ha->req_q_map[0];
7733 struct rsp_que *rsp = ha->rsp_q_map[0];
7734 struct scsi_qla_host *vp;
feafb7b1 7735 unsigned long flags;
a9083016
GM		 7736
7737 status = qla2x00_init_rings(vha);
7738 if (!status) {
7739 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7740 ha->flags.chip_reset_done = 1;
7741
7742 status = qla2x00_fw_ready(vha);
7743 if (!status) {
a9083016
GM		 7744 /* Issue a marker after FW becomes ready. */
7745 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 7746 vha->flags.online = 1;
7108b76e 7747 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 7748 }
7749
7750 /* if no cable then assume it's good */
7751 if ((vha->device_flags & DFLG_NO_CABLE))
7752 status = 0;
a9083016
GM		 7753 }
7754
7755 if (!status) {
7756 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7757
7758 if (!atomic_read(&vha->loop_down_timer)) {
7759 /*
7760 * Issue marker command only when we are going
7761 * to start the I/O .
7762 */
7763 vha->marker_needed = 1;
7764 }
7765
a9083016
GM		 7766 ha->isp_ops->enable_intrs(ha);
7767
7768 ha->isp_abort_cnt = 0;
7769 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7770
53296788 7771 /* Update the firmware version */
3173167f 7772 status = qla82xx_check_md_needed(vha);
53296788 7773
a9083016
GM		 7774 if (ha->fce) {
7775 ha->flags.fce_enabled = 1;
7776 memset(ha->fce, 0,
7777 fce_calc_size(ha->fce_bufs));
7778 rval = qla2x00_enable_fce_trace(vha,
7779 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
7780 &ha->fce_bufs);
7781 if (rval) {
cfb0919c 7782 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 7783 "Unable to reinitialize FCE (%d).\n",
7784 rval);
a9083016
GM		 7785 ha->flags.fce_enabled = 0;
7786 }
7787 }
7788
7789 if (ha->eft) {
7790 memset(ha->eft, 0, EFT_SIZE);
7791 rval = qla2x00_enable_eft_trace(vha,
7792 ha->eft_dma, EFT_NUM_BUFFERS);
7793 if (rval) {
cfb0919c 7794 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 7795 "Unable to reinitialize EFT (%d).\n",
7796 rval);
a9083016
GM		 7797 }
7798 }
a9083016
GM		 7799 }
7800
7801 if (!status) {
cfb0919c 7802 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 7803 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 7804
7805 spin_lock_irqsave(&ha->vport_slock, flags);
7806 list_for_each_entry(vp, &ha->vp_list, list) {
7807 if (vp->vp_idx) {
7808 atomic_inc(&vp->vref_count);
7809 spin_unlock_irqrestore(&ha->vport_slock, flags);
7810
a9083016 7811 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 7812
7813 spin_lock_irqsave(&ha->vport_slock, flags);
7814 atomic_dec(&vp->vref_count);
7815 }
a9083016 7816 }
feafb7b1
AE		 7817 spin_unlock_irqrestore(&ha->vport_slock, flags);
7818
a9083016 7819 } else {
cfb0919c 7820 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 7821 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 7822 }
7823
7824 return status;
7825}
7826
3a03eb79 7827void
ae97c91e 7828qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 7829{
ae97c91e
AV		 7830 struct qla_hw_data *ha = vha->hw;
7831
f198cafa
HM		 7832 /* Hold status IOCBs until ABTS response received. */
7833 if (ql2xfwholdabts)
7834 ha->fw_options[3] |= BIT_12;
7835
088d09d4
GM		 7836 /* Set Retry FLOGI in case of P2P connection */
7837 if (ha->operating_mode == P2P) {
7838 ha->fw_options[2] |= BIT_3;
7839 ql_dbg(ql_dbg_disc, vha, 0x2103,
7840 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
7841 __func__, ha->fw_options[2]);
7842 }
7843
41dc529a
QT		 7844 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
7845 if (ql2xmvasynctoatio) {
7846 if (qla_tgt_mode_enabled(vha) ||
7847 qla_dual_mode_enabled(vha))
7848 ha->fw_options[2] |= BIT_11;
7849 else
7850 ha->fw_options[2] &= ~BIT_11;
7851 }
7852
f7e761f5 7853 if (qla_tgt_mode_enabled(vha) ||
2da52737
QT		 7854 qla_dual_mode_enabled(vha)) {
7855 /* FW auto send SCSI status during */
7856 ha->fw_options[1] |= BIT_8;
7857 ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
7858
7859 /* FW perform Exchange validation */
f7e761f5 7860 ha->fw_options[2] |= BIT_4;
2da52737
QT		 7861 } else {
7862 ha->fw_options[1] &= ~BIT_8;
7863 ha->fw_options[10] &= 0x00ff;
7864
f7e761f5 7865 ha->fw_options[2] &= ~BIT_4;
2da52737 7866 }
f7e761f5 7867
41dc529a
QT		 7868 if (ql2xetsenable) {
7869 /* Enable ETS Burst. */
7870 memset(ha->fw_options, 0, sizeof(ha->fw_options));
7871 ha->fw_options[2] |= BIT_9;
7872 }
7873
83548fe2
QT		 7874 ql_dbg(ql_dbg_init, vha, 0x00e9,
7875 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
7876 __func__, ha->fw_options[1], ha->fw_options[2],
7877 ha->fw_options[3], vha->host->active_mode);
ae97c91e 7878
ae97c91e 7879 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 7880}
09ff701a
SR		 7881
7882/*
7883 * qla24xx_get_fcp_prio
7884 * Gets the fcp cmd priority value for the logged in port.
7885 * Looks for a match of the port descriptors within
7886 * each of the fcp prio config entries. If a match is found,
7887 * the tag (priority) value is returned.
7888 *
7889 * Input:
21090cbe 7890 * vha = scsi host structure pointer.
09ff701a
SR		 7891 * fcport = port structure pointer.
7892 *
7893 * Return:
6c452a45 7894 * non-zero (if found)
f28a0a96 7895 * -1 (if not found)
09ff701a
SR		 7896 *
7897 * Context:
7898 * Kernel context
7899 */
f28a0a96 7900static int
09ff701a
SR		 7901qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
7902{
7903 int i, entries;
7904 uint8_t pid_match, wwn_match;
f28a0a96 7905 int priority;
09ff701a
SR		 7906 uint32_t pid1, pid2;
7907 uint64_t wwn1, wwn2;
7908 struct qla_fcp_prio_entry *pri_entry;
7909 struct qla_hw_data *ha = vha->hw;
7910
7911 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 7912 return -1;
09ff701a 7913
f28a0a96 7914 priority = -1;
09ff701a
SR		 7915 entries = ha->fcp_prio_cfg->num_entries;
7916 pri_entry = &ha->fcp_prio_cfg->entry[0];
7917
7918 for (i = 0; i < entries; i++) {
7919 pid_match = wwn_match = 0;
7920
7921 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
7922 pri_entry++;
7923 continue;
7924 }
7925
7926 /* check source pid for a match */
7927 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
7928 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
7929 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
7930 if (pid1 == INVALID_PORT_ID)
7931 pid_match++;
7932 else if (pid1 == pid2)
7933 pid_match++;
7934 }
7935
7936 /* check destination pid for a match */
7937 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
7938 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
7939 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
7940 if (pid1 == INVALID_PORT_ID)
7941 pid_match++;
7942 else if (pid1 == pid2)
7943 pid_match++;
7944 }
7945
7946 /* check source WWN for a match */
7947 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
7948 wwn1 = wwn_to_u64(vha->port_name);
7949 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
7950 if (wwn2 == (uint64_t)-1)
7951 wwn_match++;
7952 else if (wwn1 == wwn2)
7953 wwn_match++;
7954 }
7955
7956 /* check destination WWN for a match */
7957 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
7958 wwn1 = wwn_to_u64(fcport->port_name);
7959 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
7960 if (wwn2 == (uint64_t)-1)
7961 wwn_match++;
7962 else if (wwn1 == wwn2)
7963 wwn_match++;
7964 }
7965
7966 if (pid_match == 2 || wwn_match == 2) {
7967 /* Found a matching entry */
7968 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
7969 priority = pri_entry->tag;
7970 break;
7971 }
7972
7973 pri_entry++;
7974 }
7975
7976 return priority;
7977}
7978
7979/*
7980 * qla24xx_update_fcport_fcp_prio
7981 * Activates fcp priority for the logged in fc port
7982 *
7983 * Input:
21090cbe 7984 * vha = scsi host structure pointer.
09ff701a
SR		 7985 * fcp = port structure pointer.
7986 *
7987 * Return:
7988 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7989 *
7990 * Context:
7991 * Kernel context.
7992 */
7993int
21090cbe 7994qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 7995{
7996 int ret;
f28a0a96 7997 int priority;
09ff701a
SR		 7998 uint16_t mb[5];
7999
21090cbe
MI		 8000 if (fcport->port_type != FCT_TARGET ||
8001 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 8002 return QLA_FUNCTION_FAILED;
8003
21090cbe 8004 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 8005 if (priority < 0)
8006 return QLA_FUNCTION_FAILED;
8007
7ec0effd 8008 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 8009 fcport->fcp_prio = priority & 0xf;
8010 return QLA_SUCCESS;
8011 }
8012
21090cbe 8013 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 8014 if (ret == QLA_SUCCESS) {
8015 if (fcport->fcp_prio != priority)
8016 ql_dbg(ql_dbg_user, vha, 0x709e,
8017 "Updated FCP_CMND priority - value=%d loop_id=%d "
8018 "port_id=%02x%02x%02x.\n", priority,
8019 fcport->loop_id, fcport->d_id.b.domain,
8020 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 8021 fcport->fcp_prio = priority & 0xf;
cfb0919c 8022 } else
7c3df132 8023 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 8024 "Unable to update FCP_CMND priority - ret=0x%x for "
8025 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
8026 fcport->d_id.b.domain, fcport->d_id.b.area,
8027 fcport->d_id.b.al_pa);
09ff701a
SR		 8028 return ret;
8029}
8030
8031/*
8032 * qla24xx_update_all_fcp_prio
8033 * Activates fcp priority for all the logged in ports
8034 *
8035 * Input:
8036 * ha = adapter block pointer.
8037 *
8038 * Return:
8039 * QLA_SUCCESS or QLA_FUNCTION_FAILED
8040 *
8041 * Context:
8042 * Kernel context.
8043 */
8044int
8045qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
8046{
8047 int ret;
8048 fc_port_t *fcport;
8049
8050 ret = QLA_FUNCTION_FAILED;
8051 /* We need to set priority for all logged in ports */
8052 list_for_each_entry(fcport, &vha->vp_fcports, list)
8053 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
8054
8055 return ret;
8056}
d7459527 8057
82de802a
QT		 8058struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
8059 int vp_idx, bool startqp)
d7459527
MH		 8060{
8061 int rsp_id = 0;
8062 int req_id = 0;
8063 int i;
8064 struct qla_hw_data *ha = vha->hw;
8065 uint16_t qpair_id = 0;
8066 struct qla_qpair *qpair = NULL;
8067 struct qla_msix_entry *msix;
8068
8069 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
8070 ql_log(ql_log_warn, vha, 0x00181,
8071 "FW/Driver is not multi-queue capable.\n");
8072 return NULL;
8073 }
8074
c38d1baf 8075 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 8076 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
8077 if (qpair == NULL) {
8078 ql_log(ql_log_warn, vha, 0x0182,
8079 "Failed to allocate memory for queue pair.\n");
8080 return NULL;
8081 }
8082 memset(qpair, 0, sizeof(struct qla_qpair));
8083
8084 qpair->hw = vha->hw;
25ff6af1 8085 qpair->vha = vha;
82de802a
QT		 8086 qpair->qp_lock_ptr = &qpair->qp_lock;
8087 spin_lock_init(&qpair->qp_lock);
af7bb382 8088 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d7459527
MH		 8089
8090 /* Assign available que pair id */
8091 mutex_lock(&ha->mq_lock);
8092 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 8093 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 8094 mutex_unlock(&ha->mq_lock);
8095 ql_log(ql_log_warn, vha, 0x0183,
8096 "No resources to create additional q pair.\n");
8097 goto fail_qid_map;
8098 }
b95b9452 8099 ha->num_qpairs++;
d7459527
MH		 8100 set_bit(qpair_id, ha->qpair_qid_map);
8101 ha->queue_pair_map[qpair_id] = qpair;
8102 qpair->id = qpair_id;
8103 qpair->vp_idx = vp_idx;
e6373f33 8104 qpair->fw_started = ha->flags.fw_started;
e326d22a 8105 INIT_LIST_HEAD(&qpair->hints_list);
cf19c45d 8106 INIT_LIST_HEAD(&qpair->nvme_done_list);
7c3f8fd1
QT		 8107 qpair->chip_reset = ha->base_qpair->chip_reset;
8108 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
8109 qpair->enable_explicit_conf =
8110 ha->base_qpair->enable_explicit_conf;
d7459527
MH		 8111
8112 for (i = 0; i < ha->msix_count; i++) {
093df737 8113 msix = &ha->msix_entries[i];
d7459527
MH		 8114 if (msix->in_use)
8115 continue;
8116 qpair->msix = msix;
83548fe2 8117 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
d7459527
MH		 8118 "Vector %x selected for qpair\n", msix->vector);
8119 break;
8120 }
8121 if (!qpair->msix) {
8122 ql_log(ql_log_warn, vha, 0x0184,
8123 "Out of MSI-X vectors!.\n");
8124 goto fail_msix;
8125 }
8126
8127 qpair->msix->in_use = 1;
8128 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
8abfa9e2
QT		 8129 qpair->pdev = ha->pdev;
8130 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
8131 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
d7459527
MH		 8132
8133 mutex_unlock(&ha->mq_lock);
8134
8135 /* Create response queue first */
82de802a 8136 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
d7459527
MH		 8137 if (!rsp_id) {
8138 ql_log(ql_log_warn, vha, 0x0185,
8139 "Failed to create response queue.\n");
8140 goto fail_rsp;
8141 }
8142
8143 qpair->rsp = ha->rsp_q_map[rsp_id];
8144
8145 /* Create request queue */
82de802a
QT		 8146 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
8147 startqp);
d7459527
MH		 8148 if (!req_id) {
8149 ql_log(ql_log_warn, vha, 0x0186,
8150 "Failed to create request queue.\n");
8151 goto fail_req;
8152 }
8153
8154 qpair->req = ha->req_q_map[req_id];
8155 qpair->rsp->req = qpair->req;
82de802a 8156 qpair->rsp->qpair = qpair;
e326d22a
QT		 8157 /* init qpair to this cpu. Will adjust at run time. */
8158 qla_cpu_update(qpair, smp_processor_id());
d7459527
MH		 8159
8160 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
8161 if (ha->fw_attributes & BIT_4)
8162 qpair->difdix_supported = 1;
8163 }
8164
8165 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
8166 if (!qpair->srb_mempool) {
83548fe2 8167 ql_log(ql_log_warn, vha, 0xd036,
d7459527
MH		 8168 "Failed to create srb mempool for qpair %d\n",
8169 qpair->id);
8170 goto fail_mempool;
8171 }
8172
8173 /* Mark as online */
8174 qpair->online = 1;
8175
8176 if (!vha->flags.qpairs_available)
8177 vha->flags.qpairs_available = 1;
8178
8179 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
8180 "Request/Response queue pair created, id %d\n",
8181 qpair->id);
8182 ql_dbg(ql_dbg_init, vha, 0x0187,
8183 "Request/Response queue pair created, id %d\n",
8184 qpair->id);
8185 }
8186 return qpair;
8187
8188fail_mempool:
8189fail_req:
8190 qla25xx_delete_rsp_que(vha, qpair->rsp);
8191fail_rsp:
8192 mutex_lock(&ha->mq_lock);
8193 qpair->msix->in_use = 0;
8194 list_del(&qpair->qp_list_elem);
8195 if (list_empty(&vha->qp_list))
8196 vha->flags.qpairs_available = 0;
8197fail_msix:
8198 ha->queue_pair_map[qpair_id] = NULL;
8199 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 8200 ha->num_qpairs--;
d7459527
MH		 8201 mutex_unlock(&ha->mq_lock);
8202fail_qid_map:
8203 kfree(qpair);
8204 return NULL;
8205}
8206
8207int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
8208{
d65237c7 8209 int ret = QLA_FUNCTION_FAILED;
d7459527
MH		 8210 struct qla_hw_data *ha = qpair->hw;
8211
d65237c7
SC		 8212 if (!vha->flags.qpairs_req_created && !vha->flags.qpairs_rsp_created)
8213 goto fail;
8214
d7459527
MH		 8215 qpair->delete_in_progress = 1;
8216 while (atomic_read(&qpair->ref_count))
8217 msleep(500);
8218
8219 ret = qla25xx_delete_req_que(vha, qpair->req);
8220 if (ret != QLA_SUCCESS)
8221 goto fail;
8222 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
8223 if (ret != QLA_SUCCESS)
8224 goto fail;
8225
8226 mutex_lock(&ha->mq_lock);
8227 ha->queue_pair_map[qpair->id] = NULL;
8228 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 8229 ha->num_qpairs--;
d7459527 8230 list_del(&qpair->qp_list_elem);
d65237c7 8231 if (list_empty(&vha->qp_list)) {
d7459527 8232 vha->flags.qpairs_available = 0;
d65237c7
SC		 8233 vha->flags.qpairs_req_created = 0;
8234 vha->flags.qpairs_rsp_created = 0;
8235 }
d7459527
MH		 8236 mempool_destroy(qpair->srb_mempool);
8237 kfree(qpair);
8238 mutex_unlock(&ha->mq_lock);
8239
8240 return QLA_SUCCESS;
8241fail:
8242 return ret;
8243}
Linux 6.x block layer and io_uring tree(s)