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qla2xxx: Add serdes read/write support for ISP27XX
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
faef62d1 274qla2x00_tmf_iocb_timeout(void *data)
3822263e 275{
faef62d1
AB		 276 srb_t *sp = (srb_t *)data;
277 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 278
faef62d1
AB		 279 tmf->u.tmf.comp_status = CS_TIMEOUT;
280 complete(&tmf->u.tmf.comp);
281}
9ba56b95 282
faef62d1
AB		 283static void
284qla2x00_tmf_sp_done(void *data, void *ptr, int res)
285{
286 srb_t *sp = (srb_t *)ptr;
287 struct srb_iocb *tmf = &sp->u.iocb_cmd;
288 complete(&tmf->u.tmf.comp);
3822263e
MI		 289}
290
291int
faef62d1 292qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 293 uint32_t tag)
294{
295 struct scsi_qla_host *vha = fcport->vha;
faef62d1 296 struct srb_iocb *tm_iocb;
3822263e 297 srb_t *sp;
faef62d1 298 int rval = QLA_FUNCTION_FAILED;
3822263e 299
9ba56b95 300 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 301 if (!sp)
302 goto done;
303
faef62d1 304 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 305 sp->type = SRB_TM_CMD;
306 sp->name = "tmf";
faef62d1
AB		 307 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
308 tm_iocb->u.tmf.flags = flags;
309 tm_iocb->u.tmf.lun = lun;
310 tm_iocb->u.tmf.data = tag;
311 sp->done = qla2x00_tmf_sp_done;
312 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
313 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 314
315 rval = qla2x00_start_sp(sp);
316 if (rval != QLA_SUCCESS)
317 goto done_free_sp;
318
7c3df132 319 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 320 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
321 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
322 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 323
324 wait_for_completion(&tm_iocb->u.tmf.comp);
325
326 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
327 QLA_SUCCESS : QLA_FUNCTION_FAILED;
328
329 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
330 ql_dbg(ql_dbg_taskm, vha, 0x8030,
331 "TM IOCB failed (%x).\n", rval);
332 }
333
334 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
335 flags = tm_iocb->u.tmf.flags;
336 lun = (uint16_t)tm_iocb->u.tmf.lun;
337
338 /* Issue Marker IOCB */
339 qla2x00_marker(vha, vha->hw->req_q_map[0],
340 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
341 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
342 }
3822263e
MI		 343
344done_free_sp:
faef62d1 345 sp->free(vha, sp);
3822263e
MI		 346done:
347 return rval;
348}
349
4440e46d
AB		 350static void
351qla24xx_abort_iocb_timeout(void *data)
352{
353 srb_t *sp = (srb_t *)data;
354 struct srb_iocb *abt = &sp->u.iocb_cmd;
355
356 abt->u.abt.comp_status = CS_TIMEOUT;
357 complete(&abt->u.abt.comp);
358}
359
360static void
361qla24xx_abort_sp_done(void *data, void *ptr, int res)
362{
363 srb_t *sp = (srb_t *)ptr;
364 struct srb_iocb *abt = &sp->u.iocb_cmd;
365
366 complete(&abt->u.abt.comp);
367}
368
369static int
370qla24xx_async_abort_cmd(srb_t *cmd_sp)
371{
372 scsi_qla_host_t *vha = cmd_sp->fcport->vha;
373 fc_port_t *fcport = cmd_sp->fcport;
374 struct srb_iocb *abt_iocb;
375 srb_t *sp;
376 int rval = QLA_FUNCTION_FAILED;
377
378 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
379 if (!sp)
380 goto done;
381
382 abt_iocb = &sp->u.iocb_cmd;
383 sp->type = SRB_ABT_CMD;
384 sp->name = "abort";
385 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
386 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
387 sp->done = qla24xx_abort_sp_done;
388 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
389 init_completion(&abt_iocb->u.abt.comp);
390
391 rval = qla2x00_start_sp(sp);
392 if (rval != QLA_SUCCESS)
393 goto done_free_sp;
394
395 ql_dbg(ql_dbg_async, vha, 0x507c,
396 "Abort command issued - hdl=%x, target_id=%x\n",
397 cmd_sp->handle, fcport->tgt_id);
398
399 wait_for_completion(&abt_iocb->u.abt.comp);
400
401 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
402 QLA_SUCCESS : QLA_FUNCTION_FAILED;
403
404done_free_sp:
405 sp->free(vha, sp);
406done:
407 return rval;
408}
409
410int
411qla24xx_async_abort_command(srb_t *sp)
412{
413 unsigned long flags = 0;
414
415 uint32_t handle;
416 fc_port_t *fcport = sp->fcport;
417 struct scsi_qla_host *vha = fcport->vha;
418 struct qla_hw_data *ha = vha->hw;
419 struct req_que *req = vha->req;
420
421 spin_lock_irqsave(&ha->hardware_lock, flags);
422 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
423 if (req->outstanding_cmds[handle] == sp)
424 break;
425 }
426 spin_unlock_irqrestore(&ha->hardware_lock, flags);
427 if (handle == req->num_outstanding_cmds) {
428 /* Command not found. */
429 return QLA_FUNCTION_FAILED;
430 }
431 if (sp->type == SRB_FXIOCB_DCMD)
432 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
433 FXDISC_ABORT_IOCTL);
434
435 return qla24xx_async_abort_cmd(sp);
436}
437
4916392b 438void
ac280b67
AV		 439qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
440 uint16_t *data)
441{
442 int rval;
ac280b67
AV		 443
444 switch (data[0]) {
445 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 446 /*
447 * Driver must validate login state - If PRLI not complete,
448 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
449 * requests.
450 */
451 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 452 if (rval == QLA_NOT_LOGGED_IN) {
453 fcport->flags &= ~FCF_ASYNC_SENT;
454 fcport->flags |= FCF_LOGIN_NEEDED;
455 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
456 break;
457 }
458
a4f92a32
AV		 459 if (rval != QLA_SUCCESS) {
460 qla2x00_post_async_logout_work(vha, fcport, NULL);
461 qla2x00_post_async_login_work(vha, fcport, NULL);
462 break;
463 }
99b0bec7 464 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 465 qla2x00_post_async_adisc_work(vha, fcport, data);
466 break;
99b0bec7
AV		 467 }
468 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 469 break;
470 case MBS_COMMAND_ERROR:
5ff1d584 471 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 472 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
474 else
80d79440 475 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 476 break;
477 case MBS_PORT_ID_USED:
478 fcport->loop_id = data[1];
6ac52608 479 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 480 qla2x00_post_async_login_work(vha, fcport, NULL);
481 break;
482 case MBS_LOOP_ID_USED:
483 fcport->loop_id++;
484 rval = qla2x00_find_new_loop_id(vha, fcport);
485 if (rval != QLA_SUCCESS) {
5ff1d584 486 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 487 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 488 break;
489 }
490 qla2x00_post_async_login_work(vha, fcport, NULL);
491 break;
492 }
4916392b 493 return;
ac280b67
AV		 494}
495
4916392b 496void
ac280b67
AV		 497qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
498 uint16_t *data)
499{
500 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 501 return;
ac280b67
AV		 502}
503
4916392b 504void
5ff1d584
AV		 505qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
506 uint16_t *data)
507{
508 if (data[0] == MBS_COMMAND_COMPLETE) {
509 qla2x00_update_fcport(vha, fcport);
510
4916392b 511 return;
5ff1d584
AV		 512 }
513
514 /* Retry login. */
515 fcport->flags &= ~FCF_ASYNC_SENT;
516 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
517 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
518 else
80d79440 519 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 520
4916392b 521 return;
5ff1d584
AV		 522}
523
1da177e4
LT		 524/****************************************************************************/
525/* QLogic ISP2x00 Hardware Support Functions. */
526/****************************************************************************/
527
fa492630 528static int
7d613ac6
SV		 529qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
530{
531 int rval = QLA_SUCCESS;
532 struct qla_hw_data *ha = vha->hw;
533 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 534 uint16_t config[4];
7d613ac6
SV		 535
536 qla83xx_idc_lock(vha, 0);
537
538 /* SV: TODO: Assign initialization timeout from
539 * flash-info / other param
540 */
541 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
542 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
543
544 /* Set our fcoe function presence */
545 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
546 ql_dbg(ql_dbg_p3p, vha, 0xb077,
547 "Error while setting DRV-Presence.\n");
548 rval = QLA_FUNCTION_FAILED;
549 goto exit;
550 }
551
552 /* Decide the reset ownership */
553 qla83xx_reset_ownership(vha);
554
555 /*
556 * On first protocol driver load:
557 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
558 * register.
559 * Others: Check compatibility with current IDC Major version.
560 */
561 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
562 if (ha->flags.nic_core_reset_owner) {
563 /* Set IDC Major version */
564 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
565 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
566
567 /* Clearing IDC-Lock-Recovery register */
568 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
569 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
570 /*
571 * Clear further IDC participation if we are not compatible with
572 * the current IDC Major Version.
573 */
574 ql_log(ql_log_warn, vha, 0xb07d,
575 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
576 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
577 __qla83xx_clear_drv_presence(vha);
578 rval = QLA_FUNCTION_FAILED;
579 goto exit;
580 }
581 /* Each function sets its supported Minor version. */
582 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
583 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
584 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
585
711aa7f7
SK		 586 if (ha->flags.nic_core_reset_owner) {
587 memset(config, 0, sizeof(config));
588 if (!qla81xx_get_port_config(vha, config))
589 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
590 QLA8XXX_DEV_READY);
591 }
592
7d613ac6
SV		 593 rval = qla83xx_idc_state_handler(vha);
594
595exit:
596 qla83xx_idc_unlock(vha, 0);
597
598 return rval;
599}
600
1da177e4
LT		 601/*
602* qla2x00_initialize_adapter
603* Initialize board.
604*
605* Input:
606* ha = adapter block pointer.
607*
608* Returns:
609* 0 = success
610*/
611int
e315cd28 612qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 613{
614 int rval;
e315cd28 615 struct qla_hw_data *ha = vha->hw;
73208dfd 616 struct req_que *req = ha->req_q_map[0];
2533cf67 617
1da177e4 618 /* Clear adapter flags. */
e315cd28 619 vha->flags.online = 0;
2533cf67 620 ha->flags.chip_reset_done = 0;
e315cd28 621 vha->flags.reset_active = 0;
85880801
AV		 622 ha->flags.pci_channel_io_perm_failure = 0;
623 ha->flags.eeh_busy = 0;
fabbb8df 624 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 625 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
626 atomic_set(&vha->loop_state, LOOP_DOWN);
627 vha->device_flags = DFLG_NO_CABLE;
628 vha->dpc_flags = 0;
629 vha->flags.management_server_logged_in = 0;
630 vha->marker_needed = 0;
1da177e4
LT		 631 ha->isp_abort_cnt = 0;
632 ha->beacon_blink_led = 0;
633
73208dfd
AC		 634 set_bit(0, ha->req_qid_map);
635 set_bit(0, ha->rsp_qid_map);
636
cfb0919c 637 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 638 "Configuring PCI space...\n");
e315cd28 639 rval = ha->isp_ops->pci_config(vha);
1da177e4 640 if (rval) {
7c3df132
SK		 641 ql_log(ql_log_warn, vha, 0x0044,
642 "Unable to configure PCI space.\n");
1da177e4
LT		 643 return (rval);
644 }
645
e315cd28 646 ha->isp_ops->reset_chip(vha);
1da177e4 647
e315cd28 648 rval = qla2xxx_get_flash_info(vha);
c00d8994 649 if (rval) {
7c3df132
SK		 650 ql_log(ql_log_fatal, vha, 0x004f,
651 "Unable to validate FLASH data.\n");
7ec0effd
AD		 652 return rval;
653 }
654
655 if (IS_QLA8044(ha)) {
656 qla8044_read_reset_template(vha);
657
658 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
659 * If DONRESET_BIT0 is set, drivers should not set dev_state
660 * to NEED_RESET. But if NEED_RESET is set, drivers should
661 * should honor the reset. */
662 if (ql2xdontresethba == 1)
663 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 664 }
665
73208dfd 666 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 667 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 668 "Configure NVRAM parameters...\n");
0107109e 669
e315cd28 670 ha->isp_ops->nvram_config(vha);
1da177e4 671
d4c760c2
AV		 672 if (ha->flags.disable_serdes) {
673 /* Mask HBA via NVRAM settings? */
7c3df132 674 ql_log(ql_log_info, vha, 0x0077,
7b833558 675 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 676 return QLA_FUNCTION_FAILED;
677 }
678
cfb0919c 679 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 680 "Verifying loaded RISC code...\n");
1da177e4 681
e315cd28
AC		 682 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
683 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 684 if (rval)
685 return (rval);
e315cd28 686 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 687 if (rval)
688 return (rval);
1da177e4 689 }
a9083016 690
4d4df193 691 if (IS_QLA84XX(ha)) {
e315cd28 692 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 693 if (!ha->cs84xx) {
7c3df132 694 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 695 "Unable to configure ISP84XX.\n");
696 return QLA_FUNCTION_FAILED;
697 }
698 }
2d70c103
NB		 699
700 if (qla_ini_mode_enabled(vha))
701 rval = qla2x00_init_rings(vha);
702
2533cf67 703 ha->flags.chip_reset_done = 1;
1da177e4 704
9a069e19 705 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 706 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 707 rval = qla84xx_init_chip(vha);
708 if (rval != QLA_SUCCESS) {
7c3df132
SK		 709 ql_log(ql_log_warn, vha, 0x00d4,
710 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 711 qla84xx_put_chip(vha);
712 }
713 }
714
7d613ac6
SV		 715 /* Load the NIC Core f/w if we are the first protocol driver. */
716 if (IS_QLA8031(ha)) {
717 rval = qla83xx_nic_core_fw_load(vha);
718 if (rval)
719 ql_log(ql_log_warn, vha, 0x0124,
720 "Error in initializing NIC Core f/w.\n");
721 }
722
2f0f3f4f
MI		 723 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
724 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 725
c46e65c7
JC		 726 if (IS_P3P_TYPE(ha))
727 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
728 else
729 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
730
1da177e4
LT		 731 return (rval);
732}
733
734/**
abbd8870 735 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 736 * @ha: HA context
737 *
738 * Returns 0 on success.
739 */
abbd8870 740int
e315cd28 741qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 742{
a157b101 743 uint16_t w;
abbd8870 744 unsigned long flags;
e315cd28 745 struct qla_hw_data *ha = vha->hw;
3d71644c 746 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 747
1da177e4 748 pci_set_master(ha->pdev);
af6177d8 749 pci_try_set_mwi(ha->pdev);
1da177e4 750
1da177e4 751 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 752 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 753 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
754
737faece 755 pci_disable_rom(ha->pdev);
1da177e4
LT		 756
757 /* Get PCI bus information. */
758 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 759 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 760 spin_unlock_irqrestore(&ha->hardware_lock, flags);
761
abbd8870
AV		 762 return QLA_SUCCESS;
763}
1da177e4 764
abbd8870
AV		 765/**
766 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
767 * @ha: HA context
768 *
769 * Returns 0 on success.
770 */
771int
e315cd28 772qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 773{
a157b101 774 uint16_t w;
abbd8870
AV		 775 unsigned long flags = 0;
776 uint32_t cnt;
e315cd28 777 struct qla_hw_data *ha = vha->hw;
3d71644c 778 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 779
abbd8870 780 pci_set_master(ha->pdev);
af6177d8 781 pci_try_set_mwi(ha->pdev);
1da177e4 782
abbd8870 783 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 784 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 785
abbd8870
AV		 786 if (IS_QLA2322(ha) || IS_QLA6322(ha))
787 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 788 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 789
abbd8870
AV		 790 /*
791 * If this is a 2300 card and not 2312, reset the
792 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
793 * the 2310 also reports itself as a 2300 so we need to get the
794 * fb revision level -- a 6 indicates it really is a 2300 and
795 * not a 2310.
796 */
797 if (IS_QLA2300(ha)) {
798 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 799
abbd8870 800 /* Pause RISC. */
3d71644c 801 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 802 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 803 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 804 break;
1da177e4 805
abbd8870
AV		 806 udelay(10);
807 }
1da177e4 808
abbd8870 809 /* Select FPM registers. */
3d71644c
AV		 810 WRT_REG_WORD(&reg->ctrl_status, 0x20);
811 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 812
813 /* Get the fb rev level */
3d71644c 814 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 815
816 if (ha->fb_rev == FPM_2300)
a157b101 817 pci_clear_mwi(ha->pdev);
abbd8870
AV		 818
819 /* Deselect FPM registers. */
3d71644c
AV		 820 WRT_REG_WORD(&reg->ctrl_status, 0x0);
821 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 822
823 /* Release RISC module. */
3d71644c 824 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 825 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 826 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 827 break;
828
829 udelay(10);
1da177e4 830 }
1da177e4 831
abbd8870
AV		 832 spin_unlock_irqrestore(&ha->hardware_lock, flags);
833 }
1da177e4 834
abbd8870
AV		 835 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
836
737faece 837 pci_disable_rom(ha->pdev);
1da177e4 838
abbd8870
AV		 839 /* Get PCI bus information. */
840 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 841 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 842 spin_unlock_irqrestore(&ha->hardware_lock, flags);
843
844 return QLA_SUCCESS;
1da177e4
LT		 845}
846
0107109e
AV		 847/**
848 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
849 * @ha: HA context
850 *
851 * Returns 0 on success.
852 */
853int
e315cd28 854qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 855{
a157b101 856 uint16_t w;
0107109e 857 unsigned long flags = 0;
e315cd28 858 struct qla_hw_data *ha = vha->hw;
0107109e 859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 860
861 pci_set_master(ha->pdev);
af6177d8 862 pci_try_set_mwi(ha->pdev);
0107109e
AV		 863
864 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 865 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 866 w &= ~PCI_COMMAND_INTX_DISABLE;
867 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
868
869 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
870
871 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 872 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
873 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 874
875 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 876 if (pci_is_pcie(ha->pdev))
5ffd3a52 877 pcie_set_readrq(ha->pdev, 4096);
0107109e 878
737faece 879 pci_disable_rom(ha->pdev);
0107109e 880
44c10138 881 ha->chip_revision = ha->pdev->revision;
a8488abe 882
0107109e
AV		 883 /* Get PCI bus information. */
884 spin_lock_irqsave(&ha->hardware_lock, flags);
885 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
887
888 return QLA_SUCCESS;
889}
890
c3a2f0df
AV		 891/**
892 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
893 * @ha: HA context
894 *
895 * Returns 0 on success.
896 */
897int
e315cd28 898qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 899{
900 uint16_t w;
e315cd28 901 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 902
903 pci_set_master(ha->pdev);
904 pci_try_set_mwi(ha->pdev);
905
906 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
907 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
908 w &= ~PCI_COMMAND_INTX_DISABLE;
909 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
910
911 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 912 if (pci_is_pcie(ha->pdev))
5ffd3a52 913 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 914
737faece 915 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 916
917 ha->chip_revision = ha->pdev->revision;
918
919 return QLA_SUCCESS;
920}
921
1da177e4
LT		 922/**
923 * qla2x00_isp_firmware() - Choose firmware image.
924 * @ha: HA context
925 *
926 * Returns 0 on success.
927 */
928static int
e315cd28 929qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 930{
931 int rval;
42e421b1
AV		 932 uint16_t loop_id, topo, sw_cap;
933 uint8_t domain, area, al_pa;
e315cd28 934 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 935
936 /* Assume loading risc code */
fa2a1ce5 937 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 938
939 if (ha->flags.disable_risc_code_load) {
7c3df132 940 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 941
942 /* Verify checksum of loaded RISC code. */
e315cd28 943 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 944 if (rval == QLA_SUCCESS) {
945 /* And, verify we are not in ROM code. */
e315cd28 946 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 947 &area, &domain, &topo, &sw_cap);
948 }
1da177e4
LT		 949 }
950
7c3df132
SK		 951 if (rval)
952 ql_dbg(ql_dbg_init, vha, 0x007a,
953 "**** Load RISC code ****.\n");
1da177e4
LT		 954
955 return (rval);
956}
957
958/**
959 * qla2x00_reset_chip() - Reset ISP chip.
960 * @ha: HA context
961 *
962 * Returns 0 on success.
963 */
abbd8870 964void
e315cd28 965qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 966{
967 unsigned long flags = 0;
e315cd28 968 struct qla_hw_data *ha = vha->hw;
3d71644c 969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 970 uint32_t cnt;
1da177e4
LT		 971 uint16_t cmd;
972
85880801
AV		 973 if (unlikely(pci_channel_offline(ha->pdev)))
974 return;
975
fd34f556 976 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 977
978 spin_lock_irqsave(&ha->hardware_lock, flags);
979
980 /* Turn off master enable */
981 cmd = 0;
982 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
983 cmd &= ~PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 if (!IS_QLA2100(ha)) {
987 /* Pause RISC. */
988 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
989 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
990 for (cnt = 0; cnt < 30000; cnt++) {
991 if ((RD_REG_WORD(&reg->hccr) &
992 HCCR_RISC_PAUSE) != 0)
993 break;
994 udelay(100);
995 }
996 } else {
997 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
998 udelay(10);
999 }
1000
1001 /* Select FPM registers. */
1002 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1003 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1004
1005 /* FPM Soft Reset. */
1006 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1007 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1008
1009 /* Toggle Fpm Reset. */
1010 if (!IS_QLA2200(ha)) {
1011 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1012 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1013 }
1014
1015 /* Select frame buffer registers. */
1016 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1017 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1018
1019 /* Reset frame buffer FIFOs. */
1020 if (IS_QLA2200(ha)) {
1021 WRT_FB_CMD_REG(ha, reg, 0xa000);
1022 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1023 } else {
1024 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1025
1026 /* Read back fb_cmd until zero or 3 seconds max */
1027 for (cnt = 0; cnt < 3000; cnt++) {
1028 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1029 break;
1030 udelay(100);
1031 }
1032 }
1033
1034 /* Select RISC module registers. */
1035 WRT_REG_WORD(&reg->ctrl_status, 0);
1036 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1037
1038 /* Reset RISC processor. */
1039 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1040 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1041
1042 /* Release RISC processor. */
1043 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1044 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1045 }
1046
1047 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1048 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1049
1050 /* Reset ISP chip. */
1051 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1052
1053 /* Wait for RISC to recover from reset. */
1054 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1055 /*
1056 * It is necessary to for a delay here since the card doesn't
1057 * respond to PCI reads during a reset. On some architectures
1058 * this will result in an MCA.
1059 */
1060 udelay(20);
1061 for (cnt = 30000; cnt; cnt--) {
1062 if ((RD_REG_WORD(&reg->ctrl_status) &
1063 CSR_ISP_SOFT_RESET) == 0)
1064 break;
1065 udelay(100);
1066 }
1067 } else
1068 udelay(10);
1069
1070 /* Reset RISC processor. */
1071 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1072
1073 WRT_REG_WORD(&reg->semaphore, 0);
1074
1075 /* Release RISC processor. */
1076 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1077 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1078
1079 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1080 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1081 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1082 break;
1da177e4
LT		 1083
1084 udelay(100);
1085 }
1086 } else
1087 udelay(100);
1088
1089 /* Turn on master enable */
1090 cmd |= PCI_COMMAND_MASTER;
1091 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1092
1093 /* Disable RISC pause on FPM parity error. */
1094 if (!IS_QLA2100(ha)) {
1095 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1096 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1097 }
1098
1099 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1100}
1101
b1d46989
MI		 1102/**
1103 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1104 *
1105 * Returns 0 on success.
1106 */
fa492630 1107static int
b1d46989
MI		 1108qla81xx_reset_mpi(scsi_qla_host_t *vha)
1109{
1110 uint16_t mb[4] = {0x1010, 0, 1, 0};
1111
6246b8a1
GM		 1112 if (!IS_QLA81XX(vha->hw))
1113 return QLA_SUCCESS;
1114
b1d46989
MI		 1115 return qla81xx_write_mpi_register(vha, mb);
1116}
1117
0107109e 1118/**
88c26663 1119 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1120 * @ha: HA context
1121 *
1122 * Returns 0 on success.
1123 */
88c26663 1124static inline void
e315cd28 1125qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1126{
1127 unsigned long flags = 0;
e315cd28 1128 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1129 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1130 uint32_t cnt, d2;
335a1cc9 1131 uint16_t wd;
b1d46989 1132 static int abts_cnt; /* ISP abort retry counts */
0107109e 1133
0107109e
AV		 1134 spin_lock_irqsave(&ha->hardware_lock, flags);
1135
1136 /* Reset RISC. */
1137 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1138 for (cnt = 0; cnt < 30000; cnt++) {
1139 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1140 break;
1141
1142 udelay(10);
1143 }
1144
1145 WRT_REG_DWORD(&reg->ctrl_status,
1146 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1147 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1148
335a1cc9 1149 udelay(100);
88c26663 1150 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1151 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1152 for (cnt = 10000 ; cnt && d2; cnt--) {
1153 udelay(5);
1154 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1155 barrier();
1156 }
1157
335a1cc9 1158 /* Wait for soft-reset to complete. */
0107109e
AV		 1159 d2 = RD_REG_DWORD(&reg->ctrl_status);
1160 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1161 udelay(5);
1162 d2 = RD_REG_DWORD(&reg->ctrl_status);
1163 barrier();
1164 }
1165
b1d46989
MI		 1166 /* If required, do an MPI FW reset now */
1167 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1168 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1169 if (++abts_cnt < 5) {
1170 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1171 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1172 } else {
1173 /*
1174 * We exhausted the ISP abort retries. We have to
1175 * set the board offline.
1176 */
1177 abts_cnt = 0;
1178 vha->flags.online = 0;
1179 }
1180 }
1181 }
1182
0107109e
AV		 1183 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1184 RD_REG_DWORD(&reg->hccr);
1185
1186 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1187 RD_REG_DWORD(&reg->hccr);
1188
1189 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1190 RD_REG_DWORD(&reg->hccr);
1191
1192 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1193 for (cnt = 6000000 ; cnt && d2; cnt--) {
1194 udelay(5);
1195 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1196 barrier();
1197 }
1198
1199 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1200
1201 if (IS_NOPOLLING_TYPE(ha))
1202 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1203}
1204
4ea2c9c7
JC		 1205static void
1206qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1207{
1208 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1209
1210 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1211 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1212
1213}
1214
1215static void
1216qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1217{
1218 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1219
1220 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1221 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1222}
1223
1224static void
1225qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1226{
1227 struct qla_hw_data *ha = vha->hw;
1228 uint32_t wd32 = 0;
1229 uint delta_msec = 100;
1230 uint elapsed_msec = 0;
1231 uint timeout_msec;
1232 ulong n;
1233
1234 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1235 return;
1236
1237attempt:
1238 timeout_msec = TIMEOUT_SEMAPHORE;
1239 n = timeout_msec / delta_msec;
1240 while (n--) {
1241 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1242 qla25xx_read_risc_sema_reg(vha, &wd32);
1243 if (wd32 & RISC_SEMAPHORE)
1244 break;
1245 msleep(delta_msec);
1246 elapsed_msec += delta_msec;
1247 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1248 goto force;
1249 }
1250
1251 if (!(wd32 & RISC_SEMAPHORE))
1252 goto force;
1253
1254 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1255 goto acquired;
1256
1257 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1258 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1259 n = timeout_msec / delta_msec;
1260 while (n--) {
1261 qla25xx_read_risc_sema_reg(vha, &wd32);
1262 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1263 break;
1264 msleep(delta_msec);
1265 elapsed_msec += delta_msec;
1266 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1267 goto force;
1268 }
1269
1270 if (wd32 & RISC_SEMAPHORE_FORCE)
1271 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1272
1273 goto attempt;
1274
1275force:
1276 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1277
1278acquired:
1279 return;
1280}
1281
88c26663
AV		 1282/**
1283 * qla24xx_reset_chip() - Reset ISP24xx chip.
1284 * @ha: HA context
1285 *
1286 * Returns 0 on success.
1287 */
1288void
e315cd28 1289qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1290{
e315cd28 1291 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1292
1293 if (pci_channel_offline(ha->pdev) &&
1294 ha->flags.pci_channel_io_perm_failure) {
1295 return;
1296 }
1297
fd34f556 1298 ha->isp_ops->disable_intrs(ha);
88c26663 1299
4ea2c9c7
JC		 1300 qla25xx_manipulate_risc_semaphore(vha);
1301
88c26663 1302 /* Perform RISC reset. */
e315cd28 1303 qla24xx_reset_risc(vha);
88c26663
AV		 1304}
1305
1da177e4
LT		 1306/**
1307 * qla2x00_chip_diag() - Test chip for proper operation.
1308 * @ha: HA context
1309 *
1310 * Returns 0 on success.
1311 */
abbd8870 1312int
e315cd28 1313qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1314{
1315 int rval;
e315cd28 1316 struct qla_hw_data *ha = vha->hw;
3d71644c 1317 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1318 unsigned long flags = 0;
1319 uint16_t data;
1320 uint32_t cnt;
1321 uint16_t mb[5];
73208dfd 1322 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1323
1324 /* Assume a failed state */
1325 rval = QLA_FUNCTION_FAILED;
1326
7c3df132
SK		 1327 ql_dbg(ql_dbg_init, vha, 0x007b,
1328 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1329
1330 spin_lock_irqsave(&ha->hardware_lock, flags);
1331
1332 /* Reset ISP chip. */
1333 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1334
1335 /*
1336 * We need to have a delay here since the card will not respond while
1337 * in reset causing an MCA on some architectures.
1338 */
1339 udelay(20);
1340 data = qla2x00_debounce_register(&reg->ctrl_status);
1341 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1342 udelay(5);
1343 data = RD_REG_WORD(&reg->ctrl_status);
1344 barrier();
1345 }
1346
1347 if (!cnt)
1348 goto chip_diag_failed;
1349
7c3df132
SK		 1350 ql_dbg(ql_dbg_init, vha, 0x007c,
1351 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1352
1353 /* Reset RISC processor. */
1354 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1355 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1356
1357 /* Workaround for QLA2312 PCI parity error */
1358 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1359 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1360 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1361 udelay(5);
1362 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1363 barrier();
1da177e4
LT		 1364 }
1365 } else
1366 udelay(10);
1367
1368 if (!cnt)
1369 goto chip_diag_failed;
1370
1371 /* Check product ID of chip */
7c3df132 1372 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1373
1374 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1375 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1376 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1377 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1378 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1379 mb[3] != PROD_ID_3) {
7c3df132
SK		 1380 ql_log(ql_log_warn, vha, 0x0062,
1381 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1382 mb[1], mb[2], mb[3]);
1da177e4
LT		 1383
1384 goto chip_diag_failed;
1385 }
1386 ha->product_id[0] = mb[1];
1387 ha->product_id[1] = mb[2];
1388 ha->product_id[2] = mb[3];
1389 ha->product_id[3] = mb[4];
1390
1391 /* Adjust fw RISC transfer size */
73208dfd 1392 if (req->length > 1024)
1da177e4
LT		 1393 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1394 else
1395 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1396 req->length;
1da177e4
LT		 1397
1398 if (IS_QLA2200(ha) &&
1399 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1400 /* Limit firmware transfer size with a 2200A */
7c3df132 1401 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1402
ea5b6382 1403 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1404 ha->fw_transfer_size = 128;
1405 }
1406
1407 /* Wrap Incoming Mailboxes Test. */
1408 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1409
7c3df132 1410 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1411 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1412 if (rval)
1413 ql_log(ql_log_warn, vha, 0x0080,
1414 "Failed mailbox send register test.\n");
1415 else
1da177e4
LT		 1416 /* Flag a successful rval */
1417 rval = QLA_SUCCESS;
1da177e4
LT		 1418 spin_lock_irqsave(&ha->hardware_lock, flags);
1419
1420chip_diag_failed:
1421 if (rval)
7c3df132
SK		 1422 ql_log(ql_log_info, vha, 0x0081,
1423 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1424
1425 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1426
1427 return (rval);
1428}
1429
0107109e
AV		 1430/**
1431 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1432 * @ha: HA context
1433 *
1434 * Returns 0 on success.
1435 */
1436int
e315cd28 1437qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1438{
1439 int rval;
e315cd28 1440 struct qla_hw_data *ha = vha->hw;
73208dfd 1441 struct req_que *req = ha->req_q_map[0];
0107109e 1442
7ec0effd 1443 if (IS_P3P_TYPE(ha))
a9083016
GM		 1444 return QLA_SUCCESS;
1445
73208dfd 1446 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1447
e315cd28 1448 rval = qla2x00_mbx_reg_test(vha);
0107109e 1449 if (rval) {
7c3df132
SK		 1450 ql_log(ql_log_warn, vha, 0x0082,
1451 "Failed mailbox send register test.\n");
0107109e
AV		 1452 } else {
1453 /* Flag a successful rval */
1454 rval = QLA_SUCCESS;
1455 }
1456
1457 return rval;
1458}
1459
a7a167bf 1460void
e315cd28 1461qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1462{
a7a167bf
AV		 1463 int rval;
1464 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1465 eft_size, fce_size, mq_size;
df613b96
AV		 1466 dma_addr_t tc_dma;
1467 void *tc;
e315cd28 1468 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1469 struct req_que *req = ha->req_q_map[0];
1470 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1471
1472 if (ha->fw_dump) {
7c3df132
SK		 1473 ql_dbg(ql_dbg_init, vha, 0x00bd,
1474 "Firmware dump already allocated.\n");
a7a167bf
AV		 1475 return;
1476 }
d4e3e04d 1477
0107109e 1478 ha->fw_dumped = 0;
61f098dd 1479 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 1480 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1481 req_q_size = rsp_q_size = 0;
1482
1483 if (IS_QLA27XX(ha))
1484 goto try_fce;
1485
d4e3e04d 1486 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1487 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1488 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1489 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1490 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1491 sizeof(uint16_t);
e428924c 1492 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1493 if (IS_QLA83XX(ha))
1494 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1495 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1496 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1497 else if (IS_QLA25XX(ha))
1498 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1499 else
1500 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1501
a7a167bf
AV		 1502 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1503 sizeof(uint32_t);
050c9bb1 1504 if (ha->mqenable) {
6246b8a1
GM		 1505 if (!IS_QLA83XX(ha))
1506 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1507 /*
1508 * Allocate maximum buffer size for all queues.
1509 * Resizing must be done at end-of-dump processing.
1510 */
1511 mq_size += ha->max_req_queues *
1512 (req->length * sizeof(request_t));
1513 mq_size += ha->max_rsp_queues *
1514 (rsp->length * sizeof(response_t));
1515 }
00876ae8 1516 if (ha->tgt.atio_ring)
2d70c103 1517 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1518 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1519 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1520 !IS_QLA27XX(ha))
436a7b11 1521 goto try_eft;
df613b96 1522
f73cb695
CD		 1523try_fce:
1524 if (ha->fce)
1525 dma_free_coherent(&ha->pdev->dev,
1526 FCE_SIZE, ha->fce, ha->fce_dma);
1527
1528 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 1529 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1530 GFP_KERNEL);
df613b96 1531 if (!tc) {
7c3df132
SK		 1532 ql_log(ql_log_warn, vha, 0x00be,
1533 "Unable to allocate (%d KB) for FCE.\n",
1534 FCE_SIZE / 1024);
17d98630 1535 goto try_eft;
df613b96
AV		 1536 }
1537
e315cd28 1538 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1539 ha->fce_mb, &ha->fce_bufs);
1540 if (rval) {
7c3df132
SK		 1541 ql_log(ql_log_warn, vha, 0x00bf,
1542 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1543 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1544 tc_dma);
1545 ha->flags.fce_enabled = 0;
17d98630 1546 goto try_eft;
df613b96 1547 }
cfb0919c 1548 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1549 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1550
7d9dade3 1551 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1552 ha->flags.fce_enabled = 1;
1553 ha->fce_dma = tc_dma;
1554 ha->fce = tc;
f73cb695 1555
436a7b11 1556try_eft:
f73cb695
CD		 1557 if (ha->eft)
1558 dma_free_coherent(&ha->pdev->dev,
1559 EFT_SIZE, ha->eft, ha->eft_dma);
1560
436a7b11 1561 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 1562 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1563 GFP_KERNEL);
436a7b11 1564 if (!tc) {
7c3df132
SK		 1565 ql_log(ql_log_warn, vha, 0x00c1,
1566 "Unable to allocate (%d KB) for EFT.\n",
1567 EFT_SIZE / 1024);
436a7b11
AV		 1568 goto cont_alloc;
1569 }
1570
e315cd28 1571 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1572 if (rval) {
7c3df132
SK		 1573 ql_log(ql_log_warn, vha, 0x00c2,
1574 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1575 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1576 tc_dma);
1577 goto cont_alloc;
1578 }
cfb0919c 1579 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1580 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1581
1582 eft_size = EFT_SIZE;
1583 ha->eft_dma = tc_dma;
1584 ha->eft = tc;
d4e3e04d 1585 }
f73cb695 1586
a7a167bf 1587cont_alloc:
f73cb695
CD		 1588 if (IS_QLA27XX(ha)) {
1589 if (!ha->fw_dump_template) {
1590 ql_log(ql_log_warn, vha, 0x00ba,
1591 "Failed missing fwdump template\n");
1592 return;
1593 }
1594 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1595 ql_dbg(ql_dbg_init, vha, 0x00fa,
1596 "-> allocating fwdump (%x bytes)...\n", dump_size);
1597 goto allocate;
1598 }
1599
73208dfd
AC		 1600 req_q_size = req->length * sizeof(request_t);
1601 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1602 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1603 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1604 ha->chain_offset = dump_size;
1605 dump_size += mq_size + fce_size;
d4e3e04d 1606
f73cb695 1607allocate:
d4e3e04d 1608 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1609 if (!ha->fw_dump) {
7c3df132
SK		 1610 ql_log(ql_log_warn, vha, 0x00c4,
1611 "Unable to allocate (%d KB) for firmware dump.\n",
1612 dump_size / 1024);
a7a167bf 1613
e30d1756
MI		 1614 if (ha->fce) {
1615 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1616 ha->fce_dma);
1617 ha->fce = NULL;
1618 ha->fce_dma = 0;
1619 }
1620
a7a167bf
AV		 1621 if (ha->eft) {
1622 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1623 ha->eft_dma);
1624 ha->eft = NULL;
1625 ha->eft_dma = 0;
1626 }
1627 return;
1628 }
f73cb695 1629 ha->fw_dump_len = dump_size;
cfb0919c 1630 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1631 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1632
f73cb695
CD		 1633 if (IS_QLA27XX(ha))
1634 return;
1635
a7a167bf
AV		 1636 ha->fw_dump->signature[0] = 'Q';
1637 ha->fw_dump->signature[1] = 'L';
1638 ha->fw_dump->signature[2] = 'G';
1639 ha->fw_dump->signature[3] = 'C';
1640 ha->fw_dump->version = __constant_htonl(1);
1641
1642 ha->fw_dump->fixed_size = htonl(fixed_size);
1643 ha->fw_dump->mem_size = htonl(mem_size);
1644 ha->fw_dump->req_q_size = htonl(req_q_size);
1645 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1646
1647 ha->fw_dump->eft_size = htonl(eft_size);
1648 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1649 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1650
1651 ha->fw_dump->header_size =
1652 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1653}
1654
18e7555a
AV		 1655static int
1656qla81xx_mpi_sync(scsi_qla_host_t *vha)
1657{
1658#define MPS_MASK 0xe0
1659 int rval;
1660 uint16_t dc;
1661 uint32_t dw;
18e7555a
AV		 1662
1663 if (!IS_QLA81XX(vha->hw))
1664 return QLA_SUCCESS;
1665
1666 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1667 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1668 ql_log(ql_log_warn, vha, 0x0105,
1669 "Unable to acquire semaphore.\n");
18e7555a
AV		 1670 goto done;
1671 }
1672
1673 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1674 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1675 if (rval != QLA_SUCCESS) {
7c3df132 1676 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1677 goto done_release;
1678 }
1679
1680 dc &= MPS_MASK;
1681 if (dc == (dw & MPS_MASK))
1682 goto done_release;
1683
1684 dw &= ~MPS_MASK;
1685 dw |= dc;
1686 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1687 if (rval != QLA_SUCCESS) {
7c3df132 1688 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1689 }
1690
1691done_release:
1692 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1693 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1694 ql_log(ql_log_warn, vha, 0x006d,
1695 "Unable to release semaphore.\n");
18e7555a
AV		 1696 }
1697
1698done:
1699 return rval;
1700}
1701
8d93f550
CD		 1702int
1703qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1704{
1705 /* Don't try to reallocate the array */
1706 if (req->outstanding_cmds)
1707 return QLA_SUCCESS;
1708
1709 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1710 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1711 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1712 else {
1713 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1714 req->num_outstanding_cmds = ha->fw_xcb_count;
1715 else
1716 req->num_outstanding_cmds = ha->fw_iocb_count;
1717 }
1718
1719 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1720 req->num_outstanding_cmds, GFP_KERNEL);
1721
1722 if (!req->outstanding_cmds) {
1723 /*
1724 * Try to allocate a minimal size just so we can get through
1725 * initialization.
1726 */
1727 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1728 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1729 req->num_outstanding_cmds, GFP_KERNEL);
1730
1731 if (!req->outstanding_cmds) {
1732 ql_log(ql_log_fatal, NULL, 0x0126,
1733 "Failed to allocate memory for "
1734 "outstanding_cmds for req_que %p.\n", req);
1735 req->num_outstanding_cmds = 0;
1736 return QLA_FUNCTION_FAILED;
1737 }
1738 }
1739
1740 return QLA_SUCCESS;
1741}
1742
1da177e4
LT		 1743/**
1744 * qla2x00_setup_chip() - Load and start RISC firmware.
1745 * @ha: HA context
1746 *
1747 * Returns 0 on success.
1748 */
1749static int
e315cd28 1750qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1751{
0107109e
AV		 1752 int rval;
1753 uint32_t srisc_address = 0;
e315cd28 1754 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1755 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1756 unsigned long flags;
dda772e8 1757 uint16_t fw_major_version;
3db0652e 1758
7ec0effd 1759 if (IS_P3P_TYPE(ha)) {
a9083016 1760 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1761 if (rval == QLA_SUCCESS) {
1762 qla2x00_stop_firmware(vha);
a9083016 1763 goto enable_82xx_npiv;
14e303d9 1764 } else
b963752f 1765 goto failed;
a9083016
GM		 1766 }
1767
3db0652e
AV		 1768 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1769 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1770 spin_lock_irqsave(&ha->hardware_lock, flags);
1771 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1772 RD_REG_WORD(&reg->hccr);
1773 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1774 }
1da177e4 1775
18e7555a
AV		 1776 qla81xx_mpi_sync(vha);
1777
1da177e4 1778 /* Load firmware sequences */
e315cd28 1779 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1780 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1781 ql_dbg(ql_dbg_init, vha, 0x00c9,
1782 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1783
e315cd28 1784 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1785 if (rval == QLA_SUCCESS) {
1786 /* Start firmware execution. */
7c3df132
SK		 1787 ql_dbg(ql_dbg_init, vha, 0x00ca,
1788 "Starting firmware.\n");
1da177e4 1789
e315cd28 1790 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1791 /* Retrieve firmware information. */
dda772e8 1792 if (rval == QLA_SUCCESS) {
a9083016 1793enable_82xx_npiv:
dda772e8 1794 fw_major_version = ha->fw_major_version;
7ec0effd 1795 if (IS_P3P_TYPE(ha))
3173167f 1796 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1797 else
1798 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1799 if (rval != QLA_SUCCESS)
1800 goto failed;
2c3dfe3f 1801 ha->flags.npiv_supported = 0;
e315cd28 1802 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1803 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1804 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1805 if ((!ha->max_npiv_vports) ||
1806 ((ha->max_npiv_vports + 1) %
eb66dc60 1807 MIN_MULTI_ID_FABRIC))
4d0ea247 1808 ha->max_npiv_vports =
eb66dc60 1809 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1810 }
24a08138 1811 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1812 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1813 &ha->max_npiv_vports, NULL);
d743de66 1814
8d93f550
CD		 1815 /*
1816 * Allocate the array of outstanding commands
1817 * now that we know the firmware resources.
1818 */
1819 rval = qla2x00_alloc_outstanding_cmds(ha,
1820 vha->req);
1821 if (rval != QLA_SUCCESS)
1822 goto failed;
1823
be5ea3cf 1824 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1825 && !(IS_P3P_TYPE(ha)))
08de2844 1826 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1827 } else {
1828 goto failed;
1da177e4
LT		 1829 }
1830 } else {
7c3df132
SK		 1831 ql_log(ql_log_fatal, vha, 0x00cd,
1832 "ISP Firmware failed checksum.\n");
1833 goto failed;
1da177e4 1834 }
c74d88a4
AV		 1835 } else
1836 goto failed;
1da177e4 1837
3db0652e
AV		 1838 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1839 /* Enable proper parity. */
1840 spin_lock_irqsave(&ha->hardware_lock, flags);
1841 if (IS_QLA2300(ha))
1842 /* SRAM parity */
1843 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1844 else
1845 /* SRAM, Instruction RAM and GP RAM parity */
1846 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1847 RD_REG_WORD(&reg->hccr);
1848 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1849 }
1850
f3982d89
CD		 1851 if (IS_QLA27XX(ha))
1852 ha->flags.fac_supported = 1;
1853 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 1854 uint32_t size;
1855
1856 rval = qla81xx_fac_get_sector_size(vha, &size);
1857 if (rval == QLA_SUCCESS) {
1858 ha->flags.fac_supported = 1;
1859 ha->fdt_block_size = size << 2;
1860 } else {
7c3df132 1861 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1862 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1863 ha->fw_major_version, ha->fw_minor_version,
1864 ha->fw_subminor_version);
1ca60e3b 1865
f73cb695 1866 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1867 ha->flags.fac_supported = 0;
1868 rval = QLA_SUCCESS;
1869 }
1d2874de
JC		 1870 }
1871 }
ca9e9c3e 1872failed:
1da177e4 1873 if (rval) {
7c3df132
SK		 1874 ql_log(ql_log_fatal, vha, 0x00cf,
1875 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1876 }
1877
1878 return (rval);
1879}
1880
1881/**
1882 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1883 * @ha: HA context
1884 *
1885 * Beginning of request ring has initialization control block already built
1886 * by nvram config routine.
1887 *
1888 * Returns 0 on success.
1889 */
73208dfd
AC		 1890void
1891qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1892{
1893 uint16_t cnt;
1894 response_t *pkt;
1895
2afa19a9
AC		 1896 rsp->ring_ptr = rsp->ring;
1897 rsp->ring_index = 0;
1898 rsp->status_srb = NULL;
e315cd28
AC		 1899 pkt = rsp->ring_ptr;
1900 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1901 pkt->signature = RESPONSE_PROCESSED;
1902 pkt++;
1903 }
1da177e4
LT		 1904}
1905
1906/**
1907 * qla2x00_update_fw_options() - Read and process firmware options.
1908 * @ha: HA context
1909 *
1910 * Returns 0 on success.
1911 */
abbd8870 1912void
e315cd28 1913qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1914{
1915 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1916 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1917
1918 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1919 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1920
1921 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1922 return;
1923
1924 /* Serial Link options. */
7c3df132
SK		 1925 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1926 "Serial link options.\n");
1927 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1928 (uint8_t *)&ha->fw_seriallink_options,
1929 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1930
1931 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1932 if (ha->fw_seriallink_options[3] & BIT_2) {
1933 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1934
1935 /* 1G settings */
1936 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1937 emphasis = (ha->fw_seriallink_options[2] &
1938 (BIT_4 | BIT_3)) >> 3;
1939 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1940 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1941 rx_sens = (ha->fw_seriallink_options[0] &
1942 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1943 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1944 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1945 if (rx_sens == 0x0)
1946 rx_sens = 0x3;
1947 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1948 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1949 ha->fw_options[10] |= BIT_5 |
1950 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1951 (tx_sens & (BIT_1 | BIT_0));
1952
1953 /* 2G settings */
1954 swing = (ha->fw_seriallink_options[2] &
1955 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1956 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1957 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1958 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1959 rx_sens = (ha->fw_seriallink_options[1] &
1960 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1961 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1962 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1963 if (rx_sens == 0x0)
1964 rx_sens = 0x3;
1965 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1966 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1967 ha->fw_options[11] |= BIT_5 |
1968 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1969 (tx_sens & (BIT_1 | BIT_0));
1970 }
1971
1972 /* FCP2 options. */
1973 /* Return command IOCBs without waiting for an ABTS to complete. */
1974 ha->fw_options[3] |= BIT_13;
1975
1976 /* LED scheme. */
1977 if (ha->flags.enable_led_scheme)
1978 ha->fw_options[2] |= BIT_12;
1979
48c02fde 1980 /* Detect ISP6312. */
1981 if (IS_QLA6312(ha))
1982 ha->fw_options[2] |= BIT_13;
1983
1da177e4 1984 /* Update firmware options. */
e315cd28 1985 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1986}
1987
0107109e 1988void
e315cd28 1989qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1990{
1991 int rval;
e315cd28 1992 struct qla_hw_data *ha = vha->hw;
0107109e 1993
7ec0effd 1994 if (IS_P3P_TYPE(ha))
a9083016
GM		 1995 return;
1996
0107109e 1997 /* Update Serial Link options. */
f94097ed 1998 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1999 return;
2000
e315cd28 2001 rval = qla2x00_set_serdes_params(vha,
f94097ed 2002 le16_to_cpu(ha->fw_seriallink_options24[1]),
2003 le16_to_cpu(ha->fw_seriallink_options24[2]),
2004 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2005 if (rval != QLA_SUCCESS) {
7c3df132 2006 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2007 "Unable to update Serial Link options (%x).\n", rval);
2008 }
2009}
2010
abbd8870 2011void
e315cd28 2012qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2013{
e315cd28 2014 struct qla_hw_data *ha = vha->hw;
3d71644c 2015 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2016 struct req_que *req = ha->req_q_map[0];
2017 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2018
2019 /* Setup ring parameters in initialization control block. */
2020 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
2021 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2022 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2023 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2024 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2025 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2026 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2027 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2028
2029 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2030 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2031 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2032 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2033 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
2034}
2035
0107109e 2036void
e315cd28 2037qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 2038{
e315cd28 2039 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2040 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
2041 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2042 struct qla_msix_entry *msix;
0107109e 2043 struct init_cb_24xx *icb;
73208dfd
AC		 2044 uint16_t rid = 0;
2045 struct req_que *req = ha->req_q_map[0];
2046 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 2047
6246b8a1 2048 /* Setup ring parameters in initialization control block. */
0107109e
AV		 2049 icb = (struct init_cb_24xx *)ha->init_cb;
2050 icb->request_q_outpointer = __constant_cpu_to_le16(0);
2051 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2052 icb->request_q_length = cpu_to_le16(req->length);
2053 icb->response_q_length = cpu_to_le16(rsp->length);
2054 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2055 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2056 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2057 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 2058
2d70c103
NB		 2059 /* Setup ATIO queue dma pointers for target mode */
2060 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
2061 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2062 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2063 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2064
7c6300e3
JC		 2065 if (IS_SHADOW_REG_CAPABLE(ha))
2066 icb->firmware_options_2 |=
2067 __constant_cpu_to_le32(BIT_30|BIT_29);
2068
f73cb695 2069 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
73208dfd
AC		 2070 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2071 icb->rid = __constant_cpu_to_le16(rid);
2072 if (ha->flags.msix_enabled) {
2073 msix = &ha->msix_entries[1];
7c3df132
SK		 2074 ql_dbg(ql_dbg_init, vha, 0x00fd,
2075 "Registering vector 0x%x for base que.\n",
2076 msix->entry);
73208dfd
AC		 2077 icb->msix = cpu_to_le16(msix->entry);
2078 }
2079 /* Use alternate PCI bus number */
2080 if (MSB(rid))
2081 icb->firmware_options_2 |=
2082 __constant_cpu_to_le32(BIT_19);
2083 /* Use alternate PCI devfn */
2084 if (LSB(rid))
2085 icb->firmware_options_2 |=
2086 __constant_cpu_to_le32(BIT_18);
2087
3155754a 2088 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 2089 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2090 (ha->flags.msix_enabled)) {
3155754a
AC		 2091 icb->firmware_options_2 &=
2092 __constant_cpu_to_le32(~BIT_22);
2093 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 2094 ql_dbg(ql_dbg_init, vha, 0x00fe,
2095 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 2096 } else {
2097 icb->firmware_options_2 |=
2098 __constant_cpu_to_le32(BIT_22);
2099 }
73208dfd 2100 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 2101
2102 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2103 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2104 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2105 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2106 } else {
2107 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2108 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2109 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2110 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2111 }
aa230bc5 2112 qlt_24xx_config_rings(vha);
2d70c103 2113
73208dfd
AC		 2114 /* PCI posting */
2115 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2116}
2117
1da177e4
LT		 2118/**
2119 * qla2x00_init_rings() - Initializes firmware.
2120 * @ha: HA context
2121 *
2122 * Beginning of request ring has initialization control block already built
2123 * by nvram config routine.
2124 *
2125 * Returns 0 on success.
2126 */
8ae6d9c7 2127int
e315cd28 2128qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2129{
2130 int rval;
2131 unsigned long flags = 0;
29bdccbe 2132 int cnt, que;
e315cd28 2133 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2134 struct req_que *req;
2135 struct rsp_que *rsp;
2c3dfe3f
SJ		 2136 struct mid_init_cb_24xx *mid_init_cb =
2137 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2138
2139 spin_lock_irqsave(&ha->hardware_lock, flags);
2140
2141 /* Clear outstanding commands array. */
2afa19a9 2142 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2143 req = ha->req_q_map[que];
2144 if (!req)
2145 continue;
7c6300e3
JC		 2146 req->out_ptr = (void *)(req->ring + req->length);
2147 *req->out_ptr = 0;
8d93f550 2148 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2149 req->outstanding_cmds[cnt] = NULL;
1da177e4 2150
2afa19a9 2151 req->current_outstanding_cmd = 1;
1da177e4 2152
29bdccbe
AC		 2153 /* Initialize firmware. */
2154 req->ring_ptr = req->ring;
2155 req->ring_index = 0;
2156 req->cnt = req->length;
2157 }
1da177e4 2158
2afa19a9 2159 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2160 rsp = ha->rsp_q_map[que];
2161 if (!rsp)
2162 continue;
7c6300e3
JC		 2163 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
2164 *rsp->in_ptr = 0;
29bdccbe 2165 /* Initialize response queue entries */
8ae6d9c7
GM		 2166 if (IS_QLAFX00(ha))
2167 qlafx00_init_response_q_entries(rsp);
2168 else
2169 qla2x00_init_response_q_entries(rsp);
29bdccbe 2170 }
1da177e4 2171
2d70c103
NB		 2172 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2173 ha->tgt.atio_ring_index = 0;
2174 /* Initialize ATIO queue entries */
2175 qlt_init_atio_q_entries(vha);
2176
e315cd28 2177 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2178
2179 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2180
8ae6d9c7
GM		 2181 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2182
2183 if (IS_QLAFX00(ha)) {
2184 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2185 goto next_check;
2186 }
2187
1da177e4 2188 /* Update any ISP specific firmware options before initialization. */
e315cd28 2189 ha->isp_ops->update_fw_options(vha);
1da177e4 2190
605aa2bc 2191 if (ha->flags.npiv_supported) {
45980cc2 2192 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2193 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2194 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2195 }
2196
24a08138
AV		 2197 if (IS_FWI2_CAPABLE(ha)) {
2198 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2199 mid_init_cb->init_cb.execution_throttle =
2200 cpu_to_le16(ha->fw_xcb_count);
25232cc9
HM		 2201 /* D-Port Status */
2202 if (IS_DPORT_CAPABLE(ha))
2203 mid_init_cb->init_cb.firmware_options_1 |=
2204 cpu_to_le16(BIT_7);
2486c627
HM		 2205 /* Enable FA-WWPN */
2206 ha->flags.fawwpn_enabled =
2207 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) ? 1 : 0;
2208 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n",
2209 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 2210 }
2c3dfe3f 2211
e315cd28 2212 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2213next_check:
1da177e4 2214 if (rval) {
7c3df132
SK		 2215 ql_log(ql_log_fatal, vha, 0x00d2,
2216 "Init Firmware **** FAILED ****.\n");
1da177e4 2217 } else {
7c3df132
SK		 2218 ql_dbg(ql_dbg_init, vha, 0x00d3,
2219 "Init Firmware -- success.\n");
1da177e4
LT		 2220 }
2221
2222 return (rval);
2223}
2224
2225/**
2226 * qla2x00_fw_ready() - Waits for firmware ready.
2227 * @ha: HA context
2228 *
2229 * Returns 0 on success.
2230 */
2231static int
e315cd28 2232qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2233{
2234 int rval;
4d4df193 2235 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2236 uint16_t min_wait; /* Minimum wait time if loop is down */
2237 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 2238 uint16_t state[6];
e315cd28 2239 struct qla_hw_data *ha = vha->hw;
1da177e4 2240
8ae6d9c7
GM		 2241 if (IS_QLAFX00(vha->hw))
2242 return qlafx00_fw_ready(vha);
2243
1da177e4
LT		 2244 rval = QLA_SUCCESS;
2245
33461491
CD		 2246 /* Time to wait for loop down */
2247 if (IS_P3P_TYPE(ha))
2248 min_wait = 30;
2249 else
2250 min_wait = 20;
1da177e4
LT		 2251
2252 /*
2253 * Firmware should take at most one RATOV to login, plus 5 seconds for
2254 * our own processing.
2255 */
2256 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2257 wait_time = min_wait;
2258 }
2259
2260 /* Min wait time if loop down */
2261 mtime = jiffies + (min_wait * HZ);
2262
2263 /* wait time before firmware ready */
2264 wtime = jiffies + (wait_time * HZ);
2265
2266 /* Wait for ISP to finish LIP */
e315cd28 2267 if (!vha->flags.init_done)
7c3df132
SK		 2268 ql_log(ql_log_info, vha, 0x801e,
2269 "Waiting for LIP to complete.\n");
1da177e4
LT		 2270
2271 do {
5b939038 2272 memset(state, -1, sizeof(state));
e315cd28 2273 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2274 if (rval == QLA_SUCCESS) {
4d4df193 2275 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2276 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2277 }
4d4df193 2278 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2279 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2280 "fw_state=%x 84xx=%x.\n", state[0],
2281 state[2]);
4d4df193
HK		 2282 if ((state[2] & FSTATE_LOGGED_IN) &&
2283 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2284 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2285 "Sending verify iocb.\n");
4d4df193
HK		 2286
2287 cs84xx_time = jiffies;
e315cd28 2288 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2289 if (rval != QLA_SUCCESS) {
2290 ql_log(ql_log_warn,
cfb0919c 2291 vha, 0x8007,
7c3df132 2292 "Init chip failed.\n");
4d4df193 2293 break;
7c3df132 2294 }
4d4df193
HK		 2295
2296 /* Add time taken to initialize. */
2297 cs84xx_time = jiffies - cs84xx_time;
2298 wtime += cs84xx_time;
2299 mtime += cs84xx_time;
cfb0919c 2300 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2301 "Increasing wait time by %ld. "
2302 "New time %ld.\n", cs84xx_time,
2303 wtime);
4d4df193
HK		 2304 }
2305 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2306 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2307 "F/W Ready - OK.\n");
1da177e4 2308
e315cd28 2309 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2310 &ha->login_timeout, &ha->r_a_tov);
2311
2312 rval = QLA_SUCCESS;
2313 break;
2314 }
2315
2316 rval = QLA_FUNCTION_FAILED;
2317
e315cd28 2318 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2319 state[0] != FSTATE_READY) {
1da177e4 2320 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2321 * other than Wait for Login.
2322 */
1da177e4 2323 if (time_after_eq(jiffies, mtime)) {
7c3df132 2324 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2325 "Cable is unplugged...\n");
2326
e315cd28 2327 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2328 break;
2329 }
2330 }
2331 } else {
2332 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2333 if (time_after_eq(jiffies, mtime) ||
7190575f 2334 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2335 break;
2336 }
2337
2338 if (time_after_eq(jiffies, wtime))
2339 break;
2340
2341 /* Delay for a while */
2342 msleep(500);
1da177e4
LT		 2343 } while (1);
2344
7c3df132 2345 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 2346 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
2347 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 2348
cfb0919c 2349 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2350 ql_log(ql_log_warn, vha, 0x803b,
2351 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2352 }
2353
2354 return (rval);
2355}
2356
2357/*
2358* qla2x00_configure_hba
2359* Setup adapter context.
2360*
2361* Input:
2362* ha = adapter state pointer.
2363*
2364* Returns:
2365* 0 = success
2366*
2367* Context:
2368* Kernel context.
2369*/
2370static int
e315cd28 2371qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2372{
2373 int rval;
2374 uint16_t loop_id;
2375 uint16_t topo;
2c3dfe3f 2376 uint16_t sw_cap;
1da177e4
LT		 2377 uint8_t al_pa;
2378 uint8_t area;
2379 uint8_t domain;
2380 char connect_type[22];
e315cd28 2381 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2382 unsigned long flags;
61e1b269 2383 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2384
2385 /* Get host addresses. */
e315cd28 2386 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2387 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2388 if (rval != QLA_SUCCESS) {
e315cd28 2389 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2390 IS_CNA_CAPABLE(ha) ||
33135aa2 2391 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2392 ql_dbg(ql_dbg_disc, vha, 0x2008,
2393 "Loop is in a transition state.\n");
33135aa2 2394 } else {
7c3df132
SK		 2395 ql_log(ql_log_warn, vha, 0x2009,
2396 "Unable to get host loop ID.\n");
61e1b269
JC		 2397 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2398 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2399 ql_log(ql_log_warn, vha, 0x1151,
2400 "Doing link init.\n");
2401 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2402 return rval;
2403 }
e315cd28 2404 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2405 }
1da177e4
LT		 2406 return (rval);
2407 }
2408
2409 if (topo == 4) {
7c3df132
SK		 2410 ql_log(ql_log_info, vha, 0x200a,
2411 "Cannot get topology - retrying.\n");
1da177e4
LT		 2412 return (QLA_FUNCTION_FAILED);
2413 }
2414
e315cd28 2415 vha->loop_id = loop_id;
1da177e4
LT		 2416
2417 /* initialize */
2418 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2419 ha->operating_mode = LOOP;
2c3dfe3f 2420 ha->switch_cap = 0;
1da177e4
LT		 2421
2422 switch (topo) {
2423 case 0:
7c3df132 2424 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2425 ha->current_topology = ISP_CFG_NL;
2426 strcpy(connect_type, "(Loop)");
2427 break;
2428
2429 case 1:
7c3df132 2430 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2431 ha->switch_cap = sw_cap;
1da177e4
LT		 2432 ha->current_topology = ISP_CFG_FL;
2433 strcpy(connect_type, "(FL_Port)");
2434 break;
2435
2436 case 2:
7c3df132 2437 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2438 ha->operating_mode = P2P;
2439 ha->current_topology = ISP_CFG_N;
2440 strcpy(connect_type, "(N_Port-to-N_Port)");
2441 break;
2442
2443 case 3:
7c3df132 2444 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2445 ha->switch_cap = sw_cap;
1da177e4
LT		 2446 ha->operating_mode = P2P;
2447 ha->current_topology = ISP_CFG_F;
2448 strcpy(connect_type, "(F_Port)");
2449 break;
2450
2451 default:
7c3df132
SK		 2452 ql_dbg(ql_dbg_disc, vha, 0x200f,
2453 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2454 ha->current_topology = ISP_CFG_NL;
2455 strcpy(connect_type, "(Loop)");
2456 break;
2457 }
2458
2459 /* Save Host port and loop ID. */
2460 /* byte order - Big Endian */
e315cd28
AC		 2461 vha->d_id.b.domain = domain;
2462 vha->d_id.b.area = area;
2463 vha->d_id.b.al_pa = al_pa;
1da177e4 2464
f24b5cb8 2465 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2466 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2467 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2468
e315cd28 2469 if (!vha->flags.init_done)
7c3df132
SK		 2470 ql_log(ql_log_info, vha, 0x2010,
2471 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2472 connect_type, vha->loop_id);
1da177e4 2473
1da177e4
LT		 2474 return(rval);
2475}
2476
a9083016 2477inline void
e315cd28
AC		 2478qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2479 char *def)
9bb9fcf2
AV		 2480{
2481 char *st, *en;
2482 uint16_t index;
e315cd28 2483 struct qla_hw_data *ha = vha->hw;
ab671149 2484 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2485 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2486
2487 if (memcmp(model, BINZERO, len) != 0) {
2488 strncpy(ha->model_number, model, len);
2489 st = en = ha->model_number;
2490 en += len - 1;
2491 while (en > st) {
2492 if (*en != 0x20 && *en != 0x00)
2493 break;
2494 *en-- = '\0';
2495 }
2496
2497 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2498 if (use_tbl &&
2499 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2500 index < QLA_MODEL_NAMES)
1ee27146
JC		 2501 strncpy(ha->model_desc,
2502 qla2x00_model_name[index * 2 + 1],
2503 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2504 } else {
2505 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2506 if (use_tbl &&
2507 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2508 index < QLA_MODEL_NAMES) {
2509 strcpy(ha->model_number,
2510 qla2x00_model_name[index * 2]);
1ee27146
JC		 2511 strncpy(ha->model_desc,
2512 qla2x00_model_name[index * 2 + 1],
2513 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2514 } else {
2515 strcpy(ha->model_number, def);
2516 }
2517 }
1ee27146 2518 if (IS_FWI2_CAPABLE(ha))
e315cd28 2519 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2520 sizeof(ha->model_desc));
9bb9fcf2
AV		 2521}
2522
4e08df3f
DM		 2523/* On sparc systems, obtain port and node WWN from firmware
2524 * properties.
2525 */
e315cd28 2526static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2527{
2528#ifdef CONFIG_SPARC
e315cd28 2529 struct qla_hw_data *ha = vha->hw;
4e08df3f 2530 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2531 struct device_node *dp = pci_device_to_OF_node(pdev);
2532 const u8 *val;
4e08df3f
DM		 2533 int len;
2534
2535 val = of_get_property(dp, "port-wwn", &len);
2536 if (val && len >= WWN_SIZE)
2537 memcpy(nv->port_name, val, WWN_SIZE);
2538
2539 val = of_get_property(dp, "node-wwn", &len);
2540 if (val && len >= WWN_SIZE)
2541 memcpy(nv->node_name, val, WWN_SIZE);
2542#endif
2543}
2544
1da177e4
LT		 2545/*
2546* NVRAM configuration for ISP 2xxx
2547*
2548* Input:
2549* ha = adapter block pointer.
2550*
2551* Output:
2552* initialization control block in response_ring
2553* host adapters parameters in host adapter block
2554*
2555* Returns:
2556* 0 = success.
2557*/
abbd8870 2558int
e315cd28 2559qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2560{
4e08df3f 2561 int rval;
0107109e
AV		 2562 uint8_t chksum = 0;
2563 uint16_t cnt;
2564 uint8_t *dptr1, *dptr2;
e315cd28 2565 struct qla_hw_data *ha = vha->hw;
0107109e 2566 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2567 nvram_t *nv = ha->nvram;
2568 uint8_t *ptr = ha->nvram;
3d71644c 2569 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2570
4e08df3f
DM		 2571 rval = QLA_SUCCESS;
2572
1da177e4 2573 /* Determine NVRAM starting address. */
0107109e 2574 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2575 ha->nvram_base = 0;
2576 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2577 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2578 ha->nvram_base = 0x80;
2579
2580 /* Get NVRAM data and calculate checksum. */
e315cd28 2581 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2582 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2583 chksum += *ptr++;
1da177e4 2584
7c3df132
SK		 2585 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2586 "Contents of NVRAM.\n");
2587 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2588 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2589
2590 /* Bad NVRAM data, set defaults parameters. */
2591 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2592 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2593 /* Reset NVRAM data. */
7c3df132 2594 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2595 "Inconsistent NVRAM "
7c3df132
SK		 2596 "detected: checksum=0x%x id=%c version=0x%x.\n",
2597 chksum, nv->id[0], nv->nvram_version);
2598 ql_log(ql_log_warn, vha, 0x0065,
2599 "Falling back to "
2600 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2601
2602 /*
2603 * Set default initialization control block.
2604 */
2605 memset(nv, 0, ha->nvram_size);
2606 nv->parameter_block_version = ICB_VERSION;
2607
2608 if (IS_QLA23XX(ha)) {
2609 nv->firmware_options[0] = BIT_2 | BIT_1;
2610 nv->firmware_options[1] = BIT_7 | BIT_5;
2611 nv->add_firmware_options[0] = BIT_5;
2612 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2613 nv->frame_payload_size = 2048;
4e08df3f
DM		 2614 nv->special_options[1] = BIT_7;
2615 } else if (IS_QLA2200(ha)) {
2616 nv->firmware_options[0] = BIT_2 | BIT_1;
2617 nv->firmware_options[1] = BIT_7 | BIT_5;
2618 nv->add_firmware_options[0] = BIT_5;
2619 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2620 nv->frame_payload_size = 1024;
4e08df3f
DM		 2621 } else if (IS_QLA2100(ha)) {
2622 nv->firmware_options[0] = BIT_3 | BIT_1;
2623 nv->firmware_options[1] = BIT_5;
98aee70d 2624 nv->frame_payload_size = 1024;
4e08df3f
DM		 2625 }
2626
2627 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2628 nv->execution_throttle = __constant_cpu_to_le16(16);
2629 nv->retry_count = 8;
2630 nv->retry_delay = 1;
2631
2632 nv->port_name[0] = 33;
2633 nv->port_name[3] = 224;
2634 nv->port_name[4] = 139;
2635
e315cd28 2636 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2637
2638 nv->login_timeout = 4;
2639
2640 /*
2641 * Set default host adapter parameters
2642 */
2643 nv->host_p[1] = BIT_2;
2644 nv->reset_delay = 5;
2645 nv->port_down_retry_count = 8;
2646 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2647 nv->link_down_timeout = 60;
2648
2649 rval = 1;
1da177e4
LT		 2650 }
2651
2652#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2653 /*
2654 * The SN2 does not provide BIOS emulation which means you can't change
2655 * potentially bogus BIOS settings. Force the use of default settings
2656 * for link rate and frame size. Hope that the rest of the settings
2657 * are valid.
2658 */
2659 if (ia64_platform_is("sn2")) {
98aee70d 2660 nv->frame_payload_size = 2048;
1da177e4
LT		 2661 if (IS_QLA23XX(ha))
2662 nv->special_options[1] = BIT_7;
2663 }
2664#endif
2665
2666 /* Reset Initialization control block */
0107109e 2667 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2668
2669 /*
2670 * Setup driver NVRAM options.
2671 */
2672 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2673 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2674 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2675 nv->firmware_options[1] &= ~BIT_4;
2676
2677 if (IS_QLA23XX(ha)) {
2678 nv->firmware_options[0] |= BIT_2;
2679 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2680 nv->special_options[0] &= ~BIT_6;
0107109e 2681 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2682
2683 if (IS_QLA2300(ha)) {
2684 if (ha->fb_rev == FPM_2310) {
2685 strcpy(ha->model_number, "QLA2310");
2686 } else {
2687 strcpy(ha->model_number, "QLA2300");
2688 }
2689 } else {
e315cd28 2690 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2691 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2692 }
2693 } else if (IS_QLA2200(ha)) {
2694 nv->firmware_options[0] |= BIT_2;
2695 /*
2696 * 'Point-to-point preferred, else loop' is not a safe
2697 * connection mode setting.
2698 */
2699 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2700 (BIT_5 | BIT_4)) {
2701 /* Force 'loop preferred, else point-to-point'. */
2702 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2703 nv->add_firmware_options[0] |= BIT_5;
2704 }
2705 strcpy(ha->model_number, "QLA22xx");
2706 } else /*if (IS_QLA2100(ha))*/ {
2707 strcpy(ha->model_number, "QLA2100");
2708 }
2709
2710 /*
2711 * Copy over NVRAM RISC parameter block to initialization control block.
2712 */
2713 dptr1 = (uint8_t *)icb;
2714 dptr2 = (uint8_t *)&nv->parameter_block_version;
2715 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2716 while (cnt--)
2717 *dptr1++ = *dptr2++;
2718
2719 /* Copy 2nd half. */
2720 dptr1 = (uint8_t *)icb->add_firmware_options;
2721 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2722 while (cnt--)
2723 *dptr1++ = *dptr2++;
2724
5341e868
AV		 2725 /* Use alternate WWN? */
2726 if (nv->host_p[1] & BIT_7) {
2727 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2728 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2729 }
2730
1da177e4
LT		 2731 /* Prepare nodename */
2732 if ((icb->firmware_options[1] & BIT_6) == 0) {
2733 /*
2734 * Firmware will apply the following mask if the nodename was
2735 * not provided.
2736 */
2737 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2738 icb->node_name[0] &= 0xF0;
2739 }
2740
2741 /*
2742 * Set host adapter parameters.
2743 */
3ce8866c
SK		 2744
2745 /*
2746 * BIT_7 in the host-parameters section allows for modification to
2747 * internal driver logging.
2748 */
0181944f 2749 if (nv->host_p[0] & BIT_7)
cfb0919c 2750 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2751 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2752 /* Always load RISC code on non ISP2[12]00 chips. */
2753 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2754 ha->flags.disable_risc_code_load = 0;
2755 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2756 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2757 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2758 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2759 ha->flags.disable_serdes = 0;
1da177e4
LT		 2760
2761 ha->operating_mode =
2762 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2763
2764 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2765 sizeof(ha->fw_seriallink_options));
2766
2767 /* save HBA serial number */
2768 ha->serial0 = icb->port_name[5];
2769 ha->serial1 = icb->port_name[6];
2770 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2771 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2772 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2773
2774 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2775
2776 ha->retry_count = nv->retry_count;
2777
2778 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2779 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2780 nv->login_timeout = ql2xlogintimeout;
2781 if (nv->login_timeout < 4)
2782 nv->login_timeout = 4;
2783 ha->login_timeout = nv->login_timeout;
2784 icb->login_timeout = nv->login_timeout;
2785
00a537b8
AV		 2786 /* Set minimum RATOV to 100 tenths of a second. */
2787 ha->r_a_tov = 100;
1da177e4 2788
1da177e4
LT		 2789 ha->loop_reset_delay = nv->reset_delay;
2790
1da177e4
LT		 2791 /* Link Down Timeout = 0:
2792 *
2793 * When Port Down timer expires we will start returning
2794 * I/O's to OS with "DID_NO_CONNECT".
2795 *
2796 * Link Down Timeout != 0:
2797 *
2798 * The driver waits for the link to come up after link down
2799 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2800 */
1da177e4
LT		 2801 if (nv->link_down_timeout == 0) {
2802 ha->loop_down_abort_time =
354d6b21 2803 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2804 } else {
2805 ha->link_down_timeout = nv->link_down_timeout;
2806 ha->loop_down_abort_time =
2807 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2808 }
1da177e4 2809
1da177e4
LT		 2810 /*
2811 * Need enough time to try and get the port back.
2812 */
2813 ha->port_down_retry_count = nv->port_down_retry_count;
2814 if (qlport_down_retry)
2815 ha->port_down_retry_count = qlport_down_retry;
2816 /* Set login_retry_count */
2817 ha->login_retry_count = nv->retry_count;
2818 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2819 ha->port_down_retry_count > 3)
2820 ha->login_retry_count = ha->port_down_retry_count;
2821 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2822 ha->login_retry_count = ha->port_down_retry_count;
2823 if (ql2xloginretrycount)
2824 ha->login_retry_count = ql2xloginretrycount;
2825
1da177e4
LT		 2826 icb->lun_enables = __constant_cpu_to_le16(0);
2827 icb->command_resource_count = 0;
2828 icb->immediate_notify_resource_count = 0;
2829 icb->timeout = __constant_cpu_to_le16(0);
2830
2831 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2832 /* Enable RIO */
2833 icb->firmware_options[0] &= ~BIT_3;
2834 icb->add_firmware_options[0] &=
2835 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2836 icb->add_firmware_options[0] |= BIT_2;
2837 icb->response_accumulation_timer = 3;
2838 icb->interrupt_delay_timer = 5;
2839
e315cd28 2840 vha->flags.process_response_queue = 1;
1da177e4 2841 } else {
4fdfefe5 2842 /* Enable ZIO. */
e315cd28 2843 if (!vha->flags.init_done) {
4fdfefe5
AV		 2844 ha->zio_mode = icb->add_firmware_options[0] &
2845 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2846 ha->zio_timer = icb->interrupt_delay_timer ?
2847 icb->interrupt_delay_timer: 2;
2848 }
1da177e4
LT		 2849 icb->add_firmware_options[0] &=
2850 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2851 vha->flags.process_response_queue = 0;
4fdfefe5 2852 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 2853 ha->zio_mode = QLA_ZIO_MODE_6;
2854
7c3df132 2855 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2856 "ZIO mode %d enabled; timer delay (%d us).\n",
2857 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2858
4fdfefe5
AV		 2859 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2860 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2861 vha->flags.process_response_queue = 1;
1da177e4
LT		 2862 }
2863 }
2864
4e08df3f 2865 if (rval) {
7c3df132
SK		 2866 ql_log(ql_log_warn, vha, 0x0069,
2867 "NVRAM configuration failed.\n");
4e08df3f
DM		 2868 }
2869 return (rval);
1da177e4
LT		 2870}
2871
19a7b4ae
JSEC		 2872static void
2873qla2x00_rport_del(void *data)
2874{
2875 fc_port_t *fcport = data;
d97994dc 2876 struct fc_rport *rport;
2d70c103 2877 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2878 unsigned long flags;
d97994dc 2879
044d78e1 2880 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2881 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2882 fcport->drport = NULL;
044d78e1 2883 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2884 if (rport) {
d97994dc 2885 fc_remote_port_delete(rport);
2d70c103
NB		 2886 /*
2887 * Release the target mode FC NEXUS in qla_target.c code
2888 * if target mod is enabled.
2889 */
2890 qlt_fc_port_deleted(vha, fcport);
2891 }
19a7b4ae
JSEC		 2892}
2893
1da177e4
LT		 2894/**
2895 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2896 * @ha: HA context
2897 * @flags: allocation flags
2898 *
2899 * Returns a pointer to the allocated fcport, or NULL, if none available.
2900 */
9a069e19 2901fc_port_t *
e315cd28 2902qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2903{
2904 fc_port_t *fcport;
2905
bbfbbbc1
MK		 2906 fcport = kzalloc(sizeof(fc_port_t), flags);
2907 if (!fcport)
2908 return NULL;
1da177e4
LT		 2909
2910 /* Setup fcport template structure. */
e315cd28 2911 fcport->vha = vha;
1da177e4
LT		 2912 fcport->port_type = FCT_UNKNOWN;
2913 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2914 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2915 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2916
bbfbbbc1 2917 return fcport;
1da177e4
LT		 2918}
2919
2920/*
2921 * qla2x00_configure_loop
2922 * Updates Fibre Channel Device Database with what is actually on loop.
2923 *
2924 * Input:
2925 * ha = adapter block pointer.
2926 *
2927 * Returns:
2928 * 0 = success.
2929 * 1 = error.
2930 * 2 = database was full and device was not configured.
2931 */
2932static int
e315cd28 2933qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2934{
2935 int rval;
2936 unsigned long flags, save_flags;
e315cd28 2937 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2938 rval = QLA_SUCCESS;
2939
2940 /* Get Initiator ID */
e315cd28
AC		 2941 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2942 rval = qla2x00_configure_hba(vha);
1da177e4 2943 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2944 ql_dbg(ql_dbg_disc, vha, 0x2013,
2945 "Unable to configure HBA.\n");
1da177e4
LT		 2946 return (rval);
2947 }
2948 }
2949
e315cd28 2950 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2951 ql_dbg(ql_dbg_disc, vha, 0x2014,
2952 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2953
2954 /*
2955 * If we have both an RSCN and PORT UPDATE pending then handle them
2956 * both at the same time.
2957 */
e315cd28
AC		 2958 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2959 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2960
3064ff39
MH		 2961 qla2x00_get_data_rate(vha);
2962
1da177e4
LT		 2963 /* Determine what we need to do */
2964 if (ha->current_topology == ISP_CFG_FL &&
2965 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2966
1da177e4
LT		 2967 set_bit(RSCN_UPDATE, &flags);
2968
2969 } else if (ha->current_topology == ISP_CFG_F &&
2970 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2971
1da177e4
LT		 2972 set_bit(RSCN_UPDATE, &flags);
2973 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2974
2975 } else if (ha->current_topology == ISP_CFG_N) {
2976 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2977
e315cd28 2978 } else if (!vha->flags.online ||
1da177e4
LT		 2979 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2980
1da177e4
LT		 2981 set_bit(RSCN_UPDATE, &flags);
2982 set_bit(LOCAL_LOOP_UPDATE, &flags);
2983 }
2984
2985 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2986 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2987 ql_dbg(ql_dbg_disc, vha, 0x2015,
2988 "Loop resync needed, failing.\n");
1da177e4 2989 rval = QLA_FUNCTION_FAILED;
642ef983 2990 } else
e315cd28 2991 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2992 }
2993
2994 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2995 if (LOOP_TRANSITION(vha)) {
2996 ql_dbg(ql_dbg_disc, vha, 0x201e,
2997 "Needs RSCN update and loop transition.\n");
1da177e4 2998 rval = QLA_FUNCTION_FAILED;
7c3df132 2999 }
e315cd28
AC		 3000 else
3001 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 3002 }
3003
3004 if (rval == QLA_SUCCESS) {
e315cd28
AC		 3005 if (atomic_read(&vha->loop_down_timer) ||
3006 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 3007 rval = QLA_FUNCTION_FAILED;
3008 } else {
e315cd28 3009 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 3010 ql_dbg(ql_dbg_disc, vha, 0x2069,
3011 "LOOP READY.\n");
1da177e4
LT		 3012 }
3013 }
3014
3015 if (rval) {
7c3df132
SK		 3016 ql_dbg(ql_dbg_disc, vha, 0x206a,
3017 "%s *** FAILED ***.\n", __func__);
1da177e4 3018 } else {
7c3df132
SK		 3019 ql_dbg(ql_dbg_disc, vha, 0x206b,
3020 "%s: exiting normally.\n", __func__);
1da177e4
LT		 3021 }
3022
cc3ef7bc 3023 /* Restore state if a resync event occurred during processing */
e315cd28 3024 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 3025 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 3026 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 3027 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 3028 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 3029 }
1da177e4
LT		 3030 }
3031
3032 return (rval);
3033}
3034
3035
3036
3037/*
3038 * qla2x00_configure_local_loop
3039 * Updates Fibre Channel Device Database with local loop devices.
3040 *
3041 * Input:
3042 * ha = adapter block pointer.
3043 *
3044 * Returns:
3045 * 0 = success.
3046 */
3047static int
e315cd28 3048qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3049{
3050 int rval, rval2;
3051 int found_devs;
3052 int found;
3053 fc_port_t *fcport, *new_fcport;
3054
3055 uint16_t index;
3056 uint16_t entries;
3057 char *id_iter;
3058 uint16_t loop_id;
3059 uint8_t domain, area, al_pa;
e315cd28 3060 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3061
3062 found_devs = 0;
3063 new_fcport = NULL;
642ef983 3064 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 3065
1da177e4 3066 /* Get list of logged in devices. */
642ef983 3067 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 3068 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 3069 &entries);
3070 if (rval != QLA_SUCCESS)
3071 goto cleanup_allocation;
3072
7c3df132
SK		 3073 ql_dbg(ql_dbg_disc, vha, 0x2017,
3074 "Entries in ID list (%d).\n", entries);
3075 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
3076 (uint8_t *)ha->gid_list,
3077 entries * sizeof(struct gid_list_info));
1da177e4
LT		 3078
3079 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3080 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3081 if (new_fcport == NULL) {
7c3df132
SK		 3082 ql_log(ql_log_warn, vha, 0x2018,
3083 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3084 rval = QLA_MEMORY_ALLOC_FAILED;
3085 goto cleanup_allocation;
3086 }
3087 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3088
3089 /*
3090 * Mark local devices that were present with FCF_DEVICE_LOST for now.
3091 */
e315cd28 3092 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3093 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3094 fcport->port_type != FCT_BROADCAST &&
3095 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3096
7c3df132
SK		 3097 ql_dbg(ql_dbg_disc, vha, 0x2019,
3098 "Marking port lost loop_id=0x%04x.\n",
3099 fcport->loop_id);
1da177e4 3100
ec426e10 3101 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3102 }
3103 }
3104
3105 /* Add devices to port list. */
3106 id_iter = (char *)ha->gid_list;
3107 for (index = 0; index < entries; index++) {
3108 domain = ((struct gid_list_info *)id_iter)->domain;
3109 area = ((struct gid_list_info *)id_iter)->area;
3110 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 3111 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 3112 loop_id = (uint16_t)
3113 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 3114 else
1da177e4
LT		 3115 loop_id = le16_to_cpu(
3116 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 3117 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3118
3119 /* Bypass reserved domain fields. */
3120 if ((domain & 0xf0) == 0xf0)
3121 continue;
3122
3123 /* Bypass if not same domain and area of adapter. */
f7d289f6 3124 if (area && domain &&
e315cd28 3125 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3126 continue;
3127
3128 /* Bypass invalid local loop ID. */
3129 if (loop_id > LAST_LOCAL_LOOP_ID)
3130 continue;
3131
370d550e
AE		 3132 memset(new_fcport, 0, sizeof(fc_port_t));
3133
1da177e4
LT		 3134 /* Fill in member data. */
3135 new_fcport->d_id.b.domain = domain;
3136 new_fcport->d_id.b.area = area;
3137 new_fcport->d_id.b.al_pa = al_pa;
3138 new_fcport->loop_id = loop_id;
e315cd28 3139 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3140 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3141 ql_dbg(ql_dbg_disc, vha, 0x201a,
3142 "Failed to retrieve fcport information "
3143 "-- get_port_database=%x, loop_id=0x%04x.\n",
3144 rval2, new_fcport->loop_id);
3145 ql_dbg(ql_dbg_disc, vha, 0x201b,
3146 "Scheduling resync.\n");
e315cd28 3147 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3148 continue;
3149 }
3150
3151 /* Check for matching device in port list. */
3152 found = 0;
3153 fcport = NULL;
e315cd28 3154 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3155 if (memcmp(new_fcport->port_name, fcport->port_name,
3156 WWN_SIZE))
3157 continue;
3158
ddb9b126 3159 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3160 fcport->loop_id = new_fcport->loop_id;
3161 fcport->port_type = new_fcport->port_type;
3162 fcport->d_id.b24 = new_fcport->d_id.b24;
3163 memcpy(fcport->node_name, new_fcport->node_name,
3164 WWN_SIZE);
3165
3166 found++;
3167 break;
3168 }
3169
3170 if (!found) {
3171 /* New device, add to fcports list. */
e315cd28 3172 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3173
3174 /* Allocate a new replacement fcport. */
3175 fcport = new_fcport;
e315cd28 3176 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3177 if (new_fcport == NULL) {
7c3df132
SK		 3178 ql_log(ql_log_warn, vha, 0x201c,
3179 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3180 rval = QLA_MEMORY_ALLOC_FAILED;
3181 goto cleanup_allocation;
3182 }
3183 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3184 }
3185
d8b45213 3186 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3187 fcport->fp_speed = ha->link_data_rate;
d8b45213 3188
e315cd28 3189 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3190
3191 found_devs++;
3192 }
3193
3194cleanup_allocation:
c9475cb0 3195 kfree(new_fcport);
1da177e4
LT		 3196
3197 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3198 ql_dbg(ql_dbg_disc, vha, 0x201d,
3199 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3200 }
3201
1da177e4
LT		 3202 return (rval);
3203}
3204
d8b45213 3205static void
e315cd28 3206qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3207{
d8b45213 3208 int rval;
93f2bd67 3209 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3210 struct qla_hw_data *ha = vha->hw;
d8b45213 3211
c76f2c01 3212 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3213 return;
3214
c9afb9a2
GM		 3215 if (atomic_read(&fcport->state) != FCS_ONLINE)
3216 return;
3217
39bd9622
AV		 3218 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3219 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3220 return;
3221
e315cd28 3222 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3223 mb);
d8b45213 3224 if (rval != QLA_SUCCESS) {
7c3df132 3225 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3226 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3227 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3228 } else {
7c3df132 3229 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3230 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3231 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3232 fcport->port_name);
d8b45213
AV		 3233 }
3234}
3235
23be331d 3236static void
e315cd28 3237qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 3238{
3239 struct fc_rport_identifiers rport_ids;
bdf79621 3240 struct fc_rport *rport;
044d78e1 3241 unsigned long flags;
8482e118 3242
f8b02a85
AV		 3243 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3244 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 3245 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3246 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3247 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3248 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3249 if (!rport) {
7c3df132
SK		 3250 ql_log(ql_log_warn, vha, 0x2006,
3251 "Unable to allocate fc remote port.\n");
77d74143
AV		 3252 return;
3253 }
2d70c103
NB		 3254 /*
3255 * Create target mode FC NEXUS in qla_target.c if target mode is
3256 * enabled..
3257 */
3258 qlt_fc_port_added(vha, fcport);
3259
044d78e1 3260 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3261 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3262 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3263
ad3e0eda 3264 rport->supported_classes = fcport->supported_classes;
77d74143 3265
8482e118 3266 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3267 if (fcport->port_type == FCT_INITIATOR)
3268 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3269 if (fcport->port_type == FCT_TARGET)
3270 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3271 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3272}
3273
23be331d
AB		 3274/*
3275 * qla2x00_update_fcport
3276 * Updates device on list.
3277 *
3278 * Input:
3279 * ha = adapter block pointer.
3280 * fcport = port structure pointer.
3281 *
3282 * Return:
3283 * 0 - Success
3284 * BIT_0 - error
3285 *
3286 * Context:
3287 * Kernel context.
3288 */
3289void
e315cd28 3290qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3291{
e315cd28 3292 fcport->vha = vha;
8ae6d9c7
GM		 3293
3294 if (IS_QLAFX00(vha->hw)) {
3295 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3296 qla2x00_reg_remote_port(vha, fcport);
3297 return;
3298 }
23be331d 3299 fcport->login_retry = 0;
5ff1d584 3300 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3301
1f93da52 3302 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3303 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3304 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3305 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3306}
3307
1da177e4
LT		 3308/*
3309 * qla2x00_configure_fabric
3310 * Setup SNS devices with loop ID's.
3311 *
3312 * Input:
3313 * ha = adapter block pointer.
3314 *
3315 * Returns:
3316 * 0 = success.
3317 * BIT_0 = error
3318 */
3319static int
e315cd28 3320qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3321{
b3b02e6e 3322 int rval;
e452ceb6 3323 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3324 uint16_t next_loopid;
3325 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3326 uint16_t loop_id;
1da177e4 3327 LIST_HEAD(new_fcports);
e315cd28
AC		 3328 struct qla_hw_data *ha = vha->hw;
3329 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3330
3331 /* If FL port exists, then SNS is present */
e428924c 3332 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3333 loop_id = NPH_F_PORT;
3334 else
3335 loop_id = SNS_FL_PORT;
e315cd28 3336 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3337 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3338 ql_dbg(ql_dbg_disc, vha, 0x201f,
3339 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3340
e315cd28 3341 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3342 return (QLA_SUCCESS);
3343 }
e315cd28 3344 vha->device_flags |= SWITCH_FOUND;
1da177e4 3345
1da177e4 3346 do {
cca5335c
AV		 3347 /* FDMI support. */
3348 if (ql2xfdmienable &&
e315cd28
AC		 3349 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3350 qla2x00_fdmi_register(vha);
cca5335c 3351
1da177e4 3352 /* Ensure we are logged into the SNS. */
e428924c 3353 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3354 loop_id = NPH_SNS;
3355 else
3356 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3357 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3358 0xfc, mb, BIT_1|BIT_0);
3359 if (rval != QLA_SUCCESS) {
3360 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3361 return rval;
0b91d116 3362 }
1da177e4 3363 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3364 ql_dbg(ql_dbg_disc, vha, 0x2042,
3365 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3366 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3367 mb[2], mb[6], mb[7]);
1da177e4
LT		 3368 return (QLA_SUCCESS);
3369 }
3370
e315cd28
AC		 3371 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3372 if (qla2x00_rft_id(vha)) {
1da177e4 3373 /* EMPTY */
7c3df132
SK		 3374 ql_dbg(ql_dbg_disc, vha, 0x2045,
3375 "Register FC-4 TYPE failed.\n");
1da177e4 3376 }
e315cd28 3377 if (qla2x00_rff_id(vha)) {
1da177e4 3378 /* EMPTY */
7c3df132
SK		 3379 ql_dbg(ql_dbg_disc, vha, 0x2049,
3380 "Register FC-4 Features failed.\n");
1da177e4 3381 }
e315cd28 3382 if (qla2x00_rnn_id(vha)) {
1da177e4 3383 /* EMPTY */
7c3df132
SK		 3384 ql_dbg(ql_dbg_disc, vha, 0x204f,
3385 "Register Node Name failed.\n");
e315cd28 3386 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3387 /* EMPTY */
7c3df132
SK		 3388 ql_dbg(ql_dbg_disc, vha, 0x2053,
3389 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3390 }
3391 }
3392
827210ba
JC		 3393#define QLA_FCPORT_SCAN 1
3394#define QLA_FCPORT_FOUND 2
3395
3396 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3397 fcport->scan_state = QLA_FCPORT_SCAN;
3398 }
3399
e315cd28 3400 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3401 if (rval != QLA_SUCCESS)
3402 break;
3403
e452ceb6
JC		 3404 /*
3405 * Logout all previous fabric devices marked lost, except
3406 * FCP2 devices.
3407 */
e315cd28
AC		 3408 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3409 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3410 break;
3411
3412 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3413 continue;
3414
827210ba 3415 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3416 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3417 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3418 ql2xplogiabsentdevice, 0);
1da177e4 3419 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3420 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3421 fcport->port_type != FCT_INITIATOR &&
3422 fcport->port_type != FCT_BROADCAST) {
e315cd28 3423 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3424 fcport->loop_id,
3425 fcport->d_id.b.domain,
3426 fcport->d_id.b.area,
3427 fcport->d_id.b.al_pa);
1a5c69bf 3428 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3429 }
3430 }
e452ceb6 3431 }
1da177e4 3432
e452ceb6
JC		 3433 /* Starting free loop ID. */
3434 next_loopid = ha->min_external_loopid;
3435
3436 /*
3437 * Scan through our port list and login entries that need to be
3438 * logged in.
3439 */
3440 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3441 if (atomic_read(&vha->loop_down_timer) ||
3442 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3443 break;
3444
3445 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3446 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3447 continue;
3448
3449 if (fcport->loop_id == FC_NO_LOOP_ID) {
3450 fcport->loop_id = next_loopid;
3451 rval = qla2x00_find_new_loop_id(
3452 base_vha, fcport);
3453 if (rval != QLA_SUCCESS) {
3454 /* Ran out of IDs to use */
3455 break;
1da177e4
LT		 3456 }
3457 }
e452ceb6
JC		 3458 /* Login and update database */
3459 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3460 }
3461
3462 /* Exit if out of loop IDs. */
3463 if (rval != QLA_SUCCESS) {
3464 break;
3465 }
3466
3467 /*
3468 * Login and add the new devices to our port list.
3469 */
3470 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3471 if (atomic_read(&vha->loop_down_timer) ||
3472 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3473 break;
3474
3475 /* Find a new loop ID to use. */
3476 fcport->loop_id = next_loopid;
3477 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3478 if (rval != QLA_SUCCESS) {
3479 /* Ran out of IDs to use */
3480 break;
3481 }
1da177e4 3482
bdf79621 3483 /* Login and update database */
e315cd28 3484 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3485
3486 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3487 }
3488 } while (0);
3489
e452ceb6
JC		 3490 /* Free all new device structures not processed. */
3491 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3492 list_del(&fcport->list);
3493 kfree(fcport);
3494 }
3495
1da177e4 3496 if (rval) {
7c3df132
SK		 3497 ql_dbg(ql_dbg_disc, vha, 0x2068,
3498 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3499 }
3500
3501 return (rval);
3502}
3503
1da177e4
LT		 3504/*
3505 * qla2x00_find_all_fabric_devs
3506 *
3507 * Input:
3508 * ha = adapter block pointer.
3509 * dev = database device entry pointer.
3510 *
3511 * Returns:
3512 * 0 = success.
3513 *
3514 * Context:
3515 * Kernel context.
3516 */
3517static int
e315cd28
AC		 3518qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3519 struct list_head *new_fcports)
1da177e4
LT		 3520{
3521 int rval;
3522 uint16_t loop_id;
3523 fc_port_t *fcport, *new_fcport, *fcptemp;
3524 int found;
3525
3526 sw_info_t *swl;
3527 int swl_idx;
3528 int first_dev, last_dev;
1516ef44 3529 port_id_t wrap = {}, nxt_d_id;
e315cd28 3530 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3531 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3532
3533 rval = QLA_SUCCESS;
3534
3535 /* Try GID_PT to get device list, else GAN. */
7a67735b 3536 if (!ha->swl)
642ef983 3537 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3538 GFP_KERNEL);
3539 swl = ha->swl;
bbfbbbc1 3540 if (!swl) {
1da177e4 3541 /*EMPTY*/
7c3df132
SK		 3542 ql_dbg(ql_dbg_disc, vha, 0x2054,
3543 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3544 } else {
642ef983 3545 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3546 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3547 swl = NULL;
e315cd28 3548 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3549 swl = NULL;
e315cd28 3550 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3551 swl = NULL;
e5896bd5 3552 } else if (ql2xiidmaenable &&
e315cd28
AC		 3553 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3554 qla2x00_gpsc(vha, swl);
1da177e4 3555 }
e8c72ba5
CD		 3556
3557 /* If other queries succeeded probe for FC-4 type */
3558 if (swl)
3559 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3560 }
3561 swl_idx = 0;
3562
3563 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3564 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3565 if (new_fcport == NULL) {
7c3df132
SK		 3566 ql_log(ql_log_warn, vha, 0x205e,
3567 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3568 return (QLA_MEMORY_ALLOC_FAILED);
3569 }
3570 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3571 /* Set start port ID scan at adapter ID. */
3572 first_dev = 1;
3573 last_dev = 0;
3574
3575 /* Starting free loop ID. */
e315cd28
AC		 3576 loop_id = ha->min_external_loopid;
3577 for (; loop_id <= ha->max_loop_id; loop_id++) {
3578 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3579 continue;
3580
3a6478df
GM		 3581 if (ha->current_topology == ISP_CFG_FL &&
3582 (atomic_read(&vha->loop_down_timer) ||
3583 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3584 atomic_set(&vha->loop_down_timer, 0);
3585 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3586 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3587 break;
bb2d52b2 3588 }
1da177e4
LT		 3589
3590 if (swl != NULL) {
3591 if (last_dev) {
3592 wrap.b24 = new_fcport->d_id.b24;
3593 } else {
3594 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3595 memcpy(new_fcport->node_name,
3596 swl[swl_idx].node_name, WWN_SIZE);
3597 memcpy(new_fcport->port_name,
3598 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3599 memcpy(new_fcport->fabric_port_name,
3600 swl[swl_idx].fabric_port_name, WWN_SIZE);
3601 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3602 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3603
3604 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3605 last_dev = 1;
3606 }
3607 swl_idx++;
3608 }
3609 } else {
3610 /* Send GA_NXT to the switch */
e315cd28 3611 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3612 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3613 ql_log(ql_log_warn, vha, 0x2064,
3614 "SNS scan failed -- assuming "
3615 "zero-entry result.\n");
1da177e4
LT		 3616 list_for_each_entry_safe(fcport, fcptemp,
3617 new_fcports, list) {
3618 list_del(&fcport->list);
3619 kfree(fcport);
3620 }
3621 rval = QLA_SUCCESS;
3622 break;
3623 }
3624 }
3625
3626 /* If wrap on switch device list, exit. */
3627 if (first_dev) {
3628 wrap.b24 = new_fcport->d_id.b24;
3629 first_dev = 0;
3630 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3631 ql_dbg(ql_dbg_disc, vha, 0x2065,
3632 "Device wrap (%02x%02x%02x).\n",
3633 new_fcport->d_id.b.domain,
3634 new_fcport->d_id.b.area,
3635 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3636 break;
3637 }
3638
2c3dfe3f 3639 /* Bypass if same physical adapter. */
e315cd28 3640 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3641 continue;
3642
2c3dfe3f 3643 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3644 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3645 continue;
2c3dfe3f 3646
f7d289f6
AV		 3647 /* Bypass if same domain and area of adapter. */
3648 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3649 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3650 ISP_CFG_FL)
3651 continue;
3652
1da177e4
LT		 3653 /* Bypass reserved domain fields. */
3654 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3655 continue;
3656
e8c72ba5 3657 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3658 if (ql2xgffidenable &&
3659 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3660 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3661 continue;
3662
1da177e4
LT		 3663 /* Locate matching device in database. */
3664 found = 0;
e315cd28 3665 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3666 if (memcmp(new_fcport->port_name, fcport->port_name,
3667 WWN_SIZE))
3668 continue;
3669
827210ba 3670 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3671
1da177e4
LT		 3672 found++;
3673
d8b45213
AV		 3674 /* Update port state. */
3675 memcpy(fcport->fabric_port_name,
3676 new_fcport->fabric_port_name, WWN_SIZE);
3677 fcport->fp_speed = new_fcport->fp_speed;
3678
1da177e4
LT		 3679 /*
3680 * If address the same and state FCS_ONLINE, nothing
3681 * changed.
3682 */
3683 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3684 atomic_read(&fcport->state) == FCS_ONLINE) {
3685 break;
3686 }
3687
3688 /*
3689 * If device was not a fabric device before.
3690 */
3691 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3692 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3693 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3694 fcport->flags |= (FCF_FABRIC_DEVICE |
3695 FCF_LOGIN_NEEDED);
1da177e4
LT		 3696 break;
3697 }
3698
3699 /*
3700 * Port ID changed or device was marked to be updated;
3701 * Log it out if still logged in and mark it for
3702 * relogin later.
3703 */
3704 fcport->d_id.b24 = new_fcport->d_id.b24;
3705 fcport->flags |= FCF_LOGIN_NEEDED;
3706 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3707 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3708 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3709 fcport->port_type != FCT_INITIATOR &&
3710 fcport->port_type != FCT_BROADCAST) {
e315cd28 3711 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3712 fcport->d_id.b.domain, fcport->d_id.b.area,
3713 fcport->d_id.b.al_pa);
5f16b331 3714 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3715 }
3716
3717 break;
3718 }
3719
3720 if (found)
3721 continue;
1da177e4
LT		 3722 /* If device was not in our fcports list, then add it. */
3723 list_add_tail(&new_fcport->list, new_fcports);
3724
3725 /* Allocate a new replacement fcport. */
3726 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3727 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3728 if (new_fcport == NULL) {
7c3df132
SK		 3729 ql_log(ql_log_warn, vha, 0x2066,
3730 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3731 return (QLA_MEMORY_ALLOC_FAILED);
3732 }
3733 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3734 new_fcport->d_id.b24 = nxt_d_id.b24;
3735 }
3736
c9475cb0 3737 kfree(new_fcport);
1da177e4 3738
1da177e4
LT		 3739 return (rval);
3740}
3741
3742/*
3743 * qla2x00_find_new_loop_id
3744 * Scan through our port list and find a new usable loop ID.
3745 *
3746 * Input:
3747 * ha: adapter state pointer.
3748 * dev: port structure pointer.
3749 *
3750 * Returns:
3751 * qla2x00 local function return status code.
3752 *
3753 * Context:
3754 * Kernel context.
3755 */
03bcfb57 3756int
e315cd28 3757qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3758{
3759 int rval;
e315cd28 3760 struct qla_hw_data *ha = vha->hw;
feafb7b1 3761 unsigned long flags = 0;
1da177e4
LT		 3762
3763 rval = QLA_SUCCESS;
3764
5f16b331 3765 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3766
5f16b331
CD		 3767 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3768 LOOPID_MAP_SIZE);
3769 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3770 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3771 dev->loop_id = FC_NO_LOOP_ID;
3772 rval = QLA_FUNCTION_FAILED;
3773 } else
3774 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3775
5f16b331 3776 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3777
5f16b331
CD		 3778 if (rval == QLA_SUCCESS)
3779 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3780 "Assigning new loopid=%x, portid=%x.\n",
3781 dev->loop_id, dev->d_id.b24);
3782 else
3783 ql_log(ql_log_warn, dev->vha, 0x2087,
3784 "No loop_id's available, portid=%x.\n",
3785 dev->d_id.b24);
1da177e4
LT		 3786
3787 return (rval);
3788}
3789
1da177e4
LT		 3790/*
3791 * qla2x00_fabric_dev_login
3792 * Login fabric target device and update FC port database.
3793 *
3794 * Input:
3795 * ha: adapter state pointer.
3796 * fcport: port structure list pointer.
3797 * next_loopid: contains value of a new loop ID that can be used
3798 * by the next login attempt.
3799 *
3800 * Returns:
3801 * qla2x00 local function return status code.
3802 *
3803 * Context:
3804 * Kernel context.
3805 */
3806static int
e315cd28 3807qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3808 uint16_t *next_loopid)
3809{
3810 int rval;
3811 int retry;
0107109e 3812 uint8_t opts;
e315cd28 3813 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3814
3815 rval = QLA_SUCCESS;
3816 retry = 0;
3817
ac280b67 3818 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3819 if (fcport->flags & FCF_ASYNC_SENT)
3820 return rval;
3821 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3822 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3823 if (!rval)
3824 return rval;
3825 }
3826
5ff1d584 3827 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3828 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3829 if (rval == QLA_SUCCESS) {
f08b7251 3830 /* Send an ADISC to FCP2 devices.*/
0107109e 3831 opts = 0;
f08b7251 3832 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3833 opts |= BIT_1;
e315cd28 3834 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3835 if (rval != QLA_SUCCESS) {
e315cd28 3836 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3837 fcport->d_id.b.domain, fcport->d_id.b.area,
3838 fcport->d_id.b.al_pa);
e315cd28 3839 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3840 } else {
e315cd28 3841 qla2x00_update_fcport(vha, fcport);
1da177e4 3842 }
0b91d116
CD		 3843 } else {
3844 /* Retry Login. */
3845 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3846 }
3847
3848 return (rval);
3849}
3850
3851/*
3852 * qla2x00_fabric_login
3853 * Issue fabric login command.
3854 *
3855 * Input:
3856 * ha = adapter block pointer.
3857 * device = pointer to FC device type structure.
3858 *
3859 * Returns:
3860 * 0 - Login successfully
3861 * 1 - Login failed
3862 * 2 - Initiator device
3863 * 3 - Fatal error
3864 */
3865int
e315cd28 3866qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3867 uint16_t *next_loopid)
3868{
3869 int rval;
3870 int retry;
3871 uint16_t tmp_loopid;
3872 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3873 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3874
3875 retry = 0;
3876 tmp_loopid = 0;
3877
3878 for (;;) {
7c3df132
SK		 3879 ql_dbg(ql_dbg_disc, vha, 0x2000,
3880 "Trying Fabric Login w/loop id 0x%04x for port "
3881 "%02x%02x%02x.\n",
3882 fcport->loop_id, fcport->d_id.b.domain,
3883 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3884
3885 /* Login fcport on switch. */
0b91d116 3886 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3887 fcport->d_id.b.domain, fcport->d_id.b.area,
3888 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3889 if (rval != QLA_SUCCESS) {
3890 return rval;
3891 }
1da177e4
LT		 3892 if (mb[0] == MBS_PORT_ID_USED) {
3893 /*
3894 * Device has another loop ID. The firmware team
0107109e
AV		 3895 * recommends the driver perform an implicit login with
3896 * the specified ID again. The ID we just used is save
3897 * here so we return with an ID that can be tried by
3898 * the next login.
1da177e4
LT		 3899 */
3900 retry++;
3901 tmp_loopid = fcport->loop_id;
3902 fcport->loop_id = mb[1];
3903
7c3df132
SK		 3904 ql_dbg(ql_dbg_disc, vha, 0x2001,
3905 "Fabric Login: port in use - next loop "
3906 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3907 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3908 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3909
3910 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3911 /*
3912 * Login succeeded.
3913 */
3914 if (retry) {
3915 /* A retry occurred before. */
3916 *next_loopid = tmp_loopid;
3917 } else {
3918 /*
3919 * No retry occurred before. Just increment the
3920 * ID value for next login.
3921 */
3922 *next_loopid = (fcport->loop_id + 1);
3923 }
3924
3925 if (mb[1] & BIT_0) {
3926 fcport->port_type = FCT_INITIATOR;
3927 } else {
3928 fcport->port_type = FCT_TARGET;
3929 if (mb[1] & BIT_1) {
8474f3a0 3930 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3931 }
3932 }
3933
ad3e0eda
AV		 3934 if (mb[10] & BIT_0)
3935 fcport->supported_classes |= FC_COS_CLASS2;
3936 if (mb[10] & BIT_1)
3937 fcport->supported_classes |= FC_COS_CLASS3;
3938
2d70c103
NB		 3939 if (IS_FWI2_CAPABLE(ha)) {
3940 if (mb[10] & BIT_7)
3941 fcport->flags |=
3942 FCF_CONF_COMP_SUPPORTED;
3943 }
3944
1da177e4
LT		 3945 rval = QLA_SUCCESS;
3946 break;
3947 } else if (mb[0] == MBS_LOOP_ID_USED) {
3948 /*
3949 * Loop ID already used, try next loop ID.
3950 */
3951 fcport->loop_id++;
e315cd28 3952 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3953 if (rval != QLA_SUCCESS) {
3954 /* Ran out of loop IDs to use */
3955 break;
3956 }
3957 } else if (mb[0] == MBS_COMMAND_ERROR) {
3958 /*
3959 * Firmware possibly timed out during login. If NO
3960 * retries are left to do then the device is declared
3961 * dead.
3962 */
3963 *next_loopid = fcport->loop_id;
e315cd28 3964 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3965 fcport->d_id.b.domain, fcport->d_id.b.area,
3966 fcport->d_id.b.al_pa);
e315cd28 3967 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3968
3969 rval = 1;
3970 break;
3971 } else {
3972 /*
3973 * unrecoverable / not handled error
3974 */
7c3df132
SK		 3975 ql_dbg(ql_dbg_disc, vha, 0x2002,
3976 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3977 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3978 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3979 fcport->loop_id, jiffies);
1da177e4
LT		 3980
3981 *next_loopid = fcport->loop_id;
e315cd28 3982 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3983 fcport->d_id.b.domain, fcport->d_id.b.area,
3984 fcport->d_id.b.al_pa);
5f16b331 3985 qla2x00_clear_loop_id(fcport);
0eedfcf0 3986 fcport->login_retry = 0;
1da177e4
LT		 3987
3988 rval = 3;
3989 break;
3990 }
3991 }
3992
3993 return (rval);
3994}
3995
3996/*
3997 * qla2x00_local_device_login
3998 * Issue local device login command.
3999 *
4000 * Input:
4001 * ha = adapter block pointer.
4002 * loop_id = loop id of device to login to.
4003 *
4004 * Returns (Where's the #define!!!!):
4005 * 0 - Login successfully
4006 * 1 - Login failed
4007 * 3 - Fatal error
4008 */
4009int
e315cd28 4010qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 4011{
4012 int rval;
4013 uint16_t mb[MAILBOX_REGISTER_COUNT];
4014
4015 memset(mb, 0, sizeof(mb));
e315cd28 4016 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 4017 if (rval == QLA_SUCCESS) {
4018 /* Interrogate mailbox registers for any errors */
4019 if (mb[0] == MBS_COMMAND_ERROR)
4020 rval = 1;
4021 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4022 /* device not in PCB table */
4023 rval = 3;
4024 }
4025
4026 return (rval);
4027}
4028
4029/*
4030 * qla2x00_loop_resync
4031 * Resync with fibre channel devices.
4032 *
4033 * Input:
4034 * ha = adapter block pointer.
4035 *
4036 * Returns:
4037 * 0 = success
4038 */
4039int
e315cd28 4040qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 4041{
73208dfd 4042 int rval = QLA_SUCCESS;
1da177e4 4043 uint32_t wait_time;
67c2e93a
AC		 4044 struct req_que *req;
4045 struct rsp_que *rsp;
4046
7163ea81 4047 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 4048 req = vha->hw->req_q_map[0];
4049 else
4050 req = vha->req;
4051 rsp = req->rsp;
1da177e4 4052
e315cd28
AC		 4053 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4054 if (vha->flags.online) {
4055 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 4056 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4057 wait_time = 256;
4058 do {
8ae6d9c7
GM		 4059 if (!IS_QLAFX00(vha->hw)) {
4060 /*
4061 * Issue a marker after FW becomes
4062 * ready.
4063 */
4064 qla2x00_marker(vha, req, rsp, 0, 0,
4065 MK_SYNC_ALL);
4066 vha->marker_needed = 0;
4067 }
1da177e4
LT		 4068
4069 /* Remap devices on Loop. */
e315cd28 4070 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 4071
8ae6d9c7
GM		 4072 if (IS_QLAFX00(vha->hw))
4073 qlafx00_configure_devices(vha);
4074 else
4075 qla2x00_configure_loop(vha);
4076
1da177e4 4077 wait_time--;
e315cd28
AC		 4078 } while (!atomic_read(&vha->loop_down_timer) &&
4079 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4080 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4081 &vha->dpc_flags)));
1da177e4 4082 }
1da177e4
LT		 4083 }
4084
e315cd28 4085 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 4086 return (QLA_FUNCTION_FAILED);
1da177e4 4087
e315cd28 4088 if (rval)
7c3df132
SK		 4089 ql_dbg(ql_dbg_disc, vha, 0x206c,
4090 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 4091
4092 return (rval);
4093}
4094
579d12b5
SK		 4095/*
4096* qla2x00_perform_loop_resync
4097* Description: This function will set the appropriate flags and call
4098* qla2x00_loop_resync. If successful loop will be resynced
4099* Arguments : scsi_qla_host_t pointer
4100* returm : Success or Failure
4101*/
4102
4103int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
4104{
4105 int32_t rval = 0;
4106
4107 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4108 /*Configure the flags so that resync happens properly*/
4109 atomic_set(&ha->loop_down_timer, 0);
4110 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4111 atomic_set(&ha->loop_state, LOOP_UP);
4112 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4113 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4114 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4115
4116 rval = qla2x00_loop_resync(ha);
4117 } else
4118 atomic_set(&ha->loop_state, LOOP_DEAD);
4119
4120 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4121 }
4122
4123 return rval;
4124}
4125
d97994dc 4126void
67becc00 4127qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 4128{
4129 fc_port_t *fcport;
feafb7b1
AE		 4130 struct scsi_qla_host *vha;
4131 struct qla_hw_data *ha = base_vha->hw;
4132 unsigned long flags;
d97994dc 4133
feafb7b1 4134 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4135 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4136 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4137 atomic_inc(&vha->vref_count);
4138 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4139 if (fcport->drport &&
feafb7b1
AE		 4140 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4141 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4142 qla2x00_rport_del(fcport);
feafb7b1
AE		 4143 spin_lock_irqsave(&ha->vport_slock, flags);
4144 }
4145 }
4146 atomic_dec(&vha->vref_count);
4147 }
4148 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 4149}
4150
7d613ac6
SV		 4151/* Assumes idc_lock always held on entry */
4152void
4153qla83xx_reset_ownership(scsi_qla_host_t *vha)
4154{
4155 struct qla_hw_data *ha = vha->hw;
4156 uint32_t drv_presence, drv_presence_mask;
4157 uint32_t dev_part_info1, dev_part_info2, class_type;
4158 uint32_t class_type_mask = 0x3;
4159 uint16_t fcoe_other_function = 0xffff, i;
4160
7ec0effd
AD		 4161 if (IS_QLA8044(ha)) {
4162 drv_presence = qla8044_rd_direct(vha,
4163 QLA8044_CRB_DRV_ACTIVE_INDEX);
4164 dev_part_info1 = qla8044_rd_direct(vha,
4165 QLA8044_CRB_DEV_PART_INFO_INDEX);
4166 dev_part_info2 = qla8044_rd_direct(vha,
4167 QLA8044_CRB_DEV_PART_INFO2);
4168 } else {
4169 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4170 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4171 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4172 }
7d613ac6
SV		 4173 for (i = 0; i < 8; i++) {
4174 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4175 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4176 (i != ha->portnum)) {
4177 fcoe_other_function = i;
4178 break;
4179 }
4180 }
4181 if (fcoe_other_function == 0xffff) {
4182 for (i = 0; i < 8; i++) {
4183 class_type = ((dev_part_info2 >> (i * 4)) &
4184 class_type_mask);
4185 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4186 ((i + 8) != ha->portnum)) {
4187 fcoe_other_function = i + 8;
4188 break;
4189 }
4190 }
4191 }
4192 /*
4193 * Prepare drv-presence mask based on fcoe functions present.
4194 * However consider only valid physical fcoe function numbers (0-15).
4195 */
4196 drv_presence_mask = ~((1 << (ha->portnum)) |
4197 ((fcoe_other_function == 0xffff) ?
4198 0 : (1 << (fcoe_other_function))));
4199
4200 /* We are the reset owner iff:
4201 * - No other protocol drivers present.
4202 * - This is the lowest among fcoe functions. */
4203 if (!(drv_presence & drv_presence_mask) &&
4204 (ha->portnum < fcoe_other_function)) {
4205 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4206 "This host is Reset owner.\n");
4207 ha->flags.nic_core_reset_owner = 1;
4208 }
4209}
4210
fa492630 4211static int
7d613ac6
SV		 4212__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4213{
4214 int rval = QLA_SUCCESS;
4215 struct qla_hw_data *ha = vha->hw;
4216 uint32_t drv_ack;
4217
4218 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4219 if (rval == QLA_SUCCESS) {
4220 drv_ack |= (1 << ha->portnum);
4221 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4222 }
4223
4224 return rval;
4225}
4226
fa492630 4227static int
7d613ac6
SV		 4228__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4229{
4230 int rval = QLA_SUCCESS;
4231 struct qla_hw_data *ha = vha->hw;
4232 uint32_t drv_ack;
4233
4234 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4235 if (rval == QLA_SUCCESS) {
4236 drv_ack &= ~(1 << ha->portnum);
4237 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4238 }
4239
4240 return rval;
4241}
4242
fa492630 4243static const char *
7d613ac6
SV		 4244qla83xx_dev_state_to_string(uint32_t dev_state)
4245{
4246 switch (dev_state) {
4247 case QLA8XXX_DEV_COLD:
4248 return "COLD/RE-INIT";
4249 case QLA8XXX_DEV_INITIALIZING:
4250 return "INITIALIZING";
4251 case QLA8XXX_DEV_READY:
4252 return "READY";
4253 case QLA8XXX_DEV_NEED_RESET:
4254 return "NEED RESET";
4255 case QLA8XXX_DEV_NEED_QUIESCENT:
4256 return "NEED QUIESCENT";
4257 case QLA8XXX_DEV_FAILED:
4258 return "FAILED";
4259 case QLA8XXX_DEV_QUIESCENT:
4260 return "QUIESCENT";
4261 default:
4262 return "Unknown";
4263 }
4264}
4265
4266/* Assumes idc-lock always held on entry */
4267void
4268qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4269{
4270 struct qla_hw_data *ha = vha->hw;
4271 uint32_t idc_audit_reg = 0, duration_secs = 0;
4272
4273 switch (audit_type) {
4274 case IDC_AUDIT_TIMESTAMP:
4275 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4276 idc_audit_reg = (ha->portnum) |
4277 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4278 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4279 break;
4280
4281 case IDC_AUDIT_COMPLETION:
4282 duration_secs = ((jiffies_to_msecs(jiffies) -
4283 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4284 idc_audit_reg = (ha->portnum) |
4285 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4286 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4287 break;
4288
4289 default:
4290 ql_log(ql_log_warn, vha, 0xb078,
4291 "Invalid audit type specified.\n");
4292 break;
4293 }
4294}
4295
4296/* Assumes idc_lock always held on entry */
fa492630 4297static int
7d613ac6
SV		 4298qla83xx_initiating_reset(scsi_qla_host_t *vha)
4299{
4300 struct qla_hw_data *ha = vha->hw;
4301 uint32_t idc_control, dev_state;
4302
4303 __qla83xx_get_idc_control(vha, &idc_control);
4304 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4305 ql_log(ql_log_info, vha, 0xb080,
4306 "NIC Core reset has been disabled. idc-control=0x%x\n",
4307 idc_control);
4308 return QLA_FUNCTION_FAILED;
4309 }
4310
4311 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4312 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4313 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4314 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4315 QLA8XXX_DEV_NEED_RESET);
4316 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4317 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4318 } else {
4319 const char *state = qla83xx_dev_state_to_string(dev_state);
4320 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4321
4322 /* SV: XXX: Is timeout required here? */
4323 /* Wait for IDC state change READY -> NEED_RESET */
4324 while (dev_state == QLA8XXX_DEV_READY) {
4325 qla83xx_idc_unlock(vha, 0);
4326 msleep(200);
4327 qla83xx_idc_lock(vha, 0);
4328 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4329 }
4330 }
4331
4332 /* Send IDC ack by writing to drv-ack register */
4333 __qla83xx_set_drv_ack(vha);
4334
4335 return QLA_SUCCESS;
4336}
4337
4338int
4339__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4340{
4341 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4342}
4343
7d613ac6
SV		 4344int
4345__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4346{
4347 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4348}
4349
fa492630 4350static int
7d613ac6
SV		 4351qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4352{
4353 uint32_t drv_presence = 0;
4354 struct qla_hw_data *ha = vha->hw;
4355
4356 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4357 if (drv_presence & (1 << ha->portnum))
4358 return QLA_SUCCESS;
4359 else
4360 return QLA_TEST_FAILED;
4361}
4362
4363int
4364qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4365{
4366 int rval = QLA_SUCCESS;
4367 struct qla_hw_data *ha = vha->hw;
4368
4369 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4370 "Entered %s().\n", __func__);
4371
4372 if (vha->device_flags & DFLG_DEV_FAILED) {
4373 ql_log(ql_log_warn, vha, 0xb059,
4374 "Device in unrecoverable FAILED state.\n");
4375 return QLA_FUNCTION_FAILED;
4376 }
4377
4378 qla83xx_idc_lock(vha, 0);
4379
4380 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4381 ql_log(ql_log_warn, vha, 0xb05a,
4382 "Function=0x%x has been removed from IDC participation.\n",
4383 ha->portnum);
4384 rval = QLA_FUNCTION_FAILED;
4385 goto exit;
4386 }
4387
4388 qla83xx_reset_ownership(vha);
4389
4390 rval = qla83xx_initiating_reset(vha);
4391
4392 /*
4393 * Perform reset if we are the reset-owner,
4394 * else wait till IDC state changes to READY/FAILED.
4395 */
4396 if (rval == QLA_SUCCESS) {
4397 rval = qla83xx_idc_state_handler(vha);
4398
4399 if (rval == QLA_SUCCESS)
4400 ha->flags.nic_core_hung = 0;
4401 __qla83xx_clear_drv_ack(vha);
4402 }
4403
4404exit:
4405 qla83xx_idc_unlock(vha, 0);
4406
4407 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4408
4409 return rval;
4410}
4411
81178772
SK		 4412int
4413qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4414{
4415 struct qla_hw_data *ha = vha->hw;
4416 int rval = QLA_FUNCTION_FAILED;
4417
4418 if (!IS_MCTP_CAPABLE(ha)) {
4419 /* This message can be removed from the final version */
4420 ql_log(ql_log_info, vha, 0x506d,
4421 "This board is not MCTP capable\n");
4422 return rval;
4423 }
4424
4425 if (!ha->mctp_dump) {
4426 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4427 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4428
4429 if (!ha->mctp_dump) {
4430 ql_log(ql_log_warn, vha, 0x506e,
4431 "Failed to allocate memory for mctp dump\n");
4432 return rval;
4433 }
4434 }
4435
4436#define MCTP_DUMP_STR_ADDR 0x00000000
4437 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4438 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4439 if (rval != QLA_SUCCESS) {
4440 ql_log(ql_log_warn, vha, 0x506f,
4441 "Failed to capture mctp dump\n");
4442 } else {
4443 ql_log(ql_log_info, vha, 0x5070,
4444 "Mctp dump capture for host (%ld/%p).\n",
4445 vha->host_no, ha->mctp_dump);
4446 ha->mctp_dumped = 1;
4447 }
4448
409ee0fe 4449 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4450 ha->flags.nic_core_reset_hdlr_active = 1;
4451 rval = qla83xx_restart_nic_firmware(vha);
4452 if (rval)
4453 /* NIC Core reset failed. */
4454 ql_log(ql_log_warn, vha, 0x5071,
4455 "Failed to restart nic firmware\n");
4456 else
4457 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4458 "Restarted NIC firmware successfully.\n");
4459 ha->flags.nic_core_reset_hdlr_active = 0;
4460 }
4461
4462 return rval;
4463
4464}
4465
579d12b5 4466/*
8fcd6b8b 4467* qla2x00_quiesce_io
579d12b5
SK		 4468* Description: This function will block the new I/Os
4469* Its not aborting any I/Os as context
4470* is not destroyed during quiescence
4471* Arguments: scsi_qla_host_t
4472* return : void
4473*/
4474void
8fcd6b8b 4475qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4476{
4477 struct qla_hw_data *ha = vha->hw;
4478 struct scsi_qla_host *vp;
4479
8fcd6b8b
CD		 4480 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4481 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4482
4483 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4484 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4485 atomic_set(&vha->loop_state, LOOP_DOWN);
4486 qla2x00_mark_all_devices_lost(vha, 0);
4487 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4488 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4489 } else {
4490 if (!atomic_read(&vha->loop_down_timer))
4491 atomic_set(&vha->loop_down_timer,
4492 LOOP_DOWN_TIME);
4493 }
4494 /* Wait for pending cmds to complete */
4495 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4496}
4497
a9083016
GM		 4498void
4499qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4500{
4501 struct qla_hw_data *ha = vha->hw;
579d12b5 4502 struct scsi_qla_host *vp;
feafb7b1 4503 unsigned long flags;
6aef87be 4504 fc_port_t *fcport;
a9083016 4505
e46ef004
SK		 4506 /* For ISP82XX, driver waits for completion of the commands.
4507 * online flag should be set.
4508 */
7ec0effd 4509 if (!(IS_P3P_TYPE(ha)))
e46ef004 4510 vha->flags.online = 0;
a9083016
GM		 4511 ha->flags.chip_reset_done = 0;
4512 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4513 vha->qla_stats.total_isp_aborts++;
a9083016 4514
7c3df132
SK		 4515 ql_log(ql_log_info, vha, 0x00af,
4516 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4517
e46ef004
SK		 4518 /* For ISP82XX, reset_chip is just disabling interrupts.
4519 * Driver waits for the completion of the commands.
4520 * the interrupts need to be enabled.
4521 */
7ec0effd 4522 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4523 ha->isp_ops->reset_chip(vha);
4524
4525 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4526 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4527 atomic_set(&vha->loop_state, LOOP_DOWN);
4528 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4529
4530 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4531 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4532 atomic_inc(&vp->vref_count);
4533 spin_unlock_irqrestore(&ha->vport_slock, flags);
4534
a9083016 4535 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4536
4537 spin_lock_irqsave(&ha->vport_slock, flags);
4538 atomic_dec(&vp->vref_count);
4539 }
4540 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4541 } else {
4542 if (!atomic_read(&vha->loop_down_timer))
4543 atomic_set(&vha->loop_down_timer,
4544 LOOP_DOWN_TIME);
4545 }
4546
6aef87be
AV		 4547 /* Clear all async request states across all VPs. */
4548 list_for_each_entry(fcport, &vha->vp_fcports, list)
4549 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4550 spin_lock_irqsave(&ha->vport_slock, flags);
4551 list_for_each_entry(vp, &ha->vp_list, list) {
4552 atomic_inc(&vp->vref_count);
4553 spin_unlock_irqrestore(&ha->vport_slock, flags);
4554
4555 list_for_each_entry(fcport, &vp->vp_fcports, list)
4556 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4557
4558 spin_lock_irqsave(&ha->vport_slock, flags);
4559 atomic_dec(&vp->vref_count);
4560 }
4561 spin_unlock_irqrestore(&ha->vport_slock, flags);
4562
bddd2d65
LC		 4563 if (!ha->flags.eeh_busy) {
4564 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4565 if (IS_P3P_TYPE(ha)) {
7190575f 4566 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4567 ql_log(ql_log_info, vha, 0x00b4,
4568 "Done chip reset cleanup.\n");
a9083016 4569
e46ef004
SK		 4570 /* Done waiting for pending commands.
4571 * Reset the online flag.
4572 */
4573 vha->flags.online = 0;
4d78c973 4574 }
a9083016 4575
bddd2d65
LC		 4576 /* Requeue all commands in outstanding command list. */
4577 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4578 }
b6a029e1
AE		 4579
4580 ha->chip_reset++;
4581 /* memory barrier */
4582 wmb();
a9083016
GM		 4583}
4584
1da177e4
LT		 4585/*
4586* qla2x00_abort_isp
4587* Resets ISP and aborts all outstanding commands.
4588*
4589* Input:
4590* ha = adapter block pointer.
4591*
4592* Returns:
4593* 0 = success
4594*/
4595int
e315cd28 4596qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4597{
476e8978 4598 int rval;
1da177e4 4599 uint8_t status = 0;
e315cd28
AC		 4600 struct qla_hw_data *ha = vha->hw;
4601 struct scsi_qla_host *vp;
73208dfd 4602 struct req_que *req = ha->req_q_map[0];
feafb7b1 4603 unsigned long flags;
1da177e4 4604
e315cd28 4605 if (vha->flags.online) {
a9083016 4606 qla2x00_abort_isp_cleanup(vha);
1da177e4 4607
a6171297
SV		 4608 if (IS_QLA8031(ha)) {
4609 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4610 "Clearing fcoe driver presence.\n");
4611 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4612 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4613 "Error while clearing DRV-Presence.\n");
4614 }
4615
85880801
AV		 4616 if (unlikely(pci_channel_offline(ha->pdev) &&
4617 ha->flags.pci_channel_io_perm_failure)) {
4618 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4619 status = 0;
4620 return status;
4621 }
4622
73208dfd 4623 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4624
e315cd28 4625 ha->isp_ops->nvram_config(vha);
1da177e4 4626
e315cd28
AC		 4627 if (!qla2x00_restart_isp(vha)) {
4628 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4629
e315cd28 4630 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4631 /*
4632 * Issue marker command only when we are going
4633 * to start the I/O .
4634 */
e315cd28 4635 vha->marker_needed = 1;
1da177e4
LT		 4636 }
4637
e315cd28 4638 vha->flags.online = 1;
1da177e4 4639
fd34f556 4640 ha->isp_ops->enable_intrs(ha);
1da177e4 4641
fa2a1ce5 4642 ha->isp_abort_cnt = 0;
e315cd28 4643 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4644
6246b8a1
GM		 4645 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4646 qla2x00_get_fw_version(vha);
df613b96
AV		 4647 if (ha->fce) {
4648 ha->flags.fce_enabled = 1;
4649 memset(ha->fce, 0,
4650 fce_calc_size(ha->fce_bufs));
e315cd28 4651 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4652 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4653 &ha->fce_bufs);
4654 if (rval) {
7c3df132 4655 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4656 "Unable to reinitialize FCE "
4657 "(%d).\n", rval);
4658 ha->flags.fce_enabled = 0;
4659 }
4660 }
436a7b11
AV		 4661
4662 if (ha->eft) {
4663 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4664 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4665 ha->eft_dma, EFT_NUM_BUFFERS);
4666 if (rval) {
7c3df132 4667 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4668 "Unable to reinitialize EFT "
4669 "(%d).\n", rval);
4670 }
4671 }
1da177e4 4672 } else { /* failed the ISP abort */
e315cd28
AC		 4673 vha->flags.online = 1;
4674 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4675 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4676 ql_log(ql_log_fatal, vha, 0x8035,
4677 "ISP error recover failed - "
4678 "board disabled.\n");
fa2a1ce5 4679 /*
1da177e4
LT		 4680 * The next call disables the board
4681 * completely.
4682 */
e315cd28
AC		 4683 ha->isp_ops->reset_adapter(vha);
4684 vha->flags.online = 0;
1da177e4 4685 clear_bit(ISP_ABORT_RETRY,
e315cd28 4686 &vha->dpc_flags);
1da177e4
LT		 4687 status = 0;
4688 } else { /* schedule another ISP abort */
4689 ha->isp_abort_cnt--;
7c3df132
SK		 4690 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4691 "ISP abort - retry remaining %d.\n",
4692 ha->isp_abort_cnt);
1da177e4
LT		 4693 status = 1;
4694 }
4695 } else {
4696 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4697 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4698 "ISP error recovery - retrying (%d) "
4699 "more times.\n", ha->isp_abort_cnt);
e315cd28 4700 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4701 status = 1;
4702 }
4703 }
fa2a1ce5 4704
1da177e4
LT		 4705 }
4706
e315cd28 4707 if (!status) {
7c3df132 4708 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4709
4710 spin_lock_irqsave(&ha->vport_slock, flags);
4711 list_for_each_entry(vp, &ha->vp_list, list) {
4712 if (vp->vp_idx) {
4713 atomic_inc(&vp->vref_count);
4714 spin_unlock_irqrestore(&ha->vport_slock, flags);
4715
e315cd28 4716 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4717
4718 spin_lock_irqsave(&ha->vport_slock, flags);
4719 atomic_dec(&vp->vref_count);
4720 }
e315cd28 4721 }
feafb7b1
AE		 4722 spin_unlock_irqrestore(&ha->vport_slock, flags);
4723
7d613ac6
SV		 4724 if (IS_QLA8031(ha)) {
4725 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4726 "Setting back fcoe driver presence.\n");
4727 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4728 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4729 "Error while setting DRV-Presence.\n");
4730 }
e315cd28 4731 } else {
d8424f68
JP		 4732 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4733 __func__);
1da177e4
LT		 4734 }
4735
4736 return(status);
4737}
4738
4739/*
4740* qla2x00_restart_isp
4741* restarts the ISP after a reset
4742*
4743* Input:
4744* ha = adapter block pointer.
4745*
4746* Returns:
4747* 0 = success
4748*/
4749static int
e315cd28 4750qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4751{
c6b2fca8 4752 int status = 0;
e315cd28 4753 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4754 struct req_que *req = ha->req_q_map[0];
4755 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4756 unsigned long flags;
1da177e4
LT		 4757
4758 /* If firmware needs to be loaded */
e315cd28
AC		 4759 if (qla2x00_isp_firmware(vha)) {
4760 vha->flags.online = 0;
4761 status = ha->isp_ops->chip_diag(vha);
4762 if (!status)
4763 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4764 }
4765
e315cd28
AC		 4766 if (!status && !(status = qla2x00_init_rings(vha))) {
4767 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4768 ha->flags.chip_reset_done = 1;
7108b76e 4769
73208dfd
AC		 4770 /* Initialize the queues in use */
4771 qla25xx_init_queues(ha);
4772
e315cd28
AC		 4773 status = qla2x00_fw_ready(vha);
4774 if (!status) {
0107109e 4775 /* Issue a marker after FW becomes ready. */
73208dfd 4776 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4777
e315cd28 4778 vha->flags.online = 1;
2d70c103
NB		 4779
4780 /*
4781 * Process any ATIO queue entries that came in
4782 * while we weren't online.
4783 */
4784 spin_lock_irqsave(&ha->hardware_lock, flags);
4785 if (qla_tgt_mode_enabled(vha))
4786 qlt_24xx_process_atio_queue(vha);
4787 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4788
7108b76e 4789 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4790 }
4791
4792 /* if no cable then assume it's good */
e315cd28 4793 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 4794 status = 0;
1da177e4
LT		 4795 }
4796 return (status);
4797}
4798
73208dfd
AC		 4799static int
4800qla25xx_init_queues(struct qla_hw_data *ha)
4801{
4802 struct rsp_que *rsp = NULL;
4803 struct req_que *req = NULL;
4804 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4805 int ret = -1;
4806 int i;
4807
2afa19a9 4808 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4809 rsp = ha->rsp_q_map[i];
4810 if (rsp) {
4811 rsp->options &= ~BIT_0;
618a7523 4812 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4813 if (ret != QLA_SUCCESS)
7c3df132
SK		 4814 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4815 "%s Rsp que: %d init failed.\n",
4816 __func__, rsp->id);
73208dfd 4817 else
7c3df132
SK		 4818 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4819 "%s Rsp que: %d inited.\n",
4820 __func__, rsp->id);
73208dfd 4821 }
2afa19a9
AC		 4822 }
4823 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4824 req = ha->req_q_map[i];
4825 if (req) {
29bdccbe 4826 /* Clear outstanding commands array. */
73208dfd 4827 req->options &= ~BIT_0;
618a7523 4828 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4829 if (ret != QLA_SUCCESS)
7c3df132
SK		 4830 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4831 "%s Req que: %d init failed.\n",
4832 __func__, req->id);
73208dfd 4833 else
7c3df132
SK		 4834 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4835 "%s Req que: %d inited.\n",
4836 __func__, req->id);
73208dfd
AC		 4837 }
4838 }
4839 return ret;
4840}
4841
1da177e4
LT		 4842/*
4843* qla2x00_reset_adapter
4844* Reset adapter.
4845*
4846* Input:
4847* ha = adapter block pointer.
4848*/
abbd8870 4849void
e315cd28 4850qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4851{
4852 unsigned long flags = 0;
e315cd28 4853 struct qla_hw_data *ha = vha->hw;
3d71644c 4854 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4855
e315cd28 4856 vha->flags.online = 0;
fd34f556 4857 ha->isp_ops->disable_intrs(ha);
1da177e4 4858
1da177e4
LT		 4859 spin_lock_irqsave(&ha->hardware_lock, flags);
4860 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4861 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4862 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4863 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4864 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4865}
0107109e
AV		 4866
4867void
e315cd28 4868qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4869{
4870 unsigned long flags = 0;
e315cd28 4871 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4872 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4873
7ec0effd 4874 if (IS_P3P_TYPE(ha))
a9083016
GM		 4875 return;
4876
e315cd28 4877 vha->flags.online = 0;
fd34f556 4878 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4879
4880 spin_lock_irqsave(&ha->hardware_lock, flags);
4881 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4882 RD_REG_DWORD(&reg->hccr);
4883 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4884 RD_REG_DWORD(&reg->hccr);
4885 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4886
4887 if (IS_NOPOLLING_TYPE(ha))
4888 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4889}
4890
4e08df3f
DM		 4891/* On sparc systems, obtain port and node WWN from firmware
4892 * properties.
4893 */
e315cd28
AC		 4894static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4895 struct nvram_24xx *nv)
4e08df3f
DM		 4896{
4897#ifdef CONFIG_SPARC
e315cd28 4898 struct qla_hw_data *ha = vha->hw;
4e08df3f 4899 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4900 struct device_node *dp = pci_device_to_OF_node(pdev);
4901 const u8 *val;
4e08df3f
DM		 4902 int len;
4903
4904 val = of_get_property(dp, "port-wwn", &len);
4905 if (val && len >= WWN_SIZE)
4906 memcpy(nv->port_name, val, WWN_SIZE);
4907
4908 val = of_get_property(dp, "node-wwn", &len);
4909 if (val && len >= WWN_SIZE)
4910 memcpy(nv->node_name, val, WWN_SIZE);
4911#endif
4912}
4913
0107109e 4914int
e315cd28 4915qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4916{
4e08df3f 4917 int rval;
0107109e
AV		 4918 struct init_cb_24xx *icb;
4919 struct nvram_24xx *nv;
4920 uint32_t *dptr;
4921 uint8_t *dptr1, *dptr2;
4922 uint32_t chksum;
4923 uint16_t cnt;
e315cd28 4924 struct qla_hw_data *ha = vha->hw;
0107109e 4925
4e08df3f 4926 rval = QLA_SUCCESS;
0107109e 4927 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4928 nv = ha->nvram;
0107109e
AV		 4929
4930 /* Determine NVRAM starting address. */
f73cb695 4931 if (ha->port_no == 0) {
e5b68a61
AC		 4932 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4933 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4934 } else {
0107109e 4935 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 4936 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4937 }
f73cb695 4938
e5b68a61
AC		 4939 ha->nvram_size = sizeof(struct nvram_24xx);
4940 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4941
281afe19
SJ		 4942 /* Get VPD data into cache */
4943 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4944 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4945 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4946
4947 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4948 dptr = (uint32_t *)nv;
e315cd28 4949 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4950 ha->nvram_size);
4951 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4952 chksum += le32_to_cpu(*dptr++);
4953
7c3df132
SK		 4954 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4955 "Contents of NVRAM\n");
4956 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4957 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4958
4959 /* Bad NVRAM data, set defaults parameters. */
4960 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4961 || nv->id[3] != ' ' ||
4962 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4963 /* Reset NVRAM data. */
7c3df132 4964 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4965 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4966 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4967 ql_log(ql_log_warn, vha, 0x006c,
4968 "Falling back to functioning (yet invalid -- WWPN) "
4969 "defaults.\n");
4e08df3f
DM		 4970
4971 /*
4972 * Set default initialization control block.
4973 */
4974 memset(nv, 0, ha->nvram_size);
4975 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4976 nv->version = __constant_cpu_to_le16(ICB_VERSION);
98aee70d 4977 nv->frame_payload_size = 2048;
4e08df3f
DM		 4978 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4979 nv->exchange_count = __constant_cpu_to_le16(0);
4980 nv->hard_address = __constant_cpu_to_le16(124);
4981 nv->port_name[0] = 0x21;
f73cb695 4982 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 4983 nv->port_name[2] = 0x00;
4984 nv->port_name[3] = 0xe0;
4985 nv->port_name[4] = 0x8b;
4986 nv->port_name[5] = 0x1c;
4987 nv->port_name[6] = 0x55;
4988 nv->port_name[7] = 0x86;
4989 nv->node_name[0] = 0x20;
4990 nv->node_name[1] = 0x00;
4991 nv->node_name[2] = 0x00;
4992 nv->node_name[3] = 0xe0;
4993 nv->node_name[4] = 0x8b;
4994 nv->node_name[5] = 0x1c;
4995 nv->node_name[6] = 0x55;
4996 nv->node_name[7] = 0x86;
e315cd28 4997 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4998 nv->login_retry_count = __constant_cpu_to_le16(8);
4999 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5000 nv->login_timeout = __constant_cpu_to_le16(0);
5001 nv->firmware_options_1 =
5002 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5003 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5004 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5005 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5006 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5007 nv->efi_parameters = __constant_cpu_to_le32(0);
5008 nv->reset_delay = 5;
5009 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5010 nv->port_down_retry_count = __constant_cpu_to_le16(30);
5011 nv->link_down_timeout = __constant_cpu_to_le16(30);
5012
5013 rval = 1;
0107109e
AV		 5014 }
5015
2d70c103
NB		 5016 if (!qla_ini_mode_enabled(vha)) {
5017 /* Don't enable full login after initial LIP */
5018 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
5019 /* Don't enable LIP full login for initiator */
5020 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
5021 }
5022
5023 qlt_24xx_config_nvram_stage1(vha, nv);
5024
0107109e 5025 /* Reset Initialization control block */
e315cd28 5026 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5027
5028 /* Copy 1st segment. */
5029 dptr1 = (uint8_t *)icb;
5030 dptr2 = (uint8_t *)&nv->version;
5031 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5032 while (cnt--)
5033 *dptr1++ = *dptr2++;
5034
5035 icb->login_retry_count = nv->login_retry_count;
3ea66e28 5036 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 5037
5038 /* Copy 2nd segment. */
5039 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5040 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5041 cnt = (uint8_t *)&icb->reserved_3 -
5042 (uint8_t *)&icb->interrupt_delay_timer;
5043 while (cnt--)
5044 *dptr1++ = *dptr2++;
5045
5046 /*
5047 * Setup driver NVRAM options.
5048 */
e315cd28 5049 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 5050 "QLA2462");
0107109e 5051
2d70c103
NB		 5052 qlt_24xx_config_nvram_stage2(vha, icb);
5053
5341e868 5054 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 5055 /* Use alternate WWN? */
5341e868
AV		 5056 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5057 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5058 }
5059
0107109e 5060 /* Prepare nodename */
fd0e7e4d 5061 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 5062 /*
5063 * Firmware will apply the following mask if the nodename was
5064 * not provided.
5065 */
5066 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5067 icb->node_name[0] &= 0xF0;
5068 }
5069
5070 /* Set host adapter parameters. */
5071 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 5072 ha->flags.enable_lip_reset = 0;
5073 ha->flags.enable_lip_full_login =
5074 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5075 ha->flags.enable_target_reset =
5076 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 5077 ha->flags.enable_led_scheme = 0;
d4c760c2 5078 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 5079
fd0e7e4d
AV		 5080 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5081 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 5082
5083 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
5084 sizeof(ha->fw_seriallink_options24));
5085
5086 /* save HBA serial number */
5087 ha->serial0 = icb->port_name[5];
5088 ha->serial1 = icb->port_name[6];
5089 ha->serial2 = icb->port_name[7];
e315cd28
AC		 5090 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5091 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 5092
bc8fb3cb 5093 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5094
0107109e
AV		 5095 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5096
5097 /* Set minimum login_timeout to 4 seconds. */
5098 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5099 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5100 if (le16_to_cpu(nv->login_timeout) < 4)
5101 nv->login_timeout = __constant_cpu_to_le16(4);
5102 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 5103 icb->login_timeout = nv->login_timeout;
0107109e 5104
00a537b8
AV		 5105 /* Set minimum RATOV to 100 tenths of a second. */
5106 ha->r_a_tov = 100;
0107109e
AV		 5107
5108 ha->loop_reset_delay = nv->reset_delay;
5109
5110 /* Link Down Timeout = 0:
5111 *
5112 * When Port Down timer expires we will start returning
5113 * I/O's to OS with "DID_NO_CONNECT".
5114 *
5115 * Link Down Timeout != 0:
5116 *
5117 * The driver waits for the link to come up after link down
5118 * before returning I/Os to OS with "DID_NO_CONNECT".
5119 */
5120 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5121 ha->loop_down_abort_time =
5122 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5123 } else {
5124 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5125 ha->loop_down_abort_time =
5126 (LOOP_DOWN_TIME - ha->link_down_timeout);
5127 }
5128
5129 /* Need enough time to try and get the port back. */
5130 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5131 if (qlport_down_retry)
5132 ha->port_down_retry_count = qlport_down_retry;
5133
5134 /* Set login_retry_count */
5135 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5136 if (ha->port_down_retry_count ==
5137 le16_to_cpu(nv->port_down_retry_count) &&
5138 ha->port_down_retry_count > 3)
5139 ha->login_retry_count = ha->port_down_retry_count;
5140 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5141 ha->login_retry_count = ha->port_down_retry_count;
5142 if (ql2xloginretrycount)
5143 ha->login_retry_count = ql2xloginretrycount;
5144
4fdfefe5 5145 /* Enable ZIO. */
e315cd28 5146 if (!vha->flags.init_done) {
4fdfefe5
AV		 5147 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5148 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5149 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5150 le16_to_cpu(icb->interrupt_delay_timer): 2;
5151 }
5152 icb->firmware_options_2 &= __constant_cpu_to_le32(
5153 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5154 vha->flags.process_response_queue = 0;
4fdfefe5 5155 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 5156 ha->zio_mode = QLA_ZIO_MODE_6;
5157
7c3df132 5158 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5159 "ZIO mode %d enabled; timer delay (%d us).\n",
5160 ha->zio_mode, ha->zio_timer * 100);
5161
5162 icb->firmware_options_2 |= cpu_to_le32(
5163 (uint32_t)ha->zio_mode);
5164 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5165 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5166 }
5167
4e08df3f 5168 if (rval) {
7c3df132
SK		 5169 ql_log(ql_log_warn, vha, 0x0070,
5170 "NVRAM configuration failed.\n");
4e08df3f
DM		 5171 }
5172 return (rval);
0107109e
AV		 5173}
5174
413975a0 5175static int
cbc8eb67
AV		 5176qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5177 uint32_t faddr)
d1c61909 5178{
73208dfd 5179 int rval = QLA_SUCCESS;
d1c61909 5180 int segments, fragment;
d1c61909
AV		 5181 uint32_t *dcode, dlen;
5182 uint32_t risc_addr;
5183 uint32_t risc_size;
5184 uint32_t i;
e315cd28 5185 struct qla_hw_data *ha = vha->hw;
73208dfd 5186 struct req_que *req = ha->req_q_map[0];
eaac30be 5187
7c3df132 5188 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5189 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5190
d1c61909
AV		 5191 rval = QLA_SUCCESS;
5192
5193 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5194 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5195 *srisc_addr = 0;
5196
5197 /* Validate firmware image by checking version. */
e315cd28 5198 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5199 for (i = 0; i < 4; i++)
5200 dcode[i] = be32_to_cpu(dcode[i]);
5201 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5202 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5203 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5204 dcode[3] == 0)) {
7c3df132
SK		 5205 ql_log(ql_log_fatal, vha, 0x008c,
5206 "Unable to verify the integrity of flash firmware "
5207 "image.\n");
5208 ql_log(ql_log_fatal, vha, 0x008d,
5209 "Firmware data: %08x %08x %08x %08x.\n",
5210 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5211
5212 return QLA_FUNCTION_FAILED;
5213 }
5214
5215 while (segments && rval == QLA_SUCCESS) {
5216 /* Read segment's load information. */
e315cd28 5217 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5218
5219 risc_addr = be32_to_cpu(dcode[2]);
5220 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5221 risc_size = be32_to_cpu(dcode[3]);
5222
5223 fragment = 0;
5224 while (risc_size > 0 && rval == QLA_SUCCESS) {
5225 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5226 if (dlen > risc_size)
5227 dlen = risc_size;
5228
7c3df132
SK		 5229 ql_dbg(ql_dbg_init, vha, 0x008e,
5230 "Loading risc segment@ risc addr %x "
5231 "number of dwords 0x%x offset 0x%x.\n",
5232 risc_addr, dlen, faddr);
d1c61909 5233
e315cd28 5234 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5235 for (i = 0; i < dlen; i++)
5236 dcode[i] = swab32(dcode[i]);
5237
73208dfd 5238 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5239 dlen);
5240 if (rval) {
7c3df132
SK		 5241 ql_log(ql_log_fatal, vha, 0x008f,
5242 "Failed to load segment %d of firmware.\n",
5243 fragment);
f261f7af 5244 return QLA_FUNCTION_FAILED;
d1c61909
AV		 5245 }
5246
5247 faddr += dlen;
5248 risc_addr += dlen;
5249 risc_size -= dlen;
5250 fragment++;
5251 }
5252
5253 /* Next segment. */
5254 segments--;
5255 }
5256
f73cb695
CD		 5257 if (!IS_QLA27XX(ha))
5258 return rval;
5259
5260 if (ha->fw_dump_template)
5261 vfree(ha->fw_dump_template);
5262 ha->fw_dump_template = NULL;
5263 ha->fw_dump_template_len = 0;
5264
5265 ql_dbg(ql_dbg_init, vha, 0x0161,
5266 "Loading fwdump template from %x\n", faddr);
5267 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5268 risc_size = be32_to_cpu(dcode[2]);
5269 ql_dbg(ql_dbg_init, vha, 0x0162,
5270 "-> array size %x dwords\n", risc_size);
5271 if (risc_size == 0 || risc_size == ~0)
5272 goto default_template;
5273
5274 dlen = (risc_size - 8) * sizeof(*dcode);
5275 ql_dbg(ql_dbg_init, vha, 0x0163,
5276 "-> template allocating %x bytes...\n", dlen);
5277 ha->fw_dump_template = vmalloc(dlen);
5278 if (!ha->fw_dump_template) {
5279 ql_log(ql_log_warn, vha, 0x0164,
5280 "Failed fwdump template allocate %x bytes.\n", risc_size);
5281 goto default_template;
5282 }
5283
5284 faddr += 7;
5285 risc_size -= 8;
5286 dcode = ha->fw_dump_template;
5287 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5288 for (i = 0; i < risc_size; i++)
5289 dcode[i] = le32_to_cpu(dcode[i]);
5290
5291 if (!qla27xx_fwdt_template_valid(dcode)) {
5292 ql_log(ql_log_warn, vha, 0x0165,
5293 "Failed fwdump template validate\n");
5294 goto default_template;
5295 }
5296
5297 dlen = qla27xx_fwdt_template_size(dcode);
5298 ql_dbg(ql_dbg_init, vha, 0x0166,
5299 "-> template size %x bytes\n", dlen);
5300 if (dlen > risc_size * sizeof(*dcode)) {
5301 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 5302 "Failed fwdump template exceeds array by %x bytes\n",
5303 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 5304 goto default_template;
5305 }
5306 ha->fw_dump_template_len = dlen;
5307 return rval;
5308
5309default_template:
5310 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5311 if (ha->fw_dump_template)
5312 vfree(ha->fw_dump_template);
5313 ha->fw_dump_template = NULL;
5314 ha->fw_dump_template_len = 0;
5315
5316 dlen = qla27xx_fwdt_template_default_size();
5317 ql_dbg(ql_dbg_init, vha, 0x0169,
5318 "-> template allocating %x bytes...\n", dlen);
5319 ha->fw_dump_template = vmalloc(dlen);
5320 if (!ha->fw_dump_template) {
5321 ql_log(ql_log_warn, vha, 0x016a,
5322 "Failed fwdump template allocate %x bytes.\n", risc_size);
5323 goto failed_template;
5324 }
5325
5326 dcode = ha->fw_dump_template;
5327 risc_size = dlen / sizeof(*dcode);
5328 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5329 for (i = 0; i < risc_size; i++)
5330 dcode[i] = be32_to_cpu(dcode[i]);
5331
5332 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5333 ql_log(ql_log_warn, vha, 0x016b,
5334 "Failed fwdump template validate\n");
5335 goto failed_template;
5336 }
5337
5338 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5339 ql_dbg(ql_dbg_init, vha, 0x016c,
5340 "-> template size %x bytes\n", dlen);
5341 ha->fw_dump_template_len = dlen;
5342 return rval;
5343
5344failed_template:
5345 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5346 if (ha->fw_dump_template)
5347 vfree(ha->fw_dump_template);
5348 ha->fw_dump_template = NULL;
5349 ha->fw_dump_template_len = 0;
d1c61909
AV		 5350 return rval;
5351}
5352
e9454a88 5353#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5354
0107109e 5355int
e315cd28 5356qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5357{
5358 int rval;
5359 int i, fragment;
5360 uint16_t *wcode, *fwcode;
5361 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5362 struct fw_blob *blob;
e315cd28 5363 struct qla_hw_data *ha = vha->hw;
73208dfd 5364 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5365
5366 /* Load firmware blob. */
e315cd28 5367 blob = qla2x00_request_firmware(vha);
5433383e 5368 if (!blob) {
7c3df132
SK		 5369 ql_log(ql_log_info, vha, 0x0083,
5370 "Fimware image unavailable.\n");
5371 ql_log(ql_log_info, vha, 0x0084,
5372 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5373 return QLA_FUNCTION_FAILED;
5374 }
5375
5376 rval = QLA_SUCCESS;
5377
73208dfd 5378 wcode = (uint16_t *)req->ring;
5433383e
AV		 5379 *srisc_addr = 0;
5380 fwcode = (uint16_t *)blob->fw->data;
5381 fwclen = 0;
5382
5383 /* Validate firmware image by checking version. */
5384 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5385 ql_log(ql_log_fatal, vha, 0x0085,
5386 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5387 blob->fw->size);
5388 goto fail_fw_integrity;
5389 }
5390 for (i = 0; i < 4; i++)
5391 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5392 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5393 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5394 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5395 ql_log(ql_log_fatal, vha, 0x0086,
5396 "Unable to verify integrity of firmware image.\n");
5397 ql_log(ql_log_fatal, vha, 0x0087,
5398 "Firmware data: %04x %04x %04x %04x.\n",
5399 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5400 goto fail_fw_integrity;
5401 }
5402
5403 seg = blob->segs;
5404 while (*seg && rval == QLA_SUCCESS) {
5405 risc_addr = *seg;
5406 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5407 risc_size = be16_to_cpu(fwcode[3]);
5408
5409 /* Validate firmware image size. */
5410 fwclen += risc_size * sizeof(uint16_t);
5411 if (blob->fw->size < fwclen) {
7c3df132 5412 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5413 "Unable to verify integrity of firmware image "
7c3df132 5414 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5415 goto fail_fw_integrity;
5416 }
5417
5418 fragment = 0;
5419 while (risc_size > 0 && rval == QLA_SUCCESS) {
5420 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5421 if (wlen > risc_size)
5422 wlen = risc_size;
7c3df132
SK		 5423 ql_dbg(ql_dbg_init, vha, 0x0089,
5424 "Loading risc segment@ risc addr %x number of "
5425 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5426
5427 for (i = 0; i < wlen; i++)
5428 wcode[i] = swab16(fwcode[i]);
5429
73208dfd 5430 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5431 wlen);
5432 if (rval) {
7c3df132
SK		 5433 ql_log(ql_log_fatal, vha, 0x008a,
5434 "Failed to load segment %d of firmware.\n",
5435 fragment);
5433383e
AV		 5436 break;
5437 }
5438
5439 fwcode += wlen;
5440 risc_addr += wlen;
5441 risc_size -= wlen;
5442 fragment++;
5443 }
5444
5445 /* Next segment. */
5446 seg++;
5447 }
5448 return rval;
5449
5450fail_fw_integrity:
5451 return QLA_FUNCTION_FAILED;
5452}
5453
eaac30be
AV		 5454static int
5455qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5456{
5457 int rval;
5458 int segments, fragment;
5459 uint32_t *dcode, dlen;
5460 uint32_t risc_addr;
5461 uint32_t risc_size;
5462 uint32_t i;
5433383e 5463 struct fw_blob *blob;
f73cb695
CD		 5464 const uint32_t *fwcode;
5465 uint32_t fwclen;
e315cd28 5466 struct qla_hw_data *ha = vha->hw;
73208dfd 5467 struct req_que *req = ha->req_q_map[0];
0107109e 5468
5433383e 5469 /* Load firmware blob. */
e315cd28 5470 blob = qla2x00_request_firmware(vha);
5433383e 5471 if (!blob) {
7c3df132
SK		 5472 ql_log(ql_log_warn, vha, 0x0090,
5473 "Fimware image unavailable.\n");
5474 ql_log(ql_log_warn, vha, 0x0091,
5475 "Firmware images can be retrieved from: "
5476 QLA_FW_URL ".\n");
d1c61909 5477
eaac30be 5478 return QLA_FUNCTION_FAILED;
0107109e
AV		 5479 }
5480
cfb0919c
CD		 5481 ql_dbg(ql_dbg_init, vha, 0x0092,
5482 "FW: Loading via request-firmware.\n");
eaac30be 5483
0107109e
AV		 5484 rval = QLA_SUCCESS;
5485
5486 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5487 dcode = (uint32_t *)req->ring;
0107109e 5488 *srisc_addr = 0;
5433383e 5489 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5490 fwclen = 0;
5491
5492 /* Validate firmware image by checking version. */
5433383e 5493 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5494 ql_log(ql_log_fatal, vha, 0x0093,
5495 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5496 blob->fw->size);
f73cb695 5497 return QLA_FUNCTION_FAILED;
0107109e
AV		 5498 }
5499 for (i = 0; i < 4; i++)
5500 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5501 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5502 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5503 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5504 dcode[3] == 0)) {
7c3df132
SK		 5505 ql_log(ql_log_fatal, vha, 0x0094,
5506 "Unable to verify integrity of firmware image (%Zd).\n",
5507 blob->fw->size);
5508 ql_log(ql_log_fatal, vha, 0x0095,
5509 "Firmware data: %08x %08x %08x %08x.\n",
5510 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5511 return QLA_FUNCTION_FAILED;
0107109e
AV		 5512 }
5513
5514 while (segments && rval == QLA_SUCCESS) {
5515 risc_addr = be32_to_cpu(fwcode[2]);
5516 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5517 risc_size = be32_to_cpu(fwcode[3]);
5518
5519 /* Validate firmware image size. */
5520 fwclen += risc_size * sizeof(uint32_t);
5433383e 5521 if (blob->fw->size < fwclen) {
7c3df132 5522 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5523 "Unable to verify integrity of firmware image "
7c3df132 5524 "(%Zd).\n", blob->fw->size);
f73cb695 5525 return QLA_FUNCTION_FAILED;
0107109e
AV		 5526 }
5527
5528 fragment = 0;
5529 while (risc_size > 0 && rval == QLA_SUCCESS) {
5530 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5531 if (dlen > risc_size)
5532 dlen = risc_size;
5533
7c3df132
SK		 5534 ql_dbg(ql_dbg_init, vha, 0x0097,
5535 "Loading risc segment@ risc addr %x "
5536 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5537
5538 for (i = 0; i < dlen; i++)
5539 dcode[i] = swab32(fwcode[i]);
5540
73208dfd 5541 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5542 dlen);
0107109e 5543 if (rval) {
7c3df132
SK		 5544 ql_log(ql_log_fatal, vha, 0x0098,
5545 "Failed to load segment %d of firmware.\n",
5546 fragment);
f261f7af 5547 return QLA_FUNCTION_FAILED;
0107109e
AV		 5548 }
5549
5550 fwcode += dlen;
5551 risc_addr += dlen;
5552 risc_size -= dlen;
5553 fragment++;
5554 }
5555
5556 /* Next segment. */
5557 segments--;
5558 }
f73cb695
CD		 5559
5560 if (!IS_QLA27XX(ha))
5561 return rval;
5562
5563 if (ha->fw_dump_template)
5564 vfree(ha->fw_dump_template);
5565 ha->fw_dump_template = NULL;
5566 ha->fw_dump_template_len = 0;
5567
5568 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 5569 "Loading fwdump template from %x\n",
5570 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 5571 risc_size = be32_to_cpu(fwcode[2]);
5572 ql_dbg(ql_dbg_init, vha, 0x172,
5573 "-> array size %x dwords\n", risc_size);
5574 if (risc_size == 0 || risc_size == ~0)
5575 goto default_template;
5576
5577 dlen = (risc_size - 8) * sizeof(*fwcode);
5578 ql_dbg(ql_dbg_init, vha, 0x0173,
5579 "-> template allocating %x bytes...\n", dlen);
5580 ha->fw_dump_template = vmalloc(dlen);
5581 if (!ha->fw_dump_template) {
5582 ql_log(ql_log_warn, vha, 0x0174,
5583 "Failed fwdump template allocate %x bytes.\n", risc_size);
5584 goto default_template;
5585 }
5586
5587 fwcode += 7;
5588 risc_size -= 8;
5589 dcode = ha->fw_dump_template;
5590 for (i = 0; i < risc_size; i++)
5591 dcode[i] = le32_to_cpu(fwcode[i]);
5592
5593 if (!qla27xx_fwdt_template_valid(dcode)) {
5594 ql_log(ql_log_warn, vha, 0x0175,
5595 "Failed fwdump template validate\n");
5596 goto default_template;
5597 }
5598
5599 dlen = qla27xx_fwdt_template_size(dcode);
5600 ql_dbg(ql_dbg_init, vha, 0x0176,
5601 "-> template size %x bytes\n", dlen);
5602 if (dlen > risc_size * sizeof(*fwcode)) {
5603 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 5604 "Failed fwdump template exceeds array by %x bytes\n",
5605 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 5606 goto default_template;
5607 }
5608 ha->fw_dump_template_len = dlen;
0107109e
AV		 5609 return rval;
5610
f73cb695
CD		 5611default_template:
5612 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5613 if (ha->fw_dump_template)
5614 vfree(ha->fw_dump_template);
5615 ha->fw_dump_template = NULL;
5616 ha->fw_dump_template_len = 0;
5617
5618 dlen = qla27xx_fwdt_template_default_size();
5619 ql_dbg(ql_dbg_init, vha, 0x0179,
5620 "-> template allocating %x bytes...\n", dlen);
5621 ha->fw_dump_template = vmalloc(dlen);
5622 if (!ha->fw_dump_template) {
5623 ql_log(ql_log_warn, vha, 0x017a,
5624 "Failed fwdump template allocate %x bytes.\n", risc_size);
5625 goto failed_template;
5626 }
5627
5628 dcode = ha->fw_dump_template;
5629 risc_size = dlen / sizeof(*fwcode);
5630 fwcode = qla27xx_fwdt_template_default();
5631 for (i = 0; i < risc_size; i++)
5632 dcode[i] = be32_to_cpu(fwcode[i]);
5633
5634 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5635 ql_log(ql_log_warn, vha, 0x017b,
5636 "Failed fwdump template validate\n");
5637 goto failed_template;
5638 }
5639
5640 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5641 ql_dbg(ql_dbg_init, vha, 0x017c,
5642 "-> template size %x bytes\n", dlen);
5643 ha->fw_dump_template_len = dlen;
5644 return rval;
5645
5646failed_template:
5647 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5648 if (ha->fw_dump_template)
5649 vfree(ha->fw_dump_template);
5650 ha->fw_dump_template = NULL;
5651 ha->fw_dump_template_len = 0;
5652 return rval;
0107109e 5653}
18c6c127 5654
eaac30be
AV		 5655int
5656qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5657{
5658 int rval;
5659
e337d907
AV		 5660 if (ql2xfwloadbin == 1)
5661 return qla81xx_load_risc(vha, srisc_addr);
5662
eaac30be
AV		 5663 /*
5664 * FW Load priority:
5665 * 1) Firmware via request-firmware interface (.bin file).
5666 * 2) Firmware residing in flash.
5667 */
5668 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5669 if (rval == QLA_SUCCESS)
5670 return rval;
5671
cbc8eb67
AV		 5672 return qla24xx_load_risc_flash(vha, srisc_addr,
5673 vha->hw->flt_region_fw);
eaac30be
AV		 5674}
5675
5676int
5677qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5678{
5679 int rval;
cbc8eb67 5680 struct qla_hw_data *ha = vha->hw;
eaac30be 5681
e337d907 5682 if (ql2xfwloadbin == 2)
cbc8eb67 5683 goto try_blob_fw;
e337d907 5684
eaac30be
AV		 5685 /*
5686 * FW Load priority:
5687 * 1) Firmware residing in flash.
5688 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5689 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5690 */
cbc8eb67 5691 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5692 if (rval == QLA_SUCCESS)
5693 return rval;
5694
cbc8eb67
AV		 5695try_blob_fw:
5696 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5697 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5698 return rval;
5699
7c3df132
SK		 5700 ql_log(ql_log_info, vha, 0x0099,
5701 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5702 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5703 if (rval != QLA_SUCCESS)
5704 return rval;
5705
7c3df132 5706 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5707 ha->flags.running_gold_fw = 1;
cbc8eb67 5708 return rval;
eaac30be
AV		 5709}
5710
18c6c127 5711void
e315cd28 5712qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5713{
5714 int ret, retries;
e315cd28 5715 struct qla_hw_data *ha = vha->hw;
18c6c127 5716
85880801
AV		 5717 if (ha->flags.pci_channel_io_perm_failure)
5718 return;
e428924c 5719 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5720 return;
75edf81d
AV		 5721 if (!ha->fw_major_version)
5722 return;
18c6c127 5723
e315cd28 5724 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5725 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5726 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5727 ha->isp_ops->reset_chip(vha);
5728 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5729 continue;
e315cd28 5730 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5731 continue;
7c3df132
SK		 5732 ql_log(ql_log_info, vha, 0x8015,
5733 "Attempting retry of stop-firmware command.\n");
e315cd28 5734 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5735 }
5736}
2c3dfe3f
SJ		 5737
5738int
e315cd28 5739qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5740{
5741 int rval = QLA_SUCCESS;
0b91d116 5742 int rval2;
2c3dfe3f 5743 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5744 struct qla_hw_data *ha = vha->hw;
5745 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5746 struct req_que *req;
5747 struct rsp_que *rsp;
2c3dfe3f 5748
e315cd28 5749 if (!vha->vp_idx)
2c3dfe3f
SJ		 5750 return -EINVAL;
5751
e315cd28 5752 rval = qla2x00_fw_ready(base_vha);
7163ea81 5753 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5754 req = ha->req_q_map[0];
5755 else
5756 req = vha->req;
5757 rsp = req->rsp;
5758
2c3dfe3f 5759 if (rval == QLA_SUCCESS) {
e315cd28 5760 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5761 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5762 }
5763
e315cd28 5764 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5765
5766 /* Login to SNS first */
0b91d116
CD		 5767 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5768 BIT_1);
5769 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5770 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5771 ql_dbg(ql_dbg_init, vha, 0x0120,
5772 "Failed SNS login: loop_id=%x, rval2=%d\n",
5773 NPH_SNS, rval2);
5774 else
5775 ql_dbg(ql_dbg_init, vha, 0x0103,
5776 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5777 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5778 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5779 return (QLA_FUNCTION_FAILED);
5780 }
5781
e315cd28
AC		 5782 atomic_set(&vha->loop_down_timer, 0);
5783 atomic_set(&vha->loop_state, LOOP_UP);
5784 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5785 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5786 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5787
5788 return rval;
5789}
4d4df193
HK		 5790
5791/* 84XX Support **************************************************************/
5792
5793static LIST_HEAD(qla_cs84xx_list);
5794static DEFINE_MUTEX(qla_cs84xx_mutex);
5795
5796static struct qla_chip_state_84xx *
e315cd28 5797qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5798{
5799 struct qla_chip_state_84xx *cs84xx;
e315cd28 5800 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5801
5802 mutex_lock(&qla_cs84xx_mutex);
5803
5804 /* Find any shared 84xx chip. */
5805 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5806 if (cs84xx->bus == ha->pdev->bus) {
5807 kref_get(&cs84xx->kref);
5808 goto done;
5809 }
5810 }
5811
5812 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5813 if (!cs84xx)
5814 goto done;
5815
5816 kref_init(&cs84xx->kref);
5817 spin_lock_init(&cs84xx->access_lock);
5818 mutex_init(&cs84xx->fw_update_mutex);
5819 cs84xx->bus = ha->pdev->bus;
5820
5821 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5822done:
5823 mutex_unlock(&qla_cs84xx_mutex);
5824 return cs84xx;
5825}
5826
5827static void
5828__qla84xx_chip_release(struct kref *kref)
5829{
5830 struct qla_chip_state_84xx *cs84xx =
5831 container_of(kref, struct qla_chip_state_84xx, kref);
5832
5833 mutex_lock(&qla_cs84xx_mutex);
5834 list_del(&cs84xx->list);
5835 mutex_unlock(&qla_cs84xx_mutex);
5836 kfree(cs84xx);
5837}
5838
5839void
e315cd28 5840qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5841{
e315cd28 5842 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5843 if (ha->cs84xx)
5844 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5845}
5846
5847static int
e315cd28 5848qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5849{
5850 int rval;
5851 uint16_t status[2];
e315cd28 5852 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5853
5854 mutex_lock(&ha->cs84xx->fw_update_mutex);
5855
e315cd28 5856 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5857
5858 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5859
5860 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5861 QLA_SUCCESS;
5862}
3a03eb79
AV		 5863
5864/* 81XX Support **************************************************************/
5865
5866int
5867qla81xx_nvram_config(scsi_qla_host_t *vha)
5868{
5869 int rval;
5870 struct init_cb_81xx *icb;
5871 struct nvram_81xx *nv;
5872 uint32_t *dptr;
5873 uint8_t *dptr1, *dptr2;
5874 uint32_t chksum;
5875 uint16_t cnt;
5876 struct qla_hw_data *ha = vha->hw;
5877
5878 rval = QLA_SUCCESS;
5879 icb = (struct init_cb_81xx *)ha->init_cb;
5880 nv = ha->nvram;
5881
5882 /* Determine NVRAM starting address. */
5883 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5884 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5885 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5886 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5887
5888 /* Get VPD data into cache */
5889 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5890 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5891 ha->vpd_size);
3a03eb79
AV		 5892
5893 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5894 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5895 ha->nvram_size);
3d79038f 5896 dptr = (uint32_t *)nv;
3a03eb79
AV		 5897 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5898 chksum += le32_to_cpu(*dptr++);
5899
7c3df132
SK		 5900 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5901 "Contents of NVRAM:\n");
5902 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5903 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5904
5905 /* Bad NVRAM data, set defaults parameters. */
5906 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5907 || nv->id[3] != ' ' ||
5908 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5909 /* Reset NVRAM data. */
7c3df132 5910 ql_log(ql_log_info, vha, 0x0073,
9e336520 5911 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5912 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5913 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5914 ql_log(ql_log_info, vha, 0x0074,
5915 "Falling back to functioning (yet invalid -- WWPN) "
5916 "defaults.\n");
3a03eb79
AV		 5917
5918 /*
5919 * Set default initialization control block.
5920 */
5921 memset(nv, 0, ha->nvram_size);
5922 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5923 nv->version = __constant_cpu_to_le16(ICB_VERSION);
98aee70d 5924 nv->frame_payload_size = 2048;
3a03eb79
AV		 5925 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5926 nv->exchange_count = __constant_cpu_to_le16(0);
5927 nv->port_name[0] = 0x21;
f73cb695 5928 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 5929 nv->port_name[2] = 0x00;
5930 nv->port_name[3] = 0xe0;
5931 nv->port_name[4] = 0x8b;
5932 nv->port_name[5] = 0x1c;
5933 nv->port_name[6] = 0x55;
5934 nv->port_name[7] = 0x86;
5935 nv->node_name[0] = 0x20;
5936 nv->node_name[1] = 0x00;
5937 nv->node_name[2] = 0x00;
5938 nv->node_name[3] = 0xe0;
5939 nv->node_name[4] = 0x8b;
5940 nv->node_name[5] = 0x1c;
5941 nv->node_name[6] = 0x55;
5942 nv->node_name[7] = 0x86;
5943 nv->login_retry_count = __constant_cpu_to_le16(8);
5944 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5945 nv->login_timeout = __constant_cpu_to_le16(0);
5946 nv->firmware_options_1 =
5947 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5948 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5949 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5950 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5951 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5952 nv->efi_parameters = __constant_cpu_to_le32(0);
5953 nv->reset_delay = 5;
5954 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5955 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5956 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5957 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5958 nv->enode_mac[1] = 0xC0;
5959 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5960 nv->enode_mac[3] = 0x04;
5961 nv->enode_mac[4] = 0x05;
f73cb695 5962 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5963
5964 rval = 1;
5965 }
5966
9e522cd8
AE		 5967 if (IS_T10_PI_CAPABLE(ha))
5968 nv->frame_payload_size &= ~7;
5969
aa230bc5
AE		 5970 qlt_81xx_config_nvram_stage1(vha, nv);
5971
3a03eb79 5972 /* Reset Initialization control block */
773120e4 5973 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5974
5975 /* Copy 1st segment. */
5976 dptr1 = (uint8_t *)icb;
5977 dptr2 = (uint8_t *)&nv->version;
5978 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5979 while (cnt--)
5980 *dptr1++ = *dptr2++;
5981
5982 icb->login_retry_count = nv->login_retry_count;
5983
5984 /* Copy 2nd segment. */
5985 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5986 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5987 cnt = (uint8_t *)&icb->reserved_5 -
5988 (uint8_t *)&icb->interrupt_delay_timer;
5989 while (cnt--)
5990 *dptr1++ = *dptr2++;
5991
5992 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5993 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5994 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5995 icb->enode_mac[0] = 0x00;
5996 icb->enode_mac[1] = 0xC0;
5997 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5998 icb->enode_mac[3] = 0x04;
5999 icb->enode_mac[4] = 0x05;
f73cb695 6000 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 6001 }
6002
b64b0e8f
AV		 6003 /* Use extended-initialization control block. */
6004 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
6005
3a03eb79
AV		 6006 /*
6007 * Setup driver NVRAM options.
6008 */
6009 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 6010 "QLE8XXX");
3a03eb79 6011
aa230bc5
AE		 6012 qlt_81xx_config_nvram_stage2(vha, icb);
6013
3a03eb79
AV		 6014 /* Use alternate WWN? */
6015 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
6016 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6017 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6018 }
6019
6020 /* Prepare nodename */
6021 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
6022 /*
6023 * Firmware will apply the following mask if the nodename was
6024 * not provided.
6025 */
6026 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6027 icb->node_name[0] &= 0xF0;
6028 }
6029
6030 /* Set host adapter parameters. */
6031 ha->flags.disable_risc_code_load = 0;
6032 ha->flags.enable_lip_reset = 0;
6033 ha->flags.enable_lip_full_login =
6034 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6035 ha->flags.enable_target_reset =
6036 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
6037 ha->flags.enable_led_scheme = 0;
6038 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
6039
6040 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6041 (BIT_6 | BIT_5 | BIT_4)) >> 4;
6042
6043 /* save HBA serial number */
6044 ha->serial0 = icb->port_name[5];
6045 ha->serial1 = icb->port_name[6];
6046 ha->serial2 = icb->port_name[7];
6047 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6048 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
6049
6050 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
6051
6052 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6053
6054 /* Set minimum login_timeout to 4 seconds. */
6055 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6056 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6057 if (le16_to_cpu(nv->login_timeout) < 4)
6058 nv->login_timeout = __constant_cpu_to_le16(4);
6059 ha->login_timeout = le16_to_cpu(nv->login_timeout);
6060 icb->login_timeout = nv->login_timeout;
6061
6062 /* Set minimum RATOV to 100 tenths of a second. */
6063 ha->r_a_tov = 100;
6064
6065 ha->loop_reset_delay = nv->reset_delay;
6066
6067 /* Link Down Timeout = 0:
6068 *
7ec0effd 6069 * When Port Down timer expires we will start returning
3a03eb79
AV		 6070 * I/O's to OS with "DID_NO_CONNECT".
6071 *
6072 * Link Down Timeout != 0:
6073 *
6074 * The driver waits for the link to come up after link down
6075 * before returning I/Os to OS with "DID_NO_CONNECT".
6076 */
6077 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6078 ha->loop_down_abort_time =
6079 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6080 } else {
6081 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6082 ha->loop_down_abort_time =
6083 (LOOP_DOWN_TIME - ha->link_down_timeout);
6084 }
6085
6086 /* Need enough time to try and get the port back. */
6087 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6088 if (qlport_down_retry)
6089 ha->port_down_retry_count = qlport_down_retry;
6090
6091 /* Set login_retry_count */
6092 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6093 if (ha->port_down_retry_count ==
6094 le16_to_cpu(nv->port_down_retry_count) &&
6095 ha->port_down_retry_count > 3)
6096 ha->login_retry_count = ha->port_down_retry_count;
6097 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6098 ha->login_retry_count = ha->port_down_retry_count;
6099 if (ql2xloginretrycount)
6100 ha->login_retry_count = ql2xloginretrycount;
6101
6246b8a1 6102 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 6103 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
6246b8a1
GM		 6104 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
6105
3a03eb79
AV		 6106 /* Enable ZIO. */
6107 if (!vha->flags.init_done) {
6108 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6109 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6110 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6111 le16_to_cpu(icb->interrupt_delay_timer): 2;
6112 }
6113 icb->firmware_options_2 &= __constant_cpu_to_le32(
6114 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6115 vha->flags.process_response_queue = 0;
6116 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6117 ha->zio_mode = QLA_ZIO_MODE_6;
6118
7c3df132 6119 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6120 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6121 ha->zio_mode,
6122 ha->zio_timer * 100);
3a03eb79
AV		 6123
6124 icb->firmware_options_2 |= cpu_to_le32(
6125 (uint32_t)ha->zio_mode);
6126 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6127 vha->flags.process_response_queue = 1;
6128 }
6129
6130 if (rval) {
7c3df132
SK		 6131 ql_log(ql_log_warn, vha, 0x0076,
6132 "NVRAM configuration failed.\n");
3a03eb79
AV		 6133 }
6134 return (rval);
6135}
6136
a9083016
GM		 6137int
6138qla82xx_restart_isp(scsi_qla_host_t *vha)
6139{
6140 int status, rval;
a9083016
GM		 6141 struct qla_hw_data *ha = vha->hw;
6142 struct req_que *req = ha->req_q_map[0];
6143 struct rsp_que *rsp = ha->rsp_q_map[0];
6144 struct scsi_qla_host *vp;
feafb7b1 6145 unsigned long flags;
a9083016
GM		 6146
6147 status = qla2x00_init_rings(vha);
6148 if (!status) {
6149 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6150 ha->flags.chip_reset_done = 1;
6151
6152 status = qla2x00_fw_ready(vha);
6153 if (!status) {
a9083016
GM		 6154 /* Issue a marker after FW becomes ready. */
6155 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 6156 vha->flags.online = 1;
7108b76e 6157 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 6158 }
6159
6160 /* if no cable then assume it's good */
6161 if ((vha->device_flags & DFLG_NO_CABLE))
6162 status = 0;
a9083016
GM		 6163 }
6164
6165 if (!status) {
6166 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6167
6168 if (!atomic_read(&vha->loop_down_timer)) {
6169 /*
6170 * Issue marker command only when we are going
6171 * to start the I/O .
6172 */
6173 vha->marker_needed = 1;
6174 }
6175
a9083016
GM		 6176 ha->isp_ops->enable_intrs(ha);
6177
6178 ha->isp_abort_cnt = 0;
6179 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6180
53296788 6181 /* Update the firmware version */
3173167f 6182 status = qla82xx_check_md_needed(vha);
53296788 6183
a9083016
GM		 6184 if (ha->fce) {
6185 ha->flags.fce_enabled = 1;
6186 memset(ha->fce, 0,
6187 fce_calc_size(ha->fce_bufs));
6188 rval = qla2x00_enable_fce_trace(vha,
6189 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6190 &ha->fce_bufs);
6191 if (rval) {
cfb0919c 6192 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6193 "Unable to reinitialize FCE (%d).\n",
6194 rval);
a9083016
GM		 6195 ha->flags.fce_enabled = 0;
6196 }
6197 }
6198
6199 if (ha->eft) {
6200 memset(ha->eft, 0, EFT_SIZE);
6201 rval = qla2x00_enable_eft_trace(vha,
6202 ha->eft_dma, EFT_NUM_BUFFERS);
6203 if (rval) {
cfb0919c 6204 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6205 "Unable to reinitialize EFT (%d).\n",
6206 rval);
a9083016
GM		 6207 }
6208 }
a9083016
GM		 6209 }
6210
6211 if (!status) {
cfb0919c 6212 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6213 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6214
6215 spin_lock_irqsave(&ha->vport_slock, flags);
6216 list_for_each_entry(vp, &ha->vp_list, list) {
6217 if (vp->vp_idx) {
6218 atomic_inc(&vp->vref_count);
6219 spin_unlock_irqrestore(&ha->vport_slock, flags);
6220
a9083016 6221 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6222
6223 spin_lock_irqsave(&ha->vport_slock, flags);
6224 atomic_dec(&vp->vref_count);
6225 }
a9083016 6226 }
feafb7b1
AE		 6227 spin_unlock_irqrestore(&ha->vport_slock, flags);
6228
a9083016 6229 } else {
cfb0919c 6230 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6231 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6232 }
6233
6234 return status;
6235}
6236
3a03eb79 6237void
ae97c91e 6238qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6239{
ae97c91e
AV		 6240 struct qla_hw_data *ha = vha->hw;
6241
6242 if (!ql2xetsenable)
6243 return;
6244
6245 /* Enable ETS Burst. */
6246 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6247 ha->fw_options[2] |= BIT_9;
6248 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6249}
09ff701a
SR		 6250
6251/*
6252 * qla24xx_get_fcp_prio
6253 * Gets the fcp cmd priority value for the logged in port.
6254 * Looks for a match of the port descriptors within
6255 * each of the fcp prio config entries. If a match is found,
6256 * the tag (priority) value is returned.
6257 *
6258 * Input:
21090cbe 6259 * vha = scsi host structure pointer.
09ff701a
SR		 6260 * fcport = port structure pointer.
6261 *
6262 * Return:
6c452a45 6263 * non-zero (if found)
f28a0a96 6264 * -1 (if not found)
09ff701a
SR		 6265 *
6266 * Context:
6267 * Kernel context
6268 */
f28a0a96 6269static int
09ff701a
SR		 6270qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6271{
6272 int i, entries;
6273 uint8_t pid_match, wwn_match;
f28a0a96 6274 int priority;
09ff701a
SR		 6275 uint32_t pid1, pid2;
6276 uint64_t wwn1, wwn2;
6277 struct qla_fcp_prio_entry *pri_entry;
6278 struct qla_hw_data *ha = vha->hw;
6279
6280 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6281 return -1;
09ff701a 6282
f28a0a96 6283 priority = -1;
09ff701a
SR		 6284 entries = ha->fcp_prio_cfg->num_entries;
6285 pri_entry = &ha->fcp_prio_cfg->entry[0];
6286
6287 for (i = 0; i < entries; i++) {
6288 pid_match = wwn_match = 0;
6289
6290 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6291 pri_entry++;
6292 continue;
6293 }
6294
6295 /* check source pid for a match */
6296 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6297 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6298 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6299 if (pid1 == INVALID_PORT_ID)
6300 pid_match++;
6301 else if (pid1 == pid2)
6302 pid_match++;
6303 }
6304
6305 /* check destination pid for a match */
6306 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6307 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6308 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6309 if (pid1 == INVALID_PORT_ID)
6310 pid_match++;
6311 else if (pid1 == pid2)
6312 pid_match++;
6313 }
6314
6315 /* check source WWN for a match */
6316 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6317 wwn1 = wwn_to_u64(vha->port_name);
6318 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6319 if (wwn2 == (uint64_t)-1)
6320 wwn_match++;
6321 else if (wwn1 == wwn2)
6322 wwn_match++;
6323 }
6324
6325 /* check destination WWN for a match */
6326 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6327 wwn1 = wwn_to_u64(fcport->port_name);
6328 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6329 if (wwn2 == (uint64_t)-1)
6330 wwn_match++;
6331 else if (wwn1 == wwn2)
6332 wwn_match++;
6333 }
6334
6335 if (pid_match == 2 || wwn_match == 2) {
6336 /* Found a matching entry */
6337 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6338 priority = pri_entry->tag;
6339 break;
6340 }
6341
6342 pri_entry++;
6343 }
6344
6345 return priority;
6346}
6347
6348/*
6349 * qla24xx_update_fcport_fcp_prio
6350 * Activates fcp priority for the logged in fc port
6351 *
6352 * Input:
21090cbe 6353 * vha = scsi host structure pointer.
09ff701a
SR		 6354 * fcp = port structure pointer.
6355 *
6356 * Return:
6357 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6358 *
6359 * Context:
6360 * Kernel context.
6361 */
6362int
21090cbe 6363qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6364{
6365 int ret;
f28a0a96 6366 int priority;
09ff701a
SR		 6367 uint16_t mb[5];
6368
21090cbe
MI		 6369 if (fcport->port_type != FCT_TARGET ||
6370 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6371 return QLA_FUNCTION_FAILED;
6372
21090cbe 6373 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6374 if (priority < 0)
6375 return QLA_FUNCTION_FAILED;
6376
7ec0effd 6377 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6378 fcport->fcp_prio = priority & 0xf;
6379 return QLA_SUCCESS;
6380 }
6381
21090cbe 6382 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6383 if (ret == QLA_SUCCESS) {
6384 if (fcport->fcp_prio != priority)
6385 ql_dbg(ql_dbg_user, vha, 0x709e,
6386 "Updated FCP_CMND priority - value=%d loop_id=%d "
6387 "port_id=%02x%02x%02x.\n", priority,
6388 fcport->loop_id, fcport->d_id.b.domain,
6389 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6390 fcport->fcp_prio = priority & 0xf;
cfb0919c 6391 } else
7c3df132 6392 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6393 "Unable to update FCP_CMND priority - ret=0x%x for "
6394 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6395 fcport->d_id.b.domain, fcport->d_id.b.area,
6396 fcport->d_id.b.al_pa);
09ff701a
SR		 6397 return ret;
6398}
6399
6400/*
6401 * qla24xx_update_all_fcp_prio
6402 * Activates fcp priority for all the logged in ports
6403 *
6404 * Input:
6405 * ha = adapter block pointer.
6406 *
6407 * Return:
6408 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6409 *
6410 * Context:
6411 * Kernel context.
6412 */
6413int
6414qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6415{
6416 int ret;
6417 fc_port_t *fcport;
6418
6419 ret = QLA_FUNCTION_FAILED;
6420 /* We need to set priority for all logged in ports */
6421 list_for_each_entry(fcport, &vha->vp_fcports, list)
6422 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6423
6424 return ret;
6425}
Linux 6.x block layer and io_uring tree(s)