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[PATCH] libata-hp-prep: use __ata_scsi_find_dev()
[linux-2.6-block.git] / drivers / scsi / libata-core.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
3373efd8
TH		 64static unsigned int ata_dev_init_params(struct ata_device *dev,
65 u16 heads, u16 sectors);
66static unsigned int ata_dev_set_xfermode(struct ata_device *dev);
67static void ata_dev_xfermask(struct ata_device *dev);
1da177e4
LT		 68
69static unsigned int ata_unique_id = 1;
70static struct workqueue_struct *ata_wq;
71
418dc1f5 72int atapi_enabled = 1;
1623c81e
JG		 73module_param(atapi_enabled, int, 0444);
74MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
75
95de719a
AL		 76int atapi_dmadir = 0;
77module_param(atapi_dmadir, int, 0444);
78MODULE_PARM_DESC(atapi_dmadir, "Enable ATAPI DMADIR bridge support (0=off, 1=on)");
79
c3c013a2
JG		 80int libata_fua = 0;
81module_param_named(fua, libata_fua, int, 0444);
82MODULE_PARM_DESC(fua, "FUA support (0=off, 1=on)");
83
1da177e4
LT		 84MODULE_AUTHOR("Jeff Garzik");
85MODULE_DESCRIPTION("Library module for ATA devices");
86MODULE_LICENSE("GPL");
87MODULE_VERSION(DRV_VERSION);
88
0baab86b 89
1da177e4
LT		 90/**
91 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
92 * @tf: Taskfile to convert
93 * @fis: Buffer into which data will output
94 * @pmp: Port multiplier port
95 *
96 * Converts a standard ATA taskfile to a Serial ATA
97 * FIS structure (Register - Host to Device).
98 *
99 * LOCKING:
100 * Inherited from caller.
101 */
102
057ace5e 103void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 104{
105 fis[0] = 0x27; /* Register - Host to Device FIS */
106 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
107 bit 7 indicates Command FIS */
108 fis[2] = tf->command;
109 fis[3] = tf->feature;
110
111 fis[4] = tf->lbal;
112 fis[5] = tf->lbam;
113 fis[6] = tf->lbah;
114 fis[7] = tf->device;
115
116 fis[8] = tf->hob_lbal;
117 fis[9] = tf->hob_lbam;
118 fis[10] = tf->hob_lbah;
119 fis[11] = tf->hob_feature;
120
121 fis[12] = tf->nsect;
122 fis[13] = tf->hob_nsect;
123 fis[14] = 0;
124 fis[15] = tf->ctl;
125
126 fis[16] = 0;
127 fis[17] = 0;
128 fis[18] = 0;
129 fis[19] = 0;
130}
131
132/**
133 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
134 * @fis: Buffer from which data will be input
135 * @tf: Taskfile to output
136 *
e12a1be6 137 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 138 *
139 * LOCKING:
140 * Inherited from caller.
141 */
142
057ace5e 143void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 144{
145 tf->command = fis[2]; /* status */
146 tf->feature = fis[3]; /* error */
147
148 tf->lbal = fis[4];
149 tf->lbam = fis[5];
150 tf->lbah = fis[6];
151 tf->device = fis[7];
152
153 tf->hob_lbal = fis[8];
154 tf->hob_lbam = fis[9];
155 tf->hob_lbah = fis[10];
156
157 tf->nsect = fis[12];
158 tf->hob_nsect = fis[13];
159}
160
8cbd6df1
AL		 161static const u8 ata_rw_cmds[] = {
162 /* pio multi */
163 ATA_CMD_READ_MULTI,
164 ATA_CMD_WRITE_MULTI,
165 ATA_CMD_READ_MULTI_EXT,
166 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH		 167 0,
168 0,
169 0,
170 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL		 171 /* pio */
172 ATA_CMD_PIO_READ,
173 ATA_CMD_PIO_WRITE,
174 ATA_CMD_PIO_READ_EXT,
175 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH		 176 0,
177 0,
178 0,
179 0,
8cbd6df1
AL		 180 /* dma */
181 ATA_CMD_READ,
182 ATA_CMD_WRITE,
183 ATA_CMD_READ_EXT,
9a3dccc4
TH		 184 ATA_CMD_WRITE_EXT,
185 0,
186 0,
187 0,
188 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 189};
1da177e4
LT		 190
191/**
8cbd6df1
AL		 192 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
193 * @qc: command to examine and configure
1da177e4 194 *
2e9edbf8 195 * Examine the device configuration and tf->flags to calculate
8cbd6df1 196 * the proper read/write commands and protocol to use.
1da177e4
LT		 197 *
198 * LOCKING:
199 * caller.
200 */
9a3dccc4 201int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 202{
8cbd6df1
AL		 203 struct ata_taskfile *tf = &qc->tf;
204 struct ata_device *dev = qc->dev;
9a3dccc4 205 u8 cmd;
1da177e4 206
9a3dccc4 207 int index, fua, lba48, write;
2e9edbf8 208
9a3dccc4 209 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL		 210 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
211 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 212
8cbd6df1
AL		 213 if (dev->flags & ATA_DFLAG_PIO) {
214 tf->protocol = ATA_PROT_PIO;
9a3dccc4 215 index = dev->multi_count ? 0 : 8;
8d238e01
AC		 216 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
217 /* Unable to use DMA due to host limitation */
218 tf->protocol = ATA_PROT_PIO;
0565c26d 219 index = dev->multi_count ? 0 : 8;
8cbd6df1
AL		 220 } else {
221 tf->protocol = ATA_PROT_DMA;
9a3dccc4 222 index = 16;
8cbd6df1 223 }
1da177e4 224
9a3dccc4
TH		 225 cmd = ata_rw_cmds[index + fua + lba48 + write];
226 if (cmd) {
227 tf->command = cmd;
228 return 0;
229 }
230 return -1;
1da177e4
LT		 231}
232
cb95d562
TH		 233/**
234 * ata_pack_xfermask - Pack pio, mwdma and udma masks into xfer_mask
235 * @pio_mask: pio_mask
236 * @mwdma_mask: mwdma_mask
237 * @udma_mask: udma_mask
238 *
239 * Pack @pio_mask, @mwdma_mask and @udma_mask into a single
240 * unsigned int xfer_mask.
241 *
242 * LOCKING:
243 * None.
244 *
245 * RETURNS:
246 * Packed xfer_mask.
247 */
248static unsigned int ata_pack_xfermask(unsigned int pio_mask,
249 unsigned int mwdma_mask,
250 unsigned int udma_mask)
251{
252 return ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
253 ((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
254 ((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
255}
256
c0489e4e
TH		 257/**
258 * ata_unpack_xfermask - Unpack xfer_mask into pio, mwdma and udma masks
259 * @xfer_mask: xfer_mask to unpack
260 * @pio_mask: resulting pio_mask
261 * @mwdma_mask: resulting mwdma_mask
262 * @udma_mask: resulting udma_mask
263 *
264 * Unpack @xfer_mask into @pio_mask, @mwdma_mask and @udma_mask.
265 * Any NULL distination masks will be ignored.
266 */
267static void ata_unpack_xfermask(unsigned int xfer_mask,
268 unsigned int *pio_mask,
269 unsigned int *mwdma_mask,
270 unsigned int *udma_mask)
271{
272 if (pio_mask)
273 *pio_mask = (xfer_mask & ATA_MASK_PIO) >> ATA_SHIFT_PIO;
274 if (mwdma_mask)
275 *mwdma_mask = (xfer_mask & ATA_MASK_MWDMA) >> ATA_SHIFT_MWDMA;
276 if (udma_mask)
277 *udma_mask = (xfer_mask & ATA_MASK_UDMA) >> ATA_SHIFT_UDMA;
278}
279
cb95d562 280static const struct ata_xfer_ent {
be9a50c8 281 int shift, bits;
cb95d562
TH		 282 u8 base;
283} ata_xfer_tbl[] = {
284 { ATA_SHIFT_PIO, ATA_BITS_PIO, XFER_PIO_0 },
285 { ATA_SHIFT_MWDMA, ATA_BITS_MWDMA, XFER_MW_DMA_0 },
286 { ATA_SHIFT_UDMA, ATA_BITS_UDMA, XFER_UDMA_0 },
287 { -1, },
288};
289
290/**
291 * ata_xfer_mask2mode - Find matching XFER_* for the given xfer_mask
292 * @xfer_mask: xfer_mask of interest
293 *
294 * Return matching XFER_* value for @xfer_mask. Only the highest
295 * bit of @xfer_mask is considered.
296 *
297 * LOCKING:
298 * None.
299 *
300 * RETURNS:
301 * Matching XFER_* value, 0 if no match found.
302 */
303static u8 ata_xfer_mask2mode(unsigned int xfer_mask)
304{
305 int highbit = fls(xfer_mask) - 1;
306 const struct ata_xfer_ent *ent;
307
308 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
309 if (highbit >= ent->shift && highbit < ent->shift + ent->bits)
310 return ent->base + highbit - ent->shift;
311 return 0;
312}
313
314/**
315 * ata_xfer_mode2mask - Find matching xfer_mask for XFER_*
316 * @xfer_mode: XFER_* of interest
317 *
318 * Return matching xfer_mask for @xfer_mode.
319 *
320 * LOCKING:
321 * None.
322 *
323 * RETURNS:
324 * Matching xfer_mask, 0 if no match found.
325 */
326static unsigned int ata_xfer_mode2mask(u8 xfer_mode)
327{
328 const struct ata_xfer_ent *ent;
329
330 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
331 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
332 return 1 << (ent->shift + xfer_mode - ent->base);
333 return 0;
334}
335
336/**
337 * ata_xfer_mode2shift - Find matching xfer_shift for XFER_*
338 * @xfer_mode: XFER_* of interest
339 *
340 * Return matching xfer_shift for @xfer_mode.
341 *
342 * LOCKING:
343 * None.
344 *
345 * RETURNS:
346 * Matching xfer_shift, -1 if no match found.
347 */
348static int ata_xfer_mode2shift(unsigned int xfer_mode)
349{
350 const struct ata_xfer_ent *ent;
351
352 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
353 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
354 return ent->shift;
355 return -1;
356}
357
1da177e4 358/**
1da7b0d0
TH		 359 * ata_mode_string - convert xfer_mask to string
360 * @xfer_mask: mask of bits supported; only highest bit counts.
1da177e4
LT		 361 *
362 * Determine string which represents the highest speed
1da7b0d0 363 * (highest bit in @modemask).
1da177e4
LT		 364 *
365 * LOCKING:
366 * None.
367 *
368 * RETURNS:
369 * Constant C string representing highest speed listed in
1da7b0d0 370 * @mode_mask, or the constant C string "<n/a>".
1da177e4 371 */
1da7b0d0 372static const char *ata_mode_string(unsigned int xfer_mask)
1da177e4 373{
75f554bc
TH		 374 static const char * const xfer_mode_str[] = {
375 "PIO0",
376 "PIO1",
377 "PIO2",
378 "PIO3",
379 "PIO4",
380 "MWDMA0",
381 "MWDMA1",
382 "MWDMA2",
383 "UDMA/16",
384 "UDMA/25",
385 "UDMA/33",
386 "UDMA/44",
387 "UDMA/66",
388 "UDMA/100",
389 "UDMA/133",
390 "UDMA7",
391 };
1da7b0d0 392 int highbit;
1da177e4 393
1da7b0d0
TH		 394 highbit = fls(xfer_mask) - 1;
395 if (highbit >= 0 && highbit < ARRAY_SIZE(xfer_mode_str))
396 return xfer_mode_str[highbit];
1da177e4 397 return "<n/a>";
1da177e4
LT		 398}
399
4c360c81
TH		 400static const char *sata_spd_string(unsigned int spd)
401{
402 static const char * const spd_str[] = {
403 "1.5 Gbps",
404 "3.0 Gbps",
405 };
406
407 if (spd == 0 || (spd - 1) >= ARRAY_SIZE(spd_str))
408 return "<unknown>";
409 return spd_str[spd - 1];
410}
411
3373efd8 412void ata_dev_disable(struct ata_device *dev)
0b8efb0a 413{
e1211e3f 414 if (ata_dev_enabled(dev)) {
f15a1daf 415 ata_dev_printk(dev, KERN_WARNING, "disabled\n");
0b8efb0a
TH		 416 dev->class++;
417 }
418}
419
1da177e4
LT		 420/**
421 * ata_pio_devchk - PATA device presence detection
422 * @ap: ATA channel to examine
423 * @device: Device to examine (starting at zero)
424 *
425 * This technique was originally described in
426 * Hale Landis's ATADRVR (www.ata-atapi.com), and
427 * later found its way into the ATA/ATAPI spec.
428 *
429 * Write a pattern to the ATA shadow registers,
430 * and if a device is present, it will respond by
431 * correctly storing and echoing back the
432 * ATA shadow register contents.
433 *
434 * LOCKING:
435 * caller.
436 */
437
438static unsigned int ata_pio_devchk(struct ata_port *ap,
439 unsigned int device)
440{
441 struct ata_ioports *ioaddr = &ap->ioaddr;
442 u8 nsect, lbal;
443
444 ap->ops->dev_select(ap, device);
445
446 outb(0x55, ioaddr->nsect_addr);
447 outb(0xaa, ioaddr->lbal_addr);
448
449 outb(0xaa, ioaddr->nsect_addr);
450 outb(0x55, ioaddr->lbal_addr);
451
452 outb(0x55, ioaddr->nsect_addr);
453 outb(0xaa, ioaddr->lbal_addr);
454
455 nsect = inb(ioaddr->nsect_addr);
456 lbal = inb(ioaddr->lbal_addr);
457
458 if ((nsect == 0x55) && (lbal == 0xaa))
459 return 1; /* we found a device */
460
461 return 0; /* nothing found */
462}
463
464/**
465 * ata_mmio_devchk - PATA device presence detection
466 * @ap: ATA channel to examine
467 * @device: Device to examine (starting at zero)
468 *
469 * This technique was originally described in
470 * Hale Landis's ATADRVR (www.ata-atapi.com), and
471 * later found its way into the ATA/ATAPI spec.
472 *
473 * Write a pattern to the ATA shadow registers,
474 * and if a device is present, it will respond by
475 * correctly storing and echoing back the
476 * ATA shadow register contents.
477 *
478 * LOCKING:
479 * caller.
480 */
481
482static unsigned int ata_mmio_devchk(struct ata_port *ap,
483 unsigned int device)
484{
485 struct ata_ioports *ioaddr = &ap->ioaddr;
486 u8 nsect, lbal;
487
488 ap->ops->dev_select(ap, device);
489
490 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
491 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
492
493 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
494 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
495
496 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
497 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
498
499 nsect = readb((void __iomem *) ioaddr->nsect_addr);
500 lbal = readb((void __iomem *) ioaddr->lbal_addr);
501
502 if ((nsect == 0x55) && (lbal == 0xaa))
503 return 1; /* we found a device */
504
505 return 0; /* nothing found */
506}
507
508/**
509 * ata_devchk - PATA device presence detection
510 * @ap: ATA channel to examine
511 * @device: Device to examine (starting at zero)
512 *
513 * Dispatch ATA device presence detection, depending
514 * on whether we are using PIO or MMIO to talk to the
515 * ATA shadow registers.
516 *
517 * LOCKING:
518 * caller.
519 */
520
521static unsigned int ata_devchk(struct ata_port *ap,
522 unsigned int device)
523{
524 if (ap->flags & ATA_FLAG_MMIO)
525 return ata_mmio_devchk(ap, device);
526 return ata_pio_devchk(ap, device);
527}
528
529/**
530 * ata_dev_classify - determine device type based on ATA-spec signature
531 * @tf: ATA taskfile register set for device to be identified
532 *
533 * Determine from taskfile register contents whether a device is
534 * ATA or ATAPI, as per "Signature and persistence" section
535 * of ATA/PI spec (volume 1, sect 5.14).
536 *
537 * LOCKING:
538 * None.
539 *
540 * RETURNS:
541 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
542 * the event of failure.
543 */
544
057ace5e 545unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 546{
547 /* Apple's open source Darwin code hints that some devices only
548 * put a proper signature into the LBA mid/high registers,
549 * So, we only check those. It's sufficient for uniqueness.
550 */
551
552 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
553 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
554 DPRINTK("found ATA device by sig\n");
555 return ATA_DEV_ATA;
556 }
557
558 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
559 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
560 DPRINTK("found ATAPI device by sig\n");
561 return ATA_DEV_ATAPI;
562 }
563
564 DPRINTK("unknown device\n");
565 return ATA_DEV_UNKNOWN;
566}
567
568/**
569 * ata_dev_try_classify - Parse returned ATA device signature
570 * @ap: ATA channel to examine
571 * @device: Device to examine (starting at zero)
b4dc7623 572 * @r_err: Value of error register on completion
1da177e4
LT		 573 *
574 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
575 * an ATA/ATAPI-defined set of values is placed in the ATA
576 * shadow registers, indicating the results of device detection
577 * and diagnostics.
578 *
579 * Select the ATA device, and read the values from the ATA shadow
580 * registers. Then parse according to the Error register value,
581 * and the spec-defined values examined by ata_dev_classify().
582 *
583 * LOCKING:
584 * caller.
b4dc7623
TH		 585 *
586 * RETURNS:
587 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT		 588 */
589
b4dc7623
TH		 590static unsigned int
591ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 592{
1da177e4
LT		 593 struct ata_taskfile tf;
594 unsigned int class;
595 u8 err;
596
597 ap->ops->dev_select(ap, device);
598
599 memset(&tf, 0, sizeof(tf));
600
1da177e4 601 ap->ops->tf_read(ap, &tf);
0169e284 602 err = tf.feature;
b4dc7623
TH		 603 if (r_err)
604 *r_err = err;
1da177e4
LT		 605
606 /* see if device passed diags */
607 if (err == 1)
608 /* do nothing */ ;
609 else if ((device == 0) && (err == 0x81))
610 /* do nothing */ ;
611 else
b4dc7623 612 return ATA_DEV_NONE;
1da177e4 613
b4dc7623 614 /* determine if device is ATA or ATAPI */
1da177e4 615 class = ata_dev_classify(&tf);
b4dc7623 616
1da177e4 617 if (class == ATA_DEV_UNKNOWN)
b4dc7623 618 return ATA_DEV_NONE;
1da177e4 619 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH		 620 return ATA_DEV_NONE;
621 return class;
1da177e4
LT		 622}
623
624/**
6a62a04d 625 * ata_id_string - Convert IDENTIFY DEVICE page into string
1da177e4
LT		 626 * @id: IDENTIFY DEVICE results we will examine
627 * @s: string into which data is output
628 * @ofs: offset into identify device page
629 * @len: length of string to return. must be an even number.
630 *
631 * The strings in the IDENTIFY DEVICE page are broken up into
632 * 16-bit chunks. Run through the string, and output each
633 * 8-bit chunk linearly, regardless of platform.
634 *
635 * LOCKING:
636 * caller.
637 */
638
6a62a04d
TH		 639void ata_id_string(const u16 *id, unsigned char *s,
640 unsigned int ofs, unsigned int len)
1da177e4
LT		 641{
642 unsigned int c;
643
644 while (len > 0) {
645 c = id[ofs] >> 8;
646 *s = c;
647 s++;
648
649 c = id[ofs] & 0xff;
650 *s = c;
651 s++;
652
653 ofs++;
654 len -= 2;
655 }
656}
657
0e949ff3 658/**
6a62a04d 659 * ata_id_c_string - Convert IDENTIFY DEVICE page into C string
0e949ff3
TH		 660 * @id: IDENTIFY DEVICE results we will examine
661 * @s: string into which data is output
662 * @ofs: offset into identify device page
663 * @len: length of string to return. must be an odd number.
664 *
6a62a04d 665 * This function is identical to ata_id_string except that it
0e949ff3
TH		 666 * trims trailing spaces and terminates the resulting string with
667 * null. @len must be actual maximum length (even number) + 1.
668 *
669 * LOCKING:
670 * caller.
671 */
6a62a04d
TH		 672void ata_id_c_string(const u16 *id, unsigned char *s,
673 unsigned int ofs, unsigned int len)
0e949ff3
TH		 674{
675 unsigned char *p;
676
677 WARN_ON(!(len & 1));
678
6a62a04d 679 ata_id_string(id, s, ofs, len - 1);
0e949ff3
TH		 680
681 p = s + strnlen(s, len - 1);
682 while (p > s && p[-1] == ' ')
683 p--;
684 *p = '\0';
685}
0baab86b 686
2940740b
TH		 687static u64 ata_id_n_sectors(const u16 *id)
688{
689 if (ata_id_has_lba(id)) {
690 if (ata_id_has_lba48(id))
691 return ata_id_u64(id, 100);
692 else
693 return ata_id_u32(id, 60);
694 } else {
695 if (ata_id_current_chs_valid(id))
696 return ata_id_u32(id, 57);
697 else
698 return id[1] * id[3] * id[6];
699 }
700}
701
0baab86b
EF		 702/**
703 * ata_noop_dev_select - Select device 0/1 on ATA bus
704 * @ap: ATA channel to manipulate
705 * @device: ATA device (numbered from zero) to select
706 *
707 * This function performs no actual function.
708 *
709 * May be used as the dev_select() entry in ata_port_operations.
710 *
711 * LOCKING:
712 * caller.
713 */
1da177e4
LT		 714void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
715{
716}
717
0baab86b 718
1da177e4
LT		 719/**
720 * ata_std_dev_select - Select device 0/1 on ATA bus
721 * @ap: ATA channel to manipulate
722 * @device: ATA device (numbered from zero) to select
723 *
724 * Use the method defined in the ATA specification to
725 * make either device 0, or device 1, active on the
0baab86b
EF		 726 * ATA channel. Works with both PIO and MMIO.
727 *
728 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 729 *
730 * LOCKING:
731 * caller.
732 */
733
734void ata_std_dev_select (struct ata_port *ap, unsigned int device)
735{
736 u8 tmp;
737
738 if (device == 0)
739 tmp = ATA_DEVICE_OBS;
740 else
741 tmp = ATA_DEVICE_OBS | ATA_DEV1;
742
743 if (ap->flags & ATA_FLAG_MMIO) {
744 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
745 } else {
746 outb(tmp, ap->ioaddr.device_addr);
747 }
748 ata_pause(ap); /* needed; also flushes, for mmio */
749}
750
751/**
752 * ata_dev_select - Select device 0/1 on ATA bus
753 * @ap: ATA channel to manipulate
754 * @device: ATA device (numbered from zero) to select
755 * @wait: non-zero to wait for Status register BSY bit to clear
756 * @can_sleep: non-zero if context allows sleeping
757 *
758 * Use the method defined in the ATA specification to
759 * make either device 0, or device 1, active on the
760 * ATA channel.
761 *
762 * This is a high-level version of ata_std_dev_select(),
763 * which additionally provides the services of inserting
764 * the proper pauses and status polling, where needed.
765 *
766 * LOCKING:
767 * caller.
768 */
769
770void ata_dev_select(struct ata_port *ap, unsigned int device,
771 unsigned int wait, unsigned int can_sleep)
772{
773 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
774 ap->id, device, wait);
775
776 if (wait)
777 ata_wait_idle(ap);
778
779 ap->ops->dev_select(ap, device);
780
781 if (wait) {
782 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
783 msleep(150);
784 ata_wait_idle(ap);
785 }
786}
787
788/**
789 * ata_dump_id - IDENTIFY DEVICE info debugging output
0bd3300a 790 * @id: IDENTIFY DEVICE page to dump
1da177e4 791 *
0bd3300a
TH		 792 * Dump selected 16-bit words from the given IDENTIFY DEVICE
793 * page.
1da177e4
LT		 794 *
795 * LOCKING:
796 * caller.
797 */
798
0bd3300a 799static inline void ata_dump_id(const u16 *id)
1da177e4
LT		 800{
801 DPRINTK("49==0x%04x "
802 "53==0x%04x "
803 "63==0x%04x "
804 "64==0x%04x "
805 "75==0x%04x \n",
0bd3300a
TH		 806 id[49],
807 id[53],
808 id[63],
809 id[64],
810 id[75]);
1da177e4
LT		 811 DPRINTK("80==0x%04x "
812 "81==0x%04x "
813 "82==0x%04x "
814 "83==0x%04x "
815 "84==0x%04x \n",
0bd3300a
TH		 816 id[80],
817 id[81],
818 id[82],
819 id[83],
820 id[84]);
1da177e4
LT		 821 DPRINTK("88==0x%04x "
822 "93==0x%04x\n",
0bd3300a
TH		 823 id[88],
824 id[93]);
1da177e4
LT		 825}
826
cb95d562
TH		 827/**
828 * ata_id_xfermask - Compute xfermask from the given IDENTIFY data
829 * @id: IDENTIFY data to compute xfer mask from
830 *
831 * Compute the xfermask for this device. This is not as trivial
832 * as it seems if we must consider early devices correctly.
833 *
834 * FIXME: pre IDE drive timing (do we care ?).
835 *
836 * LOCKING:
837 * None.
838 *
839 * RETURNS:
840 * Computed xfermask
841 */
842static unsigned int ata_id_xfermask(const u16 *id)
843{
844 unsigned int pio_mask, mwdma_mask, udma_mask;
845
846 /* Usual case. Word 53 indicates word 64 is valid */
847 if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
848 pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
849 pio_mask <<= 3;
850 pio_mask |= 0x7;
851 } else {
852 /* If word 64 isn't valid then Word 51 high byte holds
853 * the PIO timing number for the maximum. Turn it into
854 * a mask.
855 */
856 pio_mask = (2 << (id[ATA_ID_OLD_PIO_MODES] & 0xFF)) - 1 ;
857
858 /* But wait.. there's more. Design your standards by
859 * committee and you too can get a free iordy field to
860 * process. However its the speeds not the modes that
861 * are supported... Note drivers using the timing API
862 * will get this right anyway
863 */
864 }
865
866 mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
fb21f0d0
TH		 867
868 udma_mask = 0;
869 if (id[ATA_ID_FIELD_VALID] & (1 << 2))
870 udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
cb95d562
TH		 871
872 return ata_pack_xfermask(pio_mask, mwdma_mask, udma_mask);
873}
874
86e45b6b
TH		 875/**
876 * ata_port_queue_task - Queue port_task
877 * @ap: The ata_port to queue port_task for
e2a7f77a
RD		 878 * @fn: workqueue function to be scheduled
879 * @data: data value to pass to workqueue function
880 * @delay: delay time for workqueue function
86e45b6b
TH		 881 *
882 * Schedule @fn(@data) for execution after @delay jiffies using
883 * port_task. There is one port_task per port and it's the
884 * user(low level driver)'s responsibility to make sure that only
885 * one task is active at any given time.
886 *
887 * libata core layer takes care of synchronization between
888 * port_task and EH. ata_port_queue_task() may be ignored for EH
889 * synchronization.
890 *
891 * LOCKING:
892 * Inherited from caller.
893 */
894void ata_port_queue_task(struct ata_port *ap, void (*fn)(void *), void *data,
895 unsigned long delay)
896{
897 int rc;
898
2e755f68 899 if (ap->flags & ATA_FLAG_FLUSH_PORT_TASK)
86e45b6b
TH		 900 return;
901
902 PREPARE_WORK(&ap->port_task, fn, data);
903
904 if (!delay)
905 rc = queue_work(ata_wq, &ap->port_task);
906 else
907 rc = queue_delayed_work(ata_wq, &ap->port_task, delay);
908
909 /* rc == 0 means that another user is using port task */
910 WARN_ON(rc == 0);
911}
912
913/**
914 * ata_port_flush_task - Flush port_task
915 * @ap: The ata_port to flush port_task for
916 *
917 * After this function completes, port_task is guranteed not to
918 * be running or scheduled.
919 *
920 * LOCKING:
921 * Kernel thread context (may sleep)
922 */
923void ata_port_flush_task(struct ata_port *ap)
924{
925 unsigned long flags;
926
927 DPRINTK("ENTER\n");
928
929 spin_lock_irqsave(&ap->host_set->lock, flags);
2e755f68 930 ap->flags |= ATA_FLAG_FLUSH_PORT_TASK;
86e45b6b
TH		 931 spin_unlock_irqrestore(&ap->host_set->lock, flags);
932
933 DPRINTK("flush #1\n");
934 flush_workqueue(ata_wq);
935
936 /*
937 * At this point, if a task is running, it's guaranteed to see
938 * the FLUSH flag; thus, it will never queue pio tasks again.
939 * Cancel and flush.
940 */
941 if (!cancel_delayed_work(&ap->port_task)) {
942 DPRINTK("flush #2\n");
943 flush_workqueue(ata_wq);
944 }
945
946 spin_lock_irqsave(&ap->host_set->lock, flags);
2e755f68 947 ap->flags &= ~ATA_FLAG_FLUSH_PORT_TASK;
86e45b6b
TH		 948 spin_unlock_irqrestore(&ap->host_set->lock, flags);
949
950 DPRINTK("EXIT\n");
951}
952
77853bf2 953void ata_qc_complete_internal(struct ata_queued_cmd *qc)
a2a7a662 954{
77853bf2 955 struct completion *waiting = qc->private_data;
a2a7a662 956
a2a7a662 957 complete(waiting);
a2a7a662
TH		 958}
959
960/**
961 * ata_exec_internal - execute libata internal command
a2a7a662
TH		 962 * @dev: Device to which the command is sent
963 * @tf: Taskfile registers for the command and the result
d69cf37d 964 * @cdb: CDB for packet command
a2a7a662
TH		 965 * @dma_dir: Data tranfer direction of the command
966 * @buf: Data buffer of the command
967 * @buflen: Length of data buffer
968 *
969 * Executes libata internal command with timeout. @tf contains
970 * command on entry and result on return. Timeout and error
971 * conditions are reported via return value. No recovery action
972 * is taken after a command times out. It's caller's duty to
973 * clean up after timeout.
974 *
975 * LOCKING:
976 * None. Should be called with kernel context, might sleep.
977 */
978
3373efd8 979unsigned ata_exec_internal(struct ata_device *dev,
1ad8e7f9
TH		 980 struct ata_taskfile *tf, const u8 *cdb,
981 int dma_dir, void *buf, unsigned int buflen)
a2a7a662 982{
3373efd8 983 struct ata_port *ap = dev->ap;
a2a7a662
TH		 984 u8 command = tf->command;
985 struct ata_queued_cmd *qc;
2ab7db1f 986 unsigned int tag, preempted_tag;
dedaf2b0 987 u32 preempted_sactive, preempted_qc_active;
a2a7a662
TH		 988 DECLARE_COMPLETION(wait);
989 unsigned long flags;
77853bf2 990 unsigned int err_mask;
d95a717f 991 int rc;
a2a7a662
TH		 992
993 spin_lock_irqsave(&ap->host_set->lock, flags);
994
e3180499
TH		 995 /* no internal command while frozen */
996 if (ap->flags & ATA_FLAG_FROZEN) {
997 spin_unlock_irqrestore(&ap->host_set->lock, flags);
998 return AC_ERR_SYSTEM;
999 }
1000
2ab7db1f 1001 /* initialize internal qc */
a2a7a662 1002
2ab7db1f
TH		 1003 /* XXX: Tag 0 is used for drivers with legacy EH as some
1004 * drivers choke if any other tag is given. This breaks
1005 * ata_tag_internal() test for those drivers. Don't use new
1006 * EH stuff without converting to it.
1007 */
1008 if (ap->ops->error_handler)
1009 tag = ATA_TAG_INTERNAL;
1010 else
1011 tag = 0;
1012
6cec4a39 1013 if (test_and_set_bit(tag, &ap->qc_allocated))
2ab7db1f 1014 BUG();
f69499f4 1015 qc = __ata_qc_from_tag(ap, tag);
2ab7db1f
TH		 1016
1017 qc->tag = tag;
1018 qc->scsicmd = NULL;
1019 qc->ap = ap;
1020 qc->dev = dev;
1021 ata_qc_reinit(qc);
1022
1023 preempted_tag = ap->active_tag;
dedaf2b0
TH		 1024 preempted_sactive = ap->sactive;
1025 preempted_qc_active = ap->qc_active;
2ab7db1f 1026 ap->active_tag = ATA_TAG_POISON;
dedaf2b0
TH		 1027 ap->sactive = 0;
1028 ap->qc_active = 0;
2ab7db1f
TH		 1029
1030 /* prepare & issue qc */
a2a7a662 1031 qc->tf = *tf;
d69cf37d
TH		 1032 if (cdb)
1033 memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
e61e0672 1034 qc->flags |= ATA_QCFLAG_RESULT_TF;
a2a7a662
TH		 1035 qc->dma_dir = dma_dir;
1036 if (dma_dir != DMA_NONE) {
1037 ata_sg_init_one(qc, buf, buflen);
1038 qc->nsect = buflen / ATA_SECT_SIZE;
1039 }
1040
77853bf2 1041 qc->private_data = &wait;
a2a7a662
TH		 1042 qc->complete_fn = ata_qc_complete_internal;
1043
8e0e694a 1044 ata_qc_issue(qc);
a2a7a662
TH		 1045
1046 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1047
d95a717f
TH		 1048 rc = wait_for_completion_timeout(&wait, ATA_TMOUT_INTERNAL);
1049
1050 ata_port_flush_task(ap);
41ade50c 1051
d95a717f 1052 if (!rc) {
a2a7a662
TH		 1053 spin_lock_irqsave(&ap->host_set->lock, flags);
1054
1055 /* We're racing with irq here. If we lose, the
1056 * following test prevents us from completing the qc
d95a717f
TH		 1057 * twice. If we win, the port is frozen and will be
1058 * cleaned up by ->post_internal_cmd().
a2a7a662 1059 */
77853bf2 1060 if (qc->flags & ATA_QCFLAG_ACTIVE) {
d95a717f
TH		 1061 qc->err_mask |= AC_ERR_TIMEOUT;
1062
1063 if (ap->ops->error_handler)
1064 ata_port_freeze(ap);
1065 else
1066 ata_qc_complete(qc);
f15a1daf
TH		 1067
1068 ata_dev_printk(dev, KERN_WARNING,
1069 "qc timeout (cmd 0x%x)\n", command);
a2a7a662
TH		 1070 }
1071
1072 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1073 }
1074
d95a717f
TH		 1075 /* do post_internal_cmd */
1076 if (ap->ops->post_internal_cmd)
1077 ap->ops->post_internal_cmd(qc);
1078
1079 if (qc->flags & ATA_QCFLAG_FAILED && !qc->err_mask) {
1080 ata_dev_printk(dev, KERN_WARNING, "zero err_mask for failed "
1081 "internal command, assuming AC_ERR_OTHER\n");
1082 qc->err_mask |= AC_ERR_OTHER;
1083 }
1084
15869303
TH		 1085 /* finish up */
1086 spin_lock_irqsave(&ap->host_set->lock, flags);
1087
e61e0672 1088 *tf = qc->result_tf;
77853bf2
TH		 1089 err_mask = qc->err_mask;
1090
1091 ata_qc_free(qc);
2ab7db1f 1092 ap->active_tag = preempted_tag;
dedaf2b0
TH		 1093 ap->sactive = preempted_sactive;
1094 ap->qc_active = preempted_qc_active;
77853bf2 1095
1f7dd3e9
TH		 1096 /* XXX - Some LLDDs (sata_mv) disable port on command failure.
1097 * Until those drivers are fixed, we detect the condition
1098 * here, fail the command with AC_ERR_SYSTEM and reenable the
1099 * port.
1100 *
1101 * Note that this doesn't change any behavior as internal
1102 * command failure results in disabling the device in the
1103 * higher layer for LLDDs without new reset/EH callbacks.
1104 *
1105 * Kill the following code as soon as those drivers are fixed.
1106 */
198e0fed 1107 if (ap->flags & ATA_FLAG_DISABLED) {
1f7dd3e9
TH		 1108 err_mask |= AC_ERR_SYSTEM;
1109 ata_port_probe(ap);
1110 }
1111
15869303
TH		 1112 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1113
77853bf2 1114 return err_mask;
a2a7a662
TH		 1115}
1116
1bc4ccff
AC		 1117/**
1118 * ata_pio_need_iordy - check if iordy needed
1119 * @adev: ATA device
1120 *
1121 * Check if the current speed of the device requires IORDY. Used
1122 * by various controllers for chip configuration.
1123 */
1124
1125unsigned int ata_pio_need_iordy(const struct ata_device *adev)
1126{
1127 int pio;
1128 int speed = adev->pio_mode - XFER_PIO_0;
1129
1130 if (speed < 2)
1131 return 0;
1132 if (speed > 2)
1133 return 1;
2e9edbf8 1134
1bc4ccff
AC		 1135 /* If we have no drive specific rule, then PIO 2 is non IORDY */
1136
1137 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
1138 pio = adev->id[ATA_ID_EIDE_PIO];
1139 /* Is the speed faster than the drive allows non IORDY ? */
1140 if (pio) {
1141 /* This is cycle times not frequency - watch the logic! */
1142 if (pio > 240) /* PIO2 is 240nS per cycle */
1143 return 1;
1144 return 0;
1145 }
1146 }
1147 return 0;
1148}
1149
1da177e4 1150/**
49016aca 1151 * ata_dev_read_id - Read ID data from the specified device
49016aca
TH		 1152 * @dev: target device
1153 * @p_class: pointer to class of the target device (may be changed)
1154 * @post_reset: is this read ID post-reset?
fe635c7e 1155 * @id: buffer to read IDENTIFY data into
1da177e4 1156 *
49016aca
TH		 1157 * Read ID data from the specified device. ATA_CMD_ID_ATA is
1158 * performed on ATA devices and ATA_CMD_ID_ATAPI on ATAPI
aec5c3c1
TH		 1159 * devices. This function also issues ATA_CMD_INIT_DEV_PARAMS
1160 * for pre-ATA4 drives.
1da177e4
LT		 1161 *
1162 * LOCKING:
49016aca
TH		 1163 * Kernel thread context (may sleep)
1164 *
1165 * RETURNS:
1166 * 0 on success, -errno otherwise.
1da177e4 1167 */
3373efd8
TH		 1168static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
1169 int post_reset, u16 *id)
1da177e4 1170{
3373efd8 1171 struct ata_port *ap = dev->ap;
49016aca 1172 unsigned int class = *p_class;
a0123703 1173 struct ata_taskfile tf;
49016aca
TH		 1174 unsigned int err_mask = 0;
1175 const char *reason;
1176 int rc;
1da177e4 1177
49016aca 1178 DPRINTK("ENTER, host %u, dev %u\n", ap->id, dev->devno);
1da177e4 1179
49016aca 1180 ata_dev_select(ap, dev->devno, 1, 1); /* select device 0/1 */
1da177e4 1181
49016aca 1182 retry:
3373efd8 1183 ata_tf_init(dev, &tf);
a0123703 1184
49016aca
TH		 1185 switch (class) {
1186 case ATA_DEV_ATA:
a0123703 1187 tf.command = ATA_CMD_ID_ATA;
49016aca
TH		 1188 break;
1189 case ATA_DEV_ATAPI:
a0123703 1190 tf.command = ATA_CMD_ID_ATAPI;
49016aca
TH		 1191 break;
1192 default:
1193 rc = -ENODEV;
1194 reason = "unsupported class";
1195 goto err_out;
1da177e4
LT		 1196 }
1197
a0123703 1198 tf.protocol = ATA_PROT_PIO;
1da177e4 1199
3373efd8 1200 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
49016aca 1201 id, sizeof(id[0]) * ATA_ID_WORDS);
a0123703 1202 if (err_mask) {
49016aca
TH		 1203 rc = -EIO;
1204 reason = "I/O error";
1da177e4
LT		 1205 goto err_out;
1206 }
1207
49016aca 1208 swap_buf_le16(id, ATA_ID_WORDS);
1da177e4 1209
49016aca 1210 /* sanity check */
692785e7 1211 if ((class == ATA_DEV_ATA) != (ata_id_is_ata(id) | ata_id_is_cfa(id))) {
49016aca
TH		 1212 rc = -EINVAL;
1213 reason = "device reports illegal type";
1214 goto err_out;
1215 }
1216
1217 if (post_reset && class == ATA_DEV_ATA) {
1218 /*
1219 * The exact sequence expected by certain pre-ATA4 drives is:
1220 * SRST RESET
1221 * IDENTIFY
1222 * INITIALIZE DEVICE PARAMETERS
1223 * anything else..
1224 * Some drives were very specific about that exact sequence.
1225 */
1226 if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
3373efd8 1227 err_mask = ata_dev_init_params(dev, id[3], id[6]);
49016aca
TH		 1228 if (err_mask) {
1229 rc = -EIO;
1230 reason = "INIT_DEV_PARAMS failed";
1231 goto err_out;
1232 }
1233
1234 /* current CHS translation info (id[53-58]) might be
1235 * changed. reread the identify device info.
1236 */
1237 post_reset = 0;
1238 goto retry;
1239 }
1240 }
1241
1242 *p_class = class;
fe635c7e 1243
49016aca
TH		 1244 return 0;
1245
1246 err_out:
f15a1daf
TH		 1247 ata_dev_printk(dev, KERN_WARNING, "failed to IDENTIFY "
1248 "(%s, err_mask=0x%x)\n", reason, err_mask);
49016aca
TH		 1249 return rc;
1250}
1251
3373efd8 1252static inline u8 ata_dev_knobble(struct ata_device *dev)
4b2f3ede 1253{
3373efd8 1254 return ((dev->ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
4b2f3ede
TH		 1255}
1256
a6e6ce8e
TH		 1257static void ata_dev_config_ncq(struct ata_device *dev,
1258 char *desc, size_t desc_sz)
1259{
1260 struct ata_port *ap = dev->ap;
1261 int hdepth = 0, ddepth = ata_id_queue_depth(dev->id);
1262
1263 if (!ata_id_has_ncq(dev->id)) {
1264 desc[0] = '\0';
1265 return;
1266 }
1267
1268 if (ap->flags & ATA_FLAG_NCQ) {
1269 hdepth = min(ap->host->can_queue, ATA_MAX_QUEUE - 1);
1270 dev->flags |= ATA_DFLAG_NCQ;
1271 }
1272
1273 if (hdepth >= ddepth)
1274 snprintf(desc, desc_sz, "NCQ (depth %d)", ddepth);
1275 else
1276 snprintf(desc, desc_sz, "NCQ (depth %d/%d)", hdepth, ddepth);
1277}
1278
49016aca 1279/**
ffeae418 1280 * ata_dev_configure - Configure the specified ATA/ATAPI device
ffeae418 1281 * @dev: Target device to configure
4c2d721a 1282 * @print_info: Enable device info printout
ffeae418
TH		 1283 *
1284 * Configure @dev according to @dev->id. Generic and low-level
1285 * driver specific fixups are also applied.
49016aca
TH		 1286 *
1287 * LOCKING:
ffeae418
TH		 1288 * Kernel thread context (may sleep)
1289 *
1290 * RETURNS:
1291 * 0 on success, -errno otherwise
49016aca 1292 */
3373efd8 1293static int ata_dev_configure(struct ata_device *dev, int print_info)
49016aca 1294{
3373efd8 1295 struct ata_port *ap = dev->ap;
1148c3a7 1296 const u16 *id = dev->id;
ff8854b2 1297 unsigned int xfer_mask;
49016aca
TH		 1298 int i, rc;
1299
e1211e3f 1300 if (!ata_dev_enabled(dev)) {
49016aca 1301 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
ffeae418
TH		 1302 ap->id, dev->devno);
1303 return 0;
49016aca
TH		 1304 }
1305
ffeae418 1306 DPRINTK("ENTER, host %u, dev %u\n", ap->id, dev->devno);
1da177e4 1307
c39f5ebe
TH		 1308 /* print device capabilities */
1309 if (print_info)
f15a1daf
TH		 1310 ata_dev_printk(dev, KERN_DEBUG, "cfg 49:%04x 82:%04x 83:%04x "
1311 "84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
1312 id[49], id[82], id[83], id[84],
1313 id[85], id[86], id[87], id[88]);
c39f5ebe 1314
208a9933 1315 /* initialize to-be-configured parameters */
ea1dd4e1 1316 dev->flags &= ~ATA_DFLAG_CFG_MASK;
208a9933
TH		 1317 dev->max_sectors = 0;
1318 dev->cdb_len = 0;
1319 dev->n_sectors = 0;
1320 dev->cylinders = 0;
1321 dev->heads = 0;
1322 dev->sectors = 0;
1323
1da177e4
LT		 1324 /*
1325 * common ATA, ATAPI feature tests
1326 */
1327
ff8854b2 1328 /* find max transfer mode; for printk only */
1148c3a7 1329 xfer_mask = ata_id_xfermask(id);
1da177e4 1330
1148c3a7 1331 ata_dump_id(id);
1da177e4
LT		 1332
1333 /* ATA-specific feature tests */
1334 if (dev->class == ATA_DEV_ATA) {
1148c3a7 1335 dev->n_sectors = ata_id_n_sectors(id);
2940740b 1336
1148c3a7 1337 if (ata_id_has_lba(id)) {
4c2d721a 1338 const char *lba_desc;
a6e6ce8e 1339 char ncq_desc[20];
8bf62ece 1340
4c2d721a
TH		 1341 lba_desc = "LBA";
1342 dev->flags |= ATA_DFLAG_LBA;
1148c3a7 1343 if (ata_id_has_lba48(id)) {
8bf62ece 1344 dev->flags |= ATA_DFLAG_LBA48;
4c2d721a
TH		 1345 lba_desc = "LBA48";
1346 }
8bf62ece 1347
a6e6ce8e
TH		 1348 /* config NCQ */
1349 ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
1350
8bf62ece 1351 /* print device info to dmesg */
4c2d721a 1352 if (print_info)
f15a1daf 1353 ata_dev_printk(dev, KERN_INFO, "ATA-%d, "
a6e6ce8e 1354 "max %s, %Lu sectors: %s %s\n",
f15a1daf
TH		 1355 ata_id_major_version(id),
1356 ata_mode_string(xfer_mask),
1357 (unsigned long long)dev->n_sectors,
a6e6ce8e 1358 lba_desc, ncq_desc);
ffeae418 1359 } else {
8bf62ece
AL		 1360 /* CHS */
1361
1362 /* Default translation */
1148c3a7
TH		 1363 dev->cylinders = id[1];
1364 dev->heads = id[3];
1365 dev->sectors = id[6];
8bf62ece 1366
1148c3a7 1367 if (ata_id_current_chs_valid(id)) {
8bf62ece 1368 /* Current CHS translation is valid. */
1148c3a7
TH		 1369 dev->cylinders = id[54];
1370 dev->heads = id[55];
1371 dev->sectors = id[56];
8bf62ece
AL		 1372 }
1373
1374 /* print device info to dmesg */
4c2d721a 1375 if (print_info)
f15a1daf
TH		 1376 ata_dev_printk(dev, KERN_INFO, "ATA-%d, "
1377 "max %s, %Lu sectors: CHS %u/%u/%u\n",
1378 ata_id_major_version(id),
1379 ata_mode_string(xfer_mask),
1380 (unsigned long long)dev->n_sectors,
1381 dev->cylinders, dev->heads, dev->sectors);
1da177e4
LT		 1382 }
1383
07f6f7d0
AL		 1384 if (dev->id[59] & 0x100) {
1385 dev->multi_count = dev->id[59] & 0xff;
1386 DPRINTK("ata%u: dev %u multi count %u\n",
999bb6f4 1387 ap->id, dev->devno, dev->multi_count);
07f6f7d0
AL		 1388 }
1389
6e7846e9 1390 dev->cdb_len = 16;
1da177e4
LT		 1391 }
1392
1393 /* ATAPI-specific feature tests */
2c13b7ce 1394 else if (dev->class == ATA_DEV_ATAPI) {
08a556db
AL		 1395 char *cdb_intr_string = "";
1396
1148c3a7 1397 rc = atapi_cdb_len(id);
1da177e4 1398 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
f15a1daf
TH		 1399 ata_dev_printk(dev, KERN_WARNING,
1400 "unsupported CDB len\n");
ffeae418 1401 rc = -EINVAL;
1da177e4
LT		 1402 goto err_out_nosup;
1403 }
6e7846e9 1404 dev->cdb_len = (unsigned int) rc;
1da177e4 1405
08a556db 1406 if (ata_id_cdb_intr(dev->id)) {
312f7da2 1407 dev->flags |= ATA_DFLAG_CDB_INTR;
08a556db
AL		 1408 cdb_intr_string = ", CDB intr";
1409 }
312f7da2 1410
1da177e4 1411 /* print device info to dmesg */
4c2d721a 1412 if (print_info)
12436c30
TH		 1413 ata_dev_printk(dev, KERN_INFO, "ATAPI, max %s%s\n",
1414 ata_mode_string(xfer_mask),
1415 cdb_intr_string);
1da177e4
LT		 1416 }
1417
6e7846e9
TH		 1418 ap->host->max_cmd_len = 0;
1419 for (i = 0; i < ATA_MAX_DEVICES; i++)
1420 ap->host->max_cmd_len = max_t(unsigned int,
1421 ap->host->max_cmd_len,
1422 ap->device[i].cdb_len);
1423
4b2f3ede 1424 /* limit bridge transfers to udma5, 200 sectors */
3373efd8 1425 if (ata_dev_knobble(dev)) {
4c2d721a 1426 if (print_info)
f15a1daf
TH		 1427 ata_dev_printk(dev, KERN_INFO,
1428 "applying bridge limits\n");
5a529139 1429 dev->udma_mask &= ATA_UDMA5;
4b2f3ede
TH		 1430 dev->max_sectors = ATA_MAX_SECTORS;
1431 }
1432
1433 if (ap->ops->dev_config)
1434 ap->ops->dev_config(ap, dev);
1435
1da177e4 1436 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
ffeae418 1437 return 0;
1da177e4
LT		 1438
1439err_out_nosup:
1da177e4 1440 DPRINTK("EXIT, err\n");
ffeae418 1441 return rc;
1da177e4
LT		 1442}
1443
1444/**
1445 * ata_bus_probe - Reset and probe ATA bus
1446 * @ap: Bus to probe
1447 *
0cba632b
JG		 1448 * Master ATA bus probing function. Initiates a hardware-dependent
1449 * bus reset, then attempts to identify any devices found on
1450 * the bus.
1451 *
1da177e4 1452 * LOCKING:
0cba632b 1453 * PCI/etc. bus probe sem.
1da177e4
LT		 1454 *
1455 * RETURNS:
96072e69 1456 * Zero on success, negative errno otherwise.
1da177e4
LT		 1457 */
1458
1459static int ata_bus_probe(struct ata_port *ap)
1460{
28ca5c57 1461 unsigned int classes[ATA_MAX_DEVICES];
14d2bac1
TH		 1462 int tries[ATA_MAX_DEVICES];
1463 int i, rc, down_xfermask;
e82cbdb9 1464 struct ata_device *dev;
1da177e4 1465
28ca5c57 1466 ata_port_probe(ap);
c19ba8af 1467
14d2bac1
TH		 1468 for (i = 0; i < ATA_MAX_DEVICES; i++)
1469 tries[i] = ATA_PROBE_MAX_TRIES;
1470
1471 retry:
1472 down_xfermask = 0;
1473
2044470c
TH		 1474 /* reset and determine device classes */
1475 for (i = 0; i < ATA_MAX_DEVICES; i++)
1476 classes[i] = ATA_DEV_UNKNOWN;
2061a47a 1477
2044470c 1478 if (ap->ops->probe_reset) {
c19ba8af 1479 rc = ap->ops->probe_reset(ap, classes);
28ca5c57 1480 if (rc) {
f15a1daf
TH		 1481 ata_port_printk(ap, KERN_ERR,
1482 "reset failed (errno=%d)\n", rc);
28ca5c57 1483 return rc;
c19ba8af 1484 }
28ca5c57 1485 } else {
c19ba8af
TH		 1486 ap->ops->phy_reset(ap);
1487
f8c2c420
TH		 1488 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1489 if (!(ap->flags & ATA_FLAG_DISABLED))
28ca5c57 1490 classes[i] = ap->device[i].class;
f8c2c420
TH		 1491 ap->device[i].class = ATA_DEV_UNKNOWN;
1492 }
2044470c 1493
28ca5c57
TH		 1494 ata_port_probe(ap);
1495 }
1da177e4 1496
2044470c
TH		 1497 for (i = 0; i < ATA_MAX_DEVICES; i++)
1498 if (classes[i] == ATA_DEV_UNKNOWN)
1499 classes[i] = ATA_DEV_NONE;
1500
b6079ca4
AC		 1501 /* after the reset the device state is PIO 0 and the controller
1502 state is undefined. Record the mode */
1503
1504 for (i = 0; i < ATA_MAX_DEVICES; i++)
1505 ap->device[i].pio_mode = XFER_PIO_0;
1506
28ca5c57 1507 /* read IDENTIFY page and configure devices */
1da177e4 1508 for (i = 0; i < ATA_MAX_DEVICES; i++) {
e82cbdb9 1509 dev = &ap->device[i];
28ca5c57 1510
ec573755
TH		 1511 if (tries[i])
1512 dev->class = classes[i];
ffeae418 1513
14d2bac1 1514 if (!ata_dev_enabled(dev))
ffeae418 1515 continue;
ffeae418 1516
3373efd8 1517 rc = ata_dev_read_id(dev, &dev->class, 1, dev->id);
14d2bac1
TH		 1518 if (rc)
1519 goto fail;
1520
3373efd8 1521 rc = ata_dev_configure(dev, 1);
14d2bac1
TH		 1522 if (rc)
1523 goto fail;
1da177e4
LT		 1524 }
1525
e82cbdb9 1526 /* configure transfer mode */
3adcebb2 1527 rc = ata_set_mode(ap, &dev);
51713d35
TH		 1528 if (rc) {
1529 down_xfermask = 1;
1530 goto fail;
e82cbdb9 1531 }
1da177e4 1532
e82cbdb9
TH		 1533 for (i = 0; i < ATA_MAX_DEVICES; i++)
1534 if (ata_dev_enabled(&ap->device[i]))
1535 return 0;
1da177e4 1536
e82cbdb9
TH		 1537 /* no device present, disable port */
1538 ata_port_disable(ap);
1da177e4 1539 ap->ops->port_disable(ap);
96072e69 1540 return -ENODEV;
14d2bac1
TH		 1541
1542 fail:
1543 switch (rc) {
1544 case -EINVAL:
1545 case -ENODEV:
1546 tries[dev->devno] = 0;
1547 break;
1548 case -EIO:
3c567b7d 1549 sata_down_spd_limit(ap);
14d2bac1
TH		 1550 /* fall through */
1551 default:
1552 tries[dev->devno]--;
1553 if (down_xfermask &&
3373efd8 1554 ata_down_xfermask_limit(dev, tries[dev->devno] == 1))
14d2bac1
TH		 1555 tries[dev->devno] = 0;
1556 }
1557
ec573755 1558 if (!tries[dev->devno]) {
3373efd8
TH		 1559 ata_down_xfermask_limit(dev, 1);
1560 ata_dev_disable(dev);
ec573755
TH		 1561 }
1562
14d2bac1 1563 goto retry;
1da177e4
LT		 1564}
1565
1566/**
0cba632b
JG		 1567 * ata_port_probe - Mark port as enabled
1568 * @ap: Port for which we indicate enablement
1da177e4 1569 *
0cba632b
JG		 1570 * Modify @ap data structure such that the system
1571 * thinks that the entire port is enabled.
1572 *
1573 * LOCKING: host_set lock, or some other form of
1574 * serialization.
1da177e4
LT		 1575 */
1576
1577void ata_port_probe(struct ata_port *ap)
1578{
198e0fed 1579 ap->flags &= ~ATA_FLAG_DISABLED;
1da177e4
LT		 1580}
1581
3be680b7
TH		 1582/**
1583 * sata_print_link_status - Print SATA link status
1584 * @ap: SATA port to printk link status about
1585 *
1586 * This function prints link speed and status of a SATA link.
1587 *
1588 * LOCKING:
1589 * None.
1590 */
1591static void sata_print_link_status(struct ata_port *ap)
1592{
6d5f9732 1593 u32 sstatus, scontrol, tmp;
3be680b7 1594
81952c54 1595 if (sata_scr_read(ap, SCR_STATUS, &sstatus))
3be680b7 1596 return;
81952c54 1597 sata_scr_read(ap, SCR_CONTROL, &scontrol);
3be680b7 1598
81952c54 1599 if (ata_port_online(ap)) {
3be680b7 1600 tmp = (sstatus >> 4) & 0xf;
f15a1daf
TH		 1601 ata_port_printk(ap, KERN_INFO,
1602 "SATA link up %s (SStatus %X SControl %X)\n",
1603 sata_spd_string(tmp), sstatus, scontrol);
3be680b7 1604 } else {
f15a1daf
TH		 1605 ata_port_printk(ap, KERN_INFO,
1606 "SATA link down (SStatus %X SControl %X)\n",
1607 sstatus, scontrol);
3be680b7
TH		 1608 }
1609}
1610
1da177e4 1611/**
780a87f7
JG		 1612 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1613 * @ap: SATA port associated with target SATA PHY.
1da177e4 1614 *
780a87f7
JG		 1615 * This function issues commands to standard SATA Sxxx
1616 * PHY registers, to wake up the phy (and device), and
1617 * clear any reset condition.
1da177e4
LT		 1618 *
1619 * LOCKING:
0cba632b 1620 * PCI/etc. bus probe sem.
1da177e4
LT		 1621 *
1622 */
1623void __sata_phy_reset(struct ata_port *ap)
1624{
1625 u32 sstatus;
1626 unsigned long timeout = jiffies + (HZ * 5);
1627
1628 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e 1629 /* issue phy wake/reset */
81952c54 1630 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1631 /* Couldn't find anything in SATA I/II specs, but
1632 * AHCI-1.1 10.4.2 says at least 1 ms. */
1633 mdelay(1);
1da177e4 1634 }
81952c54
TH		 1635 /* phy wake/clear reset */
1636 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1da177e4
LT		 1637
1638 /* wait for phy to become ready, if necessary */
1639 do {
1640 msleep(200);
81952c54 1641 sata_scr_read(ap, SCR_STATUS, &sstatus);
1da177e4
LT		 1642 if ((sstatus & 0xf) != 1)
1643 break;
1644 } while (time_before(jiffies, timeout));
1645
3be680b7
TH		 1646 /* print link status */
1647 sata_print_link_status(ap);
656563e3 1648
3be680b7 1649 /* TODO: phy layer with polling, timeouts, etc. */
81952c54 1650 if (!ata_port_offline(ap))
1da177e4 1651 ata_port_probe(ap);
3be680b7 1652 else
1da177e4 1653 ata_port_disable(ap);
1da177e4 1654
198e0fed 1655 if (ap->flags & ATA_FLAG_DISABLED)
1da177e4
LT		 1656 return;
1657
1658 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1659 ata_port_disable(ap);
1660 return;
1661 }
1662
1663 ap->cbl = ATA_CBL_SATA;
1664}
1665
1666/**
780a87f7
JG		 1667 * sata_phy_reset - Reset SATA bus.
1668 * @ap: SATA port associated with target SATA PHY.
1da177e4 1669 *
780a87f7
JG		 1670 * This function resets the SATA bus, and then probes
1671 * the bus for devices.
1da177e4
LT		 1672 *
1673 * LOCKING:
0cba632b 1674 * PCI/etc. bus probe sem.
1da177e4
LT		 1675 *
1676 */
1677void sata_phy_reset(struct ata_port *ap)
1678{
1679 __sata_phy_reset(ap);
198e0fed 1680 if (ap->flags & ATA_FLAG_DISABLED)
1da177e4
LT		 1681 return;
1682 ata_bus_reset(ap);
1683}
1684
ebdfca6e
AC		 1685/**
1686 * ata_dev_pair - return other device on cable
ebdfca6e
AC		 1687 * @adev: device
1688 *
1689 * Obtain the other device on the same cable, or if none is
1690 * present NULL is returned
1691 */
2e9edbf8 1692
3373efd8 1693struct ata_device *ata_dev_pair(struct ata_device *adev)
ebdfca6e 1694{
3373efd8 1695 struct ata_port *ap = adev->ap;
ebdfca6e 1696 struct ata_device *pair = &ap->device[1 - adev->devno];
e1211e3f 1697 if (!ata_dev_enabled(pair))
ebdfca6e
AC		 1698 return NULL;
1699 return pair;
1700}
1701
1da177e4 1702/**
780a87f7
JG		 1703 * ata_port_disable - Disable port.
1704 * @ap: Port to be disabled.
1da177e4 1705 *
780a87f7
JG		 1706 * Modify @ap data structure such that the system
1707 * thinks that the entire port is disabled, and should
1708 * never attempt to probe or communicate with devices
1709 * on this port.
1710 *
1711 * LOCKING: host_set lock, or some other form of
1712 * serialization.
1da177e4
LT		 1713 */
1714
1715void ata_port_disable(struct ata_port *ap)
1716{
1717 ap->device[0].class = ATA_DEV_NONE;
1718 ap->device[1].class = ATA_DEV_NONE;
198e0fed 1719 ap->flags |= ATA_FLAG_DISABLED;
1da177e4
LT		 1720}
1721
1c3fae4d 1722/**
3c567b7d 1723 * sata_down_spd_limit - adjust SATA spd limit downward
1c3fae4d
TH		 1724 * @ap: Port to adjust SATA spd limit for
1725 *
1726 * Adjust SATA spd limit of @ap downward. Note that this
1727 * function only adjusts the limit. The change must be applied
3c567b7d 1728 * using sata_set_spd().
1c3fae4d
TH		 1729 *
1730 * LOCKING:
1731 * Inherited from caller.
1732 *
1733 * RETURNS:
1734 * 0 on success, negative errno on failure
1735 */
3c567b7d 1736int sata_down_spd_limit(struct ata_port *ap)
1c3fae4d 1737{
81952c54
TH		 1738 u32 sstatus, spd, mask;
1739 int rc, highbit;
1c3fae4d 1740
81952c54
TH		 1741 rc = sata_scr_read(ap, SCR_STATUS, &sstatus);
1742 if (rc)
1743 return rc;
1c3fae4d
TH		 1744
1745 mask = ap->sata_spd_limit;
1746 if (mask <= 1)
1747 return -EINVAL;
1748 highbit = fls(mask) - 1;
1749 mask &= ~(1 << highbit);
1750
81952c54 1751 spd = (sstatus >> 4) & 0xf;
1c3fae4d
TH		 1752 if (spd <= 1)
1753 return -EINVAL;
1754 spd--;
1755 mask &= (1 << spd) - 1;
1756 if (!mask)
1757 return -EINVAL;
1758
1759 ap->sata_spd_limit = mask;
1760
f15a1daf
TH		 1761 ata_port_printk(ap, KERN_WARNING, "limiting SATA link speed to %s\n",
1762 sata_spd_string(fls(mask)));
1c3fae4d
TH		 1763
1764 return 0;
1765}
1766
3c567b7d 1767static int __sata_set_spd_needed(struct ata_port *ap, u32 *scontrol)
1c3fae4d
TH		 1768{
1769 u32 spd, limit;
1770
1771 if (ap->sata_spd_limit == UINT_MAX)
1772 limit = 0;
1773 else
1774 limit = fls(ap->sata_spd_limit);
1775
1776 spd = (*scontrol >> 4) & 0xf;
1777 *scontrol = (*scontrol & ~0xf0) | ((limit & 0xf) << 4);
1778
1779 return spd != limit;
1780}
1781
1782/**
3c567b7d 1783 * sata_set_spd_needed - is SATA spd configuration needed
1c3fae4d
TH		 1784 * @ap: Port in question
1785 *
1786 * Test whether the spd limit in SControl matches
1787 * @ap->sata_spd_limit. This function is used to determine
1788 * whether hardreset is necessary to apply SATA spd
1789 * configuration.
1790 *
1791 * LOCKING:
1792 * Inherited from caller.
1793 *
1794 * RETURNS:
1795 * 1 if SATA spd configuration is needed, 0 otherwise.
1796 */
3c567b7d 1797int sata_set_spd_needed(struct ata_port *ap)
1c3fae4d
TH		 1798{
1799 u32 scontrol;
1800
81952c54 1801 if (sata_scr_read(ap, SCR_CONTROL, &scontrol))
1c3fae4d
TH		 1802 return 0;
1803
3c567b7d 1804 return __sata_set_spd_needed(ap, &scontrol);
1c3fae4d
TH		 1805}
1806
1807/**
3c567b7d 1808 * sata_set_spd - set SATA spd according to spd limit
1c3fae4d
TH		 1809 * @ap: Port to set SATA spd for
1810 *
1811 * Set SATA spd of @ap according to sata_spd_limit.
1812 *
1813 * LOCKING:
1814 * Inherited from caller.
1815 *
1816 * RETURNS:
1817 * 0 if spd doesn't need to be changed, 1 if spd has been
81952c54 1818 * changed. Negative errno if SCR registers are inaccessible.
1c3fae4d 1819 */
3c567b7d 1820int sata_set_spd(struct ata_port *ap)
1c3fae4d
TH		 1821{
1822 u32 scontrol;
81952c54 1823 int rc;
1c3fae4d 1824
81952c54
TH		 1825 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
1826 return rc;
1c3fae4d 1827
3c567b7d 1828 if (!__sata_set_spd_needed(ap, &scontrol))
1c3fae4d
TH		 1829 return 0;
1830
81952c54
TH		 1831 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
1832 return rc;
1833
1c3fae4d
TH		 1834 return 1;
1835}
1836
452503f9
AC		 1837/*
1838 * This mode timing computation functionality is ported over from
1839 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1840 */
1841/*
1842 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1843 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1844 * for PIO 5, which is a nonstandard extension and UDMA6, which
2e9edbf8 1845 * is currently supported only by Maxtor drives.
452503f9
AC		 1846 */
1847
1848static const struct ata_timing ata_timing[] = {
1849
1850 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1851 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1852 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1853 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1854
1855 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1856 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1857 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1858
1859/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
2e9edbf8 1860
452503f9
AC		 1861 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1862 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1863 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
2e9edbf8 1864
452503f9
AC		 1865 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1866 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1867 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1868
1869/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1870 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1871 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1872
1873 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1874 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1875 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1876
1877/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1878
1879 { 0xFF }
1880};
1881
1882#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1883#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1884
1885static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1886{
1887 q->setup = EZ(t->setup * 1000, T);
1888 q->act8b = EZ(t->act8b * 1000, T);
1889 q->rec8b = EZ(t->rec8b * 1000, T);
1890 q->cyc8b = EZ(t->cyc8b * 1000, T);
1891 q->active = EZ(t->active * 1000, T);
1892 q->recover = EZ(t->recover * 1000, T);
1893 q->cycle = EZ(t->cycle * 1000, T);
1894 q->udma = EZ(t->udma * 1000, UT);
1895}
1896
1897void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1898 struct ata_timing *m, unsigned int what)
1899{
1900 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1901 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1902 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1903 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1904 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1905 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1906 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1907 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1908}
1909
1910static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1911{
1912 const struct ata_timing *t;
1913
1914 for (t = ata_timing; t->mode != speed; t++)
91190758 1915 if (t->mode == 0xFF)
452503f9 1916 return NULL;
2e9edbf8 1917 return t;
452503f9
AC		 1918}
1919
1920int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1921 struct ata_timing *t, int T, int UT)
1922{
1923 const struct ata_timing *s;
1924 struct ata_timing p;
1925
1926 /*
2e9edbf8 1927 * Find the mode.
75b1f2f8 1928 */
452503f9
AC		 1929
1930 if (!(s = ata_timing_find_mode(speed)))
1931 return -EINVAL;
1932
75b1f2f8
AL		 1933 memcpy(t, s, sizeof(*s));
1934
452503f9
AC		 1935 /*
1936 * If the drive is an EIDE drive, it can tell us it needs extended
1937 * PIO/MW_DMA cycle timing.
1938 */
1939
1940 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1941 memset(&p, 0, sizeof(p));
1942 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1943 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1944 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1945 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1946 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1947 }
1948 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1949 }
1950
1951 /*
1952 * Convert the timing to bus clock counts.
1953 */
1954
75b1f2f8 1955 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 1956
1957 /*
c893a3ae
RD		 1958 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
1959 * S.M.A.R.T * and some other commands. We have to ensure that the
1960 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC		 1961 */
1962
1963 if (speed > XFER_PIO_4) {
1964 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1965 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1966 }
1967
1968 /*
c893a3ae 1969 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC		 1970 */
1971
1972 if (t->act8b + t->rec8b < t->cyc8b) {
1973 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1974 t->rec8b = t->cyc8b - t->act8b;
1975 }
1976
1977 if (t->active + t->recover < t->cycle) {
1978 t->active += (t->cycle - (t->active + t->recover)) / 2;
1979 t->recover = t->cycle - t->active;
1980 }
1981
1982 return 0;
1983}
1984
cf176e1a
TH		 1985/**
1986 * ata_down_xfermask_limit - adjust dev xfer masks downward
cf176e1a
TH		 1987 * @dev: Device to adjust xfer masks
1988 * @force_pio0: Force PIO0
1989 *
1990 * Adjust xfer masks of @dev downward. Note that this function
1991 * does not apply the change. Invoking ata_set_mode() afterwards
1992 * will apply the limit.
1993 *
1994 * LOCKING:
1995 * Inherited from caller.
1996 *
1997 * RETURNS:
1998 * 0 on success, negative errno on failure
1999 */
3373efd8 2000int ata_down_xfermask_limit(struct ata_device *dev, int force_pio0)
cf176e1a
TH		 2001{
2002 unsigned long xfer_mask;
2003 int highbit;
2004
2005 xfer_mask = ata_pack_xfermask(dev->pio_mask, dev->mwdma_mask,
2006 dev->udma_mask);
2007
2008 if (!xfer_mask)
2009 goto fail;
2010 /* don't gear down to MWDMA from UDMA, go directly to PIO */
2011 if (xfer_mask & ATA_MASK_UDMA)
2012 xfer_mask &= ~ATA_MASK_MWDMA;
2013
2014 highbit = fls(xfer_mask) - 1;
2015 xfer_mask &= ~(1 << highbit);
2016 if (force_pio0)
2017 xfer_mask &= 1 << ATA_SHIFT_PIO;
2018 if (!xfer_mask)
2019 goto fail;
2020
2021 ata_unpack_xfermask(xfer_mask, &dev->pio_mask, &dev->mwdma_mask,
2022 &dev->udma_mask);
2023
f15a1daf
TH		 2024 ata_dev_printk(dev, KERN_WARNING, "limiting speed to %s\n",
2025 ata_mode_string(xfer_mask));
cf176e1a
TH		 2026
2027 return 0;
2028
2029 fail:
2030 return -EINVAL;
2031}
2032
3373efd8 2033static int ata_dev_set_mode(struct ata_device *dev)
1da177e4 2034{
83206a29
TH		 2035 unsigned int err_mask;
2036 int rc;
1da177e4 2037
e8384607 2038 dev->flags &= ~ATA_DFLAG_PIO;
1da177e4
LT		 2039 if (dev->xfer_shift == ATA_SHIFT_PIO)
2040 dev->flags |= ATA_DFLAG_PIO;
2041
3373efd8 2042 err_mask = ata_dev_set_xfermode(dev);
83206a29 2043 if (err_mask) {
f15a1daf
TH		 2044 ata_dev_printk(dev, KERN_ERR, "failed to set xfermode "
2045 "(err_mask=0x%x)\n", err_mask);
83206a29
TH		 2046 return -EIO;
2047 }
1da177e4 2048
3373efd8 2049 rc = ata_dev_revalidate(dev, 0);
5eb45c02 2050 if (rc)
83206a29 2051 return rc;
48a8a14f 2052
23e71c3d
TH		 2053 DPRINTK("xfer_shift=%u, xfer_mode=0x%x\n",
2054 dev->xfer_shift, (int)dev->xfer_mode);
1da177e4 2055
f15a1daf
TH		 2056 ata_dev_printk(dev, KERN_INFO, "configured for %s\n",
2057 ata_mode_string(ata_xfer_mode2mask(dev->xfer_mode)));
83206a29 2058 return 0;
1da177e4
LT		 2059}
2060
1da177e4
LT		 2061/**
2062 * ata_set_mode - Program timings and issue SET FEATURES - XFER
2063 * @ap: port on which timings will be programmed
e82cbdb9 2064 * @r_failed_dev: out paramter for failed device
1da177e4 2065 *
e82cbdb9
TH		 2066 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.). If
2067 * ata_set_mode() fails, pointer to the failing device is
2068 * returned in @r_failed_dev.
780a87f7 2069 *
1da177e4 2070 * LOCKING:
0cba632b 2071 * PCI/etc. bus probe sem.
e82cbdb9
TH		 2072 *
2073 * RETURNS:
2074 * 0 on success, negative errno otherwise
1da177e4 2075 */
1ad8e7f9 2076int ata_set_mode(struct ata_port *ap, struct ata_device **r_failed_dev)
1da177e4 2077{
e8e0619f 2078 struct ata_device *dev;
e82cbdb9 2079 int i, rc = 0, used_dma = 0, found = 0;
1da177e4 2080
3adcebb2
TH		 2081 /* has private set_mode? */
2082 if (ap->ops->set_mode) {
2083 /* FIXME: make ->set_mode handle no device case and
2084 * return error code and failing device on failure.
2085 */
2086 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2087 if (ata_dev_enabled(&ap->device[i])) {
2088 ap->ops->set_mode(ap);
2089 break;
2090 }
2091 }
2092 return 0;
2093 }
2094
a6d5a51c
TH		 2095 /* step 1: calculate xfer_mask */
2096 for (i = 0; i < ATA_MAX_DEVICES; i++) {
acf356b1 2097 unsigned int pio_mask, dma_mask;
a6d5a51c 2098
e8e0619f
TH		 2099 dev = &ap->device[i];
2100
e1211e3f 2101 if (!ata_dev_enabled(dev))
a6d5a51c
TH		 2102 continue;
2103
3373efd8 2104 ata_dev_xfermask(dev);
1da177e4 2105
acf356b1
TH		 2106 pio_mask = ata_pack_xfermask(dev->pio_mask, 0, 0);
2107 dma_mask = ata_pack_xfermask(0, dev->mwdma_mask, dev->udma_mask);
2108 dev->pio_mode = ata_xfer_mask2mode(pio_mask);
2109 dev->dma_mode = ata_xfer_mask2mode(dma_mask);
5444a6f4 2110
4f65977d 2111 found = 1;
5444a6f4
AC		 2112 if (dev->dma_mode)
2113 used_dma = 1;
a6d5a51c 2114 }
4f65977d 2115 if (!found)
e82cbdb9 2116 goto out;
a6d5a51c
TH		 2117
2118 /* step 2: always set host PIO timings */
e8e0619f
TH		 2119 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2120 dev = &ap->device[i];
2121 if (!ata_dev_enabled(dev))
2122 continue;
2123
2124 if (!dev->pio_mode) {
f15a1daf 2125 ata_dev_printk(dev, KERN_WARNING, "no PIO support\n");
e8e0619f 2126 rc = -EINVAL;
e82cbdb9 2127 goto out;
e8e0619f
TH		 2128 }
2129
2130 dev->xfer_mode = dev->pio_mode;
2131 dev->xfer_shift = ATA_SHIFT_PIO;
2132 if (ap->ops->set_piomode)
2133 ap->ops->set_piomode(ap, dev);
2134 }
1da177e4 2135
a6d5a51c 2136 /* step 3: set host DMA timings */
e8e0619f
TH		 2137 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2138 dev = &ap->device[i];
2139
2140 if (!ata_dev_enabled(dev) || !dev->dma_mode)
2141 continue;
2142
2143 dev->xfer_mode = dev->dma_mode;
2144 dev->xfer_shift = ata_xfer_mode2shift(dev->dma_mode);
2145 if (ap->ops->set_dmamode)
2146 ap->ops->set_dmamode(ap, dev);
2147 }
1da177e4
LT		 2148
2149 /* step 4: update devices' xfer mode */
83206a29 2150 for (i = 0; i < ATA_MAX_DEVICES; i++) {
e8e0619f 2151 dev = &ap->device[i];
1da177e4 2152
e1211e3f 2153 if (!ata_dev_enabled(dev))
83206a29
TH		 2154 continue;
2155
3373efd8 2156 rc = ata_dev_set_mode(dev);
5bbc53f4 2157 if (rc)
e82cbdb9 2158 goto out;
83206a29 2159 }
1da177e4 2160
e8e0619f
TH		 2161 /* Record simplex status. If we selected DMA then the other
2162 * host channels are not permitted to do so.
5444a6f4 2163 */
5444a6f4
AC		 2164 if (used_dma && (ap->host_set->flags & ATA_HOST_SIMPLEX))
2165 ap->host_set->simplex_claimed = 1;
2166
e8e0619f 2167 /* step5: chip specific finalisation */
1da177e4
LT		 2168 if (ap->ops->post_set_mode)
2169 ap->ops->post_set_mode(ap);
2170
e82cbdb9
TH		 2171 out:
2172 if (rc)
2173 *r_failed_dev = dev;
2174 return rc;
1da177e4
LT		 2175}
2176
1fdffbce
JG		 2177/**
2178 * ata_tf_to_host - issue ATA taskfile to host controller
2179 * @ap: port to which command is being issued
2180 * @tf: ATA taskfile register set
2181 *
2182 * Issues ATA taskfile register set to ATA host controller,
2183 * with proper synchronization with interrupt handler and
2184 * other threads.
2185 *
2186 * LOCKING:
2187 * spin_lock_irqsave(host_set lock)
2188 */
2189
2190static inline void ata_tf_to_host(struct ata_port *ap,
2191 const struct ata_taskfile *tf)
2192{
2193 ap->ops->tf_load(ap, tf);
2194 ap->ops->exec_command(ap, tf);
2195}
2196
1da177e4
LT		 2197/**
2198 * ata_busy_sleep - sleep until BSY clears, or timeout
2199 * @ap: port containing status register to be polled
2200 * @tmout_pat: impatience timeout
2201 * @tmout: overall timeout
2202 *
780a87f7
JG		 2203 * Sleep until ATA Status register bit BSY clears,
2204 * or a timeout occurs.
2205 *
2206 * LOCKING: None.
1da177e4
LT		 2207 */
2208
6f8b9958
TH		 2209unsigned int ata_busy_sleep (struct ata_port *ap,
2210 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT		 2211{
2212 unsigned long timer_start, timeout;
2213 u8 status;
2214
2215 status = ata_busy_wait(ap, ATA_BUSY, 300);
2216 timer_start = jiffies;
2217 timeout = timer_start + tmout_pat;
2218 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
2219 msleep(50);
2220 status = ata_busy_wait(ap, ATA_BUSY, 3);
2221 }
2222
2223 if (status & ATA_BUSY)
f15a1daf
TH		 2224 ata_port_printk(ap, KERN_WARNING,
2225 "port is slow to respond, please be patient\n");
1da177e4
LT		 2226
2227 timeout = timer_start + tmout;
2228 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
2229 msleep(50);
2230 status = ata_chk_status(ap);
2231 }
2232
2233 if (status & ATA_BUSY) {
f15a1daf
TH		 2234 ata_port_printk(ap, KERN_ERR, "port failed to respond "
2235 "(%lu secs)\n", tmout / HZ);
1da177e4
LT		 2236 return 1;
2237 }
2238
2239 return 0;
2240}
2241
2242static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
2243{
2244 struct ata_ioports *ioaddr = &ap->ioaddr;
2245 unsigned int dev0 = devmask & (1 << 0);
2246 unsigned int dev1 = devmask & (1 << 1);
2247 unsigned long timeout;
2248
2249 /* if device 0 was found in ata_devchk, wait for its
2250 * BSY bit to clear
2251 */
2252 if (dev0)
2253 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2254
2255 /* if device 1 was found in ata_devchk, wait for
2256 * register access, then wait for BSY to clear
2257 */
2258 timeout = jiffies + ATA_TMOUT_BOOT;
2259 while (dev1) {
2260 u8 nsect, lbal;
2261
2262 ap->ops->dev_select(ap, 1);
2263 if (ap->flags & ATA_FLAG_MMIO) {
2264 nsect = readb((void __iomem *) ioaddr->nsect_addr);
2265 lbal = readb((void __iomem *) ioaddr->lbal_addr);
2266 } else {
2267 nsect = inb(ioaddr->nsect_addr);
2268 lbal = inb(ioaddr->lbal_addr);
2269 }
2270 if ((nsect == 1) && (lbal == 1))
2271 break;
2272 if (time_after(jiffies, timeout)) {
2273 dev1 = 0;
2274 break;
2275 }
2276 msleep(50); /* give drive a breather */
2277 }
2278 if (dev1)
2279 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2280
2281 /* is all this really necessary? */
2282 ap->ops->dev_select(ap, 0);
2283 if (dev1)
2284 ap->ops->dev_select(ap, 1);
2285 if (dev0)
2286 ap->ops->dev_select(ap, 0);
2287}
2288
1da177e4
LT		 2289static unsigned int ata_bus_softreset(struct ata_port *ap,
2290 unsigned int devmask)
2291{
2292 struct ata_ioports *ioaddr = &ap->ioaddr;
2293
2294 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
2295
2296 /* software reset. causes dev0 to be selected */
2297 if (ap->flags & ATA_FLAG_MMIO) {
2298 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2299 udelay(20); /* FIXME: flush */
2300 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
2301 udelay(20); /* FIXME: flush */
2302 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2303 } else {
2304 outb(ap->ctl, ioaddr->ctl_addr);
2305 udelay(10);
2306 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2307 udelay(10);
2308 outb(ap->ctl, ioaddr->ctl_addr);
2309 }
2310
2311 /* spec mandates ">= 2ms" before checking status.
2312 * We wait 150ms, because that was the magic delay used for
2313 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
2314 * between when the ATA command register is written, and then
2315 * status is checked. Because waiting for "a while" before
2316 * checking status is fine, post SRST, we perform this magic
2317 * delay here as well.
09c7ad79
AC		 2318 *
2319 * Old drivers/ide uses the 2mS rule and then waits for ready
1da177e4
LT		 2320 */
2321 msleep(150);
2322
2e9edbf8 2323 /* Before we perform post reset processing we want to see if
298a41ca
TH		 2324 * the bus shows 0xFF because the odd clown forgets the D7
2325 * pulldown resistor.
2326 */
987d2f05 2327 if (ata_check_status(ap) == 0xFF) {
f15a1daf 2328 ata_port_printk(ap, KERN_ERR, "SRST failed (status 0xFF)\n");
298a41ca 2329 return AC_ERR_OTHER;
987d2f05 2330 }
09c7ad79 2331
1da177e4
LT		 2332 ata_bus_post_reset(ap, devmask);
2333
2334 return 0;
2335}
2336
2337/**
2338 * ata_bus_reset - reset host port and associated ATA channel
2339 * @ap: port to reset
2340 *
2341 * This is typically the first time we actually start issuing
2342 * commands to the ATA channel. We wait for BSY to clear, then
2343 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2344 * result. Determine what devices, if any, are on the channel
2345 * by looking at the device 0/1 error register. Look at the signature
2346 * stored in each device's taskfile registers, to determine if
2347 * the device is ATA or ATAPI.
2348 *
2349 * LOCKING:
0cba632b
JG		 2350 * PCI/etc. bus probe sem.
2351 * Obtains host_set lock.
1da177e4
LT		 2352 *
2353 * SIDE EFFECTS:
198e0fed 2354 * Sets ATA_FLAG_DISABLED if bus reset fails.
1da177e4
LT		 2355 */
2356
2357void ata_bus_reset(struct ata_port *ap)
2358{
2359 struct ata_ioports *ioaddr = &ap->ioaddr;
2360 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2361 u8 err;
aec5c3c1 2362 unsigned int dev0, dev1 = 0, devmask = 0;
1da177e4
LT		 2363
2364 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
2365
2366 /* determine if device 0/1 are present */
2367 if (ap->flags & ATA_FLAG_SATA_RESET)
2368 dev0 = 1;
2369 else {
2370 dev0 = ata_devchk(ap, 0);
2371 if (slave_possible)
2372 dev1 = ata_devchk(ap, 1);
2373 }
2374
2375 if (dev0)
2376 devmask |= (1 << 0);
2377 if (dev1)
2378 devmask |= (1 << 1);
2379
2380 /* select device 0 again */
2381 ap->ops->dev_select(ap, 0);
2382
2383 /* issue bus reset */
2384 if (ap->flags & ATA_FLAG_SRST)
aec5c3c1
TH		 2385 if (ata_bus_softreset(ap, devmask))
2386 goto err_out;
1da177e4
LT		 2387
2388 /*
2389 * determine by signature whether we have ATA or ATAPI devices
2390 */
b4dc7623 2391 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 2392 if ((slave_possible) && (err != 0x81))
b4dc7623 2393 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT		 2394
2395 /* re-enable interrupts */
2396 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2397 ata_irq_on(ap);
2398
2399 /* is double-select really necessary? */
2400 if (ap->device[1].class != ATA_DEV_NONE)
2401 ap->ops->dev_select(ap, 1);
2402 if (ap->device[0].class != ATA_DEV_NONE)
2403 ap->ops->dev_select(ap, 0);
2404
2405 /* if no devices were detected, disable this port */
2406 if ((ap->device[0].class == ATA_DEV_NONE) &&
2407 (ap->device[1].class == ATA_DEV_NONE))
2408 goto err_out;
2409
2410 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2411 /* set up device control for ATA_FLAG_SATA_RESET */
2412 if (ap->flags & ATA_FLAG_MMIO)
2413 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2414 else
2415 outb(ap->ctl, ioaddr->ctl_addr);
2416 }
2417
2418 DPRINTK("EXIT\n");
2419 return;
2420
2421err_out:
f15a1daf 2422 ata_port_printk(ap, KERN_ERR, "disabling port\n");
1da177e4
LT		 2423 ap->ops->port_disable(ap);
2424
2425 DPRINTK("EXIT\n");
2426}
2427
7a7921e8
TH		 2428static int sata_phy_resume(struct ata_port *ap)
2429{
2430 unsigned long timeout = jiffies + (HZ * 5);
852ee16a 2431 u32 scontrol, sstatus;
81952c54
TH		 2432 int rc;
2433
2434 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2435 return rc;
7a7921e8 2436
852ee16a 2437 scontrol = (scontrol & 0x0f0) | 0x300;
81952c54
TH		 2438
2439 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
2440 return rc;
7a7921e8
TH		 2441
2442 /* Wait for phy to become ready, if necessary. */
2443 do {
2444 msleep(200);
81952c54
TH		 2445 if ((rc = sata_scr_read(ap, SCR_STATUS, &sstatus)))
2446 return rc;
7a7921e8
TH		 2447 if ((sstatus & 0xf) != 1)
2448 return 0;
2449 } while (time_before(jiffies, timeout));
2450
81952c54 2451 return -EBUSY;
7a7921e8
TH		 2452}
2453
8a19ac89
TH		 2454/**
2455 * ata_std_probeinit - initialize probing
2456 * @ap: port to be probed
2457 *
2458 * @ap is about to be probed. Initialize it. This function is
2459 * to be used as standard callback for ata_drive_probe_reset().
3a39746a
TH		 2460 *
2461 * NOTE!!! Do not use this function as probeinit if a low level
2462 * driver implements only hardreset. Just pass NULL as probeinit
2463 * in that case. Using this function is probably okay but doing
2464 * so makes reset sequence different from the original
2465 * ->phy_reset implementation and Jeff nervous. :-P
8a19ac89 2466 */
17efc5f7 2467void ata_std_probeinit(struct ata_port *ap)
8a19ac89 2468{
81952c54 2469 u32 scontrol;
1c3fae4d 2470
81952c54
TH		 2471 /* resume link */
2472 sata_phy_resume(ap);
1c3fae4d 2473
81952c54
TH		 2474 /* init sata_spd_limit to the current value */
2475 if (sata_scr_read(ap, SCR_CONTROL, &scontrol) == 0) {
2476 int spd = (scontrol >> 4) & 0xf;
2477 ap->sata_spd_limit &= (1 << spd) - 1;
3a39746a 2478 }
81952c54
TH		 2479
2480 /* wait for device */
2481 if (ata_port_online(ap))
2482 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
8a19ac89
TH		 2483}
2484
c2bd5804
TH		 2485/**
2486 * ata_std_softreset - reset host port via ATA SRST
2487 * @ap: port to reset
c2bd5804
TH		 2488 * @classes: resulting classes of attached devices
2489 *
2490 * Reset host port using ATA SRST. This function is to be used
2491 * as standard callback for ata_drive_*_reset() functions.
2492 *
2493 * LOCKING:
2494 * Kernel thread context (may sleep)
2495 *
2496 * RETURNS:
2497 * 0 on success, -errno otherwise.
2498 */
2bf2cb26 2499int ata_std_softreset(struct ata_port *ap, unsigned int *classes)
c2bd5804
TH		 2500{
2501 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2502 unsigned int devmask = 0, err_mask;
2503 u8 err;
2504
2505 DPRINTK("ENTER\n");
2506
81952c54 2507 if (ata_port_offline(ap)) {
3a39746a
TH		 2508 classes[0] = ATA_DEV_NONE;
2509 goto out;
2510 }
2511
c2bd5804
TH		 2512 /* determine if device 0/1 are present */
2513 if (ata_devchk(ap, 0))
2514 devmask |= (1 << 0);
2515 if (slave_possible && ata_devchk(ap, 1))
2516 devmask |= (1 << 1);
2517
c2bd5804
TH		 2518 /* select device 0 again */
2519 ap->ops->dev_select(ap, 0);
2520
2521 /* issue bus reset */
2522 DPRINTK("about to softreset, devmask=%x\n", devmask);
2523 err_mask = ata_bus_softreset(ap, devmask);
2524 if (err_mask) {
f15a1daf
TH		 2525 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
2526 err_mask);
c2bd5804
TH		 2527 return -EIO;
2528 }
2529
2530 /* determine by signature whether we have ATA or ATAPI devices */
2531 classes[0] = ata_dev_try_classify(ap, 0, &err);
2532 if (slave_possible && err != 0x81)
2533 classes[1] = ata_dev_try_classify(ap, 1, &err);
2534
3a39746a 2535 out:
c2bd5804
TH		 2536 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2537 return 0;
2538}
2539
2540/**
2541 * sata_std_hardreset - reset host port via SATA phy reset
2542 * @ap: port to reset
c2bd5804
TH		 2543 * @class: resulting class of attached device
2544 *
2545 * SATA phy-reset host port using DET bits of SControl register.
2546 * This function is to be used as standard callback for
2547 * ata_drive_*_reset().
2548 *
2549 * LOCKING:
2550 * Kernel thread context (may sleep)
2551 *
2552 * RETURNS:
2553 * 0 on success, -errno otherwise.
2554 */
2bf2cb26 2555int sata_std_hardreset(struct ata_port *ap, unsigned int *class)
c2bd5804 2556{
852ee16a 2557 u32 scontrol;
81952c54 2558 int rc;
852ee16a 2559
c2bd5804
TH		 2560 DPRINTK("ENTER\n");
2561
3c567b7d 2562 if (sata_set_spd_needed(ap)) {
1c3fae4d
TH		 2563 /* SATA spec says nothing about how to reconfigure
2564 * spd. To be on the safe side, turn off phy during
2565 * reconfiguration. This works for at least ICH7 AHCI
2566 * and Sil3124.
2567 */
81952c54
TH		 2568 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2569 return rc;
2570
1c3fae4d 2571 scontrol = (scontrol & 0x0f0) | 0x302;
81952c54
TH		 2572
2573 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
2574 return rc;
1c3fae4d 2575
3c567b7d 2576 sata_set_spd(ap);
1c3fae4d
TH		 2577 }
2578
2579 /* issue phy wake/reset */
81952c54
TH		 2580 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2581 return rc;
2582
852ee16a 2583 scontrol = (scontrol & 0x0f0) | 0x301;
81952c54
TH		 2584
2585 if ((rc = sata_scr_write_flush(ap, SCR_CONTROL, scontrol)))
2586 return rc;
c2bd5804 2587
1c3fae4d 2588 /* Couldn't find anything in SATA I/II specs, but AHCI-1.1
c2bd5804
TH		 2589 * 10.4.2 says at least 1 ms.
2590 */
2591 msleep(1);
2592
1c3fae4d 2593 /* bring phy back */
7a7921e8 2594 sata_phy_resume(ap);
c2bd5804 2595
c2bd5804 2596 /* TODO: phy layer with polling, timeouts, etc. */
81952c54 2597 if (ata_port_offline(ap)) {
c2bd5804
TH		 2598 *class = ATA_DEV_NONE;
2599 DPRINTK("EXIT, link offline\n");
2600 return 0;
2601 }
2602
2603 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
f15a1daf
TH		 2604 ata_port_printk(ap, KERN_ERR,
2605 "COMRESET failed (device not ready)\n");
c2bd5804
TH		 2606 return -EIO;
2607 }
2608
3a39746a
TH		 2609 ap->ops->dev_select(ap, 0); /* probably unnecessary */
2610
c2bd5804
TH		 2611 *class = ata_dev_try_classify(ap, 0, NULL);
2612
2613 DPRINTK("EXIT, class=%u\n", *class);
2614 return 0;
2615}
2616
2617/**
2618 * ata_std_postreset - standard postreset callback
2619 * @ap: the target ata_port
2620 * @classes: classes of attached devices
2621 *
2622 * This function is invoked after a successful reset. Note that
2623 * the device might have been reset more than once using
2624 * different reset methods before postreset is invoked.
c2bd5804
TH		 2625 *
2626 * This function is to be used as standard callback for
2627 * ata_drive_*_reset().
2628 *
2629 * LOCKING:
2630 * Kernel thread context (may sleep)
2631 */
2632void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2633{
dc2b3515
TH		 2634 u32 serror;
2635
c2bd5804
TH		 2636 DPRINTK("ENTER\n");
2637
c2bd5804 2638 /* print link status */
81952c54 2639 sata_print_link_status(ap);
c2bd5804 2640
dc2b3515
TH		 2641 /* clear SError */
2642 if (sata_scr_read(ap, SCR_ERROR, &serror) == 0)
2643 sata_scr_write(ap, SCR_ERROR, serror);
2644
3a39746a 2645 /* re-enable interrupts */
e3180499
TH		 2646 if (!ap->ops->error_handler) {
2647 /* FIXME: hack. create a hook instead */
2648 if (ap->ioaddr.ctl_addr)
2649 ata_irq_on(ap);
2650 }
c2bd5804
TH		 2651
2652 /* is double-select really necessary? */
2653 if (classes[0] != ATA_DEV_NONE)
2654 ap->ops->dev_select(ap, 1);
2655 if (classes[1] != ATA_DEV_NONE)
2656 ap->ops->dev_select(ap, 0);
2657
3a39746a
TH		 2658 /* bail out if no device is present */
2659 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2660 DPRINTK("EXIT, no device\n");
2661 return;
2662 }
2663
2664 /* set up device control */
2665 if (ap->ioaddr.ctl_addr) {
2666 if (ap->flags & ATA_FLAG_MMIO)
2667 writeb(ap->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
2668 else
2669 outb(ap->ctl, ap->ioaddr.ctl_addr);
2670 }
c2bd5804
TH		 2671
2672 DPRINTK("EXIT\n");
2673}
2674
2675/**
2676 * ata_std_probe_reset - standard probe reset method
2677 * @ap: prot to perform probe-reset
2678 * @classes: resulting classes of attached devices
2679 *
2680 * The stock off-the-shelf ->probe_reset method.
2681 *
2682 * LOCKING:
2683 * Kernel thread context (may sleep)
2684 *
2685 * RETURNS:
2686 * 0 on success, -errno otherwise.
2687 */
2688int ata_std_probe_reset(struct ata_port *ap, unsigned int *classes)
2689{
2690 ata_reset_fn_t hardreset;
2691
2692 hardreset = NULL;
81952c54 2693 if (sata_scr_valid(ap))
c2bd5804
TH		 2694 hardreset = sata_std_hardreset;
2695
8a19ac89 2696 return ata_drive_probe_reset(ap, ata_std_probeinit,
7944ea95 2697 ata_std_softreset, hardreset,
c2bd5804
TH		 2698 ata_std_postreset, classes);
2699}
2700
2bf2cb26 2701int ata_do_reset(struct ata_port *ap, ata_reset_fn_t reset,
96bd39ec 2702 unsigned int *classes)
a62c0fc5
TH		 2703{
2704 int i, rc;
2705
2706 for (i = 0; i < ATA_MAX_DEVICES; i++)
2707 classes[i] = ATA_DEV_UNKNOWN;
2708
2bf2cb26 2709 rc = reset(ap, classes);
a62c0fc5
TH		 2710 if (rc)
2711 return rc;
2712
2713 /* If any class isn't ATA_DEV_UNKNOWN, consider classification
2714 * is complete and convert all ATA_DEV_UNKNOWN to
2715 * ATA_DEV_NONE.
2716 */
2717 for (i = 0; i < ATA_MAX_DEVICES; i++)
2718 if (classes[i] != ATA_DEV_UNKNOWN)
2719 break;
2720
2721 if (i < ATA_MAX_DEVICES)
2722 for (i = 0; i < ATA_MAX_DEVICES; i++)
2723 if (classes[i] == ATA_DEV_UNKNOWN)
2724 classes[i] = ATA_DEV_NONE;
2725
9974e7cc 2726 return 0;
a62c0fc5
TH		 2727}
2728
2729/**
2730 * ata_drive_probe_reset - Perform probe reset with given methods
2731 * @ap: port to reset
7944ea95 2732 * @probeinit: probeinit method (can be NULL)
a62c0fc5
TH		 2733 * @softreset: softreset method (can be NULL)
2734 * @hardreset: hardreset method (can be NULL)
2735 * @postreset: postreset method (can be NULL)
2736 * @classes: resulting classes of attached devices
2737 *
2738 * Reset the specified port and classify attached devices using
2739 * given methods. This function prefers softreset but tries all
2740 * possible reset sequences to reset and classify devices. This
2741 * function is intended to be used for constructing ->probe_reset
2742 * callback by low level drivers.
2743 *
2744 * Reset methods should follow the following rules.
2745 *
2746 * - Return 0 on sucess, -errno on failure.
2747 * - If classification is supported, fill classes[] with
2748 * recognized class codes.
2749 * - If classification is not supported, leave classes[] alone.
a62c0fc5
TH		 2750 *
2751 * LOCKING:
2752 * Kernel thread context (may sleep)
2753 *
2754 * RETURNS:
2755 * 0 on success, -EINVAL if no reset method is avaliable, -ENODEV
2756 * if classification fails, and any error code from reset
2757 * methods.
2758 */
7944ea95 2759int ata_drive_probe_reset(struct ata_port *ap, ata_probeinit_fn_t probeinit,
a62c0fc5
TH		 2760 ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
2761 ata_postreset_fn_t postreset, unsigned int *classes)
2762{
2763 int rc = -EINVAL;
2764
e3180499
TH		 2765 ata_eh_freeze_port(ap);
2766
7944ea95
TH		 2767 if (probeinit)
2768 probeinit(ap);
2769
3c567b7d 2770 if (softreset && !sata_set_spd_needed(ap)) {
96bd39ec 2771 rc = ata_do_reset(ap, softreset, classes);
9974e7cc
TH		 2772 if (rc == 0 && classes[0] != ATA_DEV_UNKNOWN)
2773 goto done;
f15a1daf
TH		 2774 ata_port_printk(ap, KERN_INFO, "softreset failed, "
2775 "will try hardreset in 5 secs\n");
edbabd86 2776 ssleep(5);
a62c0fc5
TH		 2777 }
2778
2779 if (!hardreset)
9974e7cc 2780 goto done;
a62c0fc5 2781
90dac02c 2782 while (1) {
96bd39ec 2783 rc = ata_do_reset(ap, hardreset, classes);
90dac02c
TH		 2784 if (rc == 0) {
2785 if (classes[0] != ATA_DEV_UNKNOWN)
2786 goto done;
2787 break;
2788 }
2789
3c567b7d 2790 if (sata_down_spd_limit(ap))
90dac02c 2791 goto done;
edbabd86 2792
f15a1daf
TH		 2793 ata_port_printk(ap, KERN_INFO, "hardreset failed, "
2794 "will retry in 5 secs\n");
edbabd86 2795 ssleep(5);
90dac02c 2796 }
a62c0fc5 2797
edbabd86 2798 if (softreset) {
f15a1daf
TH		 2799 ata_port_printk(ap, KERN_INFO,
2800 "hardreset succeeded without classification, "
2801 "will retry softreset in 5 secs\n");
edbabd86
TH		 2802 ssleep(5);
2803
96bd39ec 2804 rc = ata_do_reset(ap, softreset, classes);
edbabd86 2805 }
a62c0fc5 2806
9974e7cc 2807 done:
96bd39ec
TH		 2808 if (rc == 0) {
2809 if (postreset)
2810 postreset(ap, classes);
e3180499
TH		 2811
2812 ata_eh_thaw_port(ap);
2813
96bd39ec
TH		 2814 if (classes[0] == ATA_DEV_UNKNOWN)
2815 rc = -ENODEV;
2816 }
a62c0fc5
TH		 2817 return rc;
2818}
2819
623a3128
TH		 2820/**
2821 * ata_dev_same_device - Determine whether new ID matches configured device
623a3128
TH		 2822 * @dev: device to compare against
2823 * @new_class: class of the new device
2824 * @new_id: IDENTIFY page of the new device
2825 *
2826 * Compare @new_class and @new_id against @dev and determine
2827 * whether @dev is the device indicated by @new_class and
2828 * @new_id.
2829 *
2830 * LOCKING:
2831 * None.
2832 *
2833 * RETURNS:
2834 * 1 if @dev matches @new_class and @new_id, 0 otherwise.
2835 */
3373efd8
TH		 2836static int ata_dev_same_device(struct ata_device *dev, unsigned int new_class,
2837 const u16 *new_id)
623a3128
TH		 2838{
2839 const u16 *old_id = dev->id;
2840 unsigned char model[2][41], serial[2][21];
2841 u64 new_n_sectors;
2842
2843 if (dev->class != new_class) {
f15a1daf
TH		 2844 ata_dev_printk(dev, KERN_INFO, "class mismatch %d != %d\n",
2845 dev->class, new_class);
623a3128
TH		 2846 return 0;
2847 }
2848
2849 ata_id_c_string(old_id, model[0], ATA_ID_PROD_OFS, sizeof(model[0]));
2850 ata_id_c_string(new_id, model[1], ATA_ID_PROD_OFS, sizeof(model[1]));
2851 ata_id_c_string(old_id, serial[0], ATA_ID_SERNO_OFS, sizeof(serial[0]));
2852 ata_id_c_string(new_id, serial[1], ATA_ID_SERNO_OFS, sizeof(serial[1]));
2853 new_n_sectors = ata_id_n_sectors(new_id);
2854
2855 if (strcmp(model[0], model[1])) {
f15a1daf
TH		 2856 ata_dev_printk(dev, KERN_INFO, "model number mismatch "
2857 "'%s' != '%s'\n", model[0], model[1]);
623a3128
TH		 2858 return 0;
2859 }
2860
2861 if (strcmp(serial[0], serial[1])) {
f15a1daf
TH		 2862 ata_dev_printk(dev, KERN_INFO, "serial number mismatch "
2863 "'%s' != '%s'\n", serial[0], serial[1]);
623a3128
TH		 2864 return 0;
2865 }
2866
2867 if (dev->class == ATA_DEV_ATA && dev->n_sectors != new_n_sectors) {
f15a1daf
TH		 2868 ata_dev_printk(dev, KERN_INFO, "n_sectors mismatch "
2869 "%llu != %llu\n",
2870 (unsigned long long)dev->n_sectors,
2871 (unsigned long long)new_n_sectors);
623a3128
TH		 2872 return 0;
2873 }
2874
2875 return 1;
2876}
2877
2878/**
2879 * ata_dev_revalidate - Revalidate ATA device
623a3128
TH		 2880 * @dev: device to revalidate
2881 * @post_reset: is this revalidation after reset?
2882 *
2883 * Re-read IDENTIFY page and make sure @dev is still attached to
2884 * the port.
2885 *
2886 * LOCKING:
2887 * Kernel thread context (may sleep)
2888 *
2889 * RETURNS:
2890 * 0 on success, negative errno otherwise
2891 */
3373efd8 2892int ata_dev_revalidate(struct ata_device *dev, int post_reset)
623a3128 2893{
5eb45c02 2894 unsigned int class = dev->class;
f15a1daf 2895 u16 *id = (void *)dev->ap->sector_buf;
623a3128
TH		 2896 int rc;
2897
5eb45c02
TH		 2898 if (!ata_dev_enabled(dev)) {
2899 rc = -ENODEV;
2900 goto fail;
2901 }
623a3128 2902
fe635c7e 2903 /* read ID data */
3373efd8 2904 rc = ata_dev_read_id(dev, &class, post_reset, id);
623a3128
TH		 2905 if (rc)
2906 goto fail;
2907
2908 /* is the device still there? */
3373efd8 2909 if (!ata_dev_same_device(dev, class, id)) {
623a3128
TH		 2910 rc = -ENODEV;
2911 goto fail;
2912 }
2913
fe635c7e 2914 memcpy(dev->id, id, sizeof(id[0]) * ATA_ID_WORDS);
623a3128
TH		 2915
2916 /* configure device according to the new ID */
3373efd8 2917 rc = ata_dev_configure(dev, 0);
5eb45c02
TH		 2918 if (rc == 0)
2919 return 0;
623a3128
TH		 2920
2921 fail:
f15a1daf 2922 ata_dev_printk(dev, KERN_ERR, "revalidation failed (errno=%d)\n", rc);
623a3128
TH		 2923 return rc;
2924}
2925
98ac62de 2926static const char * const ata_dma_blacklist [] = {
f4b15fef
AC		 2927 "WDC AC11000H", NULL,
2928 "WDC AC22100H", NULL,
2929 "WDC AC32500H", NULL,
2930 "WDC AC33100H", NULL,
2931 "WDC AC31600H", NULL,
2932 "WDC AC32100H", "24.09P07",
2933 "WDC AC23200L", "21.10N21",
2934 "Compaq CRD-8241B", NULL,
2935 "CRD-8400B", NULL,
2936 "CRD-8480B", NULL,
2937 "CRD-8482B", NULL,
2938 "CRD-84", NULL,
2939 "SanDisk SDP3B", NULL,
2940 "SanDisk SDP3B-64", NULL,
2941 "SANYO CD-ROM CRD", NULL,
2942 "HITACHI CDR-8", NULL,
2e9edbf8 2943 "HITACHI CDR-8335", NULL,
f4b15fef 2944 "HITACHI CDR-8435", NULL,
2e9edbf8
JG		 2945 "Toshiba CD-ROM XM-6202B", NULL,
2946 "TOSHIBA CD-ROM XM-1702BC", NULL,
2947 "CD-532E-A", NULL,
2948 "E-IDE CD-ROM CR-840", NULL,
2949 "CD-ROM Drive/F5A", NULL,
2950 "WPI CDD-820", NULL,
f4b15fef 2951 "SAMSUNG CD-ROM SC-148C", NULL,
2e9edbf8 2952 "SAMSUNG CD-ROM SC", NULL,
f4b15fef
AC		 2953 "SanDisk SDP3B-64", NULL,
2954 "ATAPI CD-ROM DRIVE 40X MAXIMUM",NULL,
2955 "_NEC DV5800A", NULL,
2956 "SAMSUNG CD-ROM SN-124", "N001"
1da177e4 2957};
2e9edbf8 2958
f4b15fef
AC		 2959static int ata_strim(char *s, size_t len)
2960{
2961 len = strnlen(s, len);
2962
2963 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2964 while ((len > 0) && (s[len - 1] == ' ')) {
2965 len--;
2966 s[len] = 0;
2967 }
2968 return len;
2969}
1da177e4 2970
057ace5e 2971static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4 2972{
f4b15fef
AC		 2973 unsigned char model_num[40];
2974 unsigned char model_rev[16];
2975 unsigned int nlen, rlen;
1da177e4
LT		 2976 int i;
2977
f4b15fef
AC		 2978 ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2979 sizeof(model_num));
2980 ata_id_string(dev->id, model_rev, ATA_ID_FW_REV_OFS,
2981 sizeof(model_rev));
2982 nlen = ata_strim(model_num, sizeof(model_num));
2983 rlen = ata_strim(model_rev, sizeof(model_rev));
1da177e4 2984
f4b15fef
AC		 2985 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i += 2) {
2986 if (!strncmp(ata_dma_blacklist[i], model_num, nlen)) {
2987 if (ata_dma_blacklist[i+1] == NULL)
2988 return 1;
2989 if (!strncmp(ata_dma_blacklist[i], model_rev, rlen))
2990 return 1;
2991 }
2992 }
1da177e4
LT		 2993 return 0;
2994}
2995
a6d5a51c
TH		 2996/**
2997 * ata_dev_xfermask - Compute supported xfermask of the given device
a6d5a51c
TH		 2998 * @dev: Device to compute xfermask for
2999 *
acf356b1
TH		 3000 * Compute supported xfermask of @dev and store it in
3001 * dev->*_mask. This function is responsible for applying all
3002 * known limits including host controller limits, device
3003 * blacklist, etc...
a6d5a51c 3004 *
600511e8
TH		 3005 * FIXME: The current implementation limits all transfer modes to
3006 * the fastest of the lowested device on the port. This is not
05c8e0ac 3007 * required on most controllers.
600511e8 3008 *
a6d5a51c
TH		 3009 * LOCKING:
3010 * None.
a6d5a51c 3011 */
3373efd8 3012static void ata_dev_xfermask(struct ata_device *dev)
1da177e4 3013{
3373efd8 3014 struct ata_port *ap = dev->ap;
5444a6f4 3015 struct ata_host_set *hs = ap->host_set;
a6d5a51c
TH		 3016 unsigned long xfer_mask;
3017 int i;
1da177e4 3018
565083e1
TH		 3019 xfer_mask = ata_pack_xfermask(ap->pio_mask,
3020 ap->mwdma_mask, ap->udma_mask);
3021
3022 /* Apply cable rule here. Don't apply it early because when
3023 * we handle hot plug the cable type can itself change.
3024 */
3025 if (ap->cbl == ATA_CBL_PATA40)
3026 xfer_mask &= ~(0xF8 << ATA_SHIFT_UDMA);
1da177e4 3027
5444a6f4 3028 /* FIXME: Use port-wide xfermask for now */
a6d5a51c
TH		 3029 for (i = 0; i < ATA_MAX_DEVICES; i++) {
3030 struct ata_device *d = &ap->device[i];
565083e1
TH		 3031
3032 if (ata_dev_absent(d))
3033 continue;
3034
3035 if (ata_dev_disabled(d)) {
3036 /* to avoid violating device selection timing */
3037 xfer_mask &= ata_pack_xfermask(d->pio_mask,
3038 UINT_MAX, UINT_MAX);
a6d5a51c 3039 continue;
565083e1
TH		 3040 }
3041
3042 xfer_mask &= ata_pack_xfermask(d->pio_mask,
3043 d->mwdma_mask, d->udma_mask);
a6d5a51c
TH		 3044 xfer_mask &= ata_id_xfermask(d->id);
3045 if (ata_dma_blacklisted(d))
3046 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
1da177e4
LT		 3047 }
3048
a6d5a51c 3049 if (ata_dma_blacklisted(dev))
f15a1daf
TH		 3050 ata_dev_printk(dev, KERN_WARNING,
3051 "device is on DMA blacklist, disabling DMA\n");
a6d5a51c 3052
5444a6f4
AC		 3053 if (hs->flags & ATA_HOST_SIMPLEX) {
3054 if (hs->simplex_claimed)
3055 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
3056 }
565083e1 3057
5444a6f4
AC		 3058 if (ap->ops->mode_filter)
3059 xfer_mask = ap->ops->mode_filter(ap, dev, xfer_mask);
3060
565083e1
TH		 3061 ata_unpack_xfermask(xfer_mask, &dev->pio_mask,
3062 &dev->mwdma_mask, &dev->udma_mask);
1da177e4
LT		 3063}
3064
1da177e4
LT		 3065/**
3066 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
1da177e4
LT		 3067 * @dev: Device to which command will be sent
3068 *
780a87f7
JG		 3069 * Issue SET FEATURES - XFER MODE command to device @dev
3070 * on port @ap.
3071 *
1da177e4 3072 * LOCKING:
0cba632b 3073 * PCI/etc. bus probe sem.
83206a29
TH		 3074 *
3075 * RETURNS:
3076 * 0 on success, AC_ERR_* mask otherwise.
1da177e4
LT		 3077 */
3078
3373efd8 3079static unsigned int ata_dev_set_xfermode(struct ata_device *dev)
1da177e4 3080{
a0123703 3081 struct ata_taskfile tf;
83206a29 3082 unsigned int err_mask;
1da177e4
LT		 3083
3084 /* set up set-features taskfile */
3085 DPRINTK("set features - xfer mode\n");
3086
3373efd8 3087 ata_tf_init(dev, &tf);
a0123703
TH		 3088 tf.command = ATA_CMD_SET_FEATURES;
3089 tf.feature = SETFEATURES_XFER;
3090 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
3091 tf.protocol = ATA_PROT_NODATA;
3092 tf.nsect = dev->xfer_mode;
1da177e4 3093
3373efd8 3094 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
1da177e4 3095
83206a29
TH		 3096 DPRINTK("EXIT, err_mask=%x\n", err_mask);
3097 return err_mask;
1da177e4
LT		 3098}
3099
8bf62ece
AL		 3100/**
3101 * ata_dev_init_params - Issue INIT DEV PARAMS command
8bf62ece 3102 * @dev: Device to which command will be sent
e2a7f77a
RD		 3103 * @heads: Number of heads (taskfile parameter)
3104 * @sectors: Number of sectors (taskfile parameter)
8bf62ece
AL		 3105 *
3106 * LOCKING:
6aff8f1f
TH		 3107 * Kernel thread context (may sleep)
3108 *
3109 * RETURNS:
3110 * 0 on success, AC_ERR_* mask otherwise.
8bf62ece 3111 */
3373efd8
TH		 3112static unsigned int ata_dev_init_params(struct ata_device *dev,
3113 u16 heads, u16 sectors)
8bf62ece 3114{
a0123703 3115 struct ata_taskfile tf;
6aff8f1f 3116 unsigned int err_mask;
8bf62ece
AL		 3117
3118 /* Number of sectors per track 1-255. Number of heads 1-16 */
3119 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
00b6f5e9 3120 return AC_ERR_INVALID;
8bf62ece
AL		 3121
3122 /* set up init dev params taskfile */
3123 DPRINTK("init dev params \n");
3124
3373efd8 3125 ata_tf_init(dev, &tf);
a0123703
TH		 3126 tf.command = ATA_CMD_INIT_DEV_PARAMS;
3127 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
3128 tf.protocol = ATA_PROT_NODATA;
3129 tf.nsect = sectors;
3130 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 3131
3373efd8 3132 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
8bf62ece 3133
6aff8f1f
TH		 3134 DPRINTK("EXIT, err_mask=%x\n", err_mask);
3135 return err_mask;
8bf62ece
AL		 3136}
3137
1da177e4 3138/**
0cba632b
JG		 3139 * ata_sg_clean - Unmap DMA memory associated with command
3140 * @qc: Command containing DMA memory to be released
3141 *
3142 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 3143 *
3144 * LOCKING:
0cba632b 3145 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3146 */
3147
3148static void ata_sg_clean(struct ata_queued_cmd *qc)
3149{
3150 struct ata_port *ap = qc->ap;
cedc9a47 3151 struct scatterlist *sg = qc->__sg;
1da177e4 3152 int dir = qc->dma_dir;
cedc9a47 3153 void *pad_buf = NULL;
1da177e4 3154
a4631474
TH		 3155 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
3156 WARN_ON(sg == NULL);
1da177e4
LT		 3157
3158 if (qc->flags & ATA_QCFLAG_SINGLE)
f131883e 3159 WARN_ON(qc->n_elem > 1);
1da177e4 3160
2c13b7ce 3161 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 3162
cedc9a47
JG		 3163 /* if we padded the buffer out to 32-bit bound, and data
3164 * xfer direction is from-device, we must copy from the
3165 * pad buffer back into the supplied buffer
3166 */
3167 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
3168 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3169
3170 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d 3171 if (qc->n_elem)
2f1f610b 3172 dma_unmap_sg(ap->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 3173 /* restore last sg */
3174 sg[qc->orig_n_elem - 1].length += qc->pad_len;
3175 if (pad_buf) {
3176 struct scatterlist *psg = &qc->pad_sgent;
3177 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3178 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 3179 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3180 }
3181 } else {
2e242fa9 3182 if (qc->n_elem)
2f1f610b 3183 dma_unmap_single(ap->dev,
e1410f2d
JG		 3184 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
3185 dir);
cedc9a47
JG		 3186 /* restore sg */
3187 sg->length += qc->pad_len;
3188 if (pad_buf)
3189 memcpy(qc->buf_virt + sg->length - qc->pad_len,
3190 pad_buf, qc->pad_len);
3191 }
1da177e4
LT		 3192
3193 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 3194 qc->__sg = NULL;
1da177e4
LT		 3195}
3196
3197/**
3198 * ata_fill_sg - Fill PCI IDE PRD table
3199 * @qc: Metadata associated with taskfile to be transferred
3200 *
780a87f7
JG		 3201 * Fill PCI IDE PRD (scatter-gather) table with segments
3202 * associated with the current disk command.
3203 *
1da177e4 3204 * LOCKING:
780a87f7 3205 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3206 *
3207 */
3208static void ata_fill_sg(struct ata_queued_cmd *qc)
3209{
1da177e4 3210 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3211 struct scatterlist *sg;
3212 unsigned int idx;
1da177e4 3213
a4631474 3214 WARN_ON(qc->__sg == NULL);
f131883e 3215 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
1da177e4
LT		 3216
3217 idx = 0;
cedc9a47 3218 ata_for_each_sg(sg, qc) {
1da177e4
LT		 3219 u32 addr, offset;
3220 u32 sg_len, len;
3221
3222 /* determine if physical DMA addr spans 64K boundary.
3223 * Note h/w doesn't support 64-bit, so we unconditionally
3224 * truncate dma_addr_t to u32.
3225 */
3226 addr = (u32) sg_dma_address(sg);
3227 sg_len = sg_dma_len(sg);
3228
3229 while (sg_len) {
3230 offset = addr & 0xffff;
3231 len = sg_len;
3232 if ((offset + sg_len) > 0x10000)
3233 len = 0x10000 - offset;
3234
3235 ap->prd[idx].addr = cpu_to_le32(addr);
3236 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
3237 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
3238
3239 idx++;
3240 sg_len -= len;
3241 addr += len;
3242 }
3243 }
3244
3245 if (idx)
3246 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
3247}
3248/**
3249 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
3250 * @qc: Metadata associated with taskfile to check
3251 *
780a87f7
JG		 3252 * Allow low-level driver to filter ATA PACKET commands, returning
3253 * a status indicating whether or not it is OK to use DMA for the
3254 * supplied PACKET command.
3255 *
1da177e4 3256 * LOCKING:
0cba632b
JG		 3257 * spin_lock_irqsave(host_set lock)
3258 *
1da177e4
LT		 3259 * RETURNS: 0 when ATAPI DMA can be used
3260 * nonzero otherwise
3261 */
3262int ata_check_atapi_dma(struct ata_queued_cmd *qc)
3263{
3264 struct ata_port *ap = qc->ap;
3265 int rc = 0; /* Assume ATAPI DMA is OK by default */
3266
3267 if (ap->ops->check_atapi_dma)
3268 rc = ap->ops->check_atapi_dma(qc);
3269
c2bbc551
AL		 3270 /* We don't support polling DMA.
3271 * Use PIO if the LLDD handles only interrupts in
3272 * the HSM_ST_LAST state and the ATAPI device
3273 * generates CDB interrupts.
3274 */
3275 if ((ap->flags & ATA_FLAG_PIO_POLLING) &&
3276 (qc->dev->flags & ATA_DFLAG_CDB_INTR))
3277 rc = 1;
3278
1da177e4
LT		 3279 return rc;
3280}
3281/**
3282 * ata_qc_prep - Prepare taskfile for submission
3283 * @qc: Metadata associated with taskfile to be prepared
3284 *
780a87f7
JG		 3285 * Prepare ATA taskfile for submission.
3286 *
1da177e4
LT		 3287 * LOCKING:
3288 * spin_lock_irqsave(host_set lock)
3289 */
3290void ata_qc_prep(struct ata_queued_cmd *qc)
3291{
3292 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
3293 return;
3294
3295 ata_fill_sg(qc);
3296}
3297
e46834cd
BK		 3298void ata_noop_qc_prep(struct ata_queued_cmd *qc) { }
3299
0cba632b
JG		 3300/**
3301 * ata_sg_init_one - Associate command with memory buffer
3302 * @qc: Command to be associated
3303 * @buf: Memory buffer
3304 * @buflen: Length of memory buffer, in bytes.
3305 *
3306 * Initialize the data-related elements of queued_cmd @qc
3307 * to point to a single memory buffer, @buf of byte length @buflen.
3308 *
3309 * LOCKING:
3310 * spin_lock_irqsave(host_set lock)
3311 */
3312
1da177e4
LT		 3313void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
3314{
3315 struct scatterlist *sg;
3316
3317 qc->flags |= ATA_QCFLAG_SINGLE;
3318
3319 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 3320 qc->__sg = &qc->sgent;
1da177e4 3321 qc->n_elem = 1;
cedc9a47 3322 qc->orig_n_elem = 1;
1da177e4
LT		 3323 qc->buf_virt = buf;
3324
cedc9a47 3325 sg = qc->__sg;
f0612bbc 3326 sg_init_one(sg, buf, buflen);
1da177e4
LT		 3327}
3328
0cba632b
JG		 3329/**
3330 * ata_sg_init - Associate command with scatter-gather table.
3331 * @qc: Command to be associated
3332 * @sg: Scatter-gather table.
3333 * @n_elem: Number of elements in s/g table.
3334 *
3335 * Initialize the data-related elements of queued_cmd @qc
3336 * to point to a scatter-gather table @sg, containing @n_elem
3337 * elements.
3338 *
3339 * LOCKING:
3340 * spin_lock_irqsave(host_set lock)
3341 */
3342
1da177e4
LT		 3343void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
3344 unsigned int n_elem)
3345{
3346 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 3347 qc->__sg = sg;
1da177e4 3348 qc->n_elem = n_elem;
cedc9a47 3349 qc->orig_n_elem = n_elem;
1da177e4
LT		 3350}
3351
3352/**
0cba632b
JG		 3353 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
3354 * @qc: Command with memory buffer to be mapped.
3355 *
3356 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 3357 *
3358 * LOCKING:
3359 * spin_lock_irqsave(host_set lock)
3360 *
3361 * RETURNS:
0cba632b 3362 * Zero on success, negative on error.
1da177e4
LT		 3363 */
3364
3365static int ata_sg_setup_one(struct ata_queued_cmd *qc)
3366{
3367 struct ata_port *ap = qc->ap;
3368 int dir = qc->dma_dir;
cedc9a47 3369 struct scatterlist *sg = qc->__sg;
1da177e4 3370 dma_addr_t dma_address;
2e242fa9 3371 int trim_sg = 0;
1da177e4 3372
cedc9a47
JG		 3373 /* we must lengthen transfers to end on a 32-bit boundary */
3374 qc->pad_len = sg->length & 3;
3375 if (qc->pad_len) {
3376 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3377 struct scatterlist *psg = &qc->pad_sgent;
3378
a4631474 3379 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3380
3381 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3382
3383 if (qc->tf.flags & ATA_TFLAG_WRITE)
3384 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
3385 qc->pad_len);
3386
3387 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3388 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3389 /* trim sg */
3390 sg->length -= qc->pad_len;
2e242fa9
TH		 3391 if (sg->length == 0)
3392 trim_sg = 1;
cedc9a47
JG		 3393
3394 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
3395 sg->length, qc->pad_len);
3396 }
3397
2e242fa9
TH		 3398 if (trim_sg) {
3399 qc->n_elem--;
e1410f2d
JG		 3400 goto skip_map;
3401 }
3402
2f1f610b 3403 dma_address = dma_map_single(ap->dev, qc->buf_virt,
32529e01 3404 sg->length, dir);
537a95d9
TH		 3405 if (dma_mapping_error(dma_address)) {
3406 /* restore sg */
3407 sg->length += qc->pad_len;
1da177e4 3408 return -1;
537a95d9 3409 }
1da177e4
LT		 3410
3411 sg_dma_address(sg) = dma_address;
32529e01 3412 sg_dma_len(sg) = sg->length;
1da177e4 3413
2e242fa9 3414skip_map:
1da177e4
LT		 3415 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
3416 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3417
3418 return 0;
3419}
3420
3421/**
0cba632b
JG		 3422 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
3423 * @qc: Command with scatter-gather table to be mapped.
3424 *
3425 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 3426 *
3427 * LOCKING:
3428 * spin_lock_irqsave(host_set lock)
3429 *
3430 * RETURNS:
0cba632b 3431 * Zero on success, negative on error.
1da177e4
LT		 3432 *
3433 */
3434
3435static int ata_sg_setup(struct ata_queued_cmd *qc)
3436{
3437 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3438 struct scatterlist *sg = qc->__sg;
3439 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 3440 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 3441
3442 VPRINTK("ENTER, ata%u\n", ap->id);
a4631474 3443 WARN_ON(!(qc->flags & ATA_QCFLAG_SG));
1da177e4 3444
cedc9a47
JG		 3445 /* we must lengthen transfers to end on a 32-bit boundary */
3446 qc->pad_len = lsg->length & 3;
3447 if (qc->pad_len) {
3448 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3449 struct scatterlist *psg = &qc->pad_sgent;
3450 unsigned int offset;
3451
a4631474 3452 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3453
3454 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3455
3456 /*
3457 * psg->page/offset are used to copy to-be-written
3458 * data in this function or read data in ata_sg_clean.
3459 */
3460 offset = lsg->offset + lsg->length - qc->pad_len;
3461 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
3462 psg->offset = offset_in_page(offset);
3463
3464 if (qc->tf.flags & ATA_TFLAG_WRITE) {
3465 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3466 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 3467 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3468 }
3469
3470 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3471 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3472 /* trim last sg */
3473 lsg->length -= qc->pad_len;
e1410f2d
JG		 3474 if (lsg->length == 0)
3475 trim_sg = 1;
cedc9a47
JG		 3476
3477 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
3478 qc->n_elem - 1, lsg->length, qc->pad_len);
3479 }
3480
e1410f2d
JG		 3481 pre_n_elem = qc->n_elem;
3482 if (trim_sg && pre_n_elem)
3483 pre_n_elem--;
3484
3485 if (!pre_n_elem) {
3486 n_elem = 0;
3487 goto skip_map;
3488 }
3489
1da177e4 3490 dir = qc->dma_dir;
2f1f610b 3491 n_elem = dma_map_sg(ap->dev, sg, pre_n_elem, dir);
537a95d9
TH		 3492 if (n_elem < 1) {
3493 /* restore last sg */
3494 lsg->length += qc->pad_len;
1da177e4 3495 return -1;
537a95d9 3496 }
1da177e4
LT		 3497
3498 DPRINTK("%d sg elements mapped\n", n_elem);
3499
e1410f2d 3500skip_map:
1da177e4
LT		 3501 qc->n_elem = n_elem;
3502
3503 return 0;
3504}
3505
0baab86b 3506/**
c893a3ae 3507 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF		 3508 * @buf: Buffer to swap
3509 * @buf_words: Number of 16-bit words in buffer.
3510 *
3511 * Swap halves of 16-bit words if needed to convert from
3512 * little-endian byte order to native cpu byte order, or
3513 * vice-versa.
3514 *
3515 * LOCKING:
6f0ef4fa 3516 * Inherited from caller.
0baab86b 3517 */
1da177e4
LT		 3518void swap_buf_le16(u16 *buf, unsigned int buf_words)
3519{
3520#ifdef __BIG_ENDIAN
3521 unsigned int i;
3522
3523 for (i = 0; i < buf_words; i++)
3524 buf[i] = le16_to_cpu(buf[i]);
3525#endif /* __BIG_ENDIAN */
3526}
3527
6ae4cfb5
AL		 3528/**
3529 * ata_mmio_data_xfer - Transfer data by MMIO
a6b2c5d4 3530 * @dev: device for this I/O
6ae4cfb5
AL		 3531 * @buf: data buffer
3532 * @buflen: buffer length
344babaa 3533 * @write_data: read/write
6ae4cfb5
AL		 3534 *
3535 * Transfer data from/to the device data register by MMIO.
3536 *
3537 * LOCKING:
3538 * Inherited from caller.
6ae4cfb5
AL		 3539 */
3540
a6b2c5d4
AC		 3541void ata_mmio_data_xfer(struct ata_device *adev, unsigned char *buf,
3542 unsigned int buflen, int write_data)
1da177e4 3543{
a6b2c5d4 3544 struct ata_port *ap = adev->ap;
1da177e4
LT		 3545 unsigned int i;
3546 unsigned int words = buflen >> 1;
3547 u16 *buf16 = (u16 *) buf;
3548 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3549
6ae4cfb5 3550 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3551 if (write_data) {
3552 for (i = 0; i < words; i++)
3553 writew(le16_to_cpu(buf16[i]), mmio);
3554 } else {
3555 for (i = 0; i < words; i++)
3556 buf16[i] = cpu_to_le16(readw(mmio));
3557 }
6ae4cfb5
AL		 3558
3559 /* Transfer trailing 1 byte, if any. */
3560 if (unlikely(buflen & 0x01)) {
3561 u16 align_buf[1] = { 0 };
3562 unsigned char *trailing_buf = buf + buflen - 1;
3563
3564 if (write_data) {
3565 memcpy(align_buf, trailing_buf, 1);
3566 writew(le16_to_cpu(align_buf[0]), mmio);
3567 } else {
3568 align_buf[0] = cpu_to_le16(readw(mmio));
3569 memcpy(trailing_buf, align_buf, 1);
3570 }
3571 }
1da177e4
LT		 3572}
3573
6ae4cfb5
AL		 3574/**
3575 * ata_pio_data_xfer - Transfer data by PIO
a6b2c5d4 3576 * @adev: device to target
6ae4cfb5
AL		 3577 * @buf: data buffer
3578 * @buflen: buffer length
344babaa 3579 * @write_data: read/write
6ae4cfb5
AL		 3580 *
3581 * Transfer data from/to the device data register by PIO.
3582 *
3583 * LOCKING:
3584 * Inherited from caller.
6ae4cfb5
AL		 3585 */
3586
a6b2c5d4
AC		 3587void ata_pio_data_xfer(struct ata_device *adev, unsigned char *buf,
3588 unsigned int buflen, int write_data)
1da177e4 3589{
a6b2c5d4 3590 struct ata_port *ap = adev->ap;
6ae4cfb5 3591 unsigned int words = buflen >> 1;
1da177e4 3592
6ae4cfb5 3593 /* Transfer multiple of 2 bytes */
1da177e4 3594 if (write_data)
6ae4cfb5 3595 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3596 else
6ae4cfb5
AL		 3597 insw(ap->ioaddr.data_addr, buf, words);
3598
3599 /* Transfer trailing 1 byte, if any. */
3600 if (unlikely(buflen & 0x01)) {
3601 u16 align_buf[1] = { 0 };
3602 unsigned char *trailing_buf = buf + buflen - 1;
3603
3604 if (write_data) {
3605 memcpy(align_buf, trailing_buf, 1);
3606 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3607 } else {
3608 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3609 memcpy(trailing_buf, align_buf, 1);
3610 }
3611 }
1da177e4
LT		 3612}
3613
75e99585
AC		 3614/**
3615 * ata_pio_data_xfer_noirq - Transfer data by PIO
3616 * @adev: device to target
3617 * @buf: data buffer
3618 * @buflen: buffer length
3619 * @write_data: read/write
3620 *
3621 * Transfer data from/to the device data register by PIO. Do the
3622 * transfer with interrupts disabled.
3623 *
3624 * LOCKING:
3625 * Inherited from caller.
3626 */
3627
3628void ata_pio_data_xfer_noirq(struct ata_device *adev, unsigned char *buf,
3629 unsigned int buflen, int write_data)
3630{
3631 unsigned long flags;
3632 local_irq_save(flags);
3633 ata_pio_data_xfer(adev, buf, buflen, write_data);
3634 local_irq_restore(flags);
3635}
3636
3637
6ae4cfb5
AL		 3638/**
3639 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3640 * @qc: Command on going
3641 *
3642 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3643 *
3644 * LOCKING:
3645 * Inherited from caller.
3646 */
3647
1da177e4
LT		 3648static void ata_pio_sector(struct ata_queued_cmd *qc)
3649{
3650 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3651 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3652 struct ata_port *ap = qc->ap;
3653 struct page *page;
3654 unsigned int offset;
3655 unsigned char *buf;
3656
3657 if (qc->cursect == (qc->nsect - 1))
14be71f4 3658 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3659
3660 page = sg[qc->cursg].page;
3661 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3662
3663 /* get the current page and offset */
3664 page = nth_page(page, (offset >> PAGE_SHIFT));
3665 offset %= PAGE_SIZE;
3666
1da177e4
LT		 3667 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3668
91b8b313
AL		 3669 if (PageHighMem(page)) {
3670 unsigned long flags;
3671
a6b2c5d4 3672 /* FIXME: use a bounce buffer */
91b8b313
AL		 3673 local_irq_save(flags);
3674 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3675
91b8b313 3676 /* do the actual data transfer */
a6b2c5d4 3677 ap->ops->data_xfer(qc->dev, buf + offset, ATA_SECT_SIZE, do_write);
1da177e4 3678
91b8b313
AL		 3679 kunmap_atomic(buf, KM_IRQ0);
3680 local_irq_restore(flags);
3681 } else {
3682 buf = page_address(page);
a6b2c5d4 3683 ap->ops->data_xfer(qc->dev, buf + offset, ATA_SECT_SIZE, do_write);
91b8b313 3684 }
1da177e4
LT		 3685
3686 qc->cursect++;
3687 qc->cursg_ofs++;
3688
32529e01 3689 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3690 qc->cursg++;
3691 qc->cursg_ofs = 0;
3692 }
1da177e4 3693}
1da177e4 3694
07f6f7d0
AL		 3695/**
3696 * ata_pio_sectors - Transfer one or many 512-byte sectors.
3697 * @qc: Command on going
3698 *
c81e29b4 3699 * Transfer one or many ATA_SECT_SIZE of data from/to the
07f6f7d0
AL		 3700 * ATA device for the DRQ request.
3701 *
3702 * LOCKING:
3703 * Inherited from caller.
3704 */
1da177e4 3705
07f6f7d0
AL		 3706static void ata_pio_sectors(struct ata_queued_cmd *qc)
3707{
3708 if (is_multi_taskfile(&qc->tf)) {
3709 /* READ/WRITE MULTIPLE */
3710 unsigned int nsect;
3711
587005de 3712 WARN_ON(qc->dev->multi_count == 0);
1da177e4 3713
07f6f7d0
AL		 3714 nsect = min(qc->nsect - qc->cursect, qc->dev->multi_count);
3715 while (nsect--)
3716 ata_pio_sector(qc);
3717 } else
3718 ata_pio_sector(qc);
3719}
3720
c71c1857
AL		 3721/**
3722 * atapi_send_cdb - Write CDB bytes to hardware
3723 * @ap: Port to which ATAPI device is attached.
3724 * @qc: Taskfile currently active
3725 *
3726 * When device has indicated its readiness to accept
3727 * a CDB, this function is called. Send the CDB.
3728 *
3729 * LOCKING:
3730 * caller.
3731 */
3732
3733static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
3734{
3735 /* send SCSI cdb */
3736 DPRINTK("send cdb\n");
db024d53 3737 WARN_ON(qc->dev->cdb_len < 12);
c71c1857 3738
a6b2c5d4 3739 ap->ops->data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
c71c1857
AL		 3740 ata_altstatus(ap); /* flush */
3741
3742 switch (qc->tf.protocol) {
3743 case ATA_PROT_ATAPI:
3744 ap->hsm_task_state = HSM_ST;
3745 break;
3746 case ATA_PROT_ATAPI_NODATA:
3747 ap->hsm_task_state = HSM_ST_LAST;
3748 break;
3749 case ATA_PROT_ATAPI_DMA:
3750 ap->hsm_task_state = HSM_ST_LAST;
3751 /* initiate bmdma */
3752 ap->ops->bmdma_start(qc);
3753 break;
3754 }
1da177e4
LT		 3755}
3756
6ae4cfb5
AL		 3757/**
3758 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3759 * @qc: Command on going
3760 * @bytes: number of bytes
3761 *
3762 * Transfer Transfer data from/to the ATAPI device.
3763 *
3764 * LOCKING:
3765 * Inherited from caller.
3766 *
3767 */
3768
1da177e4
LT		 3769static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3770{
3771 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3772 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3773 struct ata_port *ap = qc->ap;
3774 struct page *page;
3775 unsigned char *buf;
3776 unsigned int offset, count;
3777
563a6e1f 3778 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3779 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3780
3781next_sg:
563a6e1f 3782 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3783 /*
563a6e1f
AL		 3784 * The end of qc->sg is reached and the device expects
3785 * more data to transfer. In order not to overrun qc->sg
3786 * and fulfill length specified in the byte count register,
3787 * - for read case, discard trailing data from the device
3788 * - for write case, padding zero data to the device
3789 */
3790 u16 pad_buf[1] = { 0 };
3791 unsigned int words = bytes >> 1;
3792 unsigned int i;
3793
3794 if (words) /* warning if bytes > 1 */
f15a1daf
TH		 3795 ata_dev_printk(qc->dev, KERN_WARNING,
3796 "%u bytes trailing data\n", bytes);
563a6e1f
AL		 3797
3798 for (i = 0; i < words; i++)
a6b2c5d4 3799 ap->ops->data_xfer(qc->dev, (unsigned char*)pad_buf, 2, do_write);
563a6e1f 3800
14be71f4 3801 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3802 return;
3803 }
3804
cedc9a47 3805 sg = &qc->__sg[qc->cursg];
1da177e4 3806
1da177e4
LT		 3807 page = sg->page;
3808 offset = sg->offset + qc->cursg_ofs;
3809
3810 /* get the current page and offset */
3811 page = nth_page(page, (offset >> PAGE_SHIFT));
3812 offset %= PAGE_SIZE;
3813
6952df03 3814 /* don't overrun current sg */
32529e01 3815 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3816
3817 /* don't cross page boundaries */
3818 count = min(count, (unsigned int)PAGE_SIZE - offset);
3819
7282aa4b
AL		 3820 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3821
91b8b313
AL		 3822 if (PageHighMem(page)) {
3823 unsigned long flags;
3824
a6b2c5d4 3825 /* FIXME: use bounce buffer */
91b8b313
AL		 3826 local_irq_save(flags);
3827 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3828
91b8b313 3829 /* do the actual data transfer */
a6b2c5d4 3830 ap->ops->data_xfer(qc->dev, buf + offset, count, do_write);
7282aa4b 3831
91b8b313
AL		 3832 kunmap_atomic(buf, KM_IRQ0);
3833 local_irq_restore(flags);
3834 } else {
3835 buf = page_address(page);
a6b2c5d4 3836 ap->ops->data_xfer(qc->dev, buf + offset, count, do_write);
91b8b313 3837 }
1da177e4
LT		 3838
3839 bytes -= count;
3840 qc->curbytes += count;
3841 qc->cursg_ofs += count;
3842
32529e01 3843 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3844 qc->cursg++;
3845 qc->cursg_ofs = 0;
3846 }
3847
563a6e1f 3848 if (bytes)
1da177e4 3849 goto next_sg;
1da177e4
LT		 3850}
3851
6ae4cfb5
AL		 3852/**
3853 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3854 * @qc: Command on going
3855 *
3856 * Transfer Transfer data from/to the ATAPI device.
3857 *
3858 * LOCKING:
3859 * Inherited from caller.
6ae4cfb5
AL		 3860 */
3861
1da177e4
LT		 3862static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3863{
3864 struct ata_port *ap = qc->ap;
3865 struct ata_device *dev = qc->dev;
3866 unsigned int ireason, bc_lo, bc_hi, bytes;
3867 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3868
eec4c3f3
AL		 3869 /* Abuse qc->result_tf for temp storage of intermediate TF
3870 * here to save some kernel stack usage.
3871 * For normal completion, qc->result_tf is not relevant. For
3872 * error, qc->result_tf is later overwritten by ata_qc_complete().
3873 * So, the correctness of qc->result_tf is not affected.
3874 */
3875 ap->ops->tf_read(ap, &qc->result_tf);
3876 ireason = qc->result_tf.nsect;
3877 bc_lo = qc->result_tf.lbam;
3878 bc_hi = qc->result_tf.lbah;
1da177e4
LT		 3879 bytes = (bc_hi << 8) | bc_lo;
3880
3881 /* shall be cleared to zero, indicating xfer of data */
3882 if (ireason & (1 << 0))
3883 goto err_out;
3884
3885 /* make sure transfer direction matches expected */
3886 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3887 if (do_write != i_write)
3888 goto err_out;
3889
312f7da2
AL		 3890 VPRINTK("ata%u: xfering %d bytes\n", ap->id, bytes);
3891
1da177e4
LT		 3892 __atapi_pio_bytes(qc, bytes);
3893
3894 return;
3895
3896err_out:
f15a1daf 3897 ata_dev_printk(dev, KERN_INFO, "ATAPI check failed\n");
11a56d24 3898 qc->err_mask |= AC_ERR_HSM;
14be71f4 3899 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3900}
3901
3902/**
c234fb00
AL		 3903 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
3904 * @ap: the target ata_port
3905 * @qc: qc on going
1da177e4 3906 *
c234fb00
AL		 3907 * RETURNS:
3908 * 1 if ok in workqueue, 0 otherwise.
1da177e4 3909 */
c234fb00
AL		 3910
3911static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
1da177e4 3912{
c234fb00
AL		 3913 if (qc->tf.flags & ATA_TFLAG_POLLING)
3914 return 1;
1da177e4 3915
c234fb00
AL		 3916 if (ap->hsm_task_state == HSM_ST_FIRST) {
3917 if (qc->tf.protocol == ATA_PROT_PIO &&
3918 (qc->tf.flags & ATA_TFLAG_WRITE))
3919 return 1;
1da177e4 3920
c234fb00
AL		 3921 if (is_atapi_taskfile(&qc->tf) &&
3922 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
3923 return 1;
fe79e683
AL		 3924 }
3925
c234fb00
AL		 3926 return 0;
3927}
1da177e4 3928
c17ea20d
TH		 3929/**
3930 * ata_hsm_qc_complete - finish a qc running on standard HSM
3931 * @qc: Command to complete
3932 * @in_wq: 1 if called from workqueue, 0 otherwise
3933 *
3934 * Finish @qc which is running on standard HSM.
3935 *
3936 * LOCKING:
3937 * If @in_wq is zero, spin_lock_irqsave(host_set lock).
3938 * Otherwise, none on entry and grabs host lock.
3939 */
3940static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
3941{
3942 struct ata_port *ap = qc->ap;
3943 unsigned long flags;
3944
3945 if (ap->ops->error_handler) {
3946 if (in_wq) {
3947 spin_lock_irqsave(&ap->host_set->lock, flags);
3948
3949 /* EH might have kicked in while host_set lock
3950 * is released.
3951 */
3952 qc = ata_qc_from_tag(ap, qc->tag);
3953 if (qc) {
3954 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
3955 ata_irq_on(ap);
3956 ata_qc_complete(qc);
3957 } else
3958 ata_port_freeze(ap);
3959 }
3960
3961 spin_unlock_irqrestore(&ap->host_set->lock, flags);
3962 } else {
3963 if (likely(!(qc->err_mask & AC_ERR_HSM)))
3964 ata_qc_complete(qc);
3965 else
3966 ata_port_freeze(ap);
3967 }
3968 } else {
3969 if (in_wq) {
3970 spin_lock_irqsave(&ap->host_set->lock, flags);
3971 ata_irq_on(ap);
3972 ata_qc_complete(qc);
3973 spin_unlock_irqrestore(&ap->host_set->lock, flags);
3974 } else
3975 ata_qc_complete(qc);
3976 }
1da177e4 3977
c81e29b4 3978 ata_altstatus(ap); /* flush */
c17ea20d
TH		 3979}
3980
bb5cb290
AL		 3981/**
3982 * ata_hsm_move - move the HSM to the next state.
3983 * @ap: the target ata_port
3984 * @qc: qc on going
3985 * @status: current device status
3986 * @in_wq: 1 if called from workqueue, 0 otherwise
3987 *
3988 * RETURNS:
3989 * 1 when poll next status needed, 0 otherwise.
3990 */
3991
3992static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
3993 u8 status, int in_wq)
e2cec771 3994{
bb5cb290
AL		 3995 unsigned long flags = 0;
3996 int poll_next;
3997
6912ccd5
AL		 3998 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
3999
bb5cb290
AL		 4000 /* Make sure ata_qc_issue_prot() does not throw things
4001 * like DMA polling into the workqueue. Notice that
4002 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
4003 */
c234fb00 4004 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
bb5cb290 4005
e2cec771 4006fsm_start:
999bb6f4
AL		 4007 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
4008 ap->id, qc->tf.protocol, ap->hsm_task_state, status);
4009
e2cec771
AL		 4010 switch (ap->hsm_task_state) {
4011 case HSM_ST_FIRST:
bb5cb290
AL		 4012 /* Send first data block or PACKET CDB */
4013
4014 /* If polling, we will stay in the work queue after
4015 * sending the data. Otherwise, interrupt handler
4016 * takes over after sending the data.
4017 */
4018 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
4019
e2cec771 4020 /* check device status */
3655d1d3
AL		 4021 if (unlikely((status & ATA_DRQ) == 0)) {
4022 /* handle BSY=0, DRQ=0 as error */
4023 if (likely(status & (ATA_ERR | ATA_DF)))
4024 /* device stops HSM for abort/error */
4025 qc->err_mask |= AC_ERR_DEV;
4026 else
4027 /* HSM violation. Let EH handle this */
4028 qc->err_mask |= AC_ERR_HSM;
4029
14be71f4 4030 ap->hsm_task_state = HSM_ST_ERR;
e2cec771 4031 goto fsm_start;
1da177e4
LT		 4032 }
4033
71601958
AL		 4034 /* Device should not ask for data transfer (DRQ=1)
4035 * when it finds something wrong.
eee6c32f
AL		 4036 * We ignore DRQ here and stop the HSM by
4037 * changing hsm_task_state to HSM_ST_ERR and
4038 * let the EH abort the command or reset the device.
71601958
AL		 4039 */
4040 if (unlikely(status & (ATA_ERR | ATA_DF))) {
4041 printk(KERN_WARNING "ata%d: DRQ=1 with device error, dev_stat 0x%X\n",
4042 ap->id, status);
3655d1d3 4043 qc->err_mask |= AC_ERR_HSM;
eee6c32f
AL		 4044 ap->hsm_task_state = HSM_ST_ERR;
4045 goto fsm_start;
71601958 4046 }
1da177e4 4047
bb5cb290
AL		 4048 /* Send the CDB (atapi) or the first data block (ata pio out).
4049 * During the state transition, interrupt handler shouldn't
4050 * be invoked before the data transfer is complete and
4051 * hsm_task_state is changed. Hence, the following locking.
4052 */
4053 if (in_wq)
4054 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 4055
bb5cb290
AL		 4056 if (qc->tf.protocol == ATA_PROT_PIO) {
4057 /* PIO data out protocol.
4058 * send first data block.
4059 */
0565c26d 4060
bb5cb290
AL		 4061 /* ata_pio_sectors() might change the state
4062 * to HSM_ST_LAST. so, the state is changed here
4063 * before ata_pio_sectors().
4064 */
4065 ap->hsm_task_state = HSM_ST;
4066 ata_pio_sectors(qc);
4067 ata_altstatus(ap); /* flush */
4068 } else
4069 /* send CDB */
4070 atapi_send_cdb(ap, qc);
4071
4072 if (in_wq)
4073 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4074
4075 /* if polling, ata_pio_task() handles the rest.
4076 * otherwise, interrupt handler takes over from here.
4077 */
e2cec771 4078 break;
1c848984 4079
e2cec771
AL		 4080 case HSM_ST:
4081 /* complete command or read/write the data register */
4082 if (qc->tf.protocol == ATA_PROT_ATAPI) {
4083 /* ATAPI PIO protocol */
4084 if ((status & ATA_DRQ) == 0) {
3655d1d3
AL		 4085 /* No more data to transfer or device error.
4086 * Device error will be tagged in HSM_ST_LAST.
4087 */
e2cec771
AL		 4088 ap->hsm_task_state = HSM_ST_LAST;
4089 goto fsm_start;
4090 }
1da177e4 4091
71601958
AL		 4092 /* Device should not ask for data transfer (DRQ=1)
4093 * when it finds something wrong.
eee6c32f
AL		 4094 * We ignore DRQ here and stop the HSM by
4095 * changing hsm_task_state to HSM_ST_ERR and
4096 * let the EH abort the command or reset the device.
71601958
AL		 4097 */
4098 if (unlikely(status & (ATA_ERR | ATA_DF))) {
4099 printk(KERN_WARNING "ata%d: DRQ=1 with device error, dev_stat 0x%X\n",
4100 ap->id, status);
3655d1d3 4101 qc->err_mask |= AC_ERR_HSM;
eee6c32f
AL		 4102 ap->hsm_task_state = HSM_ST_ERR;
4103 goto fsm_start;
71601958 4104 }
1da177e4 4105
e2cec771 4106 atapi_pio_bytes(qc);
7fb6ec28 4107
e2cec771
AL		 4108 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
4109 /* bad ireason reported by device */
4110 goto fsm_start;
1da177e4 4111
e2cec771
AL		 4112 } else {
4113 /* ATA PIO protocol */
4114 if (unlikely((status & ATA_DRQ) == 0)) {
4115 /* handle BSY=0, DRQ=0 as error */
3655d1d3
AL		 4116 if (likely(status & (ATA_ERR | ATA_DF)))
4117 /* device stops HSM for abort/error */
4118 qc->err_mask |= AC_ERR_DEV;
4119 else
4120 /* HSM violation. Let EH handle this */
4121 qc->err_mask |= AC_ERR_HSM;
4122
e2cec771
AL		 4123 ap->hsm_task_state = HSM_ST_ERR;
4124 goto fsm_start;
4125 }
1da177e4 4126
eee6c32f
AL		 4127 /* For PIO reads, some devices may ask for
4128 * data transfer (DRQ=1) alone with ERR=1.
4129 * We respect DRQ here and transfer one
4130 * block of junk data before changing the
4131 * hsm_task_state to HSM_ST_ERR.
4132 *
4133 * For PIO writes, ERR=1 DRQ=1 doesn't make
4134 * sense since the data block has been
4135 * transferred to the device.
71601958
AL		 4136 */
4137 if (unlikely(status & (ATA_ERR | ATA_DF))) {
71601958
AL		 4138 /* data might be corrputed */
4139 qc->err_mask |= AC_ERR_DEV;
eee6c32f
AL		 4140
4141 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
4142 ata_pio_sectors(qc);
4143 ata_altstatus(ap);
4144 status = ata_wait_idle(ap);
4145 }
4146
3655d1d3
AL		 4147 if (status & (ATA_BUSY | ATA_DRQ))
4148 qc->err_mask |= AC_ERR_HSM;
4149
eee6c32f
AL		 4150 /* ata_pio_sectors() might change the
4151 * state to HSM_ST_LAST. so, the state
4152 * is changed after ata_pio_sectors().
4153 */
4154 ap->hsm_task_state = HSM_ST_ERR;
4155 goto fsm_start;
71601958
AL		 4156 }
4157
e2cec771
AL		 4158 ata_pio_sectors(qc);
4159
4160 if (ap->hsm_task_state == HSM_ST_LAST &&
4161 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
4162 /* all data read */
4163 ata_altstatus(ap);
52a32205 4164 status = ata_wait_idle(ap);
e2cec771
AL		 4165 goto fsm_start;
4166 }
4167 }
4168
4169 ata_altstatus(ap); /* flush */
bb5cb290 4170 poll_next = 1;
1da177e4
LT		 4171 break;
4172
14be71f4 4173 case HSM_ST_LAST:
6912ccd5
AL		 4174 if (unlikely(!ata_ok(status))) {
4175 qc->err_mask |= __ac_err_mask(status);
e2cec771
AL		 4176 ap->hsm_task_state = HSM_ST_ERR;
4177 goto fsm_start;
4178 }
4179
4180 /* no more data to transfer */
4332a771
AL		 4181 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
4182 ap->id, qc->dev->devno, status);
e2cec771 4183
6912ccd5
AL		 4184 WARN_ON(qc->err_mask);
4185
e2cec771 4186 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 4187
e2cec771 4188 /* complete taskfile transaction */
c17ea20d 4189 ata_hsm_qc_complete(qc, in_wq);
bb5cb290
AL		 4190
4191 poll_next = 0;
1da177e4
LT		 4192 break;
4193
14be71f4 4194 case HSM_ST_ERR:
e2cec771
AL		 4195 /* make sure qc->err_mask is available to
4196 * know what's wrong and recover
4197 */
4198 WARN_ON(qc->err_mask == 0);
4199
4200 ap->hsm_task_state = HSM_ST_IDLE;
bb5cb290 4201
999bb6f4 4202 /* complete taskfile transaction */
c17ea20d 4203 ata_hsm_qc_complete(qc, in_wq);
bb5cb290
AL		 4204
4205 poll_next = 0;
e2cec771
AL		 4206 break;
4207 default:
bb5cb290 4208 poll_next = 0;
6912ccd5 4209 BUG();
1da177e4
LT		 4210 }
4211
bb5cb290 4212 return poll_next;
1da177e4
LT		 4213}
4214
1da177e4 4215static void ata_pio_task(void *_data)
8061f5f0 4216{
c91af2c8
TH		 4217 struct ata_queued_cmd *qc = _data;
4218 struct ata_port *ap = qc->ap;
8061f5f0 4219 u8 status;
a1af3734 4220 int poll_next;
8061f5f0 4221
7fb6ec28 4222fsm_start:
a1af3734 4223 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
8061f5f0 4224
a1af3734
AL		 4225 /*
4226 * This is purely heuristic. This is a fast path.
4227 * Sometimes when we enter, BSY will be cleared in
4228 * a chk-status or two. If not, the drive is probably seeking
4229 * or something. Snooze for a couple msecs, then
4230 * chk-status again. If still busy, queue delayed work.
4231 */
4232 status = ata_busy_wait(ap, ATA_BUSY, 5);
4233 if (status & ATA_BUSY) {
4234 msleep(2);
4235 status = ata_busy_wait(ap, ATA_BUSY, 10);
4236 if (status & ATA_BUSY) {
31ce6dae 4237 ata_port_queue_task(ap, ata_pio_task, qc, ATA_SHORT_PAUSE);
a1af3734
AL		 4238 return;
4239 }
8061f5f0
TH		 4240 }
4241
a1af3734
AL		 4242 /* move the HSM */
4243 poll_next = ata_hsm_move(ap, qc, status, 1);
8061f5f0 4244
a1af3734
AL		 4245 /* another command or interrupt handler
4246 * may be running at this point.
4247 */
4248 if (poll_next)
7fb6ec28 4249 goto fsm_start;
8061f5f0
TH		 4250}
4251
1da177e4
LT		 4252/**
4253 * ata_qc_new - Request an available ATA command, for queueing
4254 * @ap: Port associated with device @dev
4255 * @dev: Device from whom we request an available command structure
4256 *
4257 * LOCKING:
0cba632b 4258 * None.
1da177e4
LT		 4259 */
4260
4261static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
4262{
4263 struct ata_queued_cmd *qc = NULL;
4264 unsigned int i;
4265
e3180499
TH		 4266 /* no command while frozen */
4267 if (unlikely(ap->flags & ATA_FLAG_FROZEN))
4268 return NULL;
4269
2ab7db1f
TH		 4270 /* the last tag is reserved for internal command. */
4271 for (i = 0; i < ATA_MAX_QUEUE - 1; i++)
6cec4a39 4272 if (!test_and_set_bit(i, &ap->qc_allocated)) {
f69499f4 4273 qc = __ata_qc_from_tag(ap, i);
1da177e4
LT		 4274 break;
4275 }
4276
4277 if (qc)
4278 qc->tag = i;
4279
4280 return qc;
4281}
4282
4283/**
4284 * ata_qc_new_init - Request an available ATA command, and initialize it
1da177e4
LT		 4285 * @dev: Device from whom we request an available command structure
4286 *
4287 * LOCKING:
0cba632b 4288 * None.
1da177e4
LT		 4289 */
4290
3373efd8 4291struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev)
1da177e4 4292{
3373efd8 4293 struct ata_port *ap = dev->ap;
1da177e4
LT		 4294 struct ata_queued_cmd *qc;
4295
4296 qc = ata_qc_new(ap);
4297 if (qc) {
1da177e4
LT		 4298 qc->scsicmd = NULL;
4299 qc->ap = ap;
4300 qc->dev = dev;
1da177e4 4301
2c13b7ce 4302 ata_qc_reinit(qc);
1da177e4
LT		 4303 }
4304
4305 return qc;
4306}
4307
1da177e4
LT		 4308/**
4309 * ata_qc_free - free unused ata_queued_cmd
4310 * @qc: Command to complete
4311 *
4312 * Designed to free unused ata_queued_cmd object
4313 * in case something prevents using it.
4314 *
4315 * LOCKING:
0cba632b 4316 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 4317 */
4318void ata_qc_free(struct ata_queued_cmd *qc)
4319{
4ba946e9
TH		 4320 struct ata_port *ap = qc->ap;
4321 unsigned int tag;
4322
a4631474 4323 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 4324
4ba946e9
TH		 4325 qc->flags = 0;
4326 tag = qc->tag;
4327 if (likely(ata_tag_valid(tag))) {
4ba946e9 4328 qc->tag = ATA_TAG_POISON;
6cec4a39 4329 clear_bit(tag, &ap->qc_allocated);
4ba946e9 4330 }
1da177e4
LT		 4331}
4332
76014427 4333void __ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 4334{
dedaf2b0
TH		 4335 struct ata_port *ap = qc->ap;
4336
a4631474
TH		 4337 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
4338 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 4339
4340 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
4341 ata_sg_clean(qc);
4342
7401abf2 4343 /* command should be marked inactive atomically with qc completion */
dedaf2b0
TH		 4344 if (qc->tf.protocol == ATA_PROT_NCQ)
4345 ap->sactive &= ~(1 << qc->tag);
4346 else
4347 ap->active_tag = ATA_TAG_POISON;
7401abf2 4348
3f3791d3
AL		 4349 /* atapi: mark qc as inactive to prevent the interrupt handler
4350 * from completing the command twice later, before the error handler
4351 * is called. (when rc != 0 and atapi request sense is needed)
4352 */
4353 qc->flags &= ~ATA_QCFLAG_ACTIVE;
dedaf2b0 4354 ap->qc_active &= ~(1 << qc->tag);
3f3791d3 4355
1da177e4 4356 /* call completion callback */
77853bf2 4357 qc->complete_fn(qc);
1da177e4
LT		 4358}
4359
f686bcb8
TH		 4360/**
4361 * ata_qc_complete - Complete an active ATA command
4362 * @qc: Command to complete
4363 * @err_mask: ATA Status register contents
4364 *
4365 * Indicate to the mid and upper layers that an ATA
4366 * command has completed, with either an ok or not-ok status.
4367 *
4368 * LOCKING:
4369 * spin_lock_irqsave(host_set lock)
4370 */
4371void ata_qc_complete(struct ata_queued_cmd *qc)
4372{
4373 struct ata_port *ap = qc->ap;
4374
4375 /* XXX: New EH and old EH use different mechanisms to
4376 * synchronize EH with regular execution path.
4377 *
4378 * In new EH, a failed qc is marked with ATA_QCFLAG_FAILED.
4379 * Normal execution path is responsible for not accessing a
4380 * failed qc. libata core enforces the rule by returning NULL
4381 * from ata_qc_from_tag() for failed qcs.
4382 *
4383 * Old EH depends on ata_qc_complete() nullifying completion
4384 * requests if ATA_QCFLAG_EH_SCHEDULED is set. Old EH does
4385 * not synchronize with interrupt handler. Only PIO task is
4386 * taken care of.
4387 */
4388 if (ap->ops->error_handler) {
4389 WARN_ON(ap->flags & ATA_FLAG_FROZEN);
4390
4391 if (unlikely(qc->err_mask))
4392 qc->flags |= ATA_QCFLAG_FAILED;
4393
4394 if (unlikely(qc->flags & ATA_QCFLAG_FAILED)) {
4395 if (!ata_tag_internal(qc->tag)) {
4396 /* always fill result TF for failed qc */
4397 ap->ops->tf_read(ap, &qc->result_tf);
4398 ata_qc_schedule_eh(qc);
4399 return;
4400 }
4401 }
4402
4403 /* read result TF if requested */
4404 if (qc->flags & ATA_QCFLAG_RESULT_TF)
4405 ap->ops->tf_read(ap, &qc->result_tf);
4406
4407 __ata_qc_complete(qc);
4408 } else {
4409 if (qc->flags & ATA_QCFLAG_EH_SCHEDULED)
4410 return;
4411
4412 /* read result TF if failed or requested */
4413 if (qc->err_mask || qc->flags & ATA_QCFLAG_RESULT_TF)
4414 ap->ops->tf_read(ap, &qc->result_tf);
4415
4416 __ata_qc_complete(qc);
4417 }
4418}
4419
dedaf2b0
TH		 4420/**
4421 * ata_qc_complete_multiple - Complete multiple qcs successfully
4422 * @ap: port in question
4423 * @qc_active: new qc_active mask
4424 * @finish_qc: LLDD callback invoked before completing a qc
4425 *
4426 * Complete in-flight commands. This functions is meant to be
4427 * called from low-level driver's interrupt routine to complete
4428 * requests normally. ap->qc_active and @qc_active is compared
4429 * and commands are completed accordingly.
4430 *
4431 * LOCKING:
4432 * spin_lock_irqsave(host_set lock)
4433 *
4434 * RETURNS:
4435 * Number of completed commands on success, -errno otherwise.
4436 */
4437int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active,
4438 void (*finish_qc)(struct ata_queued_cmd *))
4439{
4440 int nr_done = 0;
4441 u32 done_mask;
4442 int i;
4443
4444 done_mask = ap->qc_active ^ qc_active;
4445
4446 if (unlikely(done_mask & qc_active)) {
4447 ata_port_printk(ap, KERN_ERR, "illegal qc_active transition "
4448 "(%08x->%08x)\n", ap->qc_active, qc_active);
4449 return -EINVAL;
4450 }
4451
4452 for (i = 0; i < ATA_MAX_QUEUE; i++) {
4453 struct ata_queued_cmd *qc;
4454
4455 if (!(done_mask & (1 << i)))
4456 continue;
4457
4458 if ((qc = ata_qc_from_tag(ap, i))) {
4459 if (finish_qc)
4460 finish_qc(qc);
4461 ata_qc_complete(qc);
4462 nr_done++;
4463 }
4464 }
4465
4466 return nr_done;
4467}
4468
1da177e4
LT		 4469static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
4470{
4471 struct ata_port *ap = qc->ap;
4472
4473 switch (qc->tf.protocol) {
3dc1d881 4474 case ATA_PROT_NCQ:
1da177e4
LT		 4475 case ATA_PROT_DMA:
4476 case ATA_PROT_ATAPI_DMA:
4477 return 1;
4478
4479 case ATA_PROT_ATAPI:
4480 case ATA_PROT_PIO:
1da177e4
LT		 4481 if (ap->flags & ATA_FLAG_PIO_DMA)
4482 return 1;
4483
4484 /* fall through */
4485
4486 default:
4487 return 0;
4488 }
4489
4490 /* never reached */
4491}
4492
4493/**
4494 * ata_qc_issue - issue taskfile to device
4495 * @qc: command to issue to device
4496 *
4497 * Prepare an ATA command to submission to device.
4498 * This includes mapping the data into a DMA-able
4499 * area, filling in the S/G table, and finally
4500 * writing the taskfile to hardware, starting the command.
4501 *
4502 * LOCKING:
4503 * spin_lock_irqsave(host_set lock)
1da177e4 4504 */
8e0e694a 4505void ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 4506{
4507 struct ata_port *ap = qc->ap;
4508
dedaf2b0
TH		 4509 /* Make sure only one non-NCQ command is outstanding. The
4510 * check is skipped for old EH because it reuses active qc to
4511 * request ATAPI sense.
4512 */
4513 WARN_ON(ap->ops->error_handler && ata_tag_valid(ap->active_tag));
4514
4515 if (qc->tf.protocol == ATA_PROT_NCQ) {
4516 WARN_ON(ap->sactive & (1 << qc->tag));
4517 ap->sactive |= 1 << qc->tag;
4518 } else {
4519 WARN_ON(ap->sactive);
4520 ap->active_tag = qc->tag;
4521 }
4522
e4a70e76 4523 qc->flags |= ATA_QCFLAG_ACTIVE;
dedaf2b0 4524 ap->qc_active |= 1 << qc->tag;
e4a70e76 4525
1da177e4
LT		 4526 if (ata_should_dma_map(qc)) {
4527 if (qc->flags & ATA_QCFLAG_SG) {
4528 if (ata_sg_setup(qc))
8e436af9 4529 goto sg_err;
1da177e4
LT		 4530 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
4531 if (ata_sg_setup_one(qc))
8e436af9 4532 goto sg_err;
1da177e4
LT		 4533 }
4534 } else {
4535 qc->flags &= ~ATA_QCFLAG_DMAMAP;
4536 }
4537
4538 ap->ops->qc_prep(qc);
4539
8e0e694a
TH		 4540 qc->err_mask |= ap->ops->qc_issue(qc);
4541 if (unlikely(qc->err_mask))
4542 goto err;
4543 return;
1da177e4 4544
8e436af9
TH		 4545sg_err:
4546 qc->flags &= ~ATA_QCFLAG_DMAMAP;
8e0e694a
TH		 4547 qc->err_mask |= AC_ERR_SYSTEM;
4548err:
4549 ata_qc_complete(qc);
1da177e4
LT		 4550}
4551
4552/**
4553 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
4554 * @qc: command to issue to device
4555 *
4556 * Using various libata functions and hooks, this function
4557 * starts an ATA command. ATA commands are grouped into
4558 * classes called "protocols", and issuing each type of protocol
4559 * is slightly different.
4560 *
0baab86b
EF		 4561 * May be used as the qc_issue() entry in ata_port_operations.
4562 *
1da177e4
LT		 4563 * LOCKING:
4564 * spin_lock_irqsave(host_set lock)
4565 *
4566 * RETURNS:
9a3d9eb0 4567 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 4568 */
4569
9a3d9eb0 4570unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 4571{
4572 struct ata_port *ap = qc->ap;
4573
e50362ec
AL		 4574 /* Use polling pio if the LLD doesn't handle
4575 * interrupt driven pio and atapi CDB interrupt.
4576 */
4577 if (ap->flags & ATA_FLAG_PIO_POLLING) {
4578 switch (qc->tf.protocol) {
4579 case ATA_PROT_PIO:
4580 case ATA_PROT_ATAPI:
4581 case ATA_PROT_ATAPI_NODATA:
4582 qc->tf.flags |= ATA_TFLAG_POLLING;
4583 break;
4584 case ATA_PROT_ATAPI_DMA:
4585 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
c2bbc551 4586 /* see ata_check_atapi_dma() */
e50362ec
AL		 4587 BUG();
4588 break;
4589 default:
4590 break;
4591 }
4592 }
4593
312f7da2 4594 /* select the device */
1da177e4
LT		 4595 ata_dev_select(ap, qc->dev->devno, 1, 0);
4596
312f7da2 4597 /* start the command */
1da177e4
LT		 4598 switch (qc->tf.protocol) {
4599 case ATA_PROT_NODATA:
312f7da2
AL		 4600 if (qc->tf.flags & ATA_TFLAG_POLLING)
4601 ata_qc_set_polling(qc);
4602
e5338254 4603 ata_tf_to_host(ap, &qc->tf);
312f7da2
AL		 4604 ap->hsm_task_state = HSM_ST_LAST;
4605
4606 if (qc->tf.flags & ATA_TFLAG_POLLING)
31ce6dae 4607 ata_port_queue_task(ap, ata_pio_task, qc, 0);
312f7da2 4608
1da177e4
LT		 4609 break;
4610
4611 case ATA_PROT_DMA:
587005de 4612 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
312f7da2 4613
1da177e4
LT		 4614 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4615 ap->ops->bmdma_setup(qc); /* set up bmdma */
4616 ap->ops->bmdma_start(qc); /* initiate bmdma */
312f7da2 4617 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 4618 break;
4619
312f7da2
AL		 4620 case ATA_PROT_PIO:
4621 if (qc->tf.flags & ATA_TFLAG_POLLING)
4622 ata_qc_set_polling(qc);
1da177e4 4623
e5338254 4624 ata_tf_to_host(ap, &qc->tf);
312f7da2 4625
54f00389
AL		 4626 if (qc->tf.flags & ATA_TFLAG_WRITE) {
4627 /* PIO data out protocol */
4628 ap->hsm_task_state = HSM_ST_FIRST;
31ce6dae 4629 ata_port_queue_task(ap, ata_pio_task, qc, 0);
54f00389
AL		 4630
4631 /* always send first data block using
e27486db 4632 * the ata_pio_task() codepath.
54f00389 4633 */
312f7da2 4634 } else {
54f00389
AL		 4635 /* PIO data in protocol */
4636 ap->hsm_task_state = HSM_ST;
4637
4638 if (qc->tf.flags & ATA_TFLAG_POLLING)
31ce6dae 4639 ata_port_queue_task(ap, ata_pio_task, qc, 0);
54f00389
AL		 4640
4641 /* if polling, ata_pio_task() handles the rest.
4642 * otherwise, interrupt handler takes over from here.
4643 */
312f7da2
AL		 4644 }
4645
1da177e4
LT		 4646 break;
4647
1da177e4 4648 case ATA_PROT_ATAPI:
1da177e4 4649 case ATA_PROT_ATAPI_NODATA:
312f7da2
AL		 4650 if (qc->tf.flags & ATA_TFLAG_POLLING)
4651 ata_qc_set_polling(qc);
4652
e5338254 4653 ata_tf_to_host(ap, &qc->tf);
f6ef65e6 4654
312f7da2
AL		 4655 ap->hsm_task_state = HSM_ST_FIRST;
4656
4657 /* send cdb by polling if no cdb interrupt */
4658 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
4659 (qc->tf.flags & ATA_TFLAG_POLLING))
31ce6dae 4660 ata_port_queue_task(ap, ata_pio_task, qc, 0);
1da177e4
LT		 4661 break;
4662
4663 case ATA_PROT_ATAPI_DMA:
587005de 4664 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
312f7da2 4665
1da177e4
LT		 4666 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4667 ap->ops->bmdma_setup(qc); /* set up bmdma */
312f7da2
AL		 4668 ap->hsm_task_state = HSM_ST_FIRST;
4669
4670 /* send cdb by polling if no cdb interrupt */
4671 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
31ce6dae 4672 ata_port_queue_task(ap, ata_pio_task, qc, 0);
1da177e4
LT		 4673 break;
4674
4675 default:
4676 WARN_ON(1);
9a3d9eb0 4677 return AC_ERR_SYSTEM;
1da177e4
LT		 4678 }
4679
4680 return 0;
4681}
4682
1da177e4
LT		 4683/**
4684 * ata_host_intr - Handle host interrupt for given (port, task)
4685 * @ap: Port on which interrupt arrived (possibly...)
4686 * @qc: Taskfile currently active in engine
4687 *
4688 * Handle host interrupt for given queued command. Currently,
4689 * only DMA interrupts are handled. All other commands are
4690 * handled via polling with interrupts disabled (nIEN bit).
4691 *
4692 * LOCKING:
4693 * spin_lock_irqsave(host_set lock)
4694 *
4695 * RETURNS:
4696 * One if interrupt was handled, zero if not (shared irq).
4697 */
4698
4699inline unsigned int ata_host_intr (struct ata_port *ap,
4700 struct ata_queued_cmd *qc)
4701{
312f7da2 4702 u8 status, host_stat = 0;
1da177e4 4703
312f7da2
AL		 4704 VPRINTK("ata%u: protocol %d task_state %d\n",
4705 ap->id, qc->tf.protocol, ap->hsm_task_state);
1da177e4 4706
312f7da2
AL		 4707 /* Check whether we are expecting interrupt in this state */
4708 switch (ap->hsm_task_state) {
4709 case HSM_ST_FIRST:
6912ccd5
AL		 4710 /* Some pre-ATAPI-4 devices assert INTRQ
4711 * at this state when ready to receive CDB.
4712 */
1da177e4 4713
312f7da2
AL		 4714 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
4715 * The flag was turned on only for atapi devices.
4716 * No need to check is_atapi_taskfile(&qc->tf) again.
4717 */
4718 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1da177e4 4719 goto idle_irq;
1da177e4 4720 break;
312f7da2
AL		 4721 case HSM_ST_LAST:
4722 if (qc->tf.protocol == ATA_PROT_DMA ||
4723 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
4724 /* check status of DMA engine */
4725 host_stat = ap->ops->bmdma_status(ap);
4726 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4727
4728 /* if it's not our irq... */
4729 if (!(host_stat & ATA_DMA_INTR))
4730 goto idle_irq;
4731
4732 /* before we do anything else, clear DMA-Start bit */
4733 ap->ops->bmdma_stop(qc);
a4f16610
AL		 4734
4735 if (unlikely(host_stat & ATA_DMA_ERR)) {
4736 /* error when transfering data to/from memory */
4737 qc->err_mask |= AC_ERR_HOST_BUS;
4738 ap->hsm_task_state = HSM_ST_ERR;
4739 }
312f7da2
AL		 4740 }
4741 break;
4742 case HSM_ST:
4743 break;
1da177e4
LT		 4744 default:
4745 goto idle_irq;
4746 }
4747
312f7da2
AL		 4748 /* check altstatus */
4749 status = ata_altstatus(ap);
4750 if (status & ATA_BUSY)
4751 goto idle_irq;
1da177e4 4752
312f7da2
AL		 4753 /* check main status, clearing INTRQ */
4754 status = ata_chk_status(ap);
4755 if (unlikely(status & ATA_BUSY))
4756 goto idle_irq;
1da177e4 4757
312f7da2
AL		 4758 /* ack bmdma irq events */
4759 ap->ops->irq_clear(ap);
1da177e4 4760
bb5cb290 4761 ata_hsm_move(ap, qc, status, 0);
1da177e4
LT		 4762 return 1; /* irq handled */
4763
4764idle_irq:
4765 ap->stats.idle_irq++;
4766
4767#ifdef ATA_IRQ_TRAP
4768 if ((ap->stats.idle_irq % 1000) == 0) {
1da177e4 4769 ata_irq_ack(ap, 0); /* debug trap */
f15a1daf 4770 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
23cfce89 4771 return 1;
1da177e4
LT		 4772 }
4773#endif
4774 return 0; /* irq not handled */
4775}
4776
4777/**
4778 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 4779 * @irq: irq line (unused)
4780 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 4781 * @regs: unused
4782 *
0cba632b
JG		 4783 * Default interrupt handler for PCI IDE devices. Calls
4784 * ata_host_intr() for each port that is not disabled.
4785 *
1da177e4 4786 * LOCKING:
0cba632b 4787 * Obtains host_set lock during operation.
1da177e4
LT		 4788 *
4789 * RETURNS:
0cba632b 4790 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4791 */
4792
4793irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4794{
4795 struct ata_host_set *host_set = dev_instance;
4796 unsigned int i;
4797 unsigned int handled = 0;
4798 unsigned long flags;
4799
4800 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4801 spin_lock_irqsave(&host_set->lock, flags);
4802
4803 for (i = 0; i < host_set->n_ports; i++) {
4804 struct ata_port *ap;
4805
4806 ap = host_set->ports[i];
c1389503 4807 if (ap &&
029f5468 4808 !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4
LT		 4809 struct ata_queued_cmd *qc;
4810
4811 qc = ata_qc_from_tag(ap, ap->active_tag);
312f7da2 4812 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
21b1ed74 4813 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4814 handled |= ata_host_intr(ap, qc);
4815 }
4816 }
4817
4818 spin_unlock_irqrestore(&host_set->lock, flags);
4819
4820 return IRQ_RETVAL(handled);
4821}
4822
34bf2170
TH		 4823/**
4824 * sata_scr_valid - test whether SCRs are accessible
4825 * @ap: ATA port to test SCR accessibility for
4826 *
4827 * Test whether SCRs are accessible for @ap.
4828 *
4829 * LOCKING:
4830 * None.
4831 *
4832 * RETURNS:
4833 * 1 if SCRs are accessible, 0 otherwise.
4834 */
4835int sata_scr_valid(struct ata_port *ap)
4836{
4837 return ap->cbl == ATA_CBL_SATA && ap->ops->scr_read;
4838}
4839
4840/**
4841 * sata_scr_read - read SCR register of the specified port
4842 * @ap: ATA port to read SCR for
4843 * @reg: SCR to read
4844 * @val: Place to store read value
4845 *
4846 * Read SCR register @reg of @ap into *@val. This function is
4847 * guaranteed to succeed if the cable type of the port is SATA
4848 * and the port implements ->scr_read.
4849 *
4850 * LOCKING:
4851 * None.
4852 *
4853 * RETURNS:
4854 * 0 on success, negative errno on failure.
4855 */
4856int sata_scr_read(struct ata_port *ap, int reg, u32 *val)
4857{
4858 if (sata_scr_valid(ap)) {
4859 *val = ap->ops->scr_read(ap, reg);
4860 return 0;
4861 }
4862 return -EOPNOTSUPP;
4863}
4864
4865/**
4866 * sata_scr_write - write SCR register of the specified port
4867 * @ap: ATA port to write SCR for
4868 * @reg: SCR to write
4869 * @val: value to write
4870 *
4871 * Write @val to SCR register @reg of @ap. This function is
4872 * guaranteed to succeed if the cable type of the port is SATA
4873 * and the port implements ->scr_read.
4874 *
4875 * LOCKING:
4876 * None.
4877 *
4878 * RETURNS:
4879 * 0 on success, negative errno on failure.
4880 */
4881int sata_scr_write(struct ata_port *ap, int reg, u32 val)
4882{
4883 if (sata_scr_valid(ap)) {
4884 ap->ops->scr_write(ap, reg, val);
4885 return 0;
4886 }
4887 return -EOPNOTSUPP;
4888}
4889
4890/**
4891 * sata_scr_write_flush - write SCR register of the specified port and flush
4892 * @ap: ATA port to write SCR for
4893 * @reg: SCR to write
4894 * @val: value to write
4895 *
4896 * This function is identical to sata_scr_write() except that this
4897 * function performs flush after writing to the register.
4898 *
4899 * LOCKING:
4900 * None.
4901 *
4902 * RETURNS:
4903 * 0 on success, negative errno on failure.
4904 */
4905int sata_scr_write_flush(struct ata_port *ap, int reg, u32 val)
4906{
4907 if (sata_scr_valid(ap)) {
4908 ap->ops->scr_write(ap, reg, val);
4909 ap->ops->scr_read(ap, reg);
4910 return 0;
4911 }
4912 return -EOPNOTSUPP;
4913}
4914
4915/**
4916 * ata_port_online - test whether the given port is online
4917 * @ap: ATA port to test
4918 *
4919 * Test whether @ap is online. Note that this function returns 0
4920 * if online status of @ap cannot be obtained, so
4921 * ata_port_online(ap) != !ata_port_offline(ap).
4922 *
4923 * LOCKING:
4924 * None.
4925 *
4926 * RETURNS:
4927 * 1 if the port online status is available and online.
4928 */
4929int ata_port_online(struct ata_port *ap)
4930{
4931 u32 sstatus;
4932
4933 if (!sata_scr_read(ap, SCR_STATUS, &sstatus) && (sstatus & 0xf) == 0x3)
4934 return 1;
4935 return 0;
4936}
4937
4938/**
4939 * ata_port_offline - test whether the given port is offline
4940 * @ap: ATA port to test
4941 *
4942 * Test whether @ap is offline. Note that this function returns
4943 * 0 if offline status of @ap cannot be obtained, so
4944 * ata_port_online(ap) != !ata_port_offline(ap).
4945 *
4946 * LOCKING:
4947 * None.
4948 *
4949 * RETURNS:
4950 * 1 if the port offline status is available and offline.
4951 */
4952int ata_port_offline(struct ata_port *ap)
4953{
4954 u32 sstatus;
4955
4956 if (!sata_scr_read(ap, SCR_STATUS, &sstatus) && (sstatus & 0xf) != 0x3)
4957 return 1;
4958 return 0;
4959}
0baab86b 4960
9b847548
JA		 4961/*
4962 * Execute a 'simple' command, that only consists of the opcode 'cmd' itself,
4963 * without filling any other registers
4964 */
3373efd8 4965static int ata_do_simple_cmd(struct ata_device *dev, u8 cmd)
9b847548
JA		 4966{
4967 struct ata_taskfile tf;
4968 int err;
4969
3373efd8 4970 ata_tf_init(dev, &tf);
9b847548
JA		 4971
4972 tf.command = cmd;
4973 tf.flags |= ATA_TFLAG_DEVICE;
4974 tf.protocol = ATA_PROT_NODATA;
4975
3373efd8 4976 err = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
9b847548 4977 if (err)
f15a1daf
TH		 4978 ata_dev_printk(dev, KERN_ERR, "%s: ata command failed: %d\n",
4979 __FUNCTION__, err);
9b847548
JA		 4980
4981 return err;
4982}
4983
3373efd8 4984static int ata_flush_cache(struct ata_device *dev)
9b847548
JA		 4985{
4986 u8 cmd;
4987
4988 if (!ata_try_flush_cache(dev))
4989 return 0;
4990
4991 if (ata_id_has_flush_ext(dev->id))
4992 cmd = ATA_CMD_FLUSH_EXT;
4993 else
4994 cmd = ATA_CMD_FLUSH;
4995
3373efd8 4996 return ata_do_simple_cmd(dev, cmd);
9b847548
JA		 4997}
4998
3373efd8 4999static int ata_standby_drive(struct ata_device *dev)
9b847548 5000{
3373efd8 5001 return ata_do_simple_cmd(dev, ATA_CMD_STANDBYNOW1);
9b847548
JA		 5002}
5003
3373efd8 5004static int ata_start_drive(struct ata_device *dev)
9b847548 5005{
3373efd8 5006 return ata_do_simple_cmd(dev, ATA_CMD_IDLEIMMEDIATE);
9b847548
JA		 5007}
5008
5009/**
5010 * ata_device_resume - wakeup a previously suspended devices
c893a3ae 5011 * @dev: the device to resume
9b847548
JA		 5012 *
5013 * Kick the drive back into action, by sending it an idle immediate
5014 * command and making sure its transfer mode matches between drive
5015 * and host.
5016 *
5017 */
3373efd8 5018int ata_device_resume(struct ata_device *dev)
9b847548 5019{
3373efd8
TH		 5020 struct ata_port *ap = dev->ap;
5021
9b847548 5022 if (ap->flags & ATA_FLAG_SUSPENDED) {
e82cbdb9 5023 struct ata_device *failed_dev;
e42d7be2 5024
0737ac89 5025 ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 200000);
e42d7be2 5026
9b847548 5027 ap->flags &= ~ATA_FLAG_SUSPENDED;
e82cbdb9 5028 while (ata_set_mode(ap, &failed_dev))
3373efd8 5029 ata_dev_disable(failed_dev);
9b847548 5030 }
e1211e3f 5031 if (!ata_dev_enabled(dev))
9b847548
JA		 5032 return 0;
5033 if (dev->class == ATA_DEV_ATA)
3373efd8 5034 ata_start_drive(dev);
9b847548
JA		 5035
5036 return 0;
5037}
5038
5039/**
5040 * ata_device_suspend - prepare a device for suspend
c893a3ae 5041 * @dev: the device to suspend
e2a7f77a 5042 * @state: target power management state
9b847548
JA		 5043 *
5044 * Flush the cache on the drive, if appropriate, then issue a
5045 * standbynow command.
9b847548 5046 */
3373efd8 5047int ata_device_suspend(struct ata_device *dev, pm_message_t state)
9b847548 5048{
3373efd8
TH		 5049 struct ata_port *ap = dev->ap;
5050
e1211e3f 5051 if (!ata_dev_enabled(dev))
9b847548
JA		 5052 return 0;
5053 if (dev->class == ATA_DEV_ATA)
3373efd8 5054 ata_flush_cache(dev);
9b847548 5055
082776e4 5056 if (state.event != PM_EVENT_FREEZE)
3373efd8 5057 ata_standby_drive(dev);
9b847548
JA		 5058 ap->flags |= ATA_FLAG_SUSPENDED;
5059 return 0;
5060}
5061
c893a3ae
RD		 5062/**
5063 * ata_port_start - Set port up for dma.
5064 * @ap: Port to initialize
5065 *
5066 * Called just after data structures for each port are
5067 * initialized. Allocates space for PRD table.
5068 *
5069 * May be used as the port_start() entry in ata_port_operations.
5070 *
5071 * LOCKING:
5072 * Inherited from caller.
5073 */
5074
1da177e4
LT		 5075int ata_port_start (struct ata_port *ap)
5076{
2f1f610b 5077 struct device *dev = ap->dev;
6037d6bb 5078 int rc;
1da177e4
LT		 5079
5080 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
5081 if (!ap->prd)
5082 return -ENOMEM;
5083
6037d6bb
JG		 5084 rc = ata_pad_alloc(ap, dev);
5085 if (rc) {
cedc9a47 5086 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 5087 return rc;
cedc9a47
JG		 5088 }
5089
1da177e4
LT		 5090 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
5091
5092 return 0;
5093}
5094
0baab86b
EF		 5095
5096/**
5097 * ata_port_stop - Undo ata_port_start()
5098 * @ap: Port to shut down
5099 *
5100 * Frees the PRD table.
5101 *
5102 * May be used as the port_stop() entry in ata_port_operations.
5103 *
5104 * LOCKING:
6f0ef4fa 5105 * Inherited from caller.
0baab86b
EF		 5106 */
5107
1da177e4
LT		 5108void ata_port_stop (struct ata_port *ap)
5109{
2f1f610b 5110 struct device *dev = ap->dev;
1da177e4
LT		 5111
5112 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 5113 ata_pad_free(ap, dev);
1da177e4
LT		 5114}
5115
aa8f0dc6
JG		 5116void ata_host_stop (struct ata_host_set *host_set)
5117{
5118 if (host_set->mmio_base)
5119 iounmap(host_set->mmio_base);
5120}
5121
5122
1da177e4
LT		 5123/**
5124 * ata_host_remove - Unregister SCSI host structure with upper layers
5125 * @ap: Port to unregister
5126 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
5127 *
5128 * LOCKING:
6f0ef4fa 5129 * Inherited from caller.
1da177e4
LT		 5130 */
5131
5132static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
5133{
5134 struct Scsi_Host *sh = ap->host;
5135
5136 DPRINTK("ENTER\n");
5137
5138 if (do_unregister)
5139 scsi_remove_host(sh);
5140
5141 ap->ops->port_stop(ap);
5142}
5143
3ef3b43d
TH		 5144/**
5145 * ata_dev_init - Initialize an ata_device structure
5146 * @dev: Device structure to initialize
5147 *
5148 * Initialize @dev in preparation for probing.
5149 *
5150 * LOCKING:
5151 * Inherited from caller.
5152 */
5153void ata_dev_init(struct ata_device *dev)
5154{
5155 struct ata_port *ap = dev->ap;
72fa4b74
TH		 5156 unsigned long flags;
5157
5158 /* High bits of dev->flags are used to record warm plug
5159 * requests which occur asynchronously. Synchronize using
5160 * host_set lock.
5161 */
5162 spin_lock_irqsave(&ap->host_set->lock, flags);
5163 dev->flags &= ~ATA_DFLAG_INIT_MASK;
5164 spin_unlock_irqrestore(&ap->host_set->lock, flags);
3ef3b43d 5165
72fa4b74
TH		 5166 memset((void *)dev + ATA_DEVICE_CLEAR_OFFSET, 0,
5167 sizeof(*dev) - ATA_DEVICE_CLEAR_OFFSET);
3ef3b43d
TH		 5168 dev->pio_mask = UINT_MAX;
5169 dev->mwdma_mask = UINT_MAX;
5170 dev->udma_mask = UINT_MAX;
5171}
5172
1da177e4
LT		 5173/**
5174 * ata_host_init - Initialize an ata_port structure
5175 * @ap: Structure to initialize
5176 * @host: associated SCSI mid-layer structure
5177 * @host_set: Collection of hosts to which @ap belongs
5178 * @ent: Probe information provided by low-level driver
5179 * @port_no: Port number associated with this ata_port
5180 *
0cba632b
JG		 5181 * Initialize a new ata_port structure, and its associated
5182 * scsi_host.
5183 *
1da177e4 5184 * LOCKING:
0cba632b 5185 * Inherited from caller.
1da177e4 5186 */
1da177e4
LT		 5187static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
5188 struct ata_host_set *host_set,
057ace5e 5189 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 5190{
5191 unsigned int i;
5192
5193 host->max_id = 16;
5194 host->max_lun = 1;
5195 host->max_channel = 1;
5196 host->unique_id = ata_unique_id++;
5197 host->max_cmd_len = 12;
12413197 5198
198e0fed 5199 ap->flags = ATA_FLAG_DISABLED;
1da177e4
LT		 5200 ap->id = host->unique_id;
5201 ap->host = host;
5202 ap->ctl = ATA_DEVCTL_OBS;
5203 ap->host_set = host_set;
2f1f610b 5204 ap->dev = ent->dev;
1da177e4
LT		 5205 ap->port_no = port_no;
5206 ap->hard_port_no =
5207 ent->legacy_mode ? ent->hard_port_no : port_no;
5208 ap->pio_mask = ent->pio_mask;
5209 ap->mwdma_mask = ent->mwdma_mask;
5210 ap->udma_mask = ent->udma_mask;
5211 ap->flags |= ent->host_flags;
5212 ap->ops = ent->port_ops;
1c3fae4d 5213 ap->sata_spd_limit = UINT_MAX;
1da177e4
LT		 5214 ap->active_tag = ATA_TAG_POISON;
5215 ap->last_ctl = 0xFF;
ef282407 5216 ap->msg_enable = ATA_MSG_DRV;
1da177e4 5217
86e45b6b 5218 INIT_WORK(&ap->port_task, NULL, NULL);
a72ec4ce 5219 INIT_LIST_HEAD(&ap->eh_done_q);
c6cf9e99 5220 init_waitqueue_head(&ap->eh_wait_q);
1da177e4 5221
838df628
TH		 5222 /* set cable type */
5223 ap->cbl = ATA_CBL_NONE;
5224 if (ap->flags & ATA_FLAG_SATA)
5225 ap->cbl = ATA_CBL_SATA;
5226
acf356b1
TH		 5227 for (i = 0; i < ATA_MAX_DEVICES; i++) {
5228 struct ata_device *dev = &ap->device[i];
38d87234 5229 dev->ap = ap;
72fa4b74 5230 dev->devno = i;
3ef3b43d 5231 ata_dev_init(dev);
acf356b1 5232 }
1da177e4
LT		 5233
5234#ifdef ATA_IRQ_TRAP
5235 ap->stats.unhandled_irq = 1;
5236 ap->stats.idle_irq = 1;
5237#endif
5238
5239 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
5240}
5241
5242/**
5243 * ata_host_add - Attach low-level ATA driver to system
5244 * @ent: Information provided by low-level driver
5245 * @host_set: Collections of ports to which we add
5246 * @port_no: Port number associated with this host
5247 *
0cba632b
JG		 5248 * Attach low-level ATA driver to system.
5249 *
1da177e4 5250 * LOCKING:
0cba632b 5251 * PCI/etc. bus probe sem.
1da177e4
LT		 5252 *
5253 * RETURNS:
0cba632b 5254 * New ata_port on success, for NULL on error.
1da177e4
LT		 5255 */
5256
057ace5e 5257static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 5258 struct ata_host_set *host_set,
5259 unsigned int port_no)
5260{
5261 struct Scsi_Host *host;
5262 struct ata_port *ap;
5263 int rc;
5264
5265 DPRINTK("ENTER\n");
aec5c3c1
TH		 5266
5267 if (!ent->port_ops->probe_reset &&
5268 !(ent->host_flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST))) {
5269 printk(KERN_ERR "ata%u: no reset mechanism available\n",
5270 port_no);
5271 return NULL;
5272 }
5273
1da177e4
LT		 5274 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
5275 if (!host)
5276 return NULL;
5277
30afc84c
TH		 5278 host->transportt = &ata_scsi_transport_template;
5279
35bb94b1 5280 ap = ata_shost_to_port(host);
1da177e4
LT		 5281
5282 ata_host_init(ap, host, host_set, ent, port_no);
5283
5284 rc = ap->ops->port_start(ap);
5285 if (rc)
5286 goto err_out;
5287
5288 return ap;
5289
5290err_out:
5291 scsi_host_put(host);
5292 return NULL;
5293}
5294
5295/**
0cba632b
JG		 5296 * ata_device_add - Register hardware device with ATA and SCSI layers
5297 * @ent: Probe information describing hardware device to be registered
5298 *
5299 * This function processes the information provided in the probe
5300 * information struct @ent, allocates the necessary ATA and SCSI
5301 * host information structures, initializes them, and registers
5302 * everything with requisite kernel subsystems.
5303 *
5304 * This function requests irqs, probes the ATA bus, and probes
5305 * the SCSI bus.
1da177e4
LT		 5306 *
5307 * LOCKING:
0cba632b 5308 * PCI/etc. bus probe sem.
1da177e4
LT		 5309 *
5310 * RETURNS:
0cba632b 5311 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 5312 */
5313
057ace5e 5314int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 5315{
5316 unsigned int count = 0, i;
5317 struct device *dev = ent->dev;
5318 struct ata_host_set *host_set;
5319
5320 DPRINTK("ENTER\n");
5321 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 5322 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 5323 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
5324 if (!host_set)
5325 return 0;
1da177e4
LT		 5326 spin_lock_init(&host_set->lock);
5327
5328 host_set->dev = dev;
5329 host_set->n_ports = ent->n_ports;
5330 host_set->irq = ent->irq;
5331 host_set->mmio_base = ent->mmio_base;
5332 host_set->private_data = ent->private_data;
5333 host_set->ops = ent->port_ops;
5444a6f4 5334 host_set->flags = ent->host_set_flags;
1da177e4
LT		 5335
5336 /* register each port bound to this device */
5337 for (i = 0; i < ent->n_ports; i++) {
5338 struct ata_port *ap;
5339 unsigned long xfer_mode_mask;
5340
5341 ap = ata_host_add(ent, host_set, i);
5342 if (!ap)
5343 goto err_out;
5344
5345 host_set->ports[i] = ap;
5346 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
5347 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
5348 (ap->pio_mask << ATA_SHIFT_PIO);
5349
5350 /* print per-port info to dmesg */
f15a1daf
TH		 5351 ata_port_printk(ap, KERN_INFO, "%cATA max %s cmd 0x%lX "
5352 "ctl 0x%lX bmdma 0x%lX irq %lu\n",
5353 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
5354 ata_mode_string(xfer_mode_mask),
5355 ap->ioaddr.cmd_addr,
5356 ap->ioaddr.ctl_addr,
5357 ap->ioaddr.bmdma_addr,
5358 ent->irq);
1da177e4
LT		 5359
5360 ata_chk_status(ap);
5361 host_set->ops->irq_clear(ap);
e3180499 5362 ata_eh_freeze_port(ap); /* freeze port before requesting IRQ */
1da177e4
LT		 5363 count++;
5364 }
5365
57f3bda8
RD		 5366 if (!count)
5367 goto err_free_ret;
1da177e4
LT		 5368
5369 /* obtain irq, that is shared between channels */
5370 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
5371 DRV_NAME, host_set))
5372 goto err_out;
5373
5374 /* perform each probe synchronously */
5375 DPRINTK("probe begin\n");
5376 for (i = 0; i < count; i++) {
5377 struct ata_port *ap;
5378 int rc;
5379
5380 ap = host_set->ports[i];
5381
c893a3ae 5382 DPRINTK("ata%u: bus probe begin\n", ap->id);
1da177e4 5383 rc = ata_bus_probe(ap);
c893a3ae 5384 DPRINTK("ata%u: bus probe end\n", ap->id);
1da177e4
LT		 5385
5386 if (rc) {
5387 /* FIXME: do something useful here?
5388 * Current libata behavior will
5389 * tear down everything when
5390 * the module is removed
5391 * or the h/w is unplugged.
5392 */
5393 }
5394
5395 rc = scsi_add_host(ap->host, dev);
5396 if (rc) {
f15a1daf 5397 ata_port_printk(ap, KERN_ERR, "scsi_add_host failed\n");
1da177e4
LT		 5398 /* FIXME: do something useful here */
5399 /* FIXME: handle unconditional calls to
5400 * scsi_scan_host and ata_host_remove, below,
5401 * at the very least
5402 */
5403 }
5404 }
5405
5406 /* probes are done, now scan each port's disk(s) */
c893a3ae 5407 DPRINTK("host probe begin\n");
1da177e4
LT		 5408 for (i = 0; i < count; i++) {
5409 struct ata_port *ap = host_set->ports[i];
5410
644dd0cc 5411 ata_scsi_scan_host(ap);
1da177e4
LT		 5412 }
5413
5414 dev_set_drvdata(dev, host_set);
5415
5416 VPRINTK("EXIT, returning %u\n", ent->n_ports);
5417 return ent->n_ports; /* success */
5418
5419err_out:
5420 for (i = 0; i < count; i++) {
5421 ata_host_remove(host_set->ports[i], 1);
5422 scsi_host_put(host_set->ports[i]->host);
5423 }
57f3bda8 5424err_free_ret:
1da177e4
LT		 5425 kfree(host_set);
5426 VPRINTK("EXIT, returning 0\n");
5427 return 0;
5428}
5429
17b14451
AC		 5430/**
5431 * ata_host_set_remove - PCI layer callback for device removal
5432 * @host_set: ATA host set that was removed
5433 *
2e9edbf8 5434 * Unregister all objects associated with this host set. Free those
17b14451
AC		 5435 * objects.
5436 *
5437 * LOCKING:
5438 * Inherited from calling layer (may sleep).
5439 */
5440
17b14451
AC		 5441void ata_host_set_remove(struct ata_host_set *host_set)
5442{
5443 struct ata_port *ap;
5444 unsigned int i;
5445
5446 for (i = 0; i < host_set->n_ports; i++) {
5447 ap = host_set->ports[i];
5448 scsi_remove_host(ap->host);
5449 }
5450
5451 free_irq(host_set->irq, host_set);
5452
5453 for (i = 0; i < host_set->n_ports; i++) {
5454 ap = host_set->ports[i];
5455
5456 ata_scsi_release(ap->host);
5457
5458 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
5459 struct ata_ioports *ioaddr = &ap->ioaddr;
5460
5461 if (ioaddr->cmd_addr == 0x1f0)
5462 release_region(0x1f0, 8);
5463 else if (ioaddr->cmd_addr == 0x170)
5464 release_region(0x170, 8);
5465 }
5466
5467 scsi_host_put(ap->host);
5468 }
5469
5470 if (host_set->ops->host_stop)
5471 host_set->ops->host_stop(host_set);
5472
5473 kfree(host_set);
5474}
5475
1da177e4
LT		 5476/**
5477 * ata_scsi_release - SCSI layer callback hook for host unload
5478 * @host: libata host to be unloaded
5479 *
5480 * Performs all duties necessary to shut down a libata port...
5481 * Kill port kthread, disable port, and release resources.
5482 *
5483 * LOCKING:
5484 * Inherited from SCSI layer.
5485 *
5486 * RETURNS:
5487 * One.
5488 */
5489
5490int ata_scsi_release(struct Scsi_Host *host)
5491{
35bb94b1 5492 struct ata_port *ap = ata_shost_to_port(host);
1da177e4
LT		 5493
5494 DPRINTK("ENTER\n");
5495
5496 ap->ops->port_disable(ap);
5497 ata_host_remove(ap, 0);
5498
5499 DPRINTK("EXIT\n");
5500 return 1;
5501}
5502
5503/**
5504 * ata_std_ports - initialize ioaddr with standard port offsets.
5505 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 5506 *
5507 * Utility function which initializes data_addr, error_addr,
5508 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
5509 * device_addr, status_addr, and command_addr to standard offsets
5510 * relative to cmd_addr.
5511 *
5512 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 5513 */
0baab86b 5514
1da177e4
LT		 5515void ata_std_ports(struct ata_ioports *ioaddr)
5516{
5517 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
5518 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
5519 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
5520 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
5521 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
5522 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
5523 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
5524 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
5525 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
5526 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
5527}
5528
0baab86b 5529
374b1873
JG		 5530#ifdef CONFIG_PCI
5531
5532void ata_pci_host_stop (struct ata_host_set *host_set)
5533{
5534 struct pci_dev *pdev = to_pci_dev(host_set->dev);
5535
5536 pci_iounmap(pdev, host_set->mmio_base);
5537}
5538
1da177e4
LT		 5539/**
5540 * ata_pci_remove_one - PCI layer callback for device removal
5541 * @pdev: PCI device that was removed
5542 *
5543 * PCI layer indicates to libata via this hook that
6f0ef4fa 5544 * hot-unplug or module unload event has occurred.
1da177e4
LT		 5545 * Handle this by unregistering all objects associated
5546 * with this PCI device. Free those objects. Then finally
5547 * release PCI resources and disable device.
5548 *
5549 * LOCKING:
5550 * Inherited from PCI layer (may sleep).
5551 */
5552
5553void ata_pci_remove_one (struct pci_dev *pdev)
5554{
5555 struct device *dev = pci_dev_to_dev(pdev);
5556 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 5557
17b14451 5558 ata_host_set_remove(host_set);
1da177e4
LT		 5559 pci_release_regions(pdev);
5560 pci_disable_device(pdev);
5561 dev_set_drvdata(dev, NULL);
5562}
5563
5564/* move to PCI subsystem */
057ace5e 5565int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 5566{
5567 unsigned long tmp = 0;
5568
5569 switch (bits->width) {
5570 case 1: {
5571 u8 tmp8 = 0;
5572 pci_read_config_byte(pdev, bits->reg, &tmp8);
5573 tmp = tmp8;
5574 break;
5575 }
5576 case 2: {
5577 u16 tmp16 = 0;
5578 pci_read_config_word(pdev, bits->reg, &tmp16);
5579 tmp = tmp16;
5580 break;
5581 }
5582 case 4: {
5583 u32 tmp32 = 0;
5584 pci_read_config_dword(pdev, bits->reg, &tmp32);
5585 tmp = tmp32;
5586 break;
5587 }
5588
5589 default:
5590 return -EINVAL;
5591 }
5592
5593 tmp &= bits->mask;
5594
5595 return (tmp == bits->val) ? 1 : 0;
5596}
9b847548
JA		 5597
5598int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t state)
5599{
5600 pci_save_state(pdev);
5601 pci_disable_device(pdev);
5602 pci_set_power_state(pdev, PCI_D3hot);
5603 return 0;
5604}
5605
5606int ata_pci_device_resume(struct pci_dev *pdev)
5607{
5608 pci_set_power_state(pdev, PCI_D0);
5609 pci_restore_state(pdev);
5610 pci_enable_device(pdev);
5611 pci_set_master(pdev);
5612 return 0;
5613}
1da177e4
LT		 5614#endif /* CONFIG_PCI */
5615
5616
1da177e4
LT		 5617static int __init ata_init(void)
5618{
5619 ata_wq = create_workqueue("ata");
5620 if (!ata_wq)
5621 return -ENOMEM;
5622
5623 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
5624 return 0;
5625}
5626
5627static void __exit ata_exit(void)
5628{
5629 destroy_workqueue(ata_wq);
5630}
5631
5632module_init(ata_init);
5633module_exit(ata_exit);
5634
67846b30
JG		 5635static unsigned long ratelimit_time;
5636static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
5637
5638int ata_ratelimit(void)
5639{
5640 int rc;
5641 unsigned long flags;
5642
5643 spin_lock_irqsave(&ata_ratelimit_lock, flags);
5644
5645 if (time_after(jiffies, ratelimit_time)) {
5646 rc = 1;
5647 ratelimit_time = jiffies + (HZ/5);
5648 } else
5649 rc = 0;
5650
5651 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
5652
5653 return rc;
5654}
5655
c22daff4
TH		 5656/**
5657 * ata_wait_register - wait until register value changes
5658 * @reg: IO-mapped register
5659 * @mask: Mask to apply to read register value
5660 * @val: Wait condition
5661 * @interval_msec: polling interval in milliseconds
5662 * @timeout_msec: timeout in milliseconds
5663 *
5664 * Waiting for some bits of register to change is a common
5665 * operation for ATA controllers. This function reads 32bit LE
5666 * IO-mapped register @reg and tests for the following condition.
5667 *
5668 * (*@reg & mask) != val
5669 *
5670 * If the condition is met, it returns; otherwise, the process is
5671 * repeated after @interval_msec until timeout.
5672 *
5673 * LOCKING:
5674 * Kernel thread context (may sleep)
5675 *
5676 * RETURNS:
5677 * The final register value.
5678 */
5679u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
5680 unsigned long interval_msec,
5681 unsigned long timeout_msec)
5682{
5683 unsigned long timeout;
5684 u32 tmp;
5685
5686 tmp = ioread32(reg);
5687
5688 /* Calculate timeout _after_ the first read to make sure
5689 * preceding writes reach the controller before starting to
5690 * eat away the timeout.
5691 */
5692 timeout = jiffies + (timeout_msec * HZ) / 1000;
5693
5694 while ((tmp & mask) == val && time_before(jiffies, timeout)) {
5695 msleep(interval_msec);
5696 tmp = ioread32(reg);
5697 }
5698
5699 return tmp;
5700}
5701
1da177e4
LT		 5702/*
5703 * libata is essentially a library of internal helper functions for
5704 * low-level ATA host controller drivers. As such, the API/ABI is
5705 * likely to change as new drivers are added and updated.
5706 * Do not depend on ABI/API stability.
5707 */
5708
5709EXPORT_SYMBOL_GPL(ata_std_bios_param);
5710EXPORT_SYMBOL_GPL(ata_std_ports);
5711EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 5712EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 5713EXPORT_SYMBOL_GPL(ata_sg_init);
5714EXPORT_SYMBOL_GPL(ata_sg_init_one);
f686bcb8 5715EXPORT_SYMBOL_GPL(ata_qc_complete);
dedaf2b0 5716EXPORT_SYMBOL_GPL(ata_qc_complete_multiple);
1da177e4 5717EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
1da177e4
LT		 5718EXPORT_SYMBOL_GPL(ata_tf_load);
5719EXPORT_SYMBOL_GPL(ata_tf_read);
5720EXPORT_SYMBOL_GPL(ata_noop_dev_select);
5721EXPORT_SYMBOL_GPL(ata_std_dev_select);
5722EXPORT_SYMBOL_GPL(ata_tf_to_fis);
5723EXPORT_SYMBOL_GPL(ata_tf_from_fis);
5724EXPORT_SYMBOL_GPL(ata_check_status);
5725EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 5726EXPORT_SYMBOL_GPL(ata_exec_command);
5727EXPORT_SYMBOL_GPL(ata_port_start);
5728EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 5729EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4 5730EXPORT_SYMBOL_GPL(ata_interrupt);
a6b2c5d4
AC		 5731EXPORT_SYMBOL_GPL(ata_mmio_data_xfer);
5732EXPORT_SYMBOL_GPL(ata_pio_data_xfer);
75e99585 5733EXPORT_SYMBOL_GPL(ata_pio_data_xfer_noirq);
1da177e4 5734EXPORT_SYMBOL_GPL(ata_qc_prep);
e46834cd 5735EXPORT_SYMBOL_GPL(ata_noop_qc_prep);
1da177e4
LT		 5736EXPORT_SYMBOL_GPL(ata_bmdma_setup);
5737EXPORT_SYMBOL_GPL(ata_bmdma_start);
5738EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
5739EXPORT_SYMBOL_GPL(ata_bmdma_status);
5740EXPORT_SYMBOL_GPL(ata_bmdma_stop);
6d97dbd7
TH		 5741EXPORT_SYMBOL_GPL(ata_bmdma_freeze);
5742EXPORT_SYMBOL_GPL(ata_bmdma_thaw);
5743EXPORT_SYMBOL_GPL(ata_bmdma_drive_eh);
5744EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
5745EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
1da177e4 5746EXPORT_SYMBOL_GPL(ata_port_probe);
3c567b7d 5747EXPORT_SYMBOL_GPL(sata_set_spd);
1da177e4
LT		 5748EXPORT_SYMBOL_GPL(sata_phy_reset);
5749EXPORT_SYMBOL_GPL(__sata_phy_reset);
5750EXPORT_SYMBOL_GPL(ata_bus_reset);
8a19ac89 5751EXPORT_SYMBOL_GPL(ata_std_probeinit);
c2bd5804
TH		 5752EXPORT_SYMBOL_GPL(ata_std_softreset);
5753EXPORT_SYMBOL_GPL(sata_std_hardreset);
5754EXPORT_SYMBOL_GPL(ata_std_postreset);
5755EXPORT_SYMBOL_GPL(ata_std_probe_reset);
a62c0fc5 5756EXPORT_SYMBOL_GPL(ata_drive_probe_reset);
623a3128 5757EXPORT_SYMBOL_GPL(ata_dev_revalidate);
2e9edbf8
JG		 5758EXPORT_SYMBOL_GPL(ata_dev_classify);
5759EXPORT_SYMBOL_GPL(ata_dev_pair);
1da177e4 5760EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 5761EXPORT_SYMBOL_GPL(ata_ratelimit);
c22daff4 5762EXPORT_SYMBOL_GPL(ata_wait_register);
6f8b9958 5763EXPORT_SYMBOL_GPL(ata_busy_sleep);
86e45b6b 5764EXPORT_SYMBOL_GPL(ata_port_queue_task);
1da177e4
LT		 5765EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
5766EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
1da177e4 5767EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
a6e6ce8e 5768EXPORT_SYMBOL_GPL(ata_scsi_change_queue_depth);
1da177e4
LT		 5769EXPORT_SYMBOL_GPL(ata_scsi_release);
5770EXPORT_SYMBOL_GPL(ata_host_intr);
34bf2170
TH		 5771EXPORT_SYMBOL_GPL(sata_scr_valid);
5772EXPORT_SYMBOL_GPL(sata_scr_read);
5773EXPORT_SYMBOL_GPL(sata_scr_write);
5774EXPORT_SYMBOL_GPL(sata_scr_write_flush);
5775EXPORT_SYMBOL_GPL(ata_port_online);
5776EXPORT_SYMBOL_GPL(ata_port_offline);
6a62a04d
TH		 5777EXPORT_SYMBOL_GPL(ata_id_string);
5778EXPORT_SYMBOL_GPL(ata_id_c_string);
1da177e4
LT		 5779EXPORT_SYMBOL_GPL(ata_scsi_simulate);
5780
1bc4ccff 5781EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC		 5782EXPORT_SYMBOL_GPL(ata_timing_compute);
5783EXPORT_SYMBOL_GPL(ata_timing_merge);
5784
1da177e4
LT		 5785#ifdef CONFIG_PCI
5786EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 5787EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 5788EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
5789EXPORT_SYMBOL_GPL(ata_pci_init_one);
5790EXPORT_SYMBOL_GPL(ata_pci_remove_one);
9b847548
JA		 5791EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
5792EXPORT_SYMBOL_GPL(ata_pci_device_resume);
67951ade
AC		 5793EXPORT_SYMBOL_GPL(ata_pci_default_filter);
5794EXPORT_SYMBOL_GPL(ata_pci_clear_simplex);
1da177e4 5795#endif /* CONFIG_PCI */
9b847548
JA		 5796
5797EXPORT_SYMBOL_GPL(ata_device_suspend);
5798EXPORT_SYMBOL_GPL(ata_device_resume);
5799EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
5800EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
ece1d636 5801
ece1d636 5802EXPORT_SYMBOL_GPL(ata_eng_timeout);
7b70fc03
TH		 5803EXPORT_SYMBOL_GPL(ata_port_schedule_eh);
5804EXPORT_SYMBOL_GPL(ata_port_abort);
e3180499
TH		 5805EXPORT_SYMBOL_GPL(ata_port_freeze);
5806EXPORT_SYMBOL_GPL(ata_eh_freeze_port);
5807EXPORT_SYMBOL_GPL(ata_eh_thaw_port);
ece1d636
TH		 5808EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
5809EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
022bdb07 5810EXPORT_SYMBOL_GPL(ata_do_eh);
Linux 6.x block layer and io_uring tree(s)