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Merge tag 'pm-6.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[linux-2.6-block.git] / drivers / scsi / arcmsr / arcmsr_hba.c
CommitLineData
1c57e86d
EC		 1/*
2*******************************************************************************
3** O.S : Linux
4** FILE NAME : arcmsr_hba.c
aaa64f69
CH		 5** BY : Nick Cheng, C.L. Huang
6** Description: SCSI RAID Device Driver for Areca RAID Controller
1c57e86d 7*******************************************************************************
aaa64f69 8** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved
1c57e86d
EC		 9**
10** Web site: www.areca.com.tw
1a4f550a 11** E-mail: support@areca.com.tw
1c57e86d
EC		 12**
13** This program is free software; you can redistribute it and/or modify
14** it under the terms of the GNU General Public License version 2 as
15** published by the Free Software Foundation.
16** This program is distributed in the hope that it will be useful,
17** but WITHOUT ANY WARRANTY; without even the implied warranty of
18** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19** GNU General Public License for more details.
20*******************************************************************************
21** Redistribution and use in source and binary forms, with or without
22** modification, are permitted provided that the following conditions
23** are met:
24** 1. Redistributions of source code must retain the above copyright
25** notice, this list of conditions and the following disclaimer.
26** 2. Redistributions in binary form must reproduce the above copyright
27** notice, this list of conditions and the following disclaimer in the
28** documentation and/or other materials provided with the distribution.
29** 3. The name of the author may not be used to endorse or promote products
30** derived from this software without specific prior written permission.
31**
32** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
33** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
34** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
35** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
36** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
37** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
39** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
41** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42*******************************************************************************
43** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
dade67f4 44** Firmware Specification, see Documentation/scsi/arcmsr_spec.rst
1c57e86d
EC		 45*******************************************************************************
46*/
47#include <linux/module.h>
48#include <linux/reboot.h>
49#include <linux/spinlock.h>
50#include <linux/pci_ids.h>
51#include <linux/interrupt.h>
52#include <linux/moduleparam.h>
53#include <linux/errno.h>
54#include <linux/types.h>
55#include <linux/delay.h>
56#include <linux/dma-mapping.h>
57#include <linux/timer.h>
a7c8962b 58#include <linux/slab.h>
1c57e86d 59#include <linux/pci.h>
2e9feb43 60#include <linux/circ_buf.h>
1c57e86d
EC		 61#include <asm/dma.h>
62#include <asm/io.h>
7c0f6ba6 63#include <linux/uaccess.h>
1c57e86d
EC		 64#include <scsi/scsi_host.h>
65#include <scsi/scsi.h>
66#include <scsi/scsi_cmnd.h>
67#include <scsi/scsi_tcq.h>
68#include <scsi/scsi_device.h>
69#include <scsi/scsi_transport.h>
70#include <scsi/scsicam.h>
71#include "arcmsr.h"
aaa64f69
CH		 72MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
73MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
1c57e86d
EC		 74MODULE_LICENSE("Dual BSD/GPL");
75MODULE_VERSION(ARCMSR_DRIVER_VERSION);
8b7eb86f 76
07640404
CH		 77static int msix_enable = 1;
78module_param(msix_enable, int, S_IRUGO);
79MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)");
80
a18686eb
CH		 81static int msi_enable = 1;
82module_param(msi_enable, int, S_IRUGO);
83MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)");
84
dd6206e1
CH		 85static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
86module_param(host_can_queue, int, S_IRUGO);
87MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128");
88
abf33d83
CH		 89static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
90module_param(cmd_per_lun, int, S_IRUGO);
91MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32");
92
7ec7261f
CH		 93static int dma_mask_64 = 0;
94module_param(dma_mask_64, int, S_IRUGO);
95MODULE_PARM_DESC(dma_mask_64, " set DMA mask to 64 bits(0 ~ 1), dma_mask_64=1(64 bits), =0(32 bits)");
96
b416c099
CH		 97static int set_date_time = 0;
98module_param(set_date_time, int, S_IRUGO);
99MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable");
100
4f1826b8
H		 101static int cmd_timeout = ARCMSR_DEFAULT_TIMEOUT;
102module_param(cmd_timeout, int, S_IRUGO);
103MODULE_PARM_DESC(cmd_timeout, " scsi cmd timeout(0 ~ 120 sec.), default is 90");
104
8b7eb86f
TH		 105#define ARCMSR_SLEEPTIME 10
106#define ARCMSR_RETRYCOUNT 12
107
c10b1d54 108static wait_queue_head_t wait_q;
1a4f550a
NC		 109static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
110 struct scsi_cmnd *cmd);
111static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
1c57e86d
EC		 112static int arcmsr_abort(struct scsi_cmnd *);
113static int arcmsr_bus_reset(struct scsi_cmnd *);
114static int arcmsr_bios_param(struct scsi_device *sdev,
1a4f550a 115 struct block_device *bdev, sector_t capacity, int *info);
f281233d 116static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1c57e86d
EC		 117static int arcmsr_probe(struct pci_dev *pdev,
118 const struct pci_device_id *id);
756ebbe7
VG		 119static int __maybe_unused arcmsr_suspend(struct device *dev);
120static int __maybe_unused arcmsr_resume(struct device *dev);
1c57e86d
EC		 121static void arcmsr_remove(struct pci_dev *pdev);
122static void arcmsr_shutdown(struct pci_dev *pdev);
123static void arcmsr_iop_init(struct AdapterControlBlock *acb);
124static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
1a4f550a 125static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
61cda87f
CH		 126static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
127 u32 intmask_org);
1c57e86d 128static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
626fa32c
CH		 129static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
130static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
e99e88a9 131static void arcmsr_request_device_map(struct timer_list *t);
36b83ded 132static void arcmsr_message_isr_bh_fn(struct work_struct *work);
ae52e7f0 133static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
36b83ded 134static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
626fa32c 135static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
5b37479a 136static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
23509024
CH		 137static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb);
138static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb);
ae897ae2 139static void arcmsr_hbaF_postqueue_isr(struct AdapterControlBlock *acb);
cdd3cb15 140static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
1c57e86d
EC		 141static const char *arcmsr_info(struct Scsi_Host *);
142static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
b4eb6ae9 143static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
7e315ffd 144static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb);
b416c099 145static void arcmsr_set_iop_datetime(struct timer_list *);
4f1826b8 146static int arcmsr_slave_config(struct scsi_device *sdev);
db5ed4df 147static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
1c57e86d
EC		 148{
149 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
150 queue_depth = ARCMSR_MAX_CMD_PERLUN;
db5ed4df 151 return scsi_change_queue_depth(sdev, queue_depth);
1c57e86d
EC		 152}
153
34f5d2dc 154static const struct scsi_host_template arcmsr_scsi_host_template = {
1c57e86d 155 .module = THIS_MODULE,
76556de2 156 .proc_name = ARCMSR_NAME,
aaa64f69 157 .name = "Areca SAS/SATA RAID driver",
1c57e86d
EC		 158 .info = arcmsr_info,
159 .queuecommand = arcmsr_queue_command,
a3de4b58 160 .eh_abort_handler = arcmsr_abort,
1c57e86d
EC		 161 .eh_bus_reset_handler = arcmsr_bus_reset,
162 .bios_param = arcmsr_bios_param,
4f1826b8 163 .slave_configure = arcmsr_slave_config,
1c57e86d 164 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
dd6206e1 165 .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD,
a3de4b58
CH		 166 .this_id = ARCMSR_SCSI_INITIATOR_ID,
167 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
168 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
abf33d83 169 .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN,
f2523502 170 .shost_groups = arcmsr_host_groups,
54b2b50c 171 .no_write_same = 1,
1c57e86d 172};
8b7c9942 173
1c57e86d 174static struct pci_device_id arcmsr_device_id_table[] = {
8b7c9942
CH		 175 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
176 .driver_data = ACB_ADAPTER_TYPE_A},
177 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
178 .driver_data = ACB_ADAPTER_TYPE_A},
179 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
180 .driver_data = ACB_ADAPTER_TYPE_A},
181 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
182 .driver_data = ACB_ADAPTER_TYPE_A},
183 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
184 .driver_data = ACB_ADAPTER_TYPE_A},
185 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
186 .driver_data = ACB_ADAPTER_TYPE_B},
187 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
188 .driver_data = ACB_ADAPTER_TYPE_B},
189 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
190 .driver_data = ACB_ADAPTER_TYPE_B},
7e315ffd
CH		 191 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203),
192 .driver_data = ACB_ADAPTER_TYPE_B},
8b7c9942
CH		 193 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
194 .driver_data = ACB_ADAPTER_TYPE_A},
5b37479a
CH		 195 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
196 .driver_data = ACB_ADAPTER_TYPE_D},
8b7c9942
CH		 197 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
198 .driver_data = ACB_ADAPTER_TYPE_A},
199 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
200 .driver_data = ACB_ADAPTER_TYPE_A},
201 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
202 .driver_data = ACB_ADAPTER_TYPE_A},
203 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
204 .driver_data = ACB_ADAPTER_TYPE_A},
205 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
206 .driver_data = ACB_ADAPTER_TYPE_A},
207 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
208 .driver_data = ACB_ADAPTER_TYPE_A},
209 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
210 .driver_data = ACB_ADAPTER_TYPE_A},
211 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
212 .driver_data = ACB_ADAPTER_TYPE_A},
213 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
214 .driver_data = ACB_ADAPTER_TYPE_A},
215 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
216 .driver_data = ACB_ADAPTER_TYPE_C},
41c8a1a1
H		 217 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1883),
218 .driver_data = ACB_ADAPTER_TYPE_C},
23509024
CH		 219 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884),
220 .driver_data = ACB_ADAPTER_TYPE_E},
41c8a1a1
H		 221 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1886_0),
222 .driver_data = ACB_ADAPTER_TYPE_F},
ae897ae2
H		 223 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1886),
224 .driver_data = ACB_ADAPTER_TYPE_F},
1c57e86d
EC		 225 {0, 0}, /* Terminating entry */
226};
227MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
8b7c9942 228
756ebbe7
VG		 229static SIMPLE_DEV_PM_OPS(arcmsr_pm_ops, arcmsr_suspend, arcmsr_resume);
230
1c57e86d
EC		 231static struct pci_driver arcmsr_pci_driver = {
232 .name = "arcmsr",
a3de4b58 233 .id_table = arcmsr_device_id_table,
1c57e86d
EC		 234 .probe = arcmsr_probe,
235 .remove = arcmsr_remove,
756ebbe7 236 .driver.pm = &arcmsr_pm_ops,
a1f6e021 237 .shutdown = arcmsr_shutdown,
1c57e86d 238};
cdd3cb15
NC		 239/*
240****************************************************************************
241****************************************************************************
242*/
1c57e86d 243
609d0858 244static void arcmsr_free_io_queue(struct AdapterControlBlock *acb)
ae52e7f0
NC		 245{
246 switch (acb->adapter_type) {
5b37479a 247 case ACB_ADAPTER_TYPE_B:
23509024 248 case ACB_ADAPTER_TYPE_D:
ae897ae2
H		 249 case ACB_ADAPTER_TYPE_E:
250 case ACB_ADAPTER_TYPE_F:
381d66da 251 dma_free_coherent(&acb->pdev->dev, acb->ioqueue_size,
6e38adfc
CH		 252 acb->dma_coherent2, acb->dma_coherent_handle2);
253 break;
ae52e7f0 254 }
ae52e7f0
NC		 255}
256
257static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
258{
259 struct pci_dev *pdev = acb->pdev;
cdd3cb15 260 switch (acb->adapter_type){
ae52e7f0 261 case ACB_ADAPTER_TYPE_A:{
cdd3cb15 262 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
ae52e7f0
NC		 263 if (!acb->pmuA) {
264 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
265 return false;
266 }
267 break;
268 }
269 case ACB_ADAPTER_TYPE_B:{
270 void __iomem *mem_base0, *mem_base1;
271 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
272 if (!mem_base0) {
273 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
274 return false;
275 }
276 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
277 if (!mem_base1) {
278 iounmap(mem_base0);
279 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
280 return false;
281 }
282 acb->mem_base0 = mem_base0;
283 acb->mem_base1 = mem_base1;
cdd3cb15
NC		 284 break;
285 }
286 case ACB_ADAPTER_TYPE_C:{
4bdc0d67 287 acb->pmuC = ioremap(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
cdd3cb15
NC		 288 if (!acb->pmuC) {
289 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
290 return false;
291 }
292 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
293 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
294 return true;
295 }
296 break;
ae52e7f0 297 }
5b37479a
CH		 298 case ACB_ADAPTER_TYPE_D: {
299 void __iomem *mem_base0;
18bc435e 300 unsigned long addr, range;
5b37479a
CH		 301
302 addr = (unsigned long)pci_resource_start(pdev, 0);
303 range = pci_resource_len(pdev, 0);
92b19ff5 304 mem_base0 = ioremap(addr, range);
5b37479a
CH		 305 if (!mem_base0) {
306 pr_notice("arcmsr%d: memory mapping region fail\n",
307 acb->host->host_no);
308 return false;
309 }
310 acb->mem_base0 = mem_base0;
311 break;
312 }
23509024
CH		 313 case ACB_ADAPTER_TYPE_E: {
314 acb->pmuE = ioremap(pci_resource_start(pdev, 1),
315 pci_resource_len(pdev, 1));
316 if (!acb->pmuE) {
317 pr_notice("arcmsr%d: memory mapping region fail \n",
318 acb->host->host_no);
319 return false;
320 }
321 writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/
322 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); /* synchronize doorbell to 0 */
323 acb->in_doorbell = 0;
324 acb->out_doorbell = 0;
325 break;
326 }
ae897ae2
H		 327 case ACB_ADAPTER_TYPE_F: {
328 acb->pmuF = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
329 if (!acb->pmuF) {
330 pr_notice("arcmsr%d: memory mapping region fail\n",
331 acb->host->host_no);
332 return false;
333 }
334 writel(0, &acb->pmuF->host_int_status); /* clear interrupt */
335 writel(ARCMSR_HBFMU_DOORBELL_SYNC, &acb->pmuF->iobound_doorbell);
336 acb->in_doorbell = 0;
337 acb->out_doorbell = 0;
338 break;
339 }
ae52e7f0
NC		 340 }
341 return true;
342}
343
344static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
345{
346 switch (acb->adapter_type) {
9aae1c1f 347 case ACB_ADAPTER_TYPE_A:
cdd3cb15 348 iounmap(acb->pmuA);
9aae1c1f
H		 349 break;
350 case ACB_ADAPTER_TYPE_B:
cdd3cb15
NC		 351 iounmap(acb->mem_base0);
352 iounmap(acb->mem_base1);
9aae1c1f
H		 353 break;
354 case ACB_ADAPTER_TYPE_C:
cdd3cb15 355 iounmap(acb->pmuC);
9aae1c1f 356 break;
5b37479a
CH		 357 case ACB_ADAPTER_TYPE_D:
358 iounmap(acb->mem_base0);
359 break;
23509024
CH		 360 case ACB_ADAPTER_TYPE_E:
361 iounmap(acb->pmuE);
362 break;
ae897ae2
H		 363 case ACB_ADAPTER_TYPE_F:
364 iounmap(acb->pmuF);
365 break;
ae52e7f0
NC		 366 }
367}
368
7d12e780 369static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
1c57e86d
EC		 370{
371 irqreturn_t handle_state;
1a4f550a 372 struct AdapterControlBlock *acb = dev_id;
1c57e86d 373
1c57e86d 374 handle_state = arcmsr_interrupt(acb);
1c57e86d
EC		 375 return handle_state;
376}
377
378static int arcmsr_bios_param(struct scsi_device *sdev,
379 struct block_device *bdev, sector_t capacity, int *geom)
380{
a10183d7
CH		 381 int heads, sectors, cylinders, total_capacity;
382
383 if (scsi_partsize(bdev, capacity, geom))
384 return 0;
1c57e86d 385
1c57e86d
EC		 386 total_capacity = capacity;
387 heads = 64;
388 sectors = 32;
389 cylinders = total_capacity / (heads * sectors);
390 if (cylinders > 1024) {
391 heads = 255;
392 sectors = 63;
393 cylinders = total_capacity / (heads * sectors);
394 }
395 geom[0] = heads;
396 geom[1] = sectors;
397 geom[2] = cylinders;
398 return 0;
399}
400
626fa32c 401static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
ae52e7f0
NC		 402{
403 struct MessageUnit_A __iomem *reg = acb->pmuA;
8b7eb86f
TH		 404 int i;
405
406 for (i = 0; i < 2000; i++) {
407 if (readl(&reg->outbound_intstatus) &
408 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
409 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
410 &reg->outbound_intstatus);
411 return true;
412 }
413 msleep(10);
414 } /* max 20 seconds */
ae52e7f0 415
cdd3cb15 416 return false;
ae52e7f0
NC		 417}
418
626fa32c 419static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
1a4f550a 420{
ae52e7f0 421 struct MessageUnit_B *reg = acb->pmuB;
8b7eb86f
TH		 422 int i;
423
424 for (i = 0; i < 2000; i++) {
425 if (readl(reg->iop2drv_doorbell)
426 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
427 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
428 reg->iop2drv_doorbell);
429 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
430 reg->drv2iop_doorbell);
431 return true;
432 }
433 msleep(10);
434 } /* max 20 seconds */
ae52e7f0 435
cdd3cb15 436 return false;
ae52e7f0
NC		 437}
438
626fa32c 439static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
cdd3cb15 440{
c10b1d54 441 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
8b7eb86f
TH		 442 int i;
443
444 for (i = 0; i < 2000; i++) {
445 if (readl(&phbcmu->outbound_doorbell)
446 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
447 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
448 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
449 return true;
450 }
451 msleep(10);
452 } /* max 20 seconds */
453
cdd3cb15
NC		 454 return false;
455}
8b7eb86f 456
5b37479a
CH		 457static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
458{
459 struct MessageUnit_D *reg = pACB->pmuD;
460 int i;
461
462 for (i = 0; i < 2000; i++) {
463 if (readl(reg->outbound_doorbell)
464 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
465 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
466 reg->outbound_doorbell);
467 return true;
468 }
469 msleep(10);
470 } /* max 20 seconds */
471 return false;
472}
473
23509024
CH		 474static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB)
475{
476 int i;
477 uint32_t read_doorbell;
478 struct MessageUnit_E __iomem *phbcmu = pACB->pmuE;
479
480 for (i = 0; i < 2000; i++) {
481 read_doorbell = readl(&phbcmu->iobound_doorbell);
482 if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
483 writel(0, &phbcmu->host_int_status); /*clear interrupt*/
484 pACB->in_doorbell = read_doorbell;
485 return true;
486 }
487 msleep(10);
488 } /* max 20 seconds */
489 return false;
490}
491
626fa32c 492static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
ae52e7f0
NC		 493{
494 struct MessageUnit_A __iomem *reg = acb->pmuA;
495 int retry_count = 30;
ae52e7f0
NC		 496 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
497 do {
626fa32c 498 if (arcmsr_hbaA_wait_msgint_ready(acb))
ae52e7f0
NC		 499 break;
500 else {
501 retry_count--;
502 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
503 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
504 }
505 } while (retry_count != 0);
506}
507
626fa32c 508static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
ae52e7f0
NC		 509{
510 struct MessageUnit_B *reg = acb->pmuB;
511 int retry_count = 30;
ae52e7f0
NC		 512 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
513 do {
626fa32c 514 if (arcmsr_hbaB_wait_msgint_ready(acb))
ae52e7f0
NC		 515 break;
516 else {
517 retry_count--;
518 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
519 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
520 }
521 } while (retry_count != 0);
522}
523
626fa32c 524static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
cdd3cb15 525{
c10b1d54 526 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 527 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
528 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
529 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
530 do {
626fa32c 531 if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15
NC		 532 break;
533 } else {
534 retry_count--;
535 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
536 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
537 }
538 } while (retry_count != 0);
539 return;
540}
5b37479a
CH		 541
542static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
543{
544 int retry_count = 15;
545 struct MessageUnit_D *reg = pACB->pmuD;
546
547 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
548 do {
549 if (arcmsr_hbaD_wait_msgint_ready(pACB))
550 break;
551
552 retry_count--;
553 pr_notice("arcmsr%d: wait 'flush adapter "
554 "cache' timeout, retry count down = %d\n",
555 pACB->host->host_no, retry_count);
556 } while (retry_count != 0);
557}
558
23509024
CH		 559static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB)
560{
561 int retry_count = 30;
562 struct MessageUnit_E __iomem *reg = pACB->pmuE;
563
564 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
565 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
566 writel(pACB->out_doorbell, &reg->iobound_doorbell);
567 do {
568 if (arcmsr_hbaE_wait_msgint_ready(pACB))
569 break;
570 retry_count--;
571 pr_notice("arcmsr%d: wait 'flush adapter "
572 "cache' timeout, retry count down = %d\n",
573 pACB->host->host_no, retry_count);
574 } while (retry_count != 0);
575}
576
ae52e7f0
NC		 577static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
578{
1a4f550a 579 switch (acb->adapter_type) {
1c57e86d 580
9aae1c1f 581 case ACB_ADAPTER_TYPE_A:
626fa32c 582 arcmsr_hbaA_flush_cache(acb);
ae52e7f0 583 break;
9aae1c1f 584 case ACB_ADAPTER_TYPE_B:
626fa32c 585 arcmsr_hbaB_flush_cache(acb);
cdd3cb15 586 break;
9aae1c1f 587 case ACB_ADAPTER_TYPE_C:
626fa32c 588 arcmsr_hbaC_flush_cache(acb);
5b37479a
CH		 589 break;
590 case ACB_ADAPTER_TYPE_D:
591 arcmsr_hbaD_flush_cache(acb);
592 break;
23509024 593 case ACB_ADAPTER_TYPE_E:
ae897ae2 594 case ACB_ADAPTER_TYPE_F:
23509024
CH		 595 arcmsr_hbaE_flush_cache(acb);
596 break;
ae52e7f0
NC		 597 }
598}
1a4f550a 599
222f1189
CH		 600static void arcmsr_hbaB_assign_regAddr(struct AdapterControlBlock *acb)
601{
602 struct MessageUnit_B *reg = acb->pmuB;
603
604 if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) {
605 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203);
606 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203);
607 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203);
608 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203);
609 } else {
610 reg->drv2iop_doorbell= MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL);
611 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK);
612 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL);
613 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK);
614 }
615 reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER);
616 reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER);
617 reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER);
618}
619
620static void arcmsr_hbaD_assign_regAddr(struct AdapterControlBlock *acb)
621{
622 struct MessageUnit_D *reg = acb->pmuD;
623
624 reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID);
625 reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION);
626 reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK);
627 reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET);
628 reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST);
629 reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS);
630 reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE);
631 reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0);
632 reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1);
633 reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0);
634 reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1);
635 reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL);
636 reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL);
637 reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE);
638 reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW);
639 reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH);
640 reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER);
641 reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW);
642 reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH);
643 reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER);
644 reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER);
645 reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE);
646 reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE);
647 reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER);
648 reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER);
649 reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER);
650}
651
ae897ae2
H		 652static void arcmsr_hbaF_assign_regAddr(struct AdapterControlBlock *acb)
653{
654 dma_addr_t host_buffer_dma;
655 struct MessageUnit_F __iomem *pmuF;
656
657 memset(acb->dma_coherent2, 0xff, acb->completeQ_size);
658 acb->message_wbuffer = (uint32_t *)round_up((unsigned long)acb->dma_coherent2 +
659 acb->completeQ_size, 4);
660 acb->message_rbuffer = ((void *)acb->message_wbuffer) + 0x100;
661 acb->msgcode_rwbuffer = ((void *)acb->message_wbuffer) + 0x200;
662 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE);
663 host_buffer_dma = round_up(acb->dma_coherent_handle2 + acb->completeQ_size, 4);
664 pmuF = acb->pmuF;
665 /* host buffer low address, bit0:1 all buffer active */
666 writel(lower_32_bits(host_buffer_dma | 1), &pmuF->inbound_msgaddr0);
667 /* host buffer high address */
668 writel(upper_32_bits(host_buffer_dma), &pmuF->inbound_msgaddr1);
669 /* set host buffer physical address */
670 writel(ARCMSR_HBFMU_DOORBELL_SYNC1, &pmuF->iobound_doorbell);
671}
672
02040670
CH		 673static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb)
674{
675 bool rtn = true;
676 void *dma_coherent;
677 dma_addr_t dma_coherent_handle;
678 struct pci_dev *pdev = acb->pdev;
679
680 switch (acb->adapter_type) {
681 case ACB_ADAPTER_TYPE_B: {
381d66da 682 acb->ioqueue_size = roundup(sizeof(struct MessageUnit_B), 32);
3e3153b0 683 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
02040670
CH		 684 &dma_coherent_handle, GFP_KERNEL);
685 if (!dma_coherent) {
686 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
687 return false;
688 }
689 acb->dma_coherent_handle2 = dma_coherent_handle;
690 acb->dma_coherent2 = dma_coherent;
222f1189
CH		 691 acb->pmuB = (struct MessageUnit_B *)dma_coherent;
692 arcmsr_hbaB_assign_regAddr(acb);
02040670
CH		 693 }
694 break;
695 case ACB_ADAPTER_TYPE_D: {
381d66da 696 acb->ioqueue_size = roundup(sizeof(struct MessageUnit_D), 32);
3e3153b0 697 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
02040670
CH		 698 &dma_coherent_handle, GFP_KERNEL);
699 if (!dma_coherent) {
700 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
701 return false;
702 }
703 acb->dma_coherent_handle2 = dma_coherent_handle;
704 acb->dma_coherent2 = dma_coherent;
222f1189
CH		 705 acb->pmuD = (struct MessageUnit_D *)dma_coherent;
706 arcmsr_hbaD_assign_regAddr(acb);
02040670
CH		 707 }
708 break;
23509024
CH		 709 case ACB_ADAPTER_TYPE_E: {
710 uint32_t completeQ_size;
711 completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128;
381d66da 712 acb->ioqueue_size = roundup(completeQ_size, 32);
3e3153b0 713 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
23509024
CH		 714 &dma_coherent_handle, GFP_KERNEL);
715 if (!dma_coherent){
716 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
717 return false;
718 }
719 acb->dma_coherent_handle2 = dma_coherent_handle;
720 acb->dma_coherent2 = dma_coherent;
721 acb->pCompletionQ = dma_coherent;
381d66da 722 acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ);
23509024
CH		 723 acb->doneq_index = 0;
724 }
725 break;
ae897ae2
H		 726 case ACB_ADAPTER_TYPE_F: {
727 uint32_t QueueDepth;
728 uint32_t depthTbl[] = {256, 512, 1024, 128, 64, 32};
729
730 arcmsr_wait_firmware_ready(acb);
731 QueueDepth = depthTbl[readl(&acb->pmuF->outbound_msgaddr1) & 7];
732 acb->completeQ_size = sizeof(struct deliver_completeQ) * QueueDepth + 128;
733 acb->ioqueue_size = roundup(acb->completeQ_size + MESG_RW_BUFFER_SIZE, 32);
734 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
735 &dma_coherent_handle, GFP_KERNEL);
736 if (!dma_coherent) {
737 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
738 return false;
739 }
740 acb->dma_coherent_handle2 = dma_coherent_handle;
741 acb->dma_coherent2 = dma_coherent;
742 acb->pCompletionQ = dma_coherent;
743 acb->completionQ_entry = acb->completeQ_size / sizeof(struct deliver_completeQ);
744 acb->doneq_index = 0;
745 arcmsr_hbaF_assign_regAddr(acb);
746 }
747 break;
02040670
CH		 748 default:
749 break;
750 }
751 return rtn;
752}
753
14ef4b00
H		 754static int arcmsr_alloc_xor_buffer(struct AdapterControlBlock *acb)
755{
756 int rc = 0;
757 struct pci_dev *pdev = acb->pdev;
758 void *dma_coherent;
759 dma_addr_t dma_coherent_handle;
760 int i, xor_ram;
761 struct Xor_sg *pXorPhys;
762 void **pXorVirt;
763 struct HostRamBuf *pRamBuf;
764
765 // allocate 1 MB * N physically continuous memory for XOR engine.
766 xor_ram = (acb->firm_PicStatus >> 24) & 0x0f;
767 acb->xor_mega = (xor_ram - 1) * 32 + 128 + 3;
768 acb->init2cfg_size = sizeof(struct HostRamBuf) +
769 (sizeof(struct XorHandle) * acb->xor_mega);
770 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->init2cfg_size,
771 &dma_coherent_handle, GFP_KERNEL);
772 acb->xorVirt = dma_coherent;
773 acb->xorPhys = dma_coherent_handle;
774 pXorPhys = (struct Xor_sg *)((unsigned long)dma_coherent +
775 sizeof(struct HostRamBuf));
776 acb->xorVirtOffset = sizeof(struct HostRamBuf) +
777 (sizeof(struct Xor_sg) * acb->xor_mega);
778 pXorVirt = (void **)((unsigned long)dma_coherent +
779 (unsigned long)acb->xorVirtOffset);
780 for (i = 0; i < acb->xor_mega; i++) {
781 dma_coherent = dma_alloc_coherent(&pdev->dev,
782 ARCMSR_XOR_SEG_SIZE,
783 &dma_coherent_handle, GFP_KERNEL);
784 if (dma_coherent) {
785 pXorPhys->xorPhys = dma_coherent_handle;
786 pXorPhys->xorBufLen = ARCMSR_XOR_SEG_SIZE;
787 *pXorVirt = dma_coherent;
788 pXorPhys++;
789 pXorVirt++;
790 } else {
791 pr_info("arcmsr%d: alloc max XOR buffer = 0x%x MB\n",
792 acb->host->host_no, i);
793 rc = -ENOMEM;
794 break;
795 }
796 }
797 pRamBuf = (struct HostRamBuf *)acb->xorVirt;
798 pRamBuf->hrbSignature = 0x53425248; //HRBS
799 pRamBuf->hrbSize = i * ARCMSR_XOR_SEG_SIZE;
800 pRamBuf->hrbRes[0] = 0;
801 pRamBuf->hrbRes[1] = 0;
802 return rc;
803}
804
ae52e7f0
NC		 805static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
806{
cdd3cb15
NC		 807 struct pci_dev *pdev = acb->pdev;
808 void *dma_coherent;
809 dma_addr_t dma_coherent_handle;
810 struct CommandControlBlock *ccb_tmp;
811 int i = 0, j = 0;
7860a486 812 unsigned long cdb_phyaddr, next_ccb_phy;
87f76152 813 unsigned long roundup_ccbsize;
cdd3cb15
NC		 814 unsigned long max_xfer_len;
815 unsigned long max_sg_entrys;
7860a486 816 uint32_t firm_config_version, curr_phy_upper32;
87f76152 817
cdd3cb15
NC		 818 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
819 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
820 acb->devstate[i][j] = ARECA_RAID_GONE;
821
822 max_xfer_len = ARCMSR_MAX_XFER_LEN;
823 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
824 firm_config_version = acb->firm_cfg_version;
825 if((firm_config_version & 0xFF) >= 3){
826 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
87f76152 827 max_sg_entrys = (max_xfer_len/4096);
cdd3cb15
NC		 828 }
829 acb->host->max_sectors = max_xfer_len/512;
830 acb->host->sg_tablesize = max_sg_entrys;
831 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
d076e4aa 832 acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB;
ae897ae2
H		 833 if (acb->adapter_type != ACB_ADAPTER_TYPE_F)
834 acb->uncache_size += acb->ioqueue_size;
cdd3cb15
NC		 835 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
836 if(!dma_coherent){
87f76152 837 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
cdd3cb15
NC		 838 return -ENOMEM;
839 }
840 acb->dma_coherent = dma_coherent;
841 acb->dma_coherent_handle = dma_coherent_handle;
842 memset(dma_coherent, 0, acb->uncache_size);
23509024 843 acb->ccbsize = roundup_ccbsize;
cdd3cb15 844 ccb_tmp = dma_coherent;
7860a486 845 curr_phy_upper32 = upper_32_bits(dma_coherent_handle);
cdd3cb15 846 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
d076e4aa 847 for(i = 0; i < acb->maxFreeCCB; i++){
7860a486 848 cdb_phyaddr = (unsigned long)dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
5b37479a
CH		 849 switch (acb->adapter_type) {
850 case ACB_ADAPTER_TYPE_A:
851 case ACB_ADAPTER_TYPE_B:
852 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
853 break;
854 case ACB_ADAPTER_TYPE_C:
855 case ACB_ADAPTER_TYPE_D:
23509024 856 case ACB_ADAPTER_TYPE_E:
ae897ae2 857 case ACB_ADAPTER_TYPE_F:
5b37479a
CH		 858 ccb_tmp->cdb_phyaddr = cdb_phyaddr;
859 break;
860 }
cdd3cb15
NC		 861 acb->pccb_pool[i] = ccb_tmp;
862 ccb_tmp->acb = acb;
23509024 863 ccb_tmp->smid = (u32)i << 16;
cdd3cb15 864 INIT_LIST_HEAD(&ccb_tmp->list);
7860a486
CH		 865 next_ccb_phy = dma_coherent_handle + roundup_ccbsize;
866 if (upper_32_bits(next_ccb_phy) != curr_phy_upper32) {
867 acb->maxFreeCCB = i;
868 acb->host->can_queue = i;
869 break;
870 }
871 else
872 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
cdd3cb15 873 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
7860a486 874 dma_coherent_handle = next_ccb_phy;
1a4f550a 875 }
ae897ae2
H		 876 if (acb->adapter_type != ACB_ADAPTER_TYPE_F) {
877 acb->dma_coherent_handle2 = dma_coherent_handle;
878 acb->dma_coherent2 = ccb_tmp;
879 }
222f1189
CH		 880 switch (acb->adapter_type) {
881 case ACB_ADAPTER_TYPE_B:
882 acb->pmuB = (struct MessageUnit_B *)acb->dma_coherent2;
883 arcmsr_hbaB_assign_regAddr(acb);
884 break;
885 case ACB_ADAPTER_TYPE_D:
886 acb->pmuD = (struct MessageUnit_D *)acb->dma_coherent2;
887 arcmsr_hbaD_assign_regAddr(acb);
888 break;
889 case ACB_ADAPTER_TYPE_E:
890 acb->pCompletionQ = acb->dma_coherent2;
891 acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ);
892 acb->doneq_index = 0;
893 break;
14ef4b00
H		 894 }
895 if ((acb->firm_PicStatus >> 24) & 0x0f) {
896 if (arcmsr_alloc_xor_buffer(acb))
897 return -ENOMEM;
898 }
1c57e86d
EC		 899 return 0;
900}
36b83ded 901
cdd3cb15
NC		 902static void arcmsr_message_isr_bh_fn(struct work_struct *work)
903{
12aad947
CH		 904 struct AdapterControlBlock *acb = container_of(work,
905 struct AdapterControlBlock, arcmsr_do_message_isr_bh);
906 char *acb_dev_map = (char *)acb->device_map;
907 uint32_t __iomem *signature = NULL;
908 char __iomem *devicemap = NULL;
909 int target, lun;
910 struct scsi_device *psdev;
911 char diff, temp;
912
36b83ded 913 switch (acb->adapter_type) {
12aad947
CH		 914 case ACB_ADAPTER_TYPE_A: {
915 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 916
12aad947
CH		 917 signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
918 devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
cdd3cb15 919 break;
12aad947
CH		 920 }
921 case ACB_ADAPTER_TYPE_B: {
922 struct MessageUnit_B *reg = acb->pmuB;
923
924 signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
925 devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
926 break;
927 }
928 case ACB_ADAPTER_TYPE_C: {
929 struct MessageUnit_C __iomem *reg = acb->pmuC;
930
931 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
932 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
933 break;
934 }
5b37479a
CH		 935 case ACB_ADAPTER_TYPE_D: {
936 struct MessageUnit_D *reg = acb->pmuD;
937
938 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
939 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
940 break;
941 }
23509024
CH		 942 case ACB_ADAPTER_TYPE_E: {
943 struct MessageUnit_E __iomem *reg = acb->pmuE;
944
945 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
946 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
947 break;
948 }
ae897ae2
H		 949 case ACB_ADAPTER_TYPE_F: {
950 signature = (uint32_t __iomem *)(&acb->msgcode_rwbuffer[0]);
951 devicemap = (char __iomem *)(&acb->msgcode_rwbuffer[21]);
952 break;
953 }
12aad947 954 }
12aad947
CH		 955 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
956 return;
957 for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
958 target++) {
959 temp = readb(devicemap);
960 diff = (*acb_dev_map) ^ temp;
961 if (diff != 0) {
962 *acb_dev_map = temp;
963 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
964 lun++) {
965 if ((diff & 0x01) == 1 &&
966 (temp & 0x01) == 1) {
967 scsi_add_device(acb->host,
968 0, target, lun);
969 } else if ((diff & 0x01) == 1
970 && (temp & 0x01) == 0) {
971 psdev = scsi_device_lookup(acb->host,
972 0, target, lun);
973 if (psdev != NULL) {
974 scsi_remove_device(psdev);
975 scsi_device_put(psdev);
36b83ded 976 }
36b83ded 977 }
12aad947
CH		 978 temp >>= 1;
979 diff >>= 1;
36b83ded
NC		 980 }
981 }
12aad947
CH		 982 devicemap++;
983 acb_dev_map++;
36b83ded 984 }
893f4a14 985 acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG;
36b83ded 986}
1c57e86d 987
1d1166ea
CH		 988static int
989arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
990{
68130c99
CH		 991 unsigned long flags;
992 int nvec, i;
993
07640404
CH		 994 if (msix_enable == 0)
995 goto msi_int0;
68130c99
CH		 996 nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS,
997 PCI_IRQ_MSIX);
998 if (nvec > 0) {
999 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
1000 flags = 0;
1001 } else {
07640404 1002msi_int0:
a18686eb
CH		 1003 if (msi_enable == 1) {
1004 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1005 if (nvec == 1) {
1006 dev_info(&pdev->dev, "msi enabled\n");
1007 goto msi_int1;
1008 }
1009 }
416bdc40 1010 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_INTX);
68130c99
CH		 1011 if (nvec < 1)
1012 return FAILED;
a18686eb 1013msi_int1:
68130c99
CH		 1014 flags = IRQF_SHARED;
1015 }
1016
1017 acb->vector_count = nvec;
1018 for (i = 0; i < nvec; i++) {
1019 if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt,
1020 flags, "arcmsr", acb)) {
1d1166ea 1021 pr_warn("arcmsr%d: request_irq =%d failed!\n",
68130c99
CH		 1022 acb->host->host_no, pci_irq_vector(pdev, i));
1023 goto out_free_irq;
1d1166ea 1024 }
1d1166ea 1025 }
68130c99 1026
1d1166ea 1027 return SUCCESS;
68130c99
CH		 1028out_free_irq:
1029 while (--i >= 0)
1030 free_irq(pci_irq_vector(pdev, i), acb);
1031 pci_free_irq_vectors(pdev);
1032 return FAILED;
1d1166ea
CH		 1033}
1034
ea331f30
CH		 1035static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb)
1036{
1037 INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
ea331f30
CH		 1038 pacb->fw_flag = FW_NORMAL;
1039 timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0);
1040 pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
1041 add_timer(&pacb->eternal_timer);
1042}
1043
b416c099
CH		 1044static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb)
1045{
1046 timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0);
1047 pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000);
1048 add_timer(&pacb->refresh_timer);
1049}
1050
1d120c61
CH		 1051static int arcmsr_set_dma_mask(struct AdapterControlBlock *acb)
1052{
1053 struct pci_dev *pcidev = acb->pdev;
1054
1055 if (IS_DMA64) {
1056 if (((acb->adapter_type == ACB_ADAPTER_TYPE_A) && !dma_mask_64) ||
1057 dma_set_mask(&pcidev->dev, DMA_BIT_MASK(64)))
1058 goto dma32;
c3e9b937
H		 1059 if (acb->adapter_type <= ACB_ADAPTER_TYPE_B)
1060 return 0;
1d120c61
CH		 1061 if (dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(64)) ||
1062 dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64))) {
1063 printk("arcmsr: set DMA 64 mask failed\n");
1064 return -ENXIO;
1065 }
1066 } else {
1067dma32:
1068 if (dma_set_mask(&pcidev->dev, DMA_BIT_MASK(32)) ||
1069 dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(32)) ||
1070 dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32))) {
1071 printk("arcmsr: set DMA 32-bit mask failed\n");
1072 return -ENXIO;
1073 }
1074 }
1075 return 0;
1076}
1077
ae52e7f0 1078static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1c57e86d
EC		 1079{
1080 struct Scsi_Host *host;
1081 struct AdapterControlBlock *acb;
cdd3cb15 1082 uint8_t bus,dev_fun;
1c57e86d 1083 int error;
1c57e86d 1084 error = pci_enable_device(pdev);
cdd3cb15 1085 if(error){
ae52e7f0
NC		 1086 return -ENODEV;
1087 }
1088 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
cdd3cb15
NC		 1089 if(!host){
1090 goto pci_disable_dev;
1c57e86d 1091 }
ae52e7f0 1092 init_waitqueue_head(&wait_q);
1c57e86d
EC		 1093 bus = pdev->bus->number;
1094 dev_fun = pdev->devfn;
ae52e7f0 1095 acb = (struct AdapterControlBlock *) host->hostdata;
cdd3cb15 1096 memset(acb,0,sizeof(struct AdapterControlBlock));
1c57e86d 1097 acb->pdev = pdev;
1d120c61
CH		 1098 acb->adapter_type = id->driver_data;
1099 if (arcmsr_set_dma_mask(acb))
1100 goto scsi_host_release;
ae52e7f0 1101 acb->host = host;
1c57e86d 1102 host->max_lun = ARCMSR_MAX_TARGETLUN;
cdd3cb15
NC		 1103 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
1104 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
dd6206e1
CH		 1105 if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD))
1106 host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
1107 host->can_queue = host_can_queue; /* max simultaneous cmds */
abf33d83
CH		 1108 if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN))
1109 cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
1110 host->cmd_per_lun = cmd_per_lun;
1c57e86d
EC		 1111 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
1112 host->unique_id = (bus << 8) | dev_fun;
ae52e7f0
NC		 1113 pci_set_drvdata(pdev, host);
1114 pci_set_master(pdev);
1c57e86d 1115 error = pci_request_regions(pdev, "arcmsr");
cdd3cb15 1116 if(error){
ae52e7f0 1117 goto scsi_host_release;
1c57e86d 1118 }
ae52e7f0
NC		 1119 spin_lock_init(&acb->eh_lock);
1120 spin_lock_init(&acb->ccblist_lock);
5b37479a
CH		 1121 spin_lock_init(&acb->postq_lock);
1122 spin_lock_init(&acb->doneq_lock);
bb263c4e
CH		 1123 spin_lock_init(&acb->rqbuffer_lock);
1124 spin_lock_init(&acb->wqbuffer_lock);
1c57e86d 1125 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
cdd3cb15
NC		 1126 ACB_F_MESSAGE_RQBUFFER_CLEARED |
1127 ACB_F_MESSAGE_WQBUFFER_READED);
1c57e86d
EC		 1128 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
1129 INIT_LIST_HEAD(&acb->ccb_free_list);
ae52e7f0 1130 error = arcmsr_remap_pciregion(acb);
cdd3cb15 1131 if(!error){
ae52e7f0
NC		 1132 goto pci_release_regs;
1133 }
02040670
CH		 1134 error = arcmsr_alloc_io_queue(acb);
1135 if (!error)
1136 goto unmap_pci_region;
ae52e7f0 1137 error = arcmsr_get_firmware_spec(acb);
cdd3cb15 1138 if(!error){
02040670 1139 goto free_hbb_mu;
ae52e7f0 1140 }
ae897ae2
H		 1141 if (acb->adapter_type != ACB_ADAPTER_TYPE_F)
1142 arcmsr_free_io_queue(acb);
1c57e86d 1143 error = arcmsr_alloc_ccb_pool(acb);
cdd3cb15 1144 if(error){
222f1189 1145 goto unmap_pci_region;
ae52e7f0 1146 }
1c57e86d 1147 error = scsi_add_host(host, &pdev->dev);
cdd3cb15 1148 if(error){
b4eb6ae9 1149 goto free_ccb_pool;
ae52e7f0 1150 }
1d1166ea 1151 if (arcmsr_request_irq(pdev, acb) == FAILED)
ae52e7f0 1152 goto scsi_host_remove;
1d1166ea 1153 arcmsr_iop_init(acb);
ea331f30 1154 arcmsr_init_get_devmap_timer(acb);
b416c099
CH		 1155 if (set_date_time)
1156 arcmsr_init_set_datetime_timer(acb);
cdd3cb15 1157 if(arcmsr_alloc_sysfs_attr(acb))
ae52e7f0 1158 goto out_free_sysfs;
b4eb6ae9 1159 scsi_scan_host(host);
1c57e86d 1160 return 0;
cdd3cb15 1161out_free_sysfs:
b416c099
CH		 1162 if (set_date_time)
1163 del_timer_sync(&acb->refresh_timer);
b4eb6ae9
CH		 1164 del_timer_sync(&acb->eternal_timer);
1165 flush_work(&acb->arcmsr_do_message_isr_bh);
ae52e7f0
NC		 1166 arcmsr_stop_adapter_bgrb(acb);
1167 arcmsr_flush_adapter_cache(acb);
b4eb6ae9
CH		 1168 arcmsr_free_irq(pdev, acb);
1169scsi_host_remove:
1170 scsi_remove_host(host);
1171free_ccb_pool:
1c57e86d 1172 arcmsr_free_ccb_pool(acb);
222f1189 1173 goto unmap_pci_region;
ae52e7f0 1174free_hbb_mu:
609d0858 1175 arcmsr_free_io_queue(acb);
ae52e7f0
NC		 1176unmap_pci_region:
1177 arcmsr_unmap_pciregion(acb);
1178pci_release_regs:
1c57e86d 1179 pci_release_regions(pdev);
ae52e7f0 1180scsi_host_release:
1c57e86d 1181 scsi_host_put(host);
ae52e7f0 1182pci_disable_dev:
1c57e86d 1183 pci_disable_device(pdev);
ae52e7f0 1184 return -ENODEV;
1a4f550a
NC		 1185}
1186
1d1166ea
CH		 1187static void arcmsr_free_irq(struct pci_dev *pdev,
1188 struct AdapterControlBlock *acb)
1189{
1190 int i;
1191
68130c99
CH		 1192 for (i = 0; i < acb->vector_count; i++)
1193 free_irq(pci_irq_vector(pdev, i), acb);
1194 pci_free_irq_vectors(pdev);
1d1166ea
CH		 1195}
1196
756ebbe7 1197static int __maybe_unused arcmsr_suspend(struct device *dev)
61cda87f 1198{
756ebbe7 1199 struct pci_dev *pdev = to_pci_dev(dev);
61cda87f
CH		 1200 struct Scsi_Host *host = pci_get_drvdata(pdev);
1201 struct AdapterControlBlock *acb =
1202 (struct AdapterControlBlock *)host->hostdata;
1203
18bc435e 1204 arcmsr_disable_outbound_ints(acb);
61cda87f
CH		 1205 arcmsr_free_irq(pdev, acb);
1206 del_timer_sync(&acb->eternal_timer);
b416c099
CH		 1207 if (set_date_time)
1208 del_timer_sync(&acb->refresh_timer);
61cda87f
CH		 1209 flush_work(&acb->arcmsr_do_message_isr_bh);
1210 arcmsr_stop_adapter_bgrb(acb);
1211 arcmsr_flush_adapter_cache(acb);
61cda87f
CH		 1212 return 0;
1213}
1214
756ebbe7 1215static int __maybe_unused arcmsr_resume(struct device *dev)
61cda87f 1216{
756ebbe7 1217 struct pci_dev *pdev = to_pci_dev(dev);
61cda87f
CH		 1218 struct Scsi_Host *host = pci_get_drvdata(pdev);
1219 struct AdapterControlBlock *acb =
1220 (struct AdapterControlBlock *)host->hostdata;
1221
1d120c61
CH		 1222 if (arcmsr_set_dma_mask(acb))
1223 goto controller_unregister;
61cda87f
CH		 1224 if (arcmsr_request_irq(pdev, acb) == FAILED)
1225 goto controller_stop;
afdda878
CH		 1226 switch (acb->adapter_type) {
1227 case ACB_ADAPTER_TYPE_B: {
1228 struct MessageUnit_B *reg = acb->pmuB;
317d0e02
CH		 1229 uint32_t i;
1230 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
1231 reg->post_qbuffer[i] = 0;
1232 reg->done_qbuffer[i] = 0;
1233 }
afdda878
CH		 1234 reg->postq_index = 0;
1235 reg->doneq_index = 0;
1236 break;
1237 }
1238 case ACB_ADAPTER_TYPE_E:
97fe2225
CH		 1239 writel(0, &acb->pmuE->host_int_status);
1240 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell);
1241 acb->in_doorbell = 0;
1242 acb->out_doorbell = 0;
1243 acb->doneq_index = 0;
afdda878 1244 break;
ae897ae2
H		 1245 case ACB_ADAPTER_TYPE_F:
1246 writel(0, &acb->pmuF->host_int_status);
1247 writel(ARCMSR_HBFMU_DOORBELL_SYNC, &acb->pmuF->iobound_doorbell);
1248 acb->in_doorbell = 0;
1249 acb->out_doorbell = 0;
1250 acb->doneq_index = 0;
1251 arcmsr_hbaF_assign_regAddr(acb);
1252 break;
97fe2225 1253 }
61cda87f 1254 arcmsr_iop_init(acb);
ea331f30 1255 arcmsr_init_get_devmap_timer(acb);
b416c099
CH		 1256 if (set_date_time)
1257 arcmsr_init_set_datetime_timer(acb);
61cda87f
CH		 1258 return 0;
1259controller_stop:
1260 arcmsr_stop_adapter_bgrb(acb);
1261 arcmsr_flush_adapter_cache(acb);
1262controller_unregister:
1263 scsi_remove_host(host);
1264 arcmsr_free_ccb_pool(acb);
ae897ae2
H		 1265 if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
1266 arcmsr_free_io_queue(acb);
61cda87f 1267 arcmsr_unmap_pciregion(acb);
61cda87f 1268 scsi_host_put(host);
61cda87f
CH		 1269 return -ENODEV;
1270}
1271
626fa32c 1272static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
1c57e86d 1273{
80da1adb 1274 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 1275 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
626fa32c 1276 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a 1277 printk(KERN_NOTICE
626fa32c 1278 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1a4f550a 1279 , acb->host->host_no);
cdd3cb15 1280 return false;
36b83ded 1281 }
cdd3cb15 1282 return true;
1a4f550a
NC		 1283}
1284
626fa32c 1285static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
1a4f550a 1286{
80da1adb 1287 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1288
ae52e7f0 1289 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
626fa32c 1290 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1c57e86d 1291 printk(KERN_NOTICE
626fa32c 1292 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1c57e86d 1293 , acb->host->host_no);
cdd3cb15 1294 return false;
36b83ded 1295 }
cdd3cb15
NC		 1296 return true;
1297}
626fa32c 1298static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
cdd3cb15 1299{
c10b1d54 1300 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 1301 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
1302 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
626fa32c 1303 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15 1304 printk(KERN_NOTICE
626fa32c 1305 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
cdd3cb15
NC		 1306 , pACB->host->host_no);
1307 return false;
1308 }
1309 return true;
1c57e86d 1310}
5b37479a
CH		 1311
1312static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
1313{
1314 struct MessageUnit_D *reg = pACB->pmuD;
1315
1316 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
1317 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
1318 pr_notice("arcmsr%d: wait 'abort all outstanding "
1319 "command' timeout\n", pACB->host->host_no);
1320 return false;
1321 }
1322 return true;
1323}
1324
23509024
CH		 1325static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB)
1326{
1327 struct MessageUnit_E __iomem *reg = pACB->pmuE;
1328
1329 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
1330 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1331 writel(pACB->out_doorbell, &reg->iobound_doorbell);
1332 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
1333 pr_notice("arcmsr%d: wait 'abort all outstanding "
1334 "command' timeout\n", pACB->host->host_no);
1335 return false;
1336 }
1337 return true;
1338}
1339
36b83ded 1340static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
1a4f550a 1341{
36b83ded 1342 uint8_t rtnval = 0;
1a4f550a 1343 switch (acb->adapter_type) {
9aae1c1f 1344 case ACB_ADAPTER_TYPE_A:
626fa32c 1345 rtnval = arcmsr_hbaA_abort_allcmd(acb);
1a4f550a 1346 break;
9aae1c1f 1347 case ACB_ADAPTER_TYPE_B:
626fa32c 1348 rtnval = arcmsr_hbaB_abort_allcmd(acb);
cdd3cb15 1349 break;
9aae1c1f 1350 case ACB_ADAPTER_TYPE_C:
626fa32c 1351 rtnval = arcmsr_hbaC_abort_allcmd(acb);
5b37479a 1352 break;
5b37479a
CH		 1353 case ACB_ADAPTER_TYPE_D:
1354 rtnval = arcmsr_hbaD_abort_allcmd(acb);
1355 break;
23509024 1356 case ACB_ADAPTER_TYPE_E:
ae897ae2 1357 case ACB_ADAPTER_TYPE_F:
23509024
CH		 1358 rtnval = arcmsr_hbaE_abort_allcmd(acb);
1359 break;
1a4f550a 1360 }
36b83ded 1361 return rtnval;
1a4f550a
NC		 1362}
1363
ae52e7f0 1364static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
1c57e86d
EC		 1365{
1366 struct AdapterControlBlock *acb = ccb->acb;
1367 struct scsi_cmnd *pcmd = ccb->pcmd;
ae52e7f0 1368 unsigned long flags;
ae52e7f0 1369 atomic_dec(&acb->ccboutstandingcount);
959c014f 1370 scsi_dma_unmap(ccb->pcmd);
1c57e86d 1371 ccb->startdone = ARCMSR_CCB_DONE;
ae52e7f0 1372 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d 1373 list_add_tail(&ccb->list, &acb->ccb_free_list);
ae52e7f0 1374 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
3f0b59b6 1375 scsi_done(pcmd);
1c57e86d
EC		 1376}
1377
1a4f550a
NC		 1378static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
1379{
1a4f550a 1380 struct scsi_cmnd *pcmd = ccb->pcmd;
86a6a0bd 1381
3d45cefc 1382 pcmd->result = (DID_OK << 16) | SAM_STAT_CHECK_CONDITION;
86a6a0bd
KC		 1383 if (pcmd->sense_buffer) {
1384 struct SENSE_DATA *sensebuffer;
1385
1386 memcpy_and_pad(pcmd->sense_buffer,
1387 SCSI_SENSE_BUFFERSIZE,
1388 ccb->arcmsr_cdb.SenseData,
1389 sizeof(ccb->arcmsr_cdb.SenseData),
1390 0);
1391
1392 sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
1a4f550a
NC		 1393 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
1394 sensebuffer->Valid = 1;
1395 }
1396}
1397
1398static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
1399{
1400 u32 orig_mask = 0;
cdd3cb15 1401 switch (acb->adapter_type) {
1a4f550a 1402 case ACB_ADAPTER_TYPE_A : {
80da1adb 1403 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 1404 orig_mask = readl(&reg->outbound_intmask);
1a4f550a
NC		 1405 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
1406 &reg->outbound_intmask);
1407 }
1408 break;
1a4f550a 1409 case ACB_ADAPTER_TYPE_B : {
80da1adb 1410 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 1411 orig_mask = readl(reg->iop2drv_doorbell_mask);
1412 writel(0, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 1413 }
1414 break;
cdd3cb15 1415 case ACB_ADAPTER_TYPE_C:{
c10b1d54 1416 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 1417 /* disable all outbound interrupt */
1418 orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
1419 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
1420 }
1421 break;
5b37479a
CH		 1422 case ACB_ADAPTER_TYPE_D: {
1423 struct MessageUnit_D *reg = acb->pmuD;
1424 /* disable all outbound interrupt */
1425 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
1426 }
1427 break;
ae897ae2
H		 1428 case ACB_ADAPTER_TYPE_E:
1429 case ACB_ADAPTER_TYPE_F: {
23509024
CH		 1430 struct MessageUnit_E __iomem *reg = acb->pmuE;
1431 orig_mask = readl(&reg->host_int_mask);
1432 writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, &reg->host_int_mask);
1433 readl(&reg->host_int_mask); /* Dummy readl to force pci flush */
1434 }
1435 break;
1a4f550a
NC		 1436 }
1437 return orig_mask;
1438}
1439
cdd3cb15
NC		 1440static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
1441 struct CommandControlBlock *ccb, bool error)
1a4f550a 1442{
1a4f550a
NC		 1443 uint8_t id, lun;
1444 id = ccb->pcmd->device->id;
1445 lun = ccb->pcmd->device->lun;
cdd3cb15 1446 if (!error) {
1a4f550a
NC		 1447 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
1448 acb->devstate[id][lun] = ARECA_RAID_GOOD;
7968f194
JL		 1449 ccb->pcmd->result = DID_OK << 16;
1450 arcmsr_ccb_complete(ccb);
cdd3cb15 1451 }else{
1a4f550a
NC		 1452 switch (ccb->arcmsr_cdb.DeviceStatus) {
1453 case ARCMSR_DEV_SELECT_TIMEOUT: {
1454 acb->devstate[id][lun] = ARECA_RAID_GONE;
1455 ccb->pcmd->result = DID_NO_CONNECT << 16;
ae52e7f0 1456 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1457 }
1458 break;
1459
1460 case ARCMSR_DEV_ABORTED:
1461
1462 case ARCMSR_DEV_INIT_FAIL: {
1463 acb->devstate[id][lun] = ARECA_RAID_GONE;
1464 ccb->pcmd->result = DID_BAD_TARGET << 16;
ae52e7f0 1465 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1466 }
1467 break;
1468
1469 case ARCMSR_DEV_CHECK_CONDITION: {
1470 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1471 arcmsr_report_sense_info(ccb);
ae52e7f0 1472 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1473 }
1474 break;
1475
1476 default:
cdd3cb15
NC		 1477 printk(KERN_NOTICE
1478 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
1479 but got unknown DeviceStatus = 0x%x \n"
1480 , acb->host->host_no
1481 , id
1482 , lun
1483 , ccb->arcmsr_cdb.DeviceStatus);
1484 acb->devstate[id][lun] = ARECA_RAID_GONE;
1485 ccb->pcmd->result = DID_NO_CONNECT << 16;
1486 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1487 break;
1488 }
1489 }
1490}
1491
cdd3cb15 1492static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1a4f550a 1493{
cdd3cb15
NC		 1494 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
1495 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
1496 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1a4f550a
NC		 1497 if (abortcmd) {
1498 abortcmd->result |= DID_ABORT << 16;
cdd3cb15
NC		 1499 arcmsr_ccb_complete(pCCB);
1500 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
1501 acb->host->host_no, pCCB);
1a4f550a 1502 }
cdd3cb15 1503 return;
1a4f550a
NC		 1504 }
1505 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
1506 done acb = '0x%p'"
1507 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
1508 " ccboutstandingcount = %d \n"
1509 , acb->host->host_no
1510 , acb
cdd3cb15
NC		 1511 , pCCB
1512 , pCCB->acb
1513 , pCCB->startdone
1a4f550a 1514 , atomic_read(&acb->ccboutstandingcount));
9b44ffab 1515 return;
97b99127 1516 }
cdd3cb15 1517 arcmsr_report_ccb_state(acb, pCCB, error);
1a4f550a
NC		 1518}
1519
1520static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
1521{
1522 int i = 0;
9e386a55 1523 uint32_t flag_ccb;
cdd3cb15
NC		 1524 struct ARCMSR_CDB *pARCMSR_CDB;
1525 bool error;
1526 struct CommandControlBlock *pCCB;
18bc435e 1527 unsigned long ccb_cdb_phy;
9e386a55 1528
1a4f550a
NC		 1529 switch (acb->adapter_type) {
1530
1531 case ACB_ADAPTER_TYPE_A: {
80da1adb 1532 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1533 uint32_t outbound_intstatus;
80da1adb 1534 outbound_intstatus = readl(&reg->outbound_intstatus) &
1a4f550a
NC		 1535 acb->outbound_int_enable;
1536 /*clear and abort all outbound posted Q*/
1537 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
cdd3cb15 1538 while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
e4587f45 1539 && (i++ < acb->maxOutstanding)) {
9e386a55
CH		 1540 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
1541 if (acb->cdb_phyadd_hipart)
1542 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
1543 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
cdd3cb15
NC		 1544 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1545 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1546 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1547 }
1548 }
1549 break;
1550
1551 case ACB_ADAPTER_TYPE_B: {
80da1adb 1552 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1553 /*clear all outbound posted Q*/
97b99127 1554 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
1a4f550a 1555 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
c10b1d54
CH		 1556 flag_ccb = reg->done_qbuffer[i];
1557 if (flag_ccb != 0) {
1558 reg->done_qbuffer[i] = 0;
e66764f2
CH		 1559 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
1560 if (acb->cdb_phyadd_hipart)
1561 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
1562 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
cdd3cb15
NC		 1563 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1564 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1565 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a 1566 }
cdd3cb15 1567 reg->post_qbuffer[i] = 0;
1a4f550a
NC		 1568 }
1569 reg->doneq_index = 0;
1570 reg->postq_index = 0;
1571 }
1572 break;
cdd3cb15 1573 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1574 struct MessageUnit_C __iomem *reg = acb->pmuC;
e4587f45 1575 while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) {
cdd3cb15
NC		 1576 /*need to do*/
1577 flag_ccb = readl(&reg->outbound_queueport_low);
1578 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
c71ec551
CH		 1579 if (acb->cdb_phyadd_hipart)
1580 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
1581 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
cdd3cb15
NC		 1582 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1583 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1584 arcmsr_drain_donequeue(acb, pCCB, error);
1585 }
5b37479a
CH		 1586 }
1587 break;
1588 case ACB_ADAPTER_TYPE_D: {
1589 struct MessageUnit_D *pmu = acb->pmuD;
3b8155d5
CH		 1590 uint32_t outbound_write_pointer;
1591 uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
1592 unsigned long flags;
5b37479a 1593
5b37479a
CH		 1594 residual = atomic_read(&acb->ccboutstandingcount);
1595 for (i = 0; i < residual; i++) {
3b8155d5
CH		 1596 spin_lock_irqsave(&acb->doneq_lock, flags);
1597 outbound_write_pointer =
1598 pmu->done_qbuffer[0].addressLow + 1;
1599 doneq_index = pmu->doneq_index;
1600 if ((doneq_index & 0xFFF) !=
5b37479a 1601 (outbound_write_pointer & 0xFFF)) {
3b8155d5
CH		 1602 toggle = doneq_index & 0x4000;
1603 index_stripped = (doneq_index & 0xFFF) + 1;
1604 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
1605 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
1606 ((toggle ^ 0x4000) + 1);
5b37479a 1607 doneq_index = pmu->doneq_index;
3b8155d5 1608 spin_unlock_irqrestore(&acb->doneq_lock, flags);
5b37479a
CH		 1609 addressLow = pmu->done_qbuffer[doneq_index &
1610 0xFFF].addressLow;
1611 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
a36ade41
CH		 1612 if (acb->cdb_phyadd_hipart)
1613 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
5b37479a
CH		 1614 pARCMSR_CDB = (struct ARCMSR_CDB *)
1615 (acb->vir2phy_offset + ccb_cdb_phy);
1616 pCCB = container_of(pARCMSR_CDB,
1617 struct CommandControlBlock, arcmsr_cdb);
1618 error = (addressLow &
1619 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
1620 true : false;
1621 arcmsr_drain_donequeue(acb, pCCB, error);
1622 writel(doneq_index,
1623 pmu->outboundlist_read_pointer);
3b8155d5
CH		 1624 } else {
1625 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1626 mdelay(10);
5b37479a 1627 }
5b37479a
CH		 1628 }
1629 pmu->postq_index = 0;
1630 pmu->doneq_index = 0x40FF;
1631 }
1632 break;
23509024
CH		 1633 case ACB_ADAPTER_TYPE_E:
1634 arcmsr_hbaE_postqueue_isr(acb);
1635 break;
ae897ae2
H		 1636 case ACB_ADAPTER_TYPE_F:
1637 arcmsr_hbaF_postqueue_isr(acb);
1638 break;
1a4f550a
NC		 1639 }
1640}
1d1166ea 1641
c4c1adb3
CH		 1642static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb)
1643{
1644 char *acb_dev_map = (char *)acb->device_map;
1645 int target, lun, i;
1646 struct scsi_device *psdev;
1647 struct CommandControlBlock *ccb;
1648 char temp;
1649
1650 for (i = 0; i < acb->maxFreeCCB; i++) {
1651 ccb = acb->pccb_pool[i];
1652 if (ccb->startdone == ARCMSR_CCB_START) {
1653 ccb->pcmd->result = DID_NO_CONNECT << 16;
959c014f 1654 scsi_dma_unmap(ccb->pcmd);
3f0b59b6 1655 scsi_done(ccb->pcmd);
c4c1adb3
CH		 1656 }
1657 }
1658 for (target = 0; target < ARCMSR_MAX_TARGETID; target++) {
1659 temp = *acb_dev_map;
1660 if (temp) {
1661 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
1662 if (temp & 1) {
1663 psdev = scsi_device_lookup(acb->host,
1664 0, target, lun);
1665 if (psdev != NULL) {
1666 scsi_remove_device(psdev);
1667 scsi_device_put(psdev);
1668 }
1669 }
1670 temp >>= 1;
1671 }
1672 *acb_dev_map = 0;
1673 }
1674 acb_dev_map++;
1675 }
1676}
1677
1678static void arcmsr_free_pcidev(struct AdapterControlBlock *acb)
1679{
1680 struct pci_dev *pdev;
1681 struct Scsi_Host *host;
1682
1683 host = acb->host;
1684 arcmsr_free_sysfs_attr(acb);
1685 scsi_remove_host(host);
1686 flush_work(&acb->arcmsr_do_message_isr_bh);
1687 del_timer_sync(&acb->eternal_timer);
1688 if (set_date_time)
1689 del_timer_sync(&acb->refresh_timer);
1690 pdev = acb->pdev;
1691 arcmsr_free_irq(pdev, acb);
1692 arcmsr_free_ccb_pool(acb);
ae897ae2
H		 1693 if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
1694 arcmsr_free_io_queue(acb);
c4c1adb3
CH		 1695 arcmsr_unmap_pciregion(acb);
1696 pci_release_regions(pdev);
1697 scsi_host_put(host);
1698 pci_disable_device(pdev);
1699}
1700
1c57e86d
EC		 1701static void arcmsr_remove(struct pci_dev *pdev)
1702{
1703 struct Scsi_Host *host = pci_get_drvdata(pdev);
1704 struct AdapterControlBlock *acb =
1705 (struct AdapterControlBlock *) host->hostdata;
1c57e86d 1706 int poll_count = 0;
c4c1adb3
CH		 1707 uint16_t dev_id;
1708
1709 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
1710 if (dev_id == 0xffff) {
1711 acb->acb_flags &= ~ACB_F_IOP_INITED;
1712 acb->acb_flags |= ACB_F_ADAPTER_REMOVED;
1713 arcmsr_remove_scsi_devices(acb);
1714 arcmsr_free_pcidev(acb);
1715 return;
1716 }
1c57e86d
EC		 1717 arcmsr_free_sysfs_attr(acb);
1718 scsi_remove_host(host);
43829731 1719 flush_work(&acb->arcmsr_do_message_isr_bh);
36b83ded 1720 del_timer_sync(&acb->eternal_timer);
b416c099
CH		 1721 if (set_date_time)
1722 del_timer_sync(&acb->refresh_timer);
36b83ded 1723 arcmsr_disable_outbound_ints(acb);
1c57e86d 1724 arcmsr_stop_adapter_bgrb(acb);
cdd3cb15 1725 arcmsr_flush_adapter_cache(acb);
1c57e86d
EC		 1726 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1727 acb->acb_flags &= ~ACB_F_IOP_INITED;
1728
e4587f45 1729 for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){
1c57e86d
EC		 1730 if (!atomic_read(&acb->ccboutstandingcount))
1731 break;
1a4f550a 1732 arcmsr_interrupt(acb);/* FIXME: need spinlock */
1c57e86d
EC		 1733 msleep(25);
1734 }
1735
1736 if (atomic_read(&acb->ccboutstandingcount)) {
1737 int i;
1738
1739 arcmsr_abort_allcmd(acb);
1a4f550a 1740 arcmsr_done4abort_postqueue(acb);
d076e4aa 1741 for (i = 0; i < acb->maxFreeCCB; i++) {
1c57e86d
EC		 1742 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1743 if (ccb->startdone == ARCMSR_CCB_START) {
1744 ccb->startdone = ARCMSR_CCB_ABORTED;
1745 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 1746 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 1747 }
1748 }
1749 }
1d1166ea 1750 arcmsr_free_irq(pdev, acb);
1c57e86d 1751 arcmsr_free_ccb_pool(acb);
ae897ae2
H		 1752 if (acb->adapter_type == ACB_ADAPTER_TYPE_F)
1753 arcmsr_free_io_queue(acb);
cdd3cb15 1754 arcmsr_unmap_pciregion(acb);
1c57e86d 1755 pci_release_regions(pdev);
cdd3cb15 1756 scsi_host_put(host);
1c57e86d 1757 pci_disable_device(pdev);
1c57e86d
EC		 1758}
1759
1760static void arcmsr_shutdown(struct pci_dev *pdev)
1761{
1762 struct Scsi_Host *host = pci_get_drvdata(pdev);
1763 struct AdapterControlBlock *acb =
1764 (struct AdapterControlBlock *)host->hostdata;
c4c1adb3
CH		 1765 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
1766 return;
36b83ded 1767 del_timer_sync(&acb->eternal_timer);
b416c099
CH		 1768 if (set_date_time)
1769 del_timer_sync(&acb->refresh_timer);
36b83ded 1770 arcmsr_disable_outbound_ints(acb);
1d1166ea 1771 arcmsr_free_irq(pdev, acb);
43829731 1772 flush_work(&acb->arcmsr_do_message_isr_bh);
1c57e86d
EC		 1773 arcmsr_stop_adapter_bgrb(acb);
1774 arcmsr_flush_adapter_cache(acb);
1775}
1776
e9b525b6 1777static int __init arcmsr_module_init(void)
1c57e86d
EC		 1778{
1779 int error = 0;
1c57e86d
EC		 1780 error = pci_register_driver(&arcmsr_pci_driver);
1781 return error;
1782}
1783
e9b525b6 1784static void __exit arcmsr_module_exit(void)
1c57e86d
EC		 1785{
1786 pci_unregister_driver(&arcmsr_pci_driver);
1787}
1788module_init(arcmsr_module_init);
1789module_exit(arcmsr_module_exit);
1790
36b83ded 1791static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1a4f550a 1792 u32 intmask_org)
1c57e86d 1793{
1c57e86d 1794 u32 mask;
1a4f550a 1795 switch (acb->adapter_type) {
1c57e86d 1796
cdd3cb15 1797 case ACB_ADAPTER_TYPE_A: {
80da1adb 1798 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1799 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
36b83ded
NC		 1800 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1801 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1a4f550a
NC		 1802 writel(mask, &reg->outbound_intmask);
1803 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1804 }
1805 break;
1c57e86d 1806
cdd3cb15 1807 case ACB_ADAPTER_TYPE_B: {
80da1adb 1808 struct MessageUnit_B *reg = acb->pmuB;
36b83ded
NC		 1809 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1810 ARCMSR_IOP2DRV_DATA_READ_OK |
1811 ARCMSR_IOP2DRV_CDB_DONE |
1812 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
ae52e7f0 1813 writel(mask, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 1814 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1815 }
cdd3cb15
NC		 1816 break;
1817 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1818 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 1819 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1820 writel(intmask_org & mask, &reg->host_int_mask);
1821 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1822 }
5b37479a
CH		 1823 break;
1824 case ACB_ADAPTER_TYPE_D: {
1825 struct MessageUnit_D *reg = acb->pmuD;
1826
1827 mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
1828 writel(intmask_org | mask, reg->pcief0_int_enable);
1829 break;
1830 }
ae897ae2
H		 1831 case ACB_ADAPTER_TYPE_E:
1832 case ACB_ADAPTER_TYPE_F: {
23509024
CH		 1833 struct MessageUnit_E __iomem *reg = acb->pmuE;
1834
1835 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
1836 writel(intmask_org & mask, &reg->host_int_mask);
1837 break;
1838 }
1c57e86d
EC		 1839 }
1840}
1841
76d78300 1842static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1a4f550a 1843 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1c57e86d 1844{
1a4f550a
NC		 1845 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1846 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
80da1adb 1847 __le32 address_lo, address_hi;
1a4f550a 1848 int arccdbsize = 0x30;
ae52e7f0 1849 __le32 length = 0;
cdd3cb15 1850 int i;
ae52e7f0 1851 struct scatterlist *sg;
1a4f550a 1852 int nseg;
1c57e86d 1853 ccb->pcmd = pcmd;
1a4f550a 1854 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1c57e86d
EC		 1855 arcmsr_cdb->TargetID = pcmd->device->id;
1856 arcmsr_cdb->LUN = pcmd->device->lun;
1857 arcmsr_cdb->Function = 1;
626fa32c 1858 arcmsr_cdb->msgContext = 0;
1c57e86d 1859 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
deff2627
FT		 1860
1861 nseg = scsi_dma_map(pcmd);
cdd3cb15 1862 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
76d78300 1863 return FAILED;
cdd3cb15
NC		 1864 scsi_for_each_sg(pcmd, sg, nseg, i) {
1865 /* Get the physical address of the current data pointer */
1866 length = cpu_to_le32(sg_dma_len(sg));
1867 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1868 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1869 if (address_hi == 0) {
1870 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1871
1872 pdma_sg->address = address_lo;
1873 pdma_sg->length = length;
1874 psge += sizeof (struct SG32ENTRY);
1875 arccdbsize += sizeof (struct SG32ENTRY);
1876 } else {
1877 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1c57e86d 1878
cdd3cb15
NC		 1879 pdma_sg->addresshigh = address_hi;
1880 pdma_sg->address = address_lo;
1881 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1882 psge += sizeof (struct SG64ENTRY);
1883 arccdbsize += sizeof (struct SG64ENTRY);
1c57e86d 1884 }
cdd3cb15
NC		 1885 }
1886 arcmsr_cdb->sgcount = (uint8_t)nseg;
1887 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
ae52e7f0 1888 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
cdd3cb15
NC		 1889 if ( arccdbsize > 256)
1890 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
c32e061f 1891 if (pcmd->sc_data_direction == DMA_TO_DEVICE)
1c57e86d 1892 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
cdd3cb15 1893 ccb->arc_cdb_size = arccdbsize;
76d78300 1894 return SUCCESS;
1c57e86d
EC		 1895}
1896
1897static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1898{
626fa32c 1899 uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
1c57e86d 1900 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1c57e86d
EC		 1901 atomic_inc(&acb->ccboutstandingcount);
1902 ccb->startdone = ARCMSR_CCB_START;
1a4f550a
NC		 1903 switch (acb->adapter_type) {
1904 case ACB_ADAPTER_TYPE_A: {
80da1adb 1905 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1906
1907 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
626fa32c 1908 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1c57e86d 1909 &reg->inbound_queueport);
626fa32c
CH		 1910 else
1911 writel(cdb_phyaddr, &reg->inbound_queueport);
1a4f550a 1912 break;
626fa32c 1913 }
1c57e86d 1914
1a4f550a 1915 case ACB_ADAPTER_TYPE_B: {
80da1adb 1916 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1917 uint32_t ending_index, index = reg->postq_index;
1c57e86d 1918
1a4f550a 1919 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
c10b1d54 1920 reg->post_qbuffer[ending_index] = 0;
1a4f550a 1921 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
c10b1d54
CH		 1922 reg->post_qbuffer[index] =
1923 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
cdd3cb15 1924 } else {
c10b1d54 1925 reg->post_qbuffer[index] = cdb_phyaddr;
1a4f550a
NC		 1926 }
1927 index++;
1928 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
1929 reg->postq_index = index;
ae52e7f0 1930 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1c57e86d 1931 }
1a4f550a 1932 break;
cdd3cb15 1933 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1934 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
cdd3cb15
NC		 1935 uint32_t ccb_post_stamp, arc_cdb_size;
1936
1937 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
626fa32c 1938 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
c71ec551
CH		 1939 writel(upper_32_bits(ccb->cdb_phyaddr), &phbcmu->inbound_queueport_high);
1940 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
cdd3cb15 1941 }
5b37479a
CH		 1942 break;
1943 case ACB_ADAPTER_TYPE_D: {
1944 struct MessageUnit_D *pmu = acb->pmuD;
1945 u16 index_stripped;
3b8155d5 1946 u16 postq_index, toggle;
5b37479a
CH		 1947 unsigned long flags;
1948 struct InBound_SRB *pinbound_srb;
1949
1950 spin_lock_irqsave(&acb->postq_lock, flags);
1951 postq_index = pmu->postq_index;
1952 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
a36ade41
CH		 1953 pinbound_srb->addressHigh = upper_32_bits(ccb->cdb_phyaddr);
1954 pinbound_srb->addressLow = cdb_phyaddr;
5b37479a
CH		 1955 pinbound_srb->length = ccb->arc_cdb_size >> 2;
1956 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
3b8155d5
CH		 1957 toggle = postq_index & 0x4000;
1958 index_stripped = postq_index + 1;
1959 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
1960 pmu->postq_index = index_stripped ? (index_stripped | toggle) :
1961 (toggle ^ 0x4000);
5b37479a
CH		 1962 writel(postq_index, pmu->inboundlist_write_pointer);
1963 spin_unlock_irqrestore(&acb->postq_lock, flags);
1964 break;
1965 }
23509024
CH		 1966 case ACB_ADAPTER_TYPE_E: {
1967 struct MessageUnit_E __iomem *pmu = acb->pmuE;
1968 u32 ccb_post_stamp, arc_cdb_size;
1969
1970 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1971 ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6));
1972 writel(0, &pmu->inbound_queueport_high);
1973 writel(ccb_post_stamp, &pmu->inbound_queueport_low);
1974 break;
1975 }
ae897ae2
H		 1976 case ACB_ADAPTER_TYPE_F: {
1977 struct MessageUnit_F __iomem *pmu = acb->pmuF;
1978 u32 ccb_post_stamp, arc_cdb_size;
1979
1980 if (ccb->arc_cdb_size <= 0x300)
1981 arc_cdb_size = (ccb->arc_cdb_size - 1) >> 6 | 1;
5b864496
H		 1982 else {
1983 arc_cdb_size = ((ccb->arc_cdb_size + 0xff) >> 8) + 2;
1984 if (arc_cdb_size > 0xF)
1985 arc_cdb_size = 0xF;
1986 arc_cdb_size = (arc_cdb_size << 1) | 1;
1987 }
ae897ae2
H		 1988 ccb_post_stamp = (ccb->smid | arc_cdb_size);
1989 writel(0, &pmu->inbound_queueport_high);
1990 writel(ccb_post_stamp, &pmu->inbound_queueport_low);
1991 break;
1992 }
1c57e86d
EC		 1993 }
1994}
1995
626fa32c 1996static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
1c57e86d 1997{
80da1adb 1998 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 1999 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
2000 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
626fa32c 2001 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a 2002 printk(KERN_NOTICE
948dff7a 2003 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
1a4f550a
NC		 2004 , acb->host->host_no);
2005 }
2006}
2007
626fa32c 2008static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
1a4f550a 2009{
80da1adb 2010 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2011 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
ae52e7f0 2012 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1a4f550a 2013
626fa32c 2014 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1c57e86d 2015 printk(KERN_NOTICE
948dff7a 2016 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
1c57e86d 2017 , acb->host->host_no);
1a4f550a
NC		 2018 }
2019}
2020
626fa32c 2021static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
cdd3cb15 2022{
c10b1d54 2023 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 2024 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
2025 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
2026 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
626fa32c 2027 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15 2028 printk(KERN_NOTICE
948dff7a 2029 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
cdd3cb15
NC		 2030 , pACB->host->host_no);
2031 }
2032 return;
2033}
5b37479a
CH		 2034
2035static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
2036{
2037 struct MessageUnit_D *reg = pACB->pmuD;
2038
2039 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
2040 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
2041 if (!arcmsr_hbaD_wait_msgint_ready(pACB))
948dff7a 2042 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' "
5b37479a
CH		 2043 "timeout\n", pACB->host->host_no);
2044}
2045
23509024
CH		 2046static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB)
2047{
2048 struct MessageUnit_E __iomem *reg = pACB->pmuE;
2049
2050 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
2051 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
2052 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2053 writel(pACB->out_doorbell, &reg->iobound_doorbell);
2054 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
948dff7a 2055 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' "
23509024
CH		 2056 "timeout\n", pACB->host->host_no);
2057 }
2058}
2059
1a4f550a
NC		 2060static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
2061{
2062 switch (acb->adapter_type) {
9aae1c1f 2063 case ACB_ADAPTER_TYPE_A:
626fa32c 2064 arcmsr_hbaA_stop_bgrb(acb);
1a4f550a 2065 break;
9aae1c1f 2066 case ACB_ADAPTER_TYPE_B:
626fa32c 2067 arcmsr_hbaB_stop_bgrb(acb);
1a4f550a 2068 break;
9aae1c1f 2069 case ACB_ADAPTER_TYPE_C:
626fa32c 2070 arcmsr_hbaC_stop_bgrb(acb);
5b37479a
CH		 2071 break;
2072 case ACB_ADAPTER_TYPE_D:
2073 arcmsr_hbaD_stop_bgrb(acb);
2074 break;
23509024 2075 case ACB_ADAPTER_TYPE_E:
ae897ae2 2076 case ACB_ADAPTER_TYPE_F:
23509024
CH		 2077 arcmsr_hbaE_stop_bgrb(acb);
2078 break;
1a4f550a 2079 }
1c57e86d
EC		 2080}
2081
2082static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
2083{
14ef4b00
H		 2084 if (acb->xor_mega) {
2085 struct Xor_sg *pXorPhys;
2086 void **pXorVirt;
2087 int i;
2088
2089 pXorPhys = (struct Xor_sg *)(acb->xorVirt +
2090 sizeof(struct HostRamBuf));
2091 pXorVirt = (void **)((unsigned long)acb->xorVirt +
2092 (unsigned long)acb->xorVirtOffset);
2093 for (i = 0; i < acb->xor_mega; i++) {
2094 if (pXorPhys->xorPhys) {
2095 dma_free_coherent(&acb->pdev->dev,
2096 ARCMSR_XOR_SEG_SIZE,
2097 *pXorVirt, pXorPhys->xorPhys);
2098 pXorPhys->xorPhys = 0;
2099 *pXorVirt = NULL;
2100 }
2101 pXorPhys++;
2102 pXorVirt++;
2103 }
2104 dma_free_coherent(&acb->pdev->dev, acb->init2cfg_size,
2105 acb->xorVirt, acb->xorPhys);
2106 }
cdd3cb15 2107 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
1c57e86d
EC		 2108}
2109
c10b1d54 2110static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1c57e86d 2111{
1a4f550a
NC		 2112 switch (acb->adapter_type) {
2113 case ACB_ADAPTER_TYPE_A: {
80da1adb 2114 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2115 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
2116 }
2117 break;
1a4f550a 2118 case ACB_ADAPTER_TYPE_B: {
80da1adb 2119 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2120 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1c57e86d 2121 }
1a4f550a 2122 break;
cdd3cb15
NC		 2123 case ACB_ADAPTER_TYPE_C: {
2124 struct MessageUnit_C __iomem *reg = acb->pmuC;
5b37479a 2125
cdd3cb15
NC		 2126 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
2127 }
5b37479a
CH		 2128 break;
2129 case ACB_ADAPTER_TYPE_D: {
2130 struct MessageUnit_D *reg = acb->pmuD;
2131 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
2132 reg->inbound_doorbell);
2133 }
2134 break;
ae897ae2
H		 2135 case ACB_ADAPTER_TYPE_E:
2136 case ACB_ADAPTER_TYPE_F: {
23509024
CH		 2137 struct MessageUnit_E __iomem *reg = acb->pmuE;
2138 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
2139 writel(acb->out_doorbell, &reg->iobound_doorbell);
2140 }
2141 break;
1c57e86d 2142 }
1a4f550a
NC		 2143}
2144
2145static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
2146{
2147 switch (acb->adapter_type) {
2148 case ACB_ADAPTER_TYPE_A: {
80da1adb 2149 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 2150 /*
1a4f550a
NC		 2151 ** push inbound doorbell tell iop, driver data write ok
2152 ** and wait reply on next hwinterrupt for next Qbuffer post
1c57e86d 2153 */
1a4f550a
NC		 2154 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
2155 }
2156 break;
2157
2158 case ACB_ADAPTER_TYPE_B: {
80da1adb 2159 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 2160 /*
2161 ** push inbound doorbell tell iop, driver data write ok
2162 ** and wait reply on next hwinterrupt for next Qbuffer post
2163 */
ae52e7f0 2164 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 2165 }
2166 break;
cdd3cb15
NC		 2167 case ACB_ADAPTER_TYPE_C: {
2168 struct MessageUnit_C __iomem *reg = acb->pmuC;
2169 /*
2170 ** push inbound doorbell tell iop, driver data write ok
2171 ** and wait reply on next hwinterrupt for next Qbuffer post
2172 */
2173 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
2174 }
2175 break;
5b37479a
CH		 2176 case ACB_ADAPTER_TYPE_D: {
2177 struct MessageUnit_D *reg = acb->pmuD;
2178 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
2179 reg->inbound_doorbell);
2180 }
2181 break;
ae897ae2
H		 2182 case ACB_ADAPTER_TYPE_E:
2183 case ACB_ADAPTER_TYPE_F: {
23509024
CH		 2184 struct MessageUnit_E __iomem *reg = acb->pmuE;
2185 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
2186 writel(acb->out_doorbell, &reg->iobound_doorbell);
2187 }
2188 break;
1a4f550a
NC		 2189 }
2190}
2191
80da1adb 2192struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
1a4f550a 2193{
0c7eb2eb 2194 struct QBUFFER __iomem *qbuffer = NULL;
1a4f550a
NC		 2195 switch (acb->adapter_type) {
2196
2197 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 2198 struct MessageUnit_A __iomem *reg = acb->pmuA;
2199 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
1a4f550a
NC		 2200 }
2201 break;
1a4f550a 2202 case ACB_ADAPTER_TYPE_B: {
80da1adb 2203 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2204 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1a4f550a
NC		 2205 }
2206 break;
cdd3cb15 2207 case ACB_ADAPTER_TYPE_C: {
c10b1d54 2208 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
cdd3cb15
NC		 2209 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
2210 }
5b37479a
CH		 2211 break;
2212 case ACB_ADAPTER_TYPE_D: {
2213 struct MessageUnit_D *reg = acb->pmuD;
2214 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
2215 }
2216 break;
23509024
CH		 2217 case ACB_ADAPTER_TYPE_E: {
2218 struct MessageUnit_E __iomem *reg = acb->pmuE;
2219 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
2220 }
2221 break;
ae897ae2
H		 2222 case ACB_ADAPTER_TYPE_F: {
2223 qbuffer = (struct QBUFFER __iomem *)acb->message_rbuffer;
2224 }
2225 break;
1a4f550a
NC		 2226 }
2227 return qbuffer;
2228}
2229
80da1adb 2230static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
1a4f550a 2231{
0c7eb2eb 2232 struct QBUFFER __iomem *pqbuffer = NULL;
1a4f550a
NC		 2233 switch (acb->adapter_type) {
2234
2235 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 2236 struct MessageUnit_A __iomem *reg = acb->pmuA;
2237 pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
1a4f550a
NC		 2238 }
2239 break;
1a4f550a 2240 case ACB_ADAPTER_TYPE_B: {
80da1adb 2241 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2242 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1a4f550a
NC		 2243 }
2244 break;
cdd3cb15 2245 case ACB_ADAPTER_TYPE_C: {
c10b1d54 2246 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15 2247 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
5b37479a
CH		 2248 }
2249 break;
2250 case ACB_ADAPTER_TYPE_D: {
2251 struct MessageUnit_D *reg = acb->pmuD;
2252 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
2253 }
2254 break;
23509024
CH		 2255 case ACB_ADAPTER_TYPE_E: {
2256 struct MessageUnit_E __iomem *reg = acb->pmuE;
2257 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
2258 }
2259 break;
ae897ae2
H		 2260 case ACB_ADAPTER_TYPE_F:
2261 pqbuffer = (struct QBUFFER __iomem *)acb->message_wbuffer;
2262 break;
1a4f550a
NC		 2263 }
2264 return pqbuffer;
2265}
2266
bb263c4e
CH		 2267static uint32_t
2268arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
2269 struct QBUFFER __iomem *prbuffer)
1a4f550a 2270{
bb263c4e
CH		 2271 uint8_t *pQbuffer;
2272 uint8_t *buf1 = NULL;
2273 uint32_t __iomem *iop_data;
2274 uint32_t iop_len, data_len, *buf2 = NULL;
2275
2276 iop_data = (uint32_t __iomem *)prbuffer->data;
2277 iop_len = readl(&prbuffer->data_len);
2278 if (iop_len > 0) {
2279 buf1 = kmalloc(128, GFP_ATOMIC);
2280 buf2 = (uint32_t *)buf1;
2281 if (buf1 == NULL)
2282 return 0;
2283 data_len = iop_len;
2284 while (data_len >= 4) {
2285 *buf2++ = readl(iop_data);
1a4f550a 2286 iop_data++;
bb263c4e 2287 data_len -= 4;
1a4f550a 2288 }
bb263c4e
CH		 2289 if (data_len)
2290 *buf2 = readl(iop_data);
2291 buf2 = (uint32_t *)buf1;
2292 }
2293 while (iop_len > 0) {
2e9feb43 2294 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
bb263c4e 2295 *pQbuffer = *buf1;
2e9feb43 2296 acb->rqbuf_putIndex++;
bb263c4e 2297 /* if last, index number set it to 0 */
2e9feb43 2298 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
bb263c4e
CH		 2299 buf1++;
2300 iop_len--;
2301 }
2e9feb43 2302 kfree(buf2);
bb263c4e
CH		 2303 /* let IOP know data has been read */
2304 arcmsr_iop_message_read(acb);
2305 return 1;
2306}
2307
2308uint32_t
2309arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
2310 struct QBUFFER __iomem *prbuffer) {
2311
2312 uint8_t *pQbuffer;
2313 uint8_t __iomem *iop_data;
2314 uint32_t iop_len;
2315
52b4dab3 2316 if (acb->adapter_type > ACB_ADAPTER_TYPE_B)
bb263c4e
CH		 2317 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
2318 iop_data = (uint8_t __iomem *)prbuffer->data;
2319 iop_len = readl(&prbuffer->data_len);
2320 while (iop_len > 0) {
2e9feb43 2321 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
bb263c4e 2322 *pQbuffer = readb(iop_data);
2e9feb43
CH		 2323 acb->rqbuf_putIndex++;
2324 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
bb263c4e
CH		 2325 iop_data++;
2326 iop_len--;
1a4f550a 2327 }
bb263c4e
CH		 2328 arcmsr_iop_message_read(acb);
2329 return 1;
2330}
1a4f550a 2331
bb263c4e
CH		 2332static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
2333{
2334 unsigned long flags;
2335 struct QBUFFER __iomem *prbuffer;
2336 int32_t buf_empty_len;
2337
2338 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2339 prbuffer = arcmsr_get_iop_rqbuffer(acb);
3e408148
H		 2340 if (acb->rqbuf_putIndex >= acb->rqbuf_getIndex) {
2341 buf_empty_len = (ARCMSR_MAX_QBUFFER - 1) -
2342 (acb->rqbuf_putIndex - acb->rqbuf_getIndex);
2343 } else
2344 buf_empty_len = acb->rqbuf_getIndex - acb->rqbuf_putIndex - 1;
bb263c4e
CH		 2345 if (buf_empty_len >= readl(&prbuffer->data_len)) {
2346 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2347 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2348 } else
1a4f550a 2349 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
bb263c4e
CH		 2350 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2351}
2352
2353static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
2354{
2355 uint8_t *pQbuffer;
2356 struct QBUFFER __iomem *pwbuffer;
2357 uint8_t *buf1 = NULL;
2358 uint32_t __iomem *iop_data;
2359 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
2360
2361 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
2362 buf1 = kmalloc(128, GFP_ATOMIC);
2363 buf2 = (uint32_t *)buf1;
2364 if (buf1 == NULL)
2365 return;
2366
2367 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
2368 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
2369 iop_data = (uint32_t __iomem *)pwbuffer->data;
2e9feb43 2370 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
bb263c4e 2371 && (allxfer_len < 124)) {
2e9feb43 2372 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
bb263c4e 2373 *buf1 = *pQbuffer;
2e9feb43
CH		 2374 acb->wqbuf_getIndex++;
2375 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
bb263c4e
CH		 2376 buf1++;
2377 allxfer_len++;
2378 }
2379 data_len = allxfer_len;
2380 buf1 = (uint8_t *)buf2;
2381 while (data_len >= 4) {
2382 data = *buf2++;
2383 writel(data, iop_data);
2384 iop_data++;
2385 data_len -= 4;
2386 }
2387 if (data_len) {
2388 data = *buf2;
2389 writel(data, iop_data);
2390 }
2391 writel(allxfer_len, &pwbuffer->data_len);
2392 kfree(buf1);
2393 arcmsr_iop_message_wrote(acb);
1a4f550a
NC		 2394 }
2395}
2396
bb263c4e
CH		 2397void
2398arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
1a4f550a 2399{
bb263c4e
CH		 2400 uint8_t *pQbuffer;
2401 struct QBUFFER __iomem *pwbuffer;
2402 uint8_t __iomem *iop_data;
2403 int32_t allxfer_len = 0;
1a4f550a 2404
52b4dab3 2405 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) {
bb263c4e
CH		 2406 arcmsr_write_ioctldata2iop_in_DWORD(acb);
2407 return;
2408 }
2409 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1a4f550a
NC		 2410 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
2411 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
2412 iop_data = (uint8_t __iomem *)pwbuffer->data;
2e9feb43 2413 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
bb263c4e 2414 && (allxfer_len < 124)) {
2e9feb43 2415 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
bb263c4e 2416 writeb(*pQbuffer, iop_data);
2e9feb43
CH		 2417 acb->wqbuf_getIndex++;
2418 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
1a4f550a
NC		 2419 iop_data++;
2420 allxfer_len++;
2421 }
bb263c4e 2422 writel(allxfer_len, &pwbuffer->data_len);
1a4f550a
NC		 2423 arcmsr_iop_message_wrote(acb);
2424 }
bb263c4e 2425}
1a4f550a 2426
bb263c4e
CH		 2427static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
2428{
2429 unsigned long flags;
2430
2431 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2432 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
2e9feb43 2433 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
bb263c4e 2434 arcmsr_write_ioctldata2iop(acb);
2e9feb43 2435 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
1a4f550a 2436 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
bb263c4e 2437 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
1a4f550a
NC		 2438}
2439
626fa32c 2440static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2441{
2442 uint32_t outbound_doorbell;
80da1adb 2443 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 2444 outbound_doorbell = readl(&reg->outbound_doorbell);
6b393722
CH		 2445 do {
2446 writel(outbound_doorbell, &reg->outbound_doorbell);
2447 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
2448 arcmsr_iop2drv_data_wrote_handle(acb);
2449 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
2450 arcmsr_iop2drv_data_read_handle(acb);
2451 outbound_doorbell = readl(&reg->outbound_doorbell);
2452 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
2453 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
1a4f550a 2454}
626fa32c 2455static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
cdd3cb15
NC		 2456{
2457 uint32_t outbound_doorbell;
c10b1d54 2458 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 2459 /*
2460 *******************************************************************
2461 ** Maybe here we need to check wrqbuffer_lock is lock or not
2462 ** DOORBELL: din! don!
2463 ** check if there are any mail need to pack from firmware
2464 *******************************************************************
2465 */
2466 outbound_doorbell = readl(&reg->outbound_doorbell);
6b393722
CH		 2467 do {
2468 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
2469 readl(&reg->outbound_doorbell_clear);
2470 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
2471 arcmsr_iop2drv_data_wrote_handle(pACB);
2472 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
2473 arcmsr_iop2drv_data_read_handle(pACB);
2474 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
626fa32c 2475 arcmsr_hbaC_message_isr(pACB);
6b393722
CH		 2476 outbound_doorbell = readl(&reg->outbound_doorbell);
2477 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
2478 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
2479 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
cdd3cb15 2480}
5b37479a
CH		 2481
2482static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
2483{
2484 uint32_t outbound_doorbell;
2485 struct MessageUnit_D *pmu = pACB->pmuD;
2486
2487 outbound_doorbell = readl(pmu->outbound_doorbell);
2488 do {
2489 writel(outbound_doorbell, pmu->outbound_doorbell);
2490 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
2491 arcmsr_hbaD_message_isr(pACB);
2492 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
2493 arcmsr_iop2drv_data_wrote_handle(pACB);
2494 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
2495 arcmsr_iop2drv_data_read_handle(pACB);
2496 outbound_doorbell = readl(pmu->outbound_doorbell);
2497 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
2498 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
2499 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
2500}
2501
23509024
CH		 2502static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB)
2503{
d9a23122 2504 uint32_t outbound_doorbell, in_doorbell, tmp, i;
23509024
CH		 2505 struct MessageUnit_E __iomem *reg = pACB->pmuE;
2506
d9a23122
H		 2507 if (pACB->adapter_type == ACB_ADAPTER_TYPE_F) {
2508 for (i = 0; i < 5; i++) {
2509 in_doorbell = readl(&reg->iobound_doorbell);
2510 if (in_doorbell != 0)
2511 break;
2512 }
2513 } else
2514 in_doorbell = readl(&reg->iobound_doorbell);
23509024
CH		 2515 outbound_doorbell = in_doorbell ^ pACB->in_doorbell;
2516 do {
2517 writel(0, &reg->host_int_status); /* clear interrupt */
2518 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2519 arcmsr_iop2drv_data_wrote_handle(pACB);
2520 }
2521 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2522 arcmsr_iop2drv_data_read_handle(pACB);
2523 }
2524 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2525 arcmsr_hbaE_message_isr(pACB);
2526 }
2527 tmp = in_doorbell;
2528 in_doorbell = readl(&reg->iobound_doorbell);
2529 outbound_doorbell = tmp ^ in_doorbell;
2530 } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK
2531 | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK
2532 | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE));
2533 pACB->in_doorbell = in_doorbell;
2534}
2535
626fa32c 2536static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2537{
2538 uint32_t flag_ccb;
80da1adb 2539 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15
NC		 2540 struct ARCMSR_CDB *pARCMSR_CDB;
2541 struct CommandControlBlock *pCCB;
2542 bool error;
9e386a55
CH		 2543 unsigned long cdb_phy_addr;
2544
1a4f550a 2545 while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
9e386a55
CH		 2546 cdb_phy_addr = (flag_ccb << 5) & 0xffffffff;
2547 if (acb->cdb_phyadd_hipart)
2548 cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart;
2549 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr);
cdd3cb15
NC		 2550 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
2551 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2552 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 2553 }
2554}
626fa32c 2555static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2556{
2557 uint32_t index;
2558 uint32_t flag_ccb;
80da1adb 2559 struct MessageUnit_B *reg = acb->pmuB;
cdd3cb15
NC		 2560 struct ARCMSR_CDB *pARCMSR_CDB;
2561 struct CommandControlBlock *pCCB;
2562 bool error;
e66764f2
CH		 2563 unsigned long cdb_phy_addr;
2564
1a4f550a 2565 index = reg->doneq_index;
c10b1d54 2566 while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
e66764f2
CH		 2567 cdb_phy_addr = (flag_ccb << 5) & 0xffffffff;
2568 if (acb->cdb_phyadd_hipart)
2569 cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart;
2570 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr);
cdd3cb15
NC		 2571 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
2572 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2573 arcmsr_drain_donequeue(acb, pCCB, error);
e66764f2 2574 reg->done_qbuffer[index] = 0;
1a4f550a
NC		 2575 index++;
2576 index %= ARCMSR_MAX_HBB_POSTQUEUE;
2577 reg->doneq_index = index;
2578 }
2579}
cdd3cb15 2580
626fa32c 2581static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
cdd3cb15 2582{
c10b1d54 2583 struct MessageUnit_C __iomem *phbcmu;
cdd3cb15
NC		 2584 struct ARCMSR_CDB *arcmsr_cdb;
2585 struct CommandControlBlock *ccb;
c71ec551
CH		 2586 uint32_t flag_ccb, throttling = 0;
2587 unsigned long ccb_cdb_phy;
cdd3cb15
NC		 2588 int error;
2589
c10b1d54 2590 phbcmu = acb->pmuC;
cdd3cb15
NC		 2591 /* areca cdb command done */
2592 /* Use correct offset and size for syncing */
2593
6b393722
CH		 2594 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
2595 0xFFFFFFFF) {
2596 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
c71ec551
CH		 2597 if (acb->cdb_phyadd_hipart)
2598 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
6b393722
CH		 2599 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
2600 + ccb_cdb_phy);
2601 ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
2602 arcmsr_cdb);
2603 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2604 ? true : false;
2605 /* check if command done with no error */
2606 arcmsr_drain_donequeue(acb, ccb, error);
2607 throttling++;
2608 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2609 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
2610 &phbcmu->inbound_doorbell);
2611 throttling = 0;
2612 }
cdd3cb15
NC		 2613 }
2614}
5b37479a
CH		 2615
2616static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
2617{
3b8155d5 2618 u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
a36ade41 2619 uint32_t addressLow;
5b37479a
CH		 2620 int error;
2621 struct MessageUnit_D *pmu;
2622 struct ARCMSR_CDB *arcmsr_cdb;
2623 struct CommandControlBlock *ccb;
18bc435e 2624 unsigned long flags, ccb_cdb_phy;
5b37479a
CH		 2625
2626 spin_lock_irqsave(&acb->doneq_lock, flags);
2627 pmu = acb->pmuD;
2628 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
2629 doneq_index = pmu->doneq_index;
2630 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
2631 do {
3b8155d5
CH		 2632 toggle = doneq_index & 0x4000;
2633 index_stripped = (doneq_index & 0xFFF) + 1;
2634 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
2635 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
2636 ((toggle ^ 0x4000) + 1);
5b37479a
CH		 2637 doneq_index = pmu->doneq_index;
2638 addressLow = pmu->done_qbuffer[doneq_index &
2639 0xFFF].addressLow;
2640 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
a36ade41
CH		 2641 if (acb->cdb_phyadd_hipart)
2642 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
5b37479a
CH		 2643 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
2644 + ccb_cdb_phy);
2645 ccb = container_of(arcmsr_cdb,
2646 struct CommandControlBlock, arcmsr_cdb);
2647 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2648 ? true : false;
2649 arcmsr_drain_donequeue(acb, ccb, error);
2650 writel(doneq_index, pmu->outboundlist_read_pointer);
2651 } while ((doneq_index & 0xFFF) !=
2652 (outbound_write_pointer & 0xFFF));
2653 }
2654 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
2655 pmu->outboundlist_interrupt_cause);
2656 readl(pmu->outboundlist_interrupt_cause);
2657 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2658}
2659
23509024
CH		 2660static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb)
2661{
2662 uint32_t doneq_index;
2663 uint16_t cmdSMID;
2664 int error;
2665 struct MessageUnit_E __iomem *pmu;
2666 struct CommandControlBlock *ccb;
2667 unsigned long flags;
2668
2669 spin_lock_irqsave(&acb->doneq_lock, flags);
2670 doneq_index = acb->doneq_index;
2671 pmu = acb->pmuE;
2672 while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) {
2673 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2674 ccb = acb->pccb_pool[cmdSMID];
2675 error = (acb->pCompletionQ[doneq_index].cmdFlag
2676 & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
2677 arcmsr_drain_donequeue(acb, ccb, error);
2678 doneq_index++;
2679 if (doneq_index >= acb->completionQ_entry)
2680 doneq_index = 0;
2681 }
2682 acb->doneq_index = doneq_index;
2683 writel(doneq_index, &pmu->reply_post_consumer_index);
2684 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2685}
2686
ae897ae2
H		 2687static void arcmsr_hbaF_postqueue_isr(struct AdapterControlBlock *acb)
2688{
2689 uint32_t doneq_index;
2690 uint16_t cmdSMID;
2691 int error;
2692 struct MessageUnit_F __iomem *phbcmu;
2693 struct CommandControlBlock *ccb;
2694 unsigned long flags;
2695
2696 spin_lock_irqsave(&acb->doneq_lock, flags);
2697 doneq_index = acb->doneq_index;
2698 phbcmu = acb->pmuF;
2699 while (1) {
2700 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2701 if (cmdSMID == 0xffff)
2702 break;
2703 ccb = acb->pccb_pool[cmdSMID];
2704 error = (acb->pCompletionQ[doneq_index].cmdFlag &
2705 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
2706 arcmsr_drain_donequeue(acb, ccb, error);
2707 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff;
2708 doneq_index++;
2709 if (doneq_index >= acb->completionQ_entry)
2710 doneq_index = 0;
2711 }
2712 acb->doneq_index = doneq_index;
2713 writel(doneq_index, &phbcmu->reply_post_consumer_index);
2714 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2715}
2716
36b83ded
NC		 2717/*
2718**********************************************************************************
2719** Handle a message interrupt
2720**
cdd3cb15 2721** The only message interrupt we expect is in response to a query for the current adapter config.
36b83ded
NC		 2722** We want this in order to compare the drivemap so that we can detect newly-attached drives.
2723**********************************************************************************
2724*/
626fa32c 2725static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
36b83ded 2726{
c10b1d54 2727 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded
NC		 2728 /*clear interrupt and message state*/
2729 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
5dd8b3e7
CH		 2730 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2731 schedule_work(&acb->arcmsr_do_message_isr_bh);
36b83ded 2732}
626fa32c 2733static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
36b83ded
NC		 2734{
2735 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2736
36b83ded 2737 /*clear interrupt and message state*/
ae52e7f0 2738 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
5dd8b3e7
CH		 2739 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2740 schedule_work(&acb->arcmsr_do_message_isr_bh);
36b83ded 2741}
cdd3cb15
NC		 2742/*
2743**********************************************************************************
2744** Handle a message interrupt
2745**
2746** The only message interrupt we expect is in response to a query for the
2747** current adapter config.
2748** We want this in order to compare the drivemap so that we can detect newly-attached drives.
2749**********************************************************************************
2750*/
626fa32c 2751static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
cdd3cb15 2752{
c10b1d54 2753 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 2754 /*clear interrupt and message state*/
2755 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
5dd8b3e7
CH		 2756 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2757 schedule_work(&acb->arcmsr_do_message_isr_bh);
cdd3cb15
NC		 2758}
2759
5b37479a
CH		 2760static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
2761{
2762 struct MessageUnit_D *reg = acb->pmuD;
2763
2764 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
2765 readl(reg->outbound_doorbell);
5dd8b3e7
CH		 2766 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2767 schedule_work(&acb->arcmsr_do_message_isr_bh);
5b37479a
CH		 2768}
2769
23509024
CH		 2770static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb)
2771{
2772 struct MessageUnit_E __iomem *reg = acb->pmuE;
2773
2774 writel(0, &reg->host_int_status);
5dd8b3e7
CH		 2775 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2776 schedule_work(&acb->arcmsr_do_message_isr_bh);
23509024
CH		 2777}
2778
626fa32c 2779static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2780{
2781 uint32_t outbound_intstatus;
80da1adb 2782 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 2783 outbound_intstatus = readl(&reg->outbound_intstatus) &
cdd3cb15 2784 acb->outbound_int_enable;
6b393722
CH		 2785 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
2786 return IRQ_NONE;
2787 do {
2788 writel(outbound_intstatus, &reg->outbound_intstatus);
2789 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
626fa32c 2790 arcmsr_hbaA_doorbell_isr(acb);
6b393722 2791 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
626fa32c 2792 arcmsr_hbaA_postqueue_isr(acb);
6b393722 2793 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
626fa32c 2794 arcmsr_hbaA_message_isr(acb);
6b393722
CH		 2795 outbound_intstatus = readl(&reg->outbound_intstatus) &
2796 acb->outbound_int_enable;
2797 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
2798 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
2799 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
2800 return IRQ_HANDLED;
1a4f550a
NC		 2801}
2802
626fa32c 2803static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2804{
2805 uint32_t outbound_doorbell;
80da1adb 2806 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2807 outbound_doorbell = readl(reg->iop2drv_doorbell) &
cdd3cb15 2808 acb->outbound_int_enable;
1a4f550a 2809 if (!outbound_doorbell)
6b393722
CH		 2810 return IRQ_NONE;
2811 do {
2812 writel(~outbound_doorbell, reg->iop2drv_doorbell);
2813 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
2814 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
2815 arcmsr_iop2drv_data_wrote_handle(acb);
2816 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
2817 arcmsr_iop2drv_data_read_handle(acb);
2818 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
626fa32c 2819 arcmsr_hbaB_postqueue_isr(acb);
6b393722 2820 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
626fa32c 2821 arcmsr_hbaB_message_isr(acb);
6b393722
CH		 2822 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2823 acb->outbound_int_enable;
2824 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
2825 | ARCMSR_IOP2DRV_DATA_READ_OK
2826 | ARCMSR_IOP2DRV_CDB_DONE
2827 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
2828 return IRQ_HANDLED;
1a4f550a
NC		 2829}
2830
626fa32c 2831static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
cdd3cb15
NC		 2832{
2833 uint32_t host_interrupt_status;
c10b1d54 2834 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
cdd3cb15
NC		 2835 /*
2836 *********************************************
2837 ** check outbound intstatus
2838 *********************************************
2839 */
6b393722
CH		 2840 host_interrupt_status = readl(&phbcmu->host_int_status) &
2841 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2842 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2843 if (!host_interrupt_status)
2844 return IRQ_NONE;
2845 do {
2846 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
626fa32c 2847 arcmsr_hbaC_doorbell_isr(pACB);
6b393722
CH		 2848 /* MU post queue interrupts*/
2849 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
626fa32c 2850 arcmsr_hbaC_postqueue_isr(pACB);
6b393722
CH		 2851 host_interrupt_status = readl(&phbcmu->host_int_status);
2852 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2853 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2854 return IRQ_HANDLED;
cdd3cb15 2855}
5b37479a
CH		 2856
2857static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
2858{
2859 u32 host_interrupt_status;
2860 struct MessageUnit_D *pmu = pACB->pmuD;
2861
2862 host_interrupt_status = readl(pmu->host_int_status) &
2863 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2864 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
2865 if (!host_interrupt_status)
2866 return IRQ_NONE;
2867 do {
2868 /* MU post queue interrupts*/
2869 if (host_interrupt_status &
2870 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
2871 arcmsr_hbaD_postqueue_isr(pACB);
2872 if (host_interrupt_status &
2873 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
2874 arcmsr_hbaD_doorbell_isr(pACB);
2875 host_interrupt_status = readl(pmu->host_int_status);
2876 } while (host_interrupt_status &
2877 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2878 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
2879 return IRQ_HANDLED;
2880}
2881
23509024
CH		 2882static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB)
2883{
2884 uint32_t host_interrupt_status;
2885 struct MessageUnit_E __iomem *pmu = pACB->pmuE;
2886
2887 host_interrupt_status = readl(&pmu->host_int_status) &
2888 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2889 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2890 if (!host_interrupt_status)
2891 return IRQ_NONE;
2892 do {
2893 /* MU ioctl transfer doorbell interrupts*/
2894 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2895 arcmsr_hbaE_doorbell_isr(pACB);
2896 }
2897 /* MU post queue interrupts*/
2898 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2899 arcmsr_hbaE_postqueue_isr(pACB);
2900 }
2901 host_interrupt_status = readl(&pmu->host_int_status);
2902 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2903 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2904 return IRQ_HANDLED;
2905}
2906
ae897ae2
H		 2907static irqreturn_t arcmsr_hbaF_handle_isr(struct AdapterControlBlock *pACB)
2908{
2909 uint32_t host_interrupt_status;
2910 struct MessageUnit_F __iomem *phbcmu = pACB->pmuF;
2911
2912 host_interrupt_status = readl(&phbcmu->host_int_status) &
2913 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2914 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2915 if (!host_interrupt_status)
2916 return IRQ_NONE;
2917 do {
2918 /* MU post queue interrupts*/
2919 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR)
2920 arcmsr_hbaF_postqueue_isr(pACB);
2921
2922 /* MU ioctl transfer doorbell interrupts*/
2923 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)
2924 arcmsr_hbaE_doorbell_isr(pACB);
2925
2926 host_interrupt_status = readl(&phbcmu->host_int_status);
2927 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2928 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2929 return IRQ_HANDLED;
2930}
2931
1a4f550a
NC		 2932static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
2933{
2934 switch (acb->adapter_type) {
6b393722 2935 case ACB_ADAPTER_TYPE_A:
626fa32c 2936 return arcmsr_hbaA_handle_isr(acb);
6b393722 2937 case ACB_ADAPTER_TYPE_B:
626fa32c 2938 return arcmsr_hbaB_handle_isr(acb);
6b393722 2939 case ACB_ADAPTER_TYPE_C:
626fa32c 2940 return arcmsr_hbaC_handle_isr(acb);
5b37479a
CH		 2941 case ACB_ADAPTER_TYPE_D:
2942 return arcmsr_hbaD_handle_isr(acb);
23509024
CH		 2943 case ACB_ADAPTER_TYPE_E:
2944 return arcmsr_hbaE_handle_isr(acb);
ae897ae2
H		 2945 case ACB_ADAPTER_TYPE_F:
2946 return arcmsr_hbaF_handle_isr(acb);
6b393722
CH		 2947 default:
2948 return IRQ_NONE;
1c57e86d 2949 }
1c57e86d
EC		 2950}
2951
2952static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2953{
2954 if (acb) {
2955 /* stop adapter background rebuild */
2956 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
1a4f550a 2957 uint32_t intmask_org;
1c57e86d 2958 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1a4f550a 2959 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d
EC		 2960 arcmsr_stop_adapter_bgrb(acb);
2961 arcmsr_flush_adapter_cache(acb);
1a4f550a
NC		 2962 arcmsr_enable_outbound_ints(acb, intmask_org);
2963 }
2964 }
2965}
2966
bb263c4e
CH		 2967
2968void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
1a4f550a 2969{
bb263c4e
CH		 2970 uint32_t i;
2971
2972 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2973 for (i = 0; i < 15; i++) {
2974 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2975 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2e9feb43
CH		 2976 acb->rqbuf_getIndex = 0;
2977 acb->rqbuf_putIndex = 0;
bb263c4e
CH		 2978 arcmsr_iop_message_read(acb);
2979 mdelay(30);
2e9feb43
CH		 2980 } else if (acb->rqbuf_getIndex !=
2981 acb->rqbuf_putIndex) {
2982 acb->rqbuf_getIndex = 0;
2983 acb->rqbuf_putIndex = 0;
bb263c4e
CH		 2984 mdelay(30);
2985 } else
2986 break;
1c57e86d
EC		 2987 }
2988 }
2989}
2990
36b83ded 2991static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
bb263c4e 2992 struct scsi_cmnd *cmd)
1c57e86d 2993{
1c57e86d 2994 char *buffer;
bb263c4e
CH		 2995 unsigned short use_sg;
2996 int retvalue = 0, transfer_len = 0;
2997 unsigned long flags;
2998 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2999 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
3000 (uint32_t)cmd->cmnd[6] << 16 |
3001 (uint32_t)cmd->cmnd[7] << 8 |
3002 (uint32_t)cmd->cmnd[8];
deff2627 3003 struct scatterlist *sg;
bb263c4e
CH		 3004
3005 use_sg = scsi_sg_count(cmd);
deff2627 3006 sg = scsi_sglist(cmd);
77dfce07 3007 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
bb263c4e 3008 if (use_sg > 1) {
deff2627
FT		 3009 retvalue = ARCMSR_MESSAGE_FAIL;
3010 goto message_out;
1c57e86d 3011 }
deff2627 3012 transfer_len += sg->length;
1c57e86d
EC		 3013 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
3014 retvalue = ARCMSR_MESSAGE_FAIL;
bb263c4e 3015 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
1c57e86d
EC		 3016 goto message_out;
3017 }
bb263c4e
CH		 3018 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
3019 switch (controlcode) {
1c57e86d 3020 case ARCMSR_MESSAGE_READ_RQBUFFER: {
69e562c2 3021 unsigned char *ver_addr;
2e9feb43 3022 uint8_t *ptmpQbuffer;
bb263c4e 3023 uint32_t allxfer_len = 0;
2e9feb43 3024 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
69e562c2 3025 if (!ver_addr) {
1a4f550a 3026 retvalue = ARCMSR_MESSAGE_FAIL;
bb263c4e 3027 pr_info("%s: memory not enough!\n", __func__);
1a4f550a
NC		 3028 goto message_out;
3029 }
69e562c2 3030 ptmpQbuffer = ver_addr;
bb263c4e 3031 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2e9feb43
CH		 3032 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
3033 unsigned int tail = acb->rqbuf_getIndex;
3034 unsigned int head = acb->rqbuf_putIndex;
3035 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
3036
3037 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
3038 if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
3039 allxfer_len = ARCMSR_API_DATA_BUFLEN;
3040
3041 if (allxfer_len <= cnt_to_end)
3042 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
3043 else {
3044 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
3045 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
bb263c4e 3046 }
2e9feb43 3047 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
1a4f550a 3048 }
bb263c4e
CH		 3049 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
3050 allxfer_len);
1a4f550a 3051 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
80da1adb 3052 struct QBUFFER __iomem *prbuffer;
1a4f550a
NC		 3053 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
3054 prbuffer = arcmsr_get_iop_rqbuffer(acb);
bb263c4e
CH		 3055 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
3056 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
ae52e7f0 3057 }
bb263c4e 3058 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
69e562c2 3059 kfree(ver_addr);
bb263c4e
CH		 3060 pcmdmessagefld->cmdmessage.Length = allxfer_len;
3061 if (acb->fw_flag == FW_DEADLOCK)
3062 pcmdmessagefld->cmdmessage.ReturnCode =
3063 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3064 else
3065 pcmdmessagefld->cmdmessage.ReturnCode =
3066 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 3067 break;
bb263c4e 3068 }
1a4f550a 3069 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
69e562c2 3070 unsigned char *ver_addr;
7bc2b55a
DC		 3071 uint32_t user_len;
3072 int32_t cnt2end;
1a4f550a 3073 uint8_t *pQbuffer, *ptmpuserbuffer;
4bd173c3
BP		 3074
3075 user_len = pcmdmessagefld->cmdmessage.Length;
3076 if (user_len > ARCMSR_API_DATA_BUFLEN) {
1a4f550a
NC		 3077 retvalue = ARCMSR_MESSAGE_FAIL;
3078 goto message_out;
3079 }
4bd173c3
BP		 3080
3081 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
3082 if (!ver_addr) {
7bc2b55a 3083 retvalue = ARCMSR_MESSAGE_FAIL;
7bc2b55a
DC		 3084 goto message_out;
3085 }
4bd173c3
BP		 3086 ptmpuserbuffer = ver_addr;
3087
bb263c4e
CH		 3088 memcpy(ptmpuserbuffer,
3089 pcmdmessagefld->messagedatabuffer, user_len);
3090 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2e9feb43 3091 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
1a4f550a
NC		 3092 struct SENSE_DATA *sensebuffer =
3093 (struct SENSE_DATA *)cmd->sense_buffer;
bb263c4e 3094 arcmsr_write_ioctldata2iop(acb);
1a4f550a 3095 /* has error report sensedata */
bb263c4e 3096 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
1a4f550a
NC		 3097 sensebuffer->SenseKey = ILLEGAL_REQUEST;
3098 sensebuffer->AdditionalSenseLength = 0x0A;
3099 sensebuffer->AdditionalSenseCode = 0x20;
3100 sensebuffer->Valid = 1;
3101 retvalue = ARCMSR_MESSAGE_FAIL;
3102 } else {
2e9feb43
CH		 3103 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
3104 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
3105 if (user_len > cnt2end) {
3106 memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
3107 ptmpuserbuffer += cnt2end;
3108 user_len -= cnt2end;
3109 acb->wqbuf_putIndex = 0;
3110 pQbuffer = acb->wqbuffer;
3111 }
3112 memcpy(pQbuffer, ptmpuserbuffer, user_len);
3113 acb->wqbuf_putIndex += user_len;
3114 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
3115 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
3116 acb->acb_flags &=
1a4f550a 3117 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2e9feb43 3118 arcmsr_write_ioctldata2iop(acb);
1a4f550a 3119 }
1c57e86d 3120 }
bb263c4e
CH		 3121 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
3122 kfree(ver_addr);
3123 if (acb->fw_flag == FW_DEADLOCK)
3124 pcmdmessagefld->cmdmessage.ReturnCode =
3125 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3126 else
3127 pcmdmessagefld->cmdmessage.ReturnCode =
3128 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 3129 break;
bb263c4e 3130 }
1c57e86d 3131 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
1a4f550a 3132 uint8_t *pQbuffer = acb->rqbuffer;
bb263c4e
CH		 3133
3134 arcmsr_clear_iop2drv_rqueue_buffer(acb);
3135 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
1a4f550a 3136 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2e9feb43
CH		 3137 acb->rqbuf_getIndex = 0;
3138 acb->rqbuf_putIndex = 0;
1a4f550a 3139 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
bb263c4e
CH		 3140 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
3141 if (acb->fw_flag == FW_DEADLOCK)
ae52e7f0 3142 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 3143 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3144 else
ae52e7f0 3145 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e 3146 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 3147 break;
bb263c4e 3148 }
1c57e86d 3149 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
1a4f550a 3150 uint8_t *pQbuffer = acb->wqbuffer;
bb263c4e
CH		 3151 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
3152 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
3153 ACB_F_MESSAGE_WQBUFFER_READED);
2e9feb43
CH		 3154 acb->wqbuf_getIndex = 0;
3155 acb->wqbuf_putIndex = 0;
1a4f550a 3156 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
bb263c4e
CH		 3157 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
3158 if (acb->fw_flag == FW_DEADLOCK)
3159 pcmdmessagefld->cmdmessage.ReturnCode =
3160 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3161 else
3162 pcmdmessagefld->cmdmessage.ReturnCode =
3163 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 3164 break;
bb263c4e 3165 }
1c57e86d 3166 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
1a4f550a 3167 uint8_t *pQbuffer;
bb263c4e
CH		 3168 arcmsr_clear_iop2drv_rqueue_buffer(acb);
3169 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
3170 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2e9feb43
CH		 3171 acb->rqbuf_getIndex = 0;
3172 acb->rqbuf_putIndex = 0;
1a4f550a
NC		 3173 pQbuffer = acb->rqbuffer;
3174 memset(pQbuffer, 0, sizeof(struct QBUFFER));
bb263c4e
CH		 3175 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
3176 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
3177 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
3178 ACB_F_MESSAGE_WQBUFFER_READED);
2e9feb43
CH		 3179 acb->wqbuf_getIndex = 0;
3180 acb->wqbuf_putIndex = 0;
1a4f550a
NC		 3181 pQbuffer = acb->wqbuffer;
3182 memset(pQbuffer, 0, sizeof(struct QBUFFER));
bb263c4e
CH		 3183 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
3184 if (acb->fw_flag == FW_DEADLOCK)
ae52e7f0 3185 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 3186 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3187 else
ae52e7f0 3188 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e 3189 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 3190 break;
bb263c4e 3191 }
1c57e86d 3192 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
bb263c4e 3193 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 3194 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 3195 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3196 else
ae52e7f0 3197 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e 3198 ARCMSR_MESSAGE_RETURNCODE_3F;
1c57e86d 3199 break;
bb263c4e 3200 }
1c57e86d 3201 case ARCMSR_MESSAGE_SAY_HELLO: {
1a4f550a 3202 int8_t *hello_string = "Hello! I am ARCMSR";
bb263c4e 3203 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 3204 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 3205 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3206 else
ae52e7f0 3207 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 3208 ARCMSR_MESSAGE_RETURNCODE_OK;
3209 memcpy(pcmdmessagefld->messagedatabuffer,
3210 hello_string, (int16_t)strlen(hello_string));
1c57e86d 3211 break;
bb263c4e
CH		 3212 }
3213 case ARCMSR_MESSAGE_SAY_GOODBYE: {
3214 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 3215 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 3216 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3217 else
3218 pcmdmessagefld->cmdmessage.ReturnCode =
3219 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d
EC		 3220 arcmsr_iop_parking(acb);
3221 break;
bb263c4e
CH		 3222 }
3223 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
3224 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 3225 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 3226 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
3227 else
3228 pcmdmessagefld->cmdmessage.ReturnCode =
3229 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d
EC		 3230 arcmsr_flush_adapter_cache(acb);
3231 break;
bb263c4e 3232 }
1c57e86d
EC		 3233 default:
3234 retvalue = ARCMSR_MESSAGE_FAIL;
bb263c4e
CH		 3235 pr_info("%s: unknown controlcode!\n", __func__);
3236 }
3237message_out:
3238 if (use_sg) {
3239 struct scatterlist *sg = scsi_sglist(cmd);
3240 kunmap_atomic(buffer - sg->offset);
1c57e86d 3241 }
1c57e86d
EC		 3242 return retvalue;
3243}
3244
3245static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
3246{
eb3b956d 3247 struct list_head *head;
1c57e86d 3248 struct CommandControlBlock *ccb = NULL;
ae52e7f0 3249 unsigned long flags;
eb3b956d 3250
ae52e7f0 3251 spin_lock_irqsave(&acb->ccblist_lock, flags);
eb3b956d 3252 head = &acb->ccb_free_list;
1c57e86d
EC		 3253 if (!list_empty(head)) {
3254 ccb = list_entry(head->next, struct CommandControlBlock, list);
ae52e7f0 3255 list_del_init(&ccb->list);
cdd3cb15 3256 }else{
ae52e7f0 3257 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
c10b1d54 3258 return NULL;
1c57e86d 3259 }
ae52e7f0 3260 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 3261 return ccb;
3262}
3263
3264static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
3265 struct scsi_cmnd *cmd)
3266{
3267 switch (cmd->cmnd[0]) {
3268 case INQUIRY: {
3269 unsigned char inqdata[36];
3270 char *buffer;
deff2627 3271 struct scatterlist *sg;
1c57e86d
EC		 3272
3273 if (cmd->device->lun) {
3274 cmd->result = (DID_TIME_OUT << 16);
3f0b59b6 3275 scsi_done(cmd);
1c57e86d
EC		 3276 return;
3277 }
3278 inqdata[0] = TYPE_PROCESSOR;
3279 /* Periph Qualifier & Periph Dev Type */
3280 inqdata[1] = 0;
3281 /* rem media bit & Dev Type Modifier */
3282 inqdata[2] = 0;
a1f6e021 3283 /* ISO, ECMA, & ANSI versions */
1c57e86d
EC		 3284 inqdata[4] = 31;
3285 /* length of additional data */
d2a2f379 3286 memcpy(&inqdata[8], "Areca ", 8);
1c57e86d 3287 /* Vendor Identification */
d2a2f379 3288 memcpy(&inqdata[16], "RAID controller ", 16);
1c57e86d 3289 /* Product Identification */
d2a2f379 3290 memcpy(&inqdata[32], "R001", 4); /* Product Revision */
1c57e86d 3291
deff2627 3292 sg = scsi_sglist(cmd);
77dfce07 3293 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
deff2627 3294
1c57e86d 3295 memcpy(buffer, inqdata, sizeof(inqdata));
deff2627 3296 sg = scsi_sglist(cmd);
77dfce07 3297 kunmap_atomic(buffer - sg->offset);
1c57e86d 3298
3f0b59b6 3299 scsi_done(cmd);
1c57e86d
EC		 3300 }
3301 break;
3302 case WRITE_BUFFER:
3303 case READ_BUFFER: {
3304 if (arcmsr_iop_message_xfer(acb, cmd))
3305 cmd->result = (DID_ERROR << 16);
3f0b59b6 3306 scsi_done(cmd);
1c57e86d
EC		 3307 }
3308 break;
3309 default:
3f0b59b6 3310 scsi_done(cmd);
1c57e86d
EC		 3311 }
3312}
3313
af049dfd 3314static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd)
1c57e86d
EC		 3315{
3316 struct Scsi_Host *host = cmd->device->host;
1a4f550a 3317 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
1c57e86d
EC		 3318 struct CommandControlBlock *ccb;
3319 int target = cmd->device->id;
c4c1adb3
CH		 3320
3321 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) {
3322 cmd->result = (DID_NO_CONNECT << 16);
3f0b59b6 3323 scsi_done(cmd);
c4c1adb3
CH		 3324 return 0;
3325 }
1c57e86d
EC		 3326 cmd->host_scribble = NULL;
3327 cmd->result = 0;
a1f6e021 3328 if (target == 16) {
1c57e86d
EC		 3329 /* virtual device for iop message transfer */
3330 arcmsr_handle_virtual_command(acb, cmd);
3331 return 0;
3332 }
1c57e86d
EC		 3333 ccb = arcmsr_get_freeccb(acb);
3334 if (!ccb)
3335 return SCSI_MLQUEUE_HOST_BUSY;
cdd3cb15 3336 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
3d45cefc 3337 cmd->result = (DID_ERROR << 16) | SAM_STAT_RESERVATION_CONFLICT;
3f0b59b6 3338 scsi_done(cmd);
76d78300
NC		 3339 return 0;
3340 }
1c57e86d
EC		 3341 arcmsr_post_ccb(acb, ccb);
3342 return 0;
3343}
3344
f281233d
JG		 3345static DEF_SCSI_QCMD(arcmsr_queue_command)
3346
4f1826b8
H		 3347static int arcmsr_slave_config(struct scsi_device *sdev)
3348{
3349 unsigned int dev_timeout;
3350
3351 dev_timeout = sdev->request_queue->rq_timeout;
3352 if ((cmd_timeout > 0) && ((cmd_timeout * HZ) > dev_timeout))
3353 blk_queue_rq_timeout(sdev->request_queue, cmd_timeout * HZ);
3354 return 0;
3355}
3356
1e9c8108 3357static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer)
1c57e86d 3358{
1c57e86d 3359 int count;
1e9c8108
CH		 3360 uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model;
3361 uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version;
3362 uint32_t *acb_device_map = (uint32_t *)pACB->device_map;
3363 uint32_t *firm_model = &rwbuffer[15];
3364 uint32_t *firm_version = &rwbuffer[17];
3365 uint32_t *device_map = &rwbuffer[21];
3366
3367 count = 2;
3368 while (count) {
3369 *acb_firm_model = readl(firm_model);
1c57e86d 3370 acb_firm_model++;
1e9c8108 3371 firm_model++;
1c57e86d
EC		 3372 count--;
3373 }
1e9c8108
CH		 3374 count = 4;
3375 while (count) {
3376 *acb_firm_version = readl(firm_version);
1c57e86d 3377 acb_firm_version++;
1e9c8108 3378 firm_version++;
1c57e86d
EC		 3379 count--;
3380 }
1e9c8108
CH		 3381 count = 4;
3382 while (count) {
3383 *acb_device_map = readl(device_map);
cdd3cb15 3384 acb_device_map++;
1e9c8108 3385 device_map++;
cdd3cb15
NC		 3386 count--;
3387 }
1e9c8108
CH		 3388 pACB->signature = readl(&rwbuffer[0]);
3389 pACB->firm_request_len = readl(&rwbuffer[1]);
3390 pACB->firm_numbers_queue = readl(&rwbuffer[2]);
3391 pACB->firm_sdram_size = readl(&rwbuffer[3]);
3392 pACB->firm_hd_channels = readl(&rwbuffer[4]);
3393 pACB->firm_cfg_version = readl(&rwbuffer[25]);
14ef4b00
H		 3394 if (pACB->adapter_type == ACB_ADAPTER_TYPE_F)
3395 pACB->firm_PicStatus = readl(&rwbuffer[30]);
3396 else
3397 pACB->firm_PicStatus = 0;
a2c89bbc 3398 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
1e9c8108
CH		 3399 pACB->host->host_no,
3400 pACB->firm_model,
3401 pACB->firm_version);
3402}
3403
3404static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
3405{
3406 struct MessageUnit_A __iomem *reg = acb->pmuA;
3407
3408 arcmsr_wait_firmware_ready(acb);
3409 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3410 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3411 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3412 miscellaneous data' timeout \n", acb->host->host_no);
3413 return false;
3414 }
3415 arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
ae52e7f0 3416 return true;
1c57e86d 3417}
626fa32c 3418static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
1a4f550a 3419{
02040670 3420 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 3421
7e315ffd
CH		 3422 arcmsr_wait_firmware_ready(acb);
3423 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
3424 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3425 printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no);
02040670 3426 return false;
7e315ffd 3427 }
ae52e7f0 3428 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
626fa32c 3429 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1a4f550a
NC		 3430 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3431 miscellaneous data' timeout \n", acb->host->host_no);
02040670 3432 return false;
1a4f550a 3433 }
1e9c8108 3434 arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
ae52e7f0 3435 return true;
1a4f550a 3436}
cdd3cb15 3437
626fa32c 3438static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
cdd3cb15 3439{
df9f0ee9 3440 uint32_t intmask_org;
c10b1d54 3441 struct MessageUnit_C __iomem *reg = pACB->pmuC;
1e9c8108 3442
cdd3cb15
NC		 3443 /* disable all outbound interrupt */
3444 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
3445 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
3446 /* wait firmware ready */
df9f0ee9 3447 arcmsr_wait_firmware_ready(pACB);
cdd3cb15
NC		 3448 /* post "get config" instruction */
3449 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3450 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
3451 /* wait message ready */
df9f0ee9 3452 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15
NC		 3453 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3454 miscellaneous data' timeout \n", pACB->host->host_no);
3455 return false;
3456 }
1e9c8108 3457 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
cdd3cb15
NC		 3458 return true;
3459}
5b37479a
CH		 3460
3461static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
3462{
02040670 3463 struct MessageUnit_D *reg = acb->pmuD;
5b37479a 3464
5b37479a
CH		 3465 if (readl(acb->pmuD->outbound_doorbell) &
3466 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
3467 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
3468 acb->pmuD->outbound_doorbell);/*clear interrupt*/
3469 }
b6b3084a 3470 arcmsr_wait_firmware_ready(acb);
5b37479a
CH		 3471 /* post "get config" instruction */
3472 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
3473 /* wait message ready */
3474 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
3475 pr_notice("arcmsr%d: wait get adapter firmware "
3476 "miscellaneous data timeout\n", acb->host->host_no);
5b37479a
CH		 3477 return false;
3478 }
1e9c8108 3479 arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer);
5b37479a
CH		 3480 return true;
3481}
3482
23509024
CH		 3483static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB)
3484{
23509024 3485 struct MessageUnit_E __iomem *reg = pACB->pmuE;
22c4ae5b 3486 uint32_t intmask_org;
23509024
CH		 3487
3488 /* disable all outbound interrupt */
3489 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
3490 writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);
3491 /* wait firmware ready */
22c4ae5b 3492 arcmsr_wait_firmware_ready(pACB);
23509024
CH		 3493 mdelay(20);
3494 /* post "get config" instruction */
3495 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3496
3497 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3498 writel(pACB->out_doorbell, &reg->iobound_doorbell);
3499 /* wait message ready */
22c4ae5b 3500 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
23509024
CH		 3501 pr_notice("arcmsr%d: wait get adapter firmware "
3502 "miscellaneous data timeout\n", pACB->host->host_no);
3503 return false;
3504 }
1e9c8108 3505 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
23509024
CH		 3506 return true;
3507}
3508
ae897ae2
H		 3509static bool arcmsr_hbaF_get_config(struct AdapterControlBlock *pACB)
3510{
3511 struct MessageUnit_F __iomem *reg = pACB->pmuF;
3512 uint32_t intmask_org;
3513
3514 /* disable all outbound interrupt */
3515 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
3516 writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);
3517 /* wait firmware ready */
3518 arcmsr_wait_firmware_ready(pACB);
3519 /* post "get config" instruction */
3520 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3521
3522 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3523 writel(pACB->out_doorbell, &reg->iobound_doorbell);
3524 /* wait message ready */
3525 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
3526 pr_notice("arcmsr%d: wait get adapter firmware miscellaneous data timeout\n",
3527 pACB->host->host_no);
3528 return false;
3529 }
3530 arcmsr_get_adapter_config(pACB, pACB->msgcode_rwbuffer);
3531 return true;
3532}
3533
ae52e7f0 3534static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
1a4f550a 3535{
3df824af
CH		 3536 bool rtn = false;
3537
3538 switch (acb->adapter_type) {
3539 case ACB_ADAPTER_TYPE_A:
626fa32c 3540 rtn = arcmsr_hbaA_get_config(acb);
3df824af
CH		 3541 break;
3542 case ACB_ADAPTER_TYPE_B:
626fa32c 3543 rtn = arcmsr_hbaB_get_config(acb);
3df824af
CH		 3544 break;
3545 case ACB_ADAPTER_TYPE_C:
626fa32c 3546 rtn = arcmsr_hbaC_get_config(acb);
3df824af 3547 break;
5b37479a
CH		 3548 case ACB_ADAPTER_TYPE_D:
3549 rtn = arcmsr_hbaD_get_config(acb);
3550 break;
23509024
CH		 3551 case ACB_ADAPTER_TYPE_E:
3552 rtn = arcmsr_hbaE_get_config(acb);
3553 break;
ae897ae2
H		 3554 case ACB_ADAPTER_TYPE_F:
3555 rtn = arcmsr_hbaF_get_config(acb);
3556 break;
3df824af
CH		 3557 default:
3558 break;
3559 }
dd6206e1
CH		 3560 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3561 if (acb->host->can_queue >= acb->firm_numbers_queue)
3562 acb->host->can_queue = acb->maxOutstanding;
cdd3cb15 3563 else
dd6206e1 3564 acb->maxOutstanding = acb->host->can_queue;
d076e4aa
CH		 3565 acb->maxFreeCCB = acb->host->can_queue;
3566 if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM)
3567 acb->maxFreeCCB += 64;
3df824af 3568 return rtn;
1a4f550a
NC		 3569}
3570
626fa32c 3571static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
1c57e86d
EC		 3572 struct CommandControlBlock *poll_ccb)
3573{
80da1adb 3574 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 3575 struct CommandControlBlock *ccb;
ae52e7f0 3576 struct ARCMSR_CDB *arcmsr_cdb;
1c57e86d 3577 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 3578 int rtn;
cdd3cb15 3579 bool error;
9e386a55
CH		 3580 unsigned long ccb_cdb_phy;
3581
3582polling_hba_ccb_retry:
1c57e86d 3583 poll_count++;
1a4f550a 3584 outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
1c57e86d
EC		 3585 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
3586 while (1) {
3587 if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
cdd3cb15 3588 if (poll_ccb_done){
ae52e7f0 3589 rtn = SUCCESS;
1c57e86d 3590 break;
cdd3cb15
NC		 3591 }else {
3592 msleep(25);
3593 if (poll_count > 100){
ae52e7f0 3594 rtn = FAILED;
1c57e86d 3595 break;
ae52e7f0 3596 }
1a4f550a 3597 goto polling_hba_ccb_retry;
1c57e86d
EC		 3598 }
3599 }
9e386a55
CH		 3600 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
3601 if (acb->cdb_phyadd_hipart)
3602 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
3603 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
ae52e7f0 3604 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cab5aece 3605 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
1a4f550a
NC		 3606 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3607 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
3608 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
1c57e86d
EC		 3609 " poll command abort successfully \n"
3610 , acb->host->host_no
3611 , ccb->pcmd->device->id
9cb78c16 3612 , (u32)ccb->pcmd->device->lun
1c57e86d
EC		 3613 , ccb);
3614 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 3615 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 3616 continue;
3617 }
1a4f550a
NC		 3618 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3619 " command done ccb = '0x%p'"
a1f6e021 3620 "ccboutstandingcount = %d \n"
1c57e86d
EC		 3621 , acb->host->host_no
3622 , ccb
3623 , atomic_read(&acb->ccboutstandingcount));
3624 continue;
cdd3cb15
NC		 3625 }
3626 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3627 arcmsr_report_ccb_state(acb, ccb, error);
1a4f550a 3628 }
ae52e7f0
NC		 3629 return rtn;
3630}
1a4f550a 3631
626fa32c 3632static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 3633 struct CommandControlBlock *poll_ccb)
3634{
cdd3cb15 3635 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 3636 struct ARCMSR_CDB *arcmsr_cdb;
cdd3cb15
NC		 3637 struct CommandControlBlock *ccb;
3638 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 3639 int index, rtn;
cdd3cb15 3640 bool error;
e66764f2 3641 unsigned long ccb_cdb_phy;
97b99127 3642
e66764f2 3643polling_hbb_ccb_retry:
cdd3cb15
NC		 3644 poll_count++;
3645 /* clear doorbell interrupt */
ae52e7f0 3646 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
cdd3cb15
NC		 3647 while(1){
3648 index = reg->doneq_index;
c10b1d54
CH		 3649 flag_ccb = reg->done_qbuffer[index];
3650 if (flag_ccb == 0) {
cdd3cb15 3651 if (poll_ccb_done){
ae52e7f0 3652 rtn = SUCCESS;
cdd3cb15
NC		 3653 break;
3654 }else {
3655 msleep(25);
3656 if (poll_count > 100){
ae52e7f0 3657 rtn = FAILED;
cdd3cb15 3658 break;
1c57e86d 3659 }
cdd3cb15 3660 goto polling_hbb_ccb_retry;
1a4f550a 3661 }
cdd3cb15 3662 }
c10b1d54 3663 reg->done_qbuffer[index] = 0;
cdd3cb15
NC		 3664 index++;
3665 /*if last index number set it to 0 */
3666 index %= ARCMSR_MAX_HBB_POSTQUEUE;
3667 reg->doneq_index = index;
3668 /* check if command done with no error*/
e66764f2
CH		 3669 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
3670 if (acb->cdb_phyadd_hipart)
3671 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
3672 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
ae52e7f0 3673 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cab5aece 3674 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
cdd3cb15
NC		 3675 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3676 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
ae52e7f0
NC		 3677 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3678 " poll command abort successfully \n"
cdd3cb15
NC		 3679 ,acb->host->host_no
3680 ,ccb->pcmd->device->id
9cb78c16 3681 ,(u32)ccb->pcmd->device->lun
cdd3cb15
NC		 3682 ,ccb);
3683 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 3684 arcmsr_ccb_complete(ccb);
cdd3cb15
NC		 3685 continue;
3686 }
3687 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3688 " command done ccb = '0x%p'"
3689 "ccboutstandingcount = %d \n"
3690 , acb->host->host_no
3691 , ccb
3692 , atomic_read(&acb->ccboutstandingcount));
3693 continue;
3694 }
3695 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3696 arcmsr_report_ccb_state(acb, ccb, error);
3697 }
3698 return rtn;
3699}
3700
626fa32c
CH		 3701static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
3702 struct CommandControlBlock *poll_ccb)
cdd3cb15 3703{
c10b1d54 3704 struct MessageUnit_C __iomem *reg = acb->pmuC;
c71ec551 3705 uint32_t flag_ccb;
cdd3cb15
NC		 3706 struct ARCMSR_CDB *arcmsr_cdb;
3707 bool error;
3708 struct CommandControlBlock *pCCB;
3709 uint32_t poll_ccb_done = 0, poll_count = 0;
3710 int rtn;
c71ec551
CH		 3711 unsigned long ccb_cdb_phy;
3712
cdd3cb15
NC		 3713polling_hbc_ccb_retry:
3714 poll_count++;
3715 while (1) {
3716 if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
3717 if (poll_ccb_done) {
3718 rtn = SUCCESS;
3719 break;
3720 } else {
3721 msleep(25);
3722 if (poll_count > 100) {
3723 rtn = FAILED;
3724 break;
1c57e86d 3725 }
cdd3cb15
NC		 3726 goto polling_hbc_ccb_retry;
3727 }
3728 }
3729 flag_ccb = readl(&reg->outbound_queueport_low);
3730 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
c71ec551
CH		 3731 if (acb->cdb_phyadd_hipart)
3732 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
3733 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
cdd3cb15 3734 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cab5aece 3735 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
cdd3cb15
NC		 3736 /* check ifcommand done with no error*/
3737 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3738 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3739 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3740 " poll command abort successfully \n"
1c57e86d 3741 , acb->host->host_no
cdd3cb15 3742 , pCCB->pcmd->device->id
9cb78c16 3743 , (u32)pCCB->pcmd->device->lun
cdd3cb15 3744 , pCCB);
9b44ffab
CIK		 3745 pCCB->pcmd->result = DID_ABORT << 16;
3746 arcmsr_ccb_complete(pCCB);
1a4f550a 3747 continue;
cdd3cb15
NC		 3748 }
3749 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3750 " command done ccb = '0x%p'"
3751 "ccboutstandingcount = %d \n"
3752 , acb->host->host_no
3753 , pCCB
3754 , atomic_read(&acb->ccboutstandingcount));
3755 continue;
ae52e7f0 3756 }
cdd3cb15
NC		 3757 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3758 arcmsr_report_ccb_state(acb, pCCB, error);
3759 }
ae52e7f0 3760 return rtn;
1a4f550a 3761}
5b37479a
CH		 3762
3763static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
3764 struct CommandControlBlock *poll_ccb)
3765{
3766 bool error;
a36ade41 3767 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb;
3b8155d5 3768 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
18bc435e 3769 unsigned long flags, ccb_cdb_phy;
5b37479a
CH		 3770 struct ARCMSR_CDB *arcmsr_cdb;
3771 struct CommandControlBlock *pCCB;
3772 struct MessageUnit_D *pmu = acb->pmuD;
3773
3774polling_hbaD_ccb_retry:
3775 poll_count++;
3776 while (1) {
3b8155d5 3777 spin_lock_irqsave(&acb->doneq_lock, flags);
5b37479a
CH		 3778 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
3779 doneq_index = pmu->doneq_index;
3780 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
3b8155d5 3781 spin_unlock_irqrestore(&acb->doneq_lock, flags);
5b37479a
CH		 3782 if (poll_ccb_done) {
3783 rtn = SUCCESS;
3784 break;
3785 } else {
3786 msleep(25);
3787 if (poll_count > 40) {
3788 rtn = FAILED;
3789 break;
3790 }
3791 goto polling_hbaD_ccb_retry;
3792 }
3793 }
3b8155d5
CH		 3794 toggle = doneq_index & 0x4000;
3795 index_stripped = (doneq_index & 0xFFF) + 1;
3796 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
3797 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
3798 ((toggle ^ 0x4000) + 1);
5b37479a 3799 doneq_index = pmu->doneq_index;
3b8155d5 3800 spin_unlock_irqrestore(&acb->doneq_lock, flags);
5b37479a
CH		 3801 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
3802 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
a36ade41
CH		 3803 if (acb->cdb_phyadd_hipart)
3804 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
5b37479a
CH		 3805 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
3806 ccb_cdb_phy);
3807 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
3808 arcmsr_cdb);
3809 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3810 if ((pCCB->acb != acb) ||
3811 (pCCB->startdone != ARCMSR_CCB_START)) {
3812 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3813 pr_notice("arcmsr%d: scsi id = %d "
3814 "lun = %d ccb = '0x%p' poll command "
3815 "abort successfully\n"
3816 , acb->host->host_no
3817 , pCCB->pcmd->device->id
3818 , (u32)pCCB->pcmd->device->lun
3819 , pCCB);
3820 pCCB->pcmd->result = DID_ABORT << 16;
3821 arcmsr_ccb_complete(pCCB);
3822 continue;
3823 }
3824 pr_notice("arcmsr%d: polling an illegal "
3825 "ccb command done ccb = '0x%p' "
3826 "ccboutstandingcount = %d\n"
3827 , acb->host->host_no
3828 , pCCB
3829 , atomic_read(&acb->ccboutstandingcount));
3830 continue;
3831 }
3832 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
3833 ? true : false;
3834 arcmsr_report_ccb_state(acb, pCCB, error);
3835 }
3836 return rtn;
3837}
3838
23509024
CH		 3839static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb,
3840 struct CommandControlBlock *poll_ccb)
3841{
3842 bool error;
3843 uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index;
3844 uint16_t cmdSMID;
3845 unsigned long flags;
3846 int rtn;
3847 struct CommandControlBlock *pCCB;
3848 struct MessageUnit_E __iomem *reg = acb->pmuE;
3849
3850 polling_hbaC_ccb_retry:
3851 poll_count++;
3852 while (1) {
3853 spin_lock_irqsave(&acb->doneq_lock, flags);
3854 doneq_index = acb->doneq_index;
3855 if ((readl(&reg->reply_post_producer_index) & 0xFFFF) ==
3856 doneq_index) {
3857 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3858 if (poll_ccb_done) {
3859 rtn = SUCCESS;
3860 break;
3861 } else {
3862 msleep(25);
3863 if (poll_count > 40) {
3864 rtn = FAILED;
3865 break;
3866 }
3867 goto polling_hbaC_ccb_retry;
3868 }
3869 }
3870 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3871 doneq_index++;
3872 if (doneq_index >= acb->completionQ_entry)
3873 doneq_index = 0;
3874 acb->doneq_index = doneq_index;
3875 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3876 pCCB = acb->pccb_pool[cmdSMID];
3877 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3878 /* check if command done with no error*/
3879 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3880 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3881 pr_notice("arcmsr%d: scsi id = %d "
3882 "lun = %d ccb = '0x%p' poll command "
3883 "abort successfully\n"
3884 , acb->host->host_no
3885 , pCCB->pcmd->device->id
3886 , (u32)pCCB->pcmd->device->lun
3887 , pCCB);
3888 pCCB->pcmd->result = DID_ABORT << 16;
3889 arcmsr_ccb_complete(pCCB);
3890 continue;
3891 }
3892 pr_notice("arcmsr%d: polling an illegal "
3893 "ccb command done ccb = '0x%p' "
3894 "ccboutstandingcount = %d\n"
3895 , acb->host->host_no
3896 , pCCB
3897 , atomic_read(&acb->ccboutstandingcount));
3898 continue;
3899 }
3900 error = (acb->pCompletionQ[doneq_index].cmdFlag &
3901 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3902 arcmsr_report_ccb_state(acb, pCCB, error);
3903 }
3904 writel(doneq_index, &reg->reply_post_consumer_index);
3905 return rtn;
3906}
3907
ae52e7f0 3908static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 3909 struct CommandControlBlock *poll_ccb)
3910{
ae52e7f0 3911 int rtn = 0;
1a4f550a
NC		 3912 switch (acb->adapter_type) {
3913
9aae1c1f 3914 case ACB_ADAPTER_TYPE_A:
626fa32c 3915 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
1a4f550a 3916 break;
9aae1c1f 3917 case ACB_ADAPTER_TYPE_B:
626fa32c 3918 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
cdd3cb15 3919 break;
9aae1c1f 3920 case ACB_ADAPTER_TYPE_C:
626fa32c 3921 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
5b37479a
CH		 3922 break;
3923 case ACB_ADAPTER_TYPE_D:
3924 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
3925 break;
23509024 3926 case ACB_ADAPTER_TYPE_E:
ae897ae2 3927 case ACB_ADAPTER_TYPE_F:
23509024
CH		 3928 rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb);
3929 break;
1c57e86d 3930 }
ae52e7f0 3931 return rtn;
1c57e86d 3932}
1a4f550a 3933
b416c099
CH		 3934static void arcmsr_set_iop_datetime(struct timer_list *t)
3935{
3936 struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer);
45596c78
AB		 3937 unsigned int next_time;
3938 struct tm tm;
3939
b416c099
CH		 3940 union {
3941 struct {
3942 uint16_t signature;
3943 uint8_t year;
3944 uint8_t month;
3945 uint8_t date;
3946 uint8_t hour;
3947 uint8_t minute;
3948 uint8_t second;
3949 } a;
3950 struct {
3951 uint32_t msg_time[2];
3952 } b;
3953 } datetime;
3954
45596c78 3955 time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm);
b416c099
CH		 3956
3957 datetime.a.signature = 0x55AA;
45596c78
AB		 3958 datetime.a.year = tm.tm_year - 100; /* base 2000 instead of 1900 */
3959 datetime.a.month = tm.tm_mon;
3960 datetime.a.date = tm.tm_mday;
3961 datetime.a.hour = tm.tm_hour;
3962 datetime.a.minute = tm.tm_min;
3963 datetime.a.second = tm.tm_sec;
b416c099
CH		 3964
3965 switch (pacb->adapter_type) {
3966 case ACB_ADAPTER_TYPE_A: {
3967 struct MessageUnit_A __iomem *reg = pacb->pmuA;
3968 writel(datetime.b.msg_time[0], &reg->message_rwbuffer[0]);
3969 writel(datetime.b.msg_time[1], &reg->message_rwbuffer[1]);
3970 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
3971 break;
3972 }
3973 case ACB_ADAPTER_TYPE_B: {
3974 uint32_t __iomem *rwbuffer;
3975 struct MessageUnit_B *reg = pacb->pmuB;
3976 rwbuffer = reg->message_rwbuffer;
3977 writel(datetime.b.msg_time[0], rwbuffer++);
3978 writel(datetime.b.msg_time[1], rwbuffer++);
3979 writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell);
3980 break;
3981 }
3982 case ACB_ADAPTER_TYPE_C: {
3983 struct MessageUnit_C __iomem *reg = pacb->pmuC;
3984 writel(datetime.b.msg_time[0], &reg->msgcode_rwbuffer[0]);
3985 writel(datetime.b.msg_time[1], &reg->msgcode_rwbuffer[1]);
3986 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
3987 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
3988 break;
3989 }
3990 case ACB_ADAPTER_TYPE_D: {
3991 uint32_t __iomem *rwbuffer;
3992 struct MessageUnit_D *reg = pacb->pmuD;
3993 rwbuffer = reg->msgcode_rwbuffer;
3994 writel(datetime.b.msg_time[0], rwbuffer++);
3995 writel(datetime.b.msg_time[1], rwbuffer++);
3996 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0);
3997 break;
3998 }
3999 case ACB_ADAPTER_TYPE_E: {
4000 struct MessageUnit_E __iomem *reg = pacb->pmuE;
4001 writel(datetime.b.msg_time[0], &reg->msgcode_rwbuffer[0]);
4002 writel(datetime.b.msg_time[1], &reg->msgcode_rwbuffer[1]);
4003 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
4004 pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4005 writel(pacb->out_doorbell, &reg->iobound_doorbell);
4006 break;
4007 }
ae897ae2
H		 4008 case ACB_ADAPTER_TYPE_F: {
4009 struct MessageUnit_F __iomem *reg = pacb->pmuF;
4010
4011 pacb->msgcode_rwbuffer[0] = datetime.b.msg_time[0];
4012 pacb->msgcode_rwbuffer[1] = datetime.b.msg_time[1];
4013 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
4014 pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4015 writel(pacb->out_doorbell, &reg->iobound_doorbell);
4016 break;
4017 }
b416c099
CH		 4018 }
4019 if (sys_tz.tz_minuteswest)
4020 next_time = ARCMSR_HOURS;
4021 else
4022 next_time = ARCMSR_MINUTES;
4023 mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time));
4024}
4025
1a4f550a 4026static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
a1f6e021 4027{
ae52e7f0 4028 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
6e38adfc 4029 dma_addr_t dma_coherent_handle;
e2c70425 4030
1a4f550a
NC		 4031 /*
4032 ********************************************************************
4033 ** here we need to tell iop 331 our freeccb.HighPart
4034 ** if freeccb.HighPart is not zero
4035 ********************************************************************
4036 */
6e38adfc
CH		 4037 switch (acb->adapter_type) {
4038 case ACB_ADAPTER_TYPE_B:
5b37479a 4039 case ACB_ADAPTER_TYPE_D:
6e38adfc
CH		 4040 dma_coherent_handle = acb->dma_coherent_handle2;
4041 break;
23509024 4042 case ACB_ADAPTER_TYPE_E:
ae897ae2 4043 case ACB_ADAPTER_TYPE_F:
23509024
CH		 4044 dma_coherent_handle = acb->dma_coherent_handle +
4045 offsetof(struct CommandControlBlock, arcmsr_cdb);
4046 break;
6e38adfc
CH		 4047 default:
4048 dma_coherent_handle = acb->dma_coherent_handle;
4049 break;
4050 }
4051 cdb_phyaddr = lower_32_bits(dma_coherent_handle);
4052 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
cdd3cb15 4053 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
7860a486 4054 acb->cdb_phyadd_hipart = ((uint64_t)cdb_phyaddr_hi32) << 32;
1a4f550a
NC		 4055 /*
4056 ***********************************************************************
4057 ** if adapter type B, set window of "post command Q"
4058 ***********************************************************************
4059 */
4060 switch (acb->adapter_type) {
4061
4062 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 4063 if (cdb_phyaddr_hi32 != 0) {
80da1adb 4064 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 4065 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
4066 &reg->message_rwbuffer[0]);
ae52e7f0 4067 writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
1a4f550a
NC		 4068 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
4069 &reg->inbound_msgaddr0);
626fa32c 4070 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a
NC		 4071 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
4072 part physical address timeout\n",
4073 acb->host->host_no);
4074 return 1;
a1f6e021 4075 }
1a4f550a
NC		 4076 }
4077 }
4078 break;
a1f6e021 4079
1a4f550a 4080 case ACB_ADAPTER_TYPE_B: {
80da1adb 4081 uint32_t __iomem *rwbuffer;
a1f6e021 4082
80da1adb 4083 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 4084 reg->postq_index = 0;
4085 reg->doneq_index = 0;
ae52e7f0 4086 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
626fa32c 4087 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
47268a4f 4088 printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \
1a4f550a
NC		 4089 acb->host->host_no);
4090 return 1;
4091 }
ae52e7f0 4092 rwbuffer = reg->message_rwbuffer;
1a4f550a
NC		 4093 /* driver "set config" signature */
4094 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
4095 /* normal should be zero */
ae52e7f0 4096 writel(cdb_phyaddr_hi32, rwbuffer++);
1a4f550a 4097 /* postQ size (256 + 8)*4 */
6e38adfc 4098 writel(cdb_phyaddr, rwbuffer++);
1a4f550a 4099 /* doneQ size (256 + 8)*4 */
6e38adfc 4100 writel(cdb_phyaddr + 1056, rwbuffer++);
1a4f550a
NC		 4101 /* ccb maxQ size must be --> [(256 + 8)*4]*/
4102 writel(1056, rwbuffer);
4103
ae52e7f0 4104 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
626fa32c 4105 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1a4f550a
NC		 4106 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
4107 timeout \n",acb->host->host_no);
4108 return 1;
4109 }
a5849726 4110 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
626fa32c 4111 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
a5849726
CH		 4112 pr_err("arcmsr%d: can't set driver mode.\n",
4113 acb->host->host_no);
4114 return 1;
4115 }
1a4f550a
NC		 4116 }
4117 break;
cdd3cb15 4118 case ACB_ADAPTER_TYPE_C: {
c10b1d54 4119 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15 4120
8b7eb86f
TH		 4121 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
4122 acb->adapter_index, cdb_phyaddr_hi32);
cdd3cb15
NC		 4123 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
4124 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
4125 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
4126 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
626fa32c 4127 if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
cdd3cb15
NC		 4128 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
4129 timeout \n", acb->host->host_no);
4130 return 1;
4131 }
4132 }
5b37479a
CH		 4133 break;
4134 case ACB_ADAPTER_TYPE_D: {
4135 uint32_t __iomem *rwbuffer;
4136 struct MessageUnit_D *reg = acb->pmuD;
4137 reg->postq_index = 0;
4138 reg->doneq_index = 0;
4139 rwbuffer = reg->msgcode_rwbuffer;
4140 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
4141 writel(cdb_phyaddr_hi32, rwbuffer++);
4142 writel(cdb_phyaddr, rwbuffer++);
4143 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
4144 sizeof(struct InBound_SRB)), rwbuffer++);
4145 writel(0x100, rwbuffer);
4146 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
4147 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
4148 pr_notice("arcmsr%d: 'set command Q window' timeout\n",
4149 acb->host->host_no);
4150 return 1;
4151 }
4152 }
4153 break;
23509024
CH		 4154 case ACB_ADAPTER_TYPE_E: {
4155 struct MessageUnit_E __iomem *reg = acb->pmuE;
4156 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
4157 writel(ARCMSR_SIGNATURE_1884, &reg->msgcode_rwbuffer[1]);
4158 writel(cdb_phyaddr, &reg->msgcode_rwbuffer[2]);
4159 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[3]);
4160 writel(acb->ccbsize, &reg->msgcode_rwbuffer[4]);
ae897ae2
H		 4161 writel(lower_32_bits(acb->dma_coherent_handle2), &reg->msgcode_rwbuffer[5]);
4162 writel(upper_32_bits(acb->dma_coherent_handle2), &reg->msgcode_rwbuffer[6]);
381d66da 4163 writel(acb->ioqueue_size, &reg->msgcode_rwbuffer[7]);
23509024
CH		 4164 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
4165 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4166 writel(acb->out_doorbell, &reg->iobound_doorbell);
4167 if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
4168 pr_notice("arcmsr%d: 'set command Q window' timeout \n",
4169 acb->host->host_no);
4170 return 1;
4171 }
4172 }
4173 break;
ae897ae2
H		 4174 case ACB_ADAPTER_TYPE_F: {
4175 struct MessageUnit_F __iomem *reg = acb->pmuF;
4176
4177 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG;
4178 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886;
4179 acb->msgcode_rwbuffer[2] = cdb_phyaddr;
4180 acb->msgcode_rwbuffer[3] = cdb_phyaddr_hi32;
4181 acb->msgcode_rwbuffer[4] = acb->ccbsize;
4182 acb->msgcode_rwbuffer[5] = lower_32_bits(acb->dma_coherent_handle2);
4183 acb->msgcode_rwbuffer[6] = upper_32_bits(acb->dma_coherent_handle2);
4184 acb->msgcode_rwbuffer[7] = acb->completeQ_size;
14ef4b00
H		 4185 if (acb->xor_mega) {
4186 acb->msgcode_rwbuffer[8] = 0x455AA; //Linux init 2
4187 acb->msgcode_rwbuffer[9] = 0;
4188 acb->msgcode_rwbuffer[10] = lower_32_bits(acb->xorPhys);
4189 acb->msgcode_rwbuffer[11] = upper_32_bits(acb->xorPhys);
4190 }
ae897ae2
H		 4191 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
4192 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4193 writel(acb->out_doorbell, &reg->iobound_doorbell);
4194 if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
4195 pr_notice("arcmsr%d: 'set command Q window' timeout\n",
4196 acb->host->host_no);
4197 return 1;
4198 }
4199 }
4200 break;
1a4f550a
NC		 4201 }
4202 return 0;
4203}
a1f6e021 4204
1a4f550a
NC		 4205static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
4206{
4207 uint32_t firmware_state = 0;
1a4f550a
NC		 4208 switch (acb->adapter_type) {
4209
4210 case ACB_ADAPTER_TYPE_A: {
80da1adb 4211 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 4212 do {
c2c62ebc
CH		 4213 if (!(acb->acb_flags & ACB_F_IOP_INITED))
4214 msleep(20);
1a4f550a
NC		 4215 firmware_state = readl(&reg->outbound_msgaddr1);
4216 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
4217 }
4218 break;
4219
4220 case ACB_ADAPTER_TYPE_B: {
80da1adb 4221 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 4222 do {
c2c62ebc
CH		 4223 if (!(acb->acb_flags & ACB_F_IOP_INITED))
4224 msleep(20);
ae52e7f0 4225 firmware_state = readl(reg->iop2drv_doorbell);
1a4f550a 4226 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
ae52e7f0 4227 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
1a4f550a
NC		 4228 }
4229 break;
cdd3cb15 4230 case ACB_ADAPTER_TYPE_C: {
c10b1d54 4231 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15 4232 do {
c2c62ebc
CH		 4233 if (!(acb->acb_flags & ACB_F_IOP_INITED))
4234 msleep(20);
cdd3cb15
NC		 4235 firmware_state = readl(&reg->outbound_msgaddr1);
4236 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
4237 }
5b37479a
CH		 4238 break;
4239 case ACB_ADAPTER_TYPE_D: {
4240 struct MessageUnit_D *reg = acb->pmuD;
4241 do {
c2c62ebc
CH		 4242 if (!(acb->acb_flags & ACB_F_IOP_INITED))
4243 msleep(20);
5b37479a
CH		 4244 firmware_state = readl(reg->outbound_msgaddr1);
4245 } while ((firmware_state &
4246 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
4247 }
4248 break;
ae897ae2
H		 4249 case ACB_ADAPTER_TYPE_E:
4250 case ACB_ADAPTER_TYPE_F: {
23509024
CH		 4251 struct MessageUnit_E __iomem *reg = acb->pmuE;
4252 do {
c2c62ebc
CH		 4253 if (!(acb->acb_flags & ACB_F_IOP_INITED))
4254 msleep(20);
23509024
CH		 4255 firmware_state = readl(&reg->outbound_msgaddr1);
4256 } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0);
4257 }
4258 break;
a1f6e021 4259 }
1a4f550a
NC		 4260}
4261
6ae9abe0 4262static void arcmsr_request_device_map(struct timer_list *t)
23509024 4263{
6ae9abe0 4264 struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer);
893f4a14
H		 4265 if (acb->acb_flags & (ACB_F_MSG_GET_CONFIG | ACB_F_BUS_RESET | ACB_F_ABORT)) {
4266 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
23509024
CH		 4267 } else {
4268 acb->fw_flag = FW_NORMAL;
6ae9abe0 4269 switch (acb->adapter_type) {
36b83ded 4270 case ACB_ADAPTER_TYPE_A: {
6ae9abe0
CH		 4271 struct MessageUnit_A __iomem *reg = acb->pmuA;
4272 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
4273 break;
4274 }
36b83ded 4275 case ACB_ADAPTER_TYPE_B: {
6ae9abe0
CH		 4276 struct MessageUnit_B *reg = acb->pmuB;
4277 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
4278 break;
4279 }
cdd3cb15 4280 case ACB_ADAPTER_TYPE_C: {
6ae9abe0
CH		 4281 struct MessageUnit_C __iomem *reg = acb->pmuC;
4282 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
4283 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
4284 break;
4285 }
4286 case ACB_ADAPTER_TYPE_D: {
4287 struct MessageUnit_D *reg = acb->pmuD;
4288 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
4289 break;
4290 }
4291 case ACB_ADAPTER_TYPE_E: {
4292 struct MessageUnit_E __iomem *reg = acb->pmuE;
4293 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
4294 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4295 writel(acb->out_doorbell, &reg->iobound_doorbell);
4296 break;
4297 }
ae897ae2
H		 4298 case ACB_ADAPTER_TYPE_F: {
4299 struct MessageUnit_F __iomem *reg = acb->pmuF;
4300 uint32_t outMsg1 = readl(&reg->outbound_msgaddr1);
4301
4302 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) ||
4303 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE))
4304 goto nxt6s;
4305 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
4306 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4307 writel(acb->out_doorbell, &reg->iobound_doorbell);
4308 break;
4309 }
6ae9abe0
CH		 4310 default:
4311 return;
cdd3cb15 4312 }
6ae9abe0 4313 acb->acb_flags |= ACB_F_MSG_GET_CONFIG;
ae897ae2 4314nxt6s:
6ae9abe0 4315 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded
NC		 4316 }
4317}
4318
626fa32c 4319static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
1a4f550a 4320{
80da1adb 4321 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 4322 acb->acb_flags |= ACB_F_MSG_START_BGRB;
4323 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
626fa32c 4324 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a 4325 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
948dff7a 4326 rebuild' timeout \n", acb->host->host_no);
a1f6e021 4327 }
a1f6e021 4328}
4329
626fa32c 4330static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
1a4f550a 4331{
80da1adb 4332 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 4333 acb->acb_flags |= ACB_F_MSG_START_BGRB;
ae52e7f0 4334 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
626fa32c 4335 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1a4f550a 4336 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
948dff7a 4337 rebuild' timeout \n",acb->host->host_no);
1a4f550a
NC		 4338 }
4339}
1c57e86d 4340
626fa32c 4341static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
cdd3cb15 4342{
c10b1d54 4343 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
cdd3cb15
NC		 4344 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
4345 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
4346 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
626fa32c 4347 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15 4348 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
948dff7a 4349 rebuild' timeout \n", pACB->host->host_no);
cdd3cb15
NC		 4350 }
4351 return;
4352}
5b37479a
CH		 4353
4354static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
4355{
4356 struct MessageUnit_D *pmu = pACB->pmuD;
4357
4358 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
4359 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
4360 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
4361 pr_notice("arcmsr%d: wait 'start adapter "
948dff7a 4362 "background rebuild' timeout\n", pACB->host->host_no);
5b37479a
CH		 4363 }
4364}
4365
23509024
CH		 4366static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB)
4367{
4368 struct MessageUnit_E __iomem *pmu = pACB->pmuE;
4369
4370 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
4371 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0);
4372 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4373 writel(pACB->out_doorbell, &pmu->iobound_doorbell);
4374 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
4375 pr_notice("arcmsr%d: wait 'start adapter "
948dff7a 4376 "background rebuild' timeout \n", pACB->host->host_no);
23509024
CH		 4377 }
4378}
4379
1a4f550a 4380static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
1c57e86d 4381{
1a4f550a
NC		 4382 switch (acb->adapter_type) {
4383 case ACB_ADAPTER_TYPE_A:
626fa32c 4384 arcmsr_hbaA_start_bgrb(acb);
1a4f550a
NC		 4385 break;
4386 case ACB_ADAPTER_TYPE_B:
626fa32c 4387 arcmsr_hbaB_start_bgrb(acb);
1a4f550a 4388 break;
cdd3cb15 4389 case ACB_ADAPTER_TYPE_C:
626fa32c 4390 arcmsr_hbaC_start_bgrb(acb);
5b37479a
CH		 4391 break;
4392 case ACB_ADAPTER_TYPE_D:
4393 arcmsr_hbaD_start_bgrb(acb);
4394 break;
23509024 4395 case ACB_ADAPTER_TYPE_E:
ae897ae2 4396 case ACB_ADAPTER_TYPE_F:
23509024
CH		 4397 arcmsr_hbaE_start_bgrb(acb);
4398 break;
1a4f550a
NC		 4399 }
4400}
1c57e86d 4401
1a4f550a
NC		 4402static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
4403{
4404 switch (acb->adapter_type) {
4405 case ACB_ADAPTER_TYPE_A: {
80da1adb 4406 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 4407 uint32_t outbound_doorbell;
4408 /* empty doorbell Qbuffer if door bell ringed */
4409 outbound_doorbell = readl(&reg->outbound_doorbell);
4410 /*clear doorbell interrupt */
4411 writel(outbound_doorbell, &reg->outbound_doorbell);
4412 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
4413 }
4414 break;
1c57e86d 4415
1a4f550a 4416 case ACB_ADAPTER_TYPE_B: {
80da1adb 4417 struct MessageUnit_B *reg = acb->pmuB;
2124c5b2
CH		 4418 uint32_t outbound_doorbell, i;
4419 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
ae52e7f0 4420 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1a4f550a 4421 /* let IOP know data has been read */
2124c5b2
CH		 4422 for(i=0; i < 200; i++) {
4423 msleep(20);
4424 outbound_doorbell = readl(reg->iop2drv_doorbell);
4425 if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
4426 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
4427 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
4428 } else
4429 break;
4430 }
1a4f550a
NC		 4431 }
4432 break;
cdd3cb15 4433 case ACB_ADAPTER_TYPE_C: {
c10b1d54 4434 struct MessageUnit_C __iomem *reg = acb->pmuC;
5eb6bfa0 4435 uint32_t outbound_doorbell, i;
cdd3cb15
NC		 4436 /* empty doorbell Qbuffer if door bell ringed */
4437 outbound_doorbell = readl(&reg->outbound_doorbell);
4438 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
4439 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
5eb6bfa0
CH		 4440 for (i = 0; i < 200; i++) {
4441 msleep(20);
4442 outbound_doorbell = readl(&reg->outbound_doorbell);
4443 if (outbound_doorbell &
4444 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
4445 writel(outbound_doorbell,
4446 &reg->outbound_doorbell_clear);
4447 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
4448 &reg->inbound_doorbell);
4449 } else
4450 break;
4451 }
cdd3cb15 4452 }
5b37479a
CH		 4453 break;
4454 case ACB_ADAPTER_TYPE_D: {
4455 struct MessageUnit_D *reg = acb->pmuD;
4456 uint32_t outbound_doorbell, i;
4457 /* empty doorbell Qbuffer if door bell ringed */
4458 outbound_doorbell = readl(reg->outbound_doorbell);
4459 writel(outbound_doorbell, reg->outbound_doorbell);
4460 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
4461 reg->inbound_doorbell);
4462 for (i = 0; i < 200; i++) {
4463 msleep(20);
4464 outbound_doorbell = readl(reg->outbound_doorbell);
4465 if (outbound_doorbell &
4466 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
4467 writel(outbound_doorbell,
4468 reg->outbound_doorbell);
4469 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
4470 reg->inbound_doorbell);
4471 } else
4472 break;
4473 }
4474 }
4475 break;
ae897ae2
H		 4476 case ACB_ADAPTER_TYPE_E:
4477 case ACB_ADAPTER_TYPE_F: {
23509024
CH		 4478 struct MessageUnit_E __iomem *reg = acb->pmuE;
4479 uint32_t i, tmp;
4480
4481 acb->in_doorbell = readl(&reg->iobound_doorbell);
4482 writel(0, &reg->host_int_status); /*clear interrupt*/
4483 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4484 writel(acb->out_doorbell, &reg->iobound_doorbell);
4485 for(i=0; i < 200; i++) {
4486 msleep(20);
4487 tmp = acb->in_doorbell;
4488 acb->in_doorbell = readl(&reg->iobound_doorbell);
4489 if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
4490 writel(0, &reg->host_int_status); /*clear interrupt*/
4491 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4492 writel(acb->out_doorbell, &reg->iobound_doorbell);
4493 } else
4494 break;
4495 }
4496 }
4497 break;
1c57e86d 4498 }
1a4f550a 4499}
1c57e86d 4500
76d78300
NC		 4501static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
4502{
4503 switch (acb->adapter_type) {
4504 case ACB_ADAPTER_TYPE_A:
4505 return;
4506 case ACB_ADAPTER_TYPE_B:
4507 {
4508 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 4509 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
626fa32c 4510 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
76d78300
NC		 4511 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
4512 return;
4513 }
4514 }
4515 break;
cdd3cb15
NC		 4516 case ACB_ADAPTER_TYPE_C:
4517 return;
76d78300
NC		 4518 }
4519 return;
4520}
4521
36b83ded
NC		 4522static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
4523{
4524 uint8_t value[64];
cdd3cb15
NC		 4525 int i, count = 0;
4526 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
4527 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
5b37479a 4528 struct MessageUnit_D *pmuD = acb->pmuD;
6ad819b0 4529
36b83ded 4530 /* backup pci config data */
cdd3cb15 4531 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
36b83ded
NC		 4532 for (i = 0; i < 64; i++) {
4533 pci_read_config_byte(acb->pdev, i, &value[i]);
4534 }
4535 /* hardware reset signal */
ca2ade24 4536 if (acb->dev_id == 0x1680) {
cdd3cb15 4537 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
ca2ade24 4538 } else if (acb->dev_id == 0x1880) {
cdd3cb15
NC		 4539 do {
4540 count++;
4541 writel(0xF, &pmuC->write_sequence);
4542 writel(0x4, &pmuC->write_sequence);
4543 writel(0xB, &pmuC->write_sequence);
4544 writel(0x2, &pmuC->write_sequence);
4545 writel(0x7, &pmuC->write_sequence);
4546 writel(0xD, &pmuC->write_sequence);
6ad819b0 4547 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
cdd3cb15 4548 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
23509024
CH		 4549 } else if (acb->dev_id == 0x1884) {
4550 struct MessageUnit_E __iomem *pmuE = acb->pmuE;
4551 do {
4552 count++;
4553 writel(0x4, &pmuE->write_sequence_3xxx);
4554 writel(0xB, &pmuE->write_sequence_3xxx);
4555 writel(0x2, &pmuE->write_sequence_3xxx);
4556 writel(0x7, &pmuE->write_sequence_3xxx);
4557 writel(0xD, &pmuE->write_sequence_3xxx);
4558 mdelay(10);
4559 } while (((readl(&pmuE->host_diagnostic_3xxx) &
4560 ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5));
4561 writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx);
ca2ade24 4562 } else if (acb->dev_id == 0x1214) {
5b37479a 4563 writel(0x20, pmuD->reset_request);
ae52e7f0 4564 } else {
cdd3cb15 4565 pci_write_config_byte(acb->pdev, 0x84, 0x20);
ae52e7f0 4566 }
cdd3cb15 4567 msleep(2000);
36b83ded
NC		 4568 /* write back pci config data */
4569 for (i = 0; i < 64; i++) {
4570 pci_write_config_byte(acb->pdev, i, value[i]);
4571 }
4572 msleep(1000);
4573 return;
4574}
72a7f313
CH		 4575
4576static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb)
4577{
4578 bool rtn = true;
4579
4580 switch(acb->adapter_type) {
4581 case ACB_ADAPTER_TYPE_A:{
4582 struct MessageUnit_A __iomem *reg = acb->pmuA;
4583 rtn = ((readl(&reg->outbound_msgaddr1) &
4584 ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false;
4585 }
4586 break;
4587 case ACB_ADAPTER_TYPE_B:{
4588 struct MessageUnit_B *reg = acb->pmuB;
4589 rtn = ((readl(reg->iop2drv_doorbell) &
4590 ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false;
4591 }
4592 break;
4593 case ACB_ADAPTER_TYPE_C:{
4594 struct MessageUnit_C __iomem *reg = acb->pmuC;
4595 rtn = (readl(&reg->host_diagnostic) & 0x04) ? true : false;
4596 }
4597 break;
4598 case ACB_ADAPTER_TYPE_D:{
4599 struct MessageUnit_D *reg = acb->pmuD;
4600 rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ?
4601 true : false;
4602 }
4603 break;
ae897ae2
H		 4604 case ACB_ADAPTER_TYPE_E:
4605 case ACB_ADAPTER_TYPE_F:{
23509024
CH		 4606 struct MessageUnit_E __iomem *reg = acb->pmuE;
4607 rtn = (readl(&reg->host_diagnostic_3xxx) &
4608 ARCMSR_ARC188X_RESET_ADAPTER) ? true : false;
4609 }
4610 break;
72a7f313
CH		 4611 }
4612 return rtn;
4613}
4614
1a4f550a
NC		 4615static void arcmsr_iop_init(struct AdapterControlBlock *acb)
4616{
4617 uint32_t intmask_org;
cdd3cb15
NC		 4618 /* disable all outbound interrupt */
4619 intmask_org = arcmsr_disable_outbound_ints(acb);
76d78300
NC		 4620 arcmsr_wait_firmware_ready(acb);
4621 arcmsr_iop_confirm(acb);
1a4f550a
NC		 4622 /*start background rebuild*/
4623 arcmsr_start_adapter_bgrb(acb);
4624 /* empty doorbell Qbuffer if door bell ringed */
4625 arcmsr_clear_doorbell_queue_buffer(acb);
76d78300 4626 arcmsr_enable_eoi_mode(acb);
1a4f550a
NC		 4627 /* enable outbound Post Queue,outbound doorbell Interrupt */
4628 arcmsr_enable_outbound_ints(acb, intmask_org);
1c57e86d
EC		 4629 acb->acb_flags |= ACB_F_IOP_INITED;
4630}
4631
36b83ded 4632static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
1c57e86d 4633{
1c57e86d
EC		 4634 struct CommandControlBlock *ccb;
4635 uint32_t intmask_org;
36b83ded 4636 uint8_t rtnval = 0x00;
1c57e86d 4637 int i = 0;
97b99127
N		 4638 unsigned long flags;
4639
1c57e86d 4640 if (atomic_read(&acb->ccboutstandingcount) != 0) {
36b83ded
NC		 4641 /* disable all outbound interrupt */
4642 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d 4643 /* talk to iop 331 outstanding command aborted */
36b83ded 4644 rtnval = arcmsr_abort_allcmd(acb);
1c57e86d 4645 /* clear all outbound posted Q */
1a4f550a 4646 arcmsr_done4abort_postqueue(acb);
d076e4aa 4647 for (i = 0; i < acb->maxFreeCCB; i++) {
1c57e86d 4648 ccb = acb->pccb_pool[i];
a1f6e021 4649 if (ccb->startdone == ARCMSR_CCB_START) {
97b99127
N		 4650 scsi_dma_unmap(ccb->pcmd);
4651 ccb->startdone = ARCMSR_CCB_DONE;
4652 ccb->ccb_flags = 0;
4653 spin_lock_irqsave(&acb->ccblist_lock, flags);
4654 list_add_tail(&ccb->list, &acb->ccb_free_list);
4655 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 4656 }
4657 }
36b83ded 4658 atomic_set(&acb->ccboutstandingcount, 0);
1c57e86d
EC		 4659 /* enable all outbound interrupt */
4660 arcmsr_enable_outbound_ints(acb, intmask_org);
36b83ded 4661 return rtnval;
1c57e86d 4662 }
36b83ded 4663 return rtnval;
1c57e86d
EC		 4664}
4665
4666static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
4667{
97b99127 4668 struct AdapterControlBlock *acb;
ae52e7f0
NC		 4669 int retry_count = 0;
4670 int rtn = FAILED;
ae52e7f0 4671 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
c4c1adb3
CH		 4672 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
4673 return SUCCESS;
72a7f313
CH		 4674 pr_notice("arcmsr: executing bus reset eh.....num_resets = %d,"
4675 " num_aborts = %d \n", acb->num_resets, acb->num_aborts);
36b83ded 4676 acb->num_resets++;
36b83ded 4677
72a7f313
CH		 4678 if (acb->acb_flags & ACB_F_BUS_RESET) {
4679 long timeout;
852c3f32 4680 pr_notice("arcmsr: there is a bus reset eh proceeding...\n");
72a7f313
CH		 4681 timeout = wait_event_timeout(wait_q, (acb->acb_flags
4682 & ACB_F_BUS_RESET) == 0, 220 * HZ);
4683 if (timeout)
4684 return SUCCESS;
4685 }
4686 acb->acb_flags |= ACB_F_BUS_RESET;
4687 if (!arcmsr_iop_reset(acb)) {
4688 arcmsr_hardware_reset(acb);
4689 acb->acb_flags &= ~ACB_F_IOP_INITED;
4690wait_reset_done:
4691 ssleep(ARCMSR_SLEEPTIME);
4692 if (arcmsr_reset_in_progress(acb)) {
4693 if (retry_count > ARCMSR_RETRYCOUNT) {
4694 acb->fw_flag = FW_DEADLOCK;
4695 pr_notice("arcmsr%d: waiting for hw bus reset"
4696 " return, RETRY TERMINATED!!\n",
4697 acb->host->host_no);
4698 return FAILED;
cdd3cb15 4699 }
72a7f313
CH		 4700 retry_count++;
4701 goto wait_reset_done;
5b37479a 4702 }
72a7f313 4703 arcmsr_iop_init(acb);
72a7f313
CH		 4704 acb->fw_flag = FW_NORMAL;
4705 mod_timer(&acb->eternal_timer, jiffies +
4706 msecs_to_jiffies(6 * HZ));
4707 acb->acb_flags &= ~ACB_F_BUS_RESET;
4708 rtn = SUCCESS;
4709 pr_notice("arcmsr: scsi bus reset eh returns with success\n");
4710 } else {
4711 acb->acb_flags &= ~ACB_F_BUS_RESET;
72a7f313
CH		 4712 acb->fw_flag = FW_NORMAL;
4713 mod_timer(&acb->eternal_timer, jiffies +
4714 msecs_to_jiffies(6 * HZ));
4715 rtn = SUCCESS;
ae52e7f0
NC		 4716 }
4717 return rtn;
1c57e86d
EC		 4718}
4719
ae52e7f0 4720static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
1c57e86d
EC		 4721 struct CommandControlBlock *ccb)
4722{
ae52e7f0 4723 int rtn;
ae52e7f0 4724 rtn = arcmsr_polling_ccbdone(acb, ccb);
ae52e7f0 4725 return rtn;
1c57e86d
EC		 4726}
4727
4728static int arcmsr_abort(struct scsi_cmnd *cmd)
4729{
4730 struct AdapterControlBlock *acb =
4731 (struct AdapterControlBlock *)cmd->device->host->hostdata;
4732 int i = 0;
ae52e7f0 4733 int rtn = FAILED;
cab5aece
CH		 4734 uint32_t intmask_org;
4735
c4c1adb3
CH		 4736 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
4737 return SUCCESS;
1c57e86d 4738 printk(KERN_NOTICE
cab5aece 4739 "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
9cb78c16 4740 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
ae52e7f0 4741 acb->acb_flags |= ACB_F_ABORT;
1c57e86d 4742 acb->num_aborts++;
1c57e86d
EC		 4743 /*
4744 ************************************************
4745 ** the all interrupt service routine is locked
4746 ** we need to handle it as soon as possible and exit
4747 ************************************************
4748 */
cab5aece
CH		 4749 if (!atomic_read(&acb->ccboutstandingcount)) {
4750 acb->acb_flags &= ~ACB_F_ABORT;
ae52e7f0 4751 return rtn;
cab5aece 4752 }
1c57e86d 4753
cab5aece 4754 intmask_org = arcmsr_disable_outbound_ints(acb);
d076e4aa 4755 for (i = 0; i < acb->maxFreeCCB; i++) {
1c57e86d
EC		 4756 struct CommandControlBlock *ccb = acb->pccb_pool[i];
4757 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
ae52e7f0
NC		 4758 ccb->startdone = ARCMSR_CCB_ABORTED;
4759 rtn = arcmsr_abort_one_cmd(acb, ccb);
1c57e86d
EC		 4760 break;
4761 }
4762 }
ae52e7f0 4763 acb->acb_flags &= ~ACB_F_ABORT;
cab5aece 4764 arcmsr_enable_outbound_ints(acb, intmask_org);
ae52e7f0 4765 return rtn;
1c57e86d
EC		 4766}
4767
4768static const char *arcmsr_info(struct Scsi_Host *host)
4769{
4770 struct AdapterControlBlock *acb =
4771 (struct AdapterControlBlock *) host->hostdata;
4772 static char buf[256];
4773 char *type;
4774 int raid6 = 1;
1c57e86d
EC		 4775 switch (acb->pdev->device) {
4776 case PCI_DEVICE_ID_ARECA_1110:
1a4f550a
NC		 4777 case PCI_DEVICE_ID_ARECA_1200:
4778 case PCI_DEVICE_ID_ARECA_1202:
1c57e86d
EC		 4779 case PCI_DEVICE_ID_ARECA_1210:
4780 raid6 = 0;
df561f66 4781 fallthrough;
1c57e86d
EC		 4782 case PCI_DEVICE_ID_ARECA_1120:
4783 case PCI_DEVICE_ID_ARECA_1130:
4784 case PCI_DEVICE_ID_ARECA_1160:
4785 case PCI_DEVICE_ID_ARECA_1170:
1a4f550a 4786 case PCI_DEVICE_ID_ARECA_1201:
7e315ffd 4787 case PCI_DEVICE_ID_ARECA_1203:
1c57e86d
EC		 4788 case PCI_DEVICE_ID_ARECA_1220:
4789 case PCI_DEVICE_ID_ARECA_1230:
4790 case PCI_DEVICE_ID_ARECA_1260:
4791 case PCI_DEVICE_ID_ARECA_1270:
4792 case PCI_DEVICE_ID_ARECA_1280:
4793 type = "SATA";
4794 break;
5b37479a 4795 case PCI_DEVICE_ID_ARECA_1214:
1c57e86d
EC		 4796 case PCI_DEVICE_ID_ARECA_1380:
4797 case PCI_DEVICE_ID_ARECA_1381:
4798 case PCI_DEVICE_ID_ARECA_1680:
4799 case PCI_DEVICE_ID_ARECA_1681:
cdd3cb15 4800 case PCI_DEVICE_ID_ARECA_1880:
41c8a1a1 4801 case PCI_DEVICE_ID_ARECA_1883:
23509024 4802 case PCI_DEVICE_ID_ARECA_1884:
aaa64f69 4803 type = "SAS/SATA";
1c57e86d 4804 break;
41c8a1a1 4805 case PCI_DEVICE_ID_ARECA_1886_0:
ae897ae2
H		 4806 case PCI_DEVICE_ID_ARECA_1886:
4807 type = "NVMe/SAS/SATA";
4808 break;
1c57e86d 4809 default:
aaa64f69
CH		 4810 type = "unknown";
4811 raid6 = 0;
1c57e86d
EC		 4812 break;
4813 }
aaa64f69
CH		 4814 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
4815 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
1c57e86d
EC		 4816 return buf;
4817}
Linux 6.x block layer and io_uring tree(s)