projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
advansys: Remove CC_VERY_LONG_SG_LIST
[linux-2.6-block.git] / drivers / scsi / advansys.c
CommitLineData
01fbfe0b 1#define DRV_NAME "advansys"
8c6af9e1 2#define ASC_VERSION "3.4" /* AdvanSys Driver Version */
1da177e4
LT		 3
4/*
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 *
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
8c6af9e1 9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
1da177e4
LT		 10 * All Rights Reserved.
11 *
8c6af9e1
MW		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/*
1da177e4
LT		 19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
8c6af9e1 21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
1da177e4
LT		 22 */
23
1da177e4 24#include <linux/module.h>
1da177e4
LT		 25#include <linux/string.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/ioport.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <linux/slab.h>
32#include <linux/mm.h>
33#include <linux/proc_fs.h>
34#include <linux/init.h>
35#include <linux/blkdev.h>
c304ec94 36#include <linux/isa.h>
b09e05a7 37#include <linux/eisa.h>
8c6af9e1 38#include <linux/pci.h>
1da177e4
LT		 39#include <linux/spinlock.h>
40#include <linux/dma-mapping.h>
989bb5f5 41#include <linux/firmware.h>
1da177e4
LT		 42
43#include <asm/io.h>
1da177e4
LT		 44#include <asm/dma.h>
45
8c6af9e1
MW		 46#include <scsi/scsi_cmnd.h>
47#include <scsi/scsi_device.h>
48#include <scsi/scsi_tcq.h>
49#include <scsi/scsi.h>
50#include <scsi/scsi_host.h>
51
4bd6d7f3 52/* FIXME:
1da177e4 53 *
4bd6d7f3
MW		 54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
61 * safely?
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
349d2c44
MW		 67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
9d0e96eb 69 * 8. Add module_param to override ISA/VLB ioport array
1da177e4
LT		 70 */
71#warning this driver is still not properly converted to the DMA API
72
1da177e4
LT		 73/* Enable driver /proc statistics. */
74#define ADVANSYS_STATS
75
76/* Enable driver tracing. */
b352f923 77#undef ADVANSYS_DEBUG
1da177e4 78
1da177e4
LT		 79typedef unsigned char uchar;
80
1da177e4 81#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
1da177e4 82
2672ea86
DJ		 83#define PCI_VENDOR_ID_ASP 0x10cd
84#define PCI_DEVICE_ID_ASP_1200A 0x1100
85#define PCI_DEVICE_ID_ASP_ABP940 0x1200
86#define PCI_DEVICE_ID_ASP_ABP940U 0x1300
87#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
88#define PCI_DEVICE_ID_38C0800_REV1 0x2500
89#define PCI_DEVICE_ID_38C1600_REV1 0x2700
90
9d511a4b 91#define PortAddr unsigned int /* port address size */
1da177e4
LT		 92#define inp(port) inb(port)
93#define outp(port, byte) outb((byte), (port))
94
95#define inpw(port) inw(port)
96#define outpw(port, word) outw((word), (port))
97
98#define ASC_MAX_SG_QUEUE 7
99#define ASC_MAX_SG_LIST 255
100
101#define ASC_CS_TYPE unsigned short
102
103#define ASC_IS_ISA (0x0001)
104#define ASC_IS_ISAPNP (0x0081)
105#define ASC_IS_EISA (0x0002)
106#define ASC_IS_PCI (0x0004)
107#define ASC_IS_PCI_ULTRA (0x0104)
108#define ASC_IS_PCMCIA (0x0008)
109#define ASC_IS_MCA (0x0020)
110#define ASC_IS_VL (0x0040)
1da177e4
LT		 111#define ASC_IS_WIDESCSI_16 (0x0100)
112#define ASC_IS_WIDESCSI_32 (0x0200)
113#define ASC_IS_BIG_ENDIAN (0x8000)
95c9f162 114
1da177e4
LT		 115#define ASC_CHIP_MIN_VER_VL (0x01)
116#define ASC_CHIP_MAX_VER_VL (0x07)
117#define ASC_CHIP_MIN_VER_PCI (0x09)
118#define ASC_CHIP_MAX_VER_PCI (0x0F)
119#define ASC_CHIP_VER_PCI_BIT (0x08)
120#define ASC_CHIP_MIN_VER_ISA (0x11)
121#define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
122#define ASC_CHIP_MAX_VER_ISA (0x27)
123#define ASC_CHIP_VER_ISA_BIT (0x30)
124#define ASC_CHIP_VER_ISAPNP_BIT (0x20)
125#define ASC_CHIP_VER_ASYN_BUG (0x21)
126#define ASC_CHIP_VER_PCI 0x08
127#define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
128#define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
129#define ASC_CHIP_MIN_VER_EISA (0x41)
130#define ASC_CHIP_MAX_VER_EISA (0x47)
131#define ASC_CHIP_VER_EISA_BIT (0x40)
132#define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
1da177e4 133#define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
1da177e4 134#define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
1da177e4 135#define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
1da177e4
LT		 136
137#define ASC_SCSI_ID_BITS 3
138#define ASC_SCSI_TIX_TYPE uchar
139#define ASC_ALL_DEVICE_BIT_SET 0xFF
140#define ASC_SCSI_BIT_ID_TYPE uchar
141#define ASC_MAX_TID 7
142#define ASC_MAX_LUN 7
143#define ASC_SCSI_WIDTH_BIT_SET 0xFF
144#define ASC_MAX_SENSE_LEN 32
145#define ASC_MIN_SENSE_LEN 14
1da177e4
LT		 146#define ASC_SCSI_RESET_HOLD_TIME_US 60
147
f05ec594
MW		 148/*
149 * Narrow boards only support 12-byte commands, while wide boards
150 * extend to 16-byte commands.
151 */
152#define ASC_MAX_CDB_LEN 12
153#define ADV_MAX_CDB_LEN 16
154
1da177e4 155#define MS_SDTR_LEN 0x03
1da177e4 156#define MS_WDTR_LEN 0x02
1da177e4
LT		 157
158#define ASC_SG_LIST_PER_Q 7
159#define QS_FREE 0x00
160#define QS_READY 0x01
161#define QS_DISC1 0x02
162#define QS_DISC2 0x04
163#define QS_BUSY 0x08
164#define QS_ABORTED 0x40
165#define QS_DONE 0x80
166#define QC_NO_CALLBACK 0x01
167#define QC_SG_SWAP_QUEUE 0x02
168#define QC_SG_HEAD 0x04
169#define QC_DATA_IN 0x08
170#define QC_DATA_OUT 0x10
171#define QC_URGENT 0x20
172#define QC_MSG_OUT 0x40
173#define QC_REQ_SENSE 0x80
174#define QCSG_SG_XFER_LIST 0x02
175#define QCSG_SG_XFER_MORE 0x04
176#define QCSG_SG_XFER_END 0x08
177#define QD_IN_PROGRESS 0x00
178#define QD_NO_ERROR 0x01
179#define QD_ABORTED_BY_HOST 0x02
180#define QD_WITH_ERROR 0x04
181#define QD_INVALID_REQUEST 0x80
182#define QD_INVALID_HOST_NUM 0x81
183#define QD_INVALID_DEVICE 0x82
184#define QD_ERR_INTERNAL 0xFF
185#define QHSTA_NO_ERROR 0x00
186#define QHSTA_M_SEL_TIMEOUT 0x11
187#define QHSTA_M_DATA_OVER_RUN 0x12
188#define QHSTA_M_DATA_UNDER_RUN 0x12
189#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
190#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
191#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
192#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
193#define QHSTA_D_HOST_ABORT_FAILED 0x23
194#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
195#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
196#define QHSTA_D_ASPI_NO_BUF_POOL 0x26
197#define QHSTA_M_WTM_TIMEOUT 0x41
198#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
199#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
200#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
201#define QHSTA_M_TARGET_STATUS_BUSY 0x45
202#define QHSTA_M_BAD_TAG_CODE 0x46
203#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
204#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
205#define QHSTA_D_LRAM_CMP_ERROR 0x81
206#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
207#define ASC_FLAG_SCSIQ_REQ 0x01
208#define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
209#define ASC_FLAG_BIOS_ASYNC_IO 0x04
210#define ASC_FLAG_SRB_LINEAR_ADDR 0x08
211#define ASC_FLAG_WIN16 0x10
212#define ASC_FLAG_WIN32 0x20
213#define ASC_FLAG_ISA_OVER_16MB 0x40
214#define ASC_FLAG_DOS_VM_CALLBACK 0x80
215#define ASC_TAG_FLAG_EXTRA_BYTES 0x10
216#define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
217#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
218#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
219#define ASC_SCSIQ_CPY_BEG 4
220#define ASC_SCSIQ_SGHD_CPY_BEG 2
221#define ASC_SCSIQ_B_FWD 0
222#define ASC_SCSIQ_B_BWD 1
223#define ASC_SCSIQ_B_STATUS 2
224#define ASC_SCSIQ_B_QNO 3
225#define ASC_SCSIQ_B_CNTL 4
226#define ASC_SCSIQ_B_SG_QUEUE_CNT 5
227#define ASC_SCSIQ_D_DATA_ADDR 8
228#define ASC_SCSIQ_D_DATA_CNT 12
229#define ASC_SCSIQ_B_SENSE_LEN 20
230#define ASC_SCSIQ_DONE_INFO_BEG 22
231#define ASC_SCSIQ_D_SRBPTR 22
232#define ASC_SCSIQ_B_TARGET_IX 26
233#define ASC_SCSIQ_B_CDB_LEN 28
234#define ASC_SCSIQ_B_TAG_CODE 29
235#define ASC_SCSIQ_W_VM_ID 30
236#define ASC_SCSIQ_DONE_STATUS 32
237#define ASC_SCSIQ_HOST_STATUS 33
238#define ASC_SCSIQ_SCSI_STATUS 34
239#define ASC_SCSIQ_CDB_BEG 36
240#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
241#define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
242#define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
243#define ASC_SCSIQ_B_SG_WK_QP 49
244#define ASC_SCSIQ_B_SG_WK_IX 50
245#define ASC_SCSIQ_W_ALT_DC1 52
246#define ASC_SCSIQ_B_LIST_CNT 6
247#define ASC_SCSIQ_B_CUR_LIST_CNT 7
248#define ASC_SGQ_B_SG_CNTL 4
249#define ASC_SGQ_B_SG_HEAD_QP 5
250#define ASC_SGQ_B_SG_LIST_CNT 6
251#define ASC_SGQ_B_SG_CUR_LIST_CNT 7
252#define ASC_SGQ_LIST_BEG 8
253#define ASC_DEF_SCSI1_QNG 4
254#define ASC_MAX_SCSI1_QNG 4
255#define ASC_DEF_SCSI2_QNG 16
256#define ASC_MAX_SCSI2_QNG 32
257#define ASC_TAG_CODE_MASK 0x23
258#define ASC_STOP_REQ_RISC_STOP 0x01
259#define ASC_STOP_ACK_RISC_STOP 0x03
260#define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
261#define ASC_STOP_CLEAN_UP_DISC_Q 0x20
262#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
263#define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
264#define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
265#define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
266#define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
267#define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
268#define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
269#define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
270
271typedef struct asc_scsiq_1 {
27c868c2
MW		 272 uchar status;
273 uchar q_no;
274 uchar cntl;
275 uchar sg_queue_cnt;
276 uchar target_id;
277 uchar target_lun;
95cfab6c
HR		 278 __le32 data_addr;
279 __le32 data_cnt;
280 __le32 sense_addr;
27c868c2
MW		 281 uchar sense_len;
282 uchar extra_bytes;
1da177e4
LT		 283} ASC_SCSIQ_1;
284
285typedef struct asc_scsiq_2 {
9c17c62a 286 u32 srb_tag;
27c868c2
MW		 287 uchar target_ix;
288 uchar flag;
289 uchar cdb_len;
290 uchar tag_code;
291 ushort vm_id;
1da177e4
LT		 292} ASC_SCSIQ_2;
293
294typedef struct asc_scsiq_3 {
27c868c2
MW		 295 uchar done_stat;
296 uchar host_stat;
297 uchar scsi_stat;
298 uchar scsi_msg;
1da177e4
LT		 299} ASC_SCSIQ_3;
300
301typedef struct asc_scsiq_4 {
27c868c2
MW		 302 uchar cdb[ASC_MAX_CDB_LEN];
303 uchar y_first_sg_list_qp;
304 uchar y_working_sg_qp;
305 uchar y_working_sg_ix;
306 uchar y_res;
307 ushort x_req_count;
308 ushort x_reconnect_rtn;
95cfab6c
HR		 309 __le32 x_saved_data_addr;
310 __le32 x_saved_data_cnt;
1da177e4
LT		 311} ASC_SCSIQ_4;
312
313typedef struct asc_q_done_info {
27c868c2
MW		 314 ASC_SCSIQ_2 d2;
315 ASC_SCSIQ_3 d3;
316 uchar q_status;
317 uchar q_no;
318 uchar cntl;
319 uchar sense_len;
320 uchar extra_bytes;
321 uchar res;
95cfab6c 322 u32 remain_bytes;
1da177e4
LT		 323} ASC_QDONE_INFO;
324
325typedef struct asc_sg_list {
95cfab6c
HR		 326 __le32 addr;
327 __le32 bytes;
1da177e4
LT		 328} ASC_SG_LIST;
329
330typedef struct asc_sg_head {
27c868c2
MW		 331 ushort entry_cnt;
332 ushort queue_cnt;
333 ushort entry_to_copy;
334 ushort res;
05848b6e 335 ASC_SG_LIST sg_list[0];
1da177e4
LT		 336} ASC_SG_HEAD;
337
1da177e4 338typedef struct asc_scsi_q {
27c868c2
MW		 339 ASC_SCSIQ_1 q1;
340 ASC_SCSIQ_2 q2;
341 uchar *cdbptr;
342 ASC_SG_HEAD *sg_head;
343 ushort remain_sg_entry_cnt;
344 ushort next_sg_index;
1da177e4
LT		 345} ASC_SCSI_Q;
346
1da177e4 347typedef struct asc_scsi_bios_req_q {
27c868c2
MW		 348 ASC_SCSIQ_1 r1;
349 ASC_SCSIQ_2 r2;
350 uchar *cdbptr;
351 ASC_SG_HEAD *sg_head;
352 uchar *sense_ptr;
353 ASC_SCSIQ_3 r3;
354 uchar cdb[ASC_MAX_CDB_LEN];
355 uchar sense[ASC_MIN_SENSE_LEN];
1da177e4
LT		 356} ASC_SCSI_BIOS_REQ_Q;
357
358typedef struct asc_risc_q {
27c868c2
MW		 359 uchar fwd;
360 uchar bwd;
361 ASC_SCSIQ_1 i1;
362 ASC_SCSIQ_2 i2;
363 ASC_SCSIQ_3 i3;
364 ASC_SCSIQ_4 i4;
1da177e4
LT		 365} ASC_RISC_Q;
366
367typedef struct asc_sg_list_q {
27c868c2
MW		 368 uchar seq_no;
369 uchar q_no;
370 uchar cntl;
371 uchar sg_head_qp;
372 uchar sg_list_cnt;
373 uchar sg_cur_list_cnt;
1da177e4
LT		 374} ASC_SG_LIST_Q;
375
376typedef struct asc_risc_sg_list_q {
27c868c2
MW		 377 uchar fwd;
378 uchar bwd;
379 ASC_SG_LIST_Q sg;
380 ASC_SG_LIST sg_list[7];
1da177e4
LT		 381} ASC_RISC_SG_LIST_Q;
382
1da177e4 383#define ASCQ_ERR_Q_STATUS 0x0D
1da177e4
LT		 384#define ASCQ_ERR_CUR_QNG 0x17
385#define ASCQ_ERR_SG_Q_LINKS 0x18
1da177e4
LT		 386#define ASCQ_ERR_ISR_RE_ENTRY 0x1A
387#define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
388#define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1da177e4
LT		 389
390/*
391 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
392 */
393#define ASC_WARN_NO_ERROR 0x0000
394#define ASC_WARN_IO_PORT_ROTATE 0x0001
395#define ASC_WARN_EEPROM_CHKSUM 0x0002
396#define ASC_WARN_IRQ_MODIFIED 0x0004
397#define ASC_WARN_AUTO_CONFIG 0x0008
398#define ASC_WARN_CMD_QNG_CONFLICT 0x0010
399#define ASC_WARN_EEPROM_RECOVER 0x0020
400#define ASC_WARN_CFG_MSW_RECOVER 0x0040
1da177e4
LT		 401
402/*
720349a8 403 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
1da177e4 404 */
720349a8
MW		 405#define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
406#define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
407#define ASC_IERR_SET_PC_ADDR 0x0004
408#define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
409#define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
410#define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
411#define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
412#define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
413#define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
414#define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
415#define ASC_IERR_NO_BUS_TYPE 0x0400
416#define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
417#define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
418#define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
1da177e4 419
1da177e4
LT		 420#define ASC_DEF_MAX_TOTAL_QNG (0xF0)
421#define ASC_MIN_TAG_Q_PER_DVC (0x04)
95c9f162 422#define ASC_MIN_FREE_Q (0x02)
1da177e4
LT		 423#define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
424#define ASC_MAX_TOTAL_QNG 240
425#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
426#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
427#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
428#define ASC_MAX_INRAM_TAG_QNG 16
1da177e4 429#define ASC_IOADR_GAP 0x10
1da177e4
LT		 430#define ASC_SYN_MAX_OFFSET 0x0F
431#define ASC_DEF_SDTR_OFFSET 0x0F
1da177e4 432#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
afbb68c3
MW		 433#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
434
435/* The narrow chip only supports a limited selection of transfer rates.
436 * These are encoded in the range 0..7 or 0..15 depending whether the chip
437 * is Ultra-capable or not. These tables let us convert from one to the other.
438 */
439static const unsigned char asc_syn_xfer_period[8] = {
440 25, 30, 35, 40, 50, 60, 70, 85
441};
442
443static const unsigned char asc_syn_ultra_xfer_period[16] = {
444 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
445};
1da177e4
LT		 446
447typedef struct ext_msg {
27c868c2
MW		 448 uchar msg_type;
449 uchar msg_len;
450 uchar msg_req;
451 union {
452 struct {
453 uchar sdtr_xfer_period;
454 uchar sdtr_req_ack_offset;
455 } sdtr;
456 struct {
457 uchar wdtr_width;
458 } wdtr;
459 struct {
460 uchar mdp_b3;
461 uchar mdp_b2;
462 uchar mdp_b1;
463 uchar mdp_b0;
464 } mdp;
465 } u_ext_msg;
466 uchar res;
1da177e4
LT		 467} EXT_MSG;
468
469#define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
470#define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
471#define wdtr_width u_ext_msg.wdtr.wdtr_width
472#define mdp_b3 u_ext_msg.mdp_b3
473#define mdp_b2 u_ext_msg.mdp_b2
474#define mdp_b1 u_ext_msg.mdp_b1
475#define mdp_b0 u_ext_msg.mdp_b0
476
477typedef struct asc_dvc_cfg {
27c868c2
MW		 478 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
479 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
480 ASC_SCSI_BIT_ID_TYPE disc_enable;
481 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
482 uchar chip_scsi_id;
483 uchar isa_dma_speed;
484 uchar isa_dma_channel;
485 uchar chip_version;
27c868c2
MW		 486 ushort mcode_date;
487 ushort mcode_version;
488 uchar max_tag_qng[ASC_MAX_TID + 1];
27c868c2 489 uchar sdtr_period_offset[ASC_MAX_TID + 1];
27c868c2 490 uchar adapter_info[6];
1da177e4
LT		 491} ASC_DVC_CFG;
492
493#define ASC_DEF_DVC_CNTL 0xFFFF
494#define ASC_DEF_CHIP_SCSI_ID 7
495#define ASC_DEF_ISA_DMA_SPEED 4
1da177e4
LT		 496#define ASC_INIT_STATE_BEG_GET_CFG 0x0001
497#define ASC_INIT_STATE_END_GET_CFG 0x0002
498#define ASC_INIT_STATE_BEG_SET_CFG 0x0004
499#define ASC_INIT_STATE_END_SET_CFG 0x0008
500#define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
501#define ASC_INIT_STATE_END_LOAD_MC 0x0020
502#define ASC_INIT_STATE_BEG_INQUIRY 0x0040
503#define ASC_INIT_STATE_END_INQUIRY 0x0080
504#define ASC_INIT_RESET_SCSI_DONE 0x0100
505#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1da177e4
LT		 506#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
507#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1da177e4
LT		 508#define ASC_MIN_TAGGED_CMD 7
509#define ASC_MAX_SCSI_RESET_WAIT 30
d10fb2c7 510#define ASC_OVERRUN_BSIZE 64
1da177e4 511
27c868c2 512struct asc_dvc_var; /* Forward Declaration. */
1da177e4 513
1da177e4 514typedef struct asc_dvc_var {
27c868c2
MW		 515 PortAddr iop_base;
516 ushort err_code;
517 ushort dvc_cntl;
518 ushort bug_fix_cntl;
519 ushort bus_type;
27c868c2
MW		 520 ASC_SCSI_BIT_ID_TYPE init_sdtr;
521 ASC_SCSI_BIT_ID_TYPE sdtr_done;
522 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
523 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
524 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
525 ASC_SCSI_BIT_ID_TYPE start_motor;
7d5d408c 526 uchar *overrun_buf;
d10fb2c7 527 dma_addr_t overrun_dma;
27c868c2
MW		 528 uchar scsi_reset_wait;
529 uchar chip_no;
ae26759e 530 bool is_in_int;
27c868c2
MW		 531 uchar max_total_qng;
532 uchar cur_total_qng;
533 uchar in_critical_cnt;
27c868c2
MW		 534 uchar last_q_shortage;
535 ushort init_state;
536 uchar cur_dvc_qng[ASC_MAX_TID + 1];
537 uchar max_dvc_qng[ASC_MAX_TID + 1];
538 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
539 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
afbb68c3 540 const uchar *sdtr_period_tbl;
27c868c2
MW		 541 ASC_DVC_CFG *cfg;
542 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
543 char redo_scam;
544 ushort res2;
545 uchar dos_int13_table[ASC_MAX_TID + 1];
95cfab6c 546 unsigned int max_dma_count;
27c868c2
MW		 547 ASC_SCSI_BIT_ID_TYPE no_scam;
548 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
afbb68c3 549 uchar min_sdtr_index;
27c868c2 550 uchar max_sdtr_index;
27c868c2 551 struct asc_board *drv_ptr;
95cfab6c 552 unsigned int uc_break;
1da177e4
LT		 553} ASC_DVC_VAR;
554
555typedef struct asc_dvc_inq_info {
27c868c2 556 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1da177e4
LT		 557} ASC_DVC_INQ_INFO;
558
559typedef struct asc_cap_info {
95cfab6c
HR		 560 u32 lba;
561 u32 blk_size;
1da177e4
LT		 562} ASC_CAP_INFO;
563
564typedef struct asc_cap_info_array {
27c868c2 565 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1da177e4
LT		 566} ASC_CAP_INFO_ARRAY;
567
568#define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
569#define ASC_MCNTL_NULL_TARGET (ushort)0x0002
570#define ASC_CNTL_INITIATOR (ushort)0x0001
571#define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
572#define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
573#define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
574#define ASC_CNTL_NO_SCAM (ushort)0x0010
575#define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
576#define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
577#define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
578#define ASC_CNTL_RESET_SCSI (ushort)0x0200
579#define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
580#define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
581#define ASC_CNTL_SCSI_PARITY (ushort)0x1000
582#define ASC_CNTL_BURST_MODE (ushort)0x2000
583#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
584#define ASC_EEP_DVC_CFG_BEG_VL 2
585#define ASC_EEP_MAX_DVC_ADDR_VL 15
586#define ASC_EEP_DVC_CFG_BEG 32
587#define ASC_EEP_MAX_DVC_ADDR 45
1da177e4 588#define ASC_EEP_MAX_RETRY 20
1da177e4
LT		 589
590/*
591 * These macros keep the chip SCSI id and ISA DMA speed
592 * bitfields in board order. C bitfields aren't portable
593 * between big and little-endian platforms so they are
594 * not used.
595 */
596
597#define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
598#define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
599#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
600 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
601#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
602 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
603
604typedef struct asceep_config {
27c868c2
MW		 605 ushort cfg_lsw;
606 ushort cfg_msw;
607 uchar init_sdtr;
608 uchar disc_enable;
609 uchar use_cmd_qng;
610 uchar start_motor;
611 uchar max_total_qng;
612 uchar max_tag_qng;
613 uchar bios_scan;
614 uchar power_up_wait;
615 uchar no_scam;
616 uchar id_speed; /* low order 4 bits is chip scsi id */
617 /* high order 4 bits is isa dma speed */
618 uchar dos_int13_table[ASC_MAX_TID + 1];
619 uchar adapter_info[6];
620 ushort cntl;
621 ushort chksum;
1da177e4
LT		 622} ASCEEP_CONFIG;
623
1da177e4
LT		 624#define ASC_EEP_CMD_READ 0x80
625#define ASC_EEP_CMD_WRITE 0x40
626#define ASC_EEP_CMD_WRITE_ABLE 0x30
627#define ASC_EEP_CMD_WRITE_DISABLE 0x00
1da177e4
LT		 628#define ASCV_MSGOUT_BEG 0x0000
629#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
630#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
631#define ASCV_BREAK_SAVED_CODE (ushort)0x0006
632#define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
633#define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
634#define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
635#define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
636#define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
637#define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
638#define ASCV_BREAK_ADDR (ushort)0x0028
639#define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
640#define ASCV_BREAK_CONTROL (ushort)0x002C
641#define ASCV_BREAK_HIT_COUNT (ushort)0x002E
642
643#define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
644#define ASCV_MCODE_CHKSUM_W (ushort)0x0032
645#define ASCV_MCODE_SIZE_W (ushort)0x0034
646#define ASCV_STOP_CODE_B (ushort)0x0036
647#define ASCV_DVC_ERR_CODE_B (ushort)0x0037
648#define ASCV_OVERRUN_PADDR_D (ushort)0x0038
649#define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
650#define ASCV_HALTCODE_W (ushort)0x0040
651#define ASCV_CHKSUM_W (ushort)0x0042
652#define ASCV_MC_DATE_W (ushort)0x0044
653#define ASCV_MC_VER_W (ushort)0x0046
654#define ASCV_NEXTRDY_B (ushort)0x0048
655#define ASCV_DONENEXT_B (ushort)0x0049
656#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
657#define ASCV_SCSIBUSY_B (ushort)0x004B
658#define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
659#define ASCV_CURCDB_B (ushort)0x004D
660#define ASCV_RCLUN_B (ushort)0x004E
661#define ASCV_BUSY_QHEAD_B (ushort)0x004F
662#define ASCV_DISC1_QHEAD_B (ushort)0x0050
663#define ASCV_DISC_ENABLE_B (ushort)0x0052
664#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
665#define ASCV_HOSTSCSI_ID_B (ushort)0x0055
666#define ASCV_MCODE_CNTL_B (ushort)0x0056
667#define ASCV_NULL_TARGET_B (ushort)0x0057
668#define ASCV_FREE_Q_HEAD_W (ushort)0x0058
669#define ASCV_DONE_Q_TAIL_W (ushort)0x005A
670#define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
671#define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
672#define ASCV_HOST_FLAG_B (ushort)0x005D
673#define ASCV_TOTAL_READY_Q_B (ushort)0x0064
674#define ASCV_VER_SERIAL_B (ushort)0x0065
675#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
676#define ASCV_WTM_FLAG_B (ushort)0x0068
677#define ASCV_RISC_FLAG_B (ushort)0x006A
678#define ASCV_REQ_SG_LIST_QP (ushort)0x006B
679#define ASC_HOST_FLAG_IN_ISR 0x01
680#define ASC_HOST_FLAG_ACK_INT 0x02
681#define ASC_RISC_FLAG_GEN_INT 0x01
682#define ASC_RISC_FLAG_REQ_SG_LIST 0x02
683#define IOP_CTRL (0x0F)
684#define IOP_STATUS (0x0E)
685#define IOP_INT_ACK IOP_STATUS
686#define IOP_REG_IFC (0x0D)
687#define IOP_SYN_OFFSET (0x0B)
688#define IOP_EXTRA_CONTROL (0x0D)
689#define IOP_REG_PC (0x0C)
690#define IOP_RAM_ADDR (0x0A)
691#define IOP_RAM_DATA (0x08)
692#define IOP_EEP_DATA (0x06)
693#define IOP_EEP_CMD (0x07)
694#define IOP_VERSION (0x03)
695#define IOP_CONFIG_HIGH (0x04)
696#define IOP_CONFIG_LOW (0x02)
697#define IOP_SIG_BYTE (0x01)
698#define IOP_SIG_WORD (0x00)
699#define IOP_REG_DC1 (0x0E)
700#define IOP_REG_DC0 (0x0C)
701#define IOP_REG_SB (0x0B)
702#define IOP_REG_DA1 (0x0A)
703#define IOP_REG_DA0 (0x08)
704#define IOP_REG_SC (0x09)
705#define IOP_DMA_SPEED (0x07)
706#define IOP_REG_FLAG (0x07)
707#define IOP_FIFO_H (0x06)
708#define IOP_FIFO_L (0x04)
709#define IOP_REG_ID (0x05)
710#define IOP_REG_QP (0x03)
711#define IOP_REG_IH (0x02)
712#define IOP_REG_IX (0x01)
713#define IOP_REG_AX (0x00)
714#define IFC_REG_LOCK (0x00)
715#define IFC_REG_UNLOCK (0x09)
716#define IFC_WR_EN_FILTER (0x10)
717#define IFC_RD_NO_EEPROM (0x10)
718#define IFC_SLEW_RATE (0x20)
719#define IFC_ACT_NEG (0x40)
720#define IFC_INP_FILTER (0x80)
721#define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
722#define SC_SEL (uchar)(0x80)
723#define SC_BSY (uchar)(0x40)
724#define SC_ACK (uchar)(0x20)
725#define SC_REQ (uchar)(0x10)
726#define SC_ATN (uchar)(0x08)
727#define SC_IO (uchar)(0x04)
728#define SC_CD (uchar)(0x02)
729#define SC_MSG (uchar)(0x01)
730#define SEC_SCSI_CTL (uchar)(0x80)
731#define SEC_ACTIVE_NEGATE (uchar)(0x40)
732#define SEC_SLEW_RATE (uchar)(0x20)
733#define SEC_ENABLE_FILTER (uchar)(0x10)
734#define ASC_HALT_EXTMSG_IN (ushort)0x8000
735#define ASC_HALT_CHK_CONDITION (ushort)0x8100
736#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
737#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
738#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
739#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
740#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
741#define ASC_MAX_QNO 0xF8
742#define ASC_DATA_SEC_BEG (ushort)0x0080
743#define ASC_DATA_SEC_END (ushort)0x0080
744#define ASC_CODE_SEC_BEG (ushort)0x0080
745#define ASC_CODE_SEC_END (ushort)0x0080
746#define ASC_QADR_BEG (0x4000)
747#define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
748#define ASC_QADR_END (ushort)0x7FFF
749#define ASC_QLAST_ADR (ushort)0x7FC0
750#define ASC_QBLK_SIZE 0x40
751#define ASC_BIOS_DATA_QBEG 0xF8
752#define ASC_MIN_ACTIVE_QNO 0x01
753#define ASC_QLINK_END 0xFF
754#define ASC_EEPROM_WORDS 0x10
755#define ASC_MAX_MGS_LEN 0x10
756#define ASC_BIOS_ADDR_DEF 0xDC00
757#define ASC_BIOS_SIZE 0x3800
758#define ASC_BIOS_RAM_OFF 0x3800
759#define ASC_BIOS_RAM_SIZE 0x800
760#define ASC_BIOS_MIN_ADDR 0xC000
761#define ASC_BIOS_MAX_ADDR 0xEC00
762#define ASC_BIOS_BANK_SIZE 0x0400
763#define ASC_MCODE_START_ADDR 0x0080
764#define ASC_CFG0_HOST_INT_ON 0x0020
765#define ASC_CFG0_BIOS_ON 0x0040
766#define ASC_CFG0_VERA_BURST_ON 0x0080
767#define ASC_CFG0_SCSI_PARITY_ON 0x0800
768#define ASC_CFG1_SCSI_TARGET_ON 0x0080
769#define ASC_CFG1_LRAM_8BITS_ON 0x0800
770#define ASC_CFG_MSW_CLR_MASK 0x3080
771#define CSW_TEST1 (ASC_CS_TYPE)0x8000
772#define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
773#define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
774#define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
775#define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
776#define CSW_TEST2 (ASC_CS_TYPE)0x0400
777#define CSW_TEST3 (ASC_CS_TYPE)0x0200
778#define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
779#define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
780#define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
781#define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
782#define CSW_HALTED (ASC_CS_TYPE)0x0010
783#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
784#define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
785#define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
786#define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
787#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
788#define CIW_INT_ACK (ASC_CS_TYPE)0x0100
789#define CIW_TEST1 (ASC_CS_TYPE)0x0200
790#define CIW_TEST2 (ASC_CS_TYPE)0x0400
791#define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
792#define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
793#define CC_CHIP_RESET (uchar)0x80
794#define CC_SCSI_RESET (uchar)0x40
795#define CC_HALT (uchar)0x20
796#define CC_SINGLE_STEP (uchar)0x10
797#define CC_DMA_ABLE (uchar)0x08
798#define CC_TEST (uchar)0x04
799#define CC_BANK_ONE (uchar)0x02
800#define CC_DIAG (uchar)0x01
801#define ASC_1000_ID0W 0x04C1
802#define ASC_1000_ID0W_FIX 0x00C1
803#define ASC_1000_ID1B 0x25
1da177e4 804#define ASC_EISA_REV_IOP_MASK (0x0C83)
1da177e4
LT		 805#define ASC_EISA_CFG_IOP_MASK (0x0C86)
806#define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1da177e4
LT		 807#define INS_HALTINT (ushort)0x6281
808#define INS_HALT (ushort)0x6280
809#define INS_SINT (ushort)0x6200
810#define INS_RFLAG_WTM (ushort)0x7380
811#define ASC_MC_SAVE_CODE_WSIZE 0x500
812#define ASC_MC_SAVE_DATA_WSIZE 0x40
813
814typedef struct asc_mc_saved {
27c868c2
MW		 815 ushort data[ASC_MC_SAVE_DATA_WSIZE];
816 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1da177e4
LT		 817} ASC_MC_SAVED;
818
819#define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
820#define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
821#define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
822#define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
823#define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
824#define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
825#define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
826#define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
827#define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
828#define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
51219358
MW		 829#define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
830#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
831#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
832#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
1da177e4
LT		 833#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
834#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
835#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
836#define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
837#define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
838#define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
839#define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
840#define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
841#define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
842#define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
843#define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
844#define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
845#define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
846#define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
847#define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
848#define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
849#define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
850#define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
851#define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
852#define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
853#define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
854#define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
855#define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
856#define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
857#define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
858#define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
859#define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
860#define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
861#define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
862#define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
863#define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
864#define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
865#define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
866#define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
867#define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
868#define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
869#define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
870#define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
871#define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
872#define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
873#define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
874#define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
875#define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
876#define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
877#define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
878#define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
879#define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
880#define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
881#define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
882#define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
883#define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
884#define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
885#define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
886
1da177e4
LT		 887/*
888 * These macros are used to convert a virtual address to a
889 * 32-bit value. This currently can be used on Linux Alpha
890 * which uses 64-bit virtual address but a 32-bit bus address.
891 * This is likely to break in the future, but doing this now
892 * will give us time to change the HW and FW to handle 64-bit
893 * addresses.
894 */
1da177e4
LT		 895#define ADV_U32_TO_VADDR bus_to_virt
896
27c868c2 897#define AdvPortAddr void __iomem * /* Virtual memory address size */
1da177e4
LT		 898
899/*
900 * Define Adv Library required memory access macros.
901 */
902#define ADV_MEM_READB(addr) readb(addr)
903#define ADV_MEM_READW(addr) readw(addr)
904#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
905#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
906#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
907
1da177e4
LT		 908/*
909 * Define total number of simultaneous maximum element scatter-gather
910 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
911 * maximum number of outstanding commands per wide host adapter. Each
912 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
913 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
914 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
915 * structures or 255 scatter-gather elements.
1da177e4
LT		 916 */
917#define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
918
919/*
98d41c29 920 * Define maximum number of scatter-gather elements per request.
1da177e4
LT		 921 */
922#define ADV_MAX_SG_LIST 255
98d41c29 923#define NO_OF_SG_PER_BLOCK 15
1da177e4 924
1da177e4
LT		 925#define ADV_EEP_DVC_CFG_BEGIN (0x00)
926#define ADV_EEP_DVC_CFG_END (0x15)
27c868c2 927#define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1da177e4
LT		 928#define ADV_EEP_MAX_WORD_ADDR (0x1E)
929
930#define ADV_EEP_DELAY_MS 100
931
27c868c2
MW		 932#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
933#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1da177e4
LT		 934/*
935 * For the ASC3550 Bit 13 is Termination Polarity control bit.
936 * For later ICs Bit 13 controls whether the CIS (Card Information
937 * Service Section) is loaded from EEPROM.
938 */
27c868c2
MW		 939#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
940#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1da177e4
LT		 941/*
942 * ASC38C1600 Bit 11
943 *
944 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
945 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
946 * Function 0 will specify INT B.
947 *
948 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
949 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
950 * Function 1 will specify INT A.
951 */
27c868c2
MW		 952#define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
953
954typedef struct adveep_3550_config {
955 /* Word Offset, Description */
956
957 ushort cfg_lsw; /* 00 power up initialization */
958 /* bit 13 set - Term Polarity Control */
959 /* bit 14 set - BIOS Enable */
960 /* bit 15 set - Big Endian Mode */
961 ushort cfg_msw; /* 01 unused */
962 ushort disc_enable; /* 02 disconnect enable */
963 ushort wdtr_able; /* 03 Wide DTR able */
964 ushort sdtr_able; /* 04 Synchronous DTR able */
965 ushort start_motor; /* 05 send start up motor */
966 ushort tagqng_able; /* 06 tag queuing able */
967 ushort bios_scan; /* 07 BIOS device control */
968 ushort scam_tolerant; /* 08 no scam */
969
970 uchar adapter_scsi_id; /* 09 Host Adapter ID */
971 uchar bios_boot_delay; /* power up wait */
972
973 uchar scsi_reset_delay; /* 10 reset delay */
974 uchar bios_id_lun; /* first boot device scsi id & lun */
975 /* high nibble is lun */
976 /* low nibble is scsi id */
977
978 uchar termination; /* 11 0 - automatic */
979 /* 1 - low off / high off */
980 /* 2 - low off / high on */
981 /* 3 - low on / high on */
982 /* There is no low on / high off */
983
984 uchar reserved1; /* reserved byte (not used) */
985
986 ushort bios_ctrl; /* 12 BIOS control bits */
987 /* bit 0 BIOS don't act as initiator. */
988 /* bit 1 BIOS > 1 GB support */
989 /* bit 2 BIOS > 2 Disk Support */
990 /* bit 3 BIOS don't support removables */
991 /* bit 4 BIOS support bootable CD */
992 /* bit 5 BIOS scan enabled */
993 /* bit 6 BIOS support multiple LUNs */
994 /* bit 7 BIOS display of message */
995 /* bit 8 SCAM disabled */
996 /* bit 9 Reset SCSI bus during init. */
997 /* bit 10 */
998 /* bit 11 No verbose initialization. */
999 /* bit 12 SCSI parity enabled */
1000 /* bit 13 */
1001 /* bit 14 */
1002 /* bit 15 */
1003 ushort ultra_able; /* 13 ULTRA speed able */
1004 ushort reserved2; /* 14 reserved */
1005 uchar max_host_qng; /* 15 maximum host queuing */
1006 uchar max_dvc_qng; /* maximum per device queuing */
1007 ushort dvc_cntl; /* 16 control bit for driver */
1008 ushort bug_fix; /* 17 control bit for bug fix */
1009 ushort serial_number_word1; /* 18 Board serial number word 1 */
1010 ushort serial_number_word2; /* 19 Board serial number word 2 */
1011 ushort serial_number_word3; /* 20 Board serial number word 3 */
1012 ushort check_sum; /* 21 EEP check sum */
1013 uchar oem_name[16]; /* 22 OEM name */
1014 ushort dvc_err_code; /* 30 last device driver error code */
1015 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1016 ushort adv_err_addr; /* 32 last uc error address */
1017 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1018 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1019 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1020 ushort num_of_err; /* 36 number of error */
1da177e4
LT		 1021} ADVEEP_3550_CONFIG;
1022
27c868c2
MW		 1023typedef struct adveep_38C0800_config {
1024 /* Word Offset, Description */
1025
1026 ushort cfg_lsw; /* 00 power up initialization */
1027 /* bit 13 set - Load CIS */
1028 /* bit 14 set - BIOS Enable */
1029 /* bit 15 set - Big Endian Mode */
1030 ushort cfg_msw; /* 01 unused */
1031 ushort disc_enable; /* 02 disconnect enable */
1032 ushort wdtr_able; /* 03 Wide DTR able */
1033 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1034 ushort start_motor; /* 05 send start up motor */
1035 ushort tagqng_able; /* 06 tag queuing able */
1036 ushort bios_scan; /* 07 BIOS device control */
1037 ushort scam_tolerant; /* 08 no scam */
1038
1039 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1040 uchar bios_boot_delay; /* power up wait */
1041
1042 uchar scsi_reset_delay; /* 10 reset delay */
1043 uchar bios_id_lun; /* first boot device scsi id & lun */
1044 /* high nibble is lun */
1045 /* low nibble is scsi id */
1046
1047 uchar termination_se; /* 11 0 - automatic */
1048 /* 1 - low off / high off */
1049 /* 2 - low off / high on */
1050 /* 3 - low on / high on */
1051 /* There is no low on / high off */
1052
1053 uchar termination_lvd; /* 11 0 - automatic */
1054 /* 1 - low off / high off */
1055 /* 2 - low off / high on */
1056 /* 3 - low on / high on */
1057 /* There is no low on / high off */
1058
1059 ushort bios_ctrl; /* 12 BIOS control bits */
1060 /* bit 0 BIOS don't act as initiator. */
1061 /* bit 1 BIOS > 1 GB support */
1062 /* bit 2 BIOS > 2 Disk Support */
1063 /* bit 3 BIOS don't support removables */
1064 /* bit 4 BIOS support bootable CD */
1065 /* bit 5 BIOS scan enabled */
1066 /* bit 6 BIOS support multiple LUNs */
1067 /* bit 7 BIOS display of message */
1068 /* bit 8 SCAM disabled */
1069 /* bit 9 Reset SCSI bus during init. */
1070 /* bit 10 */
1071 /* bit 11 No verbose initialization. */
1072 /* bit 12 SCSI parity enabled */
1073 /* bit 13 */
1074 /* bit 14 */
1075 /* bit 15 */
1076 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1077 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1078 uchar max_host_qng; /* 15 maximum host queueing */
1079 uchar max_dvc_qng; /* maximum per device queuing */
1080 ushort dvc_cntl; /* 16 control bit for driver */
1081 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1082 ushort serial_number_word1; /* 18 Board serial number word 1 */
1083 ushort serial_number_word2; /* 19 Board serial number word 2 */
1084 ushort serial_number_word3; /* 20 Board serial number word 3 */
1085 ushort check_sum; /* 21 EEP check sum */
1086 uchar oem_name[16]; /* 22 OEM name */
1087 ushort dvc_err_code; /* 30 last device driver error code */
1088 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1089 ushort adv_err_addr; /* 32 last uc error address */
1090 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1091 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1092 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1093 ushort reserved36; /* 36 reserved */
1094 ushort reserved37; /* 37 reserved */
1095 ushort reserved38; /* 38 reserved */
1096 ushort reserved39; /* 39 reserved */
1097 ushort reserved40; /* 40 reserved */
1098 ushort reserved41; /* 41 reserved */
1099 ushort reserved42; /* 42 reserved */
1100 ushort reserved43; /* 43 reserved */
1101 ushort reserved44; /* 44 reserved */
1102 ushort reserved45; /* 45 reserved */
1103 ushort reserved46; /* 46 reserved */
1104 ushort reserved47; /* 47 reserved */
1105 ushort reserved48; /* 48 reserved */
1106 ushort reserved49; /* 49 reserved */
1107 ushort reserved50; /* 50 reserved */
1108 ushort reserved51; /* 51 reserved */
1109 ushort reserved52; /* 52 reserved */
1110 ushort reserved53; /* 53 reserved */
1111 ushort reserved54; /* 54 reserved */
1112 ushort reserved55; /* 55 reserved */
1113 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1114 ushort cisprt_msw; /* 57 CIS PTR MSW */
1115 ushort subsysvid; /* 58 SubSystem Vendor ID */
1116 ushort subsysid; /* 59 SubSystem ID */
1117 ushort reserved60; /* 60 reserved */
1118 ushort reserved61; /* 61 reserved */
1119 ushort reserved62; /* 62 reserved */
1120 ushort reserved63; /* 63 reserved */
1da177e4
LT		 1121} ADVEEP_38C0800_CONFIG;
1122
27c868c2
MW		 1123typedef struct adveep_38C1600_config {
1124 /* Word Offset, Description */
1125
1126 ushort cfg_lsw; /* 00 power up initialization */
1127 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1128 /* clear - Func. 0 INTA, Func. 1 INTB */
1129 /* bit 13 set - Load CIS */
1130 /* bit 14 set - BIOS Enable */
1131 /* bit 15 set - Big Endian Mode */
1132 ushort cfg_msw; /* 01 unused */
1133 ushort disc_enable; /* 02 disconnect enable */
1134 ushort wdtr_able; /* 03 Wide DTR able */
1135 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1136 ushort start_motor; /* 05 send start up motor */
1137 ushort tagqng_able; /* 06 tag queuing able */
1138 ushort bios_scan; /* 07 BIOS device control */
1139 ushort scam_tolerant; /* 08 no scam */
1140
1141 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1142 uchar bios_boot_delay; /* power up wait */
1143
1144 uchar scsi_reset_delay; /* 10 reset delay */
1145 uchar bios_id_lun; /* first boot device scsi id & lun */
1146 /* high nibble is lun */
1147 /* low nibble is scsi id */
1148
1149 uchar termination_se; /* 11 0 - automatic */
1150 /* 1 - low off / high off */
1151 /* 2 - low off / high on */
1152 /* 3 - low on / high on */
1153 /* There is no low on / high off */
1154
1155 uchar termination_lvd; /* 11 0 - automatic */
1156 /* 1 - low off / high off */
1157 /* 2 - low off / high on */
1158 /* 3 - low on / high on */
1159 /* There is no low on / high off */
1160
1161 ushort bios_ctrl; /* 12 BIOS control bits */
1162 /* bit 0 BIOS don't act as initiator. */
1163 /* bit 1 BIOS > 1 GB support */
1164 /* bit 2 BIOS > 2 Disk Support */
1165 /* bit 3 BIOS don't support removables */
1166 /* bit 4 BIOS support bootable CD */
1167 /* bit 5 BIOS scan enabled */
1168 /* bit 6 BIOS support multiple LUNs */
1169 /* bit 7 BIOS display of message */
1170 /* bit 8 SCAM disabled */
1171 /* bit 9 Reset SCSI bus during init. */
1172 /* bit 10 Basic Integrity Checking disabled */
1173 /* bit 11 No verbose initialization. */
1174 /* bit 12 SCSI parity enabled */
1175 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1176 /* bit 14 */
1177 /* bit 15 */
1178 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1179 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1180 uchar max_host_qng; /* 15 maximum host queueing */
1181 uchar max_dvc_qng; /* maximum per device queuing */
1182 ushort dvc_cntl; /* 16 control bit for driver */
1183 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1184 ushort serial_number_word1; /* 18 Board serial number word 1 */
1185 ushort serial_number_word2; /* 19 Board serial number word 2 */
1186 ushort serial_number_word3; /* 20 Board serial number word 3 */
1187 ushort check_sum; /* 21 EEP check sum */
1188 uchar oem_name[16]; /* 22 OEM name */
1189 ushort dvc_err_code; /* 30 last device driver error code */
1190 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1191 ushort adv_err_addr; /* 32 last uc error address */
1192 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1193 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1194 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1195 ushort reserved36; /* 36 reserved */
1196 ushort reserved37; /* 37 reserved */
1197 ushort reserved38; /* 38 reserved */
1198 ushort reserved39; /* 39 reserved */
1199 ushort reserved40; /* 40 reserved */
1200 ushort reserved41; /* 41 reserved */
1201 ushort reserved42; /* 42 reserved */
1202 ushort reserved43; /* 43 reserved */
1203 ushort reserved44; /* 44 reserved */
1204 ushort reserved45; /* 45 reserved */
1205 ushort reserved46; /* 46 reserved */
1206 ushort reserved47; /* 47 reserved */
1207 ushort reserved48; /* 48 reserved */
1208 ushort reserved49; /* 49 reserved */
1209 ushort reserved50; /* 50 reserved */
1210 ushort reserved51; /* 51 reserved */
1211 ushort reserved52; /* 52 reserved */
1212 ushort reserved53; /* 53 reserved */
1213 ushort reserved54; /* 54 reserved */
1214 ushort reserved55; /* 55 reserved */
1215 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1216 ushort cisprt_msw; /* 57 CIS PTR MSW */
1217 ushort subsysvid; /* 58 SubSystem Vendor ID */
1218 ushort subsysid; /* 59 SubSystem ID */
1219 ushort reserved60; /* 60 reserved */
1220 ushort reserved61; /* 61 reserved */
1221 ushort reserved62; /* 62 reserved */
1222 ushort reserved63; /* 63 reserved */
1da177e4
LT		 1223} ADVEEP_38C1600_CONFIG;
1224
1225/*
1226 * EEPROM Commands
1227 */
1228#define ASC_EEP_CMD_DONE 0x0200
1da177e4
LT		 1229
1230/* bios_ctrl */
1231#define BIOS_CTRL_BIOS 0x0001
1232#define BIOS_CTRL_EXTENDED_XLAT 0x0002
1233#define BIOS_CTRL_GT_2_DISK 0x0004
1234#define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1235#define BIOS_CTRL_BOOTABLE_CD 0x0010
1236#define BIOS_CTRL_MULTIPLE_LUN 0x0040
1237#define BIOS_CTRL_DISPLAY_MSG 0x0080
1238#define BIOS_CTRL_NO_SCAM 0x0100
1239#define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1240#define BIOS_CTRL_INIT_VERBOSE 0x0800
1241#define BIOS_CTRL_SCSI_PARITY 0x1000
1242#define BIOS_CTRL_AIPP_DIS 0x2000
1243
27c868c2 1244#define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1da177e4 1245
27c868c2 1246#define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1da177e4
LT		 1247
1248/*
1249 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1250 * a special 16K Adv Library and Microcode version. After the issue is
1251 * resolved, should restore 32K support.
1252 *
1253 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1254 */
27c868c2 1255#define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1da177e4
LT		 1256
1257/*
1258 * Byte I/O register address from base of 'iop_base'.
1259 */
1260#define IOPB_INTR_STATUS_REG 0x00
1261#define IOPB_CHIP_ID_1 0x01
1262#define IOPB_INTR_ENABLES 0x02
1263#define IOPB_CHIP_TYPE_REV 0x03
1264#define IOPB_RES_ADDR_4 0x04
1265#define IOPB_RES_ADDR_5 0x05
1266#define IOPB_RAM_DATA 0x06
1267#define IOPB_RES_ADDR_7 0x07
1268#define IOPB_FLAG_REG 0x08
1269#define IOPB_RES_ADDR_9 0x09
1270#define IOPB_RISC_CSR 0x0A
1271#define IOPB_RES_ADDR_B 0x0B
1272#define IOPB_RES_ADDR_C 0x0C
1273#define IOPB_RES_ADDR_D 0x0D
1274#define IOPB_SOFT_OVER_WR 0x0E
1275#define IOPB_RES_ADDR_F 0x0F
1276#define IOPB_MEM_CFG 0x10
1277#define IOPB_RES_ADDR_11 0x11
1278#define IOPB_GPIO_DATA 0x12
1279#define IOPB_RES_ADDR_13 0x13
1280#define IOPB_FLASH_PAGE 0x14
1281#define IOPB_RES_ADDR_15 0x15
1282#define IOPB_GPIO_CNTL 0x16
1283#define IOPB_RES_ADDR_17 0x17
1284#define IOPB_FLASH_DATA 0x18
1285#define IOPB_RES_ADDR_19 0x19
1286#define IOPB_RES_ADDR_1A 0x1A
1287#define IOPB_RES_ADDR_1B 0x1B
1288#define IOPB_RES_ADDR_1C 0x1C
1289#define IOPB_RES_ADDR_1D 0x1D
1290#define IOPB_RES_ADDR_1E 0x1E
1291#define IOPB_RES_ADDR_1F 0x1F
1292#define IOPB_DMA_CFG0 0x20
1293#define IOPB_DMA_CFG1 0x21
1294#define IOPB_TICKLE 0x22
1295#define IOPB_DMA_REG_WR 0x23
1296#define IOPB_SDMA_STATUS 0x24
1297#define IOPB_SCSI_BYTE_CNT 0x25
1298#define IOPB_HOST_BYTE_CNT 0x26
1299#define IOPB_BYTE_LEFT_TO_XFER 0x27
1300#define IOPB_BYTE_TO_XFER_0 0x28
1301#define IOPB_BYTE_TO_XFER_1 0x29
1302#define IOPB_BYTE_TO_XFER_2 0x2A
1303#define IOPB_BYTE_TO_XFER_3 0x2B
1304#define IOPB_ACC_GRP 0x2C
1305#define IOPB_RES_ADDR_2D 0x2D
1306#define IOPB_DEV_ID 0x2E
1307#define IOPB_RES_ADDR_2F 0x2F
1308#define IOPB_SCSI_DATA 0x30
1309#define IOPB_RES_ADDR_31 0x31
1310#define IOPB_RES_ADDR_32 0x32
1311#define IOPB_SCSI_DATA_HSHK 0x33
1312#define IOPB_SCSI_CTRL 0x34
1313#define IOPB_RES_ADDR_35 0x35
1314#define IOPB_RES_ADDR_36 0x36
1315#define IOPB_RES_ADDR_37 0x37
1316#define IOPB_RAM_BIST 0x38
1317#define IOPB_PLL_TEST 0x39
1318#define IOPB_PCI_INT_CFG 0x3A
1319#define IOPB_RES_ADDR_3B 0x3B
1320#define IOPB_RFIFO_CNT 0x3C
1321#define IOPB_RES_ADDR_3D 0x3D
1322#define IOPB_RES_ADDR_3E 0x3E
1323#define IOPB_RES_ADDR_3F 0x3F
1324
1325/*
1326 * Word I/O register address from base of 'iop_base'.
1327 */
27c868c2
MW		 1328#define IOPW_CHIP_ID_0 0x00 /* CID0 */
1329#define IOPW_CTRL_REG 0x02 /* CC */
1330#define IOPW_RAM_ADDR 0x04 /* LA */
1331#define IOPW_RAM_DATA 0x06 /* LD */
1da177e4 1332#define IOPW_RES_ADDR_08 0x08
27c868c2
MW		 1333#define IOPW_RISC_CSR 0x0A /* CSR */
1334#define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1335#define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1da177e4 1336#define IOPW_RES_ADDR_10 0x10
27c868c2 1337#define IOPW_SEL_MASK 0x12 /* SM */
1da177e4 1338#define IOPW_RES_ADDR_14 0x14
27c868c2 1339#define IOPW_FLASH_ADDR 0x16 /* FA */
1da177e4 1340#define IOPW_RES_ADDR_18 0x18
27c868c2
MW		 1341#define IOPW_EE_CMD 0x1A /* EC */
1342#define IOPW_EE_DATA 0x1C /* ED */
1343#define IOPW_SFIFO_CNT 0x1E /* SFC */
1da177e4 1344#define IOPW_RES_ADDR_20 0x20
27c868c2
MW		 1345#define IOPW_Q_BASE 0x22 /* QB */
1346#define IOPW_QP 0x24 /* QP */
1347#define IOPW_IX 0x26 /* IX */
1348#define IOPW_SP 0x28 /* SP */
1349#define IOPW_PC 0x2A /* PC */
1da177e4
LT		 1350#define IOPW_RES_ADDR_2C 0x2C
1351#define IOPW_RES_ADDR_2E 0x2E
27c868c2
MW		 1352#define IOPW_SCSI_DATA 0x30 /* SD */
1353#define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1354#define IOPW_SCSI_CTRL 0x34 /* SC */
1355#define IOPW_HSHK_CFG 0x36 /* HCFG */
1356#define IOPW_SXFR_STATUS 0x36 /* SXS */
1357#define IOPW_SXFR_CNTL 0x38 /* SXL */
1358#define IOPW_SXFR_CNTH 0x3A /* SXH */
1da177e4 1359#define IOPW_RES_ADDR_3C 0x3C
27c868c2 1360#define IOPW_RFIFO_DATA 0x3E /* RFD */
1da177e4
LT		 1361
1362/*
1363 * Doubleword I/O register address from base of 'iop_base'.
1364 */
1365#define IOPDW_RES_ADDR_0 0x00
1366#define IOPDW_RAM_DATA 0x04
1367#define IOPDW_RES_ADDR_8 0x08
1368#define IOPDW_RES_ADDR_C 0x0C
1369#define IOPDW_RES_ADDR_10 0x10
1370#define IOPDW_COMMA 0x14
1371#define IOPDW_COMMB 0x18
1372#define IOPDW_RES_ADDR_1C 0x1C
1373#define IOPDW_SDMA_ADDR0 0x20
1374#define IOPDW_SDMA_ADDR1 0x24
1375#define IOPDW_SDMA_COUNT 0x28
1376#define IOPDW_SDMA_ERROR 0x2C
1377#define IOPDW_RDMA_ADDR0 0x30
1378#define IOPDW_RDMA_ADDR1 0x34
1379#define IOPDW_RDMA_COUNT 0x38
1380#define IOPDW_RDMA_ERROR 0x3C
1381
1382#define ADV_CHIP_ID_BYTE 0x25
1383#define ADV_CHIP_ID_WORD 0x04C1
1384
1da177e4
LT		 1385#define ADV_INTR_ENABLE_HOST_INTR 0x01
1386#define ADV_INTR_ENABLE_SEL_INTR 0x02
1387#define ADV_INTR_ENABLE_DPR_INTR 0x04
1388#define ADV_INTR_ENABLE_RTA_INTR 0x08
1389#define ADV_INTR_ENABLE_RMA_INTR 0x10
1390#define ADV_INTR_ENABLE_RST_INTR 0x20
1391#define ADV_INTR_ENABLE_DPE_INTR 0x40
1392#define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1393
1394#define ADV_INTR_STATUS_INTRA 0x01
1395#define ADV_INTR_STATUS_INTRB 0x02
1396#define ADV_INTR_STATUS_INTRC 0x04
1397
1398#define ADV_RISC_CSR_STOP (0x0000)
1399#define ADV_RISC_TEST_COND (0x2000)
1400#define ADV_RISC_CSR_RUN (0x4000)
1401#define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1402
1403#define ADV_CTRL_REG_HOST_INTR 0x0100
1404#define ADV_CTRL_REG_SEL_INTR 0x0200
1405#define ADV_CTRL_REG_DPR_INTR 0x0400
1406#define ADV_CTRL_REG_RTA_INTR 0x0800
1407#define ADV_CTRL_REG_RMA_INTR 0x1000
1408#define ADV_CTRL_REG_RES_BIT14 0x2000
1409#define ADV_CTRL_REG_DPE_INTR 0x4000
1410#define ADV_CTRL_REG_POWER_DONE 0x8000
1411#define ADV_CTRL_REG_ANY_INTR 0xFF00
1412
1413#define ADV_CTRL_REG_CMD_RESET 0x00C6
1414#define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1415#define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1416#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1417#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1418
1419#define ADV_TICKLE_NOP 0x00
1420#define ADV_TICKLE_A 0x01
1421#define ADV_TICKLE_B 0x02
1422#define ADV_TICKLE_C 0x03
1423
1da177e4
LT		 1424#define AdvIsIntPending(port) \
1425 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1426
1427/*
1428 * SCSI_CFG0 Register bit definitions
1429 */
27c868c2
MW		 1430#define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1431#define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1432#define EVEN_PARITY 0x1000 /* Select Even Parity */
1433#define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1434#define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1435#define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1436#define SCAM_EN 0x0080 /* Enable SCAM selection */
1437#define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1438#define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1439#define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1440#define OUR_ID 0x000F /* SCSI ID */
1da177e4
LT		 1441
1442/*
1443 * SCSI_CFG1 Register bit definitions
1444 */
27c868c2
MW		 1445#define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1446#define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1447#define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1448#define FILTER_SEL 0x0C00 /* Filter Period Selection */
1449#define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1450#define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1451#define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1452#define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1453#define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1454#define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1455#define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1456#define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1457#define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1458#define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1459#define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1da177e4
LT		 1460
1461/*
1462 * Addendum for ASC-38C0800 Chip
1463 *
1464 * The ASC-38C1600 Chip uses the same definitions except that the
1465 * bus mode override bits [12:10] have been moved to byte register
1466 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1467 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1468 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1469 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1470 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1471 */
27c868c2
MW		 1472#define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1473#define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1474#define HVD 0x1000 /* HVD Device Detect */
1475#define LVD 0x0800 /* LVD Device Detect */
1476#define SE 0x0400 /* SE Device Detect */
1477#define TERM_LVD 0x00C0 /* LVD Termination Bits */
1478#define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1479#define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1480#define TERM_SE 0x0030 /* SE Termination Bits */
1481#define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1482#define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1483#define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1484#define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1485#define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1486#define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1487#define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1488#define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1da177e4
LT		 1489
1490#define CABLE_ILLEGAL_A 0x7
1491 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1492
1493#define CABLE_ILLEGAL_B 0xB
1494 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1495
1496/*
1497 * MEM_CFG Register bit definitions
1498 */
27c868c2
MW		 1499#define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1500#define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1501#define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1502#define RAM_SZ_2KB 0x00 /* 2 KB */
1503#define RAM_SZ_4KB 0x04 /* 4 KB */
1504#define RAM_SZ_8KB 0x08 /* 8 KB */
1505#define RAM_SZ_16KB 0x0C /* 16 KB */
1506#define RAM_SZ_32KB 0x10 /* 32 KB */
1507#define RAM_SZ_64KB 0x14 /* 64 KB */
1da177e4
LT		 1508
1509/*
1510 * DMA_CFG0 Register bit definitions
1511 *
1512 * This register is only accessible to the host.
1513 */
27c868c2
MW		 1514#define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1515#define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1516#define FIFO_THRESH_16B 0x00 /* 16 bytes */
1517#define FIFO_THRESH_32B 0x20 /* 32 bytes */
1518#define FIFO_THRESH_48B 0x30 /* 48 bytes */
1519#define FIFO_THRESH_64B 0x40 /* 64 bytes */
1520#define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1521#define FIFO_THRESH_96B 0x60 /* 96 bytes */
1522#define FIFO_THRESH_112B 0x70 /* 112 bytes */
1523#define START_CTL 0x0C /* DMA start conditions */
1524#define START_CTL_TH 0x00 /* Wait threshold level (default) */
1525#define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1526#define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1527#define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1528#define READ_CMD 0x03 /* Memory Read Method */
1529#define READ_CMD_MR 0x00 /* Memory Read */
1530#define READ_CMD_MRL 0x02 /* Memory Read Long */
1531#define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1da177e4
LT		 1532
1533/*
1534 * ASC-38C0800 RAM BIST Register bit definitions
1535 */
1536#define RAM_TEST_MODE 0x80
1537#define PRE_TEST_MODE 0x40
1538#define NORMAL_MODE 0x00
1539#define RAM_TEST_DONE 0x10
1540#define RAM_TEST_STATUS 0x0F
1541#define RAM_TEST_HOST_ERROR 0x08
1542#define RAM_TEST_INTRAM_ERROR 0x04
1543#define RAM_TEST_RISC_ERROR 0x02
1544#define RAM_TEST_SCSI_ERROR 0x01
1545#define RAM_TEST_SUCCESS 0x00
1546#define PRE_TEST_VALUE 0x05
1547#define NORMAL_VALUE 0x00
1548
1549/*
1550 * ASC38C1600 Definitions
1551 *
1552 * IOPB_PCI_INT_CFG Bit Field Definitions
1553 */
1554
27c868c2 1555#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1da177e4
LT		 1556
1557/*
1558 * Bit 1 can be set to change the interrupt for the Function to operate in
1559 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1560 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1561 * mode, otherwise the operating mode is undefined.
1562 */
1563#define TOTEMPOLE 0x02
1564
1565/*
1566 * Bit 0 can be used to change the Int Pin for the Function. The value is
1567 * 0 by default for both Functions with Function 0 using INT A and Function
1568 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1569 * INT A is used.
1570 *
1571 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1572 * value specified in the PCI Configuration Space.
1573 */
1574#define INTAB 0x01
1575
1da177e4
LT		 1576/*
1577 * Adv Library Status Definitions
1578 */
1579#define ADV_TRUE 1
1580#define ADV_FALSE 0
1da177e4
LT		 1581#define ADV_SUCCESS 1
1582#define ADV_BUSY 0
1583#define ADV_ERROR (-1)
1584
1da177e4
LT		 1585/*
1586 * ADV_DVC_VAR 'warn_code' values
1587 */
27c868c2
MW		 1588#define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1589#define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1590#define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
27c868c2 1591#define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1da177e4 1592
27c868c2
MW		 1593#define ADV_MAX_TID 15 /* max. target identifier */
1594#define ADV_MAX_LUN 7 /* max. logical unit number */
1da177e4 1595
1da177e4
LT		 1596/*
1597 * Fixed locations of microcode operating variables.
1598 */
27c868c2
MW		 1599#define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1600#define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1601#define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1602#define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1603#define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1604#define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1605#define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1606#define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1607#define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1608#define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1609#define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1610#define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1611#define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1da177e4
LT		 1612#define ASC_MC_CHIP_TYPE 0x009A
1613#define ASC_MC_INTRB_CODE 0x009B
1614#define ASC_MC_WDTR_ABLE 0x009C
1615#define ASC_MC_SDTR_ABLE 0x009E
1616#define ASC_MC_TAGQNG_ABLE 0x00A0
1617#define ASC_MC_DISC_ENABLE 0x00A2
1618#define ASC_MC_IDLE_CMD_STATUS 0x00A4
1619#define ASC_MC_IDLE_CMD 0x00A6
1620#define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1621#define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1622#define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1623#define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1624#define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1625#define ASC_MC_SDTR_DONE 0x00B6
1626#define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1627#define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1628#define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
27c868c2 1629#define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1da177e4 1630#define ASC_MC_WDTR_DONE 0x0124
27c868c2 1631#define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1da177e4
LT		 1632#define ASC_MC_ICQ 0x0160
1633#define ASC_MC_IRQ 0x0164
1634#define ASC_MC_PPR_ABLE 0x017A
1635
1636/*
1637 * BIOS LRAM variable absolute offsets.
1638 */
1639#define BIOS_CODESEG 0x54
1640#define BIOS_CODELEN 0x56
1641#define BIOS_SIGNATURE 0x58
1642#define BIOS_VERSION 0x5A
1643
1644/*
1645 * Microcode Control Flags
1646 *
1647 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1648 * and handled by the microcode.
1649 */
27c868c2
MW		 1650#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1651#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1da177e4
LT		 1652
1653/*
1654 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1655 */
1656#define HSHK_CFG_WIDE_XFR 0x8000
1657#define HSHK_CFG_RATE 0x0F00
1658#define HSHK_CFG_OFFSET 0x001F
1659
27c868c2
MW		 1660#define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1661#define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1662#define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1663#define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1664
1665#define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1666#define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1667#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1668#define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1669#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1670
1671#define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1672#define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1673#define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1674#define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1675#define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1da177e4
LT		 1676/*
1677 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1678 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1679 */
27c868c2
MW		 1680#define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1681#define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1da177e4
LT		 1682
1683/*
1684 * All fields here are accessed by the board microcode and need to be
1685 * little-endian.
1686 */
27c868c2 1687typedef struct adv_carr_t {
98b96a7d
HR		 1688 __le32 carr_va; /* Carrier Virtual Address */
1689 __le32 carr_pa; /* Carrier Physical Address */
9fef6ba4 1690 __le32 areq_vpa; /* ADV_SCSI_REQ_Q Virtual or Physical Address */
27c868c2
MW		 1691 /*
1692 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1693 *
1694 * next_vpa [3:1] Reserved Bits
1695 * next_vpa [0] Done Flag set in Response Queue.
1696 */
98b96a7d 1697 __le32 next_vpa;
1da177e4
LT		 1698} ADV_CARR_T;
1699
1700/*
1701 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1702 */
1703#define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1704
1705#define ASC_RQ_DONE 0x00000001
1706#define ASC_RQ_GOOD 0x00000002
1707#define ASC_CQ_STOPPER 0x00000000
1708
1709#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1710
98b96a7d
HR		 1711/*
1712 * Each carrier is 64 bytes, and we need three additional
1713 * carrier for icq, irq, and the termination carrier.
1714 */
1715#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1da177e4
LT		 1716
1717#define ADV_CARRIER_BUFSIZE \
98b96a7d 1718 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1da177e4
LT		 1719
1720/*
9fef6ba4 1721 * ADV_SCSI_REQ_Q 'a_flag' definitions
1da177e4
LT		 1722 *
1723 * The Adv Library should limit use to the lower nibble (4 bits) of
1724 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1725 */
27c868c2
MW		 1726#define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1727#define ADV_SCSIQ_DONE 0x02 /* request done */
1728#define ADV_DONT_RETRY 0x08 /* don't do retry */
1da177e4 1729
27c868c2
MW		 1730#define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1731#define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1732#define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1da177e4
LT		 1733
1734/*
1735 * Adapter temporary configuration structure
1736 *
1737 * This structure can be discarded after initialization. Don't add
1738 * fields here needed after initialization.
1739 *
1740 * Field naming convention:
1741 *
1742 * *_enable indicates the field enables or disables a feature. The
1743 * value of the field is never reset.
1744 */
1745typedef struct adv_dvc_cfg {
27c868c2
MW		 1746 ushort disc_enable; /* enable disconnection */
1747 uchar chip_version; /* chip version */
1748 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
27c868c2
MW		 1749 ushort control_flag; /* Microcode Control Flag */
1750 ushort mcode_date; /* Microcode date */
1751 ushort mcode_version; /* Microcode version */
27c868c2
MW		 1752 ushort serial1; /* EEPROM serial number word 1 */
1753 ushort serial2; /* EEPROM serial number word 2 */
1754 ushort serial3; /* EEPROM serial number word 3 */
1da177e4
LT		 1755} ADV_DVC_CFG;
1756
1757struct adv_dvc_var;
1758struct adv_scsi_req_q;
1759
0ce53822 1760typedef struct adv_sg_block {
27c868c2
MW		 1761 uchar reserved1;
1762 uchar reserved2;
1763 uchar reserved3;
1764 uchar sg_cnt; /* Valid entries in block. */
0ce53822 1765 __le32 sg_ptr; /* Pointer to next sg block. */
27c868c2 1766 struct {
0ce53822
HR		 1767 __le32 sg_addr; /* SG element address. */
1768 __le32 sg_count; /* SG element count. */
27c868c2 1769 } sg_list[NO_OF_SG_PER_BLOCK];
1da177e4
LT		 1770} ADV_SG_BLOCK;
1771
1772/*
1773 * ADV_SCSI_REQ_Q - microcode request structure
1774 *
1775 * All fields in this structure up to byte 60 are used by the microcode.
1776 * The microcode makes assumptions about the size and ordering of fields
1777 * in this structure. Do not change the structure definition here without
1778 * coordinating the change with the microcode.
1779 *
1780 * All fields accessed by microcode must be maintained in little_endian
1781 * order.
1782 */
1783typedef struct adv_scsi_req_q {
27c868c2
MW		 1784 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1785 uchar target_cmd;
1786 uchar target_id; /* Device target identifier. */
1787 uchar target_lun; /* Device target logical unit number. */
95cfab6c
HR		 1788 __le32 data_addr; /* Data buffer physical address. */
1789 __le32 data_cnt; /* Data count. Ucode sets to residual. */
811ddc05 1790 __le32 sense_addr;
98b96a7d 1791 __le32 carr_pa;
27c868c2
MW		 1792 uchar mflag;
1793 uchar sense_len;
1794 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1795 uchar scsi_cntl;
1796 uchar done_status; /* Completion status. */
1797 uchar scsi_status; /* SCSI status byte. */
1798 uchar host_status; /* Ucode host status. */
1799 uchar sg_working_ix;
1800 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
95cfab6c 1801 __le32 sg_real_addr; /* SG list physical address. */
98b96a7d 1802 __le32 scsiq_rptr;
27c868c2 1803 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
98b96a7d
HR		 1804 __le32 scsiq_ptr;
1805 __le32 carr_va;
27c868c2
MW		 1806 /*
1807 * End of microcode structure - 60 bytes. The rest of the structure
1808 * is used by the Adv Library and ignored by the microcode.
1809 */
9c17c62a 1810 u32 srb_tag;
27c868c2 1811 uchar a_flag;
98b96a7d
HR		 1812 uchar pad[3]; /* Pad out to a word boundary. */
1813 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1da177e4
LT		 1814} ADV_SCSI_REQ_Q;
1815
98d41c29
MW		 1816/*
1817 * The following two structures are used to process Wide Board requests.
1818 *
1819 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
9c17c62a
HR		 1820 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1821 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1822 * to the Mid-Level SCSI request structure.
98d41c29
MW		 1823 *
1824 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1825 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1826 * up to 255 scatter-gather elements may be used per request or
1827 * ADV_SCSI_REQ_Q.
1828 *
1829 * Both structures must be 32 byte aligned.
1830 */
1831typedef struct adv_sgblk {
1832 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
0ce53822 1833 dma_addr_t sg_addr; /* Physical address */
98d41c29
MW		 1834 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1835} adv_sgblk_t;
1836
1837typedef struct adv_req {
1838 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
4b47e464 1839 uchar align[24]; /* Request structure padding. */
98d41c29 1840 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
4b47e464 1841 dma_addr_t req_addr;
98d41c29 1842 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
4b47e464 1843} adv_req_t __aligned(32);
98d41c29
MW		 1844
1845/*
1846 * Adapter operation variable structure.
1847 *
1848 * One structure is required per host adapter.
1849 *
1850 * Field naming convention:
1851 *
1852 * *_able indicates both whether a feature should be enabled or disabled
1853 * and whether a device isi capable of the feature. At initialization
1854 * this field may be set, but later if a device is found to be incapable
1855 * of the feature, the field is cleared.
1856 */
1857typedef struct adv_dvc_var {
1858 AdvPortAddr iop_base; /* I/O port address */
1859 ushort err_code; /* fatal error code */
1860 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1861 ushort wdtr_able; /* try WDTR for a device */
1862 ushort sdtr_able; /* try SDTR for a device */
1863 ushort ultra_able; /* try SDTR Ultra speed for a device */
1864 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1865 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1866 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1867 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1868 ushort tagqng_able; /* try tagged queuing with a device */
1869 ushort ppr_able; /* PPR message capable per TID bitmask. */
1870 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1871 ushort start_motor; /* start motor command allowed */
1872 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1873 uchar chip_no; /* should be assigned by caller */
1874 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1875 ushort no_scam; /* scam_tolerant of EEPROM */
1876 struct asc_board *drv_ptr; /* driver pointer to private structure */
1877 uchar chip_scsi_id; /* chip SCSI target ID */
1878 uchar chip_type;
1879 uchar bist_err_code;
98b96a7d 1880 ADV_CARR_T *carrier;
98d41c29 1881 ADV_CARR_T *carr_freelist; /* Carrier free list. */
98b96a7d 1882 dma_addr_t carrier_addr;
98d41c29
MW		 1883 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1884 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1885 ushort carr_pending_cnt; /* Count of pending carriers. */
98d41c29
MW		 1886 /*
1887 * Note: The following fields will not be used after initialization. The
1888 * driver may discard the buffer after initialization is done.
1889 */
1890 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1891} ADV_DVC_VAR;
1892
1da177e4
LT		 1893/*
1894 * Microcode idle loop commands
1895 */
1896#define IDLE_CMD_COMPLETED 0
1897#define IDLE_CMD_STOP_CHIP 0x0001
1898#define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1899#define IDLE_CMD_SEND_INT 0x0004
1900#define IDLE_CMD_ABORT 0x0008
1901#define IDLE_CMD_DEVICE_RESET 0x0010
27c868c2
MW		 1902#define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1903#define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1da177e4
LT		 1904#define IDLE_CMD_SCSIREQ 0x0080
1905
1906#define IDLE_CMD_STATUS_SUCCESS 0x0001
1907#define IDLE_CMD_STATUS_FAILURE 0x0002
1908
1909/*
1910 * AdvSendIdleCmd() flag definitions.
1911 */
1912#define ADV_NOWAIT 0x01
1913
1914/*
1915 * Wait loop time out values.
1916 */
27c868c2
MW		 1917#define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1918#define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
27c868c2 1919#define SCSI_MAX_RETRY 10 /* retry count */
1da177e4 1920
27c868c2
MW		 1921#define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1922#define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1923#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1924#define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1da177e4 1925
27c868c2 1926#define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1da177e4 1927
1da177e4
LT		 1928/* Read byte from a register. */
1929#define AdvReadByteRegister(iop_base, reg_off) \
1930 (ADV_MEM_READB((iop_base) + (reg_off)))
1931
1932/* Write byte to a register. */
1933#define AdvWriteByteRegister(iop_base, reg_off, byte) \
1934 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1935
1936/* Read word (2 bytes) from a register. */
1937#define AdvReadWordRegister(iop_base, reg_off) \
1938 (ADV_MEM_READW((iop_base) + (reg_off)))
1939
1940/* Write word (2 bytes) to a register. */
1941#define AdvWriteWordRegister(iop_base, reg_off, word) \
1942 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1943
1944/* Write dword (4 bytes) to a register. */
1945#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1946 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1947
1948/* Read byte from LRAM. */
1949#define AdvReadByteLram(iop_base, addr, byte) \
1950do { \
1951 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1952 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1953} while (0)
1954
1955/* Write byte to LRAM. */
1956#define AdvWriteByteLram(iop_base, addr, byte) \
1957 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1958 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1959
1960/* Read word (2 bytes) from LRAM. */
1961#define AdvReadWordLram(iop_base, addr, word) \
1962do { \
1963 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1964 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1965} while (0)
1966
1967/* Write word (2 bytes) to LRAM. */
1968#define AdvWriteWordLram(iop_base, addr, word) \
1969 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1970 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1971
1972/* Write little-endian double word (4 bytes) to LRAM */
1973/* Because of unspecified C language ordering don't use auto-increment. */
1974#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
1975 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1976 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1977 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
1978 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
1979 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1980 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
1981
1982/* Read word (2 bytes) from LRAM assuming that the address is already set. */
1983#define AdvReadWordAutoIncLram(iop_base) \
1984 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
1985
1986/* Write word (2 bytes) to LRAM assuming that the address is already set. */
1987#define AdvWriteWordAutoIncLram(iop_base, word) \
1988 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1989
1da177e4
LT		 1990/*
1991 * Define macro to check for Condor signature.
1992 *
1993 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
1994 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
1995 */
1996#define AdvFindSignature(iop_base) \
1997 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
1998 ADV_CHIP_ID_BYTE) && \
1999 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2000 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2001
2002/*
2003 * Define macro to Return the version number of the chip at 'iop_base'.
2004 *
2005 * The second parameter 'bus_type' is currently unused.
2006 */
2007#define AdvGetChipVersion(iop_base, bus_type) \
2008 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2009
2010/*
9c17c62a 2011 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
9fef6ba4 2012 * match the ADV_SCSI_REQ_Q 'srb_tag' field.
1da177e4
LT		 2013 *
2014 * If the request has not yet been sent to the device it will simply be
2015 * aborted from RISC memory. If the request is disconnected it will be
2016 * aborted on reselection by sending an Abort Message to the target ID.
2017 *
2018 * Return value:
2019 * ADV_TRUE(1) - Queue was successfully aborted.
2020 * ADV_FALSE(0) - Queue was not found on the active queue list.
2021 */
9c17c62a
HR		 2022#define AdvAbortQueue(asc_dvc, srb_tag) \
2023 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2024 (ADV_DCNT) (srb_tag))
1da177e4
LT		 2025
2026/*
2027 * Send a Bus Device Reset Message to the specified target ID.
2028 *
2029 * All outstanding commands will be purged if sending the
2030 * Bus Device Reset Message is successful.
2031 *
2032 * Return Value:
2033 * ADV_TRUE(1) - All requests on the target are purged.
2034 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2035 * are not purged.
2036 */
2037#define AdvResetDevice(asc_dvc, target_id) \
9c17c62a
HR		 2038 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2039 (ADV_DCNT) (target_id))
1da177e4
LT		 2040
2041/*
2042 * SCSI Wide Type definition.
2043 */
2044#define ADV_SCSI_BIT_ID_TYPE ushort
2045
2046/*
2047 * AdvInitScsiTarget() 'cntl_flag' options.
2048 */
2049#define ADV_SCAN_LUN 0x01
2050#define ADV_CAPINFO_NOLUN 0x02
2051
2052/*
2053 * Convert target id to target id bit mask.
2054 */
2055#define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2056
2057/*
9fef6ba4 2058 * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values.
1da177e4
LT		 2059 */
2060
27c868c2 2061#define QD_NO_STATUS 0x00 /* Request not completed yet. */
1da177e4
LT		 2062#define QD_NO_ERROR 0x01
2063#define QD_ABORTED_BY_HOST 0x02
2064#define QD_WITH_ERROR 0x04
2065
2066#define QHSTA_NO_ERROR 0x00
2067#define QHSTA_M_SEL_TIMEOUT 0x11
2068#define QHSTA_M_DATA_OVER_RUN 0x12
2069#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2070#define QHSTA_M_QUEUE_ABORTED 0x15
27c868c2
MW		 2071#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2072#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2073#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2074#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2075#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2076#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2077#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
1da177e4 2078/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
27c868c2
MW		 2079#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2080#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2081#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2082#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2083#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2084#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2085#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2086#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
1da177e4
LT		 2087#define QHSTA_M_WTM_TIMEOUT 0x41
2088#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2089#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2090#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
27c868c2
MW		 2091#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2092#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2093#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
1da177e4 2094
1da177e4 2095/* Return the address that is aligned at the next doubleword >= to 'addr'. */
1da177e4
LT		 2096#define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2097
2098/*
2099 * Total contiguous memory needed for driver SG blocks.
2100 *
2101 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2102 * number of scatter-gather elements the driver supports in a
2103 * single request.
2104 */
2105
2106#define ADV_SG_LIST_MAX_BYTE_SIZE \
2107 (sizeof(ADV_SG_BLOCK) * \
2108 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2109
d2411495 2110/* struct asc_board flags */
27c868c2 2111#define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
1da177e4
LT		 2112
2113#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
1da177e4 2114
27c868c2 2115#define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
1da177e4 2116
27c868c2 2117#define ASC_INFO_SIZE 128 /* advansys_info() line size */
1da177e4 2118
1da177e4
LT		 2119/* Asc Library return codes */
2120#define ASC_TRUE 1
2121#define ASC_FALSE 0
2122#define ASC_NOERROR 1
2123#define ASC_BUSY 0
2124#define ASC_ERROR (-1)
2125
2126/* struct scsi_cmnd function return codes */
2127#define STATUS_BYTE(byte) (byte)
2128#define MSG_BYTE(byte) ((byte) << 8)
2129#define HOST_BYTE(byte) ((byte) << 16)
2130#define DRIVER_BYTE(byte) ((byte) << 24)
2131
d2411495 2132#define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
1da177e4 2133#ifndef ADVANSYS_STATS
27c868c2 2134#define ASC_STATS_ADD(shost, counter, count)
1da177e4 2135#else /* ADVANSYS_STATS */
27c868c2 2136#define ASC_STATS_ADD(shost, counter, count) \
d2411495 2137 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
1da177e4
LT		 2138#endif /* ADVANSYS_STATS */
2139
1da177e4
LT		 2140/* If the result wraps when calculating tenths, return 0. */
2141#define ASC_TENTHS(num, den) \
2142 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2143 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2144
2145/*
2146 * Display a message to the console.
2147 */
2148#define ASC_PRINT(s) \
2149 { \
2150 printk("advansys: "); \
2151 printk(s); \
2152 }
2153
2154#define ASC_PRINT1(s, a1) \
2155 { \
2156 printk("advansys: "); \
2157 printk((s), (a1)); \
2158 }
2159
2160#define ASC_PRINT2(s, a1, a2) \
2161 { \
2162 printk("advansys: "); \
2163 printk((s), (a1), (a2)); \
2164 }
2165
2166#define ASC_PRINT3(s, a1, a2, a3) \
2167 { \
2168 printk("advansys: "); \
2169 printk((s), (a1), (a2), (a3)); \
2170 }
2171
2172#define ASC_PRINT4(s, a1, a2, a3, a4) \
2173 { \
2174 printk("advansys: "); \
2175 printk((s), (a1), (a2), (a3), (a4)); \
2176 }
2177
1da177e4
LT		 2178#ifndef ADVANSYS_DEBUG
2179
b352f923 2180#define ASC_DBG(lvl, s...)
1da177e4 2181#define ASC_DBG_PRT_SCSI_HOST(lvl, s)
1da177e4
LT		 2182#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2183#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2184#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2185#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2186#define ASC_DBG_PRT_HEX(lvl, name, start, length)
2187#define ASC_DBG_PRT_CDB(lvl, cdb, len)
2188#define ASC_DBG_PRT_SENSE(lvl, sense, len)
2189#define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2190
2191#else /* ADVANSYS_DEBUG */
2192
2193/*
2194 * Debugging Message Levels:
2195 * 0: Errors Only
2196 * 1: High-Level Tracing
2197 * 2-N: Verbose Tracing
2198 */
2199
b352f923
MW		 2200#define ASC_DBG(lvl, format, arg...) { \
2201 if (asc_dbglvl >= (lvl)) \
2202 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
cadbd4a5 2203 __func__ , ## arg); \
b352f923 2204}
1da177e4
LT		 2205
2206#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2207 { \
2208 if (asc_dbglvl >= (lvl)) { \
2209 asc_prt_scsi_host(s); \
2210 } \
2211 }
2212
1da177e4
LT		 2213#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2214 { \
2215 if (asc_dbglvl >= (lvl)) { \
2216 asc_prt_asc_scsi_q(scsiqp); \
2217 } \
2218 }
2219
2220#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2221 { \
2222 if (asc_dbglvl >= (lvl)) { \
2223 asc_prt_asc_qdone_info(qdone); \
2224 } \
2225 }
2226
2227#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2228 { \
2229 if (asc_dbglvl >= (lvl)) { \
2230 asc_prt_adv_scsi_req_q(scsiqp); \
2231 } \
2232 }
2233
2234#define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2235 { \
2236 if (asc_dbglvl >= (lvl)) { \
2237 asc_prt_hex((name), (start), (length)); \
2238 } \
2239 }
2240
2241#define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2242 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2243
2244#define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2245 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2246
2247#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2248 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2249#endif /* ADVANSYS_DEBUG */
2250
1da177e4
LT		 2251#ifdef ADVANSYS_STATS
2252
2253/* Per board statistics structure */
2254struct asc_stats {
27c868c2 2255 /* Driver Entrypoint Statistics */
95cfab6c
HR		 2256 unsigned int queuecommand; /* # calls to advansys_queuecommand() */
2257 unsigned int reset; /* # calls to advansys_eh_bus_reset() */
2258 unsigned int biosparam; /* # calls to advansys_biosparam() */
2259 unsigned int interrupt; /* # advansys_interrupt() calls */
2260 unsigned int callback; /* # calls to asc/adv_isr_callback() */
2261 unsigned int done; /* # calls to request's scsi_done function */
2262 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2263 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2264 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
27c868c2 2265 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
95cfab6c
HR		 2266 unsigned int exe_noerror; /* # ASC_NOERROR returns. */
2267 unsigned int exe_busy; /* # ASC_BUSY returns. */
2268 unsigned int exe_error; /* # ASC_ERROR returns. */
2269 unsigned int exe_unknown; /* # unknown returns. */
27c868c2 2270 /* Data Transfer Statistics */
95cfab6c
HR		 2271 unsigned int xfer_cnt; /* # I/O requests received */
2272 unsigned int xfer_elem; /* # scatter-gather elements */
2273 unsigned int xfer_sect; /* # 512-byte blocks */
1da177e4
LT		 2274};
2275#endif /* ADVANSYS_STATS */
2276
1da177e4
LT		 2277/*
2278 * Structure allocated for each board.
2279 *
8dfb5379 2280 * This structure is allocated by scsi_host_alloc() at the end
1da177e4
LT		 2281 * of the 'Scsi_Host' structure starting at the 'hostdata'
2282 * field. It is guaranteed to be allocated from DMA-able memory.
2283 */
d2411495 2284struct asc_board {
394dbf3f 2285 struct device *dev;
9c17c62a 2286 struct Scsi_Host *shost;
27c868c2 2287 uint flags; /* Board flags */
d361db48 2288 unsigned int irq;
27c868c2
MW		 2289 union {
2290 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2291 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2292 } dvc_var;
2293 union {
2294 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2295 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2296 } dvc_cfg;
2297 ushort asc_n_io_port; /* Number I/O ports. */
27c868c2 2298 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
27c868c2
MW		 2299 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2300 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2301 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2302 union {
2303 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2304 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2305 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2306 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2307 } eep_config;
27c868c2 2308 /* /proc/scsi/advansys/[0...] */
1da177e4 2309#ifdef ADVANSYS_STATS
27c868c2
MW		 2310 struct asc_stats asc_stats; /* Board statistics */
2311#endif /* ADVANSYS_STATS */
2312 /*
2313 * The following fields are used only for Narrow Boards.
2314 */
27c868c2
MW		 2315 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2316 /*
2317 * The following fields are used only for Wide Boards.
2318 */
2319 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2320 ushort ioport; /* I/O Port address. */
27c868c2 2321 adv_req_t *adv_reqp; /* Request structures. */
4b47e464
HR		 2322 dma_addr_t adv_reqp_addr;
2323 size_t adv_reqp_size;
0ce53822 2324 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
27c868c2
MW		 2325 ushort bios_signature; /* BIOS Signature. */
2326 ushort bios_version; /* BIOS Version. */
2327 ushort bios_codeseg; /* BIOS Code Segment. */
2328 ushort bios_codelen; /* BIOS Code Segment Length. */
d2411495 2329};
1da177e4 2330
d10fb2c7
MW		 2331#define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2332 dvc_var.asc_dvc_var)
13ac2d9c
MW		 2333#define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2334 dvc_var.adv_dvc_var)
2335#define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2336
1da177e4 2337#ifdef ADVANSYS_DEBUG
27c868c2 2338static int asc_dbglvl = 3;
1da177e4 2339
1da177e4 2340/*
51219358 2341 * asc_prt_asc_dvc_var()
1da177e4 2342 */
51219358 2343static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
1da177e4 2344{
51219358 2345 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
27c868c2 2346
51219358
MW		 2347 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2348 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2349
2350 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2351 (unsigned)h->init_sdtr);
2352
2353 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2354 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2355 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2356 (unsigned)h->chip_no);
2357
2358 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2359 "%u,\n", (unsigned)h->queue_full_or_busy,
2360 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2361
2362 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2363 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2364 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2365 (unsigned)h->in_critical_cnt);
2366
2367 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2368 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2369 (unsigned)h->init_state, (unsigned)h->no_scam,
2370 (unsigned)h->pci_fix_asyn_xfer);
2371
d361db48 2372 printk(" cfg 0x%lx\n", (ulong)h->cfg);
1da177e4
LT		 2373}
2374
51219358
MW		 2375/*
2376 * asc_prt_asc_dvc_cfg()
2377 */
2378static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
6ed1ef07 2379{
51219358 2380 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
6ed1ef07 2381
51219358
MW		 2382 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2383 h->can_tagged_qng, h->cmd_qng_enabled);
2384 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2385 h->disc_enable, h->sdtr_enable);
6ed1ef07 2386
b08fc565
MW		 2387 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2388 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2389 h->isa_dma_channel, h->chip_version);
51219358 2390
d10fb2c7
MW		 2391 printk(" mcode_date 0x%x, mcode_version %d\n",
2392 h->mcode_date, h->mcode_version);
6ed1ef07
MW		 2393}
2394
1da177e4 2395/*
51219358 2396 * asc_prt_adv_dvc_var()
1da177e4 2397 *
51219358 2398 * Display an ADV_DVC_VAR structure.
1da177e4 2399 */
51219358 2400static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
1da177e4 2401{
51219358 2402 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
27c868c2 2403
51219358
MW		 2404 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2405 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
1da177e4 2406
b352f923
MW		 2407 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2408 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
1da177e4 2409
d361db48
MW		 2410 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2411 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
1da177e4 2412
98b96a7d 2413 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
51219358 2414 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
98b96a7d 2415 h->carr_freelist);
1da177e4 2416
98b96a7d 2417 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
1da177e4 2418
51219358
MW		 2419 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2420 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
1da177e4 2421
51219358
MW		 2422 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2423 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2424}
1da177e4 2425
51219358
MW		 2426/*
2427 * asc_prt_adv_dvc_cfg()
2428 *
2429 * Display an ADV_DVC_CFG structure.
2430 */
2431static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2432{
2433 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
27c868c2 2434
51219358
MW		 2435 printk(" disc_enable 0x%x, termination 0x%x\n",
2436 h->disc_enable, h->termination);
1da177e4 2437
51219358
MW		 2438 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2439 h->chip_version, h->mcode_date);
27c868c2 2440
b352f923
MW		 2441 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2442 h->mcode_version, h->control_flag);
1da177e4
LT		 2443}
2444
2445/*
b352f923 2446 * asc_prt_scsi_host()
1da177e4 2447 */
b352f923 2448static void asc_prt_scsi_host(struct Scsi_Host *s)
1da177e4 2449{
b352f923 2450 struct asc_board *boardp = shost_priv(s);
51219358 2451
71610f55 2452 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
50d14a70 2453 printk(" host_busy %u, host_no %d,\n",
74665016 2454 atomic_read(&s->host_busy), s->host_no);
51219358 2455
b352f923
MW		 2456 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2457 (ulong)s->base, (ulong)s->io_port, boardp->irq);
51219358 2458
b352f923
MW		 2459 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2460 s->dma_channel, s->this_id, s->can_queue);
1da177e4 2461
b352f923
MW		 2462 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2463 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
27c868c2 2464
b352f923
MW		 2465 if (ASC_NARROW_BOARD(boardp)) {
2466 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2467 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2468 } else {
2469 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2470 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
074c8fe4 2471 }
1da177e4
LT		 2472}
2473
51219358
MW		 2474/*
2475 * asc_prt_hex()
2476 *
2477 * Print hexadecimal output in 4 byte groupings 32 bytes
2478 * or 8 double-words per line.
2479 */
2480static void asc_prt_hex(char *f, uchar *s, int l)
47d853cc 2481{
51219358
MW		 2482 int i;
2483 int j;
2484 int k;
2485 int m;
47d853cc 2486
51219358
MW		 2487 printk("%s: (%d bytes)\n", f, l);
2488
2489 for (i = 0; i < l; i += 32) {
2490
2491 /* Display a maximum of 8 double-words per line. */
2492 if ((k = (l - i) / 4) >= 8) {
2493 k = 8;
2494 m = 0;
47d853cc 2495 } else {
51219358 2496 m = (l - i) % 4;
47d853cc
MW		 2497 }
2498
51219358
MW		 2499 for (j = 0; j < k; j++) {
2500 printk(" %2.2X%2.2X%2.2X%2.2X",
2501 (unsigned)s[i + (j * 4)],
2502 (unsigned)s[i + (j * 4) + 1],
2503 (unsigned)s[i + (j * 4) + 2],
2504 (unsigned)s[i + (j * 4) + 3]);
47d853cc 2505 }
47d853cc 2506
51219358
MW		 2507 switch (m) {
2508 case 0:
2509 default:
2510 break;
2511 case 1:
2512 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2513 break;
2514 case 2:
2515 printk(" %2.2X%2.2X",
2516 (unsigned)s[i + (j * 4)],
2517 (unsigned)s[i + (j * 4) + 1]);
2518 break;
2519 case 3:
2520 printk(" %2.2X%2.2X%2.2X",
2521 (unsigned)s[i + (j * 4) + 1],
2522 (unsigned)s[i + (j * 4) + 2],
2523 (unsigned)s[i + (j * 4) + 3]);
2524 break;
2525 }
47d853cc 2526
51219358 2527 printk("\n");
47d853cc
MW		 2528 }
2529}
b352f923
MW		 2530
2531/*
2532 * asc_prt_asc_scsi_q()
2533 */
2534static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2535{
2536 ASC_SG_HEAD *sgp;
2537 int i;
2538
2539 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2540
2541 printk
9c17c62a
HR		 2542 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2543 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
b352f923
MW		 2544 q->q2.tag_code);
2545
2546 printk
2547 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2548 (ulong)le32_to_cpu(q->q1.data_addr),
2549 (ulong)le32_to_cpu(q->q1.data_cnt),
2550 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2551
2552 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2553 (ulong)q->cdbptr, q->q2.cdb_len,
2554 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2555
2556 if (q->sg_head) {
2557 sgp = q->sg_head;
2558 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2559 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2560 sgp->queue_cnt);
2561 for (i = 0; i < sgp->entry_cnt; i++) {
2562 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2563 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2564 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2565 }
2566
2567 }
2568}
2569
2570/*
2571 * asc_prt_asc_qdone_info()
2572 */
2573static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2574{
2575 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
9c17c62a
HR		 2576 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2577 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
b352f923
MW		 2578 q->d2.tag_code);
2579 printk
2580 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2581 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2582}
2583
2584/*
2585 * asc_prt_adv_sgblock()
2586 *
2587 * Display an ADV_SG_BLOCK structure.
2588 */
2589static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2590{
2591 int i;
2592
0ce53822 2593 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
b352f923
MW		 2594 (ulong)b, sgblockno);
2595 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2596 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2597 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2598 if (b->sg_ptr != 0)
2599 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2600 for (i = 0; i < b->sg_cnt; i++) {
2601 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2602 i, (ulong)b->sg_list[i].sg_addr,
2603 (ulong)b->sg_list[i].sg_count);
2604 }
2605}
2606
2607/*
2608 * asc_prt_adv_scsi_req_q()
2609 *
2610 * Display an ADV_SCSI_REQ_Q structure.
2611 */
2612static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2613{
2614 int sg_blk_cnt;
0ce53822
HR		 2615 struct adv_sg_block *sg_ptr;
2616 adv_sgblk_t *sgblkp;
b352f923
MW		 2617
2618 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2619
9c17c62a
HR		 2620 printk(" target_id %u, target_lun %u, srb_tag 0x%x, a_flag 0x%x\n",
2621 q->target_id, q->target_lun, q->srb_tag, q->a_flag);
b352f923 2622
98b96a7d
HR		 2623 printk(" cntl 0x%x, data_addr 0x%lx\n",
2624 q->cntl, (ulong)le32_to_cpu(q->data_addr));
b352f923
MW		 2625
2626 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2627 (ulong)le32_to_cpu(q->data_cnt),
2628 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2629
2630 printk
2631 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2632 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2633
2634 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2635 q->sg_working_ix, q->target_cmd);
2636
2637 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2638 (ulong)le32_to_cpu(q->scsiq_rptr),
2639 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2640
2641 /* Display the request's ADV_SG_BLOCK structures. */
2642 if (q->sg_list_ptr != NULL) {
0ce53822 2643 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
b352f923 2644 sg_blk_cnt = 0;
0ce53822
HR		 2645 while (sgblkp) {
2646 sg_ptr = &sgblkp->sg_block;
b352f923
MW		 2647 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2648 if (sg_ptr->sg_ptr == 0) {
2649 break;
2650 }
0ce53822 2651 sgblkp = sgblkp->next_sgblkp;
b352f923
MW		 2652 sg_blk_cnt++;
2653 }
2654 }
2655}
51219358 2656#endif /* ADVANSYS_DEBUG */
47d853cc 2657
1da177e4 2658/*
51219358 2659 * advansys_info()
47d853cc 2660 *
51219358
MW		 2661 * Return suitable for printing on the console with the argument
2662 * adapter's configuration information.
2663 *
2664 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2665 * otherwise the static 'info' array will be overrun.
1da177e4 2666 */
51219358 2667static const char *advansys_info(struct Scsi_Host *shost)
1da177e4 2668{
51219358 2669 static char info[ASC_INFO_SIZE];
d2411495 2670 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2671 ASC_DVC_VAR *asc_dvc_varp;
2672 ADV_DVC_VAR *adv_dvc_varp;
2673 char *busname;
2674 char *widename = NULL;
1da177e4 2675
51219358
MW		 2676 if (ASC_NARROW_BOARD(boardp)) {
2677 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
b352f923 2678 ASC_DBG(1, "begin\n");
51219358
MW		 2679 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2680 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2681 ASC_IS_ISAPNP) {
2682 busname = "ISA PnP";
2683 } else {
2684 busname = "ISA";
2685 }
2686 sprintf(info,
2687 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2688 ASC_VERSION, busname,
2689 (ulong)shost->io_port,
2690 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
d361db48 2691 boardp->irq, shost->dma_channel);
51219358
MW		 2692 } else {
2693 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2694 busname = "VL";
2695 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2696 busname = "EISA";
2697 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2698 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2699 == ASC_IS_PCI_ULTRA) {
2700 busname = "PCI Ultra";
2701 } else {
2702 busname = "PCI";
2703 }
2704 } else {
2705 busname = "?";
9d0e96eb
MW		 2706 shost_printk(KERN_ERR, shost, "unknown bus "
2707 "type %d\n", asc_dvc_varp->bus_type);
51219358
MW		 2708 }
2709 sprintf(info,
2710 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2711 ASC_VERSION, busname, (ulong)shost->io_port,
2712 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
d361db48 2713 boardp->irq);
51219358
MW		 2714 }
2715 } else {
2716 /*
2717 * Wide Adapter Information
2718 *
2719 * Memory-mapped I/O is used instead of I/O space to access
2720 * the adapter, but display the I/O Port range. The Memory
2721 * I/O address is displayed through the driver /proc file.
2722 */
2723 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2724 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2725 widename = "Ultra-Wide";
2726 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2727 widename = "Ultra2-Wide";
2728 } else {
2729 widename = "Ultra3-Wide";
2730 }
2731 sprintf(info,
2732 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2733 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
d361db48 2734 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
51219358
MW		 2735 }
2736 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
b352f923 2737 ASC_DBG(1, "end\n");
51219358 2738 return info;
47d853cc
MW		 2739}
2740
51219358 2741#ifdef CONFIG_PROC_FS
47d853cc
MW		 2742
2743/*
51219358 2744 * asc_prt_board_devices()
47d853cc 2745 *
51219358 2746 * Print driver information for devices attached to the board.
47d853cc 2747 */
b59fb6fd 2748static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
47d853cc 2749{
d2411495 2750 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2751 int chip_scsi_id;
2752 int i;
47d853cc 2753
b59fb6fd
AV		 2754 seq_printf(m,
2755 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2756 shost->host_no);
47d853cc 2757
51219358
MW		 2758 if (ASC_NARROW_BOARD(boardp)) {
2759 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2760 } else {
2761 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
47d853cc
MW		 2762 }
2763
2f979427 2764 seq_puts(m, "Target IDs Detected:");
51219358 2765 for (i = 0; i <= ADV_MAX_TID; i++) {
b59fb6fd
AV		 2766 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2767 seq_printf(m, " %X,", i);
27c868c2 2768 }
b59fb6fd 2769 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
47d853cc
MW		 2770}
2771
2772/*
51219358 2773 * Display Wide Board BIOS Information.
47d853cc 2774 */
b59fb6fd 2775static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
47d853cc 2776{
d2411495 2777 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2778 ushort major, minor, letter;
2779
2f979427 2780 seq_puts(m, "\nROM BIOS Version: ");
47d853cc
MW		 2781
2782 /*
51219358
MW		 2783 * If the BIOS saved a valid signature, then fill in
2784 * the BIOS code segment base address.
47d853cc 2785 */
51219358 2786 if (boardp->bios_signature != 0x55AA) {
3d30079c
RV		 2787 seq_puts(m, "Disabled or Pre-3.1\n"
2788 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2789 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
51219358
MW		 2790 } else {
2791 major = (boardp->bios_version >> 12) & 0xF;
2792 minor = (boardp->bios_version >> 8) & 0xF;
2793 letter = (boardp->bios_version & 0xFF);
47d853cc 2794
b59fb6fd 2795 seq_printf(m, "%d.%d%c\n",
51219358
MW		 2796 major, minor,
2797 letter >= 26 ? '?' : letter + 'A');
51219358
MW		 2798 /*
2799 * Current available ROM BIOS release is 3.1I for UW
2800 * and 3.2I for U2W. This code doesn't differentiate
2801 * UW and U2W boards.
2802 */
2803 if (major < 3 || (major <= 3 && minor < 1) ||
2804 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3d30079c
RV		 2805 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2806 "ftp://ftp.connectcom.net/pub\n");
51219358
MW		 2807 }
2808 }
1da177e4
LT		 2809}
2810
1da177e4 2811/*
51219358
MW		 2812 * Add serial number to information bar if signature AAh
2813 * is found in at bit 15-9 (7 bits) of word 1.
1da177e4 2814 *
51219358 2815 * Serial Number consists fo 12 alpha-numeric digits.
1da177e4 2816 *
51219358
MW		 2817 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2818 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2819 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2820 * 5 - Product revision (A-J) Word0: " "
1da177e4 2821 *
51219358
MW		 2822 * Signature Word1: 15-9 (7 bits)
2823 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2824 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
1da177e4 2825 *
51219358 2826 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
1da177e4 2827 *
51219358 2828 * Note 1: Only production cards will have a serial number.
1da177e4 2829 *
51219358 2830 * Note 2: Signature is most significant 7 bits (0xFE).
1da177e4 2831 *
51219358 2832 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
1da177e4 2833 */
51219358 2834static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
1da177e4 2835{
51219358 2836 ushort w, num;
27c868c2 2837
51219358
MW		 2838 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2839 return ASC_FALSE;
2840 } else {
2841 /*
2842 * First word - 6 digits.
2843 */
2844 w = serialnum[0];
27c868c2 2845
51219358
MW		 2846 /* Product type - 1st digit. */
2847 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2848 /* Product type is P=Prototype */
2849 *cp += 0x8;
2850 }
2851 cp++;
2852
2853 /* Manufacturing location - 2nd digit. */
2854 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2855
2856 /* Product ID - 3rd, 4th digits. */
2857 num = w & 0x3FF;
2858 *cp++ = '0' + (num / 100);
2859 num %= 100;
2860 *cp++ = '0' + (num / 10);
2861
2862 /* Product revision - 5th digit. */
2863 *cp++ = 'A' + (num % 10);
27c868c2 2864
27c868c2 2865 /*
51219358 2866 * Second word
27c868c2 2867 */
51219358 2868 w = serialnum[1];
27c868c2
MW		 2869
2870 /*
51219358 2871 * Year - 6th digit.
27c868c2 2872 *
51219358
MW		 2873 * If bit 15 of third word is set, then the
2874 * last digit of the year is greater than 7.
27c868c2 2875 */
51219358
MW		 2876 if (serialnum[2] & 0x8000) {
2877 *cp++ = '8' + ((w & 0x1C0) >> 6);
2878 } else {
2879 *cp++ = '0' + ((w & 0x1C0) >> 6);
27c868c2
MW		 2880 }
2881
51219358
MW		 2882 /* Week of year - 7th, 8th digits. */
2883 num = w & 0x003F;
2884 *cp++ = '0' + num / 10;
2885 num %= 10;
2886 *cp++ = '0' + num;
27c868c2
MW		 2887
2888 /*
51219358 2889 * Third word
27c868c2 2890 */
51219358 2891 w = serialnum[2] & 0x7FFF;
1da177e4 2892
51219358
MW		 2893 /* Serial number - 9th digit. */
2894 *cp++ = 'A' + (w / 1000);
27c868c2 2895
51219358
MW		 2896 /* 10th, 11th, 12th digits. */
2897 num = w % 1000;
2898 *cp++ = '0' + num / 100;
2899 num %= 100;
2900 *cp++ = '0' + num / 10;
2901 num %= 10;
2902 *cp++ = '0' + num;
2903
2904 *cp = '\0'; /* Null Terminate the string. */
2905 return ASC_TRUE;
2906 }
1da177e4
LT		 2907}
2908
2909/*
51219358 2910 * asc_prt_asc_board_eeprom()
1da177e4 2911 *
51219358 2912 * Print board EEPROM configuration.
1da177e4 2913 */
b59fb6fd 2914static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 2915{
d2411495 2916 struct asc_board *boardp = shost_priv(shost);
51219358 2917 ASC_DVC_VAR *asc_dvc_varp;
51219358
MW		 2918 ASCEEP_CONFIG *ep;
2919 int i;
2920#ifdef CONFIG_ISA
2921 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2922#endif /* CONFIG_ISA */
2923 uchar serialstr[13];
27c868c2 2924
51219358
MW		 2925 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2926 ep = &boardp->eep_config.asc_eep;
27c868c2 2927
b59fb6fd
AV		 2928 seq_printf(m,
2929 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2930 shost->host_no);
1da177e4 2931
51219358 2932 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
b59fb6fd
AV		 2933 == ASC_TRUE)
2934 seq_printf(m, " Serial Number: %s\n", serialstr);
2935 else if (ep->adapter_info[5] == 0xBB)
2f979427
RV		 2936 seq_puts(m,
2937 " Default Settings Used for EEPROM-less Adapter.\n");
b59fb6fd 2938 else
2f979427 2939 seq_puts(m, " Serial Number Signature Not Present.\n");
b59fb6fd
AV		 2940
2941 seq_printf(m,
2942 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2943 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2944 ep->max_tag_qng);
2945
2946 seq_printf(m,
2947 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2948
2f979427 2949 seq_puts(m, " Target ID: ");
b59fb6fd
AV		 2950 for (i = 0; i <= ASC_MAX_TID; i++)
2951 seq_printf(m, " %d", i);
b59fb6fd 2952
3d30079c 2953 seq_puts(m, "\n Disconnects: ");
b59fb6fd
AV		 2954 for (i = 0; i <= ASC_MAX_TID; i++)
2955 seq_printf(m, " %c",
2956 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 2957
3d30079c 2958 seq_puts(m, "\n Command Queuing: ");
b59fb6fd
AV		 2959 for (i = 0; i <= ASC_MAX_TID; i++)
2960 seq_printf(m, " %c",
2961 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 2962
3d30079c 2963 seq_puts(m, "\n Start Motor: ");
b59fb6fd
AV		 2964 for (i = 0; i <= ASC_MAX_TID; i++)
2965 seq_printf(m, " %c",
2966 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 2967
3d30079c 2968 seq_puts(m, "\n Synchronous Transfer:");
b59fb6fd
AV		 2969 for (i = 0; i <= ASC_MAX_TID; i++)
2970 seq_printf(m, " %c",
2971 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 2972 seq_putc(m, '\n');
51219358
MW		 2973
2974#ifdef CONFIG_ISA
2975 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
b59fb6fd
AV		 2976 seq_printf(m,
2977 " Host ISA DMA speed: %d MB/S\n",
2978 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
51219358
MW		 2979 }
2980#endif /* CONFIG_ISA */
1da177e4
LT		 2981}
2982
2983/*
51219358 2984 * asc_prt_adv_board_eeprom()
1da177e4 2985 *
51219358 2986 * Print board EEPROM configuration.
1da177e4 2987 */
b59fb6fd 2988static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 2989{
d2411495 2990 struct asc_board *boardp = shost_priv(shost);
51219358 2991 ADV_DVC_VAR *adv_dvc_varp;
27c868c2 2992 int i;
51219358
MW		 2993 char *termstr;
2994 uchar serialstr[13];
2995 ADVEEP_3550_CONFIG *ep_3550 = NULL;
2996 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
2997 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
2998 ushort word;
2999 ushort *wordp;
3000 ushort sdtr_speed = 0;
27c868c2 3001
51219358
MW		 3002 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3003 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3004 ep_3550 = &boardp->eep_config.adv_3550_eep;
3005 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3006 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
27c868c2 3007 } else {
51219358 3008 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
27c868c2 3009 }
1da177e4 3010
b59fb6fd
AV		 3011 seq_printf(m,
3012 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3013 shost->host_no);
27c868c2 3014
51219358
MW		 3015 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3016 wordp = &ep_3550->serial_number_word1;
3017 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3018 wordp = &ep_38C0800->serial_number_word1;
3019 } else {
3020 wordp = &ep_38C1600->serial_number_word1;
3021 }
27c868c2 3022
b59fb6fd
AV		 3023 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3024 seq_printf(m, " Serial Number: %s\n", serialstr);
3025 else
2f979427 3026 seq_puts(m, " Serial Number Signature Not Present.\n");
27c868c2 3027
b59fb6fd
AV		 3028 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3029 seq_printf(m,
3030 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3031 ep_3550->adapter_scsi_id,
3032 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3033 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3034 seq_printf(m,
3035 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3036 ep_38C0800->adapter_scsi_id,
3037 ep_38C0800->max_host_qng,
3038 ep_38C0800->max_dvc_qng);
3039 else
3040 seq_printf(m,
3041 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3042 ep_38C1600->adapter_scsi_id,
3043 ep_38C1600->max_host_qng,
3044 ep_38C1600->max_dvc_qng);
51219358
MW		 3045 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3046 word = ep_3550->termination;
3047 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3048 word = ep_38C0800->termination_lvd;
3049 } else {
3050 word = ep_38C1600->termination_lvd;
3051 }
3052 switch (word) {
3053 case 1:
3054 termstr = "Low Off/High Off";
3055 break;
3056 case 2:
3057 termstr = "Low Off/High On";
3058 break;
3059 case 3:
3060 termstr = "Low On/High On";
3061 break;
3062 default:
3063 case 0:
3064 termstr = "Automatic";
3065 break;
27c868c2 3066 }
1da177e4 3067
b59fb6fd
AV		 3068 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3069 seq_printf(m,
3070 " termination: %u (%s), bios_ctrl: 0x%x\n",
3071 ep_3550->termination, termstr,
3072 ep_3550->bios_ctrl);
3073 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3074 seq_printf(m,
3075 " termination: %u (%s), bios_ctrl: 0x%x\n",
3076 ep_38C0800->termination_lvd, termstr,
3077 ep_38C0800->bios_ctrl);
3078 else
3079 seq_printf(m,
3080 " termination: %u (%s), bios_ctrl: 0x%x\n",
3081 ep_38C1600->termination_lvd, termstr,
3082 ep_38C1600->bios_ctrl);
1da177e4 3083
2f979427 3084 seq_puts(m, " Target ID: ");
b59fb6fd
AV		 3085 for (i = 0; i <= ADV_MAX_TID; i++)
3086 seq_printf(m, " %X", i);
f50332ff 3087 seq_putc(m, '\n');
1da177e4 3088
51219358
MW		 3089 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3090 word = ep_3550->disc_enable;
3091 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3092 word = ep_38C0800->disc_enable;
3093 } else {
3094 word = ep_38C1600->disc_enable;
3095 }
2f979427 3096 seq_puts(m, " Disconnects: ");
b59fb6fd
AV		 3097 for (i = 0; i <= ADV_MAX_TID; i++)
3098 seq_printf(m, " %c",
3099 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3100 seq_putc(m, '\n');
1da177e4 3101
51219358
MW		 3102 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3103 word = ep_3550->tagqng_able;
3104 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3105 word = ep_38C0800->tagqng_able;
3106 } else {
3107 word = ep_38C1600->tagqng_able;
3108 }
2f979427 3109 seq_puts(m, " Command Queuing: ");
b59fb6fd
AV		 3110 for (i = 0; i <= ADV_MAX_TID; i++)
3111 seq_printf(m, " %c",
3112 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3113 seq_putc(m, '\n');
1da177e4 3114
51219358
MW		 3115 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3116 word = ep_3550->start_motor;
3117 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3118 word = ep_38C0800->start_motor;
27c868c2 3119 } else {
51219358
MW		 3120 word = ep_38C1600->start_motor;
3121 }
2f979427 3122 seq_puts(m, " Start Motor: ");
b59fb6fd
AV		 3123 for (i = 0; i <= ADV_MAX_TID; i++)
3124 seq_printf(m, " %c",
3125 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3126 seq_putc(m, '\n');
27c868c2 3127
51219358 3128 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2f979427 3129 seq_puts(m, " Synchronous Transfer:");
b59fb6fd
AV		 3130 for (i = 0; i <= ADV_MAX_TID; i++)
3131 seq_printf(m, " %c",
3132 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3133 'Y' : 'N');
f50332ff 3134 seq_putc(m, '\n');
51219358 3135 }
27c868c2 3136
51219358 3137 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2f979427 3138 seq_puts(m, " Ultra Transfer: ");
b59fb6fd
AV		 3139 for (i = 0; i <= ADV_MAX_TID; i++)
3140 seq_printf(m, " %c",
3141 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3142 ? 'Y' : 'N');
f50332ff 3143 seq_putc(m, '\n');
51219358 3144 }
27c868c2 3145
51219358
MW		 3146 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3147 word = ep_3550->wdtr_able;
3148 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3149 word = ep_38C0800->wdtr_able;
3150 } else {
3151 word = ep_38C1600->wdtr_able;
3152 }
2f979427 3153 seq_puts(m, " Wide Transfer: ");
b59fb6fd
AV		 3154 for (i = 0; i <= ADV_MAX_TID; i++)
3155 seq_printf(m, " %c",
3156 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3157 seq_putc(m, '\n');
1da177e4 3158
51219358
MW		 3159 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3160 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
2f979427 3161 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
51219358
MW		 3162 for (i = 0; i <= ADV_MAX_TID; i++) {
3163 char *speed_str;
1da177e4 3164
51219358
MW		 3165 if (i == 0) {
3166 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3167 } else if (i == 4) {
3168 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3169 } else if (i == 8) {
3170 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3171 } else if (i == 12) {
3172 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3173 }
3174 switch (sdtr_speed & ADV_MAX_TID) {
3175 case 0:
3176 speed_str = "Off";
3177 break;
3178 case 1:
3179 speed_str = " 5";
3180 break;
3181 case 2:
3182 speed_str = " 10";
3183 break;
3184 case 3:
3185 speed_str = " 20";
3186 break;
3187 case 4:
3188 speed_str = " 40";
3189 break;
3190 case 5:
3191 speed_str = " 80";
3192 break;
3193 default:
3194 speed_str = "Unk";
3195 break;
3196 }
b59fb6fd
AV		 3197 seq_printf(m, "%X:%s ", i, speed_str);
3198 if (i == 7)
2f979427 3199 seq_puts(m, "\n ");
51219358
MW		 3200 sdtr_speed >>= 4;
3201 }
f50332ff 3202 seq_putc(m, '\n');
51219358 3203 }
1da177e4
LT		 3204}
3205
3206/*
51219358 3207 * asc_prt_driver_conf()
1da177e4 3208 */
b59fb6fd 3209static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3210{
d2411495 3211 struct asc_board *boardp = shost_priv(shost);
51219358 3212 int chip_scsi_id;
27c868c2 3213
b59fb6fd
AV		 3214 seq_printf(m,
3215 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3216 shost->host_no);
27c868c2 3217
b59fb6fd 3218 seq_printf(m,
1abf635d 3219 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
74665016 3220 atomic_read(&shost->host_busy), shost->max_id,
b59fb6fd 3221 shost->max_lun, shost->max_channel);
95c9f162 3222
b59fb6fd
AV		 3223 seq_printf(m,
3224 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3225 shost->unique_id, shost->can_queue, shost->this_id,
3226 shost->sg_tablesize, shost->cmd_per_lun);
95c9f162 3227
b59fb6fd
AV		 3228 seq_printf(m,
3229 " unchecked_isa_dma %d, use_clustering %d\n",
3230 shost->unchecked_isa_dma, shost->use_clustering);
95c9f162 3231
b59fb6fd 3232 seq_printf(m,
31491e1a 3233 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
eac0b0c7 3234 boardp->flags, shost->last_reset, jiffies,
b59fb6fd 3235 boardp->asc_n_io_port);
27c868c2 3236
31491e1a 3237 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
27c868c2 3238
51219358
MW		 3239 if (ASC_NARROW_BOARD(boardp)) {
3240 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3241 } else {
3242 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
27c868c2 3243 }
1da177e4
LT		 3244}
3245
3246/*
51219358 3247 * asc_prt_asc_board_info()
1da177e4 3248 *
51219358 3249 * Print dynamic board configuration information.
1da177e4 3250 */
b59fb6fd 3251static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3252{
d2411495 3253 struct asc_board *boardp = shost_priv(shost);
51219358 3254 int chip_scsi_id;
51219358
MW		 3255 ASC_DVC_VAR *v;
3256 ASC_DVC_CFG *c;
3257 int i;
3258 int renegotiate = 0;
27c868c2 3259
51219358
MW		 3260 v = &boardp->dvc_var.asc_dvc_var;
3261 c = &boardp->dvc_cfg.asc_dvc_cfg;
3262 chip_scsi_id = c->chip_scsi_id;
27c868c2 3263
b59fb6fd
AV		 3264 seq_printf(m,
3265 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3266 shost->host_no);
27c868c2 3267
b59fb6fd
AV		 3268 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3269 "mcode_version 0x%x, err_code %u\n",
3270 c->chip_version, c->mcode_date, c->mcode_version,
3271 v->err_code);
1da177e4 3272
51219358 3273 /* Current number of commands waiting for the host. */
b59fb6fd
AV		 3274 seq_printf(m,
3275 " Total Command Pending: %d\n", v->cur_total_qng);
1da177e4 3276
2f979427 3277 seq_puts(m, " Command Queuing:");
51219358
MW		 3278 for (i = 0; i <= ASC_MAX_TID; i++) {
3279 if ((chip_scsi_id == i) ||
3280 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3281 continue;
27c868c2 3282 }
b59fb6fd
AV		 3283 seq_printf(m, " %X:%c",
3284 i,
3285 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
51219358 3286 }
27c868c2 3287
51219358 3288 /* Current number of commands waiting for a device. */
3d30079c 3289 seq_puts(m, "\n Command Queue Pending:");
51219358
MW		 3290 for (i = 0; i <= ASC_MAX_TID; i++) {
3291 if ((chip_scsi_id == i) ||
3292 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3293 continue;
27c868c2 3294 }
b59fb6fd 3295 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
27c868c2 3296 }
1da177e4 3297
51219358 3298 /* Current limit on number of commands that can be sent to a device. */
3d30079c 3299 seq_puts(m, "\n Command Queue Limit:");
51219358
MW		 3300 for (i = 0; i <= ASC_MAX_TID; i++) {
3301 if ((chip_scsi_id == i) ||
3302 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3303 continue;
3304 }
b59fb6fd 3305 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
27c868c2 3306 }
1da177e4 3307
51219358 3308 /* Indicate whether the device has returned queue full status. */
3d30079c 3309 seq_puts(m, "\n Command Queue Full:");
51219358
MW		 3310 for (i = 0; i <= ASC_MAX_TID; i++) {
3311 if ((chip_scsi_id == i) ||
3312 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3313 continue;
3314 }
b59fb6fd
AV		 3315 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3316 seq_printf(m, " %X:Y-%d",
3317 i, boardp->queue_full_cnt[i]);
3318 else
3319 seq_printf(m, " %X:N", i);
51219358 3320 }
1da177e4 3321
3d30079c 3322 seq_puts(m, "\n Synchronous Transfer:");
51219358
MW		 3323 for (i = 0; i <= ASC_MAX_TID; i++) {
3324 if ((chip_scsi_id == i) ||
3325 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3326 continue;
3327 }
b59fb6fd
AV		 3328 seq_printf(m, " %X:%c",
3329 i,
3330 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3331 }
f50332ff 3332 seq_putc(m, '\n');
1da177e4 3333
51219358
MW		 3334 for (i = 0; i <= ASC_MAX_TID; i++) {
3335 uchar syn_period_ix;
1da177e4 3336
51219358
MW		 3337 if ((chip_scsi_id == i) ||
3338 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3339 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3340 continue;
27c868c2 3341 }
27c868c2 3342
b59fb6fd 3343 seq_printf(m, " %X:", i);
27c868c2 3344
51219358 3345 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
2f979427 3346 seq_puts(m, " Asynchronous");
51219358
MW		 3347 } else {
3348 syn_period_ix =
3349 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3350 1);
27c868c2 3351
b59fb6fd
AV		 3352 seq_printf(m,
3353 " Transfer Period Factor: %d (%d.%d Mhz),",
3354 v->sdtr_period_tbl[syn_period_ix],
3355 250 / v->sdtr_period_tbl[syn_period_ix],
3356 ASC_TENTHS(250,
3357 v->sdtr_period_tbl[syn_period_ix]));
27c868c2 3358
b59fb6fd
AV		 3359 seq_printf(m, " REQ/ACK Offset: %d",
3360 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
51219358 3361 }
1da177e4 3362
51219358 3363 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3364 seq_puts(m, "*\n");
51219358
MW		 3365 renegotiate = 1;
3366 } else {
f50332ff 3367 seq_putc(m, '\n');
51219358 3368 }
27c868c2 3369 }
1da177e4 3370
51219358 3371 if (renegotiate) {
2f979427 3372 seq_puts(m, " * = Re-negotiation pending before next command.\n");
27c868c2 3373 }
1da177e4
LT		 3374}
3375
1da177e4 3376/*
51219358 3377 * asc_prt_adv_board_info()
1da177e4 3378 *
51219358 3379 * Print dynamic board configuration information.
1da177e4 3380 */
b59fb6fd 3381static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3382{
d2411495 3383 struct asc_board *boardp = shost_priv(shost);
27c868c2 3384 int i;
51219358
MW		 3385 ADV_DVC_VAR *v;
3386 ADV_DVC_CFG *c;
3387 AdvPortAddr iop_base;
3388 ushort chip_scsi_id;
3389 ushort lramword;
3390 uchar lrambyte;
3391 ushort tagqng_able;
3392 ushort sdtr_able, wdtr_able;
3393 ushort wdtr_done, sdtr_done;
3394 ushort period = 0;
3395 int renegotiate = 0;
27c868c2 3396
51219358
MW		 3397 v = &boardp->dvc_var.adv_dvc_var;
3398 c = &boardp->dvc_cfg.adv_dvc_cfg;
3399 iop_base = v->iop_base;
3400 chip_scsi_id = v->chip_scsi_id;
3401
b59fb6fd
AV		 3402 seq_printf(m,
3403 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3404 shost->host_no);
27c868c2 3405
b59fb6fd
AV		 3406 seq_printf(m,
3407 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
31491e1a 3408 (unsigned long)v->iop_base,
b59fb6fd
AV		 3409 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3410 v->err_code);
1da177e4 3411
b59fb6fd
AV		 3412 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3413 "mcode_version 0x%x\n", c->chip_version,
3414 c->mcode_date, c->mcode_version);
51219358
MW		 3415
3416 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
2f979427 3417 seq_puts(m, " Queuing Enabled:");
27c868c2 3418 for (i = 0; i <= ADV_MAX_TID; i++) {
51219358
MW		 3419 if ((chip_scsi_id == i) ||
3420 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3421 continue;
27c868c2 3422 }
51219358 3423
b59fb6fd
AV		 3424 seq_printf(m, " %X:%c",
3425 i,
3426 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3427 }
1da177e4 3428
3d30079c 3429 seq_puts(m, "\n Queue Limit:");
51219358
MW		 3430 for (i = 0; i <= ADV_MAX_TID; i++) {
3431 if ((chip_scsi_id == i) ||
3432 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3433 continue;
3434 }
1da177e4 3435
51219358
MW		 3436 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3437 lrambyte);
27c868c2 3438
b59fb6fd 3439 seq_printf(m, " %X:%d", i, lrambyte);
51219358 3440 }
27c868c2 3441
3d30079c 3442 seq_puts(m, "\n Command Pending:");
51219358
MW		 3443 for (i = 0; i <= ADV_MAX_TID; i++) {
3444 if ((chip_scsi_id == i) ||
3445 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3446 continue;
3447 }
27c868c2 3448
51219358
MW		 3449 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3450 lrambyte);
1da177e4 3451
b59fb6fd 3452 seq_printf(m, " %X:%d", i, lrambyte);
51219358 3453 }
f50332ff 3454 seq_putc(m, '\n');
1da177e4 3455
51219358 3456 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
2f979427 3457 seq_puts(m, " Wide Enabled:");
51219358
MW		 3458 for (i = 0; i <= ADV_MAX_TID; i++) {
3459 if ((chip_scsi_id == i) ||
3460 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3461 continue;
27c868c2 3462 }
51219358 3463
b59fb6fd
AV		 3464 seq_printf(m, " %X:%c",
3465 i,
3466 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3467 }
f50332ff 3468 seq_putc(m, '\n');
1da177e4 3469
51219358 3470 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
2f979427 3471 seq_puts(m, " Transfer Bit Width:");
51219358
MW		 3472 for (i = 0; i <= ADV_MAX_TID; i++) {
3473 if ((chip_scsi_id == i) ||
3474 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3475 continue;
3476 }
1da177e4 3477
51219358
MW		 3478 AdvReadWordLram(iop_base,
3479 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3480 lramword);
27c868c2 3481
b59fb6fd
AV		 3482 seq_printf(m, " %X:%d",
3483 i, (lramword & 0x8000) ? 16 : 8);
27c868c2 3484
51219358
MW		 3485 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3486 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
f50332ff 3487 seq_putc(m, '*');
51219358 3488 renegotiate = 1;
27c868c2 3489 }
51219358 3490 }
f50332ff 3491 seq_putc(m, '\n');
27c868c2 3492
51219358 3493 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
2f979427 3494 seq_puts(m, " Synchronous Enabled:");
51219358
MW		 3495 for (i = 0; i <= ADV_MAX_TID; i++) {
3496 if ((chip_scsi_id == i) ||
3497 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3498 continue;
3499 }
27c868c2 3500
b59fb6fd
AV		 3501 seq_printf(m, " %X:%c",
3502 i,
3503 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
51219358 3504 }
f50332ff 3505 seq_putc(m, '\n');
27c868c2 3506
51219358
MW		 3507 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3508 for (i = 0; i <= ADV_MAX_TID; i++) {
27c868c2 3509
51219358
MW		 3510 AdvReadWordLram(iop_base,
3511 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3512 lramword);
3513 lramword &= ~0x8000;
27c868c2 3514
51219358
MW		 3515 if ((chip_scsi_id == i) ||
3516 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3517 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3518 continue;
27c868c2
MW		 3519 }
3520
b59fb6fd 3521 seq_printf(m, " %X:", i);
27c868c2 3522
51219358 3523 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
2f979427 3524 seq_puts(m, " Asynchronous");
51219358 3525 } else {
2f979427 3526 seq_puts(m, " Transfer Period Factor: ");
27c868c2 3527
51219358 3528 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
2f979427 3529 seq_puts(m, "9 (80.0 Mhz),");
51219358 3530 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
2f979427 3531 seq_puts(m, "10 (40.0 Mhz),");
51219358 3532 } else { /* 20 Mhz or below. */
27c868c2 3533
51219358
MW		 3534 period = (((lramword >> 8) * 25) + 50) / 4;
3535
3536 if (period == 0) { /* Should never happen. */
31491e1a 3537 seq_printf(m, "%d (? Mhz), ", period);
51219358 3538 } else {
b59fb6fd
AV		 3539 seq_printf(m,
3540 "%d (%d.%d Mhz),",
3541 period, 250 / period,
3542 ASC_TENTHS(250, period));
51219358
MW		 3543 }
3544 }
3545
b59fb6fd
AV		 3546 seq_printf(m, " REQ/ACK Offset: %d",
3547 lramword & 0x1F);
51219358
MW		 3548 }
3549
3550 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3551 seq_puts(m, "*\n");
51219358
MW		 3552 renegotiate = 1;
3553 } else {
f50332ff 3554 seq_putc(m, '\n');
51219358 3555 }
27c868c2 3556 }
51219358
MW		 3557
3558 if (renegotiate) {
2f979427 3559 seq_puts(m, " * = Re-negotiation pending before next command.\n");
51219358 3560 }
51219358
MW		 3561}
3562
3563#ifdef ADVANSYS_STATS
3564/*
3565 * asc_prt_board_stats()
1da177e4 3566 */
b59fb6fd 3567static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3568{
d2411495
MW		 3569 struct asc_board *boardp = shost_priv(shost);
3570 struct asc_stats *s = &boardp->asc_stats;
27c868c2 3571
b59fb6fd
AV		 3572 seq_printf(m,
3573 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3574 shost->host_no);
51219358 3575
b59fb6fd 3576 seq_printf(m,
31491e1a 3577 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
b59fb6fd
AV		 3578 s->queuecommand, s->reset, s->biosparam,
3579 s->interrupt);
27c868c2 3580
b59fb6fd 3581 seq_printf(m,
31491e1a 3582 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
b59fb6fd
AV		 3583 s->callback, s->done, s->build_error,
3584 s->adv_build_noreq, s->adv_build_nosg);
27c868c2 3585
b59fb6fd 3586 seq_printf(m,
31491e1a 3587 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
b59fb6fd
AV		 3588 s->exe_noerror, s->exe_busy, s->exe_error,
3589 s->exe_unknown);
51219358
MW		 3590
3591 /*
3592 * Display data transfer statistics.
3593 */
52c334e9 3594 if (s->xfer_cnt > 0) {
31491e1a 3595 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
b59fb6fd 3596 s->xfer_cnt, s->xfer_elem);
27c868c2 3597
31491e1a 3598 seq_printf(m, "xfer_bytes %u.%01u kb\n",
b59fb6fd 3599 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
1da177e4 3600
51219358 3601 /* Scatter gather transfer statistics */
31491e1a 3602 seq_printf(m, " avg_num_elem %u.%01u, ",
b59fb6fd
AV		 3603 s->xfer_elem / s->xfer_cnt,
3604 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
51219358 3605
31491e1a 3606 seq_printf(m, "avg_elem_size %u.%01u kb, ",
b59fb6fd
AV		 3607 (s->xfer_sect / 2) / s->xfer_elem,
3608 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
51219358 3609
31491e1a 3610 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
b59fb6fd
AV		 3611 (s->xfer_sect / 2) / s->xfer_cnt,
3612 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
27c868c2 3613 }
1da177e4 3614}
51219358 3615#endif /* ADVANSYS_STATS */
1da177e4
LT		 3616
3617/*
b59fb6fd 3618 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
1da177e4 3619 *
b59fb6fd
AV		 3620 * m: seq_file to print into
3621 * shost: Scsi_Host
1da177e4 3622 *
51219358
MW		 3623 * Return the number of bytes read from or written to a
3624 * /proc/scsi/advansys/[0...] file.
1da177e4 3625 */
51219358 3626static int
b59fb6fd 3627advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3628{
d2411495 3629 struct asc_board *boardp = shost_priv(shost);
27c868c2 3630
b352f923 3631 ASC_DBG(1, "begin\n");
51219358 3632
51219358
MW		 3633 /*
3634 * User read of /proc/scsi/advansys/[0...] file.
3635 */
1da177e4 3636
51219358
MW		 3637 /*
3638 * Get board configuration information.
3639 *
3640 * advansys_info() returns the board string from its own static buffer.
3641 */
51219358 3642 /* Copy board information. */
b59fb6fd 3643 seq_printf(m, "%s\n", (char *)advansys_info(shost));
51219358
MW		 3644 /*
3645 * Display Wide Board BIOS Information.
3646 */
b59fb6fd
AV		 3647 if (!ASC_NARROW_BOARD(boardp))
3648 asc_prt_adv_bios(m, shost);
1da177e4 3649
51219358
MW		 3650 /*
3651 * Display driver information for each device attached to the board.
3652 */
b59fb6fd 3653 asc_prt_board_devices(m, shost);
51219358
MW		 3654
3655 /*
3656 * Display EEPROM configuration for the board.
3657 */
b59fb6fd
AV		 3658 if (ASC_NARROW_BOARD(boardp))
3659 asc_prt_asc_board_eeprom(m, shost);
3660 else
3661 asc_prt_adv_board_eeprom(m, shost);
1da177e4 3662
51219358
MW		 3663 /*
3664 * Display driver configuration and information for the board.
3665 */
b59fb6fd 3666 asc_prt_driver_conf(m, shost);
1da177e4 3667
51219358
MW		 3668#ifdef ADVANSYS_STATS
3669 /*
3670 * Display driver statistics for the board.
3671 */
b59fb6fd 3672 asc_prt_board_stats(m, shost);
51219358 3673#endif /* ADVANSYS_STATS */
1da177e4 3674
51219358
MW		 3675 /*
3676 * Display Asc Library dynamic configuration information
3677 * for the board.
3678 */
b59fb6fd
AV		 3679 if (ASC_NARROW_BOARD(boardp))
3680 asc_prt_asc_board_info(m, shost);
3681 else
3682 asc_prt_adv_board_info(m, shost);
3683 return 0;
51219358
MW		 3684}
3685#endif /* CONFIG_PROC_FS */
3686
3687static void asc_scsi_done(struct scsi_cmnd *scp)
3688{
52c334e9 3689 scsi_dma_unmap(scp);
51219358 3690 ASC_STATS(scp->device->host, done);
51219358
MW		 3691 scp->scsi_done(scp);
3692}
3693
3694static void AscSetBank(PortAddr iop_base, uchar bank)
3695{
3696 uchar val;
3697
3698 val = AscGetChipControl(iop_base) &
3699 (~
3700 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3701 CC_CHIP_RESET));
3702 if (bank == 1) {
3703 val |= CC_BANK_ONE;
3704 } else if (bank == 2) {
3705 val |= CC_DIAG | CC_BANK_ONE;
27c868c2 3706 } else {
51219358 3707 val &= ~CC_BANK_ONE;
27c868c2 3708 }
51219358 3709 AscSetChipControl(iop_base, val);
51219358
MW		 3710}
3711
3712static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3713{
3714 AscSetBank(iop_base, 1);
3715 AscWriteChipIH(iop_base, ins_code);
3716 AscSetBank(iop_base, 0);
51219358
MW		 3717}
3718
3719static int AscStartChip(PortAddr iop_base)
3720{
3721 AscSetChipControl(iop_base, 0);
3722 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3723 return (0);
27c868c2 3724 }
51219358
MW		 3725 return (1);
3726}
27c868c2 3727
ae26759e 3728static bool AscStopChip(PortAddr iop_base)
51219358
MW		 3729{
3730 uchar cc_val;
3731
3732 cc_val =
3733 AscGetChipControl(iop_base) &
3734 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3735 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3736 AscSetChipIH(iop_base, INS_HALT);
3737 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3738 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
ae26759e 3739 return false;
27c868c2 3740 }
ae26759e 3741 return true;
51219358 3742}
27c868c2 3743
d647c783 3744static bool AscIsChipHalted(PortAddr iop_base)
51219358
MW		 3745{
3746 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3747 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
d647c783 3748 return true;
27c868c2 3749 }
27c868c2 3750 }
d647c783 3751 return false;
51219358 3752}
27c868c2 3753
d647c783 3754static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
51219358
MW		 3755{
3756 PortAddr iop_base;
3757 int i = 10;
3758
3759 iop_base = asc_dvc->iop_base;
3760 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3761 && (i-- > 0)) {
3762 mdelay(100);
27c868c2 3763 }
51219358
MW		 3764 AscStopChip(iop_base);
3765 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3766 udelay(60);
3767 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3768 AscSetChipIH(iop_base, INS_HALT);
3769 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3770 AscSetChipControl(iop_base, CC_HALT);
3771 mdelay(200);
3772 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3773 AscSetChipStatus(iop_base, 0);
3774 return (AscIsChipHalted(iop_base));
3775}
27c868c2 3776
51219358
MW		 3777static int AscFindSignature(PortAddr iop_base)
3778{
3779 ushort sig_word;
27c868c2 3780
b352f923 3781 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
51219358
MW		 3782 iop_base, AscGetChipSignatureByte(iop_base));
3783 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
b352f923 3784 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
51219358
MW		 3785 iop_base, AscGetChipSignatureWord(iop_base));
3786 sig_word = AscGetChipSignatureWord(iop_base);
3787 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3788 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3789 return (1);
27c868c2 3790 }
27c868c2 3791 }
51219358 3792 return (0);
27c868c2
MW		 3793}
3794
51219358 3795static void AscEnableInterrupt(PortAddr iop_base)
1da177e4 3796{
51219358 3797 ushort cfg;
27c868c2 3798
51219358
MW		 3799 cfg = AscGetChipCfgLsw(iop_base);
3800 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
51219358 3801}
27c868c2 3802
51219358
MW		 3803static void AscDisableInterrupt(PortAddr iop_base)
3804{
3805 ushort cfg;
27c868c2 3806
51219358
MW		 3807 cfg = AscGetChipCfgLsw(iop_base);
3808 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
51219358 3809}
27c868c2 3810
51219358
MW		 3811static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3812{
3813 unsigned char byte_data;
3814 unsigned short word_data;
27c868c2 3815
51219358
MW		 3816 if (isodd_word(addr)) {
3817 AscSetChipLramAddr(iop_base, addr - 1);
3818 word_data = AscGetChipLramData(iop_base);
3819 byte_data = (word_data >> 8) & 0xFF;
3820 } else {
3821 AscSetChipLramAddr(iop_base, addr);
3822 word_data = AscGetChipLramData(iop_base);
3823 byte_data = word_data & 0xFF;
3824 }
3825 return byte_data;
3826}
27c868c2 3827
51219358
MW		 3828static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3829{
3830 ushort word_data;
27c868c2 3831
51219358
MW		 3832 AscSetChipLramAddr(iop_base, addr);
3833 word_data = AscGetChipLramData(iop_base);
3834 return (word_data);
3835}
27c868c2 3836
51219358
MW		 3837static void
3838AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3839{
3840 int i;
3841
3842 AscSetChipLramAddr(iop_base, s_addr);
3843 for (i = 0; i < words; i++) {
3844 AscSetChipLramData(iop_base, set_wval);
27c868c2 3845 }
51219358 3846}
1da177e4 3847
51219358
MW		 3848static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3849{
3850 AscSetChipLramAddr(iop_base, addr);
3851 AscSetChipLramData(iop_base, word_val);
51219358
MW		 3852}
3853
3854static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3855{
3856 ushort word_data;
3857
3858 if (isodd_word(addr)) {
3859 addr--;
3860 word_data = AscReadLramWord(iop_base, addr);
3861 word_data &= 0x00FF;
3862 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3863 } else {
3864 word_data = AscReadLramWord(iop_base, addr);
3865 word_data &= 0xFF00;
3866 word_data |= ((ushort)byte_val & 0x00FF);
3867 }
3868 AscWriteLramWord(iop_base, addr, word_data);
1da177e4
LT		 3869}
3870
3871/*
51219358 3872 * Copy 2 bytes to LRAM.
1da177e4 3873 *
51219358
MW		 3874 * The source data is assumed to be in little-endian order in memory
3875 * and is maintained in little-endian order when written to LRAM.
1da177e4 3876 */
51219358 3877static void
989bb5f5
JSR		 3878AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3879 const uchar *s_buffer, int words)
1da177e4 3880{
27c868c2 3881 int i;
27c868c2 3882
51219358
MW		 3883 AscSetChipLramAddr(iop_base, s_addr);
3884 for (i = 0; i < 2 * words; i += 2) {
3885 /*
3886 * On a little-endian system the second argument below
3887 * produces a little-endian ushort which is written to
3888 * LRAM in little-endian order. On a big-endian system
3889 * the second argument produces a big-endian ushort which
3890 * is "transparently" byte-swapped by outpw() and written
3891 * in little-endian order to LRAM.
3892 */
3893 outpw(iop_base + IOP_RAM_DATA,
3894 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3895 }
51219358 3896}
27c868c2 3897
51219358
MW		 3898/*
3899 * Copy 4 bytes to LRAM.
3900 *
3901 * The source data is assumed to be in little-endian order in memory
25985edc 3902 * and is maintained in little-endian order when written to LRAM.
51219358
MW		 3903 */
3904static void
3905AscMemDWordCopyPtrToLram(PortAddr iop_base,
3906 ushort s_addr, uchar *s_buffer, int dwords)
3907{
3908 int i;
27c868c2 3909
51219358
MW		 3910 AscSetChipLramAddr(iop_base, s_addr);
3911 for (i = 0; i < 4 * dwords; i += 4) {
3912 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3913 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3914 }
51219358 3915}
27c868c2 3916
51219358
MW		 3917/*
3918 * Copy 2 bytes from LRAM.
3919 *
3920 * The source data is assumed to be in little-endian order in LRAM
3921 * and is maintained in little-endian order when written to memory.
3922 */
3923static void
3924AscMemWordCopyPtrFromLram(PortAddr iop_base,
3925 ushort s_addr, uchar *d_buffer, int words)
3926{
3927 int i;
3928 ushort word;
27c868c2 3929
51219358
MW		 3930 AscSetChipLramAddr(iop_base, s_addr);
3931 for (i = 0; i < 2 * words; i += 2) {
3932 word = inpw(iop_base + IOP_RAM_DATA);
3933 d_buffer[i] = word & 0xff;
3934 d_buffer[i + 1] = (word >> 8) & 0xff;
27c868c2 3935 }
51219358 3936}
27c868c2 3937
95cfab6c 3938static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
51219358 3939{
95cfab6c 3940 u32 sum = 0;
51219358 3941 int i;
27c868c2 3942
51219358
MW		 3943 for (i = 0; i < words; i++, s_addr += 2) {
3944 sum += AscReadLramWord(iop_base, s_addr);
27c868c2 3945 }
51219358
MW		 3946 return (sum);
3947}
27c868c2 3948
f33134e5 3949static void AscInitLram(ASC_DVC_VAR *asc_dvc)
51219358
MW		 3950{
3951 uchar i;
3952 ushort s_addr;
3953 PortAddr iop_base;
27c868c2 3954
51219358 3955 iop_base = asc_dvc->iop_base;
51219358
MW		 3956 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
3957 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
3958 64) >> 1));
3959 i = ASC_MIN_ACTIVE_QNO;
3960 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
3961 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3962 (uchar)(i + 1));
3963 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3964 (uchar)(asc_dvc->max_total_qng));
3965 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3966 (uchar)i);
3967 i++;
3968 s_addr += ASC_QBLK_SIZE;
3969 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
3970 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3971 (uchar)(i + 1));
3972 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3973 (uchar)(i - 1));
3974 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3975 (uchar)i);
27c868c2 3976 }
51219358
MW		 3977 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3978 (uchar)ASC_QLINK_END);
3979 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3980 (uchar)(asc_dvc->max_total_qng - 1));
3981 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3982 (uchar)asc_dvc->max_total_qng);
3983 i++;
3984 s_addr += ASC_QBLK_SIZE;
3985 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
3986 i++, s_addr += ASC_QBLK_SIZE) {
3987 AscWriteLramByte(iop_base,
3988 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
3989 AscWriteLramByte(iop_base,
3990 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
3991 AscWriteLramByte(iop_base,
3992 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
27c868c2 3993 }
1da177e4
LT		 3994}
3995
95cfab6c 3996static u32
989bb5f5
JSR		 3997AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
3998 const uchar *mcode_buf, ushort mcode_size)
1da177e4 3999{
95cfab6c 4000 u32 chksum;
51219358
MW		 4001 ushort mcode_word_size;
4002 ushort mcode_chksum;
27c868c2 4003
51219358
MW		 4004 /* Write the microcode buffer starting at LRAM address 0. */
4005 mcode_word_size = (ushort)(mcode_size >> 1);
4006 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4007 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
27c868c2 4008
51219358 4009 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
b352f923 4010 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
51219358
MW		 4011 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4012 (ushort)ASC_CODE_SEC_BEG,
4013 (ushort)((mcode_size -
4014 s_addr - (ushort)
4015 ASC_CODE_SEC_BEG) /
4016 2));
b352f923 4017 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
51219358
MW		 4018 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4019 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
b352f923 4020 return chksum;
51219358 4021}
27c868c2 4022
51219358
MW		 4023static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4024{
4025 PortAddr iop_base;
4026 int i;
4027 ushort lram_addr;
4028
4029 iop_base = asc_dvc->iop_base;
4030 AscPutRiscVarFreeQHead(iop_base, 1);
4031 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4032 AscPutVarFreeQHead(iop_base, 1);
4033 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4034 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4035 (uchar)((int)asc_dvc->max_total_qng + 1));
4036 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4037 (uchar)((int)asc_dvc->max_total_qng + 2));
4038 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4039 asc_dvc->max_total_qng);
4040 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4041 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4042 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4043 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4044 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4045 AscPutQDoneInProgress(iop_base, 0);
4046 lram_addr = ASC_QADR_BEG;
4047 for (i = 0; i < 32; i++, lram_addr += 2) {
4048 AscWriteLramWord(iop_base, lram_addr, 0);
4049 }
4050}
4051
f33134e5 4052static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
51219358
MW		 4053{
4054 int i;
f33134e5 4055 int warn_code;
51219358 4056 PortAddr iop_base;
95cfab6c
HR		 4057 __le32 phy_addr;
4058 __le32 phy_size;
d10fb2c7 4059 struct asc_board *board = asc_dvc_to_board(asc_dvc);
51219358
MW		 4060
4061 iop_base = asc_dvc->iop_base;
4062 warn_code = 0;
4063 for (i = 0; i <= ASC_MAX_TID; i++) {
4064 AscPutMCodeInitSDTRAtID(iop_base, i,
4065 asc_dvc->cfg->sdtr_period_offset[i]);
4066 }
4067
4068 AscInitQLinkVar(asc_dvc);
4069 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4070 asc_dvc->cfg->disc_enable);
4071 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4072 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4073
d10fb2c7
MW		 4074 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4075 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4076 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4077 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
9a908c1a
HRK		 4078 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4079 warn_code = -ENOMEM;
4080 goto err_dma_map;
4081 }
d10fb2c7 4082 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
51219358
MW		 4083 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4084 (uchar *)&phy_addr, 1);
d10fb2c7 4085 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
51219358
MW		 4086 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4087 (uchar *)&phy_size, 1);
4088
4089 asc_dvc->cfg->mcode_date =
4090 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4091 asc_dvc->cfg->mcode_version =
4092 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4093
4094 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4095 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4096 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
f33134e5 4097 warn_code = -EINVAL;
9a908c1a 4098 goto err_mcode_start;
51219358
MW		 4099 }
4100 if (AscStartChip(iop_base) != 1) {
4101 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
f33134e5 4102 warn_code = -EIO;
9a908c1a 4103 goto err_mcode_start;
51219358
MW		 4104 }
4105
4106 return warn_code;
9a908c1a
HRK		 4107
4108err_mcode_start:
4109 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4110 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4111err_dma_map:
4112 asc_dvc->overrun_dma = 0;
4113 return warn_code;
51219358
MW		 4114}
4115
f33134e5 4116static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
51219358 4117{
989bb5f5
JSR		 4118 const struct firmware *fw;
4119 const char fwname[] = "advansys/mcode.bin";
4120 int err;
4121 unsigned long chksum;
f33134e5 4122 int warn_code;
51219358
MW		 4123 PortAddr iop_base;
4124
4125 iop_base = asc_dvc->iop_base;
4126 warn_code = 0;
4127 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4128 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4129 AscResetChipAndScsiBus(asc_dvc);
4130 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4131 }
4132 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4133 if (asc_dvc->err_code != 0)
f33134e5 4134 return ASC_ERROR;
51219358
MW		 4135 if (!AscFindSignature(asc_dvc->iop_base)) {
4136 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4137 return warn_code;
4138 }
4139 AscDisableInterrupt(iop_base);
f33134e5 4140 AscInitLram(asc_dvc);
989bb5f5
JSR		 4141
4142 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4143 if (err) {
4144 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4145 fwname, err);
cf747445 4146 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4147 return err;
4148 }
4149 if (fw->size < 4) {
4150 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4151 fw->size, fwname);
4152 release_firmware(fw);
cf747445 4153 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4154 return -EINVAL;
4155 }
4156 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4157 (fw->data[1] << 8) | fw->data[0];
4158 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4159 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4160 fw->size - 4) != chksum) {
51219358 4161 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5 4162 release_firmware(fw);
51219358
MW		 4163 return warn_code;
4164 }
989bb5f5 4165 release_firmware(fw);
51219358 4166 warn_code |= AscInitMicroCodeVar(asc_dvc);
9a908c1a
HRK		 4167 if (!asc_dvc->overrun_dma)
4168 return warn_code;
51219358
MW		 4169 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4170 AscEnableInterrupt(iop_base);
4171 return warn_code;
4172}
4173
4174/*
4175 * Load the Microcode
4176 *
4177 * Write the microcode image to RISC memory starting at address 0.
4178 *
4179 * The microcode is stored compressed in the following format:
4180 *
4181 * 254 word (508 byte) table indexed by byte code followed
4182 * by the following byte codes:
4183 *
4184 * 1-Byte Code:
4185 * 00: Emit word 0 in table.
4186 * 01: Emit word 1 in table.
4187 * .
4188 * FD: Emit word 253 in table.
4189 *
4190 * Multi-Byte Code:
4191 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4192 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4193 *
4194 * Returns 0 or an error if the checksum doesn't match
4195 */
989bb5f5
JSR		 4196static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4197 int size, int memsize, int chksum)
51219358
MW		 4198{
4199 int i, j, end, len = 0;
95cfab6c 4200 u32 sum;
51219358
MW		 4201
4202 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4203
4204 for (i = 253 * 2; i < size; i++) {
4205 if (buf[i] == 0xff) {
4206 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4207 for (j = 0; j < buf[i + 1]; j++) {
4208 AdvWriteWordAutoIncLram(iop_base, word);
4209 len += 2;
4210 }
4211 i += 3;
4212 } else if (buf[i] == 0xfe) {
4213 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4214 AdvWriteWordAutoIncLram(iop_base, word);
4215 i += 2;
4216 len += 2;
4217 } else {
951b62c1 4218 unsigned int off = buf[i] * 2;
51219358
MW		 4219 unsigned short word = (buf[off + 1] << 8) | buf[off];
4220 AdvWriteWordAutoIncLram(iop_base, word);
4221 len += 2;
4222 }
4223 }
4224
4225 end = len;
4226
4227 while (len < memsize) {
4228 AdvWriteWordAutoIncLram(iop_base, 0);
4229 len += 2;
4230 }
4231
4232 /* Verify the microcode checksum. */
4233 sum = 0;
4234 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4235
4236 for (len = 0; len < end; len += 2) {
4237 sum += AdvReadWordAutoIncLram(iop_base);
4238 }
4239
4240 if (sum != chksum)
4241 return ASC_IERR_MCODE_CHKSUM;
4242
4243 return 0;
4244}
4245
98b96a7d 4246static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
51219358 4247{
98b96a7d
HR		 4248 off_t carr_offset = 0, next_offset;
4249 dma_addr_t carr_paddr;
4250 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
51219358 4251
98b96a7d
HR		 4252 for (i = 0; i < carr_num; i++) {
4253 carr_offset = i * sizeof(ADV_CARR_T);
4254 /* Get physical address of the carrier 'carrp'. */
4255 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4256
4257 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4258 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4259 adv_dvc->carrier[i].areq_vpa = 0;
4260 next_offset = carr_offset + sizeof(ADV_CARR_T);
4261 if (i == carr_num)
4262 next_offset = ~0;
4263 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
51219358 4264 }
98b96a7d
HR		 4265 /*
4266 * We cannot have a carrier with 'carr_va' of '0', as
4267 * a reference to this carrier would be interpreted as
4268 * list termination.
4269 * So start at carrier 1 with the freelist.
4270 */
4271 adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4272}
51219358 4273
98b96a7d
HR		 4274static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4275{
4276 int index;
51219358 4277
98b96a7d 4278 BUG_ON(offset > ADV_CARRIER_BUFSIZE);
51219358 4279
98b96a7d
HR		 4280 index = offset / sizeof(ADV_CARR_T);
4281 return &adv_dvc->carrier[index];
4282}
51219358 4283
98b96a7d
HR		 4284static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4285{
4286 ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4287 u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4288
4289 if (next_vpa == 0 || next_vpa == ~0) {
4290 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4291 return NULL;
4292 }
51219358 4293
98b96a7d
HR		 4294 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4295 /*
4296 * insert stopper carrier to terminate list
4297 */
4298 carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4299
4300 return carrp;
51219358
MW		 4301}
4302
4b47e464
HR		 4303/*
4304 * 'offset' is the index in the request pointer array
4305 */
4306static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4307{
4308 struct asc_board *boardp = adv_dvc->drv_ptr;
4309
4310 BUG_ON(offset > adv_dvc->max_host_qng);
4311 return &boardp->adv_reqp[offset];
4312}
4313
51219358
MW		 4314/*
4315 * Send an idle command to the chip and wait for completion.
4316 *
4317 * Command completion is polled for once per microsecond.
4318 *
4319 * The function can be called from anywhere including an interrupt handler.
4320 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4321 * functions to prevent reentrancy.
4322 *
4323 * Return Values:
4324 * ADV_TRUE - command completed successfully
4325 * ADV_FALSE - command failed
4326 * ADV_ERROR - command timed out
4327 */
4328static int
4329AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
95cfab6c 4330 ushort idle_cmd, u32 idle_cmd_parameter)
51219358 4331{
95cfab6c 4332 int result, i, j;
51219358
MW		 4333 AdvPortAddr iop_base;
4334
4335 iop_base = asc_dvc->iop_base;
4336
4337 /*
4338 * Clear the idle command status which is set by the microcode
4339 * to a non-zero value to indicate when the command is completed.
4340 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4341 */
4342 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4343
4344 /*
4345 * Write the idle command value after the idle command parameter
4346 * has been written to avoid a race condition. If the order is not
4347 * followed, the microcode may process the idle command before the
4348 * parameters have been written to LRAM.
4349 */
4350 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4351 cpu_to_le32(idle_cmd_parameter));
4352 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4353
4354 /*
4355 * Tickle the RISC to tell it to process the idle command.
4356 */
4357 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4358 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4359 /*
4360 * Clear the tickle value. In the ASC-3550 the RISC flag
4361 * command 'clr_tickle_b' does not work unless the host
4362 * value is cleared.
4363 */
4364 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4365 }
4366
4367 /* Wait for up to 100 millisecond for the idle command to timeout. */
4368 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4369 /* Poll once each microsecond for command completion. */
4370 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4371 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4372 result);
4373 if (result != 0)
4374 return result;
4375 udelay(1);
4376 }
4377 }
4378
4379 BUG(); /* The idle command should never timeout. */
4380 return ADV_ERROR;
4381}
4382
4383/*
4384 * Reset SCSI Bus and purge all outstanding requests.
4385 *
4386 * Return Value:
4387 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4388 * ADV_FALSE(0) - Microcode command failed.
4389 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4390 * may be hung which requires driver recovery.
4391 */
4392static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4393{
4394 int status;
4395
4396 /*
4397 * Send the SCSI Bus Reset idle start idle command which asserts
4398 * the SCSI Bus Reset signal.
4399 */
4400 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4401 if (status != ADV_TRUE) {
4402 return status;
4403 }
4404
4405 /*
4406 * Delay for the specified SCSI Bus Reset hold time.
4407 *
4408 * The hold time delay is done on the host because the RISC has no
4409 * microsecond accurate timer.
4410 */
4411 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4412
4413 /*
4414 * Send the SCSI Bus Reset end idle command which de-asserts
4415 * the SCSI Bus Reset signal and purges any pending requests.
4416 */
4417 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4418 if (status != ADV_TRUE) {
4419 return status;
4420 }
4421
4422 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4423
4424 return status;
4425}
4426
4427/*
4428 * Initialize the ASC-3550.
4429 *
4430 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4431 *
4432 * For a non-fatal error return a warning code. If there are no warnings
4433 * then 0 is returned.
4434 *
4435 * Needed after initialization for error recovery.
4436 */
4437static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4438{
989bb5f5
JSR		 4439 const struct firmware *fw;
4440 const char fwname[] = "advansys/3550.bin";
51219358
MW		 4441 AdvPortAddr iop_base;
4442 ushort warn_code;
4443 int begin_addr;
4444 int end_addr;
4445 ushort code_sum;
4446 int word;
4447 int i;
989bb5f5
JSR		 4448 int err;
4449 unsigned long chksum;
51219358
MW		 4450 ushort scsi_cfg1;
4451 uchar tid;
4452 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4453 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4454 uchar max_cmd[ADV_MAX_TID + 1];
4455
4456 /* If there is already an error, don't continue. */
4457 if (asc_dvc->err_code != 0)
4458 return ADV_ERROR;
4459
4460 /*
4461 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4462 */
4463 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4464 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4465 return ADV_ERROR;
4466 }
4467
4468 warn_code = 0;
4469 iop_base = asc_dvc->iop_base;
4470
4471 /*
4472 * Save the RISC memory BIOS region before writing the microcode.
4473 * The BIOS may already be loaded and using its RISC LRAM region
4474 * so its region must be saved and restored.
4475 *
4476 * Note: This code makes the assumption, which is currently true,
4477 * that a chip reset does not clear RISC LRAM.
4478 */
4479 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4480 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4481 bios_mem[i]);
4482 }
4483
4484 /*
4485 * Save current per TID negotiated values.
4486 */
4487 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4488 ushort bios_version, major, minor;
4489
4490 bios_version =
4491 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4492 major = (bios_version >> 12) & 0xF;
4493 minor = (bios_version >> 8) & 0xF;
4494 if (major < 3 || (major == 3 && minor == 1)) {
4495 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4496 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4497 } else {
4498 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4499 }
4500 }
4501 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4502 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4503 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4504 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4505 max_cmd[tid]);
4506 }
4507
989bb5f5
JSR		 4508 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4509 if (err) {
4510 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4511 fwname, err);
cf747445 4512 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4513 return err;
4514 }
4515 if (fw->size < 4) {
4516 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4517 fw->size, fwname);
4518 release_firmware(fw);
cf747445 4519 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4520 return -EINVAL;
4521 }
4522 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4523 (fw->data[1] << 8) | fw->data[0];
4524 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4525 fw->size - 4, ADV_3550_MEMSIZE,
4526 chksum);
4527 release_firmware(fw);
51219358
MW		 4528 if (asc_dvc->err_code)
4529 return ADV_ERROR;
4530
4531 /*
4532 * Restore the RISC memory BIOS region.
4533 */
4534 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4535 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4536 bios_mem[i]);
4537 }
4538
4539 /*
4540 * Calculate and write the microcode code checksum to the microcode
4541 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4542 */
4543 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4544 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4545 code_sum = 0;
4546 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4547 for (word = begin_addr; word < end_addr; word += 2) {
4548 code_sum += AdvReadWordAutoIncLram(iop_base);
4549 }
4550 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4551
4552 /*
4553 * Read and save microcode version and date.
4554 */
4555 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4556 asc_dvc->cfg->mcode_date);
4557 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4558 asc_dvc->cfg->mcode_version);
4559
4560 /*
4561 * Set the chip type to indicate the ASC3550.
4562 */
4563 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4564
4565 /*
4566 * If the PCI Configuration Command Register "Parity Error Response
4567 * Control" Bit was clear (0), then set the microcode variable
4568 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4569 * to ignore DMA parity errors.
4570 */
4571 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4572 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4573 word |= CONTROL_FLAG_IGNORE_PERR;
4574 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4575 }
4576
4577 /*
4578 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4579 * threshold of 128 bytes. This register is only accessible to the host.
4580 */
4581 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4582 START_CTL_EMFU | READ_CMD_MRM);
4583
4584 /*
4585 * Microcode operating variables for WDTR, SDTR, and command tag
4586 * queuing will be set in slave_configure() based on what a
4587 * device reports it is capable of in Inquiry byte 7.
4588 *
4589 * If SCSI Bus Resets have been disabled, then directly set
4590 * SDTR and WDTR from the EEPROM configuration. This will allow
4591 * the BIOS and warm boot to work without a SCSI bus hang on
4592 * the Inquiry caused by host and target mismatched DTR values.
4593 * Without the SCSI Bus Reset, before an Inquiry a device can't
4594 * be assumed to be in Asynchronous, Narrow mode.
4595 */
4596 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4597 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4598 asc_dvc->wdtr_able);
4599 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4600 asc_dvc->sdtr_able);
4601 }
4602
4603 /*
4604 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4605 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4606 * bitmask. These values determine the maximum SDTR speed negotiated
4607 * with a device.
4608 *
4609 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4610 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4611 * without determining here whether the device supports SDTR.
4612 *
4613 * 4-bit speed SDTR speed name
4614 * =========== ===============
4615 * 0000b (0x0) SDTR disabled
4616 * 0001b (0x1) 5 Mhz
4617 * 0010b (0x2) 10 Mhz
4618 * 0011b (0x3) 20 Mhz (Ultra)
4619 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4620 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4621 * 0110b (0x6) Undefined
4622 * .
4623 * 1111b (0xF) Undefined
4624 */
4625 word = 0;
4626 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4627 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4628 /* Set Ultra speed for TID 'tid'. */
4629 word |= (0x3 << (4 * (tid % 4)));
4630 } else {
4631 /* Set Fast speed for TID 'tid'. */
4632 word |= (0x2 << (4 * (tid % 4)));
4633 }
4634 if (tid == 3) { /* Check if done with sdtr_speed1. */
4635 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4636 word = 0;
4637 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4638 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4639 word = 0;
4640 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4641 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4642 word = 0;
4643 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4644 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4645 /* End of loop. */
4646 }
4647 }
4648
4649 /*
4650 * Set microcode operating variable for the disconnect per TID bitmask.
4651 */
4652 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4653 asc_dvc->cfg->disc_enable);
4654
4655 /*
4656 * Set SCSI_CFG0 Microcode Default Value.
4657 *
4658 * The microcode will set the SCSI_CFG0 register using this value
4659 * after it is started below.
4660 */
4661 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4662 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4663 asc_dvc->chip_scsi_id);
4664
4665 /*
4666 * Determine SCSI_CFG1 Microcode Default Value.
4667 *
4668 * The microcode will set the SCSI_CFG1 register using this value
4669 * after it is started below.
4670 */
4671
4672 /* Read current SCSI_CFG1 Register value. */
4673 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4674
4675 /*
4676 * If all three connectors are in use, return an error.
4677 */
4678 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4679 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4680 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4681 return ADV_ERROR;
4682 }
4683
4684 /*
4685 * If the internal narrow cable is reversed all of the SCSI_CTRL
4686 * register signals will be set. Check for and return an error if
4687 * this condition is found.
4688 */
4689 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4690 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4691 return ADV_ERROR;
4692 }
4693
4694 /*
4695 * If this is a differential board and a single-ended device
4696 * is attached to one of the connectors, return an error.
4697 */
4698 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4699 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4700 return ADV_ERROR;
4701 }
4702
4703 /*
4704 * If automatic termination control is enabled, then set the
4705 * termination value based on a table listed in a_condor.h.
4706 *
4707 * If manual termination was specified with an EEPROM setting
4708 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4709 * is ready to be 'ored' into SCSI_CFG1.
4710 */
4711 if (asc_dvc->cfg->termination == 0) {
4712 /*
4713 * The software always controls termination by setting TERM_CTL_SEL.
4714 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4715 */
4716 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4717
4718 switch (scsi_cfg1 & CABLE_DETECT) {
4719 /* TERM_CTL_H: on, TERM_CTL_L: on */
4720 case 0x3:
4721 case 0x7:
4722 case 0xB:
4723 case 0xD:
4724 case 0xE:
4725 case 0xF:
4726 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4727 break;
4728
4729 /* TERM_CTL_H: on, TERM_CTL_L: off */
4730 case 0x1:
4731 case 0x5:
4732 case 0x9:
4733 case 0xA:
4734 case 0xC:
4735 asc_dvc->cfg->termination |= TERM_CTL_H;
4736 break;
4737
4738 /* TERM_CTL_H: off, TERM_CTL_L: off */
4739 case 0x2:
4740 case 0x6:
4741 break;
4742 }
4743 }
4744
4745 /*
4746 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4747 */
4748 scsi_cfg1 &= ~TERM_CTL;
4749
4750 /*
4751 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4752 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4753 * referenced, because the hardware internally inverts
4754 * the Termination High and Low bits if TERM_POL is set.
4755 */
4756 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4757
4758 /*
4759 * Set SCSI_CFG1 Microcode Default Value
4760 *
4761 * Set filter value and possibly modified termination control
4762 * bits in the Microcode SCSI_CFG1 Register Value.
4763 *
4764 * The microcode will set the SCSI_CFG1 register using this value
4765 * after it is started below.
4766 */
4767 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4768 FLTR_DISABLE | scsi_cfg1);
4769
4770 /*
4771 * Set MEM_CFG Microcode Default Value
4772 *
4773 * The microcode will set the MEM_CFG register using this value
4774 * after it is started below.
4775 *
4776 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4777 * are defined.
4778 *
4779 * ASC-3550 has 8KB internal memory.
4780 */
4781 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4782 BIOS_EN | RAM_SZ_8KB);
4783
4784 /*
4785 * Set SEL_MASK Microcode Default Value
4786 *
4787 * The microcode will set the SEL_MASK register using this value
4788 * after it is started below.
4789 */
4790 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4791 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4792
4793 AdvBuildCarrierFreelist(asc_dvc);
4794
4795 /*
4796 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4797 */
4798
98b96a7d
HR		 4799 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4800 if (!asc_dvc->icq_sp) {
51219358
MW		 4801 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4802 return ADV_ERROR;
4803 }
51219358
MW		 4804
4805 /*
4806 * Set RISC ICQ physical address start value.
4807 */
4808 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4809
4810 /*
4811 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4812 */
98b96a7d
HR		 4813 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4814 if (!asc_dvc->irq_sp) {
51219358
MW		 4815 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4816 return ADV_ERROR;
4817 }
51219358
MW		 4818
4819 /*
4820 * Set RISC IRQ physical address start value.
4821 */
4822 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4823 asc_dvc->carr_pending_cnt = 0;
4824
4825 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4826 (ADV_INTR_ENABLE_HOST_INTR |
4827 ADV_INTR_ENABLE_GLOBAL_INTR));
4828
4829 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4830 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4831
4832 /* finally, finally, gentlemen, start your engine */
4833 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4834
4835 /*
4836 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4837 * Resets should be performed. The RISC has to be running
4838 * to issue a SCSI Bus Reset.
4839 */
4840 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4841 /*
4842 * If the BIOS Signature is present in memory, restore the
4843 * BIOS Handshake Configuration Table and do not perform
4844 * a SCSI Bus Reset.
4845 */
4846 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4847 0x55AA) {
4848 /*
4849 * Restore per TID negotiated values.
4850 */
4851 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4852 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4853 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4854 tagqng_able);
4855 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4856 AdvWriteByteLram(iop_base,
4857 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4858 max_cmd[tid]);
4859 }
4860 } else {
4861 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4862 warn_code = ASC_WARN_BUSRESET_ERROR;
4863 }
4864 }
4865 }
4866
4867 return warn_code;
4868}
4869
4870/*
4871 * Initialize the ASC-38C0800.
4872 *
4873 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4874 *
4875 * For a non-fatal error return a warning code. If there are no warnings
4876 * then 0 is returned.
4877 *
4878 * Needed after initialization for error recovery.
4879 */
4880static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4881{
989bb5f5
JSR		 4882 const struct firmware *fw;
4883 const char fwname[] = "advansys/38C0800.bin";
51219358
MW		 4884 AdvPortAddr iop_base;
4885 ushort warn_code;
4886 int begin_addr;
4887 int end_addr;
4888 ushort code_sum;
4889 int word;
4890 int i;
989bb5f5
JSR		 4891 int err;
4892 unsigned long chksum;
51219358
MW		 4893 ushort scsi_cfg1;
4894 uchar byte;
4895 uchar tid;
4896 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4897 ushort wdtr_able, sdtr_able, tagqng_able;
4898 uchar max_cmd[ADV_MAX_TID + 1];
4899
4900 /* If there is already an error, don't continue. */
4901 if (asc_dvc->err_code != 0)
4902 return ADV_ERROR;
4903
4904 /*
4905 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4906 */
4907 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4908 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4909 return ADV_ERROR;
4910 }
4911
4912 warn_code = 0;
4913 iop_base = asc_dvc->iop_base;
4914
4915 /*
4916 * Save the RISC memory BIOS region before writing the microcode.
4917 * The BIOS may already be loaded and using its RISC LRAM region
4918 * so its region must be saved and restored.
4919 *
4920 * Note: This code makes the assumption, which is currently true,
4921 * that a chip reset does not clear RISC LRAM.
4922 */
4923 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4924 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4925 bios_mem[i]);
4926 }
4927
4928 /*
4929 * Save current per TID negotiated values.
4930 */
4931 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4932 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4933 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4934 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4935 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4936 max_cmd[tid]);
4937 }
4938
4939 /*
4940 * RAM BIST (RAM Built-In Self Test)
4941 *
4942 * Address : I/O base + offset 0x38h register (byte).
4943 * Function: Bit 7-6(RW) : RAM mode
4944 * Normal Mode : 0x00
4945 * Pre-test Mode : 0x40
4946 * RAM Test Mode : 0x80
4947 * Bit 5 : unused
4948 * Bit 4(RO) : Done bit
4949 * Bit 3-0(RO) : Status
4950 * Host Error : 0x08
4951 * Int_RAM Error : 0x04
4952 * RISC Error : 0x02
4953 * SCSI Error : 0x01
4954 * No Error : 0x00
4955 *
4956 * Note: RAM BIST code should be put right here, before loading the
4957 * microcode and after saving the RISC memory BIOS region.
4958 */
4959
4960 /*
4961 * LRAM Pre-test
4962 *
4963 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
4964 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
4965 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
4966 * to NORMAL_MODE, return an error too.
4967 */
4968 for (i = 0; i < 2; i++) {
4969 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
4970 mdelay(10); /* Wait for 10ms before reading back. */
4971 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4972 if ((byte & RAM_TEST_DONE) == 0
4973 || (byte & 0x0F) != PRE_TEST_VALUE) {
4974 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4975 return ADV_ERROR;
4976 }
4977
4978 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
4979 mdelay(10); /* Wait for 10ms before reading back. */
4980 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
4981 != NORMAL_VALUE) {
4982 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4983 return ADV_ERROR;
4984 }
4985 }
4986
4987 /*
4988 * LRAM Test - It takes about 1.5 ms to run through the test.
4989 *
4990 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
4991 * If Done bit not set or Status not 0, save register byte, set the
4992 * err_code, and return an error.
4993 */
4994 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
4995 mdelay(10); /* Wait for 10ms before checking status. */
4996
4997 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4998 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
4999 /* Get here if Done bit not set or Status not 0. */
5000 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5001 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5002 return ADV_ERROR;
5003 }
5004
5005 /* We need to reset back to normal mode after LRAM test passes. */
5006 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5007
989bb5f5
JSR		 5008 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5009 if (err) {
5010 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5011 fwname, err);
cf747445 5012 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5013 return err;
5014 }
5015 if (fw->size < 4) {
5016 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5017 fw->size, fwname);
5018 release_firmware(fw);
cf747445 5019 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5020 return -EINVAL;
5021 }
5022 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5023 (fw->data[1] << 8) | fw->data[0];
5024 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5025 fw->size - 4, ADV_38C0800_MEMSIZE,
5026 chksum);
5027 release_firmware(fw);
51219358
MW		 5028 if (asc_dvc->err_code)
5029 return ADV_ERROR;
5030
5031 /*
5032 * Restore the RISC memory BIOS region.
5033 */
5034 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5035 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5036 bios_mem[i]);
5037 }
5038
5039 /*
5040 * Calculate and write the microcode code checksum to the microcode
5041 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5042 */
5043 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5044 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5045 code_sum = 0;
5046 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5047 for (word = begin_addr; word < end_addr; word += 2) {
5048 code_sum += AdvReadWordAutoIncLram(iop_base);
5049 }
5050 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5051
5052 /*
5053 * Read microcode version and date.
5054 */
5055 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5056 asc_dvc->cfg->mcode_date);
5057 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5058 asc_dvc->cfg->mcode_version);
5059
5060 /*
5061 * Set the chip type to indicate the ASC38C0800.
5062 */
5063 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5064
5065 /*
5066 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5067 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5068 * cable detection and then we are able to read C_DET[3:0].
5069 *
5070 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5071 * Microcode Default Value' section below.
5072 */
5073 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5074 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5075 scsi_cfg1 | DIS_TERM_DRV);
5076
5077 /*
5078 * If the PCI Configuration Command Register "Parity Error Response
5079 * Control" Bit was clear (0), then set the microcode variable
5080 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5081 * to ignore DMA parity errors.
5082 */
5083 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5084 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5085 word |= CONTROL_FLAG_IGNORE_PERR;
5086 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5087 }
5088
5089 /*
5090 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5091 * bits for the default FIFO threshold.
5092 *
5093 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5094 *
5095 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5096 */
5097 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5098 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5099 READ_CMD_MRM);
5100
5101 /*
5102 * Microcode operating variables for WDTR, SDTR, and command tag
5103 * queuing will be set in slave_configure() based on what a
5104 * device reports it is capable of in Inquiry byte 7.
5105 *
5106 * If SCSI Bus Resets have been disabled, then directly set
5107 * SDTR and WDTR from the EEPROM configuration. This will allow
5108 * the BIOS and warm boot to work without a SCSI bus hang on
5109 * the Inquiry caused by host and target mismatched DTR values.
5110 * Without the SCSI Bus Reset, before an Inquiry a device can't
5111 * be assumed to be in Asynchronous, Narrow mode.
5112 */
5113 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5114 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5115 asc_dvc->wdtr_able);
5116 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5117 asc_dvc->sdtr_able);
5118 }
5119
5120 /*
5121 * Set microcode operating variables for DISC and SDTR_SPEED1,
5122 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5123 * configuration values.
5124 *
5125 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5126 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5127 * without determining here whether the device supports SDTR.
5128 */
5129 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5130 asc_dvc->cfg->disc_enable);
5131 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5132 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5133 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5134 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5135
5136 /*
5137 * Set SCSI_CFG0 Microcode Default Value.
5138 *
5139 * The microcode will set the SCSI_CFG0 register using this value
5140 * after it is started below.
5141 */
5142 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5143 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5144 asc_dvc->chip_scsi_id);
5145
5146 /*
5147 * Determine SCSI_CFG1 Microcode Default Value.
5148 *
5149 * The microcode will set the SCSI_CFG1 register using this value
5150 * after it is started below.
5151 */
5152
5153 /* Read current SCSI_CFG1 Register value. */
5154 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5155
5156 /*
5157 * If the internal narrow cable is reversed all of the SCSI_CTRL
5158 * register signals will be set. Check for and return an error if
5159 * this condition is found.
5160 */
5161 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5162 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5163 return ADV_ERROR;
5164 }
5165
5166 /*
5167 * All kind of combinations of devices attached to one of four
5168 * connectors are acceptable except HVD device attached. For example,
5169 * LVD device can be attached to SE connector while SE device attached
5170 * to LVD connector. If LVD device attached to SE connector, it only
5171 * runs up to Ultra speed.
5172 *
5173 * If an HVD device is attached to one of LVD connectors, return an
5174 * error. However, there is no way to detect HVD device attached to
5175 * SE connectors.
5176 */
5177 if (scsi_cfg1 & HVD) {
5178 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5179 return ADV_ERROR;
5180 }
5181
5182 /*
5183 * If either SE or LVD automatic termination control is enabled, then
5184 * set the termination value based on a table listed in a_condor.h.
5185 *
5186 * If manual termination was specified with an EEPROM setting then
5187 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5188 * to be 'ored' into SCSI_CFG1.
5189 */
5190 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5191 /* SE automatic termination control is enabled. */
5192 switch (scsi_cfg1 & C_DET_SE) {
5193 /* TERM_SE_HI: on, TERM_SE_LO: on */
5194 case 0x1:
5195 case 0x2:
5196 case 0x3:
5197 asc_dvc->cfg->termination |= TERM_SE;
5198 break;
5199
5200 /* TERM_SE_HI: on, TERM_SE_LO: off */
5201 case 0x0:
5202 asc_dvc->cfg->termination |= TERM_SE_HI;
5203 break;
5204 }
5205 }
5206
5207 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5208 /* LVD automatic termination control is enabled. */
5209 switch (scsi_cfg1 & C_DET_LVD) {
5210 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5211 case 0x4:
5212 case 0x8:
5213 case 0xC:
5214 asc_dvc->cfg->termination |= TERM_LVD;
5215 break;
5216
5217 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5218 case 0x0:
5219 break;
5220 }
5221 }
5222
5223 /*
5224 * Clear any set TERM_SE and TERM_LVD bits.
5225 */
5226 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5227
5228 /*
5229 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5230 */
5231 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5232
5233 /*
5234 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5235 * bits and set possibly modified termination control bits in the
5236 * Microcode SCSI_CFG1 Register Value.
5237 */
5238 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5239
5240 /*
5241 * Set SCSI_CFG1 Microcode Default Value
5242 *
5243 * Set possibly modified termination control and reset DIS_TERM_DRV
5244 * bits in the Microcode SCSI_CFG1 Register Value.
5245 *
5246 * The microcode will set the SCSI_CFG1 register using this value
5247 * after it is started below.
5248 */
5249 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5250
5251 /*
5252 * Set MEM_CFG Microcode Default Value
5253 *
5254 * The microcode will set the MEM_CFG register using this value
5255 * after it is started below.
5256 *
5257 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5258 * are defined.
5259 *
5260 * ASC-38C0800 has 16KB internal memory.
5261 */
5262 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5263 BIOS_EN | RAM_SZ_16KB);
5264
5265 /*
5266 * Set SEL_MASK Microcode Default Value
5267 *
5268 * The microcode will set the SEL_MASK register using this value
5269 * after it is started below.
5270 */
5271 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5272 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5273
5274 AdvBuildCarrierFreelist(asc_dvc);
5275
5276 /*
5277 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5278 */
5279
98b96a7d
HR		 5280 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5281 if (!asc_dvc->icq_sp) {
5282 ASC_DBG(0, "Failed to get ICQ carrier\n");
51219358
MW		 5283 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5284 return ADV_ERROR;
5285 }
51219358
MW		 5286
5287 /*
5288 * Set RISC ICQ physical address start value.
5289 * carr_pa is LE, must be native before write
5290 */
5291 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5292
5293 /*
5294 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5295 */
98b96a7d
HR		 5296 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5297 if (!asc_dvc->irq_sp) {
5298 ASC_DBG(0, "Failed to get IRQ carrier\n");
51219358
MW		 5299 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5300 return ADV_ERROR;
5301 }
51219358
MW		 5302
5303 /*
5304 * Set RISC IRQ physical address start value.
5305 *
5306 * carr_pa is LE, must be native before write *
5307 */
5308 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5309 asc_dvc->carr_pending_cnt = 0;
5310
5311 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5312 (ADV_INTR_ENABLE_HOST_INTR |
5313 ADV_INTR_ENABLE_GLOBAL_INTR));
5314
5315 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5316 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5317
5318 /* finally, finally, gentlemen, start your engine */
5319 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5320
5321 /*
5322 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5323 * Resets should be performed. The RISC has to be running
5324 * to issue a SCSI Bus Reset.
5325 */
5326 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5327 /*
5328 * If the BIOS Signature is present in memory, restore the
5329 * BIOS Handshake Configuration Table and do not perform
5330 * a SCSI Bus Reset.
5331 */
5332 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5333 0x55AA) {
5334 /*
5335 * Restore per TID negotiated values.
5336 */
5337 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5338 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5339 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5340 tagqng_able);
5341 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5342 AdvWriteByteLram(iop_base,
5343 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5344 max_cmd[tid]);
5345 }
5346 } else {
5347 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5348 warn_code = ASC_WARN_BUSRESET_ERROR;
5349 }
5350 }
5351 }
5352
5353 return warn_code;
5354}
5355
5356/*
5357 * Initialize the ASC-38C1600.
5358 *
5359 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5360 *
5361 * For a non-fatal error return a warning code. If there are no warnings
5362 * then 0 is returned.
5363 *
5364 * Needed after initialization for error recovery.
5365 */
5366static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5367{
989bb5f5
JSR		 5368 const struct firmware *fw;
5369 const char fwname[] = "advansys/38C1600.bin";
51219358
MW		 5370 AdvPortAddr iop_base;
5371 ushort warn_code;
5372 int begin_addr;
5373 int end_addr;
5374 ushort code_sum;
5375 long word;
5376 int i;
989bb5f5
JSR		 5377 int err;
5378 unsigned long chksum;
51219358
MW		 5379 ushort scsi_cfg1;
5380 uchar byte;
5381 uchar tid;
5382 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5383 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5384 uchar max_cmd[ASC_MAX_TID + 1];
5385
5386 /* If there is already an error, don't continue. */
5387 if (asc_dvc->err_code != 0) {
5388 return ADV_ERROR;
5389 }
5390
5391 /*
5392 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5393 */
5394 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5395 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5396 return ADV_ERROR;
5397 }
5398
5399 warn_code = 0;
5400 iop_base = asc_dvc->iop_base;
5401
5402 /*
5403 * Save the RISC memory BIOS region before writing the microcode.
5404 * The BIOS may already be loaded and using its RISC LRAM region
5405 * so its region must be saved and restored.
5406 *
5407 * Note: This code makes the assumption, which is currently true,
5408 * that a chip reset does not clear RISC LRAM.
5409 */
5410 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5411 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5412 bios_mem[i]);
5413 }
5414
5415 /*
5416 * Save current per TID negotiated values.
5417 */
5418 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5419 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5420 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5421 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5422 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5423 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5424 max_cmd[tid]);
5425 }
5426
5427 /*
5428 * RAM BIST (Built-In Self Test)
5429 *
5430 * Address : I/O base + offset 0x38h register (byte).
5431 * Function: Bit 7-6(RW) : RAM mode
5432 * Normal Mode : 0x00
5433 * Pre-test Mode : 0x40
5434 * RAM Test Mode : 0x80
5435 * Bit 5 : unused
5436 * Bit 4(RO) : Done bit
5437 * Bit 3-0(RO) : Status
5438 * Host Error : 0x08
5439 * Int_RAM Error : 0x04
5440 * RISC Error : 0x02
5441 * SCSI Error : 0x01
5442 * No Error : 0x00
5443 *
5444 * Note: RAM BIST code should be put right here, before loading the
5445 * microcode and after saving the RISC memory BIOS region.
5446 */
5447
5448 /*
5449 * LRAM Pre-test
5450 *
5451 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5452 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5453 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5454 * to NORMAL_MODE, return an error too.
5455 */
5456 for (i = 0; i < 2; i++) {
5457 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5458 mdelay(10); /* Wait for 10ms before reading back. */
5459 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5460 if ((byte & RAM_TEST_DONE) == 0
5461 || (byte & 0x0F) != PRE_TEST_VALUE) {
5462 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5463 return ADV_ERROR;
5464 }
5465
5466 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5467 mdelay(10); /* Wait for 10ms before reading back. */
5468 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5469 != NORMAL_VALUE) {
5470 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5471 return ADV_ERROR;
5472 }
5473 }
5474
5475 /*
5476 * LRAM Test - It takes about 1.5 ms to run through the test.
5477 *
5478 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5479 * If Done bit not set or Status not 0, save register byte, set the
5480 * err_code, and return an error.
5481 */
5482 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5483 mdelay(10); /* Wait for 10ms before checking status. */
5484
5485 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5486 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5487 /* Get here if Done bit not set or Status not 0. */
5488 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5489 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5490 return ADV_ERROR;
5491 }
5492
5493 /* We need to reset back to normal mode after LRAM test passes. */
5494 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5495
989bb5f5
JSR		 5496 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5497 if (err) {
5498 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5499 fwname, err);
cf747445 5500 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5501 return err;
5502 }
5503 if (fw->size < 4) {
5504 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5505 fw->size, fwname);
5506 release_firmware(fw);
cf747445 5507 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5508 return -EINVAL;
5509 }
5510 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5511 (fw->data[1] << 8) | fw->data[0];
5512 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5513 fw->size - 4, ADV_38C1600_MEMSIZE,
5514 chksum);
5515 release_firmware(fw);
51219358
MW		 5516 if (asc_dvc->err_code)
5517 return ADV_ERROR;
5518
5519 /*
5520 * Restore the RISC memory BIOS region.
5521 */
5522 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5523 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5524 bios_mem[i]);
5525 }
5526
5527 /*
5528 * Calculate and write the microcode code checksum to the microcode
5529 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5530 */
5531 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5532 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5533 code_sum = 0;
5534 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5535 for (word = begin_addr; word < end_addr; word += 2) {
5536 code_sum += AdvReadWordAutoIncLram(iop_base);
5537 }
5538 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5539
5540 /*
5541 * Read microcode version and date.
5542 */
5543 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5544 asc_dvc->cfg->mcode_date);
5545 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5546 asc_dvc->cfg->mcode_version);
5547
5548 /*
5549 * Set the chip type to indicate the ASC38C1600.
5550 */
5551 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5552
5553 /*
5554 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5555 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5556 * cable detection and then we are able to read C_DET[3:0].
5557 *
5558 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5559 * Microcode Default Value' section below.
5560 */
5561 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5562 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5563 scsi_cfg1 | DIS_TERM_DRV);
5564
5565 /*
5566 * If the PCI Configuration Command Register "Parity Error Response
5567 * Control" Bit was clear (0), then set the microcode variable
5568 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5569 * to ignore DMA parity errors.
5570 */
5571 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5572 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5573 word |= CONTROL_FLAG_IGNORE_PERR;
5574 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5575 }
5576
5577 /*
5578 * If the BIOS control flag AIPP (Asynchronous Information
5579 * Phase Protection) disable bit is not set, then set the firmware
5580 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5581 * AIPP checking and encoding.
5582 */
5583 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5584 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5585 word |= CONTROL_FLAG_ENABLE_AIPP;
5586 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5587 }
5588
5589 /*
5590 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5591 * and START_CTL_TH [3:2].
5592 */
5593 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5594 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5595
5596 /*
5597 * Microcode operating variables for WDTR, SDTR, and command tag
5598 * queuing will be set in slave_configure() based on what a
5599 * device reports it is capable of in Inquiry byte 7.
5600 *
5601 * If SCSI Bus Resets have been disabled, then directly set
5602 * SDTR and WDTR from the EEPROM configuration. This will allow
5603 * the BIOS and warm boot to work without a SCSI bus hang on
5604 * the Inquiry caused by host and target mismatched DTR values.
5605 * Without the SCSI Bus Reset, before an Inquiry a device can't
5606 * be assumed to be in Asynchronous, Narrow mode.
5607 */
5608 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5609 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5610 asc_dvc->wdtr_able);
5611 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5612 asc_dvc->sdtr_able);
5613 }
5614
5615 /*
5616 * Set microcode operating variables for DISC and SDTR_SPEED1,
5617 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5618 * configuration values.
5619 *
5620 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5621 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5622 * without determining here whether the device supports SDTR.
5623 */
5624 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5625 asc_dvc->cfg->disc_enable);
5626 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5627 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5628 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5629 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5630
5631 /*
5632 * Set SCSI_CFG0 Microcode Default Value.
5633 *
5634 * The microcode will set the SCSI_CFG0 register using this value
5635 * after it is started below.
5636 */
5637 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5638 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5639 asc_dvc->chip_scsi_id);
5640
5641 /*
5642 * Calculate SCSI_CFG1 Microcode Default Value.
5643 *
5644 * The microcode will set the SCSI_CFG1 register using this value
5645 * after it is started below.
5646 *
5647 * Each ASC-38C1600 function has only two cable detect bits.
5648 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5649 */
5650 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5651
5652 /*
5653 * If the cable is reversed all of the SCSI_CTRL register signals
5654 * will be set. Check for and return an error if this condition is
5655 * found.
5656 */
5657 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5658 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5659 return ADV_ERROR;
5660 }
5661
5662 /*
5663 * Each ASC-38C1600 function has two connectors. Only an HVD device
5664 * can not be connected to either connector. An LVD device or SE device
5665 * may be connected to either connecor. If an SE device is connected,
5666 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5667 *
5668 * If an HVD device is attached, return an error.
5669 */
5670 if (scsi_cfg1 & HVD) {
5671 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5672 return ADV_ERROR;
5673 }
5674
5675 /*
5676 * Each function in the ASC-38C1600 uses only the SE cable detect and
5677 * termination because there are two connectors for each function. Each
5678 * function may use either LVD or SE mode. Corresponding the SE automatic
5679 * termination control EEPROM bits are used for each function. Each
5680 * function has its own EEPROM. If SE automatic control is enabled for
5681 * the function, then set the termination value based on a table listed
5682 * in a_condor.h.
5683 *
5684 * If manual termination is specified in the EEPROM for the function,
5685 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5686 * ready to be 'ored' into SCSI_CFG1.
5687 */
5688 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5689 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5690 /* SE automatic termination control is enabled. */
5691 switch (scsi_cfg1 & C_DET_SE) {
5692 /* TERM_SE_HI: on, TERM_SE_LO: on */
5693 case 0x1:
5694 case 0x2:
5695 case 0x3:
5696 asc_dvc->cfg->termination |= TERM_SE;
5697 break;
5698
5699 case 0x0:
5700 if (PCI_FUNC(pdev->devfn) == 0) {
5701 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5702 } else {
5703 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5704 asc_dvc->cfg->termination |= TERM_SE_HI;
5705 }
5706 break;
5707 }
5708 }
5709
5710 /*
5711 * Clear any set TERM_SE bits.
5712 */
5713 scsi_cfg1 &= ~TERM_SE;
5714
5715 /*
5716 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5717 */
5718 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5719
5720 /*
5721 * Clear Big Endian and Terminator Polarity bits and set possibly
5722 * modified termination control bits in the Microcode SCSI_CFG1
5723 * Register Value.
5724 *
5725 * Big Endian bit is not used even on big endian machines.
5726 */
5727 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5728
5729 /*
5730 * Set SCSI_CFG1 Microcode Default Value
5731 *
5732 * Set possibly modified termination control bits in the Microcode
5733 * SCSI_CFG1 Register Value.
5734 *
5735 * The microcode will set the SCSI_CFG1 register using this value
5736 * after it is started below.
5737 */
5738 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5739
5740 /*
5741 * Set MEM_CFG Microcode Default Value
5742 *
5743 * The microcode will set the MEM_CFG register using this value
5744 * after it is started below.
5745 *
5746 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5747 * are defined.
5748 *
5749 * ASC-38C1600 has 32KB internal memory.
5750 *
5751 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5752 * out a special 16K Adv Library and Microcode version. After the issue
5753 * resolved, we should turn back to the 32K support. Both a_condor.h and
5754 * mcode.sas files also need to be updated.
5755 *
5756 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5757 * BIOS_EN | RAM_SZ_32KB);
5758 */
5759 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5760 BIOS_EN | RAM_SZ_16KB);
5761
5762 /*
5763 * Set SEL_MASK Microcode Default Value
5764 *
5765 * The microcode will set the SEL_MASK register using this value
5766 * after it is started below.
5767 */
5768 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5769 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5770
5771 AdvBuildCarrierFreelist(asc_dvc);
5772
5773 /*
5774 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5775 */
98b96a7d
HR		 5776 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5777 if (!asc_dvc->icq_sp) {
51219358
MW		 5778 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5779 return ADV_ERROR;
5780 }
51219358
MW		 5781
5782 /*
5783 * Set RISC ICQ physical address start value. Initialize the
5784 * COMMA register to the same value otherwise the RISC will
5785 * prematurely detect a command is available.
5786 */
5787 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5788 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5789 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5790
5791 /*
5792 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5793 */
98b96a7d
HR		 5794 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5795 if (!asc_dvc->irq_sp) {
51219358
MW		 5796 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5797 return ADV_ERROR;
5798 }
51219358
MW		 5799
5800 /*
5801 * Set RISC IRQ physical address start value.
5802 */
5803 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5804 asc_dvc->carr_pending_cnt = 0;
5805
5806 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5807 (ADV_INTR_ENABLE_HOST_INTR |
5808 ADV_INTR_ENABLE_GLOBAL_INTR));
5809 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5810 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5811
5812 /* finally, finally, gentlemen, start your engine */
5813 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5814
5815 /*
5816 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5817 * Resets should be performed. The RISC has to be running
5818 * to issue a SCSI Bus Reset.
5819 */
5820 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5821 /*
5822 * If the BIOS Signature is present in memory, restore the
5823 * per TID microcode operating variables.
5824 */
5825 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5826 0x55AA) {
5827 /*
5828 * Restore per TID negotiated values.
5829 */
5830 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5831 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5832 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5833 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5834 tagqng_able);
5835 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5836 AdvWriteByteLram(iop_base,
5837 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5838 max_cmd[tid]);
5839 }
5840 } else {
5841 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5842 warn_code = ASC_WARN_BUSRESET_ERROR;
5843 }
5844 }
5845 }
5846
5847 return warn_code;
5848}
5849
5850/*
5851 * Reset chip and SCSI Bus.
5852 *
5853 * Return Value:
5854 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5855 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5856 */
5857static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5858{
5859 int status;
5860 ushort wdtr_able, sdtr_able, tagqng_able;
5861 ushort ppr_able = 0;
5862 uchar tid, max_cmd[ADV_MAX_TID + 1];
5863 AdvPortAddr iop_base;
5864 ushort bios_sig;
5865
5866 iop_base = asc_dvc->iop_base;
5867
5868 /*
5869 * Save current per TID negotiated values.
5870 */
5871 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5872 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5873 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5874 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5875 }
5876 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5877 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5878 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5879 max_cmd[tid]);
5880 }
5881
5882 /*
5883 * Force the AdvInitAsc3550/38C0800Driver() function to
5884 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5885 * The initialization functions assumes a SCSI Bus Reset is not
5886 * needed if the BIOS signature word is present.
5887 */
5888 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5889 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5890
5891 /*
5892 * Stop chip and reset it.
5893 */
5894 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5895 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5896 mdelay(100);
5897 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5898 ADV_CTRL_REG_CMD_WR_IO_REG);
5899
5900 /*
5901 * Reset Adv Library error code, if any, and try
5902 * re-initializing the chip.
5903 */
5904 asc_dvc->err_code = 0;
5905 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5906 status = AdvInitAsc38C1600Driver(asc_dvc);
5907 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5908 status = AdvInitAsc38C0800Driver(asc_dvc);
5909 } else {
5910 status = AdvInitAsc3550Driver(asc_dvc);
5911 }
5912
5913 /* Translate initialization return value to status value. */
5914 if (status == 0) {
5915 status = ADV_TRUE;
5916 } else {
5917 status = ADV_FALSE;
5918 }
5919
5920 /*
5921 * Restore the BIOS signature word.
5922 */
5923 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5924
5925 /*
5926 * Restore per TID negotiated values.
5927 */
5928 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5929 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5930 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5931 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5932 }
5933 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5934 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5935 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5936 max_cmd[tid]);
5937 }
5938
5939 return status;
5940}
5941
5942/*
5943 * adv_async_callback() - Adv Library asynchronous event callback function.
5944 */
5945static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5946{
5947 switch (code) {
5948 case ADV_ASYNC_SCSI_BUS_RESET_DET:
5949 /*
5950 * The firmware detected a SCSI Bus reset.
5951 */
b352f923 5952 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
51219358
MW		 5953 break;
5954
5955 case ADV_ASYNC_RDMA_FAILURE:
5956 /*
5957 * Handle RDMA failure by resetting the SCSI Bus and
5958 * possibly the chip if it is unresponsive. Log the error
5959 * with a unique code.
5960 */
b352f923 5961 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
51219358
MW		 5962 AdvResetChipAndSB(adv_dvc_varp);
5963 break;
5964
5965 case ADV_HOST_SCSI_BUS_RESET:
5966 /*
5967 * Host generated SCSI bus reset occurred.
5968 */
b352f923 5969 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
51219358
MW		 5970 break;
5971
5972 default:
b352f923 5973 ASC_DBG(0, "unknown code 0x%x\n", code);
51219358
MW		 5974 break;
5975 }
5976}
5977
5978/*
5979 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
5980 *
5981 * Callback function for the Wide SCSI Adv Library.
5982 */
5983static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
5984{
9c17c62a
HR		 5985 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
5986 u32 srb_tag;
51219358
MW		 5987 adv_req_t *reqp;
5988 adv_sgblk_t *sgblkp;
5989 struct scsi_cmnd *scp;
95cfab6c 5990 u32 resid_cnt;
811ddc05 5991 dma_addr_t sense_addr;
51219358 5992
9c17c62a
HR		 5993 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
5994 adv_dvc_varp, scsiqp);
51219358
MW		 5995 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
5996
5997 /*
5998 * Get the adv_req_t structure for the command that has been
5999 * completed. The adv_req_t structure actually contains the
6000 * completed ADV_SCSI_REQ_Q structure.
6001 */
9c17c62a
HR		 6002 srb_tag = le32_to_cpu(scsiqp->srb_tag);
6003 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
51219358 6004
b352f923 6005 ASC_DBG(1, "scp 0x%p\n", scp);
51219358
MW		 6006 if (scp == NULL) {
6007 ASC_PRINT
6008 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6009 return;
6010 }
6011 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6012
9c17c62a
HR		 6013 reqp = (adv_req_t *)scp->host_scribble;
6014 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6015 if (reqp == NULL) {
6016 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6017 return;
6018 }
6019 /*
6020 * Remove backreferences to avoid duplicate
6021 * command completions.
6022 */
6023 scp->host_scribble = NULL;
6024 reqp->cmndp = NULL;
51219358 6025
9c17c62a
HR		 6026 ASC_STATS(boardp->shost, callback);
6027 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
51219358 6028
811ddc05
HR		 6029 sense_addr = le32_to_cpu(scsiqp->sense_addr);
6030 dma_unmap_single(boardp->dev, sense_addr,
6031 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6032
51219358
MW		 6033 /*
6034 * 'done_status' contains the command's ending status.
6035 */
6036 switch (scsiqp->done_status) {
6037 case QD_NO_ERROR:
b352f923 6038 ASC_DBG(2, "QD_NO_ERROR\n");
51219358
MW		 6039 scp->result = 0;
6040
6041 /*
6042 * Check for an underrun condition.
6043 *
6044 * If there was no error and an underrun condition, then
6045 * then return the number of underrun bytes.
6046 */
6047 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
52c334e9
MW		 6048 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6049 resid_cnt <= scsi_bufflen(scp)) {
b352f923 6050 ASC_DBG(1, "underrun condition %lu bytes\n",
51219358 6051 (ulong)resid_cnt);
52c334e9 6052 scsi_set_resid(scp, resid_cnt);
51219358
MW		 6053 }
6054 break;
6055
6056 case QD_WITH_ERROR:
b352f923 6057 ASC_DBG(2, "QD_WITH_ERROR\n");
51219358
MW		 6058 switch (scsiqp->host_status) {
6059 case QHSTA_NO_ERROR:
6060 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
b352f923 6061 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
51219358 6062 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
b80ca4f7 6063 SCSI_SENSE_BUFFERSIZE);
51219358
MW		 6064 /*
6065 * Note: The 'status_byte()' macro used by
6066 * target drivers defined in scsi.h shifts the
6067 * status byte returned by host drivers right
6068 * by 1 bit. This is why target drivers also
6069 * use right shifted status byte definitions.
6070 * For instance target drivers use
6071 * CHECK_CONDITION, defined to 0x1, instead of
6072 * the SCSI defined check condition value of
6073 * 0x2. Host drivers are supposed to return
6074 * the status byte as it is defined by SCSI.
6075 */
6076 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6077 STATUS_BYTE(scsiqp->scsi_status);
6078 } else {
6079 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6080 }
6081 break;
6082
6083 default:
6084 /* Some other QHSTA error occurred. */
b352f923 6085 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
51219358
MW		 6086 scp->result = HOST_BYTE(DID_BAD_TARGET);
6087 break;
6088 }
6089 break;
6090
6091 case QD_ABORTED_BY_HOST:
b352f923 6092 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
51219358
MW		 6093 scp->result =
6094 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6095 break;
6096
6097 default:
b352f923 6098 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
51219358
MW		 6099 scp->result =
6100 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6101 break;
6102 }
6103
6104 /*
6105 * If the 'init_tidmask' bit isn't already set for the target and the
6106 * current request finished normally, then set the bit for the target
6107 * to indicate that a device is present.
6108 */
6109 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6110 scsiqp->done_status == QD_NO_ERROR &&
6111 scsiqp->host_status == QHSTA_NO_ERROR) {
6112 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6113 }
6114
6115 asc_scsi_done(scp);
6116
6117 /*
6118 * Free all 'adv_sgblk_t' structures allocated for the request.
6119 */
6120 while ((sgblkp = reqp->sgblkp) != NULL) {
6121 /* Remove 'sgblkp' from the request list. */
6122 reqp->sgblkp = sgblkp->next_sgblkp;
6123
0ce53822
HR		 6124 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
6125 sgblkp->sg_addr);
51219358
MW		 6126 }
6127
b352f923 6128 ASC_DBG(1, "done\n");
51219358
MW		 6129}
6130
6131/*
6132 * Adv Library Interrupt Service Routine
6133 *
6134 * This function is called by a driver's interrupt service routine.
6135 * The function disables and re-enables interrupts.
6136 *
6137 * When a microcode idle command is completed, the ADV_DVC_VAR
6138 * 'idle_cmd_done' field is set to ADV_TRUE.
6139 *
6140 * Note: AdvISR() can be called when interrupts are disabled or even
6141 * when there is no hardware interrupt condition present. It will
6142 * always check for completed idle commands and microcode requests.
6143 * This is an important feature that shouldn't be changed because it
6144 * allows commands to be completed from polling mode loops.
6145 *
6146 * Return:
6147 * ADV_TRUE(1) - interrupt was pending
6148 * ADV_FALSE(0) - no interrupt was pending
6149 */
6150static int AdvISR(ADV_DVC_VAR *asc_dvc)
6151{
6152 AdvPortAddr iop_base;
6153 uchar int_stat;
6154 ushort target_bit;
6155 ADV_CARR_T *free_carrp;
95cfab6c 6156 __le32 irq_next_vpa;
51219358 6157 ADV_SCSI_REQ_Q *scsiq;
4b47e464 6158 adv_req_t *reqp;
51219358
MW		 6159
6160 iop_base = asc_dvc->iop_base;
6161
6162 /* Reading the register clears the interrupt. */
6163 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6164
6165 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6166 ADV_INTR_STATUS_INTRC)) == 0) {
6167 return ADV_FALSE;
6168 }
6169
6170 /*
6171 * Notify the driver of an asynchronous microcode condition by
6172 * calling the adv_async_callback function. The function
6173 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6174 */
6175 if (int_stat & ADV_INTR_STATUS_INTRB) {
6176 uchar intrb_code;
6177
6178 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6179
6180 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6181 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6182 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6183 asc_dvc->carr_pending_cnt != 0) {
6184 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6185 ADV_TICKLE_A);
6186 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6187 AdvWriteByteRegister(iop_base,
6188 IOPB_TICKLE,
6189 ADV_TICKLE_NOP);
6190 }
6191 }
6192 }
6193
6194 adv_async_callback(asc_dvc, intrb_code);
6195 }
6196
6197 /*
6198 * Check if the IRQ stopper carrier contains a completed request.
6199 */
6200 while (((irq_next_vpa =
6201 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6202 /*
6203 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6204 * The RISC will have set 'areq_vpa' to a virtual address.
6205 *
9fef6ba4 6206 * The firmware will have copied the ADV_SCSI_REQ_Q.scsiq_ptr
51219358 6207 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
9fef6ba4 6208 * below complements the conversion of ADV_SCSI_REQ_Q.scsiq_ptr'
51219358
MW		 6209 * in AdvExeScsiQueue().
6210 */
4b47e464
HR		 6211 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6212 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6213 asc_dvc->irq_sp, pa_offset);
6214 reqp = adv_get_reqp(asc_dvc, pa_offset);
6215 scsiq = &reqp->scsi_req_q;
51219358
MW		 6216
6217 /*
6218 * Request finished with good status and the queue was not
6219 * DMAed to host memory by the firmware. Set all status fields
6220 * to indicate good status.
6221 */
6222 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6223 scsiq->done_status = QD_NO_ERROR;
6224 scsiq->host_status = scsiq->scsi_status = 0;
6225 scsiq->data_cnt = 0L;
6226 }
6227
6228 /*
6229 * Advance the stopper pointer to the next carrier
6230 * ignoring the lower four bits. Free the previous
6231 * stopper carrier.
6232 */
6233 free_carrp = asc_dvc->irq_sp;
98b96a7d
HR		 6234 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6235 ASC_GET_CARRP(irq_next_vpa));
51219358 6236
98b96a7d 6237 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
51219358
MW		 6238 asc_dvc->carr_freelist = free_carrp;
6239 asc_dvc->carr_pending_cnt--;
6240
6241 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6242
6243 /*
6244 * Clear request microcode control flag.
6245 */
6246 scsiq->cntl = 0;
6247
6248 /*
6249 * Notify the driver of the completed request by passing
6250 * the ADV_SCSI_REQ_Q pointer to its callback function.
6251 */
6252 scsiq->a_flag |= ADV_SCSIQ_DONE;
6253 adv_isr_callback(asc_dvc, scsiq);
6254 /*
6255 * Note: After the driver callback function is called, 'scsiq'
6256 * can no longer be referenced.
6257 *
6258 * Fall through and continue processing other completed
6259 * requests...
6260 */
6261 }
6262 return ADV_TRUE;
6263}
6264
6265static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6266{
6267 if (asc_dvc->err_code == 0) {
6268 asc_dvc->err_code = err_code;
6269 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6270 err_code);
6271 }
6272 return err_code;
6273}
6274
6275static void AscAckInterrupt(PortAddr iop_base)
6276{
6277 uchar host_flag;
6278 uchar risc_flag;
6279 ushort loop;
6280
6281 loop = 0;
6282 do {
6283 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6284 if (loop++ > 0x7FFF) {
6285 break;
6286 }
6287 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6288 host_flag =
6289 AscReadLramByte(iop_base,
6290 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6291 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6292 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6293 AscSetChipStatus(iop_base, CIW_INT_ACK);
6294 loop = 0;
6295 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6296 AscSetChipStatus(iop_base, CIW_INT_ACK);
6297 if (loop++ > 3) {
6298 break;
6299 }
6300 }
6301 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
51219358
MW		 6302}
6303
6304static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6305{
afbb68c3 6306 const uchar *period_table;
51219358
MW		 6307 int max_index;
6308 int min_index;
6309 int i;
6310
6311 period_table = asc_dvc->sdtr_period_tbl;
6312 max_index = (int)asc_dvc->max_sdtr_index;
afbb68c3 6313 min_index = (int)asc_dvc->min_sdtr_index;
51219358
MW		 6314 if ((syn_time <= period_table[max_index])) {
6315 for (i = min_index; i < (max_index - 1); i++) {
6316 if (syn_time <= period_table[i]) {
6317 return (uchar)i;
6318 }
6319 }
6320 return (uchar)max_index;
6321 } else {
6322 return (uchar)(max_index + 1);
6323 }
6324}
6325
6326static uchar
6327AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6328{
6329 EXT_MSG sdtr_buf;
6330 uchar sdtr_period_index;
6331 PortAddr iop_base;
6332
6333 iop_base = asc_dvc->iop_base;
6334 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6335 sdtr_buf.msg_len = MS_SDTR_LEN;
6336 sdtr_buf.msg_req = EXTENDED_SDTR;
6337 sdtr_buf.xfer_period = sdtr_period;
6338 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6339 sdtr_buf.req_ack_offset = sdtr_offset;
6340 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6341 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6342 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6343 (uchar *)&sdtr_buf,
6344 sizeof(EXT_MSG) >> 1);
6345 return ((sdtr_period_index << 4) | sdtr_offset);
6346 } else {
6347 sdtr_buf.req_ack_offset = 0;
6348 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6349 (uchar *)&sdtr_buf,
6350 sizeof(EXT_MSG) >> 1);
6351 return 0;
6352 }
6353}
6354
6355static uchar
6356AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6357{
6358 uchar byte;
6359 uchar sdtr_period_ix;
6360
6361 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
afbb68c3 6362 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
51219358 6363 return 0xFF;
51219358
MW		 6364 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6365 return byte;
6366}
6367
d647c783 6368static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
51219358
MW		 6369{
6370 ASC_SCSI_BIT_ID_TYPE org_id;
6371 int i;
d647c783 6372 bool sta = true;
51219358
MW		 6373
6374 AscSetBank(iop_base, 1);
6375 org_id = AscReadChipDvcID(iop_base);
6376 for (i = 0; i <= ASC_MAX_TID; i++) {
6377 if (org_id == (0x01 << i))
6378 break;
6379 }
6380 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6381 AscWriteChipDvcID(iop_base, id);
6382 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6383 AscSetBank(iop_base, 0);
6384 AscSetChipSyn(iop_base, sdtr_data);
6385 if (AscGetChipSyn(iop_base) != sdtr_data) {
d647c783 6386 sta = false;
51219358
MW		 6387 }
6388 } else {
d647c783 6389 sta = false;
51219358
MW		 6390 }
6391 AscSetBank(iop_base, 1);
6392 AscWriteChipDvcID(iop_base, org_id);
6393 AscSetBank(iop_base, 0);
6394 return (sta);
6395}
6396
6397static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6398{
6399 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6400 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6401}
6402
6f0d2e1d 6403static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
51219358
MW		 6404{
6405 EXT_MSG ext_msg;
6406 EXT_MSG out_msg;
6407 ushort halt_q_addr;
ae26759e 6408 bool sdtr_accept;
51219358
MW		 6409 ushort int_halt_code;
6410 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6411 ASC_SCSI_BIT_ID_TYPE target_id;
6412 PortAddr iop_base;
6413 uchar tag_code;
6414 uchar q_status;
6415 uchar halt_qp;
6416 uchar sdtr_data;
6417 uchar target_ix;
6418 uchar q_cntl, tid_no;
6419 uchar cur_dvc_qng;
6420 uchar asyn_sdtr;
6421 uchar scsi_status;
d2411495 6422 struct asc_board *boardp;
51219358
MW		 6423
6424 BUG_ON(!asc_dvc->drv_ptr);
6425 boardp = asc_dvc->drv_ptr;
6426
6427 iop_base = asc_dvc->iop_base;
6428 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6429
6430 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6431 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6432 target_ix = AscReadLramByte(iop_base,
6433 (ushort)(halt_q_addr +
6434 (ushort)ASC_SCSIQ_B_TARGET_IX));
6435 q_cntl = AscReadLramByte(iop_base,
6436 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6437 tid_no = ASC_TIX_TO_TID(target_ix);
6438 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6439 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6440 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6441 } else {
6442 asyn_sdtr = 0;
6443 }
6444 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6445 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6446 AscSetChipSDTR(iop_base, 0, tid_no);
6447 boardp->sdtr_data[tid_no] = 0;
6448 }
6449 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6450 return;
51219358
MW		 6451 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6452 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6453 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6454 boardp->sdtr_data[tid_no] = asyn_sdtr;
6455 }
6456 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6457 return;
51219358
MW		 6458 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6459 AscMemWordCopyPtrFromLram(iop_base,
6460 ASCV_MSGIN_BEG,
6461 (uchar *)&ext_msg,
6462 sizeof(EXT_MSG) >> 1);
6463
6464 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6465 ext_msg.msg_req == EXTENDED_SDTR &&
6466 ext_msg.msg_len == MS_SDTR_LEN) {
ae26759e 6467 sdtr_accept = true;
51219358
MW		 6468 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6469
ae26759e 6470 sdtr_accept = false;
51219358
MW		 6471 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6472 }
6473 if ((ext_msg.xfer_period <
afbb68c3 6474 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
51219358
MW		 6475 || (ext_msg.xfer_period >
6476 asc_dvc->sdtr_period_tbl[asc_dvc->
6477 max_sdtr_index])) {
ae26759e 6478 sdtr_accept = false;
51219358
MW		 6479 ext_msg.xfer_period =
6480 asc_dvc->sdtr_period_tbl[asc_dvc->
afbb68c3 6481 min_sdtr_index];
51219358
MW		 6482 }
6483 if (sdtr_accept) {
6484 sdtr_data =
6485 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6486 ext_msg.req_ack_offset);
6487 if ((sdtr_data == 0xFF)) {
6488
6489 q_cntl |= QC_MSG_OUT;
6490 asc_dvc->init_sdtr &= ~target_id;
6491 asc_dvc->sdtr_done &= ~target_id;
6492 AscSetChipSDTR(iop_base, asyn_sdtr,
6493 tid_no);
6494 boardp->sdtr_data[tid_no] = asyn_sdtr;
6495 }
6496 }
6497 if (ext_msg.req_ack_offset == 0) {
6498
6499 q_cntl &= ~QC_MSG_OUT;
6500 asc_dvc->init_sdtr &= ~target_id;
6501 asc_dvc->sdtr_done &= ~target_id;
6502 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6503 } else {
6504 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
51219358
MW		 6505 q_cntl &= ~QC_MSG_OUT;
6506 asc_dvc->sdtr_done |= target_id;
6507 asc_dvc->init_sdtr |= target_id;
6508 asc_dvc->pci_fix_asyn_xfer &=
6509 ~target_id;
6510 sdtr_data =
6511 AscCalSDTRData(asc_dvc,
6512 ext_msg.xfer_period,
6513 ext_msg.
6514 req_ack_offset);
6515 AscSetChipSDTR(iop_base, sdtr_data,
6516 tid_no);
6517 boardp->sdtr_data[tid_no] = sdtr_data;
6518 } else {
51219358
MW		 6519 q_cntl |= QC_MSG_OUT;
6520 AscMsgOutSDTR(asc_dvc,
6521 ext_msg.xfer_period,
6522 ext_msg.req_ack_offset);
6523 asc_dvc->pci_fix_asyn_xfer &=
6524 ~target_id;
6525 sdtr_data =
6526 AscCalSDTRData(asc_dvc,
6527 ext_msg.xfer_period,
6528 ext_msg.
6529 req_ack_offset);
6530 AscSetChipSDTR(iop_base, sdtr_data,
6531 tid_no);
6532 boardp->sdtr_data[tid_no] = sdtr_data;
6533 asc_dvc->sdtr_done |= target_id;
6534 asc_dvc->init_sdtr |= target_id;
6535 }
6536 }
6537
6538 AscWriteLramByte(iop_base,
6539 (ushort)(halt_q_addr +
6540 (ushort)ASC_SCSIQ_B_CNTL),
6541 q_cntl);
6542 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6543 return;
51219358
MW		 6544 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6545 ext_msg.msg_req == EXTENDED_WDTR &&
6546 ext_msg.msg_len == MS_WDTR_LEN) {
6547
6548 ext_msg.wdtr_width = 0;
6549 AscMemWordCopyPtrToLram(iop_base,
6550 ASCV_MSGOUT_BEG,
6551 (uchar *)&ext_msg,
6552 sizeof(EXT_MSG) >> 1);
6553 q_cntl |= QC_MSG_OUT;
6554 AscWriteLramByte(iop_base,
6555 (ushort)(halt_q_addr +
6556 (ushort)ASC_SCSIQ_B_CNTL),
6557 q_cntl);
6558 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6559 return;
51219358
MW		 6560 } else {
6561
6562 ext_msg.msg_type = MESSAGE_REJECT;
6563 AscMemWordCopyPtrToLram(iop_base,
6564 ASCV_MSGOUT_BEG,
6565 (uchar *)&ext_msg,
6566 sizeof(EXT_MSG) >> 1);
6567 q_cntl |= QC_MSG_OUT;
6568 AscWriteLramByte(iop_base,
6569 (ushort)(halt_q_addr +
6570 (ushort)ASC_SCSIQ_B_CNTL),
6571 q_cntl);
6572 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6573 return;
51219358
MW		 6574 }
6575 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6576
6577 q_cntl |= QC_REQ_SENSE;
6578
6579 if ((asc_dvc->init_sdtr & target_id) != 0) {
6580
6581 asc_dvc->sdtr_done &= ~target_id;
6582
6583 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6584 q_cntl |= QC_MSG_OUT;
6585 AscMsgOutSDTR(asc_dvc,
6586 asc_dvc->
6587 sdtr_period_tbl[(sdtr_data >> 4) &
6588 (uchar)(asc_dvc->
6589 max_sdtr_index -
6590 1)],
6591 (uchar)(sdtr_data & (uchar)
6592 ASC_SYN_MAX_OFFSET));
6593 }
6594
6595 AscWriteLramByte(iop_base,
6596 (ushort)(halt_q_addr +
6597 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6598
6599 tag_code = AscReadLramByte(iop_base,
6600 (ushort)(halt_q_addr + (ushort)
6601 ASC_SCSIQ_B_TAG_CODE));
6602 tag_code &= 0xDC;
6603 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6604 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6605 ) {
6606
6607 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6608 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6609
6610 }
6611 AscWriteLramByte(iop_base,
6612 (ushort)(halt_q_addr +
6613 (ushort)ASC_SCSIQ_B_TAG_CODE),
6614 tag_code);
6615
6616 q_status = AscReadLramByte(iop_base,
6617 (ushort)(halt_q_addr + (ushort)
6618 ASC_SCSIQ_B_STATUS));
6619 q_status |= (QS_READY | QS_BUSY);
6620 AscWriteLramByte(iop_base,
6621 (ushort)(halt_q_addr +
6622 (ushort)ASC_SCSIQ_B_STATUS),
6623 q_status);
6624
6625 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6626 scsi_busy &= ~target_id;
6627 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6628
6629 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6630 return;
51219358
MW		 6631 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6632
6633 AscMemWordCopyPtrFromLram(iop_base,
6634 ASCV_MSGOUT_BEG,
6635 (uchar *)&out_msg,
6636 sizeof(EXT_MSG) >> 1);
6637
6638 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6639 (out_msg.msg_len == MS_SDTR_LEN) &&
6640 (out_msg.msg_req == EXTENDED_SDTR)) {
6641
6642 asc_dvc->init_sdtr &= ~target_id;
6643 asc_dvc->sdtr_done &= ~target_id;
6644 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6645 boardp->sdtr_data[tid_no] = asyn_sdtr;
6646 }
6647 q_cntl &= ~QC_MSG_OUT;
6648 AscWriteLramByte(iop_base,
6649 (ushort)(halt_q_addr +
6650 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6651 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6652 return;
51219358
MW		 6653 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6654
6655 scsi_status = AscReadLramByte(iop_base,
6656 (ushort)((ushort)halt_q_addr +
6657 (ushort)
6658 ASC_SCSIQ_SCSI_STATUS));
6659 cur_dvc_qng =
6660 AscReadLramByte(iop_base,
6661 (ushort)((ushort)ASC_QADR_BEG +
6662 (ushort)target_ix));
6663 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6664
6665 scsi_busy = AscReadLramByte(iop_base,
6666 (ushort)ASCV_SCSIBUSY_B);
6667 scsi_busy |= target_id;
6668 AscWriteLramByte(iop_base,
6669 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6670 asc_dvc->queue_full_or_busy |= target_id;
6671
6672 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6673 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6674 cur_dvc_qng -= 1;
6675 asc_dvc->max_dvc_qng[tid_no] =
6676 cur_dvc_qng;
6677
6678 AscWriteLramByte(iop_base,
6679 (ushort)((ushort)
6680 ASCV_MAX_DVC_QNG_BEG
6681 + (ushort)
6682 tid_no),
6683 cur_dvc_qng);
6684
6685 /*
6686 * Set the device queue depth to the
6687 * number of active requests when the
6688 * QUEUE FULL condition was encountered.
6689 */
6690 boardp->queue_full |= target_id;
6691 boardp->queue_full_cnt[tid_no] =
6692 cur_dvc_qng;
6693 }
6694 }
6695 }
6696 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6697 return;
51219358 6698 }
6f0d2e1d 6699 return;
51219358 6700}
1da177e4 6701
1da177e4 6702/*
51219358
MW		 6703 * void
6704 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
1da177e4 6705 *
51219358
MW		 6706 * Calling/Exit State:
6707 * none
1da177e4 6708 *
51219358
MW		 6709 * Description:
6710 * Input an ASC_QDONE_INFO structure from the chip
1da177e4 6711 */
51219358
MW		 6712static void
6713DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6714{
6715 int i;
6716 ushort word;
6717
6718 AscSetChipLramAddr(iop_base, s_addr);
6719 for (i = 0; i < 2 * words; i += 2) {
6720 if (i == 10) {
6721 continue;
6722 }
6723 word = inpw(iop_base + IOP_RAM_DATA);
6724 inbuf[i] = word & 0xff;
6725 inbuf[i + 1] = (word >> 8) & 0xff;
6726 }
6727 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6728}
6729
6730static uchar
6731_AscCopyLramScsiDoneQ(PortAddr iop_base,
6732 ushort q_addr,
95cfab6c 6733 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
51219358
MW		 6734{
6735 ushort _val;
6736 uchar sg_queue_cnt;
6737
6738 DvcGetQinfo(iop_base,
6739 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6740 (uchar *)scsiq,
6741 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6742
6743 _val = AscReadLramWord(iop_base,
6744 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6745 scsiq->q_status = (uchar)_val;
6746 scsiq->q_no = (uchar)(_val >> 8);
6747 _val = AscReadLramWord(iop_base,
6748 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6749 scsiq->cntl = (uchar)_val;
6750 sg_queue_cnt = (uchar)(_val >> 8);
6751 _val = AscReadLramWord(iop_base,
6752 (ushort)(q_addr +
6753 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6754 scsiq->sense_len = (uchar)_val;
6755 scsiq->extra_bytes = (uchar)(_val >> 8);
6756
6757 /*
6758 * Read high word of remain bytes from alternate location.
6759 */
95cfab6c
HR		 6760 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
6761 (ushort)(q_addr +
6762 (ushort)
6763 ASC_SCSIQ_W_ALT_DC1)))
51219358
MW		 6764 << 16);
6765 /*
6766 * Read low word of remain bytes from original location.
6767 */
6768 scsiq->remain_bytes += AscReadLramWord(iop_base,
6769 (ushort)(q_addr + (ushort)
6770 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
6771
6772 scsiq->remain_bytes &= max_dma_count;
6773 return sg_queue_cnt;
6774}
6775
6776/*
6777 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6778 *
6779 * Interrupt callback function for the Narrow SCSI Asc Library.
6780 */
6781static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6782{
9c17c62a
HR		 6783 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
6784 u32 srb_tag;
51219358 6785 struct scsi_cmnd *scp;
51219358 6786
b352f923 6787 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
51219358
MW		 6788 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6789
9c17c62a
HR		 6790 /*
6791 * Decrease the srb_tag by 1 to find the SCSI command
6792 */
6793 srb_tag = qdonep->d2.srb_tag - 1;
6794 scp = scsi_host_find_tag(boardp->shost, srb_tag);
b249c7fd 6795 if (!scp)
51219358 6796 return;
b249c7fd 6797
51219358
MW		 6798 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6799
9c17c62a 6800 ASC_STATS(boardp->shost, callback);
51219358 6801
b249c7fd 6802 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
b80ca4f7 6803 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
51219358
MW		 6804 /*
6805 * 'qdonep' contains the command's ending status.
6806 */
6807 switch (qdonep->d3.done_stat) {
6808 case QD_NO_ERROR:
b352f923 6809 ASC_DBG(2, "QD_NO_ERROR\n");
51219358
MW		 6810 scp->result = 0;
6811
6812 /*
6813 * Check for an underrun condition.
6814 *
6815 * If there was no error and an underrun condition, then
6816 * return the number of underrun bytes.
6817 */
52c334e9
MW		 6818 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
6819 qdonep->remain_bytes <= scsi_bufflen(scp)) {
b352f923 6820 ASC_DBG(1, "underrun condition %u bytes\n",
51219358 6821 (unsigned)qdonep->remain_bytes);
52c334e9 6822 scsi_set_resid(scp, qdonep->remain_bytes);
51219358
MW		 6823 }
6824 break;
6825
6826 case QD_WITH_ERROR:
b352f923 6827 ASC_DBG(2, "QD_WITH_ERROR\n");
51219358
MW		 6828 switch (qdonep->d3.host_stat) {
6829 case QHSTA_NO_ERROR:
6830 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
b352f923 6831 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
51219358 6832 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
b80ca4f7 6833 SCSI_SENSE_BUFFERSIZE);
51219358
MW		 6834 /*
6835 * Note: The 'status_byte()' macro used by
6836 * target drivers defined in scsi.h shifts the
6837 * status byte returned by host drivers right
6838 * by 1 bit. This is why target drivers also
6839 * use right shifted status byte definitions.
6840 * For instance target drivers use
6841 * CHECK_CONDITION, defined to 0x1, instead of
6842 * the SCSI defined check condition value of
6843 * 0x2. Host drivers are supposed to return
6844 * the status byte as it is defined by SCSI.
6845 */
6846 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6847 STATUS_BYTE(qdonep->d3.scsi_stat);
6848 } else {
6849 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
6850 }
6851 break;
6852
6853 default:
6854 /* QHSTA error occurred */
b352f923 6855 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
51219358
MW		 6856 scp->result = HOST_BYTE(DID_BAD_TARGET);
6857 break;
6858 }
6859 break;
6860
6861 case QD_ABORTED_BY_HOST:
b352f923 6862 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
51219358
MW		 6863 scp->result =
6864 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
6865 scsi_msg) |
6866 STATUS_BYTE(qdonep->d3.scsi_stat);
6867 break;
6868
6869 default:
b352f923 6870 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
51219358
MW		 6871 scp->result =
6872 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
6873 scsi_msg) |
6874 STATUS_BYTE(qdonep->d3.scsi_stat);
6875 break;
6876 }
6877
6878 /*
6879 * If the 'init_tidmask' bit isn't already set for the target and the
6880 * current request finished normally, then set the bit for the target
6881 * to indicate that a device is present.
6882 */
6883 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6884 qdonep->d3.done_stat == QD_NO_ERROR &&
6885 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
6886 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6887 }
1da177e4 6888
51219358 6889 asc_scsi_done(scp);
51219358
MW		 6890}
6891
6892static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
6893{
6894 uchar next_qp;
6895 uchar n_q_used;
6896 uchar sg_list_qp;
6897 uchar sg_queue_cnt;
6898 uchar q_cnt;
6899 uchar done_q_tail;
6900 uchar tid_no;
6901 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6902 ASC_SCSI_BIT_ID_TYPE target_id;
6903 PortAddr iop_base;
6904 ushort q_addr;
6905 ushort sg_q_addr;
6906 uchar cur_target_qng;
6907 ASC_QDONE_INFO scsiq_buf;
6908 ASC_QDONE_INFO *scsiq;
ae26759e 6909 bool false_overrun;
51219358
MW		 6910
6911 iop_base = asc_dvc->iop_base;
6912 n_q_used = 1;
6913 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
6914 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
6915 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
6916 next_qp = AscReadLramByte(iop_base,
6917 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
6918 if (next_qp != ASC_QLINK_END) {
6919 AscPutVarDoneQTail(iop_base, next_qp);
6920 q_addr = ASC_QNO_TO_QADDR(next_qp);
6921 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
6922 asc_dvc->max_dma_count);
6923 AscWriteLramByte(iop_base,
6924 (ushort)(q_addr +
6925 (ushort)ASC_SCSIQ_B_STATUS),
6926 (uchar)(scsiq->
6927 q_status & (uchar)~(QS_READY |
6928 QS_ABORTED)));
6929 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
6930 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
6931 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
6932 sg_q_addr = q_addr;
6933 sg_list_qp = next_qp;
6934 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
6935 sg_list_qp = AscReadLramByte(iop_base,
6936 (ushort)(sg_q_addr
6937 + (ushort)
6938 ASC_SCSIQ_B_FWD));
6939 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
6940 if (sg_list_qp == ASC_QLINK_END) {
6941 AscSetLibErrorCode(asc_dvc,
6942 ASCQ_ERR_SG_Q_LINKS);
6943 scsiq->d3.done_stat = QD_WITH_ERROR;
6944 scsiq->d3.host_stat =
6945 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
6946 goto FATAL_ERR_QDONE;
6947 }
6948 AscWriteLramByte(iop_base,
6949 (ushort)(sg_q_addr + (ushort)
6950 ASC_SCSIQ_B_STATUS),
6951 QS_FREE);
6952 }
6953 n_q_used = sg_queue_cnt + 1;
6954 AscPutVarDoneQTail(iop_base, sg_list_qp);
6955 }
6956 if (asc_dvc->queue_full_or_busy & target_id) {
6957 cur_target_qng = AscReadLramByte(iop_base,
6958 (ushort)((ushort)
6959 ASC_QADR_BEG
6960 + (ushort)
6961 scsiq->d2.
6962 target_ix));
6963 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
6964 scsi_busy = AscReadLramByte(iop_base, (ushort)
6965 ASCV_SCSIBUSY_B);
6966 scsi_busy &= ~target_id;
6967 AscWriteLramByte(iop_base,
6968 (ushort)ASCV_SCSIBUSY_B,
6969 scsi_busy);
6970 asc_dvc->queue_full_or_busy &= ~target_id;
6971 }
6972 }
6973 if (asc_dvc->cur_total_qng >= n_q_used) {
6974 asc_dvc->cur_total_qng -= n_q_used;
6975 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
6976 asc_dvc->cur_dvc_qng[tid_no]--;
6977 }
6978 } else {
6979 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
6980 scsiq->d3.done_stat = QD_WITH_ERROR;
6981 goto FATAL_ERR_QDONE;
6982 }
9c17c62a 6983 if ((scsiq->d2.srb_tag == 0UL) ||
51219358
MW		 6984 ((scsiq->q_status & QS_ABORTED) != 0)) {
6985 return (0x11);
6986 } else if (scsiq->q_status == QS_DONE) {
ae26759e
HR		 6987 /*
6988 * This is also curious.
6989 * false_overrun will _always_ be set to 'false'
6990 */
6991 false_overrun = false;
51219358 6992 if (scsiq->extra_bytes != 0) {
95cfab6c 6993 scsiq->remain_bytes += scsiq->extra_bytes;
51219358
MW		 6994 }
6995 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
6996 if (scsiq->d3.host_stat ==
6997 QHSTA_M_DATA_OVER_RUN) {
6998 if ((scsiq->
6999 cntl & (QC_DATA_IN | QC_DATA_OUT))
7000 == 0) {
7001 scsiq->d3.done_stat =
7002 QD_NO_ERROR;
7003 scsiq->d3.host_stat =
7004 QHSTA_NO_ERROR;
7005 } else if (false_overrun) {
7006 scsiq->d3.done_stat =
7007 QD_NO_ERROR;
7008 scsiq->d3.host_stat =
7009 QHSTA_NO_ERROR;
7010 }
7011 } else if (scsiq->d3.host_stat ==
7012 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7013 AscStopChip(iop_base);
7014 AscSetChipControl(iop_base,
7015 (uchar)(CC_SCSI_RESET
7016 | CC_HALT));
7017 udelay(60);
7018 AscSetChipControl(iop_base, CC_HALT);
7019 AscSetChipStatus(iop_base,
7020 CIW_CLR_SCSI_RESET_INT);
7021 AscSetChipStatus(iop_base, 0);
7022 AscSetChipControl(iop_base, 0);
7023 }
7024 }
7025 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7026 asc_isr_callback(asc_dvc, scsiq);
7027 } else {
7028 if ((AscReadLramByte(iop_base,
7029 (ushort)(q_addr + (ushort)
7030 ASC_SCSIQ_CDB_BEG))
7031 == START_STOP)) {
7032 asc_dvc->unit_not_ready &= ~target_id;
7033 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7034 asc_dvc->start_motor &=
7035 ~target_id;
7036 }
7037 }
7038 }
7039 return (1);
7040 } else {
7041 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7042 FATAL_ERR_QDONE:
7043 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7044 asc_isr_callback(asc_dvc, scsiq);
7045 }
7046 return (0x80);
7047 }
7048 }
7049 return (0);
7050}
1da177e4 7051
51219358
MW		 7052static int AscISR(ASC_DVC_VAR *asc_dvc)
7053{
7054 ASC_CS_TYPE chipstat;
7055 PortAddr iop_base;
7056 ushort saved_ram_addr;
7057 uchar ctrl_reg;
7058 uchar saved_ctrl_reg;
7059 int int_pending;
7060 int status;
7061 uchar host_flag;
1da177e4 7062
51219358 7063 iop_base = asc_dvc->iop_base;
ae26759e 7064 int_pending = ASC_FALSE;
1da177e4 7065
51219358
MW		 7066 if (AscIsIntPending(iop_base) == 0)
7067 return int_pending;
7068
7069 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
ae26759e 7070 return ASC_ERROR;
51219358
MW		 7071 }
7072 if (asc_dvc->in_critical_cnt != 0) {
7073 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
ae26759e 7074 return ASC_ERROR;
51219358
MW		 7075 }
7076 if (asc_dvc->is_in_int) {
7077 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
ae26759e 7078 return ASC_ERROR;
51219358 7079 }
ae26759e 7080 asc_dvc->is_in_int = true;
51219358
MW		 7081 ctrl_reg = AscGetChipControl(iop_base);
7082 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7083 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7084 chipstat = AscGetChipStatus(iop_base);
7085 if (chipstat & CSW_SCSI_RESET_LATCH) {
7086 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7087 int i = 10;
ae26759e 7088 int_pending = ASC_TRUE;
51219358
MW		 7089 asc_dvc->sdtr_done = 0;
7090 saved_ctrl_reg &= (uchar)(~CC_HALT);
7091 while ((AscGetChipStatus(iop_base) &
7092 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7093 mdelay(100);
7094 }
7095 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7096 AscSetChipControl(iop_base, CC_HALT);
7097 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7098 AscSetChipStatus(iop_base, 0);
7099 chipstat = AscGetChipStatus(iop_base);
7100 }
7101 }
7102 saved_ram_addr = AscGetChipLramAddr(iop_base);
7103 host_flag = AscReadLramByte(iop_base,
7104 ASCV_HOST_FLAG_B) &
7105 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7106 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7107 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7108 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7109 AscAckInterrupt(iop_base);
ae26759e 7110 int_pending = ASC_TRUE;
51219358 7111 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
6f0d2e1d
HR		 7112 AscIsrChipHalted(asc_dvc);
7113 saved_ctrl_reg &= (uchar)(~CC_HALT);
51219358 7114 } else {
51219358
MW		 7115 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7116 while (((status =
7117 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7118 }
7119 } else {
7120 do {
7121 if ((status =
7122 AscIsrQDone(asc_dvc)) == 1) {
7123 break;
7124 }
7125 } while (status == 0x11);
7126 }
7127 if ((status & 0x80) != 0)
ae26759e 7128 int_pending = ASC_ERROR;
51219358
MW		 7129 }
7130 }
7131 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7132 AscSetChipLramAddr(iop_base, saved_ram_addr);
7133 AscSetChipControl(iop_base, saved_ctrl_reg);
ae26759e 7134 asc_dvc->is_in_int = false;
51219358
MW		 7135 return int_pending;
7136}
1da177e4
LT		 7137
7138/*
51219358 7139 * advansys_reset()
1da177e4 7140 *
eac0b0c7 7141 * Reset the host associated with the command 'scp'.
1da177e4 7142 *
51219358
MW		 7143 * This function runs its own thread. Interrupts must be blocked but
7144 * sleeping is allowed and no locking other than for host structures is
7145 * required. Returns SUCCESS or FAILED.
1da177e4 7146 */
51219358 7147static int advansys_reset(struct scsi_cmnd *scp)
1da177e4 7148{
52fa0777 7149 struct Scsi_Host *shost = scp->device->host;
d2411495 7150 struct asc_board *boardp = shost_priv(shost);
52fa0777 7151 unsigned long flags;
27c868c2 7152 int status;
51219358 7153 int ret = SUCCESS;
27c868c2 7154
b352f923 7155 ASC_DBG(1, "0x%p\n", scp);
27c868c2 7156
52fa0777 7157 ASC_STATS(shost, reset);
27c868c2 7158
eac0b0c7 7159 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
51219358
MW		 7160
7161 if (ASC_NARROW_BOARD(boardp)) {
52fa0777 7162 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
1da177e4 7163
52fa0777 7164 /* Reset the chip and SCSI bus. */
b352f923 7165 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
52fa0777 7166 status = AscInitAsc1000Driver(asc_dvc);
27c868c2 7167
6070d81e 7168 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
9a908c1a 7169 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
eac0b0c7 7170 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
9a908c1a
HRK		 7171 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7172 status);
51219358
MW		 7173 ret = FAILED;
7174 } else if (status) {
eac0b0c7 7175 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
52fa0777 7176 "0x%x\n", status);
27c868c2 7177 } else {
eac0b0c7 7178 scmd_printk(KERN_INFO, scp, "SCSI host reset "
52fa0777 7179 "successful\n");
27c868c2 7180 }
a9f4a59a 7181
b352f923 7182 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
a9f4a59a 7183 } else {
a9f4a59a 7184 /*
51219358
MW		 7185 * If the suggest reset bus flags are set, then reset the bus.
7186 * Otherwise only reset the device.
a9f4a59a 7187 */
52fa0777 7188 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
a9f4a59a
MW		 7189
7190 /*
eac0b0c7 7191 * Reset the chip and SCSI bus.
a9f4a59a 7192 */
b352f923 7193 ASC_DBG(1, "before AdvResetChipAndSB()\n");
52fa0777 7194 switch (AdvResetChipAndSB(adv_dvc)) {
51219358 7195 case ASC_TRUE:
eac0b0c7 7196 scmd_printk(KERN_INFO, scp, "SCSI host reset "
52fa0777 7197 "successful\n");
51219358
MW		 7198 break;
7199 case ASC_FALSE:
7200 default:
eac0b0c7 7201 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
51219358
MW		 7202 ret = FAILED;
7203 break;
b9d96614 7204 }
f092d229 7205 spin_lock_irqsave(shost->host_lock, flags);
52fa0777 7206 AdvISR(adv_dvc);
eac0b0c7 7207 spin_unlock_irqrestore(shost->host_lock, flags);
b9d96614
MW		 7208 }
7209
b352f923 7210 ASC_DBG(1, "ret %d\n", ret);
b9d96614 7211
51219358 7212 return ret;
b9d96614
MW		 7213}
7214
1da177e4 7215/*
51219358 7216 * advansys_biosparam()
1da177e4 7217 *
51219358
MW		 7218 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7219 * support is enabled for a drive.
1da177e4 7220 *
51219358
MW		 7221 * ip (information pointer) is an int array with the following definition:
7222 * ip[0]: heads
7223 * ip[1]: sectors
7224 * ip[2]: cylinders
1da177e4 7225 */
51219358
MW		 7226static int
7227advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7228 sector_t capacity, int ip[])
1da177e4 7229{
d2411495 7230 struct asc_board *boardp = shost_priv(sdev->host);
1da177e4 7231
b352f923 7232 ASC_DBG(1, "begin\n");
51219358 7233 ASC_STATS(sdev->host, biosparam);
51219358
MW		 7234 if (ASC_NARROW_BOARD(boardp)) {
7235 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7236 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7237 ip[0] = 255;
7238 ip[1] = 63;
7239 } else {
7240 ip[0] = 64;
7241 ip[1] = 32;
7242 }
7243 } else {
7244 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7245 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7246 ip[0] = 255;
7247 ip[1] = 63;
7248 } else {
7249 ip[0] = 64;
7250 ip[1] = 32;
7251 }
27c868c2 7252 }
51219358 7253 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
b352f923 7254 ASC_DBG(1, "end\n");
51219358
MW		 7255 return 0;
7256}
1da177e4 7257
51219358
MW		 7258/*
7259 * First-level interrupt handler.
7260 *
7261 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7262 */
7263static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7264{
51219358 7265 struct Scsi_Host *shost = dev_id;
d2411495 7266 struct asc_board *boardp = shost_priv(shost);
51219358 7267 irqreturn_t result = IRQ_NONE;
27c868c2 7268
b352f923 7269 ASC_DBG(2, "boardp 0x%p\n", boardp);
f092d229 7270 spin_lock(shost->host_lock);
51219358
MW		 7271 if (ASC_NARROW_BOARD(boardp)) {
7272 if (AscIsIntPending(shost->io_port)) {
7273 result = IRQ_HANDLED;
7274 ASC_STATS(shost, interrupt);
b352f923 7275 ASC_DBG(1, "before AscISR()\n");
51219358
MW		 7276 AscISR(&boardp->dvc_var.asc_dvc_var);
7277 }
7278 } else {
b352f923 7279 ASC_DBG(1, "before AdvISR()\n");
51219358
MW		 7280 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7281 result = IRQ_HANDLED;
7282 ASC_STATS(shost, interrupt);
7283 }
27c868c2 7284 }
f092d229 7285 spin_unlock(shost->host_lock);
1da177e4 7286
b352f923 7287 ASC_DBG(1, "end\n");
51219358
MW		 7288 return result;
7289}
27c868c2 7290
d647c783 7291static bool AscHostReqRiscHalt(PortAddr iop_base)
51219358
MW		 7292{
7293 int count = 0;
d647c783 7294 bool sta = false;
51219358
MW		 7295 uchar saved_stop_code;
7296
7297 if (AscIsChipHalted(iop_base))
d647c783 7298 return true;
51219358
MW		 7299 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7300 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7301 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7302 do {
7303 if (AscIsChipHalted(iop_base)) {
d647c783 7304 sta = true;
51219358 7305 break;
27c868c2 7306 }
51219358
MW		 7307 mdelay(100);
7308 } while (count++ < 20);
7309 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
d647c783 7310 return sta;
51219358 7311}
1da177e4 7312
d647c783 7313static bool
51219358
MW		 7314AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7315{
d647c783 7316 bool sta = false;
1da177e4 7317
51219358
MW		 7318 if (AscHostReqRiscHalt(iop_base)) {
7319 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7320 AscStartChip(iop_base);
27c868c2 7321 }
51219358
MW		 7322 return sta;
7323}
1da177e4 7324
51219358
MW		 7325static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7326{
7327 char type = sdev->type;
7328 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
27c868c2 7329
51219358
MW		 7330 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7331 return;
7332 if (asc_dvc->init_sdtr & tid_bits)
7333 return;
27c868c2 7334
51219358
MW		 7335 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7336 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
27c868c2 7337
51219358
MW		 7338 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7339 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7340 (type == TYPE_ROM) || (type == TYPE_TAPE))
7341 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7342
7343 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7344 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7345 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7346}
1da177e4 7347
51219358
MW		 7348static void
7349advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7350{
7351 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7352 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
27c868c2 7353
51219358
MW		 7354 if (sdev->lun == 0) {
7355 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7356 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7357 asc_dvc->init_sdtr |= tid_bit;
7358 } else {
7359 asc_dvc->init_sdtr &= ~tid_bit;
7360 }
7361
7362 if (orig_init_sdtr != asc_dvc->init_sdtr)
7363 AscAsyncFix(asc_dvc, sdev);
27c868c2 7364 }
1da177e4 7365
51219358
MW		 7366 if (sdev->tagged_supported) {
7367 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7368 if (sdev->lun == 0) {
7369 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7370 asc_dvc->use_tagged_qng |= tid_bit;
7371 }
db5ed4df 7372 scsi_change_queue_depth(sdev,
51219358 7373 asc_dvc->max_dvc_qng[sdev->id]);
27c868c2 7374 }
51219358
MW		 7375 } else {
7376 if (sdev->lun == 0) {
7377 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7378 asc_dvc->use_tagged_qng &= ~tid_bit;
27c868c2
MW		 7379 }
7380 }
1da177e4 7381
51219358
MW		 7382 if ((sdev->lun == 0) &&
7383 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7384 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7385 asc_dvc->cfg->disc_enable);
7386 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7387 asc_dvc->use_tagged_qng);
7388 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7389 asc_dvc->cfg->can_tagged_qng);
27c868c2 7390
51219358
MW		 7391 asc_dvc->max_dvc_qng[sdev->id] =
7392 asc_dvc->cfg->max_tag_qng[sdev->id];
7393 AscWriteLramByte(asc_dvc->iop_base,
7394 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7395 asc_dvc->max_dvc_qng[sdev->id]);
7396 }
7397}
27c868c2 7398
51219358
MW		 7399/*
7400 * Wide Transfers
7401 *
7402 * If the EEPROM enabled WDTR for the device and the device supports wide
7403 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7404 * write the new value to the microcode.
7405 */
7406static void
7407advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7408{
7409 unsigned short cfg_word;
7410 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7411 if ((cfg_word & tidmask) != 0)
7412 return;
27c868c2 7413
51219358
MW		 7414 cfg_word |= tidmask;
7415 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
27c868c2
MW		 7416
7417 /*
51219358
MW		 7418 * Clear the microcode SDTR and WDTR negotiation done indicators for
7419 * the target to cause it to negotiate with the new setting set above.
7420 * WDTR when accepted causes the target to enter asynchronous mode, so
7421 * SDTR must be negotiated.
27c868c2 7422 */
51219358
MW		 7423 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7424 cfg_word &= ~tidmask;
7425 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7426 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7427 cfg_word &= ~tidmask;
7428 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7429}
1da177e4 7430
51219358
MW		 7431/*
7432 * Synchronous Transfers
7433 *
7434 * If the EEPROM enabled SDTR for the device and the device
7435 * supports synchronous transfers, then turn on the device's
7436 * 'sdtr_able' bit. Write the new value to the microcode.
7437 */
7438static void
7439advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7440{
7441 unsigned short cfg_word;
7442 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7443 if ((cfg_word & tidmask) != 0)
7444 return;
1da177e4 7445
51219358
MW		 7446 cfg_word |= tidmask;
7447 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
1da177e4 7448
27c868c2 7449 /*
51219358
MW		 7450 * Clear the microcode "SDTR negotiation" done indicator for the
7451 * target to cause it to negotiate with the new setting set above.
27c868c2 7452 */
51219358
MW		 7453 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7454 cfg_word &= ~tidmask;
7455 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7456}
27c868c2 7457
51219358
MW		 7458/*
7459 * PPR (Parallel Protocol Request) Capable
7460 *
7461 * If the device supports DT mode, then it must be PPR capable.
7462 * The PPR message will be used in place of the SDTR and WDTR
7463 * messages to negotiate synchronous speed and offset, transfer
7464 * width, and protocol options.
7465 */
7466static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7467 AdvPortAddr iop_base, unsigned short tidmask)
7468{
7469 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7470 adv_dvc->ppr_able |= tidmask;
7471 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7472}
27c868c2 7473
51219358
MW		 7474static void
7475advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7476{
7477 AdvPortAddr iop_base = adv_dvc->iop_base;
7478 unsigned short tidmask = 1 << sdev->id;
7479
7480 if (sdev->lun == 0) {
7481 /*
7482 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7483 * is enabled in the EEPROM and the device supports the
7484 * feature, then enable it in the microcode.
7485 */
27c868c2 7486
51219358
MW		 7487 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7488 advansys_wide_enable_wdtr(iop_base, tidmask);
7489 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7490 advansys_wide_enable_sdtr(iop_base, tidmask);
7491 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7492 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7493
7494 /*
7495 * Tag Queuing is disabled for the BIOS which runs in polled
7496 * mode and would see no benefit from Tag Queuing. Also by
7497 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7498 * bugs will at least work with the BIOS.
7499 */
7500 if ((adv_dvc->tagqng_able & tidmask) &&
7501 sdev->tagged_supported) {
7502 unsigned short cfg_word;
7503 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7504 cfg_word |= tidmask;
7505 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7506 cfg_word);
7507 AdvWriteByteLram(iop_base,
7508 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7509 adv_dvc->max_dvc_qng);
27c868c2
MW		 7510 }
7511 }
1da177e4 7512
db5ed4df
CH		 7513 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7514 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
51219358 7515}
27c868c2 7516
51219358
MW		 7517/*
7518 * Set the number of commands to queue per device for the
7519 * specified host adapter.
7520 */
7521static int advansys_slave_configure(struct scsi_device *sdev)
7522{
d2411495 7523 struct asc_board *boardp = shost_priv(sdev->host);
27c868c2 7524
51219358
MW		 7525 if (ASC_NARROW_BOARD(boardp))
7526 advansys_narrow_slave_configure(sdev,
7527 &boardp->dvc_var.asc_dvc_var);
7528 else
7529 advansys_wide_slave_configure(sdev,
7530 &boardp->dvc_var.adv_dvc_var);
1da177e4 7531
51219358
MW		 7532 return 0;
7533}
27c868c2 7534
b249c7fd
MW		 7535static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7536{
7537 struct asc_board *board = shost_priv(scp->device->host);
7538 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
b80ca4f7 7539 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
b249c7fd 7540 dma_cache_sync(board->dev, scp->sense_buffer,
b80ca4f7 7541 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
b249c7fd
MW		 7542 return cpu_to_le32(scp->SCp.dma_handle);
7543}
7544
d2411495 7545static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
05848b6e 7546 struct asc_scsi_q *asc_scsi_q)
51219358 7547{
b249c7fd 7548 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
52c334e9 7549 int use_sg;
9c17c62a 7550 u32 srb_tag;
52c334e9 7551
05848b6e 7552 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
27c868c2
MW		 7553
7554 /*
9c17c62a
HR		 7555 * Set the srb_tag to the command tag + 1, as
7556 * srb_tag '0' is used internally by the chip.
27c868c2 7557 */
9c17c62a
HR		 7558 srb_tag = scp->request->tag + 1;
7559 asc_scsi_q->q2.srb_tag = srb_tag;
27c868c2
MW		 7560
7561 /*
51219358 7562 * Build the ASC_SCSI_Q request.
27c868c2 7563 */
05848b6e
MW		 7564 asc_scsi_q->cdbptr = &scp->cmnd[0];
7565 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7566 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7567 asc_scsi_q->q1.target_lun = scp->device->lun;
7568 asc_scsi_q->q2.target_ix =
51219358 7569 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
b249c7fd 7570 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
b80ca4f7 7571 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
27c868c2
MW		 7572
7573 /*
51219358
MW		 7574 * If there are any outstanding requests for the current target,
7575 * then every 255th request send an ORDERED request. This heuristic
7576 * tries to retain the benefit of request sorting while preventing
7577 * request starvation. 255 is the max number of tags or pending commands
7578 * a device may have outstanding.
7579 *
7580 * The request count is incremented below for every successfully
7581 * started request.
27c868c2 7582 *
27c868c2 7583 */
b249c7fd 7584 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
51219358 7585 (boardp->reqcnt[scp->device->id] % 255) == 0) {
68d81f40 7586 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
51219358 7587 } else {
68d81f40 7588 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
51219358 7589 }
27c868c2 7590
52c334e9
MW		 7591 /* Build ASC_SCSI_Q */
7592 use_sg = scsi_dma_map(scp);
7593 if (use_sg != 0) {
51219358 7594 int sgcnt;
51219358 7595 struct scatterlist *slp;
05848b6e 7596 struct asc_sg_head *asc_sg_head;
27c868c2 7597
51219358 7598 if (use_sg > scp->device->host->sg_tablesize) {
9d0e96eb
MW		 7599 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7600 "sg_tablesize %d\n", use_sg,
7601 scp->device->host->sg_tablesize);
52c334e9 7602 scsi_dma_unmap(scp);
51219358
MW		 7603 scp->result = HOST_BYTE(DID_ERROR);
7604 return ASC_ERROR;
7605 }
27c868c2 7606
05848b6e
MW		 7607 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7608 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7609 if (!asc_sg_head) {
52c334e9 7610 scsi_dma_unmap(scp);
05848b6e
MW		 7611 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7612 return ASC_ERROR;
7613 }
51219358 7614
05848b6e
MW		 7615 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7616 asc_scsi_q->sg_head = asc_sg_head;
7617 asc_scsi_q->q1.data_cnt = 0;
7618 asc_scsi_q->q1.data_addr = 0;
51219358 7619 /* This is a byte value, otherwise it would need to be swapped. */
05848b6e 7620 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
52c334e9 7621 ASC_STATS_ADD(scp->device->host, xfer_elem,
05848b6e 7622 asc_sg_head->entry_cnt);
51219358
MW		 7623
7624 /*
7625 * Convert scatter-gather list into ASC_SG_HEAD list.
7626 */
52c334e9 7627 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
05848b6e 7628 asc_sg_head->sg_list[sgcnt].addr =
51219358 7629 cpu_to_le32(sg_dma_address(slp));
05848b6e 7630 asc_sg_head->sg_list[sgcnt].bytes =
51219358 7631 cpu_to_le32(sg_dma_len(slp));
52c334e9
MW		 7632 ASC_STATS_ADD(scp->device->host, xfer_sect,
7633 DIV_ROUND_UP(sg_dma_len(slp), 512));
27c868c2
MW		 7634 }
7635 }
1da177e4 7636
52c334e9
MW		 7637 ASC_STATS(scp->device->host, xfer_cnt);
7638
b352f923 7639 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
51219358
MW		 7640 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7641
7642 return ASC_NOERROR;
27c868c2 7643}
1da177e4 7644
27c868c2 7645/*
51219358 7646 * Build scatter-gather list for Adv Library (Wide Board).
27c868c2 7647 *
51219358
MW		 7648 * Additional ADV_SG_BLOCK structures will need to be allocated
7649 * if the total number of scatter-gather elements exceeds
7650 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7651 * assumed to be physically contiguous.
27c868c2 7652 *
51219358
MW		 7653 * Return:
7654 * ADV_SUCCESS(1) - SG List successfully created
7655 * ADV_ERROR(-1) - SG List creation failed
27c868c2 7656 */
51219358 7657static int
4b47e464
HR		 7658adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
7659 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
27c868c2 7660{
0ce53822 7661 adv_sgblk_t *sgblkp, *prev_sgblkp;
51219358
MW		 7662 struct scatterlist *slp;
7663 int sg_elem_cnt;
7664 ADV_SG_BLOCK *sg_block, *prev_sg_block;
0ce53822 7665 dma_addr_t sgblk_paddr;
27c868c2 7666 int i;
27c868c2 7667
52c334e9 7668 slp = scsi_sglist(scp);
51219358 7669 sg_elem_cnt = use_sg;
0ce53822 7670 prev_sgblkp = NULL;
51219358
MW		 7671 prev_sg_block = NULL;
7672 reqp->sgblkp = NULL;
1da177e4 7673
51219358
MW		 7674 for (;;) {
7675 /*
7676 * Allocate a 'adv_sgblk_t' structure from the board free
7677 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7678 * (15) scatter-gather elements.
7679 */
0ce53822
HR		 7680 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC,
7681 &sgblk_paddr);
7682 if (!sgblkp) {
b352f923 7683 ASC_DBG(1, "no free adv_sgblk_t\n");
51219358 7684 ASC_STATS(scp->device->host, adv_build_nosg);
1da177e4 7685
51219358
MW		 7686 /*
7687 * Allocation failed. Free 'adv_sgblk_t' structures
7688 * already allocated for the request.
7689 */
7690 while ((sgblkp = reqp->sgblkp) != NULL) {
7691 /* Remove 'sgblkp' from the request list. */
7692 reqp->sgblkp = sgblkp->next_sgblkp;
0ce53822
HR		 7693 sgblkp->next_sgblkp = NULL;
7694 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
7695 sgblkp->sg_addr);
51219358
MW		 7696 }
7697 return ASC_BUSY;
7698 }
51219358 7699 /* Complete 'adv_sgblk_t' board allocation. */
0ce53822 7700 sgblkp->sg_addr = sgblk_paddr;
51219358 7701 sgblkp->next_sgblkp = NULL;
0ce53822 7702 sg_block = &sgblkp->sg_block;
27c868c2 7703
51219358
MW		 7704 /*
7705 * Check if this is the first 'adv_sgblk_t' for the
7706 * request.
7707 */
7708 if (reqp->sgblkp == NULL) {
7709 /* Request's first scatter-gather block. */
7710 reqp->sgblkp = sgblkp;
27c868c2 7711
51219358
MW		 7712 /*
7713 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7714 * address pointers.
7715 */
7716 scsiqp->sg_list_ptr = sg_block;
0ce53822 7717 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr);
51219358
MW		 7718 } else {
7719 /* Request's second or later scatter-gather block. */
0ce53822 7720 prev_sgblkp->next_sgblkp = sgblkp;
51219358
MW		 7721
7722 /*
7723 * Point the previous ADV_SG_BLOCK structure to
7724 * the newly allocated ADV_SG_BLOCK structure.
7725 */
0ce53822 7726 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr);
27c868c2 7727 }
1da177e4 7728
51219358
MW		 7729 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7730 sg_block->sg_list[i].sg_addr =
7731 cpu_to_le32(sg_dma_address(slp));
7732 sg_block->sg_list[i].sg_count =
7733 cpu_to_le32(sg_dma_len(slp));
52c334e9
MW		 7734 ASC_STATS_ADD(scp->device->host, xfer_sect,
7735 DIV_ROUND_UP(sg_dma_len(slp), 512));
27c868c2 7736
0ce53822
HR		 7737 if (--sg_elem_cnt == 0) {
7738 /*
7739 * Last ADV_SG_BLOCK and scatter-gather entry.
7740 */
51219358 7741 sg_block->sg_cnt = i + 1;
0ce53822 7742 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
51219358
MW		 7743 return ADV_SUCCESS;
7744 }
7745 slp++;
7746 }
7747 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
7748 prev_sg_block = sg_block;
0ce53822 7749 prev_sgblkp = sgblkp;
27c868c2 7750 }
51219358 7751}
1da177e4 7752
51219358
MW		 7753/*
7754 * Build a request structure for the Adv Library (Wide Board).
7755 *
7756 * If an adv_req_t can not be allocated to issue the request,
7757 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
7758 *
9fef6ba4 7759 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the
51219358
MW		 7760 * microcode for DMA addresses or math operations are byte swapped
7761 * to little-endian order.
7762 */
7763static int
d2411495 7764adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
4b47e464 7765 adv_req_t **adv_reqpp)
51219358 7766{
9c17c62a 7767 u32 srb_tag = scp->request->tag;
51219358
MW		 7768 adv_req_t *reqp;
7769 ADV_SCSI_REQ_Q *scsiqp;
51219358 7770 int ret;
52c334e9 7771 int use_sg;
811ddc05 7772 dma_addr_t sense_addr;
1da177e4 7773
27c868c2 7774 /*
51219358
MW		 7775 * Allocate an adv_req_t structure from the board to execute
7776 * the command.
27c868c2 7777 */
9c17c62a
HR		 7778 reqp = &boardp->adv_reqp[srb_tag];
7779 if (reqp->cmndp && reqp->cmndp != scp ) {
b352f923 7780 ASC_DBG(1, "no free adv_req_t\n");
51219358
MW		 7781 ASC_STATS(scp->device->host, adv_build_noreq);
7782 return ASC_BUSY;
27c868c2 7783 }
1da177e4 7784
4b47e464
HR		 7785 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
7786
7787 scsiqp = &reqp->scsi_req_q;
27c868c2
MW		 7788
7789 /*
51219358 7790 * Initialize the structure.
27c868c2 7791 */
51219358 7792 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
27c868c2
MW		 7793
7794 /*
9c17c62a 7795 * Set the srb_tag to the command tag.
27c868c2 7796 */
9c17c62a 7797 scsiqp->srb_tag = srb_tag;
27c868c2
MW		 7798
7799 /*
4b47e464 7800 * Set 'host_scribble' to point to the adv_req_t structure.
27c868c2 7801 */
51219358 7802 reqp->cmndp = scp;
9c17c62a 7803 scp->host_scribble = (void *)reqp;
27c868c2
MW		 7804
7805 /*
51219358 7806 * Build the ADV_SCSI_REQ_Q request.
27c868c2 7807 */
51219358
MW		 7808
7809 /* Set CDB length and copy it to the request structure. */
7810 scsiqp->cdb_len = scp->cmd_len;
7811 /* Copy first 12 CDB bytes to cdb[]. */
811ddc05 7812 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
51219358 7813 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
811ddc05
HR		 7814 if (scp->cmd_len > 12) {
7815 int cdb16_len = scp->cmd_len - 12;
7816
7817 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
27c868c2 7818 }
1da177e4 7819
51219358
MW		 7820 scsiqp->target_id = scp->device->id;
7821 scsiqp->target_lun = scp->device->lun;
7822
811ddc05
HR		 7823 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
7824 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7825 scsiqp->sense_addr = cpu_to_le32(sense_addr);
7826 scsiqp->sense_len = cpu_to_le32(SCSI_SENSE_BUFFERSIZE);
27c868c2 7827
52c334e9 7828 /* Build ADV_SCSI_REQ_Q */
51219358 7829
52c334e9
MW		 7830 use_sg = scsi_dma_map(scp);
7831 if (use_sg == 0) {
7832 /* Zero-length transfer */
51219358 7833 reqp->sgblkp = NULL;
52c334e9 7834 scsiqp->data_cnt = 0;
52c334e9
MW		 7835
7836 scsiqp->data_addr = 0;
51219358
MW		 7837 scsiqp->sg_list_ptr = NULL;
7838 scsiqp->sg_real_addr = 0;
51219358 7839 } else {
51219358 7840 if (use_sg > ADV_MAX_SG_LIST) {
9d0e96eb
MW		 7841 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7842 "ADV_MAX_SG_LIST %d\n", use_sg,
51219358 7843 scp->device->host->sg_tablesize);
52c334e9 7844 scsi_dma_unmap(scp);
51219358 7845 scp->result = HOST_BYTE(DID_ERROR);
9c17c62a
HR		 7846 reqp->cmndp = NULL;
7847 scp->host_scribble = NULL;
51219358
MW		 7848
7849 return ASC_ERROR;
7850 }
7851
52c334e9
MW		 7852 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
7853
4b47e464 7854 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
51219358 7855 if (ret != ADV_SUCCESS) {
9c17c62a
HR		 7856 scsi_dma_unmap(scp);
7857 scp->result = HOST_BYTE(DID_ERROR);
7858 reqp->cmndp = NULL;
7859 scp->host_scribble = NULL;
51219358
MW		 7860
7861 return ret;
7862 }
7863
52c334e9 7864 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
27c868c2 7865 }
1da177e4 7866
52c334e9
MW		 7867 ASC_STATS(scp->device->host, xfer_cnt);
7868
51219358
MW		 7869 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
7870 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
27c868c2 7871
4b47e464 7872 *adv_reqpp = reqp;
27c868c2 7873
51219358
MW		 7874 return ASC_NOERROR;
7875}
7876
7877static int AscSgListToQueue(int sg_list)
7878{
7879 int n_sg_list_qs;
7880
7881 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
7882 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
7883 n_sg_list_qs++;
7884 return n_sg_list_qs + 1;
7885}
7886
7887static uint
7888AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
7889{
7890 uint cur_used_qs;
7891 uint cur_free_qs;
7892 ASC_SCSI_BIT_ID_TYPE target_id;
7893 uchar tid_no;
7894
7895 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
7896 tid_no = ASC_TIX_TO_TID(target_ix);
7897 if ((asc_dvc->unit_not_ready & target_id) ||
7898 (asc_dvc->queue_full_or_busy & target_id)) {
7899 return 0;
7900 }
7901 if (n_qs == 1) {
7902 cur_used_qs = (uint) asc_dvc->cur_total_qng +
7903 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
7904 } else {
7905 cur_used_qs = (uint) asc_dvc->cur_total_qng +
7906 (uint) ASC_MIN_FREE_Q;
7907 }
7908 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
7909 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
7910 if (asc_dvc->cur_dvc_qng[tid_no] >=
7911 asc_dvc->max_dvc_qng[tid_no]) {
7912 return 0;
7913 }
7914 return cur_free_qs;
7915 }
7916 if (n_qs > 1) {
7917 if ((n_qs > asc_dvc->last_q_shortage)
7918 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
7919 asc_dvc->last_q_shortage = n_qs;
7920 }
7921 }
7922 return 0;
7923}
7924
7925static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
7926{
7927 ushort q_addr;
7928 uchar next_qp;
7929 uchar q_status;
7930
7931 q_addr = ASC_QNO_TO_QADDR(free_q_head);
7932 q_status = (uchar)AscReadLramByte(iop_base,
7933 (ushort)(q_addr +
7934 ASC_SCSIQ_B_STATUS));
7935 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
7936 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
7937 return next_qp;
7938 return ASC_QLINK_END;
7939}
7940
7941static uchar
7942AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
7943{
7944 uchar i;
27c868c2 7945
51219358
MW		 7946 for (i = 0; i < n_free_q; i++) {
7947 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
7948 if (free_q_head == ASC_QLINK_END)
7949 break;
7950 }
7951 return free_q_head;
7952}
27c868c2 7953
51219358
MW		 7954/*
7955 * void
7956 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
7957 *
7958 * Calling/Exit State:
7959 * none
7960 *
7961 * Description:
7962 * Output an ASC_SCSI_Q structure to the chip
7963 */
7964static void
7965DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
7966{
7967 int i;
7968
7969 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
7970 AscSetChipLramAddr(iop_base, s_addr);
7971 for (i = 0; i < 2 * words; i += 2) {
7972 if (i == 4 || i == 20) {
7973 continue;
7974 }
7975 outpw(iop_base + IOP_RAM_DATA,
7976 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
27c868c2 7977 }
51219358 7978}
1da177e4 7979
51219358
MW		 7980static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
7981{
7982 ushort q_addr;
7983 uchar tid_no;
7984 uchar sdtr_data;
7985 uchar syn_period_ix;
7986 uchar syn_offset;
7987 PortAddr iop_base;
7988
7989 iop_base = asc_dvc->iop_base;
7990 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
7991 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
7992 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
7993 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
7994 syn_period_ix =
7995 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
7996 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
7997 AscMsgOutSDTR(asc_dvc,
7998 asc_dvc->sdtr_period_tbl[syn_period_ix],
7999 syn_offset);
8000 scsiq->q1.cntl |= QC_MSG_OUT;
8001 }
8002 q_addr = ASC_QNO_TO_QADDR(q_no);
8003 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
68d81f40 8004 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
27c868c2 8005 }
51219358
MW		 8006 scsiq->q1.status = QS_FREE;
8007 AscMemWordCopyPtrToLram(iop_base,
8008 q_addr + ASC_SCSIQ_CDB_BEG,
8009 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8010
8011 DvcPutScsiQ(iop_base,
8012 q_addr + ASC_SCSIQ_CPY_BEG,
8013 (uchar *)&scsiq->q1.cntl,
8014 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8015 AscWriteLramWord(iop_base,
8016 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8017 (ushort)(((ushort)scsiq->q1.
8018 q_no << 8) | (ushort)QS_READY));
8019 return 1;
8020}
8021
8022static int
8023AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8024{
8025 int sta;
8026 int i;
8027 ASC_SG_HEAD *sg_head;
8028 ASC_SG_LIST_Q scsi_sg_q;
95cfab6c
HR		 8029 __le32 saved_data_addr;
8030 __le32 saved_data_cnt;
51219358
MW		 8031 PortAddr iop_base;
8032 ushort sg_list_dwords;
8033 ushort sg_index;
8034 ushort sg_entry_cnt;
8035 ushort q_addr;
8036 uchar next_qp;
1da177e4 8037
51219358
MW		 8038 iop_base = asc_dvc->iop_base;
8039 sg_head = scsiq->sg_head;
8040 saved_data_addr = scsiq->q1.data_addr;
8041 saved_data_cnt = scsiq->q1.data_cnt;
37f64608
HR		 8042 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
8043 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
27c868c2 8044 /*
96aabb2a
HR		 8045 * Set sg_entry_cnt to be the number of SG elements that
8046 * will fit in the allocated SG queues. It is minus 1, because
8047 * the first SG element is handled above.
27c868c2 8048 */
96aabb2a 8049 sg_entry_cnt = sg_head->entry_cnt - 1;
27c868c2 8050
51219358
MW		 8051 if (sg_entry_cnt != 0) {
8052 scsiq->q1.cntl |= QC_SG_HEAD;
8053 q_addr = ASC_QNO_TO_QADDR(q_no);
8054 sg_index = 1;
8055 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8056 scsi_sg_q.sg_head_qp = q_no;
8057 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8058 for (i = 0; i < sg_head->queue_cnt; i++) {
8059 scsi_sg_q.seq_no = i + 1;
8060 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8061 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8062 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8063 if (i == 0) {
8064 scsi_sg_q.sg_list_cnt =
8065 ASC_SG_LIST_PER_Q;
8066 scsi_sg_q.sg_cur_list_cnt =
8067 ASC_SG_LIST_PER_Q;
8068 } else {
8069 scsi_sg_q.sg_list_cnt =
8070 ASC_SG_LIST_PER_Q - 1;
8071 scsi_sg_q.sg_cur_list_cnt =
8072 ASC_SG_LIST_PER_Q - 1;
8073 }
8074 } else {
96aabb2a 8075 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
51219358
MW		 8076 sg_list_dwords = sg_entry_cnt << 1;
8077 if (i == 0) {
8078 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8079 scsi_sg_q.sg_cur_list_cnt =
8080 sg_entry_cnt;
8081 } else {
8082 scsi_sg_q.sg_list_cnt =
8083 sg_entry_cnt - 1;
8084 scsi_sg_q.sg_cur_list_cnt =
8085 sg_entry_cnt - 1;
8086 }
8087 sg_entry_cnt = 0;
8088 }
8089 next_qp = AscReadLramByte(iop_base,
8090 (ushort)(q_addr +
8091 ASC_SCSIQ_B_FWD));
8092 scsi_sg_q.q_no = next_qp;
8093 q_addr = ASC_QNO_TO_QADDR(next_qp);
8094 AscMemWordCopyPtrToLram(iop_base,
8095 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8096 (uchar *)&scsi_sg_q,
8097 sizeof(ASC_SG_LIST_Q) >> 1);
8098 AscMemDWordCopyPtrToLram(iop_base,
8099 q_addr + ASC_SGQ_LIST_BEG,
8100 (uchar *)&sg_head->
8101 sg_list[sg_index],
8102 sg_list_dwords);
8103 sg_index += ASC_SG_LIST_PER_Q;
8104 scsiq->next_sg_index = sg_index;
27c868c2 8105 }
51219358
MW		 8106 } else {
8107 scsiq->q1.cntl &= ~QC_SG_HEAD;
27c868c2 8108 }
51219358
MW		 8109 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8110 scsiq->q1.data_addr = saved_data_addr;
8111 scsiq->q1.data_cnt = saved_data_cnt;
8112 return (sta);
8113}
27c868c2 8114
51219358
MW		 8115static int
8116AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8117{
8118 PortAddr iop_base;
8119 uchar free_q_head;
8120 uchar next_qp;
8121 uchar tid_no;
8122 uchar target_ix;
8123 int sta;
27c868c2 8124
51219358
MW		 8125 iop_base = asc_dvc->iop_base;
8126 target_ix = scsiq->q2.target_ix;
8127 tid_no = ASC_TIX_TO_TID(target_ix);
8128 sta = 0;
8129 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8130 if (n_q_required > 1) {
8131 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8132 (uchar)n_q_required);
8133 if (next_qp != ASC_QLINK_END) {
8134 asc_dvc->last_q_shortage = 0;
8135 scsiq->sg_head->queue_cnt = n_q_required - 1;
8136 scsiq->q1.q_no = free_q_head;
8137 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8138 free_q_head);
8139 }
8140 } else if (n_q_required == 1) {
8141 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8142 if (next_qp != ASC_QLINK_END) {
8143 scsiq->q1.q_no = free_q_head;
8144 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
27c868c2
MW		 8145 }
8146 }
51219358
MW		 8147 if (sta == 1) {
8148 AscPutVarFreeQHead(iop_base, next_qp);
8149 asc_dvc->cur_total_qng += n_q_required;
8150 asc_dvc->cur_dvc_qng[tid_no]++;
27c868c2 8151 }
51219358
MW		 8152 return sta;
8153}
27c868c2 8154
51219358
MW		 8155#define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8156static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8157 INQUIRY,
8158 REQUEST_SENSE,
8159 READ_CAPACITY,
8160 READ_TOC,
8161 MODE_SELECT,
8162 MODE_SENSE,
8163 MODE_SELECT_10,
8164 MODE_SENSE_10,
8165 0xFF,
8166 0xFF,
8167 0xFF,
8168 0xFF,
8169 0xFF,
8170 0xFF,
8171 0xFF,
8172 0xFF
8173};
27c868c2 8174
51219358
MW		 8175static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8176{
8177 PortAddr iop_base;
8178 int sta;
8179 int n_q_required;
ae26759e 8180 bool disable_syn_offset_one_fix;
51219358 8181 int i;
95cfab6c 8182 u32 addr;
51219358
MW		 8183 ushort sg_entry_cnt = 0;
8184 ushort sg_entry_cnt_minus_one = 0;
8185 uchar target_ix;
8186 uchar tid_no;
8187 uchar sdtr_data;
8188 uchar extra_bytes;
8189 uchar scsi_cmd;
8190 uchar disable_cmd;
8191 ASC_SG_HEAD *sg_head;
95cfab6c 8192 unsigned long data_cnt;
27c868c2 8193
51219358
MW		 8194 iop_base = asc_dvc->iop_base;
8195 sg_head = scsiq->sg_head;
8196 if (asc_dvc->err_code != 0)
f1138a84 8197 return ASC_ERROR;
51219358
MW		 8198 scsiq->q1.q_no = 0;
8199 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8200 scsiq->q1.extra_bytes = 0;
27c868c2 8201 }
51219358
MW		 8202 sta = 0;
8203 target_ix = scsiq->q2.target_ix;
8204 tid_no = ASC_TIX_TO_TID(target_ix);
8205 n_q_required = 1;
8206 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8207 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8208 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8209 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8210 AscMsgOutSDTR(asc_dvc,
8211 asc_dvc->
8212 sdtr_period_tbl[(sdtr_data >> 4) &
8213 (uchar)(asc_dvc->
8214 max_sdtr_index -
8215 1)],
8216 (uchar)(sdtr_data & (uchar)
8217 ASC_SYN_MAX_OFFSET));
8218 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8219 }
8220 }
8221 if (asc_dvc->in_critical_cnt != 0) {
8222 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
f1138a84 8223 return ASC_ERROR;
51219358
MW		 8224 }
8225 asc_dvc->in_critical_cnt++;
8226 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8227 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8228 asc_dvc->in_critical_cnt--;
f1138a84 8229 return ASC_ERROR;
51219358 8230 }
51219358
MW		 8231 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8232 asc_dvc->in_critical_cnt--;
f1138a84 8233 return ASC_ERROR;
51219358 8234 }
51219358 8235 if (sg_entry_cnt == 1) {
37f64608
HR		 8236 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
8237 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
51219358
MW		 8238 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8239 }
8240 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8241 }
8242 scsi_cmd = scsiq->cdbptr[0];
ae26759e 8243 disable_syn_offset_one_fix = false;
51219358
MW		 8244 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8245 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8246 if (scsiq->q1.cntl & QC_SG_HEAD) {
8247 data_cnt = 0;
8248 for (i = 0; i < sg_entry_cnt; i++) {
95cfab6c
HR		 8249 data_cnt += le32_to_cpu(sg_head->sg_list[i].
8250 bytes);
51219358
MW		 8251 }
8252 } else {
8253 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8254 }
8255 if (data_cnt != 0UL) {
8256 if (data_cnt < 512UL) {
ae26759e 8257 disable_syn_offset_one_fix = true;
51219358
MW		 8258 } else {
8259 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8260 i++) {
8261 disable_cmd =
8262 _syn_offset_one_disable_cmd[i];
8263 if (disable_cmd == 0xFF) {
8264 break;
8265 }
8266 if (scsi_cmd == disable_cmd) {
8267 disable_syn_offset_one_fix =
ae26759e 8268 true;
51219358
MW		 8269 break;
8270 }
8271 }
8272 }
8273 }
8274 }
8275 if (disable_syn_offset_one_fix) {
68d81f40 8276 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
51219358
MW		 8277 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8278 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8279 } else {
8280 scsiq->q2.tag_code &= 0x27;
8281 }
8282 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8283 if (asc_dvc->bug_fix_cntl) {
8284 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8285 if ((scsi_cmd == READ_6) ||
8286 (scsi_cmd == READ_10)) {
95cfab6c 8287 addr = le32_to_cpu(sg_head->
51219358
MW		 8288 sg_list
8289 [sg_entry_cnt_minus_one].
8290 addr) +
95cfab6c 8291 le32_to_cpu(sg_head->
51219358
MW		 8292 sg_list
8293 [sg_entry_cnt_minus_one].
8294 bytes);
8295 extra_bytes =
8296 (uchar)((ushort)addr & 0x0003);
8297 if ((extra_bytes != 0)
8298 &&
8299 ((scsiq->q2.
8300 tag_code &
8301 ASC_TAG_FLAG_EXTRA_BYTES)
8302 == 0)) {
8303 scsiq->q2.tag_code |=
8304 ASC_TAG_FLAG_EXTRA_BYTES;
8305 scsiq->q1.extra_bytes =
8306 extra_bytes;
8307 data_cnt =
8308 le32_to_cpu(sg_head->
8309 sg_list
8310 [sg_entry_cnt_minus_one].
8311 bytes);
95cfab6c 8312 data_cnt -= extra_bytes;
51219358
MW		 8313 sg_head->
8314 sg_list
8315 [sg_entry_cnt_minus_one].
8316 bytes =
8317 cpu_to_le32(data_cnt);
8318 }
8319 }
8320 }
8321 }
8322 sg_head->entry_to_copy = sg_head->entry_cnt;
51219358
MW		 8323 n_q_required = AscSgListToQueue(sg_entry_cnt);
8324 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8325 (uint) n_q_required)
8326 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8327 if ((sta =
8328 AscSendScsiQueue(asc_dvc, scsiq,
8329 n_q_required)) == 1) {
8330 asc_dvc->in_critical_cnt--;
8331 return (sta);
27c868c2 8332 }
51219358
MW		 8333 }
8334 } else {
8335 if (asc_dvc->bug_fix_cntl) {
8336 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8337 if ((scsi_cmd == READ_6) ||
8338 (scsi_cmd == READ_10)) {
8339 addr =
8340 le32_to_cpu(scsiq->q1.data_addr) +
8341 le32_to_cpu(scsiq->q1.data_cnt);
8342 extra_bytes =
8343 (uchar)((ushort)addr & 0x0003);
8344 if ((extra_bytes != 0)
8345 &&
8346 ((scsiq->q2.
8347 tag_code &
8348 ASC_TAG_FLAG_EXTRA_BYTES)
8349 == 0)) {
8350 data_cnt =
8351 le32_to_cpu(scsiq->q1.
8352 data_cnt);
8353 if (((ushort)data_cnt & 0x01FF)
8354 == 0) {
8355 scsiq->q2.tag_code |=
8356 ASC_TAG_FLAG_EXTRA_BYTES;
95cfab6c 8357 data_cnt -= extra_bytes;
51219358
MW		 8358 scsiq->q1.data_cnt =
8359 cpu_to_le32
8360 (data_cnt);
8361 scsiq->q1.extra_bytes =
8362 extra_bytes;
8363 }
8364 }
8365 }
8366 }
8367 }
8368 n_q_required = 1;
8369 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8370 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8371 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8372 n_q_required)) == 1) {
8373 asc_dvc->in_critical_cnt--;
8374 return (sta);
27c868c2
MW		 8375 }
8376 }
8377 }
51219358
MW		 8378 asc_dvc->in_critical_cnt--;
8379 return (sta);
1da177e4
LT		 8380}
8381
8382/*
51219358 8383 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
1da177e4 8384 *
51219358
MW		 8385 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8386 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8387 * RISC to notify it a new command is ready to be executed.
8388 *
8389 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8390 * set to SCSI_MAX_RETRY.
8391 *
9fef6ba4 8392 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode
51219358
MW		 8393 * for DMA addresses or math operations are byte swapped to little-endian
8394 * order.
8395 *
8396 * Return:
8397 * ADV_SUCCESS(1) - The request was successfully queued.
8398 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8399 * request completes.
8400 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8401 * host IC error.
8402 */
4b47e464 8403static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
51219358
MW		 8404{
8405 AdvPortAddr iop_base;
51219358 8406 ADV_CARR_T *new_carrp;
4b47e464 8407 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
1da177e4 8408
27c868c2 8409 /*
51219358 8410 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
27c868c2 8411 */
51219358
MW		 8412 if (scsiq->target_id > ADV_MAX_TID) {
8413 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8414 scsiq->done_status = QD_WITH_ERROR;
27c868c2
MW		 8415 return ADV_ERROR;
8416 }
1da177e4 8417
51219358 8418 iop_base = asc_dvc->iop_base;
1da177e4 8419
27c868c2 8420 /*
51219358
MW		 8421 * Allocate a carrier ensuring at least one carrier always
8422 * remains on the freelist and initialize fields.
27c868c2 8423 */
98b96a7d
HR		 8424 new_carrp = adv_get_next_carrier(asc_dvc);
8425 if (!new_carrp) {
8426 ASC_DBG(1, "No free carriers\n");
51219358 8427 return ADV_BUSY;
27c868c2 8428 }
1da177e4 8429
98b96a7d 8430 asc_dvc->carr_pending_cnt++;
27c868c2
MW		 8431
8432 /*
51219358 8433 * Clear the ADV_SCSI_REQ_Q done flag.
27c868c2 8434 */
51219358 8435 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
27c868c2 8436
51219358 8437 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
4b47e464
HR		 8438 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
8439 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
51219358 8440
98b96a7d 8441 scsiq->carr_va = asc_dvc->icq_sp->carr_va;
51219358 8442 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
1da177e4 8443
27c868c2 8444 /*
51219358
MW		 8445 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8446 * the microcode. The newly allocated stopper will become the new
8447 * stopper.
27c868c2 8448 */
4b47e464 8449 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
1da177e4 8450
27c868c2 8451 /*
51219358
MW		 8452 * Set the 'next_vpa' pointer for the old stopper to be the
8453 * physical address of the new stopper. The RISC can only
8454 * follow physical addresses.
27c868c2 8455 */
51219358 8456 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
27c868c2
MW		 8457
8458 /*
51219358 8459 * Set the host adapter stopper pointer to point to the new carrier.
27c868c2 8460 */
51219358
MW		 8461 asc_dvc->icq_sp = new_carrp;
8462
8463 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8464 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8465 /*
8466 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8467 */
8468 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8469 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8470 /*
8471 * Clear the tickle value. In the ASC-3550 the RISC flag
8472 * command 'clr_tickle_a' does not work unless the host
8473 * value is cleared.
8474 */
8475 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8476 ADV_TICKLE_NOP);
8477 }
8478 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8479 /*
8480 * Notify the RISC a carrier is ready by writing the physical
8481 * address of the new carrier stopper to the COMMA register.
8482 */
8483 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8484 le32_to_cpu(new_carrp->carr_pa));
27c868c2 8485 }
1da177e4 8486
51219358
MW		 8487 return ADV_SUCCESS;
8488}
8489
8490/*
8491 * Execute a single 'Scsi_Cmnd'.
51219358
MW		 8492 */
8493static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8494{
41d2493d 8495 int ret, err_code;
d2411495 8496 struct asc_board *boardp = shost_priv(scp->device->host);
51219358 8497
b352f923 8498 ASC_DBG(1, "scp 0x%p\n", scp);
27c868c2 8499
51219358 8500 if (ASC_NARROW_BOARD(boardp)) {
41d2493d 8501 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
05848b6e 8502 struct asc_scsi_q asc_scsi_q;
27c868c2 8503
41d2493d 8504 /* asc_build_req() can not return ASC_BUSY. */
05848b6e
MW		 8505 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8506 if (ret == ASC_ERROR) {
51219358
MW		 8507 ASC_STATS(scp->device->host, build_error);
8508 return ASC_ERROR;
8509 }
1da177e4 8510
41d2493d 8511 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
05848b6e 8512 kfree(asc_scsi_q.sg_head);
41d2493d 8513 err_code = asc_dvc->err_code;
51219358 8514 } else {
41d2493d 8515 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
4b47e464 8516 adv_req_t *adv_reqp;
27c868c2 8517
4b47e464 8518 switch (adv_build_req(boardp, scp, &adv_reqp)) {
51219358 8519 case ASC_NOERROR:
b352f923 8520 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
51219358
MW		 8521 break;
8522 case ASC_BUSY:
b352f923 8523 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
51219358
MW		 8524 /*
8525 * The asc_stats fields 'adv_build_noreq' and
8526 * 'adv_build_nosg' count wide board busy conditions.
8527 * They are updated in adv_build_req and
8528 * adv_get_sglist, respectively.
8529 */
8530 return ASC_BUSY;
8531 case ASC_ERROR:
8532 default:
b352f923 8533 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
51219358
MW		 8534 ASC_STATS(scp->device->host, build_error);
8535 return ASC_ERROR;
8536 }
8537
4b47e464 8538 ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
41d2493d
MW		 8539 err_code = adv_dvc->err_code;
8540 }
8541
8542 switch (ret) {
8543 case ASC_NOERROR:
8544 ASC_STATS(scp->device->host, exe_noerror);
8545 /*
8546 * Increment monotonically increasing per device
8547 * successful request counter. Wrapping doesn't matter.
8548 */
8549 boardp->reqcnt[scp->device->id]++;
b352f923 8550 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
41d2493d
MW		 8551 break;
8552 case ASC_BUSY:
4b47e464 8553 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
41d2493d
MW		 8554 ASC_STATS(scp->device->host, exe_busy);
8555 break;
8556 case ASC_ERROR:
9d0e96eb
MW		 8557 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8558 "err_code 0x%x\n", err_code);
41d2493d
MW		 8559 ASC_STATS(scp->device->host, exe_error);
8560 scp->result = HOST_BYTE(DID_ERROR);
8561 break;
8562 default:
9d0e96eb
MW		 8563 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8564 "err_code 0x%x\n", err_code);
41d2493d
MW		 8565 ASC_STATS(scp->device->host, exe_unknown);
8566 scp->result = HOST_BYTE(DID_ERROR);
8567 break;
27c868c2 8568 }
1da177e4 8569
b352f923 8570 ASC_DBG(1, "end\n");
51219358
MW		 8571 return ret;
8572}
27c868c2 8573
51219358
MW		 8574/*
8575 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8576 *
8577 * This function always returns 0. Command return status is saved
8578 * in the 'scp' result field.
8579 */
8580static int
f281233d 8581advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
51219358
MW		 8582{
8583 struct Scsi_Host *shost = scp->device->host;
51219358 8584 int asc_res, result = 0;
27c868c2 8585
51219358
MW		 8586 ASC_STATS(shost, queuecommand);
8587 scp->scsi_done = done;
27c868c2 8588
51219358 8589 asc_res = asc_execute_scsi_cmnd(scp);
51219358
MW		 8590
8591 switch (asc_res) {
8592 case ASC_NOERROR:
8593 break;
8594 case ASC_BUSY:
8595 result = SCSI_MLQUEUE_HOST_BUSY;
8596 break;
8597 case ASC_ERROR:
8598 default:
8599 asc_scsi_done(scp);
8600 break;
8601 }
8602
8603 return result;
8604}
8605
f281233d
JG		 8606static DEF_SCSI_QCMD(advansys_queuecommand)
8607
6f039790 8608static ushort AscGetEisaChipCfg(PortAddr iop_base)
51219358
MW		 8609{
8610 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8611 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8612 return inpw(eisa_cfg_iop);
8613}
8614
8615/*
8616 * Return the BIOS address of the adapter at the specified
8617 * I/O port and with the specified bus type.
8618 */
6f039790
GKH		 8619static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8620 unsigned short bus_type)
51219358
MW		 8621{
8622 unsigned short cfg_lsw;
8623 unsigned short bios_addr;
27c868c2
MW		 8624
8625 /*
51219358
MW		 8626 * The PCI BIOS is re-located by the motherboard BIOS. Because
8627 * of this the driver can not determine where a PCI BIOS is
8628 * loaded and executes.
27c868c2 8629 */
51219358
MW		 8630 if (bus_type & ASC_IS_PCI)
8631 return 0;
27c868c2 8632
51219358
MW		 8633 if ((bus_type & ASC_IS_EISA) != 0) {
8634 cfg_lsw = AscGetEisaChipCfg(iop_base);
8635 cfg_lsw &= 0x000F;
8636 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8637 return bios_addr;
8638 }
27c868c2 8639
51219358 8640 cfg_lsw = AscGetChipCfgLsw(iop_base);
27c868c2
MW		 8641
8642 /*
51219358 8643 * ISA PnP uses the top bit as the 32K BIOS flag
27c868c2 8644 */
51219358
MW		 8645 if (bus_type == ASC_IS_ISAPNP)
8646 cfg_lsw &= 0x7FFF;
8647 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8648 return bios_addr;
8649}
8650
6f039790 8651static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
51219358
MW		 8652{
8653 ushort cfg_lsw;
8654
8655 if (AscGetChipScsiID(iop_base) == new_host_id) {
8656 return (new_host_id);
27c868c2 8657 }
51219358
MW		 8658 cfg_lsw = AscGetChipCfgLsw(iop_base);
8659 cfg_lsw &= 0xF8FF;
8660 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8661 AscSetChipCfgLsw(iop_base, cfg_lsw);
8662 return (AscGetChipScsiID(iop_base));
8663}
27c868c2 8664
6f039790 8665static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
51219358
MW		 8666{
8667 unsigned char sc;
27c868c2 8668
51219358
MW		 8669 AscSetBank(iop_base, 1);
8670 sc = inp(iop_base + IOP_REG_SC);
8671 AscSetBank(iop_base, 0);
8672 return sc;
8673}
27c868c2 8674
6f039790
GKH		 8675static unsigned char AscGetChipVersion(PortAddr iop_base,
8676 unsigned short bus_type)
51219358
MW		 8677{
8678 if (bus_type & ASC_IS_EISA) {
8679 PortAddr eisa_iop;
8680 unsigned char revision;
8681 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8682 (PortAddr) ASC_EISA_REV_IOP_MASK;
8683 revision = inp(eisa_iop);
8684 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
27c868c2 8685 }
51219358
MW		 8686 return AscGetChipVerNo(iop_base);
8687}
27c868c2 8688
51219358 8689#ifdef CONFIG_ISA
6f039790 8690static void AscEnableIsaDma(uchar dma_channel)
51219358
MW		 8691{
8692 if (dma_channel < 4) {
8693 outp(0x000B, (ushort)(0xC0 | dma_channel));
8694 outp(0x000A, dma_channel);
8695 } else if (dma_channel < 8) {
8696 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
8697 outp(0x00D4, (ushort)(dma_channel - 4));
8698 }
51219358
MW		 8699}
8700#endif /* CONFIG_ISA */
8701
8702static int AscStopQueueExe(PortAddr iop_base)
8703{
8704 int count = 0;
8705
8706 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
8707 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8708 ASC_STOP_REQ_RISC_STOP);
8709 do {
8710 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
8711 ASC_STOP_ACK_RISC_STOP) {
8712 return (1);
8713 }
8714 mdelay(100);
8715 } while (count++ < 20);
8716 }
8717 return (0);
8718}
8719
95cfab6c 8720static unsigned int AscGetMaxDmaCount(ushort bus_type)
51219358
MW		 8721{
8722 if (bus_type & ASC_IS_ISA)
8723 return ASC_MAX_ISA_DMA_COUNT;
8724 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
8725 return ASC_MAX_VL_DMA_COUNT;
8726 return ASC_MAX_PCI_DMA_COUNT;
27c868c2 8727}
1da177e4 8728
51219358 8729#ifdef CONFIG_ISA
6f039790 8730static ushort AscGetIsaDmaChannel(PortAddr iop_base)
27c868c2 8731{
51219358 8732 ushort channel;
1da177e4 8733
51219358
MW		 8734 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
8735 if (channel == 0x03)
8736 return (0);
8737 else if (channel == 0x00)
8738 return (7);
8739 return (channel + 4);
8740}
1da177e4 8741
6f039790 8742static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
51219358
MW		 8743{
8744 ushort cfg_lsw;
8745 uchar value;
1da177e4 8746
51219358
MW		 8747 if ((dma_channel >= 5) && (dma_channel <= 7)) {
8748 if (dma_channel == 7)
8749 value = 0x00;
8750 else
8751 value = dma_channel - 4;
8752 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
8753 cfg_lsw |= value;
8754 AscSetChipCfgLsw(iop_base, cfg_lsw);
8755 return (AscGetIsaDmaChannel(iop_base));
8756 }
8757 return 0;
8758}
1da177e4 8759
6f039790 8760static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
51219358
MW		 8761{
8762 uchar speed_value;
1da177e4 8763
51219358
MW		 8764 AscSetBank(iop_base, 1);
8765 speed_value = AscReadChipDmaSpeed(iop_base);
8766 speed_value &= 0x07;
8767 AscSetBank(iop_base, 0);
8768 return speed_value;
8769}
1da177e4 8770
6f039790 8771static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
51219358
MW		 8772{
8773 speed_value &= 0x07;
8774 AscSetBank(iop_base, 1);
8775 AscWriteChipDmaSpeed(iop_base, speed_value);
8776 AscSetBank(iop_base, 0);
8777 return AscGetIsaDmaSpeed(iop_base);
8778}
8779#endif /* CONFIG_ISA */
1da177e4 8780
f33134e5 8781static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
51219358
MW		 8782{
8783 int i;
8784 PortAddr iop_base;
51219358 8785 uchar chip_version;
1da177e4 8786
51219358 8787 iop_base = asc_dvc->iop_base;
51219358
MW		 8788 asc_dvc->err_code = 0;
8789 if ((asc_dvc->bus_type &
8790 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
8791 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
27c868c2 8792 }
51219358
MW		 8793 AscSetChipControl(iop_base, CC_HALT);
8794 AscSetChipStatus(iop_base, 0);
8795 asc_dvc->bug_fix_cntl = 0;
8796 asc_dvc->pci_fix_asyn_xfer = 0;
8797 asc_dvc->pci_fix_asyn_xfer_always = 0;
421f91d2 8798 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
51219358
MW		 8799 asc_dvc->sdtr_done = 0;
8800 asc_dvc->cur_total_qng = 0;
ae26759e 8801 asc_dvc->is_in_int = false;
51219358
MW		 8802 asc_dvc->in_critical_cnt = 0;
8803 asc_dvc->last_q_shortage = 0;
8804 asc_dvc->use_tagged_qng = 0;
8805 asc_dvc->no_scam = 0;
8806 asc_dvc->unit_not_ready = 0;
8807 asc_dvc->queue_full_or_busy = 0;
8808 asc_dvc->redo_scam = 0;
8809 asc_dvc->res2 = 0;
afbb68c3 8810 asc_dvc->min_sdtr_index = 0;
51219358
MW		 8811 asc_dvc->cfg->can_tagged_qng = 0;
8812 asc_dvc->cfg->cmd_qng_enabled = 0;
8813 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
8814 asc_dvc->init_sdtr = 0;
8815 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
8816 asc_dvc->scsi_reset_wait = 3;
8817 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
8818 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
8819 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
8820 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
8821 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
51219358
MW		 8822 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
8823 asc_dvc->cfg->chip_version = chip_version;
afbb68c3 8824 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
51219358
MW		 8825 asc_dvc->max_sdtr_index = 7;
8826 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
8827 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
8828 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
afbb68c3 8829 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
51219358
MW		 8830 asc_dvc->max_sdtr_index = 15;
8831 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
8832 AscSetExtraControl(iop_base,
8833 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
8834 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
8835 AscSetExtraControl(iop_base,
8836 (SEC_ACTIVE_NEGATE |
8837 SEC_ENABLE_FILTER));
27c868c2
MW		 8838 }
8839 }
51219358
MW		 8840 if (asc_dvc->bus_type == ASC_IS_PCI) {
8841 AscSetExtraControl(iop_base,
8842 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
8843 }
1da177e4 8844
51219358
MW		 8845 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
8846#ifdef CONFIG_ISA
8847 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
8848 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
8849 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
8850 asc_dvc->bus_type = ASC_IS_ISAPNP;
27c868c2 8851 }
51219358
MW		 8852 asc_dvc->cfg->isa_dma_channel =
8853 (uchar)AscGetIsaDmaChannel(iop_base);
27c868c2 8854 }
51219358
MW		 8855#endif /* CONFIG_ISA */
8856 for (i = 0; i <= ASC_MAX_TID; i++) {
8857 asc_dvc->cur_dvc_qng[i] = 0;
8858 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
8859 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
8860 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
8861 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
27c868c2 8862 }
51219358 8863}
1da177e4 8864
6f039790 8865static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
51219358
MW		 8866{
8867 int retry;
27c868c2 8868
51219358
MW		 8869 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
8870 unsigned char read_back;
8871 AscSetChipEEPCmd(iop_base, cmd_reg);
8872 mdelay(1);
8873 read_back = AscGetChipEEPCmd(iop_base);
8874 if (read_back == cmd_reg)
8875 return 1;
27c868c2 8876 }
51219358
MW		 8877 return 0;
8878}
1da177e4 8879
6f039790 8880static void AscWaitEEPRead(void)
51219358
MW		 8881{
8882 mdelay(1);
27c868c2 8883}
1da177e4 8884
6f039790 8885static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
27c868c2 8886{
51219358
MW		 8887 ushort read_wval;
8888 uchar cmd_reg;
27c868c2 8889
51219358
MW		 8890 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
8891 AscWaitEEPRead();
8892 cmd_reg = addr | ASC_EEP_CMD_READ;
8893 AscWriteEEPCmdReg(iop_base, cmd_reg);
8894 AscWaitEEPRead();
8895 read_wval = AscGetChipEEPData(iop_base);
8896 AscWaitEEPRead();
8897 return read_wval;
8898}
27c868c2 8899
6f039790
GKH		 8900static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
8901 ushort bus_type)
51219358
MW		 8902{
8903 ushort wval;
8904 ushort sum;
8905 ushort *wbuf;
8906 int cfg_beg;
8907 int cfg_end;
8908 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
8909 int s_addr;
27c868c2 8910
51219358
MW		 8911 wbuf = (ushort *)cfg_buf;
8912 sum = 0;
8913 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
8914 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
8915 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
8916 sum += *wbuf;
8917 }
8918 if (bus_type & ASC_IS_VL) {
8919 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
8920 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
8921 } else {
8922 cfg_beg = ASC_EEP_DVC_CFG_BEG;
8923 cfg_end = ASC_EEP_MAX_DVC_ADDR;
8924 }
8925 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
8926 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
8927 if (s_addr <= uchar_end_in_config) {
8928 /*
8929 * Swap all char fields - must unswap bytes already swapped
8930 * by AscReadEEPWord().
8931 */
8932 *wbuf = le16_to_cpu(wval);
8933 } else {
8934 /* Don't swap word field at the end - cntl field. */
8935 *wbuf = wval;
8936 }
8937 sum += wval; /* Checksum treats all EEPROM data as words. */
8938 }
27c868c2 8939 /*
51219358
MW		 8940 * Read the checksum word which will be compared against 'sum'
8941 * by the caller. Word field already swapped.
27c868c2 8942 */
51219358
MW		 8943 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
8944 return sum;
8945}
1da177e4 8946
6f039790 8947static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
51219358
MW		 8948{
8949 PortAddr iop_base;
8950 ushort q_addr;
8951 ushort saved_word;
8952 int sta;
1da177e4 8953
51219358
MW		 8954 iop_base = asc_dvc->iop_base;
8955 sta = 0;
8956 q_addr = ASC_QNO_TO_QADDR(241);
8957 saved_word = AscReadLramWord(iop_base, q_addr);
8958 AscSetChipLramAddr(iop_base, q_addr);
8959 AscSetChipLramData(iop_base, 0x55AA);
8960 mdelay(10);
8961 AscSetChipLramAddr(iop_base, q_addr);
8962 if (AscGetChipLramData(iop_base) == 0x55AA) {
8963 sta = 1;
8964 AscWriteLramWord(iop_base, q_addr, saved_word);
8965 }
8966 return (sta);
8967}
1da177e4 8968
6f039790 8969static void AscWaitEEPWrite(void)
51219358
MW		 8970{
8971 mdelay(20);
51219358 8972}
1da177e4 8973
6f039790 8974static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
51219358
MW		 8975{
8976 ushort read_back;
8977 int retry;
1da177e4 8978
51219358 8979 retry = 0;
ae26759e 8980 while (true) {
51219358
MW		 8981 AscSetChipEEPData(iop_base, data_reg);
8982 mdelay(1);
8983 read_back = AscGetChipEEPData(iop_base);
8984 if (read_back == data_reg) {
8985 return (1);
8986 }
8987 if (retry++ > ASC_EEP_MAX_RETRY) {
8988 return (0);
8989 }
27c868c2 8990 }
51219358 8991}
27c868c2 8992
6f039790 8993static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
51219358
MW		 8994{
8995 ushort read_wval;
8996
8997 read_wval = AscReadEEPWord(iop_base, addr);
8998 if (read_wval != word_val) {
8999 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9000 AscWaitEEPRead();
9001 AscWriteEEPDataReg(iop_base, word_val);
9002 AscWaitEEPRead();
9003 AscWriteEEPCmdReg(iop_base,
9004 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9005 AscWaitEEPWrite();
9006 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9007 AscWaitEEPRead();
9008 return (AscReadEEPWord(iop_base, addr));
9009 }
9010 return (read_wval);
9011}
9012
6f039790
GKH		 9013static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9014 ushort bus_type)
51219358
MW		 9015{
9016 int n_error;
9017 ushort *wbuf;
9018 ushort word;
9019 ushort sum;
9020 int s_addr;
9021 int cfg_beg;
9022 int cfg_end;
9023 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9024
9025 wbuf = (ushort *)cfg_buf;
9026 n_error = 0;
9027 sum = 0;
9028 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9029 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9030 sum += *wbuf;
9031 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9032 n_error++;
27c868c2 9033 }
51219358
MW		 9034 }
9035 if (bus_type & ASC_IS_VL) {
9036 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9037 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9038 } else {
9039 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9040 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9041 }
9042 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9043 if (s_addr <= uchar_end_in_config) {
9044 /*
9045 * This is a char field. Swap char fields before they are
9046 * swapped again by AscWriteEEPWord().
9047 */
9048 word = cpu_to_le16(*wbuf);
9049 if (word !=
9050 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9051 n_error++;
9052 }
9053 } else {
9054 /* Don't swap word field at the end - cntl field. */
9055 if (*wbuf !=
9056 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9057 n_error++;
9058 }
27c868c2 9059 }
51219358
MW		 9060 sum += *wbuf; /* Checksum calculated from word values. */
9061 }
9062 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9063 *wbuf = sum;
9064 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9065 n_error++;
27c868c2 9066 }
1da177e4 9067
51219358
MW		 9068 /* Read EEPROM back again. */
9069 wbuf = (ushort *)cfg_buf;
27c868c2 9070 /*
51219358 9071 * Read two config words; Byte-swapping done by AscReadEEPWord().
27c868c2 9072 */
51219358
MW		 9073 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9074 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9075 n_error++;
27c868c2
MW		 9076 }
9077 }
51219358
MW		 9078 if (bus_type & ASC_IS_VL) {
9079 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9080 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9081 } else {
9082 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9083 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9084 }
9085 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9086 if (s_addr <= uchar_end_in_config) {
9087 /*
9088 * Swap all char fields. Must unswap bytes already swapped
9089 * by AscReadEEPWord().
9090 */
9091 word =
9092 le16_to_cpu(AscReadEEPWord
9093 (iop_base, (uchar)s_addr));
27c868c2 9094 } else {
51219358
MW		 9095 /* Don't swap word field at the end - cntl field. */
9096 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9097 }
9098 if (*wbuf != word) {
9099 n_error++;
27c868c2
MW		 9100 }
9101 }
51219358
MW		 9102 /* Read checksum; Byte swapping not needed. */
9103 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9104 n_error++;
27c868c2 9105 }
51219358
MW		 9106 return n_error;
9107}
1da177e4 9108
6f039790
GKH		 9109static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9110 ushort bus_type)
51219358
MW		 9111{
9112 int retry;
9113 int n_error;
27c868c2 9114
51219358 9115 retry = 0;
ae26759e 9116 while (true) {
51219358
MW		 9117 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9118 bus_type)) == 0) {
9119 break;
9120 }
9121 if (++retry > ASC_EEP_MAX_RETRY) {
9122 break;
9123 }
9124 }
9125 return n_error;
9126}
27c868c2 9127
f33134e5 9128static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9129{
9130 ASCEEP_CONFIG eep_config_buf;
9131 ASCEEP_CONFIG *eep_config;
9132 PortAddr iop_base;
9133 ushort chksum;
9134 ushort warn_code;
9135 ushort cfg_msw, cfg_lsw;
9136 int i;
9137 int write_eep = 0;
27c868c2 9138
51219358
MW		 9139 iop_base = asc_dvc->iop_base;
9140 warn_code = 0;
9141 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9142 AscStopQueueExe(iop_base);
ae26759e 9143 if ((AscStopChip(iop_base)) ||
51219358
MW		 9144 (AscGetChipScsiCtrl(iop_base) != 0)) {
9145 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9146 AscResetChipAndScsiBus(asc_dvc);
9147 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9148 }
d647c783 9149 if (!AscIsChipHalted(iop_base)) {
51219358
MW		 9150 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9151 return (warn_code);
9152 }
9153 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9154 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9155 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9156 return (warn_code);
9157 }
9158 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9159 cfg_msw = AscGetChipCfgMsw(iop_base);
9160 cfg_lsw = AscGetChipCfgLsw(iop_base);
9161 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9162 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9163 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9164 AscSetChipCfgMsw(iop_base, cfg_msw);
9165 }
9166 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
b352f923 9167 ASC_DBG(1, "chksum 0x%x\n", chksum);
51219358
MW		 9168 if (chksum == 0) {
9169 chksum = 0xaa55;
9170 }
9171 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9172 warn_code |= ASC_WARN_AUTO_CONFIG;
9173 if (asc_dvc->cfg->chip_version == 3) {
9174 if (eep_config->cfg_lsw != cfg_lsw) {
9175 warn_code |= ASC_WARN_EEPROM_RECOVER;
9176 eep_config->cfg_lsw =
9177 AscGetChipCfgLsw(iop_base);
9178 }
9179 if (eep_config->cfg_msw != cfg_msw) {
9180 warn_code |= ASC_WARN_EEPROM_RECOVER;
9181 eep_config->cfg_msw =
9182 AscGetChipCfgMsw(iop_base);
9183 }
9184 }
9185 }
9186 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9187 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
b352f923 9188 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
51219358
MW		 9189 if (chksum != eep_config->chksum) {
9190 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9191 ASC_CHIP_VER_PCI_ULTRA_3050) {
b352f923 9192 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
51219358
MW		 9193 eep_config->init_sdtr = 0xFF;
9194 eep_config->disc_enable = 0xFF;
9195 eep_config->start_motor = 0xFF;
9196 eep_config->use_cmd_qng = 0;
9197 eep_config->max_total_qng = 0xF0;
9198 eep_config->max_tag_qng = 0x20;
9199 eep_config->cntl = 0xBFFF;
9200 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9201 eep_config->no_scam = 0;
9202 eep_config->adapter_info[0] = 0;
9203 eep_config->adapter_info[1] = 0;
9204 eep_config->adapter_info[2] = 0;
9205 eep_config->adapter_info[3] = 0;
9206 eep_config->adapter_info[4] = 0;
9207 /* Indicate EEPROM-less board. */
9208 eep_config->adapter_info[5] = 0xBB;
27c868c2 9209 } else {
51219358
MW		 9210 ASC_PRINT
9211 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9212 write_eep = 1;
9213 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9214 }
9215 }
9216 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9217 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9218 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9219 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9220 asc_dvc->start_motor = eep_config->start_motor;
9221 asc_dvc->dvc_cntl = eep_config->cntl;
9222 asc_dvc->no_scam = eep_config->no_scam;
9223 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9224 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9225 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9226 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9227 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9228 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9229 if (!AscTestExternalLram(asc_dvc)) {
9230 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9231 ASC_IS_PCI_ULTRA)) {
9232 eep_config->max_total_qng =
9233 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9234 eep_config->max_tag_qng =
9235 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9236 } else {
9237 eep_config->cfg_msw |= 0x0800;
9238 cfg_msw |= 0x0800;
9239 AscSetChipCfgMsw(iop_base, cfg_msw);
9240 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9241 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
27c868c2 9242 }
51219358
MW		 9243 } else {
9244 }
9245 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9246 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9247 }
9248 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9249 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9250 }
9251 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9252 eep_config->max_tag_qng = eep_config->max_total_qng;
9253 }
9254 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9255 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9256 }
9257 asc_dvc->max_total_qng = eep_config->max_total_qng;
9258 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9259 eep_config->use_cmd_qng) {
9260 eep_config->disc_enable = eep_config->use_cmd_qng;
9261 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9262 }
51219358
MW		 9263 ASC_EEP_SET_CHIP_ID(eep_config,
9264 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9265 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9266 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9267 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
afbb68c3 9268 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
27c868c2 9269 }
1da177e4 9270
51219358
MW		 9271 for (i = 0; i <= ASC_MAX_TID; i++) {
9272 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9273 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9274 asc_dvc->cfg->sdtr_period_offset[i] =
9275 (uchar)(ASC_DEF_SDTR_OFFSET |
afbb68c3 9276 (asc_dvc->min_sdtr_index << 4));
51219358
MW		 9277 }
9278 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9279 if (write_eep) {
9280 if ((i = AscSetEEPConfig(iop_base, eep_config,
9281 asc_dvc->bus_type)) != 0) {
9282 ASC_PRINT1
9283 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9284 i);
27c868c2 9285 } else {
51219358
MW		 9286 ASC_PRINT
9287 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
27c868c2
MW		 9288 }
9289 }
51219358 9290 return (warn_code);
1da177e4
LT		 9291}
9292
6f039790 9293static int AscInitGetConfig(struct Scsi_Host *shost)
1da177e4 9294{
9d0e96eb
MW		 9295 struct asc_board *board = shost_priv(shost);
9296 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
51219358 9297 unsigned short warn_code = 0;
27c868c2 9298
51219358
MW		 9299 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9300 if (asc_dvc->err_code != 0)
9301 return asc_dvc->err_code;
27c868c2 9302
51219358 9303 if (AscFindSignature(asc_dvc->iop_base)) {
f33134e5
HR		 9304 AscInitAscDvcVar(asc_dvc);
9305 warn_code = AscInitFromEEP(asc_dvc);
51219358
MW		 9306 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9307 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9308 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9309 } else {
9310 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9311 }
27c868c2 9312
51219358
MW		 9313 switch (warn_code) {
9314 case 0: /* No error */
9315 break;
9316 case ASC_WARN_IO_PORT_ROTATE:
9d0e96eb
MW		 9317 shost_printk(KERN_WARNING, shost, "I/O port address "
9318 "modified\n");
51219358
MW		 9319 break;
9320 case ASC_WARN_AUTO_CONFIG:
9d0e96eb
MW		 9321 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9322 "enabled\n");
51219358
MW		 9323 break;
9324 case ASC_WARN_EEPROM_CHKSUM:
9d0e96eb 9325 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
51219358
MW		 9326 break;
9327 case ASC_WARN_IRQ_MODIFIED:
9d0e96eb 9328 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
51219358
MW		 9329 break;
9330 case ASC_WARN_CMD_QNG_CONFLICT:
9d0e96eb
MW		 9331 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9332 "disconnects\n");
51219358
MW		 9333 break;
9334 default:
9d0e96eb
MW		 9335 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9336 warn_code);
51219358
MW		 9337 break;
9338 }
1da177e4 9339
9d0e96eb
MW		 9340 if (asc_dvc->err_code != 0)
9341 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9342 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
27c868c2 9343
51219358
MW		 9344 return asc_dvc->err_code;
9345}
1da177e4 9346
6f039790 9347static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
51219358 9348{
9d0e96eb
MW		 9349 struct asc_board *board = shost_priv(shost);
9350 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
51219358
MW		 9351 PortAddr iop_base = asc_dvc->iop_base;
9352 unsigned short cfg_msw;
9353 unsigned short warn_code = 0;
1da177e4 9354
51219358
MW		 9355 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9356 if (asc_dvc->err_code != 0)
9357 return asc_dvc->err_code;
9358 if (!AscFindSignature(asc_dvc->iop_base)) {
9359 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9360 return asc_dvc->err_code;
27c868c2 9361 }
1da177e4 9362
51219358
MW		 9363 cfg_msw = AscGetChipCfgMsw(iop_base);
9364 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9365 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9366 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9367 AscSetChipCfgMsw(iop_base, cfg_msw);
9368 }
9369 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9370 asc_dvc->cfg->cmd_qng_enabled) {
9371 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9372 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9373 }
9374 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9375 warn_code |= ASC_WARN_AUTO_CONFIG;
9376 }
51219358
MW		 9377#ifdef CONFIG_PCI
9378 if (asc_dvc->bus_type & ASC_IS_PCI) {
9379 cfg_msw &= 0xFFC0;
9380 AscSetChipCfgMsw(iop_base, cfg_msw);
9381 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
27c868c2 9382 } else {
51219358
MW		 9383 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9384 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9385 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9386 asc_dvc->bug_fix_cntl |=
9387 ASC_BUG_FIX_ASYN_USE_SYN;
9388 }
27c868c2 9389 }
51219358
MW		 9390 } else
9391#endif /* CONFIG_PCI */
9392 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9393 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9394 == ASC_CHIP_VER_ASYN_BUG) {
9395 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
27c868c2
MW		 9396 }
9397 }
51219358
MW		 9398 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9399 asc_dvc->cfg->chip_scsi_id) {
9400 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9401 }
9402#ifdef CONFIG_ISA
9403 if (asc_dvc->bus_type & ASC_IS_ISA) {
9404 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9405 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9406 }
9407#endif /* CONFIG_ISA */
1da177e4 9408
51219358
MW		 9409 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9410
9411 switch (warn_code) {
9412 case 0: /* No error. */
9413 break;
9414 case ASC_WARN_IO_PORT_ROTATE:
9d0e96eb
MW		 9415 shost_printk(KERN_WARNING, shost, "I/O port address "
9416 "modified\n");
51219358
MW		 9417 break;
9418 case ASC_WARN_AUTO_CONFIG:
9d0e96eb
MW		 9419 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9420 "enabled\n");
51219358
MW		 9421 break;
9422 case ASC_WARN_EEPROM_CHKSUM:
9d0e96eb 9423 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
51219358
MW		 9424 break;
9425 case ASC_WARN_IRQ_MODIFIED:
9d0e96eb 9426 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
51219358
MW		 9427 break;
9428 case ASC_WARN_CMD_QNG_CONFLICT:
9d0e96eb
MW		 9429 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9430 "disconnects\n");
51219358
MW		 9431 break;
9432 default:
9d0e96eb
MW		 9433 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9434 warn_code);
51219358 9435 break;
27c868c2 9436 }
1da177e4 9437
9d0e96eb
MW		 9438 if (asc_dvc->err_code != 0)
9439 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9440 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
27c868c2 9441
51219358
MW		 9442 return asc_dvc->err_code;
9443}
27c868c2 9444
51219358
MW		 9445/*
9446 * EEPROM Configuration.
9447 *
9448 * All drivers should use this structure to set the default EEPROM
9449 * configuration. The BIOS now uses this structure when it is built.
9450 * Additional structure information can be found in a_condor.h where
9451 * the structure is defined.
9452 *
9453 * The *_Field_IsChar structs are needed to correct for endianness.
9454 * These values are read from the board 16 bits at a time directly
9455 * into the structs. Because some fields are char, the values will be
9456 * in the wrong order. The *_Field_IsChar tells when to flip the
9457 * bytes. Data read and written to PCI memory is automatically swapped
9458 * on big-endian platforms so char fields read as words are actually being
9459 * unswapped on big-endian platforms.
9460 */
6f039790 9461static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
51219358
MW		 9462 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9463 0x0000, /* cfg_msw */
9464 0xFFFF, /* disc_enable */
9465 0xFFFF, /* wdtr_able */
9466 0xFFFF, /* sdtr_able */
9467 0xFFFF, /* start_motor */
9468 0xFFFF, /* tagqng_able */
9469 0xFFFF, /* bios_scan */
9470 0, /* scam_tolerant */
9471 7, /* adapter_scsi_id */
9472 0, /* bios_boot_delay */
9473 3, /* scsi_reset_delay */
9474 0, /* bios_id_lun */
9475 0, /* termination */
9476 0, /* reserved1 */
9477 0xFFE7, /* bios_ctrl */
9478 0xFFFF, /* ultra_able */
9479 0, /* reserved2 */
9480 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9481 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9482 0, /* dvc_cntl */
9483 0, /* bug_fix */
9484 0, /* serial_number_word1 */
9485 0, /* serial_number_word2 */
9486 0, /* serial_number_word3 */
9487 0, /* check_sum */
9488 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9489 , /* oem_name[16] */
9490 0, /* dvc_err_code */
9491 0, /* adv_err_code */
9492 0, /* adv_err_addr */
9493 0, /* saved_dvc_err_code */
9494 0, /* saved_adv_err_code */
9495 0, /* saved_adv_err_addr */
9496 0 /* num_of_err */
9497};
27c868c2 9498
6f039790 9499static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
51219358
MW		 9500 0, /* cfg_lsw */
9501 0, /* cfg_msw */
9502 0, /* -disc_enable */
9503 0, /* wdtr_able */
9504 0, /* sdtr_able */
9505 0, /* start_motor */
9506 0, /* tagqng_able */
9507 0, /* bios_scan */
9508 0, /* scam_tolerant */
9509 1, /* adapter_scsi_id */
9510 1, /* bios_boot_delay */
9511 1, /* scsi_reset_delay */
9512 1, /* bios_id_lun */
9513 1, /* termination */
9514 1, /* reserved1 */
9515 0, /* bios_ctrl */
9516 0, /* ultra_able */
9517 0, /* reserved2 */
9518 1, /* max_host_qng */
9519 1, /* max_dvc_qng */
9520 0, /* dvc_cntl */
9521 0, /* bug_fix */
9522 0, /* serial_number_word1 */
9523 0, /* serial_number_word2 */
9524 0, /* serial_number_word3 */
9525 0, /* check_sum */
9526 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9527 , /* oem_name[16] */
9528 0, /* dvc_err_code */
9529 0, /* adv_err_code */
9530 0, /* adv_err_addr */
9531 0, /* saved_dvc_err_code */
9532 0, /* saved_adv_err_code */
9533 0, /* saved_adv_err_addr */
9534 0 /* num_of_err */
9535};
1da177e4 9536
6f039790 9537static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
51219358
MW		 9538 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9539 0x0000, /* 01 cfg_msw */
9540 0xFFFF, /* 02 disc_enable */
9541 0xFFFF, /* 03 wdtr_able */
9542 0x4444, /* 04 sdtr_speed1 */
9543 0xFFFF, /* 05 start_motor */
9544 0xFFFF, /* 06 tagqng_able */
9545 0xFFFF, /* 07 bios_scan */
9546 0, /* 08 scam_tolerant */
9547 7, /* 09 adapter_scsi_id */
9548 0, /* bios_boot_delay */
9549 3, /* 10 scsi_reset_delay */
9550 0, /* bios_id_lun */
9551 0, /* 11 termination_se */
9552 0, /* termination_lvd */
9553 0xFFE7, /* 12 bios_ctrl */
9554 0x4444, /* 13 sdtr_speed2 */
9555 0x4444, /* 14 sdtr_speed3 */
9556 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9557 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9558 0, /* 16 dvc_cntl */
9559 0x4444, /* 17 sdtr_speed4 */
9560 0, /* 18 serial_number_word1 */
9561 0, /* 19 serial_number_word2 */
9562 0, /* 20 serial_number_word3 */
9563 0, /* 21 check_sum */
9564 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9565 , /* 22-29 oem_name[16] */
9566 0, /* 30 dvc_err_code */
9567 0, /* 31 adv_err_code */
9568 0, /* 32 adv_err_addr */
9569 0, /* 33 saved_dvc_err_code */
9570 0, /* 34 saved_adv_err_code */
9571 0, /* 35 saved_adv_err_addr */
9572 0, /* 36 reserved */
9573 0, /* 37 reserved */
9574 0, /* 38 reserved */
9575 0, /* 39 reserved */
9576 0, /* 40 reserved */
9577 0, /* 41 reserved */
9578 0, /* 42 reserved */
9579 0, /* 43 reserved */
9580 0, /* 44 reserved */
9581 0, /* 45 reserved */
9582 0, /* 46 reserved */
9583 0, /* 47 reserved */
9584 0, /* 48 reserved */
9585 0, /* 49 reserved */
9586 0, /* 50 reserved */
9587 0, /* 51 reserved */
9588 0, /* 52 reserved */
9589 0, /* 53 reserved */
9590 0, /* 54 reserved */
9591 0, /* 55 reserved */
9592 0, /* 56 cisptr_lsw */
9593 0, /* 57 cisprt_msw */
9594 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9595 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9596 0, /* 60 reserved */
9597 0, /* 61 reserved */
9598 0, /* 62 reserved */
9599 0 /* 63 reserved */
9600};
27c868c2 9601
6f039790 9602static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
51219358
MW		 9603 0, /* 00 cfg_lsw */
9604 0, /* 01 cfg_msw */
9605 0, /* 02 disc_enable */
9606 0, /* 03 wdtr_able */
9607 0, /* 04 sdtr_speed1 */
9608 0, /* 05 start_motor */
9609 0, /* 06 tagqng_able */
9610 0, /* 07 bios_scan */
9611 0, /* 08 scam_tolerant */
9612 1, /* 09 adapter_scsi_id */
9613 1, /* bios_boot_delay */
9614 1, /* 10 scsi_reset_delay */
9615 1, /* bios_id_lun */
9616 1, /* 11 termination_se */
9617 1, /* termination_lvd */
9618 0, /* 12 bios_ctrl */
9619 0, /* 13 sdtr_speed2 */
9620 0, /* 14 sdtr_speed3 */
9621 1, /* 15 max_host_qng */
9622 1, /* max_dvc_qng */
9623 0, /* 16 dvc_cntl */
9624 0, /* 17 sdtr_speed4 */
9625 0, /* 18 serial_number_word1 */
9626 0, /* 19 serial_number_word2 */
9627 0, /* 20 serial_number_word3 */
9628 0, /* 21 check_sum */
9629 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9630 , /* 22-29 oem_name[16] */
9631 0, /* 30 dvc_err_code */
9632 0, /* 31 adv_err_code */
9633 0, /* 32 adv_err_addr */
9634 0, /* 33 saved_dvc_err_code */
9635 0, /* 34 saved_adv_err_code */
9636 0, /* 35 saved_adv_err_addr */
9637 0, /* 36 reserved */
9638 0, /* 37 reserved */
9639 0, /* 38 reserved */
9640 0, /* 39 reserved */
9641 0, /* 40 reserved */
9642 0, /* 41 reserved */
9643 0, /* 42 reserved */
9644 0, /* 43 reserved */
9645 0, /* 44 reserved */
9646 0, /* 45 reserved */
9647 0, /* 46 reserved */
9648 0, /* 47 reserved */
9649 0, /* 48 reserved */
9650 0, /* 49 reserved */
9651 0, /* 50 reserved */
9652 0, /* 51 reserved */
9653 0, /* 52 reserved */
9654 0, /* 53 reserved */
9655 0, /* 54 reserved */
9656 0, /* 55 reserved */
9657 0, /* 56 cisptr_lsw */
9658 0, /* 57 cisprt_msw */
9659 0, /* 58 subsysvid */
9660 0, /* 59 subsysid */
9661 0, /* 60 reserved */
9662 0, /* 61 reserved */
9663 0, /* 62 reserved */
9664 0 /* 63 reserved */
9665};
27c868c2 9666
6f039790 9667static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
51219358
MW		 9668 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9669 0x0000, /* 01 cfg_msw */
9670 0xFFFF, /* 02 disc_enable */
9671 0xFFFF, /* 03 wdtr_able */
9672 0x5555, /* 04 sdtr_speed1 */
9673 0xFFFF, /* 05 start_motor */
9674 0xFFFF, /* 06 tagqng_able */
9675 0xFFFF, /* 07 bios_scan */
9676 0, /* 08 scam_tolerant */
9677 7, /* 09 adapter_scsi_id */
9678 0, /* bios_boot_delay */
9679 3, /* 10 scsi_reset_delay */
9680 0, /* bios_id_lun */
9681 0, /* 11 termination_se */
9682 0, /* termination_lvd */
9683 0xFFE7, /* 12 bios_ctrl */
9684 0x5555, /* 13 sdtr_speed2 */
9685 0x5555, /* 14 sdtr_speed3 */
9686 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9687 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9688 0, /* 16 dvc_cntl */
9689 0x5555, /* 17 sdtr_speed4 */
9690 0, /* 18 serial_number_word1 */
9691 0, /* 19 serial_number_word2 */
9692 0, /* 20 serial_number_word3 */
9693 0, /* 21 check_sum */
9694 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9695 , /* 22-29 oem_name[16] */
9696 0, /* 30 dvc_err_code */
9697 0, /* 31 adv_err_code */
9698 0, /* 32 adv_err_addr */
9699 0, /* 33 saved_dvc_err_code */
9700 0, /* 34 saved_adv_err_code */
9701 0, /* 35 saved_adv_err_addr */
9702 0, /* 36 reserved */
9703 0, /* 37 reserved */
9704 0, /* 38 reserved */
9705 0, /* 39 reserved */
9706 0, /* 40 reserved */
9707 0, /* 41 reserved */
9708 0, /* 42 reserved */
9709 0, /* 43 reserved */
9710 0, /* 44 reserved */
9711 0, /* 45 reserved */
9712 0, /* 46 reserved */
9713 0, /* 47 reserved */
9714 0, /* 48 reserved */
9715 0, /* 49 reserved */
9716 0, /* 50 reserved */
9717 0, /* 51 reserved */
9718 0, /* 52 reserved */
9719 0, /* 53 reserved */
9720 0, /* 54 reserved */
9721 0, /* 55 reserved */
9722 0, /* 56 cisptr_lsw */
9723 0, /* 57 cisprt_msw */
9724 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9725 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
9726 0, /* 60 reserved */
9727 0, /* 61 reserved */
9728 0, /* 62 reserved */
9729 0 /* 63 reserved */
9730};
1da177e4 9731
6f039790 9732static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
51219358
MW		 9733 0, /* 00 cfg_lsw */
9734 0, /* 01 cfg_msw */
9735 0, /* 02 disc_enable */
9736 0, /* 03 wdtr_able */
9737 0, /* 04 sdtr_speed1 */
9738 0, /* 05 start_motor */
9739 0, /* 06 tagqng_able */
9740 0, /* 07 bios_scan */
9741 0, /* 08 scam_tolerant */
9742 1, /* 09 adapter_scsi_id */
9743 1, /* bios_boot_delay */
9744 1, /* 10 scsi_reset_delay */
9745 1, /* bios_id_lun */
9746 1, /* 11 termination_se */
9747 1, /* termination_lvd */
9748 0, /* 12 bios_ctrl */
9749 0, /* 13 sdtr_speed2 */
9750 0, /* 14 sdtr_speed3 */
9751 1, /* 15 max_host_qng */
9752 1, /* max_dvc_qng */
9753 0, /* 16 dvc_cntl */
9754 0, /* 17 sdtr_speed4 */
9755 0, /* 18 serial_number_word1 */
9756 0, /* 19 serial_number_word2 */
9757 0, /* 20 serial_number_word3 */
9758 0, /* 21 check_sum */
9759 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9760 , /* 22-29 oem_name[16] */
9761 0, /* 30 dvc_err_code */
9762 0, /* 31 adv_err_code */
9763 0, /* 32 adv_err_addr */
9764 0, /* 33 saved_dvc_err_code */
9765 0, /* 34 saved_adv_err_code */
9766 0, /* 35 saved_adv_err_addr */
9767 0, /* 36 reserved */
9768 0, /* 37 reserved */
9769 0, /* 38 reserved */
9770 0, /* 39 reserved */
9771 0, /* 40 reserved */
9772 0, /* 41 reserved */
9773 0, /* 42 reserved */
9774 0, /* 43 reserved */
9775 0, /* 44 reserved */
9776 0, /* 45 reserved */
9777 0, /* 46 reserved */
9778 0, /* 47 reserved */
9779 0, /* 48 reserved */
9780 0, /* 49 reserved */
9781 0, /* 50 reserved */
9782 0, /* 51 reserved */
9783 0, /* 52 reserved */
9784 0, /* 53 reserved */
9785 0, /* 54 reserved */
9786 0, /* 55 reserved */
9787 0, /* 56 cisptr_lsw */
9788 0, /* 57 cisprt_msw */
9789 0, /* 58 subsysvid */
9790 0, /* 59 subsysid */
9791 0, /* 60 reserved */
9792 0, /* 61 reserved */
9793 0, /* 62 reserved */
9794 0 /* 63 reserved */
9795};
1da177e4 9796
51219358 9797#ifdef CONFIG_PCI
1da177e4 9798/*
51219358 9799 * Wait for EEPROM command to complete
1da177e4 9800 */
6f039790 9801static void AdvWaitEEPCmd(AdvPortAddr iop_base)
1da177e4 9802{
51219358 9803 int eep_delay_ms;
27c868c2 9804
51219358
MW		 9805 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
9806 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
9807 ASC_EEP_CMD_DONE) {
9808 break;
27c868c2 9809 }
51219358 9810 mdelay(1);
27c868c2 9811 }
51219358
MW		 9812 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
9813 0)
9814 BUG();
1da177e4
LT		 9815}
9816
9817/*
51219358 9818 * Read the EEPROM from specified location
1da177e4 9819 */
6f039790 9820static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
51219358
MW		 9821{
9822 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9823 ASC_EEP_CMD_READ | eep_word_addr);
9824 AdvWaitEEPCmd(iop_base);
9825 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
9826}
9827
9828/*
9829 * Write the EEPROM from 'cfg_buf'.
9830 */
6f039790
GKH		 9831static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
9832 ADVEEP_3550_CONFIG *cfg_buf)
1da177e4 9833{
27c868c2 9834 ushort *wbuf;
51219358 9835 ushort addr, chksum;
27c868c2
MW		 9836 ushort *charfields;
9837
27c868c2 9838 wbuf = (ushort *)cfg_buf;
51219358 9839 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
27c868c2
MW		 9840 chksum = 0;
9841
51219358
MW		 9842 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9843 AdvWaitEEPCmd(iop_base);
9844
9845 /*
9846 * Write EEPROM from word 0 to word 20.
9847 */
9848 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9849 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9850 ushort word;
9851
27c868c2 9852 if (*charfields++) {
51219358 9853 word = cpu_to_le16(*wbuf);
27c868c2 9854 } else {
51219358 9855 word = *wbuf;
27c868c2 9856 }
51219358
MW		 9857 chksum += *wbuf; /* Checksum is calculated from word values. */
9858 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9859 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9860 ASC_EEP_CMD_WRITE | addr);
9861 AdvWaitEEPCmd(iop_base);
9862 mdelay(ADV_EEP_DELAY_MS);
27c868c2 9863 }
51219358
MW		 9864
9865 /*
9866 * Write EEPROM checksum at word 21.
9867 */
9868 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9869 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9870 AdvWaitEEPCmd(iop_base);
27c868c2
MW		 9871 wbuf++;
9872 charfields++;
9873
51219358
MW		 9874 /*
9875 * Write EEPROM OEM name at words 22 to 29.
9876 */
9877 for (addr = ADV_EEP_DVC_CTL_BEGIN;
9878 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
9879 ushort word;
9880
27c868c2 9881 if (*charfields++) {
51219358
MW		 9882 word = cpu_to_le16(*wbuf);
9883 } else {
9884 word = *wbuf;
27c868c2 9885 }
51219358
MW		 9886 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9887 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9888 ASC_EEP_CMD_WRITE | addr);
9889 AdvWaitEEPCmd(iop_base);
27c868c2 9890 }
51219358
MW		 9891 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
9892 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 9893}
9894
9895/*
51219358 9896 * Write the EEPROM from 'cfg_buf'.
1da177e4 9897 */
6f039790
GKH		 9898static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
9899 ADVEEP_38C0800_CONFIG *cfg_buf)
1da177e4 9900{
27c868c2 9901 ushort *wbuf;
27c868c2 9902 ushort *charfields;
51219358 9903 ushort addr, chksum;
27c868c2 9904
27c868c2 9905 wbuf = (ushort *)cfg_buf;
51219358 9906 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
27c868c2
MW		 9907 chksum = 0;
9908
51219358
MW		 9909 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9910 AdvWaitEEPCmd(iop_base);
9911
9912 /*
9913 * Write EEPROM from word 0 to word 20.
9914 */
9915 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9916 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9917 ushort word;
9918
27c868c2 9919 if (*charfields++) {
51219358 9920 word = cpu_to_le16(*wbuf);
27c868c2 9921 } else {
51219358 9922 word = *wbuf;
27c868c2 9923 }
51219358
MW		 9924 chksum += *wbuf; /* Checksum is calculated from word values. */
9925 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9926 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9927 ASC_EEP_CMD_WRITE | addr);
9928 AdvWaitEEPCmd(iop_base);
9929 mdelay(ADV_EEP_DELAY_MS);
27c868c2 9930 }
51219358
MW		 9931
9932 /*
9933 * Write EEPROM checksum at word 21.
9934 */
9935 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9936 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9937 AdvWaitEEPCmd(iop_base);
27c868c2
MW		 9938 wbuf++;
9939 charfields++;
9940
51219358
MW		 9941 /*
9942 * Write EEPROM OEM name at words 22 to 29.
9943 */
9944 for (addr = ADV_EEP_DVC_CTL_BEGIN;
9945 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
9946 ushort word;
9947
27c868c2 9948 if (*charfields++) {
51219358
MW		 9949 word = cpu_to_le16(*wbuf);
9950 } else {
9951 word = *wbuf;
27c868c2 9952 }
51219358
MW		 9953 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9954 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9955 ASC_EEP_CMD_WRITE | addr);
9956 AdvWaitEEPCmd(iop_base);
27c868c2 9957 }
51219358 9958 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
27c868c2 9959 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 9960}
9961
9962/*
9963 * Write the EEPROM from 'cfg_buf'.
9964 */
6f039790
GKH		 9965static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
9966 ADVEEP_38C1600_CONFIG *cfg_buf)
1da177e4 9967{
27c868c2 9968 ushort *wbuf;
27c868c2 9969 ushort *charfields;
51219358 9970 ushort addr, chksum;
27c868c2
MW		 9971
9972 wbuf = (ushort *)cfg_buf;
51219358 9973 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
27c868c2
MW		 9974 chksum = 0;
9975
9976 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9977 AdvWaitEEPCmd(iop_base);
9978
9979 /*
9980 * Write EEPROM from word 0 to word 20.
9981 */
9982 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9983 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9984 ushort word;
9985
9986 if (*charfields++) {
9987 word = cpu_to_le16(*wbuf);
9988 } else {
9989 word = *wbuf;
9990 }
9991 chksum += *wbuf; /* Checksum is calculated from word values. */
9992 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9993 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9994 ASC_EEP_CMD_WRITE | addr);
9995 AdvWaitEEPCmd(iop_base);
b009bef6 9996 mdelay(ADV_EEP_DELAY_MS);
27c868c2 9997 }
1da177e4 9998
27c868c2
MW		 9999 /*
10000 * Write EEPROM checksum at word 21.
10001 */
10002 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10003 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10004 AdvWaitEEPCmd(iop_base);
10005 wbuf++;
10006 charfields++;
10007
10008 /*
10009 * Write EEPROM OEM name at words 22 to 29.
10010 */
10011 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10012 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10013 ushort word;
10014
10015 if (*charfields++) {
10016 word = cpu_to_le16(*wbuf);
10017 } else {
10018 word = *wbuf;
10019 }
10020 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10021 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10022 ASC_EEP_CMD_WRITE | addr);
10023 AdvWaitEEPCmd(iop_base);
10024 }
10025 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10026 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10027}
10028
10029/*
51219358
MW		 10030 * Read EEPROM configuration into the specified buffer.
10031 *
10032 * Return a checksum based on the EEPROM configuration read.
1da177e4 10033 */
6f039790
GKH		 10034static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10035 ADVEEP_3550_CONFIG *cfg_buf)
1da177e4 10036{
51219358 10037 ushort wval, chksum;
27c868c2 10038 ushort *wbuf;
51219358 10039 int eep_addr;
27c868c2 10040 ushort *charfields;
27c868c2 10041
51219358 10042 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
27c868c2 10043 wbuf = (ushort *)cfg_buf;
27c868c2
MW		 10044 chksum = 0;
10045
51219358
MW		 10046 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10047 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10048 wval = AdvReadEEPWord(iop_base, eep_addr);
10049 chksum += wval; /* Checksum is calculated from word values. */
10050 if (*charfields++) {
10051 *wbuf = le16_to_cpu(wval);
10052 } else {
10053 *wbuf = wval;
10054 }
10055 }
10056 /* Read checksum word. */
10057 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10058 wbuf++;
10059 charfields++;
27c868c2 10060
51219358
MW		 10061 /* Read rest of EEPROM not covered by the checksum. */
10062 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10063 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10064 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10065 if (*charfields++) {
10066 *wbuf = le16_to_cpu(*wbuf);
10067 }
10068 }
10069 return chksum;
10070}
10071
10072/*
10073 * Read EEPROM configuration into the specified buffer.
10074 *
10075 * Return a checksum based on the EEPROM configuration read.
10076 */
6f039790
GKH		 10077static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10078 ADVEEP_38C0800_CONFIG *cfg_buf)
51219358
MW		 10079{
10080 ushort wval, chksum;
10081 ushort *wbuf;
10082 int eep_addr;
10083 ushort *charfields;
27c868c2 10084
51219358
MW		 10085 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10086 wbuf = (ushort *)cfg_buf;
10087 chksum = 0;
10088
10089 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10090 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10091 wval = AdvReadEEPWord(iop_base, eep_addr);
10092 chksum += wval; /* Checksum is calculated from word values. */
27c868c2 10093 if (*charfields++) {
51219358 10094 *wbuf = le16_to_cpu(wval);
27c868c2 10095 } else {
51219358 10096 *wbuf = wval;
27c868c2 10097 }
27c868c2 10098 }
51219358
MW		 10099 /* Read checksum word. */
10100 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2
MW		 10101 wbuf++;
10102 charfields++;
10103
51219358
MW		 10104 /* Read rest of EEPROM not covered by the checksum. */
10105 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10106 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10107 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2 10108 if (*charfields++) {
51219358 10109 *wbuf = le16_to_cpu(*wbuf);
27c868c2 10110 }
27c868c2 10111 }
51219358 10112 return chksum;
1da177e4
LT		 10113}
10114
10115/*
51219358
MW		 10116 * Read EEPROM configuration into the specified buffer.
10117 *
10118 * Return a checksum based on the EEPROM configuration read.
1da177e4 10119 */
6f039790
GKH		 10120static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10121 ADVEEP_38C1600_CONFIG *cfg_buf)
1da177e4 10122{
51219358 10123 ushort wval, chksum;
27c868c2 10124 ushort *wbuf;
51219358 10125 int eep_addr;
27c868c2 10126 ushort *charfields;
27c868c2 10127
27c868c2 10128 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
51219358 10129 wbuf = (ushort *)cfg_buf;
27c868c2
MW		 10130 chksum = 0;
10131
51219358
MW		 10132 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10133 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10134 wval = AdvReadEEPWord(iop_base, eep_addr);
10135 chksum += wval; /* Checksum is calculated from word values. */
27c868c2 10136 if (*charfields++) {
51219358 10137 *wbuf = le16_to_cpu(wval);
27c868c2 10138 } else {
51219358 10139 *wbuf = wval;
27c868c2 10140 }
27c868c2 10141 }
51219358
MW		 10142 /* Read checksum word. */
10143 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2
MW		 10144 wbuf++;
10145 charfields++;
10146
51219358
MW		 10147 /* Read rest of EEPROM not covered by the checksum. */
10148 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10149 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10150 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2 10151 if (*charfields++) {
51219358 10152 *wbuf = le16_to_cpu(*wbuf);
27c868c2 10153 }
27c868c2 10154 }
51219358 10155 return chksum;
1da177e4
LT		 10156}
10157
1da177e4 10158/*
51219358
MW		 10159 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10160 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10161 * all of this is done.
1da177e4 10162 *
51219358 10163 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10164 *
51219358
MW		 10165 * For a non-fatal error return a warning code. If there are no warnings
10166 * then 0 is returned.
1da177e4 10167 *
51219358 10168 * Note: Chip is stopped on entry.
1da177e4 10169 */
6f039790 10170static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10171{
27c868c2 10172 AdvPortAddr iop_base;
51219358
MW		 10173 ushort warn_code;
10174 ADVEEP_3550_CONFIG eep_config;
1da177e4 10175
27c868c2 10176 iop_base = asc_dvc->iop_base;
1da177e4 10177
51219358 10178 warn_code = 0;
27c868c2
MW		 10179
10180 /*
51219358
MW		 10181 * Read the board's EEPROM configuration.
10182 *
10183 * Set default values if a bad checksum is found.
27c868c2 10184 */
51219358
MW		 10185 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10186 warn_code |= ASC_WARN_EEPROM_CHKSUM;
27c868c2 10187
51219358
MW		 10188 /*
10189 * Set EEPROM default values.
10190 */
10191 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10192 sizeof(ADVEEP_3550_CONFIG));
27c868c2 10193
51219358
MW		 10194 /*
10195 * Assume the 6 byte board serial number that was read from
10196 * EEPROM is correct even if the EEPROM checksum failed.
10197 */
10198 eep_config.serial_number_word3 =
10199 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
27c868c2 10200
51219358
MW		 10201 eep_config.serial_number_word2 =
10202 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
27c868c2 10203
51219358
MW		 10204 eep_config.serial_number_word1 =
10205 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
27c868c2 10206
51219358
MW		 10207 AdvSet3550EEPConfig(iop_base, &eep_config);
10208 }
10209 /*
10210 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10211 * EEPROM configuration that was read.
10212 *
10213 * This is the mapping of EEPROM fields to Adv Library fields.
10214 */
10215 asc_dvc->wdtr_able = eep_config.wdtr_able;
10216 asc_dvc->sdtr_able = eep_config.sdtr_able;
10217 asc_dvc->ultra_able = eep_config.ultra_able;
10218 asc_dvc->tagqng_able = eep_config.tagqng_able;
10219 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10220 asc_dvc->max_host_qng = eep_config.max_host_qng;
10221 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10222 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10223 asc_dvc->start_motor = eep_config.start_motor;
10224 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10225 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10226 asc_dvc->no_scam = eep_config.scam_tolerant;
10227 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10228 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10229 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
27c868c2 10230
27c868c2 10231 /*
51219358
MW		 10232 * Set the host maximum queuing (max. 253, min. 16) and the per device
10233 * maximum queuing (max. 63, min. 4).
27c868c2 10234 */
51219358
MW		 10235 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10236 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10237 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10238 /* If the value is zero, assume it is uninitialized. */
10239 if (eep_config.max_host_qng == 0) {
10240 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10241 } else {
10242 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10243 }
10244 }
10245
10246 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10247 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10248 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10249 /* If the value is zero, assume it is uninitialized. */
10250 if (eep_config.max_dvc_qng == 0) {
10251 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10252 } else {
10253 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10254 }
10255 }
27c868c2
MW		 10256
10257 /*
51219358
MW		 10258 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10259 * set 'max_dvc_qng' to 'max_host_qng'.
27c868c2 10260 */
51219358
MW		 10261 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10262 eep_config.max_dvc_qng = eep_config.max_host_qng;
10263 }
27c868c2
MW		 10264
10265 /*
51219358
MW		 10266 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10267 * values based on possibly adjusted EEPROM values.
27c868c2 10268 */
51219358
MW		 10269 asc_dvc->max_host_qng = eep_config.max_host_qng;
10270 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
27c868c2
MW		 10271
10272 /*
51219358
MW		 10273 * If the EEPROM 'termination' field is set to automatic (0), then set
10274 * the ADV_DVC_CFG 'termination' field to automatic also.
10275 *
10276 * If the termination is specified with a non-zero 'termination'
10277 * value check that a legal value is set and set the ADV_DVC_CFG
10278 * 'termination' field appropriately.
27c868c2 10279 */
51219358
MW		 10280 if (eep_config.termination == 0) {
10281 asc_dvc->cfg->termination = 0; /* auto termination */
10282 } else {
10283 /* Enable manual control with low off / high off. */
10284 if (eep_config.termination == 1) {
10285 asc_dvc->cfg->termination = TERM_CTL_SEL;
27c868c2 10286
51219358
MW		 10287 /* Enable manual control with low off / high on. */
10288 } else if (eep_config.termination == 2) {
10289 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10290
10291 /* Enable manual control with low on / high on. */
10292 } else if (eep_config.termination == 3) {
10293 asc_dvc->cfg->termination =
10294 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10295 } else {
27c868c2 10296 /*
51219358
MW		 10297 * The EEPROM 'termination' field contains a bad value. Use
10298 * automatic termination instead.
27c868c2 10299 */
51219358
MW		 10300 asc_dvc->cfg->termination = 0;
10301 warn_code |= ASC_WARN_EEPROM_TERMINATION;
27c868c2 10302 }
27c868c2 10303 }
1da177e4 10304
51219358 10305 return warn_code;
1da177e4
LT		 10306}
10307
10308/*
51219358
MW		 10309 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10310 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10311 * all of this is done.
1da177e4 10312 *
51219358
MW		 10313 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10314 *
10315 * For a non-fatal error return a warning code. If there are no warnings
10316 * then 0 is returned.
10317 *
10318 * Note: Chip is stopped on entry.
1da177e4 10319 */
6f039790 10320static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10321{
51219358
MW		 10322 AdvPortAddr iop_base;
10323 ushort warn_code;
10324 ADVEEP_38C0800_CONFIG eep_config;
10325 uchar tid, termination;
10326 ushort sdtr_speed = 0;
27c868c2 10327
51219358 10328 iop_base = asc_dvc->iop_base;
1da177e4 10329
51219358 10330 warn_code = 0;
27c868c2
MW		 10331
10332 /*
51219358
MW		 10333 * Read the board's EEPROM configuration.
10334 *
10335 * Set default values if a bad checksum is found.
27c868c2 10336 */
51219358
MW		 10337 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10338 eep_config.check_sum) {
10339 warn_code |= ASC_WARN_EEPROM_CHKSUM;
27c868c2 10340
51219358
MW		 10341 /*
10342 * Set EEPROM default values.
10343 */
10344 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10345 sizeof(ADVEEP_38C0800_CONFIG));
1da177e4 10346
51219358
MW		 10347 /*
10348 * Assume the 6 byte board serial number that was read from
10349 * EEPROM is correct even if the EEPROM checksum failed.
10350 */
10351 eep_config.serial_number_word3 =
10352 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
1da177e4 10353
51219358
MW		 10354 eep_config.serial_number_word2 =
10355 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
27c868c2 10356
51219358
MW		 10357 eep_config.serial_number_word1 =
10358 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
27c868c2 10359
51219358 10360 AdvSet38C0800EEPConfig(iop_base, &eep_config);
27c868c2 10361 }
27c868c2 10362 /*
51219358
MW		 10363 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10364 * EEPROM configuration that was read.
10365 *
10366 * This is the mapping of EEPROM fields to Adv Library fields.
27c868c2 10367 */
51219358
MW		 10368 asc_dvc->wdtr_able = eep_config.wdtr_able;
10369 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10370 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10371 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10372 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10373 asc_dvc->tagqng_able = eep_config.tagqng_able;
10374 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10375 asc_dvc->max_host_qng = eep_config.max_host_qng;
10376 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10377 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10378 asc_dvc->start_motor = eep_config.start_motor;
10379 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10380 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10381 asc_dvc->no_scam = eep_config.scam_tolerant;
10382 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10383 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10384 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
27c868c2
MW		 10385
10386 /*
51219358
MW		 10387 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10388 * are set, then set an 'sdtr_able' bit for it.
27c868c2 10389 */
51219358
MW		 10390 asc_dvc->sdtr_able = 0;
10391 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10392 if (tid == 0) {
10393 sdtr_speed = asc_dvc->sdtr_speed1;
10394 } else if (tid == 4) {
10395 sdtr_speed = asc_dvc->sdtr_speed2;
10396 } else if (tid == 8) {
10397 sdtr_speed = asc_dvc->sdtr_speed3;
10398 } else if (tid == 12) {
10399 sdtr_speed = asc_dvc->sdtr_speed4;
10400 }
10401 if (sdtr_speed & ADV_MAX_TID) {
10402 asc_dvc->sdtr_able |= (1 << tid);
10403 }
10404 sdtr_speed >>= 4;
10405 }
27c868c2
MW		 10406
10407 /*
51219358
MW		 10408 * Set the host maximum queuing (max. 253, min. 16) and the per device
10409 * maximum queuing (max. 63, min. 4).
27c868c2 10410 */
51219358
MW		 10411 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10412 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10413 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10414 /* If the value is zero, assume it is uninitialized. */
10415 if (eep_config.max_host_qng == 0) {
10416 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10417 } else {
10418 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10419 }
27c868c2 10420 }
1da177e4 10421
51219358
MW		 10422 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10423 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10424 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10425 /* If the value is zero, assume it is uninitialized. */
10426 if (eep_config.max_dvc_qng == 0) {
10427 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10428 } else {
10429 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10430 }
10431 }
10432
10433 /*
10434 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10435 * set 'max_dvc_qng' to 'max_host_qng'.
10436 */
10437 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10438 eep_config.max_dvc_qng = eep_config.max_host_qng;
27c868c2 10439 }
1da177e4 10440
27c868c2 10441 /*
51219358
MW		 10442 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10443 * values based on possibly adjusted EEPROM values.
27c868c2 10444 */
51219358
MW		 10445 asc_dvc->max_host_qng = eep_config.max_host_qng;
10446 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
27c868c2
MW		 10447
10448 /*
51219358
MW		 10449 * If the EEPROM 'termination' field is set to automatic (0), then set
10450 * the ADV_DVC_CFG 'termination' field to automatic also.
10451 *
10452 * If the termination is specified with a non-zero 'termination'
10453 * value check that a legal value is set and set the ADV_DVC_CFG
10454 * 'termination' field appropriately.
27c868c2 10455 */
51219358
MW		 10456 if (eep_config.termination_se == 0) {
10457 termination = 0; /* auto termination for SE */
10458 } else {
10459 /* Enable manual control with low off / high off. */
10460 if (eep_config.termination_se == 1) {
10461 termination = 0;
10462
10463 /* Enable manual control with low off / high on. */
10464 } else if (eep_config.termination_se == 2) {
10465 termination = TERM_SE_HI;
10466
10467 /* Enable manual control with low on / high on. */
10468 } else if (eep_config.termination_se == 3) {
10469 termination = TERM_SE;
10470 } else {
10471 /*
10472 * The EEPROM 'termination_se' field contains a bad value.
10473 * Use automatic termination instead.
10474 */
10475 termination = 0;
10476 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10477 }
27c868c2 10478 }
51219358
MW		 10479
10480 if (eep_config.termination_lvd == 0) {
10481 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10482 } else {
10483 /* Enable manual control with low off / high off. */
10484 if (eep_config.termination_lvd == 1) {
10485 asc_dvc->cfg->termination = termination;
10486
10487 /* Enable manual control with low off / high on. */
10488 } else if (eep_config.termination_lvd == 2) {
10489 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10490
10491 /* Enable manual control with low on / high on. */
10492 } else if (eep_config.termination_lvd == 3) {
10493 asc_dvc->cfg->termination = termination | TERM_LVD;
10494 } else {
10495 /*
10496 * The EEPROM 'termination_lvd' field contains a bad value.
10497 * Use automatic termination instead.
10498 */
10499 asc_dvc->cfg->termination = termination;
10500 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10501 }
27c868c2 10502 }
1da177e4 10503
51219358 10504 return warn_code;
1da177e4
LT		 10505}
10506
10507/*
51219358
MW		 10508 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10509 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10510 * all of this is done.
1da177e4 10511 *
51219358 10512 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10513 *
51219358
MW		 10514 * For a non-fatal error return a warning code. If there are no warnings
10515 * then 0 is returned.
1da177e4 10516 *
51219358 10517 * Note: Chip is stopped on entry.
1da177e4 10518 */
6f039790 10519static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10520{
27c868c2 10521 AdvPortAddr iop_base;
51219358
MW		 10522 ushort warn_code;
10523 ADVEEP_38C1600_CONFIG eep_config;
10524 uchar tid, termination;
10525 ushort sdtr_speed = 0;
1da177e4 10526
27c868c2
MW		 10527 iop_base = asc_dvc->iop_base;
10528
51219358 10529 warn_code = 0;
27c868c2 10530
51219358
MW		 10531 /*
10532 * Read the board's EEPROM configuration.
10533 *
10534 * Set default values if a bad checksum is found.
10535 */
10536 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10537 eep_config.check_sum) {
10538 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10539 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10540
10541 /*
10542 * Set EEPROM default values.
10543 */
10544 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10545 sizeof(ADVEEP_38C1600_CONFIG));
10546
10547 if (PCI_FUNC(pdev->devfn) != 0) {
10548 u8 ints;
10549 /*
10550 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10551 * and old Mac system booting problem. The Expansion
10552 * ROM must be disabled in Function 1 for these systems
10553 */
10554 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10555 /*
10556 * Clear the INTAB (bit 11) if the GPIO 0 input
10557 * indicates the Function 1 interrupt line is wired
10558 * to INTB.
10559 *
10560 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10561 * 1 - Function 1 interrupt line wired to INT A.
10562 * 0 - Function 1 interrupt line wired to INT B.
10563 *
10564 * Note: Function 0 is always wired to INTA.
10565 * Put all 5 GPIO bits in input mode and then read
10566 * their input values.
10567 */
10568 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10569 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10570 if ((ints & 0x01) == 0)
10571 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10572 }
10573
10574 /*
10575 * Assume the 6 byte board serial number that was read from
10576 * EEPROM is correct even if the EEPROM checksum failed.
10577 */
10578 eep_config.serial_number_word3 =
10579 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10580 eep_config.serial_number_word2 =
10581 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10582 eep_config.serial_number_word1 =
10583 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10584
10585 AdvSet38C1600EEPConfig(iop_base, &eep_config);
27c868c2
MW		 10586 }
10587
10588 /*
51219358
MW		 10589 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10590 * EEPROM configuration that was read.
10591 *
10592 * This is the mapping of EEPROM fields to Adv Library fields.
27c868c2 10593 */
51219358
MW		 10594 asc_dvc->wdtr_able = eep_config.wdtr_able;
10595 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10596 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10597 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10598 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10599 asc_dvc->ppr_able = 0;
10600 asc_dvc->tagqng_able = eep_config.tagqng_able;
10601 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10602 asc_dvc->max_host_qng = eep_config.max_host_qng;
10603 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10604 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10605 asc_dvc->start_motor = eep_config.start_motor;
10606 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10607 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10608 asc_dvc->no_scam = eep_config.scam_tolerant;
27c868c2 10609
51219358
MW		 10610 /*
10611 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10612 * are set, then set an 'sdtr_able' bit for it.
10613 */
10614 asc_dvc->sdtr_able = 0;
10615 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10616 if (tid == 0) {
10617 sdtr_speed = asc_dvc->sdtr_speed1;
10618 } else if (tid == 4) {
10619 sdtr_speed = asc_dvc->sdtr_speed2;
10620 } else if (tid == 8) {
10621 sdtr_speed = asc_dvc->sdtr_speed3;
10622 } else if (tid == 12) {
10623 sdtr_speed = asc_dvc->sdtr_speed4;
10624 }
10625 if (sdtr_speed & ASC_MAX_TID) {
10626 asc_dvc->sdtr_able |= (1 << tid);
10627 }
10628 sdtr_speed >>= 4;
10629 }
27c868c2 10630
51219358
MW		 10631 /*
10632 * Set the host maximum queuing (max. 253, min. 16) and the per device
10633 * maximum queuing (max. 63, min. 4).
10634 */
10635 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10636 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10637 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10638 /* If the value is zero, assume it is uninitialized. */
10639 if (eep_config.max_host_qng == 0) {
10640 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10641 } else {
10642 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
27c868c2 10643 }
51219358 10644 }
27c868c2 10645
51219358
MW		 10646 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10647 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10648 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10649 /* If the value is zero, assume it is uninitialized. */
10650 if (eep_config.max_dvc_qng == 0) {
10651 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10652 } else {
10653 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10654 }
10655 }
10656
10657 /*
10658 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10659 * set 'max_dvc_qng' to 'max_host_qng'.
10660 */
10661 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10662 eep_config.max_dvc_qng = eep_config.max_host_qng;
27c868c2
MW		 10663 }
10664
10665 /*
51219358
MW		 10666 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10667 * values based on possibly adjusted EEPROM values.
10668 */
10669 asc_dvc->max_host_qng = eep_config.max_host_qng;
10670 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10671
10672 /*
10673 * If the EEPROM 'termination' field is set to automatic (0), then set
10674 * the ASC_DVC_CFG 'termination' field to automatic also.
10675 *
10676 * If the termination is specified with a non-zero 'termination'
10677 * value check that a legal value is set and set the ASC_DVC_CFG
10678 * 'termination' field appropriately.
27c868c2 10679 */
51219358
MW		 10680 if (eep_config.termination_se == 0) {
10681 termination = 0; /* auto termination for SE */
10682 } else {
10683 /* Enable manual control with low off / high off. */
10684 if (eep_config.termination_se == 1) {
10685 termination = 0;
27c868c2 10686
51219358
MW		 10687 /* Enable manual control with low off / high on. */
10688 } else if (eep_config.termination_se == 2) {
10689 termination = TERM_SE_HI;
27c868c2 10690
51219358
MW		 10691 /* Enable manual control with low on / high on. */
10692 } else if (eep_config.termination_se == 3) {
10693 termination = TERM_SE;
10694 } else {
10695 /*
10696 * The EEPROM 'termination_se' field contains a bad value.
10697 * Use automatic termination instead.
10698 */
10699 termination = 0;
10700 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10701 }
10702 }
27c868c2 10703
51219358
MW		 10704 if (eep_config.termination_lvd == 0) {
10705 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10706 } else {
10707 /* Enable manual control with low off / high off. */
10708 if (eep_config.termination_lvd == 1) {
10709 asc_dvc->cfg->termination = termination;
27c868c2 10710
51219358
MW		 10711 /* Enable manual control with low off / high on. */
10712 } else if (eep_config.termination_lvd == 2) {
10713 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
27c868c2 10714
51219358
MW		 10715 /* Enable manual control with low on / high on. */
10716 } else if (eep_config.termination_lvd == 3) {
10717 asc_dvc->cfg->termination = termination | TERM_LVD;
10718 } else {
10719 /*
10720 * The EEPROM 'termination_lvd' field contains a bad value.
10721 * Use automatic termination instead.
10722 */
10723 asc_dvc->cfg->termination = termination;
10724 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10725 }
27c868c2 10726 }
51219358
MW		 10727
10728 return warn_code;
1da177e4
LT		 10729}
10730
10731/*
51219358 10732 * Initialize the ADV_DVC_VAR structure.
1da177e4 10733 *
51219358 10734 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10735 *
51219358
MW		 10736 * For a non-fatal error return a warning code. If there are no warnings
10737 * then 0 is returned.
1da177e4 10738 */
6f039790 10739static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
1da177e4 10740{
9d0e96eb
MW		 10741 struct asc_board *board = shost_priv(shost);
10742 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
51219358
MW		 10743 unsigned short warn_code = 0;
10744 AdvPortAddr iop_base = asc_dvc->iop_base;
10745 u16 cmd;
10746 int status;
27c868c2 10747
51219358 10748 asc_dvc->err_code = 0;
27c868c2
MW		 10749
10750 /*
51219358
MW		 10751 * Save the state of the PCI Configuration Command Register
10752 * "Parity Error Response Control" Bit. If the bit is clear (0),
10753 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
10754 * DMA parity errors.
27c868c2 10755 */
51219358
MW		 10756 asc_dvc->cfg->control_flag = 0;
10757 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
10758 if ((cmd & PCI_COMMAND_PARITY) == 0)
10759 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
27c868c2 10760
51219358
MW		 10761 asc_dvc->cfg->chip_version =
10762 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
10763
b352f923 10764 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
51219358
MW		 10765 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
10766 (ushort)ADV_CHIP_ID_BYTE);
10767
b352f923 10768 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
51219358
MW		 10769 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
10770 (ushort)ADV_CHIP_ID_WORD);
27c868c2
MW		 10771
10772 /*
51219358 10773 * Reset the chip to start and allow register writes.
27c868c2 10774 */
51219358
MW		 10775 if (AdvFindSignature(iop_base) == 0) {
10776 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
10777 return ADV_ERROR;
10778 } else {
27c868c2 10779 /*
51219358 10780 * The caller must set 'chip_type' to a valid setting.
27c868c2 10781 */
51219358
MW		 10782 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
10783 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
10784 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
10785 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
10786 return ADV_ERROR;
10787 }
1da177e4 10788
51219358
MW		 10789 /*
10790 * Reset Chip.
10791 */
10792 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
10793 ADV_CTRL_REG_CMD_RESET);
10794 mdelay(100);
10795 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
10796 ADV_CTRL_REG_CMD_WR_IO_REG);
10797
10798 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
10799 status = AdvInitFrom38C1600EEP(asc_dvc);
10800 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
10801 status = AdvInitFrom38C0800EEP(asc_dvc);
10802 } else {
10803 status = AdvInitFrom3550EEP(asc_dvc);
27c868c2 10804 }
51219358 10805 warn_code |= status;
27c868c2 10806 }
1da177e4 10807
9d0e96eb
MW		 10808 if (warn_code != 0)
10809 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
51219358 10810
9d0e96eb
MW		 10811 if (asc_dvc->err_code)
10812 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
10813 asc_dvc->err_code);
51219358
MW		 10814
10815 return asc_dvc->err_code;
1da177e4 10816}
51219358
MW		 10817#endif
10818
10819static struct scsi_host_template advansys_template = {
10820 .proc_name = DRV_NAME,
10821#ifdef CONFIG_PROC_FS
b59fb6fd 10822 .show_info = advansys_show_info,
51219358
MW		 10823#endif
10824 .name = DRV_NAME,
10825 .info = advansys_info,
10826 .queuecommand = advansys_queuecommand,
eac0b0c7 10827 .eh_host_reset_handler = advansys_reset,
51219358
MW		 10828 .bios_param = advansys_biosparam,
10829 .slave_configure = advansys_slave_configure,
10830 /*
10831 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
10832 * must be set. The flag will be cleared in advansys_board_found
10833 * for non-ISA adapters.
10834 */
ae26759e 10835 .unchecked_isa_dma = true,
51219358
MW		 10836 /*
10837 * All adapters controlled by this driver are capable of large
10838 * scatter-gather lists. According to the mid-level SCSI documentation
10839 * this obviates any performance gain provided by setting
10840 * 'use_clustering'. But empirically while CPU utilization is increased
10841 * by enabling clustering, I/O throughput increases as well.
10842 */
10843 .use_clustering = ENABLE_CLUSTERING,
9c17c62a 10844 .use_blk_tags = 1,
51219358 10845};
1da177e4 10846
6f039790 10847static int advansys_wide_init_chip(struct Scsi_Host *shost)
b2c16f58 10848{
9d0e96eb
MW		 10849 struct asc_board *board = shost_priv(shost);
10850 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
0ce53822 10851 size_t sgblk_pool_size;
b2c16f58
MW		 10852 int warn_code, err_code;
10853
10854 /*
10855 * Allocate buffer carrier structures. The total size
98b96a7d 10856 * is about 8 KB, so allocate all at once.
b2c16f58 10857 */
98b96a7d
HR		 10858 adv_dvc->carrier = dma_alloc_coherent(board->dev,
10859 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
10860 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
b2c16f58 10861
98b96a7d 10862 if (!adv_dvc->carrier)
b2c16f58
MW		 10863 goto kmalloc_failed;
10864
10865 /*
10866 * Allocate up to 'max_host_qng' request structures for the Wide
10867 * board. The total size is about 16 KB, so allocate all at once.
10868 * If the allocation fails decrement and try again.
10869 */
4b47e464
HR		 10870 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
10871 if (board->adv_reqp_size & 0x1f) {
10872 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
10873 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
b2c16f58 10874 }
4b47e464
HR		 10875 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
10876 &board->adv_reqp_addr, GFP_KERNEL);
b2c16f58 10877
4b47e464 10878 if (!board->adv_reqp)
b2c16f58
MW		 10879 goto kmalloc_failed;
10880
4b47e464
HR		 10881 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
10882 adv_dvc->max_host_qng, board->adv_reqp_size);
b2c16f58
MW		 10883
10884 /*
10885 * Allocate up to ADV_TOT_SG_BLOCK request structures for
10886 * the Wide board. Each structure is about 136 bytes.
10887 */
0ce53822
HR		 10888 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK;
10889 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev,
10890 sgblk_pool_size, 32, 0);
b2c16f58 10891
0ce53822
HR		 10892 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK,
10893 sizeof(adv_sgblk_t), sgblk_pool_size);
b2c16f58 10894
0ce53822 10895 if (!board->adv_sgblk_pool)
b2c16f58
MW		 10896 goto kmalloc_failed;
10897
9d0e96eb 10898 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
b352f923 10899 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
9d0e96eb
MW		 10900 warn_code = AdvInitAsc3550Driver(adv_dvc);
10901 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
b352f923 10902 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
9d0e96eb 10903 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
b2c16f58 10904 } else {
b352f923 10905 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
9d0e96eb 10906 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
b2c16f58 10907 }
9d0e96eb 10908 err_code = adv_dvc->err_code;
b2c16f58
MW		 10909
10910 if (warn_code || err_code) {
9d0e96eb
MW		 10911 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
10912 "0x%x\n", warn_code, err_code);
b2c16f58
MW		 10913 }
10914
10915 goto exit;
10916
10917 kmalloc_failed:
9d0e96eb 10918 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
b2c16f58
MW		 10919 err_code = ADV_ERROR;
10920 exit:
10921 return err_code;
10922}
10923
98d41c29 10924static void advansys_wide_free_mem(struct asc_board *board)
b2c16f58 10925{
98d41c29 10926 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
98b96a7d
HR		 10927
10928 if (adv_dvc->carrier) {
10929 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
10930 adv_dvc->carrier, adv_dvc->carrier_addr);
10931 adv_dvc->carrier = NULL;
10932 }
4b47e464
HR		 10933 if (board->adv_reqp) {
10934 dma_free_coherent(board->dev, board->adv_reqp_size,
10935 board->adv_reqp, board->adv_reqp_addr);
10936 board->adv_reqp = NULL;
10937 }
0ce53822
HR		 10938 if (board->adv_sgblk_pool) {
10939 dma_pool_destroy(board->adv_sgblk_pool);
10940 board->adv_sgblk_pool = NULL;
b2c16f58
MW		 10941 }
10942}
10943
6f039790
GKH		 10944static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
10945 int bus_type)
27c868c2 10946{
d361db48 10947 struct pci_dev *pdev;
d2411495 10948 struct asc_board *boardp = shost_priv(shost);
27c868c2
MW		 10949 ASC_DVC_VAR *asc_dvc_varp = NULL;
10950 ADV_DVC_VAR *adv_dvc_varp = NULL;
d361db48 10951 int share_irq, warn_code, ret;
27c868c2 10952
d361db48 10953 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
27c868c2
MW		 10954
10955 if (ASC_NARROW_BOARD(boardp)) {
b352f923 10956 ASC_DBG(1, "narrow board\n");
27c868c2
MW		 10957 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
10958 asc_dvc_varp->bus_type = bus_type;
10959 asc_dvc_varp->drv_ptr = boardp;
10960 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
27c868c2 10961 asc_dvc_varp->iop_base = iop;
27c868c2 10962 } else {
57ba5fe9 10963#ifdef CONFIG_PCI
27c868c2
MW		 10964 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
10965 adv_dvc_varp->drv_ptr = boardp;
10966 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
27c868c2 10967 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
b352f923 10968 ASC_DBG(1, "wide board ASC-3550\n");
27c868c2
MW		 10969 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
10970 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
b352f923 10971 ASC_DBG(1, "wide board ASC-38C0800\n");
27c868c2
MW		 10972 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
10973 } else {
b352f923 10974 ASC_DBG(1, "wide board ASC-38C1600\n");
27c868c2
MW		 10975 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
10976 }
27c868c2 10977
57ba5fe9 10978 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
25729a7f 10979 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
57ba5fe9 10980 if (!boardp->ioremap_addr) {
9d511a4b 10981 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
9d0e96eb 10982 "returned NULL\n",
9d511a4b 10983 (long)pci_resource_start(pdev, 1),
9d0e96eb 10984 boardp->asc_n_io_port);
d361db48 10985 ret = -ENODEV;
b2c16f58 10986 goto err_shost;
27c868c2 10987 }
b352f923
MW		 10988 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
10989 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
27c868c2
MW		 10990
10991 /*
10992 * Even though it isn't used to access wide boards, other
10993 * than for the debug line below, save I/O Port address so
10994 * that it can be reported.
10995 */
10996 boardp->ioport = iop;
10997
b352f923
MW		 10998 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
10999 (ushort)inp(iop + 1), (ushort)inpw(iop));
57ba5fe9 11000#endif /* CONFIG_PCI */
27c868c2
MW		 11001 }
11002
27c868c2 11003 if (ASC_NARROW_BOARD(boardp)) {
27c868c2
MW		 11004 /*
11005 * Set the board bus type and PCI IRQ before
11006 * calling AscInitGetConfig().
11007 */
11008 switch (asc_dvc_varp->bus_type) {
11009#ifdef CONFIG_ISA
11010 case ASC_IS_ISA:
ae26759e 11011 shost->unchecked_isa_dma = true;
074c8fe4 11012 share_irq = 0;
27c868c2
MW		 11013 break;
11014 case ASC_IS_VL:
ae26759e 11015 shost->unchecked_isa_dma = false;
074c8fe4 11016 share_irq = 0;
27c868c2
MW		 11017 break;
11018 case ASC_IS_EISA:
ae26759e 11019 shost->unchecked_isa_dma = false;
074c8fe4 11020 share_irq = IRQF_SHARED;
27c868c2
MW		 11021 break;
11022#endif /* CONFIG_ISA */
11023#ifdef CONFIG_PCI
11024 case ASC_IS_PCI:
ae26759e 11025 shost->unchecked_isa_dma = false;
074c8fe4 11026 share_irq = IRQF_SHARED;
27c868c2
MW		 11027 break;
11028#endif /* CONFIG_PCI */
11029 default:
9d0e96eb
MW		 11030 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11031 "%d\n", asc_dvc_varp->bus_type);
ae26759e 11032 shost->unchecked_isa_dma = false;
074c8fe4 11033 share_irq = 0;
27c868c2
MW		 11034 break;
11035 }
27c868c2 11036
27c868c2
MW		 11037 /*
11038 * NOTE: AscInitGetConfig() may change the board's
11039 * bus_type value. The bus_type value should no
11040 * longer be used. If the bus_type field must be
11041 * referenced only use the bit-wise AND operator "&".
11042 */
b352f923 11043 ASC_DBG(2, "AscInitGetConfig()\n");
9d0e96eb 11044 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
27c868c2 11045 } else {
c2dce2fa
MW		 11046#ifdef CONFIG_PCI
11047 /*
11048 * For Wide boards set PCI information before calling
11049 * AdvInitGetConfig().
11050 */
ae26759e 11051 shost->unchecked_isa_dma = false;
c2dce2fa 11052 share_irq = IRQF_SHARED;
b352f923 11053 ASC_DBG(2, "AdvInitGetConfig()\n");
394dbf3f 11054
9d0e96eb 11055 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
c2dce2fa 11056#endif /* CONFIG_PCI */
27c868c2
MW		 11057 }
11058
d361db48 11059 if (ret)
b59fb6fd 11060 goto err_unmap;
27c868c2
MW		 11061
11062 /*
11063 * Save the EEPROM configuration so that it can be displayed
11064 * from /proc/scsi/advansys/[0...].
11065 */
11066 if (ASC_NARROW_BOARD(boardp)) {
11067
11068 ASCEEP_CONFIG *ep;
11069
11070 /*
11071 * Set the adapter's target id bit in the 'init_tidmask' field.
11072 */
11073 boardp->init_tidmask |=
11074 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11075
11076 /*
11077 * Save EEPROM settings for the board.
11078 */
11079 ep = &boardp->eep_config.asc_eep;
11080
11081 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11082 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11083 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11084 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11085 ep->start_motor = asc_dvc_varp->start_motor;
11086 ep->cntl = asc_dvc_varp->dvc_cntl;
11087 ep->no_scam = asc_dvc_varp->no_scam;
11088 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11089 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11090 /* 'max_tag_qng' is set to the same value for every device. */
11091 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11092 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11093 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11094 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11095 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11096 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11097 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11098
11099 /*
11100 * Modify board configuration.
11101 */
b352f923 11102 ASC_DBG(2, "AscInitSetConfig()\n");
9d0e96eb 11103 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
d361db48 11104 if (ret)
b59fb6fd 11105 goto err_unmap;
27c868c2
MW		 11106 } else {
11107 ADVEEP_3550_CONFIG *ep_3550;
11108 ADVEEP_38C0800_CONFIG *ep_38C0800;
11109 ADVEEP_38C1600_CONFIG *ep_38C1600;
11110
11111 /*
11112 * Save Wide EEP Configuration Information.
11113 */
11114 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11115 ep_3550 = &boardp->eep_config.adv_3550_eep;
11116
11117 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11118 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11119 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11120 ep_3550->termination = adv_dvc_varp->cfg->termination;
11121 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11122 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11123 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11124 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11125 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11126 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11127 ep_3550->start_motor = adv_dvc_varp->start_motor;
11128 ep_3550->scsi_reset_delay =
11129 adv_dvc_varp->scsi_reset_wait;
11130 ep_3550->serial_number_word1 =
11131 adv_dvc_varp->cfg->serial1;
11132 ep_3550->serial_number_word2 =
11133 adv_dvc_varp->cfg->serial2;
11134 ep_3550->serial_number_word3 =
11135 adv_dvc_varp->cfg->serial3;
11136 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11137 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11138
11139 ep_38C0800->adapter_scsi_id =
11140 adv_dvc_varp->chip_scsi_id;
11141 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11142 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11143 ep_38C0800->termination_lvd =
11144 adv_dvc_varp->cfg->termination;
11145 ep_38C0800->disc_enable =
11146 adv_dvc_varp->cfg->disc_enable;
11147 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11148 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11149 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11150 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11151 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11152 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11153 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11154 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11155 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11156 ep_38C0800->scsi_reset_delay =
11157 adv_dvc_varp->scsi_reset_wait;
11158 ep_38C0800->serial_number_word1 =
11159 adv_dvc_varp->cfg->serial1;
11160 ep_38C0800->serial_number_word2 =
11161 adv_dvc_varp->cfg->serial2;
11162 ep_38C0800->serial_number_word3 =
11163 adv_dvc_varp->cfg->serial3;
11164 } else {
11165 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11166
11167 ep_38C1600->adapter_scsi_id =
11168 adv_dvc_varp->chip_scsi_id;
11169 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11170 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11171 ep_38C1600->termination_lvd =
11172 adv_dvc_varp->cfg->termination;
11173 ep_38C1600->disc_enable =
11174 adv_dvc_varp->cfg->disc_enable;
11175 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11176 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11177 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11178 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11179 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11180 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11181 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11182 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11183 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11184 ep_38C1600->scsi_reset_delay =
11185 adv_dvc_varp->scsi_reset_wait;
11186 ep_38C1600->serial_number_word1 =
11187 adv_dvc_varp->cfg->serial1;
11188 ep_38C1600->serial_number_word2 =
11189 adv_dvc_varp->cfg->serial2;
11190 ep_38C1600->serial_number_word3 =
11191 adv_dvc_varp->cfg->serial3;
11192 }
11193
11194 /*
11195 * Set the adapter's target id bit in the 'init_tidmask' field.
11196 */
11197 boardp->init_tidmask |=
11198 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
27c868c2
MW		 11199 }
11200
11201 /*
11202 * Channels are numbered beginning with 0. For AdvanSys one host
11203 * structure supports one channel. Multi-channel boards have a
11204 * separate host structure for each channel.
11205 */
11206 shost->max_channel = 0;
11207 if (ASC_NARROW_BOARD(boardp)) {
11208 shost->max_id = ASC_MAX_TID + 1;
11209 shost->max_lun = ASC_MAX_LUN + 1;
f05ec594 11210 shost->max_cmd_len = ASC_MAX_CDB_LEN;
27c868c2
MW		 11211
11212 shost->io_port = asc_dvc_varp->iop_base;
11213 boardp->asc_n_io_port = ASC_IOADR_GAP;
11214 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11215
11216 /* Set maximum number of queues the adapter can handle. */
11217 shost->can_queue = asc_dvc_varp->max_total_qng;
11218 } else {
11219 shost->max_id = ADV_MAX_TID + 1;
11220 shost->max_lun = ADV_MAX_LUN + 1;
f05ec594 11221 shost->max_cmd_len = ADV_MAX_CDB_LEN;
27c868c2
MW		 11222
11223 /*
11224 * Save the I/O Port address and length even though
11225 * I/O ports are not used to access Wide boards.
11226 * Instead the Wide boards are accessed with
11227 * PCI Memory Mapped I/O.
11228 */
11229 shost->io_port = iop;
27c868c2
MW		 11230
11231 shost->this_id = adv_dvc_varp->chip_scsi_id;
11232
11233 /* Set maximum number of queues the adapter can handle. */
11234 shost->can_queue = adv_dvc_varp->max_host_qng;
11235 }
9c17c62a
HR		 11236 ret = scsi_init_shared_tag_map(shost, shost->can_queue);
11237 if (ret) {
11238 shost_printk(KERN_ERR, shost, "init tag map failed\n");
11239 goto err_free_dma;
11240 }
27c868c2 11241
27c868c2
MW		 11242 /*
11243 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11244 * and should be set to zero.
11245 *
11246 * But because of a bug introduced in v1.3.89 if the driver is
11247 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11248 * SCSI function 'allocate_device' will panic. To allow the driver
11249 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11250 *
11251 * Note: This is wrong. cmd_per_lun should be set to the depth
11252 * you want on untagged devices always.
11253 #ifdef MODULE
11254 */
11255 shost->cmd_per_lun = 1;
11256/* #else
11257 shost->cmd_per_lun = 0;
11258#endif */
11259
11260 /*
11261 * Set the maximum number of scatter-gather elements the
11262 * adapter can handle.
11263 */
11264 if (ASC_NARROW_BOARD(boardp)) {
11265 /*
11266 * Allow two commands with 'sg_tablesize' scatter-gather
11267 * elements to be executed simultaneously. This value is
11268 * the theoretical hardware limit. It may be decreased
11269 * below.
11270 */
11271 shost->sg_tablesize =
11272 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11273 ASC_SG_LIST_PER_Q) + 1;
11274 } else {
11275 shost->sg_tablesize = ADV_MAX_SG_LIST;
11276 }
11277
11278 /*
11279 * The value of 'sg_tablesize' can not exceed the SCSI
11280 * mid-level driver definition of SG_ALL. SG_ALL also
11281 * must not be exceeded, because it is used to define the
11282 * size of the scatter-gather table in 'struct asc_sg_head'.
11283 */
11284 if (shost->sg_tablesize > SG_ALL) {
11285 shost->sg_tablesize = SG_ALL;
11286 }
11287
b352f923 11288 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
27c868c2
MW		 11289
11290 /* BIOS start address. */
11291 if (ASC_NARROW_BOARD(boardp)) {
b2c16f58
MW		 11292 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11293 asc_dvc_varp->bus_type);
27c868c2
MW		 11294 } else {
11295 /*
11296 * Fill-in BIOS board variables. The Wide BIOS saves
11297 * information in LRAM that is used by the driver.
11298 */
11299 AdvReadWordLram(adv_dvc_varp->iop_base,
11300 BIOS_SIGNATURE, boardp->bios_signature);
11301 AdvReadWordLram(adv_dvc_varp->iop_base,
11302 BIOS_VERSION, boardp->bios_version);
11303 AdvReadWordLram(adv_dvc_varp->iop_base,
11304 BIOS_CODESEG, boardp->bios_codeseg);
11305 AdvReadWordLram(adv_dvc_varp->iop_base,
11306 BIOS_CODELEN, boardp->bios_codelen);
11307
b352f923 11308 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
27c868c2
MW		 11309 boardp->bios_signature, boardp->bios_version);
11310
b352f923 11311 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
27c868c2
MW		 11312 boardp->bios_codeseg, boardp->bios_codelen);
11313
11314 /*
11315 * If the BIOS saved a valid signature, then fill in
11316 * the BIOS code segment base address.
11317 */
11318 if (boardp->bios_signature == 0x55AA) {
11319 /*
11320 * Convert x86 realmode code segment to a linear
11321 * address by shifting left 4.
11322 */
11323 shost->base = ((ulong)boardp->bios_codeseg << 4);
11324 } else {
11325 shost->base = 0;
11326 }
11327 }
11328
11329 /*
11330 * Register Board Resources - I/O Port, DMA, IRQ
11331 */
11332
27c868c2
MW		 11333 /* Register DMA Channel for Narrow boards. */
11334 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11335#ifdef CONFIG_ISA
11336 if (ASC_NARROW_BOARD(boardp)) {
11337 /* Register DMA channel for ISA bus. */
11338 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11339 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
01fbfe0b 11340 ret = request_dma(shost->dma_channel, DRV_NAME);
b2c16f58 11341 if (ret) {
9d0e96eb
MW		 11342 shost_printk(KERN_ERR, shost, "request_dma() "
11343 "%d failed %d\n",
11344 shost->dma_channel, ret);
b59fb6fd 11345 goto err_unmap;
27c868c2
MW		 11346 }
11347 AscEnableIsaDma(shost->dma_channel);
11348 }
11349 }
11350#endif /* CONFIG_ISA */
11351
11352 /* Register IRQ Number. */
b352f923 11353 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
074c8fe4 11354
d361db48 11355 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
01fbfe0b 11356 DRV_NAME, shost);
074c8fe4
MW		 11357
11358 if (ret) {
27c868c2 11359 if (ret == -EBUSY) {
9d0e96eb
MW		 11360 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11361 "already in use\n", boardp->irq);
27c868c2 11362 } else if (ret == -EINVAL) {
9d0e96eb
MW		 11363 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11364 "not valid\n", boardp->irq);
27c868c2 11365 } else {
9d0e96eb
MW		 11366 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11367 "failed with %d\n", boardp->irq, ret);
27c868c2 11368 }
b2c16f58 11369 goto err_free_dma;
27c868c2
MW		 11370 }
11371
11372 /*
11373 * Initialize board RISC chip and enable interrupts.
11374 */
11375 if (ASC_NARROW_BOARD(boardp)) {
b352f923 11376 ASC_DBG(2, "AscInitAsc1000Driver()\n");
7d5d408c
FT		 11377
11378 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11379 if (!asc_dvc_varp->overrun_buf) {
11380 ret = -ENOMEM;
9a908c1a 11381 goto err_free_irq;
7d5d408c 11382 }
27c868c2 11383 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
27c868c2 11384
d361db48 11385 if (warn_code || asc_dvc_varp->err_code) {
9d0e96eb
MW		 11386 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11387 "warn 0x%x, error 0x%x\n",
11388 asc_dvc_varp->init_state, warn_code,
11389 asc_dvc_varp->err_code);
9a908c1a 11390 if (!asc_dvc_varp->overrun_dma) {
d361db48 11391 ret = -ENODEV;
9a908c1a 11392 goto err_free_mem;
7d5d408c 11393 }
27c868c2
MW		 11394 }
11395 } else {
9a908c1a 11396 if (advansys_wide_init_chip(shost)) {
d361db48 11397 ret = -ENODEV;
9a908c1a
HRK		 11398 goto err_free_mem;
11399 }
27c868c2
MW		 11400 }
11401
27c868c2
MW		 11402 ASC_DBG_PRT_SCSI_HOST(2, shost);
11403
d361db48 11404 ret = scsi_add_host(shost, boardp->dev);
8dfb5379 11405 if (ret)
9a908c1a 11406 goto err_free_mem;
8dfb5379
MW		 11407
11408 scsi_scan_host(shost);
d361db48 11409 return 0;
b2c16f58 11410
9a908c1a
HRK		 11411 err_free_mem:
11412 if (ASC_NARROW_BOARD(boardp)) {
11413 if (asc_dvc_varp->overrun_dma)
11414 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11415 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11416 kfree(asc_dvc_varp->overrun_buf);
11417 } else
11418 advansys_wide_free_mem(boardp);
11419 err_free_irq:
d361db48 11420 free_irq(boardp->irq, shost);
b2c16f58 11421 err_free_dma:
30037818 11422#ifdef CONFIG_ISA
b2c16f58
MW		 11423 if (shost->dma_channel != NO_ISA_DMA)
11424 free_dma(shost->dma_channel);
30037818 11425#endif
b2c16f58
MW		 11426 err_unmap:
11427 if (boardp->ioremap_addr)
11428 iounmap(boardp->ioremap_addr);
11429 err_shost:
d361db48 11430 return ret;
27c868c2
MW		 11431}
11432
27c868c2
MW		 11433/*
11434 * advansys_release()
11435 *
11436 * Release resources allocated for a single AdvanSys adapter.
11437 */
11438static int advansys_release(struct Scsi_Host *shost)
11439{
d10fb2c7 11440 struct asc_board *board = shost_priv(shost);
b352f923 11441 ASC_DBG(1, "begin\n");
8dfb5379 11442 scsi_remove_host(shost);
d10fb2c7 11443 free_irq(board->irq, shost);
30037818 11444#ifdef CONFIG_ISA
27c868c2 11445 if (shost->dma_channel != NO_ISA_DMA) {
b352f923 11446 ASC_DBG(1, "free_dma()\n");
27c868c2
MW		 11447 free_dma(shost->dma_channel);
11448 }
30037818 11449#endif
d10fb2c7
MW		 11450 if (ASC_NARROW_BOARD(board)) {
11451 dma_unmap_single(board->dev,
11452 board->dvc_var.asc_dvc_var.overrun_dma,
11453 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
7d5d408c 11454 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
d10fb2c7
MW		 11455 } else {
11456 iounmap(board->ioremap_addr);
11457 advansys_wide_free_mem(board);
27c868c2 11458 }
8dfb5379 11459 scsi_host_put(shost);
b352f923 11460 ASC_DBG(1, "end\n");
27c868c2
MW		 11461 return 0;
11462}
11463
95c9f162
MW		 11464#define ASC_IOADR_TABLE_MAX_IX 11
11465
747d016e 11466static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
c304ec94
MW		 11467 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11468 0x0210, 0x0230, 0x0250, 0x0330
11469};
11470
d361db48
MW		 11471/*
11472 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11473 * 00: 10
11474 * 01: 11
11475 * 10: 12
11476 * 11: 15
11477 */
6f039790 11478static unsigned int advansys_isa_irq_no(PortAddr iop_base)
d361db48
MW		 11479{
11480 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11481 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11482 if (chip_irq == 13)
11483 chip_irq = 15;
11484 return chip_irq;
11485}
11486
6f039790 11487static int advansys_isa_probe(struct device *dev, unsigned int id)
c304ec94 11488{
d361db48 11489 int err = -ENODEV;
c304ec94
MW		 11490 PortAddr iop_base = _asc_def_iop_base[id];
11491 struct Scsi_Host *shost;
d361db48 11492 struct asc_board *board;
c304ec94 11493
01fbfe0b 11494 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
b352f923 11495 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
c304ec94
MW		 11496 return -ENODEV;
11497 }
b352f923 11498 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
c304ec94 11499 if (!AscFindSignature(iop_base))
d361db48 11500 goto release_region;
c304ec94 11501 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
d361db48 11502 goto release_region;
c304ec94 11503
d361db48
MW		 11504 err = -ENOMEM;
11505 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
c304ec94 11506 if (!shost)
d361db48
MW		 11507 goto release_region;
11508
d2411495 11509 board = shost_priv(shost);
d361db48
MW		 11510 board->irq = advansys_isa_irq_no(iop_base);
11511 board->dev = dev;
9c17c62a 11512 board->shost = shost;
d361db48
MW		 11513
11514 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11515 if (err)
11516 goto free_host;
c304ec94
MW		 11517
11518 dev_set_drvdata(dev, shost);
11519 return 0;
11520
d361db48
MW		 11521 free_host:
11522 scsi_host_put(shost);
11523 release_region:
71f36115 11524 release_region(iop_base, ASC_IOADR_GAP);
d361db48 11525 return err;
c304ec94
MW		 11526}
11527
6f039790 11528static int advansys_isa_remove(struct device *dev, unsigned int id)
c304ec94 11529{
71f36115 11530 int ioport = _asc_def_iop_base[id];
c304ec94 11531 advansys_release(dev_get_drvdata(dev));
71f36115 11532 release_region(ioport, ASC_IOADR_GAP);
c304ec94
MW		 11533 return 0;
11534}
11535
11536static struct isa_driver advansys_isa_driver = {
11537 .probe = advansys_isa_probe,
6f039790 11538 .remove = advansys_isa_remove,
c304ec94
MW		 11539 .driver = {
11540 .owner = THIS_MODULE,
01fbfe0b 11541 .name = DRV_NAME,
c304ec94
MW		 11542 },
11543};
11544
d361db48
MW		 11545/*
11546 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11547 * 000: invalid
11548 * 001: 10
11549 * 010: 11
11550 * 011: 12
11551 * 100: invalid
11552 * 101: 14
11553 * 110: 15
11554 * 111: invalid
11555 */
6f039790 11556static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
d361db48
MW		 11557{
11558 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11559 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11560 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11561 return 0;
11562 return chip_irq;
11563}
11564
6f039790 11565static int advansys_vlb_probe(struct device *dev, unsigned int id)
c304ec94 11566{
d361db48 11567 int err = -ENODEV;
c304ec94
MW		 11568 PortAddr iop_base = _asc_def_iop_base[id];
11569 struct Scsi_Host *shost;
d361db48 11570 struct asc_board *board;
c304ec94 11571
01fbfe0b 11572 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
b352f923 11573 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
c304ec94
MW		 11574 return -ENODEV;
11575 }
b352f923 11576 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
c304ec94 11577 if (!AscFindSignature(iop_base))
d361db48 11578 goto release_region;
c304ec94
MW		 11579 /*
11580 * I don't think this condition can actually happen, but the old
11581 * driver did it, and the chances of finding a VLB setup in 2007
11582 * to do testing with is slight to none.
11583 */
11584 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
d361db48 11585 goto release_region;
c304ec94 11586
d361db48
MW		 11587 err = -ENOMEM;
11588 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
c304ec94 11589 if (!shost)
d361db48
MW		 11590 goto release_region;
11591
d2411495 11592 board = shost_priv(shost);
d361db48
MW		 11593 board->irq = advansys_vlb_irq_no(iop_base);
11594 board->dev = dev;
9c17c62a 11595 board->shost = shost;
d361db48
MW		 11596
11597 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11598 if (err)
11599 goto free_host;
c304ec94
MW		 11600
11601 dev_set_drvdata(dev, shost);
11602 return 0;
11603
d361db48
MW		 11604 free_host:
11605 scsi_host_put(shost);
11606 release_region:
71f36115 11607 release_region(iop_base, ASC_IOADR_GAP);
c304ec94
MW		 11608 return -ENODEV;
11609}
11610
11611static struct isa_driver advansys_vlb_driver = {
11612 .probe = advansys_vlb_probe,
6f039790 11613 .remove = advansys_isa_remove,
c304ec94
MW		 11614 .driver = {
11615 .owner = THIS_MODULE,
b8e5152b 11616 .name = "advansys_vlb",
c304ec94
MW		 11617 },
11618};
11619
6f039790 11620static struct eisa_device_id advansys_eisa_table[] = {
b09e05a7
MW		 11621 { "ABP7401" },
11622 { "ABP7501" },
11623 { "" }
11624};
11625
11626MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11627
11628/*
11629 * EISA is a little more tricky than PCI; each EISA device may have two
11630 * channels, and this driver is written to make each channel its own Scsi_Host
11631 */
11632struct eisa_scsi_data {
11633 struct Scsi_Host *host[2];
11634};
11635
d361db48
MW		 11636/*
11637 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11638 * 000: 10
11639 * 001: 11
11640 * 010: 12
11641 * 011: invalid
11642 * 100: 14
11643 * 101: 15
11644 * 110: invalid
11645 * 111: invalid
11646 */
6f039790 11647static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
d361db48
MW		 11648{
11649 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11650 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11651 if ((chip_irq == 13) || (chip_irq > 15))
11652 return 0;
11653 return chip_irq;
11654}
11655
6f039790 11656static int advansys_eisa_probe(struct device *dev)
b09e05a7 11657{
d361db48 11658 int i, ioport, irq = 0;
b09e05a7
MW		 11659 int err;
11660 struct eisa_device *edev = to_eisa_device(dev);
11661 struct eisa_scsi_data *data;
11662
11663 err = -ENOMEM;
11664 data = kzalloc(sizeof(*data), GFP_KERNEL);
11665 if (!data)
11666 goto fail;
11667 ioport = edev->base_addr + 0xc30;
11668
11669 err = -ENODEV;
11670 for (i = 0; i < 2; i++, ioport += 0x20) {
d361db48
MW		 11671 struct asc_board *board;
11672 struct Scsi_Host *shost;
01fbfe0b 11673 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
71f36115
MW		 11674 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
11675 ioport + ASC_IOADR_GAP - 1);
11676 continue;
11677 }
11678 if (!AscFindSignature(ioport)) {
11679 release_region(ioport, ASC_IOADR_GAP);
b09e05a7 11680 continue;
71f36115
MW		 11681 }
11682
b09e05a7
MW		 11683 /*
11684 * I don't know why we need to do this for EISA chips, but
11685 * not for any others. It looks to be equivalent to
11686 * AscGetChipCfgMsw, but I may have overlooked something,
11687 * so I'm not converting it until I get an EISA board to
11688 * test with.
11689 */
11690 inw(ioport + 4);
d361db48
MW		 11691
11692 if (!irq)
11693 irq = advansys_eisa_irq_no(edev);
11694
11695 err = -ENOMEM;
11696 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11697 if (!shost)
11698 goto release_region;
11699
d2411495 11700 board = shost_priv(shost);
d361db48
MW		 11701 board->irq = irq;
11702 board->dev = dev;
9c17c62a 11703 board->shost = shost;
d361db48
MW		 11704
11705 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
11706 if (!err) {
11707 data->host[i] = shost;
11708 continue;
71f36115 11709 }
b09e05a7 11710
d361db48
MW		 11711 scsi_host_put(shost);
11712 release_region:
11713 release_region(ioport, ASC_IOADR_GAP);
11714 break;
b09e05a7
MW		 11715 }
11716
d361db48
MW		 11717 if (err)
11718 goto free_data;
11719 dev_set_drvdata(dev, data);
11720 return 0;
11721
11722 free_data:
11723 kfree(data->host[0]);
11724 kfree(data->host[1]);
11725 kfree(data);
b09e05a7
MW		 11726 fail:
11727 return err;
11728}
11729
6f039790 11730static int advansys_eisa_remove(struct device *dev)
b09e05a7
MW		 11731{
11732 int i;
11733 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11734
11735 for (i = 0; i < 2; i++) {
71f36115 11736 int ioport;
b09e05a7
MW		 11737 struct Scsi_Host *shost = data->host[i];
11738 if (!shost)
11739 continue;
71f36115 11740 ioport = shost->io_port;
b09e05a7 11741 advansys_release(shost);
71f36115 11742 release_region(ioport, ASC_IOADR_GAP);
b09e05a7
MW		 11743 }
11744
11745 kfree(data);
11746 return 0;
11747}
11748
11749static struct eisa_driver advansys_eisa_driver = {
11750 .id_table = advansys_eisa_table,
11751 .driver = {
01fbfe0b 11752 .name = DRV_NAME,
b09e05a7 11753 .probe = advansys_eisa_probe,
6f039790 11754 .remove = advansys_eisa_remove,
b09e05a7
MW		 11755 }
11756};
11757
2672ea86 11758/* PCI Devices supported by this driver */
6f039790 11759static struct pci_device_id advansys_pci_tbl[] = {
27c868c2
MW		 11760 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
11761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11762 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
11763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11764 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
11765 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11766 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
11767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11768 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
11769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11770 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
11771 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11772 {}
2672ea86 11773};
27c868c2 11774
2672ea86 11775MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
78e77d8b 11776
6f039790 11777static void advansys_set_latency(struct pci_dev *pdev)
9649af39
MW		 11778{
11779 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
11780 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
11781 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
11782 } else {
11783 u8 latency;
11784 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
11785 if (latency < 0x20)
11786 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
11787 }
11788}
11789
6f039790
GKH		 11790static int advansys_pci_probe(struct pci_dev *pdev,
11791 const struct pci_device_id *ent)
78e77d8b
MW		 11792{
11793 int err, ioport;
11794 struct Scsi_Host *shost;
d361db48 11795 struct asc_board *board;
78e77d8b
MW		 11796
11797 err = pci_enable_device(pdev);
11798 if (err)
11799 goto fail;
01fbfe0b 11800 err = pci_request_regions(pdev, DRV_NAME);
71f36115
MW		 11801 if (err)
11802 goto disable_device;
9649af39
MW		 11803 pci_set_master(pdev);
11804 advansys_set_latency(pdev);
78e77d8b 11805
d361db48 11806 err = -ENODEV;
78e77d8b 11807 if (pci_resource_len(pdev, 0) == 0)
d361db48 11808 goto release_region;
78e77d8b
MW		 11809
11810 ioport = pci_resource_start(pdev, 0);
78e77d8b 11811
d361db48
MW		 11812 err = -ENOMEM;
11813 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
78e77d8b 11814 if (!shost)
d361db48
MW		 11815 goto release_region;
11816
d2411495 11817 board = shost_priv(shost);
d361db48
MW		 11818 board->irq = pdev->irq;
11819 board->dev = &pdev->dev;
9c17c62a 11820 board->shost = shost;
d361db48
MW		 11821
11822 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
11823 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
11824 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
11825 board->flags |= ASC_IS_WIDE_BOARD;
11826 }
11827
11828 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
11829 if (err)
11830 goto free_host;
78e77d8b
MW		 11831
11832 pci_set_drvdata(pdev, shost);
11833 return 0;
11834
d361db48
MW		 11835 free_host:
11836 scsi_host_put(shost);
11837 release_region:
71f36115
MW		 11838 pci_release_regions(pdev);
11839 disable_device:
78e77d8b
MW		 11840 pci_disable_device(pdev);
11841 fail:
11842 return err;
11843}
11844
6f039790 11845static void advansys_pci_remove(struct pci_dev *pdev)
78e77d8b
MW		 11846{
11847 advansys_release(pci_get_drvdata(pdev));
71f36115 11848 pci_release_regions(pdev);
78e77d8b
MW		 11849 pci_disable_device(pdev);
11850}
11851
11852static struct pci_driver advansys_pci_driver = {
01fbfe0b 11853 .name = DRV_NAME,
78e77d8b
MW		 11854 .id_table = advansys_pci_tbl,
11855 .probe = advansys_pci_probe,
6f039790 11856 .remove = advansys_pci_remove,
78e77d8b 11857};
8c6af9e1 11858
8dfb5379
MW		 11859static int __init advansys_init(void)
11860{
c304ec94 11861 int error;
b09e05a7 11862
c304ec94
MW		 11863 error = isa_register_driver(&advansys_isa_driver,
11864 ASC_IOADR_TABLE_MAX_IX);
78e77d8b
MW		 11865 if (error)
11866 goto fail;
8dfb5379 11867
c304ec94
MW		 11868 error = isa_register_driver(&advansys_vlb_driver,
11869 ASC_IOADR_TABLE_MAX_IX);
11870 if (error)
11871 goto unregister_isa;
11872
11873 error = eisa_driver_register(&advansys_eisa_driver);
11874 if (error)
11875 goto unregister_vlb;
11876
b09e05a7
MW		 11877 error = pci_register_driver(&advansys_pci_driver);
11878 if (error)
11879 goto unregister_eisa;
11880
8dfb5379 11881 return 0;
78e77d8b 11882
b09e05a7
MW		 11883 unregister_eisa:
11884 eisa_driver_unregister(&advansys_eisa_driver);
c304ec94
MW		 11885 unregister_vlb:
11886 isa_unregister_driver(&advansys_vlb_driver);
11887 unregister_isa:
11888 isa_unregister_driver(&advansys_isa_driver);
78e77d8b 11889 fail:
78e77d8b 11890 return error;
8dfb5379
MW		 11891}
11892
11893static void __exit advansys_exit(void)
11894{
78e77d8b 11895 pci_unregister_driver(&advansys_pci_driver);
b09e05a7 11896 eisa_driver_unregister(&advansys_eisa_driver);
c304ec94
MW		 11897 isa_unregister_driver(&advansys_vlb_driver);
11898 isa_unregister_driver(&advansys_isa_driver);
8dfb5379
MW		 11899}
11900
11901module_init(advansys_init);
11902module_exit(advansys_exit);
11903
8c6af9e1 11904MODULE_LICENSE("GPL");
989bb5f5
JSR		 11905MODULE_FIRMWARE("advansys/mcode.bin");
11906MODULE_FIRMWARE("advansys/3550.bin");
11907MODULE_FIRMWARE("advansys/38C0800.bin");
11908MODULE_FIRMWARE("advansys/38C1600.bin");
Linux 6.x block layer and io_uring tree(s)