[linux-2.6-block.git] / drivers / rtc / rtc-x1205.c

/*
 * An i2c driver for the Xicor/Intersil X1205 RTC
 * Copyright 2004 Karen Spearel
 * Copyright 2005 Alessandro Zummo
 *
 * please send all reports to:
 *	Karen Spearel <kas111 at gmail dot com>
 *	Alessandro Zummo <a.zummo@towertech.it>
 *
 * based on a lot of other RTC drivers.
 *
 * Information and datasheet:
 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/bitops.h>

/* offsets into CCR area */

#define CCR_SEC			0
#define CCR_MIN			1
#define CCR_HOUR		2
#define CCR_MDAY		3
#define CCR_MONTH		4
#define CCR_YEAR		5
#define CCR_WDAY		6
#define CCR_Y2K			7

#define X1205_REG_SR		0x3F	/* status register */
#define X1205_REG_Y2K		0x37
#define X1205_REG_DW		0x36
#define X1205_REG_YR		0x35
#define X1205_REG_MO		0x34
#define X1205_REG_DT		0x33
#define X1205_REG_HR		0x32
#define X1205_REG_MN		0x31
#define X1205_REG_SC		0x30
#define X1205_REG_DTR		0x13
#define X1205_REG_ATR		0x12
#define X1205_REG_INT		0x11
#define X1205_REG_0		0x10
#define X1205_REG_Y2K1		0x0F
#define X1205_REG_DWA1		0x0E
#define X1205_REG_YRA1		0x0D
#define X1205_REG_MOA1		0x0C
#define X1205_REG_DTA1		0x0B
#define X1205_REG_HRA1		0x0A
#define X1205_REG_MNA1		0x09
#define X1205_REG_SCA1		0x08
#define X1205_REG_Y2K0		0x07
#define X1205_REG_DWA0		0x06
#define X1205_REG_YRA0		0x05
#define X1205_REG_MOA0		0x04
#define X1205_REG_DTA0		0x03
#define X1205_REG_HRA0		0x02
#define X1205_REG_MNA0		0x01
#define X1205_REG_SCA0		0x00

#define X1205_CCR_BASE		0x30	/* Base address of CCR */
#define X1205_ALM0_BASE		0x00	/* Base address of ALARM0 */

#define X1205_SR_RTCF		0x01	/* Clock failure */
#define X1205_SR_WEL		0x02	/* Write Enable Latch */
#define X1205_SR_RWEL		0x04	/* Register Write Enable */
#define X1205_SR_AL0		0x20	/* Alarm 0 match */

#define X1205_DTR_DTR0		0x01
#define X1205_DTR_DTR1		0x02
#define X1205_DTR_DTR2		0x04

#define X1205_HR_MIL		0x80	/* Set in ccr.hour for 24 hr mode */

#define X1205_INT_AL0E		0x20	/* Alarm 0 enable */

static struct i2c_driver x1205_driver;

/*
 * In the routines that deal directly with the x1205 hardware, we use
 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
 * Epoch is initialized as 2000. Time is set to UTC.
 */
static int x1205_get_datetime(struct i2c_client *client, struct rtc_time *tm,
				unsigned char reg_base)
{
	unsigned char dt_addr[2] = { 0, reg_base };
	unsigned char buf[8];
	int i;

	struct i2c_msg msgs[] = {
		{/* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = dt_addr
		},
		{/* read date */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 8,
			.buf = buf
		},
	};

	/* read date registers */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev,
		"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
		"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
		__func__,
		buf[0], buf[1], buf[2], buf[3],
		buf[4], buf[5], buf[6], buf[7]);

	/* Mask out the enable bits if these are alarm registers */
	if (reg_base < X1205_CCR_BASE)
		for (i = 0; i <= 4; i++)
			buf[i] &= 0x7F;

	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
	tm->tm_min = bcd2bin(buf[CCR_MIN]);
	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
	tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
	tm->tm_year = bcd2bin(buf[CCR_YEAR])
			+ (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
	tm->tm_wday = buf[CCR_WDAY];

	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
		"mday=%d, mon=%d, year=%d, wday=%d\n",
		__func__,
		tm->tm_sec, tm->tm_min, tm->tm_hour,
		tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	return 0;
}

static int x1205_get_status(struct i2c_client *client, unsigned char *sr)
{
	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };

	struct i2c_msg msgs[] = {
		{     /* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = sr_addr
		},
		{    /* read status */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = sr
		},
	};

	/* read status register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	return 0;
}

static int x1205_set_datetime(struct i2c_client *client, struct rtc_time *tm,
			u8 reg_base, unsigned char alm_enable)
{
	int i, xfer;
	unsigned char rdata[10] = { 0, reg_base };
	unsigned char *buf = rdata + 2;

	static const unsigned char wel[3] = { 0, X1205_REG_SR,
						X1205_SR_WEL };

	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
						X1205_SR_WEL | X1205_SR_RWEL };

	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };

	dev_dbg(&client->dev,
		"%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
		__func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
		tm->tm_mon, tm->tm_year, tm->tm_wday);

	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
	buf[CCR_MIN] = bin2bcd(tm->tm_min);

	/* set hour and 24hr bit */
	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;

	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);

	/* month, 1 - 12 */
	buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);

	/* year, since the rtc epoch*/
	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
	buf[CCR_WDAY] = tm->tm_wday & 0x07;
	buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);

	/* If writing alarm registers, set compare bits on registers 0-4 */
	if (reg_base < X1205_CCR_BASE)
		for (i = 0; i <= 4; i++)
			buf[i] |= 0x80;

	/* this sequence is required to unlock the chip */
	xfer = i2c_master_send(client, wel, 3);
	if (xfer != 3) {
		dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
		return -EIO;
	}

	xfer = i2c_master_send(client, rwel, 3);
	if (xfer != 3) {
		dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
		return -EIO;
	}

	xfer = i2c_master_send(client, rdata, sizeof(rdata));
	if (xfer != sizeof(rdata)) {
		dev_err(&client->dev,
			"%s: result=%d addr=%02x, data=%02x\n",
			__func__,
			 xfer, rdata[1], rdata[2]);
		return -EIO;
	}

	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
	if (reg_base < X1205_CCR_BASE) {
		unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };

		msleep(10);

		/* ...and set or clear the AL0E bit in the INT register */

		/* Need to set RWEL again as the write has cleared it */
		xfer = i2c_master_send(client, rwel, 3);
		if (xfer != 3) {
			dev_err(&client->dev,
				"%s: aloe rwel - %d\n",
				__func__,
				xfer);
			return -EIO;
		}

		if (alm_enable)
			al0e[2] = X1205_INT_AL0E;

		xfer = i2c_master_send(client, al0e, 3);
		if (xfer != 3) {
			dev_err(&client->dev,
				"%s: al0e - %d\n",
				__func__,
				xfer);
			return -EIO;
		}

		/* and wait 10msec again for this write to complete */
		msleep(10);
	}

	/* disable further writes */
	xfer = i2c_master_send(client, diswe, 3);
	if (xfer != 3) {
		dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
		return -EIO;
	}

	return 0;
}

static int x1205_fix_osc(struct i2c_client *client)
{
	int err;
	struct rtc_time tm;

	memset(&tm, 0, sizeof(tm));

	err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
	if (err < 0)
		dev_err(&client->dev, "unable to restart the oscillator\n");

	return err;
}

static int x1205_get_dtrim(struct i2c_client *client, int *trim)
{
	unsigned char dtr;
	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };

	struct i2c_msg msgs[] = {
		{	/* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = dtr_addr
		},
		{      /* read dtr */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = &dtr
		},
	};

	/* read dtr register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);

	*trim = 0;

	if (dtr & X1205_DTR_DTR0)
		*trim += 20;

	if (dtr & X1205_DTR_DTR1)
		*trim += 10;

	if (dtr & X1205_DTR_DTR2)
		*trim = -*trim;

	return 0;
}

static int x1205_get_atrim(struct i2c_client *client, int *trim)
{
	s8 atr;
	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };

	struct i2c_msg msgs[] = {
		{/* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = atr_addr
		},
		{/* read atr */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = &atr
		},
	};

	/* read atr register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);

	/* atr is a two's complement value on 6 bits,
	 * perform sign extension. The formula is
	 * Catr = (atr * 0.25pF) + 11.00pF.
	 */
	atr = sign_extend32(atr, 5);

	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);

	*trim = (atr * 250) + 11000;

	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);

	return 0;
}

struct x1205_limit {
	unsigned char reg, mask, min, max;
};

static int x1205_validate_client(struct i2c_client *client)
{
	int i, xfer;

	/* Probe array. We will read the register at the specified
	 * address and check if the given bits are zero.
	 */
	static const unsigned char probe_zero_pattern[] = {
		/* register, mask */
		X1205_REG_SR,	0x18,
		X1205_REG_DTR,	0xF8,
		X1205_REG_ATR,	0xC0,
		X1205_REG_INT,	0x18,
		X1205_REG_0,	0xFF,
	};

	static const struct x1205_limit probe_limits_pattern[] = {
		/* register, mask, min, max */
		{ X1205_REG_Y2K,	0xFF,	19,	20	},
		{ X1205_REG_DW,		0xFF,	0,	6	},
		{ X1205_REG_YR,		0xFF,	0,	99	},
		{ X1205_REG_MO,		0xFF,	0,	12	},
		{ X1205_REG_DT,		0xFF,	0,	31	},
		{ X1205_REG_HR,		0x7F,	0,	23	},
		{ X1205_REG_MN,		0xFF,	0,	59	},
		{ X1205_REG_SC,		0xFF,	0,	59	},
		{ X1205_REG_Y2K1,	0xFF,	19,	20	},
		{ X1205_REG_Y2K0,	0xFF,	19,	20	},
	};

	/* check that registers have bits a 0 where expected */
	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
		unsigned char buf;

		unsigned char addr[2] = { 0, probe_zero_pattern[i] };

		struct i2c_msg msgs[2] = {
			{
				.addr = client->addr,
				.len = 2,
				.buf = addr
			},
			{
				.addr = client->addr,
				.flags = I2C_M_RD,
				.len = 1,
				.buf = &buf
			},
		};

		xfer = i2c_transfer(client->adapter, msgs, 2);
		if (xfer != 2) {
			dev_err(&client->dev,
				"%s: could not read register %x\n",
				__func__, probe_zero_pattern[i]);

			return -EIO;
		}

		if ((buf & probe_zero_pattern[i+1]) != 0) {
			dev_err(&client->dev,
				"%s: register=%02x, zero pattern=%d, value=%x\n",
				__func__, probe_zero_pattern[i], i, buf);

			return -ENODEV;
		}
	}

	/* check limits (only registers with bcd values) */
	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
		unsigned char reg, value;

		unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };

		struct i2c_msg msgs[2] = {
			{
				.addr = client->addr,
				.len = 2,
				.buf = addr
			},
			{
				.addr = client->addr,
				.flags = I2C_M_RD,
				.len = 1,
				.buf = &reg
			},
		};

		xfer = i2c_transfer(client->adapter, msgs, 2);
		if (xfer != 2) {
			dev_err(&client->dev,
				"%s: could not read register %x\n",
				__func__, probe_limits_pattern[i].reg);

			return -EIO;
		}

		value = bcd2bin(reg & probe_limits_pattern[i].mask);

		if (value > probe_limits_pattern[i].max ||
			value < probe_limits_pattern[i].min) {
			dev_dbg(&client->dev,
				"%s: register=%x, lim pattern=%d, value=%d\n",
				__func__, probe_limits_pattern[i].reg,
				i, value);

			return -ENODEV;
		}
	}

	return 0;
}

static int x1205_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int err;
	unsigned char intreg, status;
	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
	struct i2c_client *client = to_i2c_client(dev);
	struct i2c_msg msgs[] = {
		{ /* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = int_addr
		},
		{/* read INT register */

			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = &intreg
		},
	};

	/* read interrupt register and status register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}
	err = x1205_get_status(client, &status);
	if (err == 0) {
		alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
		alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
		err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
	}
	return err;
}

static int x1205_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	return x1205_set_datetime(to_i2c_client(dev),
		&alrm->time, X1205_ALM0_BASE, alrm->enabled);
}

static int x1205_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	return x1205_get_datetime(to_i2c_client(dev),
		tm, X1205_CCR_BASE);
}

static int x1205_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	return x1205_set_datetime(to_i2c_client(dev),
		tm, X1205_CCR_BASE, 0);
}

static int x1205_rtc_proc(struct device *dev, struct seq_file *seq)
{
	int err, dtrim, atrim;

	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	if (!err)
		seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);

	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	if (!err)
		seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
			atrim / 1000, atrim % 1000);
	return 0;
}

static const struct rtc_class_ops x1205_rtc_ops = {
	.proc		= x1205_rtc_proc,
	.read_time	= x1205_rtc_read_time,
	.set_time	= x1205_rtc_set_time,
	.read_alarm	= x1205_rtc_read_alarm,
	.set_alarm	= x1205_rtc_set_alarm,
};

static ssize_t x1205_sysfs_show_atrim(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	int err, atrim;

	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	if (err)
		return err;

	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
}
static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);

static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	int err, dtrim;

	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	if (err)
		return err;

	return sprintf(buf, "%d ppm\n", dtrim);
}
static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);

static int x1205_sysfs_register(struct device *dev)
{
	int err;

	err = device_create_file(dev, &dev_attr_atrim);
	if (err)
		return err;

	err = device_create_file(dev, &dev_attr_dtrim);
	if (err)
		device_remove_file(dev, &dev_attr_atrim);

	return err;
}

static void x1205_sysfs_unregister(struct device *dev)
{
	device_remove_file(dev, &dev_attr_atrim);
	device_remove_file(dev, &dev_attr_dtrim);
}


static int x1205_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	int err = 0;
	unsigned char sr;
	struct rtc_device *rtc;

	dev_dbg(&client->dev, "%s\n", __func__);

	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
		return -ENODEV;

	if (x1205_validate_client(client) < 0)
		return -ENODEV;

	rtc = devm_rtc_device_register(&client->dev, x1205_driver.driver.name,
					&x1205_rtc_ops, THIS_MODULE);

	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	i2c_set_clientdata(client, rtc);

	/* Check for power failures and eventually enable the osc */
	err = x1205_get_status(client, &sr);
	if (!err) {
		if (sr & X1205_SR_RTCF) {
			dev_err(&client->dev,
				"power failure detected, "
				"please set the clock\n");
			udelay(50);
			x1205_fix_osc(client);
		}
	} else {
		dev_err(&client->dev, "couldn't read status\n");
	}

	err = x1205_sysfs_register(&client->dev);
	if (err)
		dev_err(&client->dev, "Unable to create sysfs entries\n");

	return 0;
}

static int x1205_remove(struct i2c_client *client)
{
	x1205_sysfs_unregister(&client->dev);
	return 0;
}

static const struct i2c_device_id x1205_id[] = {
	{ "x1205", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, x1205_id);

static struct i2c_driver x1205_driver = {
	.driver		= {
		.name	= "rtc-x1205",
	},
	.probe		= x1205_probe,
	.remove		= x1205_remove,
	.id_table	= x1205_id,
};

module_i2c_driver(x1205_driver);

MODULE_AUTHOR(
	"Karen Spearel <kas111 at gmail dot com>, "
	"Alessandro Zummo <a.zummo@towertech.it>");
MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1fec7c66 AZ	1	/*
	2	* An i2c driver for the Xicor/Intersil X1205 RTC
	3	* Copyright 2004 Karen Spearel
	4	* Copyright 2005 Alessandro Zummo
	5	*
	6	* please send all reports to:
66e3f10c	7	* Karen Spearel <kas111 at gmail dot com>
1fec7c66 AZ	8	* Alessandro Zummo <a.zummo@towertech.it>
	9	*
	10	* based on a lot of other RTC drivers.
	11	*
890e0375 JD	12	* Information and datasheet:
	13	* http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
	14	*
1fec7c66 AZ	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include <linux/i2c.h>
	21	#include <linux/bcd.h>
	22	#include <linux/rtc.h>
	23	#include <linux/delay.h>
2113852b	24	#include <linux/module.h>
86e66604	25	#include <linux/bitops.h>
1fec7c66	26
1fec7c66 AZ	27	/* offsets into CCR area */
	28
	29	#define CCR_SEC 0
	30	#define CCR_MIN 1
	31	#define CCR_HOUR 2
	32	#define CCR_MDAY 3
	33	#define CCR_MONTH 4
	34	#define CCR_YEAR 5
	35	#define CCR_WDAY 6
	36	#define CCR_Y2K 7
	37
	38	#define X1205_REG_SR 0x3F /* status register */
	39	#define X1205_REG_Y2K 0x37
	40	#define X1205_REG_DW 0x36
	41	#define X1205_REG_YR 0x35
	42	#define X1205_REG_MO 0x34
	43	#define X1205_REG_DT 0x33
	44	#define X1205_REG_HR 0x32
	45	#define X1205_REG_MN 0x31
	46	#define X1205_REG_SC 0x30
	47	#define X1205_REG_DTR 0x13
	48	#define X1205_REG_ATR 0x12
	49	#define X1205_REG_INT 0x11
	50	#define X1205_REG_0 0x10
	51	#define X1205_REG_Y2K1 0x0F
	52	#define X1205_REG_DWA1 0x0E
	53	#define X1205_REG_YRA1 0x0D
	54	#define X1205_REG_MOA1 0x0C
	55	#define X1205_REG_DTA1 0x0B
	56	#define X1205_REG_HRA1 0x0A
	57	#define X1205_REG_MNA1 0x09
	58	#define X1205_REG_SCA1 0x08
	59	#define X1205_REG_Y2K0 0x07
	60	#define X1205_REG_DWA0 0x06
	61	#define X1205_REG_YRA0 0x05
	62	#define X1205_REG_MOA0 0x04
	63	#define X1205_REG_DTA0 0x03
	64	#define X1205_REG_HRA0 0x02
	65	#define X1205_REG_MNA0 0x01
	66	#define X1205_REG_SCA0 0x00
	67
	68	#define X1205_CCR_BASE 0x30 /* Base address of CCR */
	69	#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
	70
	71	#define X1205_SR_RTCF 0x01 /* Clock failure */
	72	#define X1205_SR_WEL 0x02 /* Write Enable Latch */
	73	#define X1205_SR_RWEL 0x04 /* Register Write Enable */
471d47e3	74	#define X1205_SR_AL0 0x20 /* Alarm 0 match */
1fec7c66 AZ	75
	76	#define X1205_DTR_DTR0 0x01
	77	#define X1205_DTR_DTR1 0x02
	78	#define X1205_DTR_DTR2 0x04
	79
	80	#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
	81
471d47e3 MH	82	#define X1205_INT_AL0E 0x20 /* Alarm 0 enable */
471d47e3 MH	83
4edac2b4	84	static struct i2c_driver x1205_driver;
1fec7c66 AZ	85
	86	/*
	87	* In the routines that deal directly with the x1205 hardware, we use
	88	* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
	89	* Epoch is initialized as 2000. Time is set to UTC.
	90	*/
	91	static int x1205_get_datetime(struct i2c_client client, struct rtc_time tm,
	92	unsigned char reg_base)
	93	{
	94	unsigned char dt_addr[2] = { 0, reg_base };
1fec7c66	95	unsigned char buf[8];
471d47e3	96	int i;
1fec7c66 AZ	97
1fec7c66 AZ	98	struct i2c_msg msgs[] = {
c3fe92b7 S	99	{/* setup read ptr */
	100	.addr = client->addr,
	101	.len = 2,
	102	.buf = dt_addr
	103	},
	104	{/* read date */
	105	.addr = client->addr,
	106	.flags = I2C_M_RD,
	107	.len = 8,
	108	.buf = buf
	109	},
1fec7c66 AZ	110	};
	111
	112	/* read date registers */
471d47e3	113	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	114	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	115	return -EIO;
	116	}
	117
	118	dev_dbg(&client->dev,
	119	"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
	120	"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
2a4e2b87	121	__func__,
1fec7c66 AZ	122	buf[0], buf[1], buf[2], buf[3],
	123	buf[4], buf[5], buf[6], buf[7]);
	124
471d47e3 MH	125	/* Mask out the enable bits if these are alarm registers */
	126	if (reg_base < X1205_CCR_BASE)
	127	for (i = 0; i <= 4; i++)
	128	buf[i] &= 0x7F;
	129
fe20ba70 AB	130	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
	131	tm->tm_min = bcd2bin(buf[CCR_MIN]);
	132	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	133	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
	134	tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
	135	tm->tm_year = bcd2bin(buf[CCR_YEAR])
	136	+ (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
1fec7c66 AZ	137	tm->tm_wday = buf[CCR_WDAY];
	138
	139	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	140	"mday=%d, mon=%d, year=%d, wday=%d\n",
2a4e2b87	141	__func__,
1fec7c66 AZ	142	tm->tm_sec, tm->tm_min, tm->tm_hour,
	143	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	144
	145	return 0;
	146	}
	147
	148	static int x1205_get_status(struct i2c_client client, unsigned char sr)
	149	{
	150	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };
	151
	152	struct i2c_msg msgs[] = {
c3fe92b7 S	153	{ /* setup read ptr */
	154	.addr = client->addr,
	155	.len = 2,
	156	.buf = sr_addr
	157	},
	158	{ /* read status */
	159	.addr = client->addr,
	160	.flags = I2C_M_RD,
	161	.len = 1,
	162	.buf = sr
	163	},
1fec7c66 AZ	164	};
	165
	166	/* read status register */
471d47e3	167	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	168	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	169	return -EIO;
	170	}
	171
	172	return 0;
	173	}
	174
	175	static int x1205_set_datetime(struct i2c_client client, struct rtc_time tm,
d973b632	176	u8 reg_base, unsigned char alm_enable)
1fec7c66	177	{
d973b632	178	int i, xfer;
471d47e3	179	unsigned char rdata[10] = { 0, reg_base };
d973b632	180	unsigned char *buf = rdata + 2;
1fec7c66 AZ	181
	182	static const unsigned char wel[3] = { 0, X1205_REG_SR,
	183	X1205_SR_WEL };
	184
	185	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
	186	X1205_SR_WEL \| X1205_SR_RWEL };
	187
	188	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };
	189
	190	dev_dbg(&client->dev,
d973b632 JW	191	"%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
	192	__func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
	193	tm->tm_mon, tm->tm_year, tm->tm_wday);
1fec7c66	194
fe20ba70 AB	195	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
fe20ba70 AB	196	buf[CCR_MIN] = bin2bcd(tm->tm_min);
1fec7c66 AZ	197
1fec7c66 AZ	198	/* set hour and 24hr bit */
fe20ba70	199	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) \| X1205_HR_MIL;
1fec7c66	200
d973b632	201	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
1fec7c66	202
d973b632 JW	203	/* month, 1 - 12 */
d973b632 JW	204	buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);
1fec7c66	205
d973b632 JW	206	/* year, since the rtc epoch*/
	207	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
	208	buf[CCR_WDAY] = tm->tm_wday & 0x07;
	209	buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);
1fec7c66	210
471d47e3 MH	211	/* If writing alarm registers, set compare bits on registers 0-4 */
	212	if (reg_base < X1205_CCR_BASE)
	213	for (i = 0; i <= 4; i++)
	214	buf[i] \|= 0x80;
	215
1fec7c66	216	/* this sequence is required to unlock the chip */
66e3f10c SK	217	xfer = i2c_master_send(client, wel, 3);
66e3f10c SK	218	if (xfer != 3) {
2a4e2b87	219	dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
1fec7c66 AZ	220	return -EIO;
	221	}
	222
66e3f10c SK	223	xfer = i2c_master_send(client, rwel, 3);
66e3f10c SK	224	if (xfer != 3) {
2a4e2b87	225	dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
1fec7c66 AZ	226	return -EIO;
	227	}
	228
d973b632 JW	229	xfer = i2c_master_send(client, rdata, sizeof(rdata));
d973b632 JW	230	if (xfer != sizeof(rdata)) {
471d47e3 MH	231	dev_err(&client->dev,
	232	"%s: result=%d addr=%02x, data=%02x\n",
	233	__func__,
	234	xfer, rdata[1], rdata[2]);
	235	return -EIO;
	236	}
	237
	238	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
	239	if (reg_base < X1205_CCR_BASE) {
	240	unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };
	241
	242	msleep(10);
	243
	244	/* ...and set or clear the AL0E bit in the INT register */
1fec7c66	245
471d47e3 MH	246	/* Need to set RWEL again as the write has cleared it */
471d47e3 MH	247	xfer = i2c_master_send(client, rwel, 3);
1fec7c66 AZ	248	if (xfer != 3) {
1fec7c66 AZ	249	dev_err(&client->dev,
471d47e3	250	"%s: aloe rwel - %d\n",
2a4e2b87	251	__func__,
471d47e3 MH	252	xfer);
	253	return -EIO;
	254	}
	255
	256	if (alm_enable)
	257	al0e[2] = X1205_INT_AL0E;
	258
	259	xfer = i2c_master_send(client, al0e, 3);
	260	if (xfer != 3) {
	261	dev_err(&client->dev,
	262	"%s: al0e - %d\n",
	263	__func__,
	264	xfer);
1fec7c66 AZ	265	return -EIO;
1fec7c66 AZ	266	}
471d47e3 MH	267
	268	/* and wait 10msec again for this write to complete */
	269	msleep(10);
	270	}
1fec7c66 AZ	271
1fec7c66 AZ	272	/* disable further writes */
66e3f10c SK	273	xfer = i2c_master_send(client, diswe, 3);
66e3f10c SK	274	if (xfer != 3) {
2a4e2b87	275	dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
1fec7c66 AZ	276	return -EIO;
	277	}
	278
	279	return 0;
	280	}
	281
	282	static int x1205_fix_osc(struct i2c_client *client)
	283	{
	284	int err;
	285	struct rtc_time tm;
	286
cb8799ee	287	memset(&tm, 0, sizeof(tm));
1fec7c66	288
d973b632	289	err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
471d47e3 MH	290	if (err < 0)
471d47e3 MH	291	dev_err(&client->dev, "unable to restart the oscillator\n");
1fec7c66 AZ	292
	293	return err;
	294	}
	295
	296	static int x1205_get_dtrim(struct i2c_client client, int trim)
	297	{
	298	unsigned char dtr;
	299	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };
	300
	301	struct i2c_msg msgs[] = {
c3fe92b7 S	302	{ /* setup read ptr */
	303	.addr = client->addr,
	304	.len = 2,
	305	.buf = dtr_addr
	306	},
	307	{ /* read dtr */
	308	.addr = client->addr,
	309	.flags = I2C_M_RD,
	310	.len = 1,
	311	.buf = &dtr
	312	},
1fec7c66 AZ	313	};
	314
	315	/* read dtr register */
471d47e3	316	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	317	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	318	return -EIO;
	319	}
	320
2a4e2b87	321	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);
1fec7c66 AZ	322
	323	*trim = 0;
	324
	325	if (dtr & X1205_DTR_DTR0)
	326	*trim += 20;
	327
	328	if (dtr & X1205_DTR_DTR1)
	329	*trim += 10;
	330
	331	if (dtr & X1205_DTR_DTR2)
	332	trim = -trim;
	333
	334	return 0;
	335	}
	336
	337	static int x1205_get_atrim(struct i2c_client client, int trim)
	338	{
	339	s8 atr;
	340	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };
	341
	342	struct i2c_msg msgs[] = {
c3fe92b7 S	343	{/* setup read ptr */
	344	.addr = client->addr,
	345	.len = 2,
	346	.buf = atr_addr
	347	},
	348	{/* read atr */
	349	.addr = client->addr,
	350	.flags = I2C_M_RD,
	351	.len = 1,
	352	.buf = &atr
	353	},
1fec7c66 AZ	354	};
	355
	356	/* read atr register */
471d47e3	357	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	358	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	359	return -EIO;
	360	}
	361
2a4e2b87	362	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);
1fec7c66 AZ	363
	364	/* atr is a two's complement value on 6 bits,
	365	* perform sign extension. The formula is
	366	* Catr = (atr * 0.25pF) + 11.00pF.
	367	*/
86e66604	368	atr = sign_extend32(atr, 5);
1fec7c66	369
2a4e2b87	370	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);
1fec7c66 AZ	371
	372	trim = (atr 250) + 11000;
	373
2a4e2b87	374	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);
1fec7c66 AZ	375
	376	return 0;
	377	}
	378
66e3f10c	379	struct x1205_limit {
1fec7c66 AZ	380	unsigned char reg, mask, min, max;
	381	};
	382
	383	static int x1205_validate_client(struct i2c_client *client)
	384	{
	385	int i, xfer;
	386
	387	/* Probe array. We will read the register at the specified
	388	* address and check if the given bits are zero.
	389	*/
	390	static const unsigned char probe_zero_pattern[] = {
	391	/* register, mask */
	392	X1205_REG_SR, 0x18,
	393	X1205_REG_DTR, 0xF8,
	394	X1205_REG_ATR, 0xC0,
	395	X1205_REG_INT, 0x18,
	396	X1205_REG_0, 0xFF,
	397	};
	398
	399	static const struct x1205_limit probe_limits_pattern[] = {
	400	/* register, mask, min, max */
	401	{ X1205_REG_Y2K, 0xFF, 19, 20 },
	402	{ X1205_REG_DW, 0xFF, 0, 6 },
	403	{ X1205_REG_YR, 0xFF, 0, 99 },
	404	{ X1205_REG_MO, 0xFF, 0, 12 },
	405	{ X1205_REG_DT, 0xFF, 0, 31 },
	406	{ X1205_REG_HR, 0x7F, 0, 23 },
	407	{ X1205_REG_MN, 0xFF, 0, 59 },
	408	{ X1205_REG_SC, 0xFF, 0, 59 },
	409	{ X1205_REG_Y2K1, 0xFF, 19, 20 },
	410	{ X1205_REG_Y2K0, 0xFF, 19, 20 },
	411	};
	412
	413	/* check that registers have bits a 0 where expected */
	414	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
	415	unsigned char buf;
	416
	417	unsigned char addr[2] = { 0, probe_zero_pattern[i] };
	418
	419	struct i2c_msg msgs[2] = {
c3fe92b7 S	420	{
	421	.addr = client->addr,
	422	.len = 2,
	423	.buf = addr
	424	},
	425	{
	426	.addr = client->addr,
	427	.flags = I2C_M_RD,
	428	.len = 1,
	429	.buf = &buf
	430	},
1fec7c66 AZ	431	};
1fec7c66 AZ	432
66e3f10c SK	433	xfer = i2c_transfer(client->adapter, msgs, 2);
66e3f10c SK	434	if (xfer != 2) {
a14e1893	435	dev_err(&client->dev,
1fec7c66	436	"%s: could not read register %x\n",
2a4e2b87	437	__func__, probe_zero_pattern[i]);
1fec7c66 AZ	438
	439	return -EIO;
	440	}
	441
	442	if ((buf & probe_zero_pattern[i+1]) != 0) {
a14e1893	443	dev_err(&client->dev,
1fec7c66	444	"%s: register=%02x, zero pattern=%d, value=%x\n",
2a4e2b87	445	__func__, probe_zero_pattern[i], i, buf);
1fec7c66 AZ	446
	447	return -ENODEV;
	448	}
	449	}
	450
	451	/* check limits (only registers with bcd values) */
	452	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
	453	unsigned char reg, value;
	454
	455	unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };
	456
	457	struct i2c_msg msgs[2] = {
c3fe92b7 S	458	{
	459	.addr = client->addr,
	460	.len = 2,
	461	.buf = addr
	462	},
	463	{
	464	.addr = client->addr,
	465	.flags = I2C_M_RD,
	466	.len = 1,
	467	.buf = &reg
	468	},
1fec7c66 AZ	469	};
1fec7c66 AZ	470
66e3f10c SK	471	xfer = i2c_transfer(client->adapter, msgs, 2);
66e3f10c SK	472	if (xfer != 2) {
a14e1893	473	dev_err(&client->dev,
1fec7c66	474	"%s: could not read register %x\n",
2a4e2b87	475	__func__, probe_limits_pattern[i].reg);
1fec7c66 AZ	476
	477	return -EIO;
	478	}
	479
fe20ba70	480	value = bcd2bin(reg & probe_limits_pattern[i].mask);
1fec7c66 AZ	481
	482	if (value > probe_limits_pattern[i].max \|\|
	483	value < probe_limits_pattern[i].min) {
a14e1893	484	dev_dbg(&client->dev,
1fec7c66	485	"%s: register=%x, lim pattern=%d, value=%d\n",
2a4e2b87	486	__func__, probe_limits_pattern[i].reg,
1fec7c66 AZ	487	i, value);
	488
	489	return -ENODEV;
	490	}
	491	}
	492
	493	return 0;
	494	}
	495
	496	static int x1205_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	497	{
471d47e3 MH	498	int err;
	499	unsigned char intreg, status;
	500	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
	501	struct i2c_client *client = to_i2c_client(dev);
	502	struct i2c_msg msgs[] = {
c3fe92b7 S	503	{ /* setup read ptr */
	504	.addr = client->addr,
	505	.len = 2,
	506	.buf = int_addr
	507	},
	508	{/* read INT register */
	509
	510	.addr = client->addr,
	511	.flags = I2C_M_RD,
	512	.len = 1,
	513	.buf = &intreg
	514	},
471d47e3 MH	515	};
	516
	517	/* read interrupt register and status register */
	518	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
	519	dev_err(&client->dev, "%s: read error\n", __func__);
	520	return -EIO;
	521	}
	522	err = x1205_get_status(client, &status);
	523	if (err == 0) {
	524	alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
	525	alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
	526	err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
	527	}
	528	return err;
1fec7c66 AZ	529	}
	530
	531	static int x1205_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	532	{
	533	return x1205_set_datetime(to_i2c_client(dev),
d973b632	534	&alrm->time, X1205_ALM0_BASE, alrm->enabled);
1fec7c66 AZ	535	}
	536
	537	static int x1205_rtc_read_time(struct device dev, struct rtc_time tm)
	538	{
	539	return x1205_get_datetime(to_i2c_client(dev),
	540	tm, X1205_CCR_BASE);
	541	}
	542
	543	static int x1205_rtc_set_time(struct device dev, struct rtc_time tm)
	544	{
	545	return x1205_set_datetime(to_i2c_client(dev),
d973b632	546	tm, X1205_CCR_BASE, 0);
1fec7c66 AZ	547	}
	548
	549	static int x1205_rtc_proc(struct device dev, struct seq_file seq)
	550	{
	551	int err, dtrim, atrim;
	552
66e3f10c SK	553	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
66e3f10c SK	554	if (!err)
1fec7c66 AZ	555	seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);
1fec7c66 AZ	556
66e3f10c SK	557	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
66e3f10c SK	558	if (!err)
1fec7c66 AZ	559	seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
	560	atrim / 1000, atrim % 1000);
	561	return 0;
	562	}
	563
ff8371ac	564	static const struct rtc_class_ops x1205_rtc_ops = {
1fec7c66 AZ	565	.proc = x1205_rtc_proc,
	566	.read_time = x1205_rtc_read_time,
	567	.set_time = x1205_rtc_set_time,
	568	.read_alarm = x1205_rtc_read_alarm,
	569	.set_alarm = x1205_rtc_set_alarm,
	570	};
	571
	572	static ssize_t x1205_sysfs_show_atrim(struct device *dev,
	573	struct device_attribute attr, char buf)
	574	{
015aefbb	575	int err, atrim;
1fec7c66	576
015aefbb AZ	577	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	578	if (err)
	579	return err;
	580
	581	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
1fec7c66 AZ	582	}
	583	static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);
	584
	585	static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
	586	struct device_attribute attr, char buf)
	587	{
015aefbb	588	int err, dtrim;
1fec7c66	589
015aefbb AZ	590	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	591	if (err)
	592	return err;
1fec7c66	593
015aefbb	594	return sprintf(buf, "%d ppm\n", dtrim);
1fec7c66 AZ	595	}
	596	static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);
	597
4edac2b4 AZ	598	static int x1205_sysfs_register(struct device *dev)
	599	{
	600	int err;
	601
	602	err = device_create_file(dev, &dev_attr_atrim);
	603	if (err)
	604	return err;
	605
	606	err = device_create_file(dev, &dev_attr_dtrim);
	607	if (err)
	608	device_remove_file(dev, &dev_attr_atrim);
	609
	610	return err;
	611	}
	612
	613	static void x1205_sysfs_unregister(struct device *dev)
1fec7c66	614	{
4edac2b4 AZ	615	device_remove_file(dev, &dev_attr_atrim);
4edac2b4 AZ	616	device_remove_file(dev, &dev_attr_dtrim);
1fec7c66 AZ	617	}
1fec7c66 AZ	618
4edac2b4	619
d2653e92 JD	620	static int x1205_probe(struct i2c_client *client,
d2653e92 JD	621	const struct i2c_device_id *id)
1fec7c66 AZ	622	{
	623	int err = 0;
	624	unsigned char sr;
1fec7c66 AZ	625	struct rtc_device *rtc;
1fec7c66 AZ	626
4edac2b4	627	dev_dbg(&client->dev, "%s\n", __func__);
1fec7c66	628
4edac2b4 AZ	629	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
4edac2b4 AZ	630	return -ENODEV;
1fec7c66	631
4edac2b4 AZ	632	if (x1205_validate_client(client) < 0)
4edac2b4 AZ	633	return -ENODEV;
1fec7c66	634
17581718 JH	635	rtc = devm_rtc_device_register(&client->dev, x1205_driver.driver.name,
17581718 JH	636	&x1205_rtc_ops, THIS_MODULE);
1fec7c66	637
4edac2b4 AZ	638	if (IS_ERR(rtc))
4edac2b4 AZ	639	return PTR_ERR(rtc);
1fec7c66 AZ	640
	641	i2c_set_clientdata(client, rtc);
	642
25985edc	643	/* Check for power failures and eventually enable the osc */
66e3f10c SK	644	err = x1205_get_status(client, &sr);
66e3f10c SK	645	if (!err) {
1fec7c66 AZ	646	if (sr & X1205_SR_RTCF) {
	647	dev_err(&client->dev,
	648	"power failure detected, "
	649	"please set the clock\n");
	650	udelay(50);
	651	x1205_fix_osc(client);
	652	}
66e3f10c	653	} else {
1fec7c66	654	dev_err(&client->dev, "couldn't read status\n");
66e3f10c	655	}
1fec7c66	656
4edac2b4 AZ	657	err = x1205_sysfs_register(&client->dev);
4edac2b4 AZ	658	if (err)
4071ea25	659	dev_err(&client->dev, "Unable to create sysfs entries\n");
1fec7c66 AZ	660
1fec7c66 AZ	661	return 0;
1fec7c66 AZ	662	}
1fec7c66 AZ	663
4edac2b4	664	static int x1205_remove(struct i2c_client *client)
1fec7c66	665	{
4edac2b4	666	x1205_sysfs_unregister(&client->dev);
1fec7c66 AZ	667	return 0;
	668	}
	669
3760f736 JD	670	static const struct i2c_device_id x1205_id[] = {
	671	{ "x1205", 0 },
	672	{ }
	673	};
	674	MODULE_DEVICE_TABLE(i2c, x1205_id);
	675
4edac2b4 AZ	676	static struct i2c_driver x1205_driver = {
	677	.driver = {
	678	.name = "rtc-x1205",
	679	},
	680	.probe = x1205_probe,
	681	.remove = x1205_remove,
3760f736	682	.id_table = x1205_id,
4edac2b4 AZ	683	};
4edac2b4 AZ	684
0abc9201	685	module_i2c_driver(x1205_driver);
1fec7c66 AZ	686
	687	MODULE_AUTHOR(
	688	"Karen Spearel <kas111 at gmail dot com>, "
	689	"Alessandro Zummo <a.zummo@towertech.it>");
	690	MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
	691	MODULE_LICENSE("GPL");