[linux-2.6-block.git] / drivers / rtc / rtc-x1205.c

/*
 * An i2c driver for the Xicor/Intersil X1205 RTC
 * Copyright 2004 Karen Spearel
 * Copyright 2005 Alessandro Zummo
 *
 * please send all reports to:
 *	Karen Spearel <kas111 at gmail dot com>
 *	Alessandro Zummo <a.zummo@towertech.it>
 *
 * based on a lot of other RTC drivers.
 *
 * Information and datasheet:
 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/bitops.h>

#define DRV_VERSION "1.0.8"

/* offsets into CCR area */

#define CCR_SEC			0
#define CCR_MIN			1
#define CCR_HOUR		2
#define CCR_MDAY		3
#define CCR_MONTH		4
#define CCR_YEAR		5
#define CCR_WDAY		6
#define CCR_Y2K			7

#define X1205_REG_SR		0x3F	/* status register */
#define X1205_REG_Y2K		0x37
#define X1205_REG_DW		0x36
#define X1205_REG_YR		0x35
#define X1205_REG_MO		0x34
#define X1205_REG_DT		0x33
#define X1205_REG_HR		0x32
#define X1205_REG_MN		0x31
#define X1205_REG_SC		0x30
#define X1205_REG_DTR		0x13
#define X1205_REG_ATR		0x12
#define X1205_REG_INT		0x11
#define X1205_REG_0		0x10
#define X1205_REG_Y2K1		0x0F
#define X1205_REG_DWA1		0x0E
#define X1205_REG_YRA1		0x0D
#define X1205_REG_MOA1		0x0C
#define X1205_REG_DTA1		0x0B
#define X1205_REG_HRA1		0x0A
#define X1205_REG_MNA1		0x09
#define X1205_REG_SCA1		0x08
#define X1205_REG_Y2K0		0x07
#define X1205_REG_DWA0		0x06
#define X1205_REG_YRA0		0x05
#define X1205_REG_MOA0		0x04
#define X1205_REG_DTA0		0x03
#define X1205_REG_HRA0		0x02
#define X1205_REG_MNA0		0x01
#define X1205_REG_SCA0		0x00

#define X1205_CCR_BASE		0x30	/* Base address of CCR */
#define X1205_ALM0_BASE		0x00	/* Base address of ALARM0 */

#define X1205_SR_RTCF		0x01	/* Clock failure */
#define X1205_SR_WEL		0x02	/* Write Enable Latch */
#define X1205_SR_RWEL		0x04	/* Register Write Enable */
#define X1205_SR_AL0		0x20	/* Alarm 0 match */

#define X1205_DTR_DTR0		0x01
#define X1205_DTR_DTR1		0x02
#define X1205_DTR_DTR2		0x04

#define X1205_HR_MIL		0x80	/* Set in ccr.hour for 24 hr mode */

#define X1205_INT_AL0E		0x20	/* Alarm 0 enable */

static struct i2c_driver x1205_driver;

/*
 * In the routines that deal directly with the x1205 hardware, we use
 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
 * Epoch is initialized as 2000. Time is set to UTC.
 */
static int x1205_get_datetime(struct i2c_client *client, struct rtc_time *tm,
				unsigned char reg_base)
{
	unsigned char dt_addr[2] = { 0, reg_base };
	unsigned char buf[8];
	int i;

	struct i2c_msg msgs[] = {
		{/* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = dt_addr
		},
		{/* read date */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 8,
			.buf = buf
		},
	};

	/* read date registers */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev,
		"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
		"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
		__func__,
		buf[0], buf[1], buf[2], buf[3],
		buf[4], buf[5], buf[6], buf[7]);

	/* Mask out the enable bits if these are alarm registers */
	if (reg_base < X1205_CCR_BASE)
		for (i = 0; i <= 4; i++)
			buf[i] &= 0x7F;

	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
	tm->tm_min = bcd2bin(buf[CCR_MIN]);
	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
	tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
	tm->tm_year = bcd2bin(buf[CCR_YEAR])
			+ (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
	tm->tm_wday = buf[CCR_WDAY];

	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
		"mday=%d, mon=%d, year=%d, wday=%d\n",
		__func__,
		tm->tm_sec, tm->tm_min, tm->tm_hour,
		tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	return 0;
}

static int x1205_get_status(struct i2c_client *client, unsigned char *sr)
{
	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };

	struct i2c_msg msgs[] = {
		{     /* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = sr_addr
		},
		{    /* read status */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = sr
		},
	};

	/* read status register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	return 0;
}

static int x1205_set_datetime(struct i2c_client *client, struct rtc_time *tm,
			u8 reg_base, unsigned char alm_enable)
{
	int i, xfer;
	unsigned char rdata[10] = { 0, reg_base };
	unsigned char *buf = rdata + 2;

	static const unsigned char wel[3] = { 0, X1205_REG_SR,
						X1205_SR_WEL };

	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
						X1205_SR_WEL | X1205_SR_RWEL };

	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };

	dev_dbg(&client->dev,
		"%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
		__func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
		tm->tm_mon, tm->tm_year, tm->tm_wday);

	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
	buf[CCR_MIN] = bin2bcd(tm->tm_min);

	/* set hour and 24hr bit */
	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;

	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);

	/* month, 1 - 12 */
	buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);

	/* year, since the rtc epoch*/
	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
	buf[CCR_WDAY] = tm->tm_wday & 0x07;
	buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);

	/* If writing alarm registers, set compare bits on registers 0-4 */
	if (reg_base < X1205_CCR_BASE)
		for (i = 0; i <= 4; i++)
			buf[i] |= 0x80;

	/* this sequence is required to unlock the chip */
	xfer = i2c_master_send(client, wel, 3);
	if (xfer != 3) {
		dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
		return -EIO;
	}

	xfer = i2c_master_send(client, rwel, 3);
	if (xfer != 3) {
		dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
		return -EIO;
	}

	xfer = i2c_master_send(client, rdata, sizeof(rdata));
	if (xfer != sizeof(rdata)) {
		dev_err(&client->dev,
			"%s: result=%d addr=%02x, data=%02x\n",
			__func__,
			 xfer, rdata[1], rdata[2]);
		return -EIO;
	}

	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
	if (reg_base < X1205_CCR_BASE) {
		unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };

		msleep(10);

		/* ...and set or clear the AL0E bit in the INT register */

		/* Need to set RWEL again as the write has cleared it */
		xfer = i2c_master_send(client, rwel, 3);
		if (xfer != 3) {
			dev_err(&client->dev,
				"%s: aloe rwel - %d\n",
				__func__,
				xfer);
			return -EIO;
		}

		if (alm_enable)
			al0e[2] = X1205_INT_AL0E;

		xfer = i2c_master_send(client, al0e, 3);
		if (xfer != 3) {
			dev_err(&client->dev,
				"%s: al0e - %d\n",
				__func__,
				xfer);
			return -EIO;
		}

		/* and wait 10msec again for this write to complete */
		msleep(10);
	}

	/* disable further writes */
	xfer = i2c_master_send(client, diswe, 3);
	if (xfer != 3) {
		dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
		return -EIO;
	}

	return 0;
}

static int x1205_fix_osc(struct i2c_client *client)
{
	int err;
	struct rtc_time tm;

	memset(&tm, 0, sizeof(tm));

	err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
	if (err < 0)
		dev_err(&client->dev, "unable to restart the oscillator\n");

	return err;
}

static int x1205_get_dtrim(struct i2c_client *client, int *trim)
{
	unsigned char dtr;
	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };

	struct i2c_msg msgs[] = {
		{	/* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = dtr_addr
		},
		{      /* read dtr */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = &dtr
		},
	};

	/* read dtr register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);

	*trim = 0;

	if (dtr & X1205_DTR_DTR0)
		*trim += 20;

	if (dtr & X1205_DTR_DTR1)
		*trim += 10;

	if (dtr & X1205_DTR_DTR2)
		*trim = -*trim;

	return 0;
}

static int x1205_get_atrim(struct i2c_client *client, int *trim)
{
	s8 atr;
	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };

	struct i2c_msg msgs[] = {
		{/* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = atr_addr
		},
		{/* read atr */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = &atr
		},
	};

	/* read atr register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);

	/* atr is a two's complement value on 6 bits,
	 * perform sign extension. The formula is
	 * Catr = (atr * 0.25pF) + 11.00pF.
	 */
	atr = sign_extend32(atr, 5);

	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);

	*trim = (atr * 250) + 11000;

	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);

	return 0;
}

struct x1205_limit {
	unsigned char reg, mask, min, max;
};

static int x1205_validate_client(struct i2c_client *client)
{
	int i, xfer;

	/* Probe array. We will read the register at the specified
	 * address and check if the given bits are zero.
	 */
	static const unsigned char probe_zero_pattern[] = {
		/* register, mask */
		X1205_REG_SR,	0x18,
		X1205_REG_DTR,	0xF8,
		X1205_REG_ATR,	0xC0,
		X1205_REG_INT,	0x18,
		X1205_REG_0,	0xFF,
	};

	static const struct x1205_limit probe_limits_pattern[] = {
		/* register, mask, min, max */
		{ X1205_REG_Y2K,	0xFF,	19,	20	},
		{ X1205_REG_DW,		0xFF,	0,	6	},
		{ X1205_REG_YR,		0xFF,	0,	99	},
		{ X1205_REG_MO,		0xFF,	0,	12	},
		{ X1205_REG_DT,		0xFF,	0,	31	},
		{ X1205_REG_HR,		0x7F,	0,	23	},
		{ X1205_REG_MN,		0xFF,	0,	59	},
		{ X1205_REG_SC,		0xFF,	0,	59	},
		{ X1205_REG_Y2K1,	0xFF,	19,	20	},
		{ X1205_REG_Y2K0,	0xFF,	19,	20	},
	};

	/* check that registers have bits a 0 where expected */
	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
		unsigned char buf;

		unsigned char addr[2] = { 0, probe_zero_pattern[i] };

		struct i2c_msg msgs[2] = {
			{
				.addr = client->addr,
				.len = 2,
				.buf = addr
			},
			{
				.addr = client->addr,
				.flags = I2C_M_RD,
				.len = 1,
				.buf = &buf
			},
		};

		xfer = i2c_transfer(client->adapter, msgs, 2);
		if (xfer != 2) {
			dev_err(&client->dev,
				"%s: could not read register %x\n",
				__func__, probe_zero_pattern[i]);

			return -EIO;
		}

		if ((buf & probe_zero_pattern[i+1]) != 0) {
			dev_err(&client->dev,
				"%s: register=%02x, zero pattern=%d, value=%x\n",
				__func__, probe_zero_pattern[i], i, buf);

			return -ENODEV;
		}
	}

	/* check limits (only registers with bcd values) */
	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
		unsigned char reg, value;

		unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };

		struct i2c_msg msgs[2] = {
			{
				.addr = client->addr,
				.len = 2,
				.buf = addr
			},
			{
				.addr = client->addr,
				.flags = I2C_M_RD,
				.len = 1,
				.buf = &reg
			},
		};

		xfer = i2c_transfer(client->adapter, msgs, 2);
		if (xfer != 2) {
			dev_err(&client->dev,
				"%s: could not read register %x\n",
				__func__, probe_limits_pattern[i].reg);

			return -EIO;
		}

		value = bcd2bin(reg & probe_limits_pattern[i].mask);

		if (value > probe_limits_pattern[i].max ||
			value < probe_limits_pattern[i].min) {
			dev_dbg(&client->dev,
				"%s: register=%x, lim pattern=%d, value=%d\n",
				__func__, probe_limits_pattern[i].reg,
				i, value);

			return -ENODEV;
		}
	}

	return 0;
}

static int x1205_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int err;
	unsigned char intreg, status;
	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
	struct i2c_client *client = to_i2c_client(dev);
	struct i2c_msg msgs[] = {
		{ /* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = int_addr
		},
		{/* read INT register */

			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = &intreg
		},
	};

	/* read interrupt register and status register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}
	err = x1205_get_status(client, &status);
	if (err == 0) {
		alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
		alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
		err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
	}
	return err;
}

static int x1205_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	return x1205_set_datetime(to_i2c_client(dev),
		&alrm->time, X1205_ALM0_BASE, alrm->enabled);
}

static int x1205_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	return x1205_get_datetime(to_i2c_client(dev),
		tm, X1205_CCR_BASE);
}

static int x1205_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	return x1205_set_datetime(to_i2c_client(dev),
		tm, X1205_CCR_BASE, 0);
}

static int x1205_rtc_proc(struct device *dev, struct seq_file *seq)
{
	int err, dtrim, atrim;

	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	if (!err)
		seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);

	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	if (!err)
		seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
			atrim / 1000, atrim % 1000);
	return 0;
}

static const struct rtc_class_ops x1205_rtc_ops = {
	.proc		= x1205_rtc_proc,
	.read_time	= x1205_rtc_read_time,
	.set_time	= x1205_rtc_set_time,
	.read_alarm	= x1205_rtc_read_alarm,
	.set_alarm	= x1205_rtc_set_alarm,
};

static ssize_t x1205_sysfs_show_atrim(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	int err, atrim;

	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	if (err)
		return err;

	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
}
static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);

static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	int err, dtrim;

	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	if (err)
		return err;

	return sprintf(buf, "%d ppm\n", dtrim);
}
static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);

static int x1205_sysfs_register(struct device *dev)
{
	int err;

	err = device_create_file(dev, &dev_attr_atrim);
	if (err)
		return err;

	err = device_create_file(dev, &dev_attr_dtrim);
	if (err)
		device_remove_file(dev, &dev_attr_atrim);

	return err;
}

static void x1205_sysfs_unregister(struct device *dev)
{
	device_remove_file(dev, &dev_attr_atrim);
	device_remove_file(dev, &dev_attr_dtrim);
}


static int x1205_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	int err = 0;
	unsigned char sr;
	struct rtc_device *rtc;

	dev_dbg(&client->dev, "%s\n", __func__);

	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
		return -ENODEV;

	if (x1205_validate_client(client) < 0)
		return -ENODEV;

	dev_info(&client->dev, "chip found, driver version " DRV_VERSION "\n");

	rtc = devm_rtc_device_register(&client->dev, x1205_driver.driver.name,
					&x1205_rtc_ops, THIS_MODULE);

	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	i2c_set_clientdata(client, rtc);

	/* Check for power failures and eventually enable the osc */
	err = x1205_get_status(client, &sr);
	if (!err) {
		if (sr & X1205_SR_RTCF) {
			dev_err(&client->dev,
				"power failure detected, "
				"please set the clock\n");
			udelay(50);
			x1205_fix_osc(client);
		}
	} else {
		dev_err(&client->dev, "couldn't read status\n");
	}

	err = x1205_sysfs_register(&client->dev);
	if (err)
		dev_err(&client->dev, "Unable to create sysfs entries\n");

	return 0;
}

static int x1205_remove(struct i2c_client *client)
{
	x1205_sysfs_unregister(&client->dev);
	return 0;
}

static const struct i2c_device_id x1205_id[] = {
	{ "x1205", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, x1205_id);

static struct i2c_driver x1205_driver = {
	.driver		= {
		.name	= "rtc-x1205",
	},
	.probe		= x1205_probe,
	.remove		= x1205_remove,
	.id_table	= x1205_id,
};

module_i2c_driver(x1205_driver);

MODULE_AUTHOR(
	"Karen Spearel <kas111 at gmail dot com>, "
	"Alessandro Zummo <a.zummo@towertech.it>");
MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
1fec7c66 AZ	1	/*
	2	* An i2c driver for the Xicor/Intersil X1205 RTC
	3	* Copyright 2004 Karen Spearel
	4	* Copyright 2005 Alessandro Zummo
	5	*
	6	* please send all reports to:
66e3f10c	7	* Karen Spearel <kas111 at gmail dot com>
1fec7c66 AZ	8	* Alessandro Zummo <a.zummo@towertech.it>
	9	*
	10	* based on a lot of other RTC drivers.
	11	*
890e0375 JD	12	* Information and datasheet:
	13	* http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
	14	*
1fec7c66 AZ	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include <linux/i2c.h>
	21	#include <linux/bcd.h>
	22	#include <linux/rtc.h>
	23	#include <linux/delay.h>
2113852b	24	#include <linux/module.h>
86e66604	25	#include <linux/bitops.h>
1fec7c66	26
4edac2b4	27	#define DRV_VERSION "1.0.8"
1fec7c66 AZ	28
	29	/* offsets into CCR area */
	30
	31	#define CCR_SEC 0
	32	#define CCR_MIN 1
	33	#define CCR_HOUR 2
	34	#define CCR_MDAY 3
	35	#define CCR_MONTH 4
	36	#define CCR_YEAR 5
	37	#define CCR_WDAY 6
	38	#define CCR_Y2K 7
	39
	40	#define X1205_REG_SR 0x3F /* status register */
	41	#define X1205_REG_Y2K 0x37
	42	#define X1205_REG_DW 0x36
	43	#define X1205_REG_YR 0x35
	44	#define X1205_REG_MO 0x34
	45	#define X1205_REG_DT 0x33
	46	#define X1205_REG_HR 0x32
	47	#define X1205_REG_MN 0x31
	48	#define X1205_REG_SC 0x30
	49	#define X1205_REG_DTR 0x13
	50	#define X1205_REG_ATR 0x12
	51	#define X1205_REG_INT 0x11
	52	#define X1205_REG_0 0x10
	53	#define X1205_REG_Y2K1 0x0F
	54	#define X1205_REG_DWA1 0x0E
	55	#define X1205_REG_YRA1 0x0D
	56	#define X1205_REG_MOA1 0x0C
	57	#define X1205_REG_DTA1 0x0B
	58	#define X1205_REG_HRA1 0x0A
	59	#define X1205_REG_MNA1 0x09
	60	#define X1205_REG_SCA1 0x08
	61	#define X1205_REG_Y2K0 0x07
	62	#define X1205_REG_DWA0 0x06
	63	#define X1205_REG_YRA0 0x05
	64	#define X1205_REG_MOA0 0x04
	65	#define X1205_REG_DTA0 0x03
	66	#define X1205_REG_HRA0 0x02
	67	#define X1205_REG_MNA0 0x01
	68	#define X1205_REG_SCA0 0x00
	69
	70	#define X1205_CCR_BASE 0x30 /* Base address of CCR */
	71	#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
	72
	73	#define X1205_SR_RTCF 0x01 /* Clock failure */
	74	#define X1205_SR_WEL 0x02 /* Write Enable Latch */
	75	#define X1205_SR_RWEL 0x04 /* Register Write Enable */
471d47e3	76	#define X1205_SR_AL0 0x20 /* Alarm 0 match */
1fec7c66 AZ	77
	78	#define X1205_DTR_DTR0 0x01
	79	#define X1205_DTR_DTR1 0x02
	80	#define X1205_DTR_DTR2 0x04
	81
	82	#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
	83
471d47e3 MH	84	#define X1205_INT_AL0E 0x20 /* Alarm 0 enable */
471d47e3 MH	85
4edac2b4	86	static struct i2c_driver x1205_driver;
1fec7c66 AZ	87
	88	/*
	89	* In the routines that deal directly with the x1205 hardware, we use
	90	* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
	91	* Epoch is initialized as 2000. Time is set to UTC.
	92	*/
	93	static int x1205_get_datetime(struct i2c_client client, struct rtc_time tm,
	94	unsigned char reg_base)
	95	{
	96	unsigned char dt_addr[2] = { 0, reg_base };
1fec7c66	97	unsigned char buf[8];
471d47e3	98	int i;
1fec7c66 AZ	99
1fec7c66 AZ	100	struct i2c_msg msgs[] = {
c3fe92b7 S	101	{/* setup read ptr */
	102	.addr = client->addr,
	103	.len = 2,
	104	.buf = dt_addr
	105	},
	106	{/* read date */
	107	.addr = client->addr,
	108	.flags = I2C_M_RD,
	109	.len = 8,
	110	.buf = buf
	111	},
1fec7c66 AZ	112	};
	113
	114	/* read date registers */
471d47e3	115	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	116	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	117	return -EIO;
	118	}
	119
	120	dev_dbg(&client->dev,
	121	"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
	122	"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
2a4e2b87	123	__func__,
1fec7c66 AZ	124	buf[0], buf[1], buf[2], buf[3],
	125	buf[4], buf[5], buf[6], buf[7]);
	126
471d47e3 MH	127	/* Mask out the enable bits if these are alarm registers */
	128	if (reg_base < X1205_CCR_BASE)
	129	for (i = 0; i <= 4; i++)
	130	buf[i] &= 0x7F;
	131
fe20ba70 AB	132	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
	133	tm->tm_min = bcd2bin(buf[CCR_MIN]);
	134	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	135	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
	136	tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
	137	tm->tm_year = bcd2bin(buf[CCR_YEAR])
	138	+ (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
1fec7c66 AZ	139	tm->tm_wday = buf[CCR_WDAY];
	140
	141	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	142	"mday=%d, mon=%d, year=%d, wday=%d\n",
2a4e2b87	143	__func__,
1fec7c66 AZ	144	tm->tm_sec, tm->tm_min, tm->tm_hour,
	145	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	146
	147	return 0;
	148	}
	149
	150	static int x1205_get_status(struct i2c_client client, unsigned char sr)
	151	{
	152	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };
	153
	154	struct i2c_msg msgs[] = {
c3fe92b7 S	155	{ /* setup read ptr */
	156	.addr = client->addr,
	157	.len = 2,
	158	.buf = sr_addr
	159	},
	160	{ /* read status */
	161	.addr = client->addr,
	162	.flags = I2C_M_RD,
	163	.len = 1,
	164	.buf = sr
	165	},
1fec7c66 AZ	166	};
	167
	168	/* read status register */
471d47e3	169	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	170	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	171	return -EIO;
	172	}
	173
	174	return 0;
	175	}
	176
	177	static int x1205_set_datetime(struct i2c_client client, struct rtc_time tm,
d973b632	178	u8 reg_base, unsigned char alm_enable)
1fec7c66	179	{
d973b632	180	int i, xfer;
471d47e3	181	unsigned char rdata[10] = { 0, reg_base };
d973b632	182	unsigned char *buf = rdata + 2;
1fec7c66 AZ	183
	184	static const unsigned char wel[3] = { 0, X1205_REG_SR,
	185	X1205_SR_WEL };
	186
	187	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
	188	X1205_SR_WEL \| X1205_SR_RWEL };
	189
	190	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };
	191
	192	dev_dbg(&client->dev,
d973b632 JW	193	"%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
	194	__func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
	195	tm->tm_mon, tm->tm_year, tm->tm_wday);
1fec7c66	196
fe20ba70 AB	197	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
fe20ba70 AB	198	buf[CCR_MIN] = bin2bcd(tm->tm_min);
1fec7c66 AZ	199
1fec7c66 AZ	200	/* set hour and 24hr bit */
fe20ba70	201	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) \| X1205_HR_MIL;
1fec7c66	202
d973b632	203	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
1fec7c66	204
d973b632 JW	205	/* month, 1 - 12 */
d973b632 JW	206	buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);
1fec7c66	207
d973b632 JW	208	/* year, since the rtc epoch*/
	209	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
	210	buf[CCR_WDAY] = tm->tm_wday & 0x07;
	211	buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);
1fec7c66	212
471d47e3 MH	213	/* If writing alarm registers, set compare bits on registers 0-4 */
	214	if (reg_base < X1205_CCR_BASE)
	215	for (i = 0; i <= 4; i++)
	216	buf[i] \|= 0x80;
	217
1fec7c66	218	/* this sequence is required to unlock the chip */
66e3f10c SK	219	xfer = i2c_master_send(client, wel, 3);
66e3f10c SK	220	if (xfer != 3) {
2a4e2b87	221	dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
1fec7c66 AZ	222	return -EIO;
	223	}
	224
66e3f10c SK	225	xfer = i2c_master_send(client, rwel, 3);
66e3f10c SK	226	if (xfer != 3) {
2a4e2b87	227	dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
1fec7c66 AZ	228	return -EIO;
	229	}
	230
d973b632 JW	231	xfer = i2c_master_send(client, rdata, sizeof(rdata));
d973b632 JW	232	if (xfer != sizeof(rdata)) {
471d47e3 MH	233	dev_err(&client->dev,
	234	"%s: result=%d addr=%02x, data=%02x\n",
	235	__func__,
	236	xfer, rdata[1], rdata[2]);
	237	return -EIO;
	238	}
	239
	240	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
	241	if (reg_base < X1205_CCR_BASE) {
	242	unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };
	243
	244	msleep(10);
	245
	246	/* ...and set or clear the AL0E bit in the INT register */
1fec7c66	247
471d47e3 MH	248	/* Need to set RWEL again as the write has cleared it */
471d47e3 MH	249	xfer = i2c_master_send(client, rwel, 3);
1fec7c66 AZ	250	if (xfer != 3) {
1fec7c66 AZ	251	dev_err(&client->dev,
471d47e3	252	"%s: aloe rwel - %d\n",
2a4e2b87	253	__func__,
471d47e3 MH	254	xfer);
	255	return -EIO;
	256	}
	257
	258	if (alm_enable)
	259	al0e[2] = X1205_INT_AL0E;
	260
	261	xfer = i2c_master_send(client, al0e, 3);
	262	if (xfer != 3) {
	263	dev_err(&client->dev,
	264	"%s: al0e - %d\n",
	265	__func__,
	266	xfer);
1fec7c66 AZ	267	return -EIO;
1fec7c66 AZ	268	}
471d47e3 MH	269
	270	/* and wait 10msec again for this write to complete */
	271	msleep(10);
	272	}
1fec7c66 AZ	273
1fec7c66 AZ	274	/* disable further writes */
66e3f10c SK	275	xfer = i2c_master_send(client, diswe, 3);
66e3f10c SK	276	if (xfer != 3) {
2a4e2b87	277	dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
1fec7c66 AZ	278	return -EIO;
	279	}
	280
	281	return 0;
	282	}
	283
	284	static int x1205_fix_osc(struct i2c_client *client)
	285	{
	286	int err;
	287	struct rtc_time tm;
	288
cb8799ee	289	memset(&tm, 0, sizeof(tm));
1fec7c66	290
d973b632	291	err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
471d47e3 MH	292	if (err < 0)
471d47e3 MH	293	dev_err(&client->dev, "unable to restart the oscillator\n");
1fec7c66 AZ	294
	295	return err;
	296	}
	297
	298	static int x1205_get_dtrim(struct i2c_client client, int trim)
	299	{
	300	unsigned char dtr;
	301	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };
	302
	303	struct i2c_msg msgs[] = {
c3fe92b7 S	304	{ /* setup read ptr */
	305	.addr = client->addr,
	306	.len = 2,
	307	.buf = dtr_addr
	308	},
	309	{ /* read dtr */
	310	.addr = client->addr,
	311	.flags = I2C_M_RD,
	312	.len = 1,
	313	.buf = &dtr
	314	},
1fec7c66 AZ	315	};
	316
	317	/* read dtr register */
471d47e3	318	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	319	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	320	return -EIO;
	321	}
	322
2a4e2b87	323	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);
1fec7c66 AZ	324
	325	*trim = 0;
	326
	327	if (dtr & X1205_DTR_DTR0)
	328	*trim += 20;
	329
	330	if (dtr & X1205_DTR_DTR1)
	331	*trim += 10;
	332
	333	if (dtr & X1205_DTR_DTR2)
	334	trim = -trim;
	335
	336	return 0;
	337	}
	338
	339	static int x1205_get_atrim(struct i2c_client client, int trim)
	340	{
	341	s8 atr;
	342	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };
	343
	344	struct i2c_msg msgs[] = {
c3fe92b7 S	345	{/* setup read ptr */
	346	.addr = client->addr,
	347	.len = 2,
	348	.buf = atr_addr
	349	},
	350	{/* read atr */
	351	.addr = client->addr,
	352	.flags = I2C_M_RD,
	353	.len = 1,
	354	.buf = &atr
	355	},
1fec7c66 AZ	356	};
	357
	358	/* read atr register */
471d47e3	359	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	360	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	361	return -EIO;
	362	}
	363
2a4e2b87	364	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);
1fec7c66 AZ	365
	366	/* atr is a two's complement value on 6 bits,
	367	* perform sign extension. The formula is
	368	* Catr = (atr * 0.25pF) + 11.00pF.
	369	*/
86e66604	370	atr = sign_extend32(atr, 5);
1fec7c66	371
2a4e2b87	372	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);
1fec7c66 AZ	373
	374	trim = (atr 250) + 11000;
	375
2a4e2b87	376	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);
1fec7c66 AZ	377
	378	return 0;
	379	}
	380
66e3f10c	381	struct x1205_limit {
1fec7c66 AZ	382	unsigned char reg, mask, min, max;
	383	};
	384
	385	static int x1205_validate_client(struct i2c_client *client)
	386	{
	387	int i, xfer;
	388
	389	/* Probe array. We will read the register at the specified
	390	* address and check if the given bits are zero.
	391	*/
	392	static const unsigned char probe_zero_pattern[] = {
	393	/* register, mask */
	394	X1205_REG_SR, 0x18,
	395	X1205_REG_DTR, 0xF8,
	396	X1205_REG_ATR, 0xC0,
	397	X1205_REG_INT, 0x18,
	398	X1205_REG_0, 0xFF,
	399	};
	400
	401	static const struct x1205_limit probe_limits_pattern[] = {
	402	/* register, mask, min, max */
	403	{ X1205_REG_Y2K, 0xFF, 19, 20 },
	404	{ X1205_REG_DW, 0xFF, 0, 6 },
	405	{ X1205_REG_YR, 0xFF, 0, 99 },
	406	{ X1205_REG_MO, 0xFF, 0, 12 },
	407	{ X1205_REG_DT, 0xFF, 0, 31 },
	408	{ X1205_REG_HR, 0x7F, 0, 23 },
	409	{ X1205_REG_MN, 0xFF, 0, 59 },
	410	{ X1205_REG_SC, 0xFF, 0, 59 },
	411	{ X1205_REG_Y2K1, 0xFF, 19, 20 },
	412	{ X1205_REG_Y2K0, 0xFF, 19, 20 },
	413	};
	414
	415	/* check that registers have bits a 0 where expected */
	416	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
	417	unsigned char buf;
	418
	419	unsigned char addr[2] = { 0, probe_zero_pattern[i] };
	420
	421	struct i2c_msg msgs[2] = {
c3fe92b7 S	422	{
	423	.addr = client->addr,
	424	.len = 2,
	425	.buf = addr
	426	},
	427	{
	428	.addr = client->addr,
	429	.flags = I2C_M_RD,
	430	.len = 1,
	431	.buf = &buf
	432	},
1fec7c66 AZ	433	};
1fec7c66 AZ	434
66e3f10c SK	435	xfer = i2c_transfer(client->adapter, msgs, 2);
66e3f10c SK	436	if (xfer != 2) {
a14e1893	437	dev_err(&client->dev,
1fec7c66	438	"%s: could not read register %x\n",
2a4e2b87	439	__func__, probe_zero_pattern[i]);
1fec7c66 AZ	440
	441	return -EIO;
	442	}
	443
	444	if ((buf & probe_zero_pattern[i+1]) != 0) {
a14e1893	445	dev_err(&client->dev,
1fec7c66	446	"%s: register=%02x, zero pattern=%d, value=%x\n",
2a4e2b87	447	__func__, probe_zero_pattern[i], i, buf);
1fec7c66 AZ	448
	449	return -ENODEV;
	450	}
	451	}
	452
	453	/* check limits (only registers with bcd values) */
	454	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
	455	unsigned char reg, value;
	456
	457	unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };
	458
	459	struct i2c_msg msgs[2] = {
c3fe92b7 S	460	{
	461	.addr = client->addr,
	462	.len = 2,
	463	.buf = addr
	464	},
	465	{
	466	.addr = client->addr,
	467	.flags = I2C_M_RD,
	468	.len = 1,
	469	.buf = &reg
	470	},
1fec7c66 AZ	471	};
1fec7c66 AZ	472
66e3f10c SK	473	xfer = i2c_transfer(client->adapter, msgs, 2);
66e3f10c SK	474	if (xfer != 2) {
a14e1893	475	dev_err(&client->dev,
1fec7c66	476	"%s: could not read register %x\n",
2a4e2b87	477	__func__, probe_limits_pattern[i].reg);
1fec7c66 AZ	478
	479	return -EIO;
	480	}
	481
fe20ba70	482	value = bcd2bin(reg & probe_limits_pattern[i].mask);
1fec7c66 AZ	483
	484	if (value > probe_limits_pattern[i].max \|\|
	485	value < probe_limits_pattern[i].min) {
a14e1893	486	dev_dbg(&client->dev,
1fec7c66	487	"%s: register=%x, lim pattern=%d, value=%d\n",
2a4e2b87	488	__func__, probe_limits_pattern[i].reg,
1fec7c66 AZ	489	i, value);
	490
	491	return -ENODEV;
	492	}
	493	}
	494
	495	return 0;
	496	}
	497
	498	static int x1205_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	499	{
471d47e3 MH	500	int err;
	501	unsigned char intreg, status;
	502	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
	503	struct i2c_client *client = to_i2c_client(dev);
	504	struct i2c_msg msgs[] = {
c3fe92b7 S	505	{ /* setup read ptr */
	506	.addr = client->addr,
	507	.len = 2,
	508	.buf = int_addr
	509	},
	510	{/* read INT register */
	511
	512	.addr = client->addr,
	513	.flags = I2C_M_RD,
	514	.len = 1,
	515	.buf = &intreg
	516	},
471d47e3 MH	517	};
	518
	519	/* read interrupt register and status register */
	520	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
	521	dev_err(&client->dev, "%s: read error\n", __func__);
	522	return -EIO;
	523	}
	524	err = x1205_get_status(client, &status);
	525	if (err == 0) {
	526	alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
	527	alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
	528	err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
	529	}
	530	return err;
1fec7c66 AZ	531	}
	532
	533	static int x1205_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	534	{
	535	return x1205_set_datetime(to_i2c_client(dev),
d973b632	536	&alrm->time, X1205_ALM0_BASE, alrm->enabled);
1fec7c66 AZ	537	}
	538
	539	static int x1205_rtc_read_time(struct device dev, struct rtc_time tm)
	540	{
	541	return x1205_get_datetime(to_i2c_client(dev),
	542	tm, X1205_CCR_BASE);
	543	}
	544
	545	static int x1205_rtc_set_time(struct device dev, struct rtc_time tm)
	546	{
	547	return x1205_set_datetime(to_i2c_client(dev),
d973b632	548	tm, X1205_CCR_BASE, 0);
1fec7c66 AZ	549	}
	550
	551	static int x1205_rtc_proc(struct device dev, struct seq_file seq)
	552	{
	553	int err, dtrim, atrim;
	554
66e3f10c SK	555	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
66e3f10c SK	556	if (!err)
1fec7c66 AZ	557	seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);
1fec7c66 AZ	558
66e3f10c SK	559	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
66e3f10c SK	560	if (!err)
1fec7c66 AZ	561	seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
	562	atrim / 1000, atrim % 1000);
	563	return 0;
	564	}
	565
ff8371ac	566	static const struct rtc_class_ops x1205_rtc_ops = {
1fec7c66 AZ	567	.proc = x1205_rtc_proc,
	568	.read_time = x1205_rtc_read_time,
	569	.set_time = x1205_rtc_set_time,
	570	.read_alarm = x1205_rtc_read_alarm,
	571	.set_alarm = x1205_rtc_set_alarm,
	572	};
	573
	574	static ssize_t x1205_sysfs_show_atrim(struct device *dev,
	575	struct device_attribute attr, char buf)
	576	{
015aefbb	577	int err, atrim;
1fec7c66	578
015aefbb AZ	579	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	580	if (err)
	581	return err;
	582
	583	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
1fec7c66 AZ	584	}
	585	static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);
	586
	587	static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
	588	struct device_attribute attr, char buf)
	589	{
015aefbb	590	int err, dtrim;
1fec7c66	591
015aefbb AZ	592	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	593	if (err)
	594	return err;
1fec7c66	595
015aefbb	596	return sprintf(buf, "%d ppm\n", dtrim);
1fec7c66 AZ	597	}
	598	static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);
	599
4edac2b4 AZ	600	static int x1205_sysfs_register(struct device *dev)
	601	{
	602	int err;
	603
	604	err = device_create_file(dev, &dev_attr_atrim);
	605	if (err)
	606	return err;
	607
	608	err = device_create_file(dev, &dev_attr_dtrim);
	609	if (err)
	610	device_remove_file(dev, &dev_attr_atrim);
	611
	612	return err;
	613	}
	614
	615	static void x1205_sysfs_unregister(struct device *dev)
1fec7c66	616	{
4edac2b4 AZ	617	device_remove_file(dev, &dev_attr_atrim);
4edac2b4 AZ	618	device_remove_file(dev, &dev_attr_dtrim);
1fec7c66 AZ	619	}
1fec7c66 AZ	620
4edac2b4	621
d2653e92 JD	622	static int x1205_probe(struct i2c_client *client,
d2653e92 JD	623	const struct i2c_device_id *id)
1fec7c66 AZ	624	{
	625	int err = 0;
	626	unsigned char sr;
1fec7c66 AZ	627	struct rtc_device *rtc;
1fec7c66 AZ	628
4edac2b4	629	dev_dbg(&client->dev, "%s\n", __func__);
1fec7c66	630
4edac2b4 AZ	631	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
4edac2b4 AZ	632	return -ENODEV;
1fec7c66	633
4edac2b4 AZ	634	if (x1205_validate_client(client) < 0)
4edac2b4 AZ	635	return -ENODEV;
1fec7c66 AZ	636
	637	dev_info(&client->dev, "chip found, driver version " DRV_VERSION "\n");
	638
17581718 JH	639	rtc = devm_rtc_device_register(&client->dev, x1205_driver.driver.name,
17581718 JH	640	&x1205_rtc_ops, THIS_MODULE);
1fec7c66	641
4edac2b4 AZ	642	if (IS_ERR(rtc))
4edac2b4 AZ	643	return PTR_ERR(rtc);
1fec7c66 AZ	644
	645	i2c_set_clientdata(client, rtc);
	646
25985edc	647	/* Check for power failures and eventually enable the osc */
66e3f10c SK	648	err = x1205_get_status(client, &sr);
66e3f10c SK	649	if (!err) {
1fec7c66 AZ	650	if (sr & X1205_SR_RTCF) {
	651	dev_err(&client->dev,
	652	"power failure detected, "
	653	"please set the clock\n");
	654	udelay(50);
	655	x1205_fix_osc(client);
	656	}
66e3f10c	657	} else {
1fec7c66	658	dev_err(&client->dev, "couldn't read status\n");
66e3f10c	659	}
1fec7c66	660
4edac2b4 AZ	661	err = x1205_sysfs_register(&client->dev);
4edac2b4 AZ	662	if (err)
4071ea25	663	dev_err(&client->dev, "Unable to create sysfs entries\n");
1fec7c66 AZ	664
1fec7c66 AZ	665	return 0;
1fec7c66 AZ	666	}
1fec7c66 AZ	667
4edac2b4	668	static int x1205_remove(struct i2c_client *client)
1fec7c66	669	{
4edac2b4	670	x1205_sysfs_unregister(&client->dev);
1fec7c66 AZ	671	return 0;
	672	}
	673
3760f736 JD	674	static const struct i2c_device_id x1205_id[] = {
	675	{ "x1205", 0 },
	676	{ }
	677	};
	678	MODULE_DEVICE_TABLE(i2c, x1205_id);
	679
4edac2b4 AZ	680	static struct i2c_driver x1205_driver = {
	681	.driver = {
	682	.name = "rtc-x1205",
	683	},
	684	.probe = x1205_probe,
	685	.remove = x1205_remove,
3760f736	686	.id_table = x1205_id,
4edac2b4 AZ	687	};
4edac2b4 AZ	688
0abc9201	689	module_i2c_driver(x1205_driver);
1fec7c66 AZ	690
	691	MODULE_AUTHOR(
	692	"Karen Spearel <kas111 at gmail dot com>, "
	693	"Alessandro Zummo <a.zummo@towertech.it>");
	694	MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
	695	MODULE_LICENSE("GPL");
	696	MODULE_VERSION(DRV_VERSION);