[linux-2.6-block.git] / drivers / rtc / rtc-twl.c

/*
 * rtc-twl.c -- TWL Real Time Clock interface
 *
 * Copyright (C) 2007 MontaVista Software, Inc
 * Author: Alexandre Rusev <source@mvista.com>
 *
 * Based on original TI driver twl4030-rtc.c
 *   Copyright (C) 2006 Texas Instruments, Inc.
 *
 * Based on rtc-omap.c
 *   Copyright (C) 2003 MontaVista Software, Inc.
 *   Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
 *   Copyright (C) 2006 David Brownell
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/of.h>

#include <linux/i2c/twl.h>


/*
 * RTC block register offsets (use TWL_MODULE_RTC)
 */
enum {
	REG_SECONDS_REG = 0,
	REG_MINUTES_REG,
	REG_HOURS_REG,
	REG_DAYS_REG,
	REG_MONTHS_REG,
	REG_YEARS_REG,
	REG_WEEKS_REG,

	REG_ALARM_SECONDS_REG,
	REG_ALARM_MINUTES_REG,
	REG_ALARM_HOURS_REG,
	REG_ALARM_DAYS_REG,
	REG_ALARM_MONTHS_REG,
	REG_ALARM_YEARS_REG,

	REG_RTC_CTRL_REG,
	REG_RTC_STATUS_REG,
	REG_RTC_INTERRUPTS_REG,

	REG_RTC_COMP_LSB_REG,
	REG_RTC_COMP_MSB_REG,
};
static const u8 twl4030_rtc_reg_map[] = {
	[REG_SECONDS_REG] = 0x00,
	[REG_MINUTES_REG] = 0x01,
	[REG_HOURS_REG] = 0x02,
	[REG_DAYS_REG] = 0x03,
	[REG_MONTHS_REG] = 0x04,
	[REG_YEARS_REG] = 0x05,
	[REG_WEEKS_REG] = 0x06,

	[REG_ALARM_SECONDS_REG] = 0x07,
	[REG_ALARM_MINUTES_REG] = 0x08,
	[REG_ALARM_HOURS_REG] = 0x09,
	[REG_ALARM_DAYS_REG] = 0x0A,
	[REG_ALARM_MONTHS_REG] = 0x0B,
	[REG_ALARM_YEARS_REG] = 0x0C,

	[REG_RTC_CTRL_REG] = 0x0D,
	[REG_RTC_STATUS_REG] = 0x0E,
	[REG_RTC_INTERRUPTS_REG] = 0x0F,

	[REG_RTC_COMP_LSB_REG] = 0x10,
	[REG_RTC_COMP_MSB_REG] = 0x11,
};
static const u8 twl6030_rtc_reg_map[] = {
	[REG_SECONDS_REG] = 0x00,
	[REG_MINUTES_REG] = 0x01,
	[REG_HOURS_REG] = 0x02,
	[REG_DAYS_REG] = 0x03,
	[REG_MONTHS_REG] = 0x04,
	[REG_YEARS_REG] = 0x05,
	[REG_WEEKS_REG] = 0x06,

	[REG_ALARM_SECONDS_REG] = 0x08,
	[REG_ALARM_MINUTES_REG] = 0x09,
	[REG_ALARM_HOURS_REG] = 0x0A,
	[REG_ALARM_DAYS_REG] = 0x0B,
	[REG_ALARM_MONTHS_REG] = 0x0C,
	[REG_ALARM_YEARS_REG] = 0x0D,

	[REG_RTC_CTRL_REG] = 0x10,
	[REG_RTC_STATUS_REG] = 0x11,
	[REG_RTC_INTERRUPTS_REG] = 0x12,

	[REG_RTC_COMP_LSB_REG] = 0x13,
	[REG_RTC_COMP_MSB_REG] = 0x14,
};

/* RTC_CTRL_REG bitfields */
#define BIT_RTC_CTRL_REG_STOP_RTC_M              0x01
#define BIT_RTC_CTRL_REG_ROUND_30S_M             0x02
#define BIT_RTC_CTRL_REG_AUTO_COMP_M             0x04
#define BIT_RTC_CTRL_REG_MODE_12_24_M            0x08
#define BIT_RTC_CTRL_REG_TEST_MODE_M             0x10
#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M        0x20
#define BIT_RTC_CTRL_REG_GET_TIME_M              0x40
#define BIT_RTC_CTRL_REG_RTC_V_OPT               0x80

/* RTC_STATUS_REG bitfields */
#define BIT_RTC_STATUS_REG_RUN_M                 0x02
#define BIT_RTC_STATUS_REG_1S_EVENT_M            0x04
#define BIT_RTC_STATUS_REG_1M_EVENT_M            0x08
#define BIT_RTC_STATUS_REG_1H_EVENT_M            0x10
#define BIT_RTC_STATUS_REG_1D_EVENT_M            0x20
#define BIT_RTC_STATUS_REG_ALARM_M               0x40
#define BIT_RTC_STATUS_REG_POWER_UP_M            0x80

/* RTC_INTERRUPTS_REG bitfields */
#define BIT_RTC_INTERRUPTS_REG_EVERY_M           0x03
#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M        0x04
#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M        0x08


/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
#define ALL_TIME_REGS		6

/*----------------------------------------------------------------------*/
static u8  *rtc_reg_map;

/*
 * Supports 1 byte read from TWL RTC register.
 */
static int twl_rtc_read_u8(u8 *data, u8 reg)
{
	int ret;

	ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
	if (ret < 0)
		pr_err("Could not read TWL register %X - error %d\n", reg, ret);
	return ret;
}

/*
 * Supports 1 byte write to TWL RTC registers.
 */
static int twl_rtc_write_u8(u8 data, u8 reg)
{
	int ret;

	ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
	if (ret < 0)
		pr_err("Could not write TWL register %X - error %d\n",
		       reg, ret);
	return ret;
}

/*
 * Cache the value for timer/alarm interrupts register; this is
 * only changed by callers holding rtc ops lock (or resume).
 */
static unsigned char rtc_irq_bits;

/*
 * Enable 1/second update and/or alarm interrupts.
 */
static int set_rtc_irq_bit(unsigned char bit)
{
	unsigned char val;
	int ret;

	/* if the bit is set, return from here */
	if (rtc_irq_bits & bit)
		return 0;

	val = rtc_irq_bits | bit;
	val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
	if (ret == 0)
		rtc_irq_bits = val;

	return ret;
}

/*
 * Disable update and/or alarm interrupts.
 */
static int mask_rtc_irq_bit(unsigned char bit)
{
	unsigned char val;
	int ret;

	/* if the bit is clear, return from here */
	if (!(rtc_irq_bits & bit))
		return 0;

	val = rtc_irq_bits & ~bit;
	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
	if (ret == 0)
		rtc_irq_bits = val;

	return ret;
}

static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
{
	struct platform_device *pdev = to_platform_device(dev);
	int irq = platform_get_irq(pdev, 0);
	static bool twl_rtc_wake_enabled;
	int ret;

	if (enabled) {
		ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
		if (device_can_wakeup(dev) && !twl_rtc_wake_enabled) {
			enable_irq_wake(irq);
			twl_rtc_wake_enabled = true;
		}
	} else {
		ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
		if (twl_rtc_wake_enabled) {
			disable_irq_wake(irq);
			twl_rtc_wake_enabled = false;
		}
	}

	return ret;
}

/*
 * Gets current TWL RTC time and date parameters.
 *
 * The RTC's time/alarm representation is not what gmtime(3) requires
 * Linux to use:
 *
 *  - Months are 1..12 vs Linux 0-11
 *  - Years are 0..99 vs Linux 1900..N (we assume 21st century)
 */
static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char rtc_data[ALL_TIME_REGS];
	int ret;
	u8 save_control;
	u8 rtc_control;

	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
	if (ret < 0) {
		dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
		return ret;
	}
	/* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
	if (twl_class_is_6030()) {
		if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
			save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
			ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
			if (ret < 0) {
				dev_err(dev, "%s clr GET_TIME, error %d\n",
					__func__, ret);
				return ret;
			}
		}
	}

	/* Copy RTC counting registers to static registers or latches */
	rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;

	/* for twl6030/32 enable read access to static shadowed registers */
	if (twl_class_is_6030())
		rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;

	ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG);
	if (ret < 0) {
		dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
		return ret;
	}

	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
			(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);

	if (ret < 0) {
		dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
		return ret;
	}

	/* for twl6030 restore original state of rtc control register */
	if (twl_class_is_6030()) {
		ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
		if (ret < 0) {
			dev_err(dev, "%s: restore CTRL_REG, error %d\n",
				__func__, ret);
			return ret;
		}
	}

	tm->tm_sec = bcd2bin(rtc_data[0]);
	tm->tm_min = bcd2bin(rtc_data[1]);
	tm->tm_hour = bcd2bin(rtc_data[2]);
	tm->tm_mday = bcd2bin(rtc_data[3]);
	tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
	tm->tm_year = bcd2bin(rtc_data[5]) + 100;

	return ret;
}

static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char save_control;
	unsigned char rtc_data[ALL_TIME_REGS];
	int ret;

	rtc_data[0] = bin2bcd(tm->tm_sec);
	rtc_data[1] = bin2bcd(tm->tm_min);
	rtc_data[2] = bin2bcd(tm->tm_hour);
	rtc_data[3] = bin2bcd(tm->tm_mday);
	rtc_data[4] = bin2bcd(tm->tm_mon + 1);
	rtc_data[5] = bin2bcd(tm->tm_year - 100);

	/* Stop RTC while updating the TC registers */
	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
	if (ret < 0)
		goto out;

	save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	if (ret < 0)
		goto out;

	/* update all the time registers in one shot */
	ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
		(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
	if (ret < 0) {
		dev_err(dev, "rtc_set_time error %d\n", ret);
		goto out;
	}

	/* Start back RTC */
	save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);

out:
	return ret;
}

/*
 * Gets current TWL RTC alarm time.
 */
static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	unsigned char rtc_data[ALL_TIME_REGS];
	int ret;

	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
			(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
	if (ret < 0) {
		dev_err(dev, "rtc_read_alarm error %d\n", ret);
		return ret;
	}

	/* some of these fields may be wildcard/"match all" */
	alm->time.tm_sec = bcd2bin(rtc_data[0]);
	alm->time.tm_min = bcd2bin(rtc_data[1]);
	alm->time.tm_hour = bcd2bin(rtc_data[2]);
	alm->time.tm_mday = bcd2bin(rtc_data[3]);
	alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
	alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;

	/* report cached alarm enable state */
	if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
		alm->enabled = 1;

	return ret;
}

static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	unsigned char alarm_data[ALL_TIME_REGS];
	int ret;

	ret = twl_rtc_alarm_irq_enable(dev, 0);
	if (ret)
		goto out;

	alarm_data[0] = bin2bcd(alm->time.tm_sec);
	alarm_data[1] = bin2bcd(alm->time.tm_min);
	alarm_data[2] = bin2bcd(alm->time.tm_hour);
	alarm_data[3] = bin2bcd(alm->time.tm_mday);
	alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
	alarm_data[5] = bin2bcd(alm->time.tm_year - 100);

	/* update all the alarm registers in one shot */
	ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
		(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
	if (ret) {
		dev_err(dev, "rtc_set_alarm error %d\n", ret);
		goto out;
	}

	if (alm->enabled)
		ret = twl_rtc_alarm_irq_enable(dev, 1);
out:
	return ret;
}

static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
{
	unsigned long events;
	int ret = IRQ_NONE;
	int res;
	u8 rd_reg;

	res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
	if (res)
		goto out;
	/*
	 * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
	 * only one (ALARM or RTC) interrupt source may be enabled
	 * at time, we also could check our results
	 * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
	 */
	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
		events = RTC_IRQF | RTC_AF;
	else
		events = RTC_IRQF | RTC_PF;

	res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
				   REG_RTC_STATUS_REG);
	if (res)
		goto out;

	if (twl_class_is_4030()) {
		/* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
		 * needs 2 reads to clear the interrupt. One read is done in
		 * do_twl_pwrirq(). Doing the second read, to clear
		 * the bit.
		 *
		 * FIXME the reason PWR_ISR1 needs an extra read is that
		 * RTC_IF retriggered until we cleared REG_ALARM_M above.
		 * But re-reading like this is a bad hack; by doing so we
		 * risk wrongly clearing status for some other IRQ (losing
		 * the interrupt).  Be smarter about handling RTC_UF ...
		 */
		res = twl_i2c_read_u8(TWL4030_MODULE_INT,
			&rd_reg, TWL4030_INT_PWR_ISR1);
		if (res)
			goto out;
	}

	/* Notify RTC core on event */
	rtc_update_irq(rtc, 1, events);

	ret = IRQ_HANDLED;
out:
	return ret;
}

static struct rtc_class_ops twl_rtc_ops = {
	.read_time	= twl_rtc_read_time,
	.set_time	= twl_rtc_set_time,
	.read_alarm	= twl_rtc_read_alarm,
	.set_alarm	= twl_rtc_set_alarm,
	.alarm_irq_enable = twl_rtc_alarm_irq_enable,
};

/*----------------------------------------------------------------------*/

static int twl_rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtc;
	int ret = -EINVAL;
	int irq = platform_get_irq(pdev, 0);
	u8 rd_reg;

	if (irq <= 0)
		return ret;

	/* Initialize the register map */
	if (twl_class_is_4030())
		rtc_reg_map = (u8 *)twl4030_rtc_reg_map;
	else
		rtc_reg_map = (u8 *)twl6030_rtc_reg_map;

	ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
	if (ret < 0)
		return ret;

	if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
		dev_warn(&pdev->dev, "Power up reset detected.\n");

	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
		dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");

	/* Clear RTC Power up reset and pending alarm interrupts */
	ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
	if (ret < 0)
		return ret;

	if (twl_class_is_6030()) {
		twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_LINE_A);
		twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_STS_A);
	}

	dev_info(&pdev->dev, "Enabling TWL-RTC\n");
	ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
	if (ret < 0)
		return ret;

	/* ensure interrupts are disabled, bootloaders can be strange */
	ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG);
	if (ret < 0)
		dev_warn(&pdev->dev, "unable to disable interrupt\n");

	/* init cached IRQ enable bits */
	ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
	if (ret < 0)
		return ret;

	device_init_wakeup(&pdev->dev, 1);

	rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
					&twl_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc)) {
		dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
			PTR_ERR(rtc));
		return PTR_ERR(rtc);
	}

	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
					twl_rtc_interrupt,
					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
					dev_name(&rtc->dev), rtc);
	if (ret < 0) {
		dev_err(&pdev->dev, "IRQ is not free.\n");
		return ret;
	}

	platform_set_drvdata(pdev, rtc);
	return 0;
}

/*
 * Disable all TWL RTC module interrupts.
 * Sets status flag to free.
 */
static int twl_rtc_remove(struct platform_device *pdev)
{
	/* leave rtc running, but disable irqs */
	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
	if (twl_class_is_6030()) {
		twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_LINE_A);
		twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_STS_A);
	}

	return 0;
}

static void twl_rtc_shutdown(struct platform_device *pdev)
{
	/* mask timer interrupts, but leave alarm interrupts on to enable
	   power-on when alarm is triggered */
	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
}

#ifdef CONFIG_PM_SLEEP
static unsigned char irqstat;

static int twl_rtc_suspend(struct device *dev)
{
	irqstat = rtc_irq_bits;

	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
	return 0;
}

static int twl_rtc_resume(struct device *dev)
{
	set_rtc_irq_bit(irqstat);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);

#ifdef CONFIG_OF
static const struct of_device_id twl_rtc_of_match[] = {
	{.compatible = "ti,twl4030-rtc", },
	{ },
};
MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
#endif

MODULE_ALIAS("platform:twl_rtc");

static struct platform_driver twl4030rtc_driver = {
	.probe		= twl_rtc_probe,
	.remove		= twl_rtc_remove,
	.shutdown	= twl_rtc_shutdown,
	.driver		= {
		.name		= "twl_rtc",
		.pm		= &twl_rtc_pm_ops,
		.of_match_table = of_match_ptr(twl_rtc_of_match),
	},
};

module_platform_driver(twl4030rtc_driver);

MODULE_AUTHOR("Texas Instruments, MontaVista Software");
MODULE_LICENSE("GPL");
Commit	Line	Data
f96411ab	1	/*
ef3b7d0d	2	* rtc-twl.c -- TWL Real Time Clock interface
f96411ab DB	3	*
	4	* Copyright (C) 2007 MontaVista Software, Inc
	5	* Author: Alexandre Rusev <source@mvista.com>
	6	*
	7	* Based on original TI driver twl4030-rtc.c
	8	* Copyright (C) 2006 Texas Instruments, Inc.
	9	*
	10	* Based on rtc-omap.c
	11	* Copyright (C) 2003 MontaVista Software, Inc.
	12	* Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
	13	* Copyright (C) 2006 David Brownell
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version
	18	* 2 of the License, or (at your option) any later version.
	19	*/
	20
a737e835 JP	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
a737e835 JP	22
f96411ab	23	#include <linux/kernel.h>
2fac6674	24	#include <linux/errno.h>
f96411ab DB	25	#include <linux/init.h>
	26	#include <linux/module.h>
	27	#include <linux/types.h>
	28	#include <linux/rtc.h>
	29	#include <linux/bcd.h>
	30	#include <linux/platform_device.h>
	31	#include <linux/interrupt.h>
c8a6046e	32	#include <linux/of.h>
f96411ab	33
b07682b6	34	#include <linux/i2c/twl.h>
f96411ab DB	35
	36
	37	/*
	38	* RTC block register offsets (use TWL_MODULE_RTC)
	39	*/
a6b49ffd B	40	enum {
	41	REG_SECONDS_REG = 0,
	42	REG_MINUTES_REG,
	43	REG_HOURS_REG,
	44	REG_DAYS_REG,
	45	REG_MONTHS_REG,
	46	REG_YEARS_REG,
	47	REG_WEEKS_REG,
	48
	49	REG_ALARM_SECONDS_REG,
	50	REG_ALARM_MINUTES_REG,
	51	REG_ALARM_HOURS_REG,
	52	REG_ALARM_DAYS_REG,
	53	REG_ALARM_MONTHS_REG,
	54	REG_ALARM_YEARS_REG,
	55
	56	REG_RTC_CTRL_REG,
	57	REG_RTC_STATUS_REG,
	58	REG_RTC_INTERRUPTS_REG,
	59
	60	REG_RTC_COMP_LSB_REG,
	61	REG_RTC_COMP_MSB_REG,
	62	};
2e84067b	63	static const u8 twl4030_rtc_reg_map[] = {
a6b49ffd B	64	[REG_SECONDS_REG] = 0x00,
	65	[REG_MINUTES_REG] = 0x01,
	66	[REG_HOURS_REG] = 0x02,
	67	[REG_DAYS_REG] = 0x03,
	68	[REG_MONTHS_REG] = 0x04,
	69	[REG_YEARS_REG] = 0x05,
	70	[REG_WEEKS_REG] = 0x06,
	71
	72	[REG_ALARM_SECONDS_REG] = 0x07,
	73	[REG_ALARM_MINUTES_REG] = 0x08,
	74	[REG_ALARM_HOURS_REG] = 0x09,
	75	[REG_ALARM_DAYS_REG] = 0x0A,
	76	[REG_ALARM_MONTHS_REG] = 0x0B,
	77	[REG_ALARM_YEARS_REG] = 0x0C,
	78
	79	[REG_RTC_CTRL_REG] = 0x0D,
	80	[REG_RTC_STATUS_REG] = 0x0E,
	81	[REG_RTC_INTERRUPTS_REG] = 0x0F,
	82
	83	[REG_RTC_COMP_LSB_REG] = 0x10,
	84	[REG_RTC_COMP_MSB_REG] = 0x11,
	85	};
2e84067b	86	static const u8 twl6030_rtc_reg_map[] = {
a6b49ffd B	87	[REG_SECONDS_REG] = 0x00,
	88	[REG_MINUTES_REG] = 0x01,
	89	[REG_HOURS_REG] = 0x02,
	90	[REG_DAYS_REG] = 0x03,
	91	[REG_MONTHS_REG] = 0x04,
	92	[REG_YEARS_REG] = 0x05,
	93	[REG_WEEKS_REG] = 0x06,
	94
	95	[REG_ALARM_SECONDS_REG] = 0x08,
	96	[REG_ALARM_MINUTES_REG] = 0x09,
	97	[REG_ALARM_HOURS_REG] = 0x0A,
	98	[REG_ALARM_DAYS_REG] = 0x0B,
	99	[REG_ALARM_MONTHS_REG] = 0x0C,
	100	[REG_ALARM_YEARS_REG] = 0x0D,
	101
	102	[REG_RTC_CTRL_REG] = 0x10,
	103	[REG_RTC_STATUS_REG] = 0x11,
	104	[REG_RTC_INTERRUPTS_REG] = 0x12,
	105
	106	[REG_RTC_COMP_LSB_REG] = 0x13,
	107	[REG_RTC_COMP_MSB_REG] = 0x14,
	108	};
f96411ab DB	109
	110	/* RTC_CTRL_REG bitfields */
	111	#define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
	112	#define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
	113	#define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
	114	#define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
	115	#define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
	116	#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
	117	#define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
f3ec434c	118	#define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80
f96411ab DB	119
	120	/* RTC_STATUS_REG bitfields */
	121	#define BIT_RTC_STATUS_REG_RUN_M 0x02
	122	#define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
	123	#define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
	124	#define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
	125	#define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
	126	#define BIT_RTC_STATUS_REG_ALARM_M 0x40
	127	#define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
	128
	129	/* RTC_INTERRUPTS_REG bitfields */
	130	#define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
	131	#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
	132	#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
	133
	134
	135	/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
	136	#define ALL_TIME_REGS 6
	137
	138	/----------------------------------------------------------------------/
a6b49ffd	139	static u8 *rtc_reg_map;
f96411ab DB	140
f96411ab DB	141	/*
ef3b7d0d	142	* Supports 1 byte read from TWL RTC register.
f96411ab	143	*/
ef3b7d0d	144	static int twl_rtc_read_u8(u8 *data, u8 reg)
f96411ab DB	145	{
	146	int ret;
	147
a6b49ffd	148	ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
f96411ab	149	if (ret < 0)
a737e835	150	pr_err("Could not read TWL register %X - error %d\n", reg, ret);
f96411ab DB	151	return ret;
	152	}
	153
	154	/*
ef3b7d0d	155	* Supports 1 byte write to TWL RTC registers.
f96411ab	156	*/
ef3b7d0d	157	static int twl_rtc_write_u8(u8 data, u8 reg)
f96411ab DB	158	{
	159	int ret;
	160
a6b49ffd	161	ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
f96411ab	162	if (ret < 0)
a737e835 JP	163	pr_err("Could not write TWL register %X - error %d\n",
a737e835 JP	164	reg, ret);
f96411ab DB	165	return ret;
	166	}
	167
	168	/*
	169	* Cache the value for timer/alarm interrupts register; this is
	170	* only changed by callers holding rtc ops lock (or resume).
	171	*/
	172	static unsigned char rtc_irq_bits;
	173
	174	/*
a748384b	175	* Enable 1/second update and/or alarm interrupts.
f96411ab DB	176	*/
	177	static int set_rtc_irq_bit(unsigned char bit)
	178	{
	179	unsigned char val;
	180	int ret;
	181
ce9f6506 VB	182	/* if the bit is set, return from here */
	183	if (rtc_irq_bits & bit)
	184	return 0;
	185
f96411ab	186	val = rtc_irq_bits \| bit;
a748384b	187	val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
ef3b7d0d	188	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
f96411ab DB	189	if (ret == 0)
	190	rtc_irq_bits = val;
	191
	192	return ret;
	193	}
	194
	195	/*
a748384b	196	* Disable update and/or alarm interrupts.
f96411ab DB	197	*/
	198	static int mask_rtc_irq_bit(unsigned char bit)
	199	{
	200	unsigned char val;
	201	int ret;
	202
ce9f6506 VB	203	/* if the bit is clear, return from here */
	204	if (!(rtc_irq_bits & bit))
	205	return 0;
	206
f96411ab	207	val = rtc_irq_bits & ~bit;
ef3b7d0d	208	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
f96411ab DB	209	if (ret == 0)
	210	rtc_irq_bits = val;
	211
	212	return ret;
	213	}
	214
ef3b7d0d	215	static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
f96411ab	216	{
ae845894 KH	217	struct platform_device *pdev = to_platform_device(dev);
	218	int irq = platform_get_irq(pdev, 0);
	219	static bool twl_rtc_wake_enabled;
f96411ab DB	220	int ret;
f96411ab DB	221
ae845894	222	if (enabled) {
f96411ab	223	ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
ae845894 KH	224	if (device_can_wakeup(dev) && !twl_rtc_wake_enabled) {
	225	enable_irq_wake(irq);
	226	twl_rtc_wake_enabled = true;
	227	}
	228	} else {
f96411ab	229	ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
ae845894 KH	230	if (twl_rtc_wake_enabled) {
	231	disable_irq_wake(irq);
	232	twl_rtc_wake_enabled = false;
	233	}
	234	}
f96411ab DB	235
	236	return ret;
	237	}
	238
f96411ab	239	/*
ef3b7d0d	240	* Gets current TWL RTC time and date parameters.
f96411ab DB	241	*
	242	* The RTC's time/alarm representation is not what gmtime(3) requires
	243	* Linux to use:
	244	*
	245	* - Months are 1..12 vs Linux 0-11
	246	* - Years are 0..99 vs Linux 1900..N (we assume 21st century)
	247	*/
ef3b7d0d	248	static int twl_rtc_read_time(struct device dev, struct rtc_time tm)
f96411ab	249	{
14591d88	250	unsigned char rtc_data[ALL_TIME_REGS];
f96411ab DB	251	int ret;
f96411ab DB	252	u8 save_control;
f3ec434c	253	u8 rtc_control;
f96411ab	254
ef3b7d0d	255	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
f3ec434c KS	256	if (ret < 0) {
f3ec434c KS	257	dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
f96411ab	258	return ret;
f3ec434c KS	259	}
	260	/* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
	261	if (twl_class_is_6030()) {
	262	if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
	263	save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
	264	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	265	if (ret < 0) {
	266	dev_err(dev, "%s clr GET_TIME, error %d\n",
	267	__func__, ret);
	268	return ret;
	269	}
	270	}
	271	}
f96411ab	272
f3ec434c KS	273	/* Copy RTC counting registers to static registers or latches */
f3ec434c KS	274	rtc_control = save_control \| BIT_RTC_CTRL_REG_GET_TIME_M;
f96411ab	275
f3ec434c KS	276	/* for twl6030/32 enable read access to static shadowed registers */
	277	if (twl_class_is_6030())
	278	rtc_control \|= BIT_RTC_CTRL_REG_RTC_V_OPT;
	279
	280	ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG);
	281	if (ret < 0) {
	282	dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
f96411ab	283	return ret;
f3ec434c	284	}
f96411ab	285
ef3b7d0d	286	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
a6b49ffd	287	(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	288
f96411ab DB	289	if (ret < 0) {
f3ec434c	290	dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
f96411ab DB	291	return ret;
	292	}
	293
f3ec434c KS	294	/* for twl6030 restore original state of rtc control register */
	295	if (twl_class_is_6030()) {
	296	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	297	if (ret < 0) {
	298	dev_err(dev, "%s: restore CTRL_REG, error %d\n",
	299	__func__, ret);
	300	return ret;
	301	}
	302	}
	303
f96411ab DB	304	tm->tm_sec = bcd2bin(rtc_data[0]);
	305	tm->tm_min = bcd2bin(rtc_data[1]);
	306	tm->tm_hour = bcd2bin(rtc_data[2]);
	307	tm->tm_mday = bcd2bin(rtc_data[3]);
	308	tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
	309	tm->tm_year = bcd2bin(rtc_data[5]) + 100;
	310
	311	return ret;
	312	}
	313
ef3b7d0d	314	static int twl_rtc_set_time(struct device dev, struct rtc_time tm)
f96411ab DB	315	{
f96411ab DB	316	unsigned char save_control;
14591d88	317	unsigned char rtc_data[ALL_TIME_REGS];
f96411ab DB	318	int ret;
f96411ab DB	319
14591d88 PU	320	rtc_data[0] = bin2bcd(tm->tm_sec);
	321	rtc_data[1] = bin2bcd(tm->tm_min);
	322	rtc_data[2] = bin2bcd(tm->tm_hour);
	323	rtc_data[3] = bin2bcd(tm->tm_mday);
	324	rtc_data[4] = bin2bcd(tm->tm_mon + 1);
	325	rtc_data[5] = bin2bcd(tm->tm_year - 100);
f96411ab DB	326
f96411ab DB	327	/* Stop RTC while updating the TC registers */
ef3b7d0d	328	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
f96411ab DB	329	if (ret < 0)
	330	goto out;
	331
	332	save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
8f6b0dd3	333	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
f96411ab DB	334	if (ret < 0)
	335	goto out;
	336
	337	/* update all the time registers in one shot */
ef3b7d0d	338	ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
a6b49ffd	339	(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	340	if (ret < 0) {
	341	dev_err(dev, "rtc_set_time error %d\n", ret);
	342	goto out;
	343	}
	344
	345	/* Start back RTC */
	346	save_control \|= BIT_RTC_CTRL_REG_STOP_RTC_M;
ef3b7d0d	347	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
f96411ab DB	348
	349	out:
	350	return ret;
	351	}
	352
	353	/*
ef3b7d0d	354	* Gets current TWL RTC alarm time.
f96411ab	355	*/
ef3b7d0d	356	static int twl_rtc_read_alarm(struct device dev, struct rtc_wkalrm alm)
f96411ab	357	{
14591d88	358	unsigned char rtc_data[ALL_TIME_REGS];
f96411ab DB	359	int ret;
f96411ab DB	360
ef3b7d0d	361	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
a6b49ffd	362	(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	363	if (ret < 0) {
	364	dev_err(dev, "rtc_read_alarm error %d\n", ret);
	365	return ret;
	366	}
	367
	368	/* some of these fields may be wildcard/"match all" */
	369	alm->time.tm_sec = bcd2bin(rtc_data[0]);
	370	alm->time.tm_min = bcd2bin(rtc_data[1]);
	371	alm->time.tm_hour = bcd2bin(rtc_data[2]);
	372	alm->time.tm_mday = bcd2bin(rtc_data[3]);
	373	alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
	374	alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
	375
	376	/* report cached alarm enable state */
	377	if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
	378	alm->enabled = 1;
	379
	380	return ret;
	381	}
	382
ef3b7d0d	383	static int twl_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm)
f96411ab	384	{
14591d88	385	unsigned char alarm_data[ALL_TIME_REGS];
f96411ab DB	386	int ret;
f96411ab DB	387
ef3b7d0d	388	ret = twl_rtc_alarm_irq_enable(dev, 0);
f96411ab DB	389	if (ret)
	390	goto out;
	391
14591d88 PU	392	alarm_data[0] = bin2bcd(alm->time.tm_sec);
	393	alarm_data[1] = bin2bcd(alm->time.tm_min);
	394	alarm_data[2] = bin2bcd(alm->time.tm_hour);
	395	alarm_data[3] = bin2bcd(alm->time.tm_mday);
	396	alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
	397	alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
f96411ab DB	398
f96411ab DB	399	/* update all the alarm registers in one shot */
ef3b7d0d	400	ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
a6b49ffd	401	(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	402	if (ret) {
	403	dev_err(dev, "rtc_set_alarm error %d\n", ret);
	404	goto out;
	405	}
	406
	407	if (alm->enabled)
ef3b7d0d	408	ret = twl_rtc_alarm_irq_enable(dev, 1);
f96411ab DB	409	out:
	410	return ret;
	411	}
	412
ef3b7d0d	413	static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
f96411ab	414	{
2778ebcc	415	unsigned long events;
f96411ab DB	416	int ret = IRQ_NONE;
	417	int res;
	418	u8 rd_reg;
	419
ef3b7d0d	420	res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
f96411ab DB	421	if (res)
	422	goto out;
	423	/*
	424	* Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
	425	* only one (ALARM or RTC) interrupt source may be enabled
	426	* at time, we also could check our results
	427	* by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
	428	*/
	429	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
2778ebcc	430	events = RTC_IRQF \| RTC_AF;
f96411ab	431	else
2778ebcc	432	events = RTC_IRQF \| RTC_PF;
f96411ab	433
94a339d0	434	res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
f96411ab DB	435	REG_RTC_STATUS_REG);
	436	if (res)
	437	goto out;
	438
a6b49ffd B	439	if (twl_class_is_4030()) {
	440	/* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
	441	* needs 2 reads to clear the interrupt. One read is done in
	442	* do_twl_pwrirq(). Doing the second read, to clear
	443	* the bit.
	444	*
	445	* FIXME the reason PWR_ISR1 needs an extra read is that
	446	* RTC_IF retriggered until we cleared REG_ALARM_M above.
	447	* But re-reading like this is a bad hack; by doing so we
	448	* risk wrongly clearing status for some other IRQ (losing
	449	* the interrupt). Be smarter about handling RTC_UF ...
	450	*/
	451	res = twl_i2c_read_u8(TWL4030_MODULE_INT,
f96411ab	452	&rd_reg, TWL4030_INT_PWR_ISR1);
a6b49ffd B	453	if (res)
	454	goto out;
	455	}
f96411ab DB	456
	457	/* Notify RTC core on event */
	458	rtc_update_irq(rtc, 1, events);
	459
	460	ret = IRQ_HANDLED;
	461	out:
	462	return ret;
	463	}
	464
ef3b7d0d B	465	static struct rtc_class_ops twl_rtc_ops = {
	466	.read_time = twl_rtc_read_time,
	467	.set_time = twl_rtc_set_time,
	468	.read_alarm = twl_rtc_read_alarm,
	469	.set_alarm = twl_rtc_set_alarm,
	470	.alarm_irq_enable = twl_rtc_alarm_irq_enable,
f96411ab DB	471	};
	472
	473	/----------------------------------------------------------------------/
	474
5a167f45	475	static int twl_rtc_probe(struct platform_device *pdev)
f96411ab DB	476	{
f96411ab DB	477	struct rtc_device *rtc;
7e72c686	478	int ret = -EINVAL;
f96411ab DB	479	int irq = platform_get_irq(pdev, 0);
	480	u8 rd_reg;
	481
2fac6674	482	if (irq <= 0)
f53eeb85	483	return ret;
f96411ab	484
d3869ff6 PU	485	/* Initialize the register map */
	486	if (twl_class_is_4030())
	487	rtc_reg_map = (u8 *)twl4030_rtc_reg_map;
	488	else
	489	rtc_reg_map = (u8 *)twl6030_rtc_reg_map;
	490
ef3b7d0d	491	ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
f96411ab	492	if (ret < 0)
f53eeb85	493	return ret;
f96411ab DB	494
	495	if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
	496	dev_warn(&pdev->dev, "Power up reset detected.\n");
	497
	498	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
	499	dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
	500
	501	/* Clear RTC Power up reset and pending alarm interrupts */
ef3b7d0d	502	ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
f96411ab	503	if (ret < 0)
f53eeb85	504	return ret;
f96411ab	505
a6b49ffd B	506	if (twl_class_is_6030()) {
	507	twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
	508	REG_INT_MSK_LINE_A);
	509	twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
	510	REG_INT_MSK_STS_A);
	511	}
	512
f7439bcb VB	513	dev_info(&pdev->dev, "Enabling TWL-RTC\n");
f7439bcb VB	514	ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
f96411ab	515	if (ret < 0)
f53eeb85	516	return ret;
f96411ab	517
8dcebaa9 KH	518	/* ensure interrupts are disabled, bootloaders can be strange */
	519	ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG);
	520	if (ret < 0)
	521	dev_warn(&pdev->dev, "unable to disable interrupt\n");
	522
f96411ab	523	/* init cached IRQ enable bits */
ef3b7d0d	524	ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
f96411ab	525	if (ret < 0)
f53eeb85	526	return ret;
7e72c686	527
b99b94b5 GS	528	device_init_wakeup(&pdev->dev, 1);
b99b94b5 GS	529
f53eeb85 JH	530	rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
f53eeb85 JH	531	&twl_rtc_ops, THIS_MODULE);
7e72c686	532	if (IS_ERR(rtc)) {
7e72c686 TP	533	dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
7e72c686 TP	534	PTR_ERR(rtc));
f53eeb85	535	return PTR_ERR(rtc);
7e72c686 TP	536	}
7e72c686 TP	537
f53eeb85 JH	538	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
	539	twl_rtc_interrupt,
	540	IRQF_TRIGGER_RISING \| IRQF_ONESHOT,
	541	dev_name(&rtc->dev), rtc);
7e72c686 TP	542	if (ret < 0) {
7e72c686 TP	543	dev_err(&pdev->dev, "IRQ is not free.\n");
f53eeb85	544	return ret;
7e72c686	545	}
f96411ab	546
7e72c686 TP	547	platform_set_drvdata(pdev, rtc);
7e72c686 TP	548	return 0;
f96411ab DB	549	}
	550
	551	/*
ef3b7d0d	552	* Disable all TWL RTC module interrupts.
f96411ab DB	553	* Sets status flag to free.
f96411ab DB	554	*/
5a167f45	555	static int twl_rtc_remove(struct platform_device *pdev)
f96411ab DB	556	{
f96411ab DB	557	/* leave rtc running, but disable irqs */
f96411ab DB	558	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
f96411ab DB	559	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
a6b49ffd B	560	if (twl_class_is_6030()) {
	561	twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
	562	REG_INT_MSK_LINE_A);
	563	twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
	564	REG_INT_MSK_STS_A);
	565	}
	566
f96411ab DB	567	return 0;
	568	}
	569
ef3b7d0d	570	static void twl_rtc_shutdown(struct platform_device *pdev)
f96411ab	571	{
cafa1d8b MH	572	/* mask timer interrupts, but leave alarm interrupts on to enable
	573	power-on when alarm is triggered */
	574	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
f96411ab DB	575	}
f96411ab DB	576
b9d8c460	577	#ifdef CONFIG_PM_SLEEP
f96411ab DB	578	static unsigned char irqstat;
f96411ab DB	579
b9d8c460	580	static int twl_rtc_suspend(struct device *dev)
f96411ab DB	581	{
	582	irqstat = rtc_irq_bits;
	583
f993004d	584	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
f96411ab DB	585	return 0;
	586	}
	587
b9d8c460	588	static int twl_rtc_resume(struct device *dev)
f96411ab DB	589	{
	590	set_rtc_irq_bit(irqstat);
	591	return 0;
	592	}
f96411ab DB	593	#endif
f96411ab DB	594
b9d8c460 JH	595	static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);
b9d8c460 JH	596
c8a6046e	597	#ifdef CONFIG_OF
948170f8 BC	598	static const struct of_device_id twl_rtc_of_match[] = {
	599	{.compatible = "ti,twl4030-rtc", },
	600	{ },
	601	};
	602	MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
c8a6046e SK	603	#endif
c8a6046e SK	604
ef3b7d0d	605	MODULE_ALIAS("platform:twl_rtc");
f96411ab DB	606
f96411ab DB	607	static struct platform_driver twl4030rtc_driver = {
ef3b7d0d	608	.probe = twl_rtc_probe,
5a167f45	609	.remove = twl_rtc_remove,
ef3b7d0d	610	.shutdown = twl_rtc_shutdown,
f96411ab	611	.driver = {
948170f8	612	.name = "twl_rtc",
b9d8c460	613	.pm = &twl_rtc_pm_ops,
c8a6046e	614	.of_match_table = of_match_ptr(twl_rtc_of_match),
f96411ab DB	615	},
	616	};
	617
5ee67484	618	module_platform_driver(twl4030rtc_driver);
f96411ab DB	619
	620	MODULE_AUTHOR("Texas Instruments, MontaVista Software");
	621	MODULE_LICENSE("GPL");