[linux-2.6-block.git] / drivers / rtc / rtc-stmp3xxx.c

/*
 * Freescale STMP37XX/STMP378X Real Time Clock driver
 *
 * Copyright (c) 2007 Sigmatel, Inc.
 * Peter Hartley, <peter.hartley@sigmatel.com>
 *
 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 * Copyright 2011 Wolfram Sang, Pengutronix e.K.
 */

/*
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/stmp_device.h>
#include <linux/stmp3xxx_rtc_wdt.h>

#define STMP3XXX_RTC_CTRL			0x0
#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN		0x00000001
#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN	0x00000002
#define STMP3XXX_RTC_CTRL_ALARM_IRQ		0x00000004
#define STMP3XXX_RTC_CTRL_WATCHDOGEN		0x00000010

#define STMP3XXX_RTC_STAT			0x10
#define STMP3XXX_RTC_STAT_STALE_SHIFT		16
#define STMP3XXX_RTC_STAT_RTC_PRESENT		0x80000000
#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT	0x10000000
#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT	0x08000000

#define STMP3XXX_RTC_SECONDS			0x30

#define STMP3XXX_RTC_ALARM			0x40

#define STMP3XXX_RTC_WATCHDOG			0x50

#define STMP3XXX_RTC_PERSISTENT0		0x60
#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE		(1 << 0)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN		(1 << 1)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN		(1 << 2)
#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP	(1 << 4)
#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP	(1 << 5)
#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ		(1 << 6)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE		(1 << 7)

#define STMP3XXX_RTC_PERSISTENT1		0x70
/* missing bitmask in headers */
#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER	0x80000000

struct stmp3xxx_rtc_data {
	struct rtc_device *rtc;
	void __iomem *io;
	int irq_alarm;
};

#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
/**
 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
 * @dev: the parent device of the watchdog (= the RTC)
 * @timeout: the desired value for the timeout register of the watchdog.
 *           0 disables the watchdog
 *
 * The watchdog needs one register and two bits which are in the RTC domain.
 * To handle the resource conflict, the RTC driver will create another
 * platform_device for the watchdog driver as a child of the RTC device.
 * The watchdog driver is passed the below accessor function via platform_data
 * to configure the watchdog. Locking is not needed because accessing SET/CLR
 * registers is atomic.
 */

static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	if (timeout) {
		writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
		writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
		       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
		writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
		       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
	} else {
		writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
		       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
		writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
		       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
	}
}

static struct stmp3xxx_wdt_pdata wdt_pdata = {
	.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
};

static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
{
	int rc = -1;
	struct platform_device *wdt_pdev =
		platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);

	if (wdt_pdev) {
		wdt_pdev->dev.parent = &rtc_pdev->dev;
		wdt_pdev->dev.platform_data = &wdt_pdata;
		rc = platform_device_add(wdt_pdev);
	}

	if (rc)
		dev_err(&rtc_pdev->dev,
			"failed to register stmp3xxx_rtc_wdt\n");
}
#else
static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
{
}
#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */

static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
{
	int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
	/*
	 * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
	 * states:
	 * | The order in which registers are updated is
	 * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
	 * | (This list is in bitfield order, from LSB to MSB, as they would
	 * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
	 * | register. For example, the Seconds register corresponds to
	 * | STALE_REGS or NEW_REGS containing 0x80.)
	 */
	do {
		if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
				(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
			return 0;
		udelay(1);
	} while (--timeout > 0);
	return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
		(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
}

/* Time read/write */
static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
{
	int ret;
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	ret = stmp3xxx_wait_time(rtc_data);
	if (ret)
		return ret;

	rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
	return 0;
}

static int stmp3xxx_rtc_set_mmss(struct device *dev, unsigned long t)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS);
	return stmp3xxx_wait_time(rtc_data);
}

/* interrupt(s) handler */
static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
	u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);

	if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
			rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
		rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	if (enabled) {
		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
			rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
				STMP_OFFSET_REG_SET);
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
			rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
	} else {
		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
			rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
				STMP_OFFSET_REG_CLR);
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
			rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
	}
	return 0;
}

static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
	return 0;
}

static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	unsigned long t;
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	rtc_tm_to_time(&alm->time, &t);
	writel(t, rtc_data->io + STMP3XXX_RTC_ALARM);

	stmp3xxx_alarm_irq_enable(dev, alm->enabled);

	return 0;
}

static struct rtc_class_ops stmp3xxx_rtc_ops = {
	.alarm_irq_enable =
			  stmp3xxx_alarm_irq_enable,
	.read_time	= stmp3xxx_rtc_gettime,
	.set_mmss	= stmp3xxx_rtc_set_mmss,
	.read_alarm	= stmp3xxx_rtc_read_alarm,
	.set_alarm	= stmp3xxx_rtc_set_alarm,
};

static int stmp3xxx_rtc_remove(struct platform_device *pdev)
{
	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);

	if (!rtc_data)
		return 0;

	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
		rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);

	return 0;
}

static int stmp3xxx_rtc_probe(struct platform_device *pdev)
{
	struct stmp3xxx_rtc_data *rtc_data;
	struct resource *r;
	u32 rtc_stat;
	u32 pers0_set, pers0_clr;
	u32 crystalfreq = 0;
	int err;

	rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
	if (!rtc_data)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(&pdev->dev, "failed to get resource\n");
		return -ENXIO;
	}

	rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
	if (!rtc_data->io) {
		dev_err(&pdev->dev, "ioremap failed\n");
		return -EIO;
	}

	rtc_data->irq_alarm = platform_get_irq(pdev, 0);

	rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
	if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
		dev_err(&pdev->dev, "no device onboard\n");
		return -ENODEV;
	}

	platform_set_drvdata(pdev, rtc_data);

	err = stmp_reset_block(rtc_data->io);
	if (err) {
		dev_err(&pdev->dev, "stmp_reset_block failed: %d\n", err);
		return err;
	}

	/*
	 * Obviously the rtc needs a clock input to be able to run.
	 * This clock can be provided by an external 32k crystal. If that one is
	 * missing XTAL must not be disabled in suspend which consumes a
	 * lot of power. Normally the presence and exact frequency (supported
	 * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
	 * proves these fuses are not blown correctly on all machines, so the
	 * frequency can be overridden in the device tree.
	 */
	if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
		crystalfreq = 32000;
	else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
		crystalfreq = 32768;

	of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
			     &crystalfreq);

	switch (crystalfreq) {
	case 32000:
		/* keep 32kHz crystal running in low-power mode */
		pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
			STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
		pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
		break;
	case 32768:
		/* keep 32.768kHz crystal running in low-power mode */
		pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
		pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
		break;
	default:
		dev_warn(&pdev->dev,
			 "invalid crystal-freq specified in device-tree. Assuming no crystal\n");
		/* fall-through */
	case 0:
		/* keep XTAL on in low-power mode */
		pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
		pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	}

	writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
			STMP_OFFSET_REG_SET);

	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
		rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);

	writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
			STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
		rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);

	rtc_data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
				&stmp3xxx_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc_data->rtc))
		return PTR_ERR(rtc_data->rtc);

	err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
			stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
	if (err) {
		dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
			rtc_data->irq_alarm);
		return err;
	}

	stmp3xxx_wdt_register(pdev);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int stmp3xxx_rtc_suspend(struct device *dev)
{
	return 0;
}

static int stmp3xxx_rtc_resume(struct device *dev)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	stmp_reset_block(rtc_data->io);
	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
		rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
			stmp3xxx_rtc_resume);

static const struct of_device_id rtc_dt_ids[] = {
	{ .compatible = "fsl,stmp3xxx-rtc", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rtc_dt_ids);

static struct platform_driver stmp3xxx_rtcdrv = {
	.probe		= stmp3xxx_rtc_probe,
	.remove		= stmp3xxx_rtc_remove,
	.driver		= {
		.name	= "stmp3xxx-rtc",
		.pm	= &stmp3xxx_rtc_pm_ops,
		.of_match_table = rtc_dt_ids,
	},
};

module_platform_driver(stmp3xxx_rtcdrv);

MODULE_DESCRIPTION("STMP3xxx RTC Driver");
MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
		"Wolfram Sang <w.sang@pengutronix.de>");
MODULE_LICENSE("GPL");
Commit	Line	Data
df17f631	1	/*
	2	* Freescale STMP37XX/STMP378X Real Time Clock driver
	3	*
	4	* Copyright (c) 2007 Sigmatel, Inc.
	5	* Peter Hartley, <peter.hartley@sigmatel.com>
	6	*
	7	* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
	8	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
7e794cb7	9	* Copyright 2011 Wolfram Sang, Pengutronix e.K.
df17f631	10	*/
	11
	12	/*
	13	* The code contained herein is licensed under the GNU General Public
	14	* License. You may obtain a copy of the GNU General Public License
	15	* Version 2 or later at the following locations:
	16	*
	17	* http://www.opensource.org/licenses/gpl-license.html
	18	* http://www.gnu.org/copyleft/gpl.html
	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
b5167159	22	#include <linux/io.h>
df17f631	23	#include <linux/init.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/interrupt.h>
28a0c883	26	#include <linux/delay.h>
df17f631	27	#include <linux/rtc.h>
5a0e3ad6	28	#include <linux/slab.h>
dd8d20a3	29	#include <linux/of_device.h>
c8a6046e	30	#include <linux/of.h>
1a71fb84 WS	31	#include <linux/stmp_device.h>
1a71fb84 WS	32	#include <linux/stmp3xxx_rtc_wdt.h>
df17f631	33
47eac337 WS	34	#define STMP3XXX_RTC_CTRL 0x0
	35	#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
	36	#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
	37	#define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
1a71fb84	38	#define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
47eac337 WS	39
	40	#define STMP3XXX_RTC_STAT 0x10
	41	#define STMP3XXX_RTC_STAT_STALE_SHIFT 16
	42	#define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
7f48b21b UKK	43	#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
7f48b21b UKK	44	#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
47eac337 WS	45
	46	#define STMP3XXX_RTC_SECONDS 0x30
	47
	48	#define STMP3XXX_RTC_ALARM 0x40
	49
1a71fb84 WS	50	#define STMP3XXX_RTC_WATCHDOG 0x50
1a71fb84 WS	51
47eac337	52	#define STMP3XXX_RTC_PERSISTENT0 0x60
7f48b21b UKK	53	#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
	54	#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
	55	#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2)
	56	#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
	57	#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
	58	#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
	59	#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
df17f631	60
1a71fb84 WS	61	#define STMP3XXX_RTC_PERSISTENT1 0x70
	62	/* missing bitmask in headers */
	63	#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
	64
df17f631	65	struct stmp3xxx_rtc_data {
df17f631	66	struct rtc_device *rtc;
df17f631	67	void __iomem *io;
7e794cb7	68	int irq_alarm;
df17f631	69	};
df17f631	70
1a71fb84 WS	71	#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
	72	/**
	73	* stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
	74	* @dev: the parent device of the watchdog (= the RTC)
	75	* @timeout: the desired value for the timeout register of the watchdog.
	76	* 0 disables the watchdog
	77	*
	78	* The watchdog needs one register and two bits which are in the RTC domain.
	79	* To handle the resource conflict, the RTC driver will create another
	80	* platform_device for the watchdog driver as a child of the RTC device.
	81	* The watchdog driver is passed the below accessor function via platform_data
	82	* to configure the watchdog. Locking is not needed because accessing SET/CLR
	83	* registers is atomic.
	84	*/
	85
	86	static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
	87	{
	88	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	89
	90	if (timeout) {
	91	writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
	92	writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
	93	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
	94	writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
	95	rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
	96	} else {
	97	writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
	98	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
	99	writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
	100	rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
	101	}
	102	}
	103
	104	static struct stmp3xxx_wdt_pdata wdt_pdata = {
	105	.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
	106	};
	107
	108	static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
	109	{
3497610a	110	int rc = -1;
1a71fb84 WS	111	struct platform_device *wdt_pdev =
	112	platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
	113
	114	if (wdt_pdev) {
	115	wdt_pdev->dev.parent = &rtc_pdev->dev;
	116	wdt_pdev->dev.platform_data = &wdt_pdata;
3497610a	117	rc = platform_device_add(wdt_pdev);
1a71fb84	118	}
3497610a SM	119
	120	if (rc)
	121	dev_err(&rtc_pdev->dev,
	122	"failed to register stmp3xxx_rtc_wdt\n");
1a71fb84 WS	123	}
	124	#else
	125	static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
	126	{
	127	}
	128	#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
	129
28a0c883	130	static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
df17f631	131	{
28a0c883	132	int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
df17f631	133	/*
28a0c883 LW	134	* The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
	135	* states:
	136	* \| The order in which registers are updated is
	137	* \| Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
	138	* \| (This list is in bitfield order, from LSB to MSB, as they would
	139	* \| appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
	140	* \| register. For example, the Seconds register corresponds to
	141	* \| STALE_REGS or NEW_REGS containing 0x80.)
df17f631	142	*/
28a0c883 LW	143	do {
	144	if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
	145	(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
	146	return 0;
	147	udelay(1);
	148	} while (--timeout > 0);
	149	return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
	150	(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
df17f631	151	}
	152
	153	/* Time read/write */
	154	static int stmp3xxx_rtc_gettime(struct device dev, struct rtc_time rtc_tm)
	155	{
28a0c883	156	int ret;
df17f631	157	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	158
28a0c883 LW	159	ret = stmp3xxx_wait_time(rtc_data);
	160	if (ret)
	161	return ret;
	162
b5167159	163	rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
df17f631	164	return 0;
	165	}
	166
	167	static int stmp3xxx_rtc_set_mmss(struct device *dev, unsigned long t)
	168	{
	169	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	170
b5167159	171	writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS);
28a0c883	172	return stmp3xxx_wait_time(rtc_data);
df17f631	173	}
	174
	175	/* interrupt(s) handler */
	176	static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
	177	{
	178	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
7e794cb7	179	u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
df17f631	180
47eac337	181	if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
b5167159	182	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
24417829	183	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
7e794cb7 WS	184	rtc_update_irq(rtc_data->rtc, 1, RTC_AF \| RTC_IRQF);
7e794cb7 WS	185	return IRQ_HANDLED;
df17f631	186	}
df17f631	187
7e794cb7	188	return IRQ_NONE;
df17f631	189	}
	190
	191	static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
	192	{
	193	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	194
df17f631	195	if (enabled) {
b5167159 WS	196	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
b5167159 WS	197	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
24417829 HG	198	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
24417829 HG	199	STMP_OFFSET_REG_SET);
b5167159	200	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	201	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
df17f631	202	} else {
b5167159 WS	203	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
b5167159 WS	204	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
24417829 HG	205	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
24417829 HG	206	STMP_OFFSET_REG_CLR);
b5167159	207	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	208	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
df17f631	209	}
	210	return 0;
	211	}
	212
df17f631	213	static int stmp3xxx_rtc_read_alarm(struct device dev, struct rtc_wkalrm alm)
	214	{
	215	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	216
b5167159	217	rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
df17f631	218	return 0;
	219	}
	220
	221	static int stmp3xxx_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm)
	222	{
	223	unsigned long t;
	224	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	225
	226	rtc_tm_to_time(&alm->time, &t);
b5167159	227	writel(t, rtc_data->io + STMP3XXX_RTC_ALARM);
7e794cb7 WS	228
	229	stmp3xxx_alarm_irq_enable(dev, alm->enabled);
	230
df17f631	231	return 0;
	232	}
	233
	234	static struct rtc_class_ops stmp3xxx_rtc_ops = {
	235	.alarm_irq_enable =
	236	stmp3xxx_alarm_irq_enable,
df17f631	237	.read_time = stmp3xxx_rtc_gettime,
	238	.set_mmss = stmp3xxx_rtc_set_mmss,
	239	.read_alarm = stmp3xxx_rtc_read_alarm,
	240	.set_alarm = stmp3xxx_rtc_set_alarm,
	241	};
	242
	243	static int stmp3xxx_rtc_remove(struct platform_device *pdev)
	244	{
	245	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
	246
	247	if (!rtc_data)
	248	return 0;
	249
7e794cb7	250	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	251	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
df17f631	252
	253	return 0;
	254	}
	255
	256	static int stmp3xxx_rtc_probe(struct platform_device *pdev)
	257	{
	258	struct stmp3xxx_rtc_data *rtc_data;
	259	struct resource *r;
7f48b21b UKK	260	u32 rtc_stat;
	261	u32 pers0_set, pers0_clr;
	262	u32 crystalfreq = 0;
df17f631	263	int err;
df17f631	264
87a81420	265	rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
df17f631	266	if (!rtc_data)
	267	return -ENOMEM;
	268
	269	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	270	if (!r) {
	271	dev_err(&pdev->dev, "failed to get resource\n");
87a81420	272	return -ENXIO;
df17f631	273	}
df17f631	274
87a81420	275	rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
df17f631	276	if (!rtc_data->io) {
df17f631	277	dev_err(&pdev->dev, "ioremap failed\n");
87a81420	278	return -EIO;
df17f631	279	}
	280
	281	rtc_data->irq_alarm = platform_get_irq(pdev, 0);
df17f631	282
7f48b21b UKK	283	rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
7f48b21b UKK	284	if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
df17f631	285	dev_err(&pdev->dev, "no device onboard\n");
87a81420	286	return -ENODEV;
df17f631	287	}
df17f631	288
a91d2bab WS	289	platform_set_drvdata(pdev, rtc_data);
a91d2bab WS	290
4e80b188 FE	291	err = stmp_reset_block(rtc_data->io);
	292	if (err) {
	293	dev_err(&pdev->dev, "stmp_reset_block failed: %d\n", err);
	294	return err;
	295	}
	296
7f48b21b UKK	297	/*
	298	* Obviously the rtc needs a clock input to be able to run.
	299	* This clock can be provided by an external 32k crystal. If that one is
	300	* missing XTAL must not be disabled in suspend which consumes a
	301	* lot of power. Normally the presence and exact frequency (supported
	302	* are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
	303	* proves these fuses are not blown correctly on all machines, so the
	304	* frequency can be overridden in the device tree.
	305	*/
	306	if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
	307	crystalfreq = 32000;
	308	else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
	309	crystalfreq = 32768;
	310
	311	of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
	312	&crystalfreq);
	313
	314	switch (crystalfreq) {
	315	case 32000:
	316	/* keep 32kHz crystal running in low-power mode */
	317	pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ \|
	318	STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP \|
	319	STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	320	pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
	321	break;
	322	case 32768:
	323	/* keep 32.768kHz crystal running in low-power mode */
	324	pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP \|
	325	STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	326	pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP \|
	327	STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
	328	break;
	329	default:
	330	dev_warn(&pdev->dev,
	331	"invalid crystal-freq specified in device-tree. Assuming no crystal\n");
	332	/* fall-through */
	333	case 0:
	334	/* keep XTAL on in low-power mode */
	335	pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
	336	pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP \|
	337	STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	338	}
	339
24417829 HG	340	writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
24417829 HG	341	STMP_OFFSET_REG_SET);
7f48b21b	342
b5167159	343	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
47eac337	344	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN \|
7f48b21b	345	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE \| pers0_clr,
24417829	346	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
a91d2bab	347
7e794cb7 WS	348	writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN \|
7e794cb7 WS	349	STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	350	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
7e794cb7	351
87a81420	352	rtc_data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
df17f631	353	&stmp3xxx_rtc_ops, THIS_MODULE);
dfd2a178 JH	354	if (IS_ERR(rtc_data->rtc))
dfd2a178 JH	355	return PTR_ERR(rtc_data->rtc);
df17f631	356
87a81420 JH	357	err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
87a81420 JH	358	stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
df17f631	359	if (err) {
	360	dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
	361	rtc_data->irq_alarm);
dfd2a178	362	return err;
df17f631	363	}
df17f631	364
1a71fb84	365	stmp3xxx_wdt_register(pdev);
df17f631	366	return 0;
df17f631	367	}
df17f631	368
ef69a7f0 JH	369	#ifdef CONFIG_PM_SLEEP
ef69a7f0 JH	370	static int stmp3xxx_rtc_suspend(struct device *dev)
df17f631	371	{
	372	return 0;
	373	}
	374
ef69a7f0	375	static int stmp3xxx_rtc_resume(struct device *dev)
df17f631	376	{
ef69a7f0	377	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	378
36d1da1d	379	stmp_reset_block(rtc_data->io);
b5167159	380	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
47eac337 WS	381	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN \|
47eac337 WS	382	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
24417829	383	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
df17f631	384	return 0;
df17f631	385	}
df17f631	386	#endif
df17f631	387
ef69a7f0 JH	388	static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
	389	stmp3xxx_rtc_resume);
	390
dd8d20a3 MV	391	static const struct of_device_id rtc_dt_ids[] = {
	392	{ .compatible = "fsl,stmp3xxx-rtc", },
	393	{ /* sentinel */ }
	394	};
	395	MODULE_DEVICE_TABLE(of, rtc_dt_ids);
	396
df17f631	397	static struct platform_driver stmp3xxx_rtcdrv = {
	398	.probe = stmp3xxx_rtc_probe,
	399	.remove = stmp3xxx_rtc_remove,
df17f631	400	.driver = {
df17f631	401	.name = "stmp3xxx-rtc",
ef69a7f0	402	.pm = &stmp3xxx_rtc_pm_ops,
462a465b	403	.of_match_table = rtc_dt_ids,
df17f631	404	},
	405	};
	406
0c4eae66	407	module_platform_driver(stmp3xxx_rtcdrv);
df17f631	408
df17f631	409	MODULE_DESCRIPTION("STMP3xxx RTC Driver");
7e794cb7 WS	410	MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
7e794cb7 WS	411	"Wolfram Sang <w.sang@pengutronix.de>");
df17f631	412	MODULE_LICENSE("GPL");