[linux-2.6-block.git] / drivers / rtc / rtc-mxc.c

/*
 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/io.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>

#define RTC_INPUT_CLK_32768HZ	(0x00 << 5)
#define RTC_INPUT_CLK_32000HZ	(0x01 << 5)
#define RTC_INPUT_CLK_38400HZ	(0x02 << 5)

#define RTC_SW_BIT      (1 << 0)
#define RTC_ALM_BIT     (1 << 2)
#define RTC_1HZ_BIT     (1 << 4)
#define RTC_2HZ_BIT     (1 << 7)
#define RTC_SAM0_BIT    (1 << 8)
#define RTC_SAM1_BIT    (1 << 9)
#define RTC_SAM2_BIT    (1 << 10)
#define RTC_SAM3_BIT    (1 << 11)
#define RTC_SAM4_BIT    (1 << 12)
#define RTC_SAM5_BIT    (1 << 13)
#define RTC_SAM6_BIT    (1 << 14)
#define RTC_SAM7_BIT    (1 << 15)
#define PIT_ALL_ON      (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
			 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
			 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)

#define RTC_ENABLE_BIT  (1 << 7)

#define MAX_PIE_NUM     9
#define MAX_PIE_FREQ    512
static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
	{ 2,		RTC_2HZ_BIT },
	{ 4,		RTC_SAM0_BIT },
	{ 8,		RTC_SAM1_BIT },
	{ 16,		RTC_SAM2_BIT },
	{ 32,		RTC_SAM3_BIT },
	{ 64,		RTC_SAM4_BIT },
	{ 128,		RTC_SAM5_BIT },
	{ 256,		RTC_SAM6_BIT },
	{ MAX_PIE_FREQ,	RTC_SAM7_BIT },
};

#define MXC_RTC_TIME	0
#define MXC_RTC_ALARM	1

#define RTC_HOURMIN	0x00	/*  32bit rtc hour/min counter reg */
#define RTC_SECOND	0x04	/*  32bit rtc seconds counter reg */
#define RTC_ALRM_HM	0x08	/*  32bit rtc alarm hour/min reg */
#define RTC_ALRM_SEC	0x0C	/*  32bit rtc alarm seconds reg */
#define RTC_RTCCTL	0x10	/*  32bit rtc control reg */
#define RTC_RTCISR	0x14	/*  32bit rtc interrupt status reg */
#define RTC_RTCIENR	0x18	/*  32bit rtc interrupt enable reg */
#define RTC_STPWCH	0x1C	/*  32bit rtc stopwatch min reg */
#define RTC_DAYR	0x20	/*  32bit rtc days counter reg */
#define RTC_DAYALARM	0x24	/*  32bit rtc day alarm reg */
#define RTC_TEST1	0x28	/*  32bit rtc test reg 1 */
#define RTC_TEST2	0x2C	/*  32bit rtc test reg 2 */
#define RTC_TEST3	0x30	/*  32bit rtc test reg 3 */

enum imx_rtc_type {
	IMX1_RTC,
	IMX21_RTC,
};

struct rtc_plat_data {
	struct rtc_device *rtc;
	void __iomem *ioaddr;
	int irq;
	struct clk *clk;
	struct rtc_time g_rtc_alarm;
	enum imx_rtc_type devtype;
};

static const struct platform_device_id imx_rtc_devtype[] = {
	{
		.name = "imx1-rtc",
		.driver_data = IMX1_RTC,
	}, {
		.name = "imx21-rtc",
		.driver_data = IMX21_RTC,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);

static inline int is_imx1_rtc(struct rtc_plat_data *data)
{
	return data->devtype == IMX1_RTC;
}

/*
 * This function is used to obtain the RTC time or the alarm value in
 * second.
 */
static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		day = readw(ioaddr + RTC_DAYR);
		hr_min = readw(ioaddr + RTC_HOURMIN);
		sec = readw(ioaddr + RTC_SECOND);
		break;
	case MXC_RTC_ALARM:
		day = readw(ioaddr + RTC_DAYALARM);
		hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
		sec = readw(ioaddr + RTC_ALRM_SEC);
		break;
	}

	hr = hr_min >> 8;
	min = hr_min & 0xff;

	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
}

/*
 * This function sets the RTC alarm value or the time value.
 */
static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
{
	u32 tod, day, hr, min, sec, temp;
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	day = div_s64_rem(time, 86400, &tod);

	/* time is within a day now */
	hr = tod / 3600;
	tod -= hr * 3600;

	/* time is within an hour now */
	min = tod / 60;
	sec = tod - min * 60;

	temp = (hr << 8) + min;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		writew(day, ioaddr + RTC_DAYR);
		writew(sec, ioaddr + RTC_SECOND);
		writew(temp, ioaddr + RTC_HOURMIN);
		break;
	case MXC_RTC_ALARM:
		writew(day, ioaddr + RTC_DAYALARM);
		writew(sec, ioaddr + RTC_ALRM_SEC);
		writew(temp, ioaddr + RTC_ALRM_HM);
		break;
	}
}

/*
 * This function updates the RTC alarm registers and then clears all the
 * interrupt status bits.
 */
static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
{
	time64_t time;
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	time = rtc_tm_to_time64(alrm);

	/* clear all the interrupt status bits */
	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
}

static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
				unsigned int enabled)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 reg;

	spin_lock_irq(&pdata->rtc->irq_lock);
	reg = readw(ioaddr + RTC_RTCIENR);

	if (enabled)
		reg |= bit;
	else
		reg &= ~bit;

	writew(reg, ioaddr + RTC_RTCIENR);
	spin_unlock_irq(&pdata->rtc->irq_lock);
}

/* This function is the RTC interrupt service routine. */
static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = dev_id;
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	unsigned long flags;
	u32 status;
	u32 events = 0;

	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	/* clear interrupt sources */
	writew(status, ioaddr + RTC_RTCISR);

	/* update irq data & counter */
	if (status & RTC_ALM_BIT) {
		events |= (RTC_AF | RTC_IRQF);
		/* RTC alarm should be one-shot */
		mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	}

	if (status & RTC_1HZ_BIT)
		events |= (RTC_UF | RTC_IRQF);

	if (status & PIT_ALL_ON)
		events |= (RTC_PF | RTC_IRQF);

	rtc_update_irq(pdata->rtc, 1, events);
	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);

	return IRQ_HANDLED;
}

/*
 * Clear all interrupts and release the IRQ
 */
static void mxc_rtc_release(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	spin_lock_irq(&pdata->rtc->irq_lock);

	/* Disable all rtc interrupts */
	writew(0, ioaddr + RTC_RTCIENR);

	/* Clear all interrupt status */
	writew(0xffffffff, ioaddr + RTC_RTCISR);

	spin_unlock_irq(&pdata->rtc->irq_lock);
}

static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	return 0;
}

/*
 * This function reads the current RTC time into tm in Gregorian date.
 */
static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	time64_t val;

	/* Avoid roll-over from reading the different registers */
	do {
		val = get_alarm_or_time(dev, MXC_RTC_TIME);
	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));

	rtc_time64_to_tm(val, tm);

	return 0;
}

/*
 * This function sets the internal RTC time based on tm in Gregorian date.
 */
static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	/*
	 * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	 */
	if (is_imx1_rtc(pdata)) {
		struct rtc_time tm;

		rtc_time64_to_tm(time, &tm);
		tm.tm_year = 70;
		time = rtc_tm_to_time64(&tm);
	}

	/* Avoid roll-over from reading the different registers */
	do {
		set_alarm_or_time(dev, MXC_RTC_TIME, time);
	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));

	return 0;
}

/*
 * This function reads the current alarm value into the passed in 'alrm'
 * argument. It updates the alrm's pending field value based on the whether
 * an alarm interrupt occurs or not.
 */
static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;

	return 0;
}

/*
 * This function sets the RTC alarm based on passed in alrm.
 */
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	rtc_update_alarm(dev, &alrm->time);

	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);

	return 0;
}

/* RTC layer */
static struct rtc_class_ops mxc_rtc_ops = {
	.release		= mxc_rtc_release,
	.read_time		= mxc_rtc_read_time,
	.set_mmss64		= mxc_rtc_set_mmss,
	.read_alarm		= mxc_rtc_read_alarm,
	.set_alarm		= mxc_rtc_set_alarm,
	.alarm_irq_enable	= mxc_rtc_alarm_irq_enable,
};

static int mxc_rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	struct rtc_plat_data *pdata = NULL;
	u32 reg;
	unsigned long rate;
	int ret;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	pdata->devtype = pdev->id_entry->driver_data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pdata->ioaddr))
		return PTR_ERR(pdata->ioaddr);

	pdata->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pdata->clk)) {
		dev_err(&pdev->dev, "unable to get clock!\n");
		return PTR_ERR(pdata->clk);
	}

	ret = clk_prepare_enable(pdata->clk);
	if (ret)
		return ret;

	rate = clk_get_rate(pdata->clk);

	if (rate == 32768)
		reg = RTC_INPUT_CLK_32768HZ;
	else if (rate == 32000)
		reg = RTC_INPUT_CLK_32000HZ;
	else if (rate == 38400)
		reg = RTC_INPUT_CLK_38400HZ;
	else {
		dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
		ret = -EINVAL;
		goto exit_put_clk;
	}

	reg |= RTC_ENABLE_BIT;
	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
		dev_err(&pdev->dev, "hardware module can't be enabled!\n");
		ret = -EIO;
		goto exit_put_clk;
	}

	platform_set_drvdata(pdev, pdata);

	/* Configure and enable the RTC */
	pdata->irq = platform_get_irq(pdev, 0);

	if (pdata->irq >= 0 &&
	    devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
			     IRQF_SHARED, pdev->name, pdev) < 0) {
		dev_warn(&pdev->dev, "interrupt not available.\n");
		pdata->irq = -1;
	}

	if (pdata->irq >= 0)
		device_init_wakeup(&pdev->dev, 1);

	rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
				  THIS_MODULE);
	if (IS_ERR(rtc)) {
		ret = PTR_ERR(rtc);
		goto exit_put_clk;
	}

	pdata->rtc = rtc;

	return 0;

exit_put_clk:
	clk_disable_unprepare(pdata->clk);

	return ret;
}

static int mxc_rtc_remove(struct platform_device *pdev)
{
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	clk_disable_unprepare(pdata->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mxc_rtc_suspend(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(pdata->irq);

	return 0;
}

static int mxc_rtc_resume(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(pdata->irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);

static struct platform_driver mxc_rtc_driver = {
	.driver = {
		   .name	= "mxc_rtc",
		   .pm		= &mxc_rtc_pm_ops,
	},
	.id_table = imx_rtc_devtype,
	.probe = mxc_rtc_probe,
	.remove = mxc_rtc_remove,
};

module_platform_driver(mxc_rtc_driver)

MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
MODULE_DESCRIPTION("RTC driver for Freescale MXC");
MODULE_LICENSE("GPL");
Commit	Line	Data
d00ed3cf DM	1	/*
	2	* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	#include <linux/io.h>
	13	#include <linux/rtc.h>
	14	#include <linux/module.h>
5a0e3ad6	15	#include <linux/slab.h>
d00ed3cf DM	16	#include <linux/interrupt.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/clk.h>
	19
d00ed3cf DM	20	#define RTC_INPUT_CLK_32768HZ (0x00 << 5)
	21	#define RTC_INPUT_CLK_32000HZ (0x01 << 5)
	22	#define RTC_INPUT_CLK_38400HZ (0x02 << 5)
	23
	24	#define RTC_SW_BIT (1 << 0)
	25	#define RTC_ALM_BIT (1 << 2)
	26	#define RTC_1HZ_BIT (1 << 4)
	27	#define RTC_2HZ_BIT (1 << 7)
	28	#define RTC_SAM0_BIT (1 << 8)
	29	#define RTC_SAM1_BIT (1 << 9)
	30	#define RTC_SAM2_BIT (1 << 10)
	31	#define RTC_SAM3_BIT (1 << 11)
	32	#define RTC_SAM4_BIT (1 << 12)
	33	#define RTC_SAM5_BIT (1 << 13)
	34	#define RTC_SAM6_BIT (1 << 14)
	35	#define RTC_SAM7_BIT (1 << 15)
	36	#define PIT_ALL_ON (RTC_2HZ_BIT \| RTC_SAM0_BIT \| RTC_SAM1_BIT \| \
	37	RTC_SAM2_BIT \| RTC_SAM3_BIT \| RTC_SAM4_BIT \| \
	38	RTC_SAM5_BIT \| RTC_SAM6_BIT \| RTC_SAM7_BIT)
	39
	40	#define RTC_ENABLE_BIT (1 << 7)
	41
	42	#define MAX_PIE_NUM 9
	43	#define MAX_PIE_FREQ 512
	44	static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = {
	45	{ 2, RTC_2HZ_BIT },
	46	{ 4, RTC_SAM0_BIT },
	47	{ 8, RTC_SAM1_BIT },
	48	{ 16, RTC_SAM2_BIT },
	49	{ 32, RTC_SAM3_BIT },
	50	{ 64, RTC_SAM4_BIT },
	51	{ 128, RTC_SAM5_BIT },
	52	{ 256, RTC_SAM6_BIT },
	53	{ MAX_PIE_FREQ, RTC_SAM7_BIT },
	54	};
	55
d00ed3cf DM	56	#define MXC_RTC_TIME 0
	57	#define MXC_RTC_ALARM 1
	58
	59	#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
	60	#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
	61	#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
	62	#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
	63	#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
	64	#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
	65	#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
	66	#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
	67	#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
	68	#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
	69	#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
	70	#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
	71	#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
	72
bb1d34a2 SG	73	enum imx_rtc_type {
	74	IMX1_RTC,
	75	IMX21_RTC,
	76	};
	77
d00ed3cf DM	78	struct rtc_plat_data {
	79	struct rtc_device *rtc;
	80	void __iomem *ioaddr;
	81	int irq;
	82	struct clk *clk;
d00ed3cf	83	struct rtc_time g_rtc_alarm;
bb1d34a2	84	enum imx_rtc_type devtype;
d00ed3cf DM	85	};
d00ed3cf DM	86
cd6ba00a	87	static const struct platform_device_id imx_rtc_devtype[] = {
bb1d34a2 SG	88	{
	89	.name = "imx1-rtc",
	90	.driver_data = IMX1_RTC,
	91	}, {
	92	.name = "imx21-rtc",
	93	.driver_data = IMX21_RTC,
	94	}, {
	95	/* sentinel */
	96	}
	97	};
	98	MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
	99
	100	static inline int is_imx1_rtc(struct rtc_plat_data *data)
	101	{
	102	return data->devtype == IMX1_RTC;
	103	}
	104
d00ed3cf DM	105	/*
	106	* This function is used to obtain the RTC time or the alarm value in
	107	* second.
	108	*/
a015b8aa	109	static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
d00ed3cf DM	110	{
	111	struct platform_device *pdev = to_platform_device(dev);
	112	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	113	void __iomem *ioaddr = pdata->ioaddr;
	114	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
	115
	116	switch (time_alarm) {
	117	case MXC_RTC_TIME:
	118	day = readw(ioaddr + RTC_DAYR);
	119	hr_min = readw(ioaddr + RTC_HOURMIN);
	120	sec = readw(ioaddr + RTC_SECOND);
	121	break;
	122	case MXC_RTC_ALARM:
	123	day = readw(ioaddr + RTC_DAYALARM);
	124	hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
	125	sec = readw(ioaddr + RTC_ALRM_SEC);
	126	break;
	127	}
	128
	129	hr = hr_min >> 8;
	130	min = hr_min & 0xff;
	131
a015b8aa	132	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
d00ed3cf DM	133	}
	134
	135	/*
	136	* This function sets the RTC alarm value or the time value.
	137	*/
a015b8aa	138	static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
d00ed3cf	139	{
a015b8aa	140	u32 tod, day, hr, min, sec, temp;
d00ed3cf DM	141	struct platform_device *pdev = to_platform_device(dev);
	142	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	143	void __iomem *ioaddr = pdata->ioaddr;
	144
a015b8aa	145	day = div_s64_rem(time, 86400, &tod);
d00ed3cf DM	146
d00ed3cf DM	147	/* time is within a day now */
a015b8aa XP	148	hr = tod / 3600;
a015b8aa XP	149	tod -= hr * 3600;
d00ed3cf DM	150
d00ed3cf DM	151	/* time is within an hour now */
a015b8aa XP	152	min = tod / 60;
a015b8aa XP	153	sec = tod - min * 60;
d00ed3cf DM	154
	155	temp = (hr << 8) + min;
	156
	157	switch (time_alarm) {
	158	case MXC_RTC_TIME:
	159	writew(day, ioaddr + RTC_DAYR);
	160	writew(sec, ioaddr + RTC_SECOND);
	161	writew(temp, ioaddr + RTC_HOURMIN);
	162	break;
	163	case MXC_RTC_ALARM:
	164	writew(day, ioaddr + RTC_DAYALARM);
	165	writew(sec, ioaddr + RTC_ALRM_SEC);
	166	writew(temp, ioaddr + RTC_ALRM_HM);
	167	break;
	168	}
	169	}
	170
	171	/*
	172	* This function updates the RTC alarm registers and then clears all the
	173	* interrupt status bits.
	174	*/
482494a8	175	static void rtc_update_alarm(struct device dev, struct rtc_time alrm)
d00ed3cf	176	{
a015b8aa	177	time64_t time;
d00ed3cf DM	178	struct platform_device *pdev = to_platform_device(dev);
	179	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	180	void __iomem *ioaddr = pdata->ioaddr;
	181
a015b8aa	182	time = rtc_tm_to_time64(alrm);
d00ed3cf	183
d00ed3cf DM	184	/* clear all the interrupt status bits */
	185	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	186	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
c92182ee YK	187	}
	188
	189	static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
	190	unsigned int enabled)
	191	{
	192	struct platform_device *pdev = to_platform_device(dev);
	193	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	194	void __iomem *ioaddr = pdata->ioaddr;
	195	u32 reg;
	196
	197	spin_lock_irq(&pdata->rtc->irq_lock);
	198	reg = readw(ioaddr + RTC_RTCIENR);
	199
	200	if (enabled)
	201	reg \|= bit;
	202	else
	203	reg &= ~bit;
	204
	205	writew(reg, ioaddr + RTC_RTCIENR);
	206	spin_unlock_irq(&pdata->rtc->irq_lock);
d00ed3cf DM	207	}
	208
	209	/* This function is the RTC interrupt service routine. */
	210	static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
	211	{
	212	struct platform_device *pdev = dev_id;
	213	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	214	void __iomem *ioaddr = pdata->ioaddr;
b59f6d1f	215	unsigned long flags;
d00ed3cf DM	216	u32 status;
	217	u32 events = 0;
	218
b59f6d1f	219	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	220	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	221	/* clear interrupt sources */
	222	writew(status, ioaddr + RTC_RTCISR);
	223
d00ed3cf	224	/* update irq data & counter */
c92182ee	225	if (status & RTC_ALM_BIT) {
d00ed3cf	226	events \|= (RTC_AF \| RTC_IRQF);
c92182ee YK	227	/* RTC alarm should be one-shot */
	228	mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	229	}
d00ed3cf DM	230
	231	if (status & RTC_1HZ_BIT)
	232	events \|= (RTC_UF \| RTC_IRQF);
	233
	234	if (status & PIT_ALL_ON)
	235	events \|= (RTC_PF \| RTC_IRQF);
	236
d00ed3cf	237	rtc_update_irq(pdata->rtc, 1, events);
b59f6d1f	238	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	239
	240	return IRQ_HANDLED;
	241	}
	242
	243	/*
	244	* Clear all interrupts and release the IRQ
	245	*/
	246	static void mxc_rtc_release(struct device *dev)
	247	{
	248	struct platform_device *pdev = to_platform_device(dev);
	249	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	250	void __iomem *ioaddr = pdata->ioaddr;
	251
	252	spin_lock_irq(&pdata->rtc->irq_lock);
	253
	254	/* Disable all rtc interrupts */
	255	writew(0, ioaddr + RTC_RTCIENR);
	256
	257	/* Clear all interrupt status */
	258	writew(0xffffffff, ioaddr + RTC_RTCISR);
	259
	260	spin_unlock_irq(&pdata->rtc->irq_lock);
	261	}
	262
d00ed3cf DM	263	static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	264	{
	265	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	266	return 0;
	267	}
	268
d00ed3cf DM	269	/*
	270	* This function reads the current RTC time into tm in Gregorian date.
	271	*/
	272	static int mxc_rtc_read_time(struct device dev, struct rtc_time tm)
	273	{
a015b8aa	274	time64_t val;
d00ed3cf DM	275
	276	/* Avoid roll-over from reading the different registers */
	277	do {
	278	val = get_alarm_or_time(dev, MXC_RTC_TIME);
	279	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
	280
a015b8aa	281	rtc_time64_to_tm(val, tm);
d00ed3cf DM	282
	283	return 0;
	284	}
	285
	286	/*
	287	* This function sets the internal RTC time based on tm in Gregorian date.
	288	*/
933623c3	289	static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
d00ed3cf	290	{
bb1d34a2 SG	291	struct platform_device *pdev = to_platform_device(dev);
	292	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	293
7287be1d YK	294	/*
	295	* TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	296	*/
bb1d34a2	297	if (is_imx1_rtc(pdata)) {
7287be1d YK	298	struct rtc_time tm;
7287be1d YK	299
933623c3	300	rtc_time64_to_tm(time, &tm);
7287be1d	301	tm.tm_year = 70;
933623c3	302	time = rtc_tm_to_time64(&tm);
7287be1d YK	303	}
7287be1d YK	304
d00ed3cf DM	305	/* Avoid roll-over from reading the different registers */
	306	do {
	307	set_alarm_or_time(dev, MXC_RTC_TIME, time);
	308	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
	309
	310	return 0;
	311	}
	312
	313	/*
	314	* This function reads the current alarm value into the passed in 'alrm'
	315	* argument. It updates the alrm's pending field value based on the whether
	316	* an alarm interrupt occurs or not.
	317	*/
	318	static int mxc_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	319	{
	320	struct platform_device *pdev = to_platform_device(dev);
	321	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	322	void __iomem *ioaddr = pdata->ioaddr;
	323
a015b8aa	324	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
d00ed3cf DM	325	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
	326
	327	return 0;
	328	}
	329
	330	/*
	331	* This function sets the RTC alarm based on passed in alrm.
	332	*/
	333	static int mxc_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	334	{
	335	struct platform_device *pdev = to_platform_device(dev);
	336	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
d00ed3cf	337
482494a8	338	rtc_update_alarm(dev, &alrm->time);
d00ed3cf DM	339
	340	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	341	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
	342
	343	return 0;
	344	}
	345
	346	/* RTC layer */
	347	static struct rtc_class_ops mxc_rtc_ops = {
	348	.release = mxc_rtc_release,
	349	.read_time = mxc_rtc_read_time,
933623c3	350	.set_mmss64 = mxc_rtc_set_mmss,
d00ed3cf DM	351	.read_alarm = mxc_rtc_read_alarm,
	352	.set_alarm = mxc_rtc_set_alarm,
	353	.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
d00ed3cf DM	354	};
d00ed3cf DM	355
5a167f45	356	static int mxc_rtc_probe(struct platform_device *pdev)
d00ed3cf	357	{
d00ed3cf DM	358	struct resource *res;
	359	struct rtc_device *rtc;
	360	struct rtc_plat_data *pdata = NULL;
	361	u32 reg;
c783a29e VZ	362	unsigned long rate;
c783a29e VZ	363	int ret;
d00ed3cf	364
c783a29e	365	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
d00ed3cf DM	366	if (!pdata)
	367	return -ENOMEM;
	368
bb1d34a2 SG	369	pdata->devtype = pdev->id_entry->driver_data;
bb1d34a2 SG	370
7c1d69ee JL	371	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	372	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	373	if (IS_ERR(pdata->ioaddr))
	374	return PTR_ERR(pdata->ioaddr);
d00ed3cf	375
0f3cde53	376	pdata->clk = devm_clk_get(&pdev->dev, NULL);
5cf8f57d VZ	377	if (IS_ERR(pdata->clk)) {
5cf8f57d VZ	378	dev_err(&pdev->dev, "unable to get clock!\n");
fbd5e754	379	return PTR_ERR(pdata->clk);
49908e73	380	}
d00ed3cf	381
1b3d2243 FE	382	ret = clk_prepare_enable(pdata->clk);
	383	if (ret)
	384	return ret;
	385
5cf8f57d	386	rate = clk_get_rate(pdata->clk);
d00ed3cf DM	387
	388	if (rate == 32768)
	389	reg = RTC_INPUT_CLK_32768HZ;
	390	else if (rate == 32000)
	391	reg = RTC_INPUT_CLK_32000HZ;
	392	else if (rate == 38400)
	393	reg = RTC_INPUT_CLK_38400HZ;
	394	else {
c783a29e	395	dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
d00ed3cf	396	ret = -EINVAL;
5cf8f57d	397	goto exit_put_clk;
d00ed3cf DM	398	}
	399
	400	reg \|= RTC_ENABLE_BIT;
	401	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	402	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
	403	dev_err(&pdev->dev, "hardware module can't be enabled!\n");
	404	ret = -EIO;
5cf8f57d	405	goto exit_put_clk;
d00ed3cf DM	406	}
d00ed3cf DM	407
d00ed3cf DM	408	platform_set_drvdata(pdev, pdata);
	409
	410	/* Configure and enable the RTC */
	411	pdata->irq = platform_get_irq(pdev, 0);
	412
	413	if (pdata->irq >= 0 &&
c783a29e VZ	414	devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
c783a29e VZ	415	IRQF_SHARED, pdev->name, pdev) < 0) {
d00ed3cf DM	416	dev_warn(&pdev->dev, "interrupt not available.\n");
	417	pdata->irq = -1;
	418	}
	419
4a8282d0	420	if (pdata->irq >= 0)
c92182ee YK	421	device_init_wakeup(&pdev->dev, 1);
c92182ee YK	422
033ca3ad	423	rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
5f54c8a0 WS	424	THIS_MODULE);
	425	if (IS_ERR(rtc)) {
	426	ret = PTR_ERR(rtc);
d2f3a398	427	goto exit_put_clk;
5f54c8a0 WS	428	}
	429
	430	pdata->rtc = rtc;
	431
d00ed3cf DM	432	return 0;
	433
	434	exit_put_clk:
0f3cde53	435	clk_disable_unprepare(pdata->clk);
d00ed3cf	436
d00ed3cf DM	437	return ret;
	438	}
	439
5a167f45	440	static int mxc_rtc_remove(struct platform_device *pdev)
d00ed3cf DM	441	{
	442	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	443
0f3cde53	444	clk_disable_unprepare(pdata->clk);
d00ed3cf DM	445
	446	return 0;
	447	}
	448
75634cc4	449	#ifdef CONFIG_PM_SLEEP
c92182ee YK	450	static int mxc_rtc_suspend(struct device *dev)
	451	{
	452	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	453
	454	if (device_may_wakeup(dev))
	455	enable_irq_wake(pdata->irq);
	456
	457	return 0;
	458	}
	459
	460	static int mxc_rtc_resume(struct device *dev)
	461	{
	462	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	463
	464	if (device_may_wakeup(dev))
	465	disable_irq_wake(pdata->irq);
	466
	467	return 0;
	468	}
c92182ee YK	469	#endif
c92182ee YK	470
75634cc4 JH	471	static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
75634cc4 JH	472
d00ed3cf DM	473	static struct platform_driver mxc_rtc_driver = {
	474	.driver = {
	475	.name = "mxc_rtc",
c92182ee	476	.pm = &mxc_rtc_pm_ops,
d00ed3cf	477	},
bb1d34a2	478	.id_table = imx_rtc_devtype,
be8b6d51	479	.probe = mxc_rtc_probe,
5a167f45	480	.remove = mxc_rtc_remove,
d00ed3cf DM	481	};
d00ed3cf DM	482
be8b6d51	483	module_platform_driver(mxc_rtc_driver)
d00ed3cf DM	484
	485	MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
	486	MODULE_DESCRIPTION("RTC driver for Freescale MXC");
	487	MODULE_LICENSE("GPL");
	488