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ACPI / debugger: Fix regression introduced by IS_ERR_VALUE() removal
[linux-2.6-block.git] / drivers / rtc / rtc-ds1685.c
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aaaf5fbf
JK		 1/*
2 * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
3 * chips.
4 *
5 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
6 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
7 *
8 * References:
9 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
10 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
11 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
12 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
a737e835
JP		 19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
aaaf5fbf
JK		 21#include <linux/bcd.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
26#include <linux/rtc.h>
27#include <linux/workqueue.h>
28
29#include <linux/rtc/ds1685.h>
30
31#ifdef CONFIG_PROC_FS
32#include <linux/proc_fs.h>
33#endif
34
aaaf5fbf
JK		 35
36/* ----------------------------------------------------------------------- */
37/* Standard read/write functions if platform does not provide overrides */
38
39/**
40 * ds1685_read - read a value from an rtc register.
41 * @rtc: pointer to the ds1685 rtc structure.
42 * @reg: the register address to read.
43 */
44static u8
45ds1685_read(struct ds1685_priv *rtc, int reg)
46{
47 return readb((u8 __iomem *)rtc->regs +
48 (reg * rtc->regstep));
49}
50
51/**
52 * ds1685_write - write a value to an rtc register.
53 * @rtc: pointer to the ds1685 rtc structure.
54 * @reg: the register address to write.
55 * @value: value to write to the register.
56 */
57static void
58ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
59{
60 writeb(value, ((u8 __iomem *)rtc->regs +
61 (reg * rtc->regstep)));
62}
63/* ----------------------------------------------------------------------- */
64
65
66/* ----------------------------------------------------------------------- */
67/* Inlined functions */
68
69/**
70 * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
71 * @rtc: pointer to the ds1685 rtc structure.
72 * @val: u8 time value to consider converting.
73 * @bcd_mask: u8 mask value if BCD mode is used.
74 * @bin_mask: u8 mask value if BIN mode is used.
75 *
76 * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
77 */
78static inline u8
79ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
80{
81 if (rtc->bcd_mode)
82 return (bcd2bin(val) & bcd_mask);
83
84 return (val & bin_mask);
85}
86
87/**
88 * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
89 * @rtc: pointer to the ds1685 rtc structure.
90 * @val: u8 time value to consider converting.
91 * @bin_mask: u8 mask value if BIN mode is used.
92 * @bcd_mask: u8 mask value if BCD mode is used.
93 *
94 * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
95 */
96static inline u8
97ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
98{
99 if (rtc->bcd_mode)
100 return (bin2bcd(val) & bcd_mask);
101
102 return (val & bin_mask);
103}
104
105/**
106 * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
107 * @rtc: pointer to the ds1685 rtc structure.
108 */
109static inline void
110ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
111{
112 rtc->write(rtc, RTC_CTRL_A,
113 (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
114}
115
116/**
117 * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
118 * @rtc: pointer to the ds1685 rtc structure.
119 */
120static inline void
121ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
122{
123 rtc->write(rtc, RTC_CTRL_A,
124 (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
125}
126
127/**
128 * ds1685_rtc_begin_data_access - prepare the rtc for data access.
129 * @rtc: pointer to the ds1685 rtc structure.
130 *
131 * This takes several steps to prepare the rtc for access to get/set time
132 * and alarm values from the rtc registers:
133 * - Sets the SET bit in Control Register B.
134 * - Reads Ext Control Register 4A and checks the INCR bit.
135 * - If INCR is active, a short delay is added before Ext Control Register 4A
136 * is read again in a loop until INCR is inactive.
137 * - Switches the rtc to bank 1. This allows access to all relevant
138 * data for normal rtc operation, as bank 0 contains only the nvram.
139 */
140static inline void
141ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
142{
143 /* Set the SET bit in Ctrl B */
144 rtc->write(rtc, RTC_CTRL_B,
145 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
146
147 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
148 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
149 cpu_relax();
150
151 /* Switch to Bank 1 */
152 ds1685_rtc_switch_to_bank1(rtc);
153}
154
155/**
156 * ds1685_rtc_end_data_access - end data access on the rtc.
157 * @rtc: pointer to the ds1685 rtc structure.
158 *
159 * This ends what was started by ds1685_rtc_begin_data_access:
160 * - Switches the rtc back to bank 0.
161 * - Clears the SET bit in Control Register B.
162 */
163static inline void
164ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
165{
166 /* Switch back to Bank 0 */
167 ds1685_rtc_switch_to_bank1(rtc);
168
169 /* Clear the SET bit in Ctrl B */
170 rtc->write(rtc, RTC_CTRL_B,
171 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
172}
173
174/**
175 * ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access.
176 * @rtc: pointer to the ds1685 rtc structure.
177 * @flags: irq flags variable for spin_lock_irqsave.
178 *
179 * This takes several steps to prepare the rtc for access to read just the
180 * control registers:
181 * - Sets a spinlock on the rtc IRQ.
182 * - Switches the rtc to bank 1. This allows access to the two extended
183 * control registers.
184 *
185 * Only use this where you are certain another lock will not be held.
186 */
187static inline void
8c09b9fd 188ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long *flags)
aaaf5fbf 189{
8c09b9fd 190 spin_lock_irqsave(&rtc->lock, *flags);
aaaf5fbf
JK		 191 ds1685_rtc_switch_to_bank1(rtc);
192}
193
194/**
195 * ds1685_rtc_end_ctrl_access - end ctrl access on the rtc.
196 * @rtc: pointer to the ds1685 rtc structure.
197 * @flags: irq flags variable for spin_unlock_irqrestore.
198 *
199 * This ends what was started by ds1685_rtc_begin_ctrl_access:
200 * - Switches the rtc back to bank 0.
201 * - Unsets the spinlock on the rtc IRQ.
202 */
203static inline void
204ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags)
205{
206 ds1685_rtc_switch_to_bank0(rtc);
207 spin_unlock_irqrestore(&rtc->lock, flags);
208}
209
210/**
211 * ds1685_rtc_get_ssn - retrieve the silicon serial number.
212 * @rtc: pointer to the ds1685 rtc structure.
213 * @ssn: u8 array to hold the bits of the silicon serial number.
214 *
215 * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
216 * first byte is the model number, the next six bytes are the serial number
217 * digits, and the final byte is a CRC check byte. Together, they form the
218 * silicon serial number.
219 *
220 * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
221 * called first before calling this function, else data will be read out of
222 * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done.
223 */
224static inline void
225ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
226{
227 ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
228 ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
229 ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
230 ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
231 ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
232 ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
233 ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
234 ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
235}
236/* ----------------------------------------------------------------------- */
237
238
239/* ----------------------------------------------------------------------- */
240/* Read/Set Time & Alarm functions */
241
242/**
243 * ds1685_rtc_read_time - reads the time registers.
244 * @dev: pointer to device structure.
245 * @tm: pointer to rtc_time structure.
246 */
247static int
248ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
249{
250 struct platform_device *pdev = to_platform_device(dev);
251 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
252 u8 ctrlb, century;
253 u8 seconds, minutes, hours, wday, mday, month, years;
254
255 /* Fetch the time info from the RTC registers. */
256 ds1685_rtc_begin_data_access(rtc);
257 seconds = rtc->read(rtc, RTC_SECS);
258 minutes = rtc->read(rtc, RTC_MINS);
259 hours = rtc->read(rtc, RTC_HRS);
260 wday = rtc->read(rtc, RTC_WDAY);
261 mday = rtc->read(rtc, RTC_MDAY);
262 month = rtc->read(rtc, RTC_MONTH);
263 years = rtc->read(rtc, RTC_YEAR);
264 century = rtc->read(rtc, RTC_CENTURY);
265 ctrlb = rtc->read(rtc, RTC_CTRL_B);
266 ds1685_rtc_end_data_access(rtc);
267
268 /* bcd2bin if needed, perform fixups, and store to rtc_time. */
269 years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
270 RTC_YEAR_BIN_MASK);
271 century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
272 RTC_CENTURY_MASK);
273 tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
274 RTC_SECS_BIN_MASK);
275 tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
276 RTC_MINS_BIN_MASK);
277 tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
278 RTC_HRS_24_BIN_MASK);
279 tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
280 RTC_WDAY_MASK) - 1);
281 tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
282 RTC_MDAY_BIN_MASK);
283 tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
284 RTC_MONTH_BIN_MASK) - 1);
285 tm->tm_year = ((years + (century * 100)) - 1900);
286 tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
287 tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
288
289 return rtc_valid_tm(tm);
290}
291
292/**
293 * ds1685_rtc_set_time - sets the time registers.
294 * @dev: pointer to device structure.
295 * @tm: pointer to rtc_time structure.
296 */
297static int
298ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
299{
300 struct platform_device *pdev = to_platform_device(dev);
301 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
302 u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
303
304 /* Fetch the time info from rtc_time. */
305 seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
306 RTC_SECS_BCD_MASK);
307 minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
308 RTC_MINS_BCD_MASK);
309 hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
310 RTC_HRS_24_BCD_MASK);
311 wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
312 RTC_WDAY_MASK);
313 mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
314 RTC_MDAY_BCD_MASK);
315 month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
316 RTC_MONTH_BCD_MASK);
317 years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
318 RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
319 century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
320 RTC_CENTURY_MASK, RTC_CENTURY_MASK);
321
322 /*
323 * Perform Sanity Checks:
324 * - Months: !> 12, Month Day != 0.
325 * - Month Day !> Max days in current month.
326 * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
327 */
328 if ((tm->tm_mon > 11) || (mday == 0))
329 return -EDOM;
330
331 if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
332 return -EDOM;
333
334 if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
335 (tm->tm_sec >= 60) || (wday > 7))
336 return -EDOM;
337
338 /*
339 * Set the data mode to use and store the time values in the
340 * RTC registers.
341 */
342 ds1685_rtc_begin_data_access(rtc);
343 ctrlb = rtc->read(rtc, RTC_CTRL_B);
344 if (rtc->bcd_mode)
345 ctrlb &= ~(RTC_CTRL_B_DM);
346 else
347 ctrlb |= RTC_CTRL_B_DM;
348 rtc->write(rtc, RTC_CTRL_B, ctrlb);
349 rtc->write(rtc, RTC_SECS, seconds);
350 rtc->write(rtc, RTC_MINS, minutes);
351 rtc->write(rtc, RTC_HRS, hours);
352 rtc->write(rtc, RTC_WDAY, wday);
353 rtc->write(rtc, RTC_MDAY, mday);
354 rtc->write(rtc, RTC_MONTH, month);
355 rtc->write(rtc, RTC_YEAR, years);
356 rtc->write(rtc, RTC_CENTURY, century);
357 ds1685_rtc_end_data_access(rtc);
358
359 return 0;
360}
361
362/**
363 * ds1685_rtc_read_alarm - reads the alarm registers.
364 * @dev: pointer to device structure.
365 * @alrm: pointer to rtc_wkalrm structure.
366 *
367 * There are three primary alarm registers: seconds, minutes, and hours.
368 * A fourth alarm register for the month date is also available in bank1 for
369 * kickstart/wakeup features. The DS1685/DS1687 manual states that a
370 * "don't care" value ranging from 0xc0 to 0xff may be written into one or
371 * more of the three alarm bytes to act as a wildcard value. The fourth
372 * byte doesn't support a "don't care" value.
373 */
374static int
375ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
376{
377 struct platform_device *pdev = to_platform_device(dev);
378 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
379 u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
380
381 /* Fetch the alarm info from the RTC alarm registers. */
382 ds1685_rtc_begin_data_access(rtc);
383 seconds = rtc->read(rtc, RTC_SECS_ALARM);
384 minutes = rtc->read(rtc, RTC_MINS_ALARM);
385 hours = rtc->read(rtc, RTC_HRS_ALARM);
386 mday = rtc->read(rtc, RTC_MDAY_ALARM);
387 ctrlb = rtc->read(rtc, RTC_CTRL_B);
388 ctrlc = rtc->read(rtc, RTC_CTRL_C);
389 ds1685_rtc_end_data_access(rtc);
390
391 /* Check month date. */
392 if (!(mday >= 1) && (mday <= 31))
393 return -EDOM;
394
395 /*
396 * Check the three alarm bytes.
397 *
398 * The Linux RTC system doesn't support the "don't care" capability
399 * of this RTC chip. We check for it anyways in case support is
400 * added in the future.
401 */
39ea34cc 402 if (unlikely(seconds >= 0xc0))
aaaf5fbf
JK		 403 alrm->time.tm_sec = -1;
404 else
405 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
406 RTC_SECS_BCD_MASK,
407 RTC_SECS_BIN_MASK);
408
39ea34cc 409 if (unlikely(minutes >= 0xc0))
aaaf5fbf
JK		 410 alrm->time.tm_min = -1;
411 else
412 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
413 RTC_MINS_BCD_MASK,
414 RTC_MINS_BIN_MASK);
415
39ea34cc 416 if (unlikely(hours >= 0xc0))
aaaf5fbf
JK		 417 alrm->time.tm_hour = -1;
418 else
419 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
420 RTC_HRS_24_BCD_MASK,
421 RTC_HRS_24_BIN_MASK);
422
423 /* Write the data to rtc_wkalrm. */
424 alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
425 RTC_MDAY_BIN_MASK);
426 alrm->time.tm_mon = -1;
427 alrm->time.tm_year = -1;
428 alrm->time.tm_wday = -1;
429 alrm->time.tm_yday = -1;
430 alrm->time.tm_isdst = -1;
431 alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
432 alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
433
434 return 0;
435}
436
437/**
438 * ds1685_rtc_set_alarm - sets the alarm in registers.
439 * @dev: pointer to device structure.
440 * @alrm: pointer to rtc_wkalrm structure.
441 */
442static int
443ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
444{
445 struct platform_device *pdev = to_platform_device(dev);
446 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
447 u8 ctrlb, seconds, minutes, hours, mday;
448
449 /* Fetch the alarm info and convert to BCD. */
450 seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
451 RTC_SECS_BIN_MASK,
452 RTC_SECS_BCD_MASK);
453 minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
454 RTC_MINS_BIN_MASK,
455 RTC_MINS_BCD_MASK);
456 hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
457 RTC_HRS_24_BIN_MASK,
458 RTC_HRS_24_BCD_MASK);
459 mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
460 RTC_MDAY_BIN_MASK,
461 RTC_MDAY_BCD_MASK);
462
463 /* Check the month date for validity. */
464 if (!(mday >= 1) && (mday <= 31))
465 return -EDOM;
466
467 /*
468 * Check the three alarm bytes.
469 *
470 * The Linux RTC system doesn't support the "don't care" capability
471 * of this RTC chip because rtc_valid_tm tries to validate every
472 * field, and we only support four fields. We put the support
473 * here anyways for the future.
474 */
39ea34cc 475 if (unlikely(seconds >= 0xc0))
aaaf5fbf
JK		 476 seconds = 0xff;
477
39ea34cc 478 if (unlikely(minutes >= 0xc0))
aaaf5fbf
JK		 479 minutes = 0xff;
480
39ea34cc 481 if (unlikely(hours >= 0xc0))
aaaf5fbf
JK		 482 hours = 0xff;
483
484 alrm->time.tm_mon = -1;
485 alrm->time.tm_year = -1;
486 alrm->time.tm_wday = -1;
487 alrm->time.tm_yday = -1;
488 alrm->time.tm_isdst = -1;
489
490 /* Disable the alarm interrupt first. */
491 ds1685_rtc_begin_data_access(rtc);
492 ctrlb = rtc->read(rtc, RTC_CTRL_B);
493 rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
494
495 /* Read ctrlc to clear RTC_CTRL_C_AF. */
496 rtc->read(rtc, RTC_CTRL_C);
497
498 /*
499 * Set the data mode to use and store the time values in the
500 * RTC registers.
501 */
502 ctrlb = rtc->read(rtc, RTC_CTRL_B);
503 if (rtc->bcd_mode)
504 ctrlb &= ~(RTC_CTRL_B_DM);
505 else
506 ctrlb |= RTC_CTRL_B_DM;
507 rtc->write(rtc, RTC_CTRL_B, ctrlb);
508 rtc->write(rtc, RTC_SECS_ALARM, seconds);
509 rtc->write(rtc, RTC_MINS_ALARM, minutes);
510 rtc->write(rtc, RTC_HRS_ALARM, hours);
511 rtc->write(rtc, RTC_MDAY_ALARM, mday);
512
513 /* Re-enable the alarm if needed. */
514 if (alrm->enabled) {
515 ctrlb = rtc->read(rtc, RTC_CTRL_B);
516 ctrlb |= RTC_CTRL_B_AIE;
517 rtc->write(rtc, RTC_CTRL_B, ctrlb);
518 }
519
520 /* Done! */
521 ds1685_rtc_end_data_access(rtc);
522
523 return 0;
524}
525/* ----------------------------------------------------------------------- */
526
527
528/* ----------------------------------------------------------------------- */
529/* /dev/rtcX Interface functions */
530
aaaf5fbf
JK		 531/**
532 * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
533 * @dev: pointer to device structure.
534 * @enabled: flag indicating whether to enable or disable.
535 */
536static int
537ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
538{
539 struct ds1685_priv *rtc = dev_get_drvdata(dev);
540 unsigned long flags = 0;
541
542 /* Enable/disable the Alarm IRQ-Enable flag. */
543 spin_lock_irqsave(&rtc->lock, flags);
544
545 /* Flip the requisite interrupt-enable bit. */
546 if (enabled)
547 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
548 RTC_CTRL_B_AIE));
549 else
550 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
551 ~(RTC_CTRL_B_AIE)));
552
553 /* Read Control C to clear all the flag bits. */
554 rtc->read(rtc, RTC_CTRL_C);
555 spin_unlock_irqrestore(&rtc->lock, flags);
556
557 return 0;
558}
aaaf5fbf
JK		 559/* ----------------------------------------------------------------------- */
560
561
562/* ----------------------------------------------------------------------- */
563/* IRQ handler & workqueue. */
564
565/**
566 * ds1685_rtc_irq_handler - IRQ handler.
567 * @irq: IRQ number.
568 * @dev_id: platform device pointer.
569 */
570static irqreturn_t
571ds1685_rtc_irq_handler(int irq, void *dev_id)
572{
573 struct platform_device *pdev = dev_id;
574 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
575 u8 ctrlb, ctrlc;
576 unsigned long events = 0;
577 u8 num_irqs = 0;
578
579 /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
580 if (unlikely(!rtc))
581 return IRQ_HANDLED;
582
583 /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
584 spin_lock(&rtc->lock);
585 ctrlb = rtc->read(rtc, RTC_CTRL_B);
586 ctrlc = rtc->read(rtc, RTC_CTRL_C);
587
588 /* Is the IRQF bit set? */
589 if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
590 /*
591 * We need to determine if it was one of the standard
592 * events: PF, AF, or UF. If so, we handle them and
593 * update the RTC core.
594 */
595 if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
596 events = RTC_IRQF;
597
598 /* Check for a periodic interrupt. */
599 if ((ctrlb & RTC_CTRL_B_PIE) &&
600 (ctrlc & RTC_CTRL_C_PF)) {
601 events |= RTC_PF;
602 num_irqs++;
603 }
604
605 /* Check for an alarm interrupt. */
606 if ((ctrlb & RTC_CTRL_B_AIE) &&
607 (ctrlc & RTC_CTRL_C_AF)) {
608 events |= RTC_AF;
609 num_irqs++;
610 }
611
612 /* Check for an update interrupt. */
613 if ((ctrlb & RTC_CTRL_B_UIE) &&
614 (ctrlc & RTC_CTRL_C_UF)) {
615 events |= RTC_UF;
616 num_irqs++;
617 }
618
619 rtc_update_irq(rtc->dev, num_irqs, events);
620 } else {
621 /*
622 * One of the "extended" interrupts was received that
623 * is not recognized by the RTC core. These need to
624 * be handled in task context as they can call other
625 * functions and the time spent in irq context needs
626 * to be minimized. Schedule them into a workqueue
627 * and inform the RTC core that the IRQs were handled.
628 */
629 spin_unlock(&rtc->lock);
630 schedule_work(&rtc->work);
631 rtc_update_irq(rtc->dev, 0, 0);
632 return IRQ_HANDLED;
633 }
634 }
635 spin_unlock(&rtc->lock);
636
637 return events ? IRQ_HANDLED : IRQ_NONE;
638}
639
640/**
641 * ds1685_rtc_work_queue - work queue handler.
642 * @work: work_struct containing data to work on in task context.
643 */
644static void
645ds1685_rtc_work_queue(struct work_struct *work)
646{
647 struct ds1685_priv *rtc = container_of(work,
648 struct ds1685_priv, work);
649 struct platform_device *pdev = to_platform_device(&rtc->dev->dev);
650 struct mutex *rtc_mutex = &rtc->dev->ops_lock;
651 u8 ctrl4a, ctrl4b;
652
653 mutex_lock(rtc_mutex);
654
655 ds1685_rtc_switch_to_bank1(rtc);
656 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
657 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
658
659 /*
660 * Check for a kickstart interrupt. With Vcc applied, this
661 * typically means that the power button was pressed, so we
662 * begin the shutdown sequence.
663 */
664 if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
665 /* Briefly disable kickstarts to debounce button presses. */
666 rtc->write(rtc, RTC_EXT_CTRL_4B,
667 (rtc->read(rtc, RTC_EXT_CTRL_4B) &
668 ~(RTC_CTRL_4B_KSE)));
669
670 /* Clear the kickstart flag. */
671 rtc->write(rtc, RTC_EXT_CTRL_4A,
672 (ctrl4a & ~(RTC_CTRL_4A_KF)));
673
674
675 /*
676 * Sleep 500ms before re-enabling kickstarts. This allows
677 * adequate time to avoid reading signal jitter as additional
678 * button presses.
679 */
680 msleep(500);
681 rtc->write(rtc, RTC_EXT_CTRL_4B,
682 (rtc->read(rtc, RTC_EXT_CTRL_4B) |
683 RTC_CTRL_4B_KSE));
684
685 /* Call the platform pre-poweroff function. Else, shutdown. */
686 if (rtc->prepare_poweroff != NULL)
687 rtc->prepare_poweroff();
688 else
689 ds1685_rtc_poweroff(pdev);
690 }
691
692 /*
693 * Check for a wake-up interrupt. With Vcc applied, this is
694 * essentially a second alarm interrupt, except it takes into
695 * account the 'date' register in bank1 in addition to the
696 * standard three alarm registers.
697 */
698 if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
699 rtc->write(rtc, RTC_EXT_CTRL_4A,
700 (ctrl4a & ~(RTC_CTRL_4A_WF)));
701
702 /* Call the platform wake_alarm function if defined. */
703 if (rtc->wake_alarm != NULL)
704 rtc->wake_alarm();
705 else
706 dev_warn(&pdev->dev,
707 "Wake Alarm IRQ just occurred!\n");
708 }
709
710 /*
711 * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0
712 * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting
713 * each byte to a logic 1. This has no effect on any extended
714 * NV-SRAM that might be present, nor on the time/calendar/alarm
715 * registers. After a ram-clear is completed, there is a minimum
716 * recovery time of ~150ms in which all reads/writes are locked out.
717 * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot
718 * catch this scenario.
719 */
720 if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
721 rtc->write(rtc, RTC_EXT_CTRL_4A,
722 (ctrl4a & ~(RTC_CTRL_4A_RF)));
723 msleep(150);
724
725 /* Call the platform post_ram_clear function if defined. */
726 if (rtc->post_ram_clear != NULL)
727 rtc->post_ram_clear();
728 else
729 dev_warn(&pdev->dev,
730 "RAM-Clear IRQ just occurred!\n");
731 }
732 ds1685_rtc_switch_to_bank0(rtc);
733
734 mutex_unlock(rtc_mutex);
735}
736/* ----------------------------------------------------------------------- */
737
738
739/* ----------------------------------------------------------------------- */
740/* ProcFS interface */
741
742#ifdef CONFIG_PROC_FS
743#define NUM_REGS 6 /* Num of control registers. */
744#define NUM_BITS 8 /* Num bits per register. */
745#define NUM_SPACES 4 /* Num spaces between each bit. */
746
747/*
748 * Periodic Interrupt Rates.
749 */
750static const char *ds1685_rtc_pirq_rate[16] = {
751 "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
752 "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
753 "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
754};
755
756/*
757 * Square-Wave Output Frequencies.
758 */
759static const char *ds1685_rtc_sqw_freq[16] = {
760 "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
761 "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
762};
763
764#ifdef CONFIG_RTC_DS1685_PROC_REGS
765/**
766 * ds1685_rtc_print_regs - helper function to print register values.
767 * @hex: hex byte to convert into binary bits.
768 * @dest: destination char array.
769 *
770 * This is basically a hex->binary function, just with extra spacing between
771 * the digits. It only works on 1-byte values (8 bits).
772 */
773static char*
774ds1685_rtc_print_regs(u8 hex, char *dest)
775{
776 u32 i, j;
777 char *tmp = dest;
778
779 for (i = 0; i < NUM_BITS; i++) {
780 *tmp++ = ((hex & 0x80) != 0 ? '1' : '0');
781 for (j = 0; j < NUM_SPACES; j++)
782 *tmp++ = ' ';
783 hex <<= 1;
784 }
785 *tmp++ = '\0';
786
787 return dest;
788}
789#endif
790
791/**
792 * ds1685_rtc_proc - procfs access function.
793 * @dev: pointer to device structure.
794 * @seq: pointer to seq_file structure.
795 */
796static int
797ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
798{
799 struct platform_device *pdev = to_platform_device(dev);
800 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
801 u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8];
52ef84d5 802 char *model;
aaaf5fbf
JK		 803#ifdef CONFIG_RTC_DS1685_PROC_REGS
804 char bits[NUM_REGS][(NUM_BITS * NUM_SPACES) + NUM_BITS + 1];
805#endif
806
807 /* Read all the relevant data from the control registers. */
808 ds1685_rtc_switch_to_bank1(rtc);
809 ds1685_rtc_get_ssn(rtc, ssn);
810 ctrla = rtc->read(rtc, RTC_CTRL_A);
811 ctrlb = rtc->read(rtc, RTC_CTRL_B);
812 ctrlc = rtc->read(rtc, RTC_CTRL_C);
813 ctrld = rtc->read(rtc, RTC_CTRL_D);
814 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
815 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
816 ds1685_rtc_switch_to_bank0(rtc);
817
818 /* Determine the RTC model. */
819 switch (ssn[0]) {
820 case RTC_MODEL_DS1685:
821 model = "DS1685/DS1687\0";
822 break;
823 case RTC_MODEL_DS1689:
824 model = "DS1689/DS1693\0";
825 break;
826 case RTC_MODEL_DS17285:
827 model = "DS17285/DS17287\0";
828 break;
829 case RTC_MODEL_DS17485:
830 model = "DS17485/DS17487\0";
831 break;
832 case RTC_MODEL_DS17885:
833 model = "DS17885/DS17887\0";
834 break;
835 default:
836 model = "Unknown\0";
837 break;
838 }
839
840 /* Print out the information. */
841 seq_printf(seq,
842 "Model\t\t: %s\n"
843 "Oscillator\t: %s\n"
844 "12/24hr\t\t: %s\n"
845 "DST\t\t: %s\n"
846 "Data mode\t: %s\n"
847 "Battery\t\t: %s\n"
848 "Aux batt\t: %s\n"
849 "Update IRQ\t: %s\n"
850 "Periodic IRQ\t: %s\n"
851 "Periodic Rate\t: %s\n"
852 "SQW Freq\t: %s\n"
853#ifdef CONFIG_RTC_DS1685_PROC_REGS
ff67abd2 854 "Serial #\t: %8phC\n"
aaaf5fbf
JK		 855 "Register Status\t:\n"
856 " Ctrl A\t: UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n"
857 "\t\t: %s\n"
858 " Ctrl B\t: SET PIE AIE UIE SQWE DM 2412 DSE\n"
859 "\t\t: %s\n"
860 " Ctrl C\t: IRQF PF AF UF --- --- --- ---\n"
861 "\t\t: %s\n"
862 " Ctrl D\t: VRT --- --- --- --- --- --- ---\n"
863 "\t\t: %s\n"
864#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
865 " Ctrl 4A\t: VRT2 INCR BME --- PAB RF WF KF\n"
866#else
867 " Ctrl 4A\t: VRT2 INCR --- --- PAB RF WF KF\n"
868#endif
869 "\t\t: %s\n"
870 " Ctrl 4B\t: ABE E32k CS RCE PRS RIE WIE KSE\n"
871 "\t\t: %s\n",
872#else
ff67abd2 873 "Serial #\t: %8phC\n",
aaaf5fbf
JK		 874#endif
875 model,
876 ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
877 ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
878 ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
879 ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
880 ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
881 ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
882 ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
883 ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
884 (!(ctrl4b & RTC_CTRL_4B_E32K) ?
885 ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
886 (!((ctrl4b & RTC_CTRL_4B_E32K)) ?
887 ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
888#ifdef CONFIG_RTC_DS1685_PROC_REGS
ff67abd2 889 ssn,
aaaf5fbf
JK		 890 ds1685_rtc_print_regs(ctrla, bits[0]),
891 ds1685_rtc_print_regs(ctrlb, bits[1]),
892 ds1685_rtc_print_regs(ctrlc, bits[2]),
893 ds1685_rtc_print_regs(ctrld, bits[3]),
894 ds1685_rtc_print_regs(ctrl4a, bits[4]),
895 ds1685_rtc_print_regs(ctrl4b, bits[5]));
896#else
ff67abd2 897 ssn);
aaaf5fbf
JK		 898#endif
899 return 0;
900}
901#else
902#define ds1685_rtc_proc NULL
903#endif /* CONFIG_PROC_FS */
904/* ----------------------------------------------------------------------- */
905
906
907/* ----------------------------------------------------------------------- */
908/* RTC Class operations */
909
910static const struct rtc_class_ops
911ds1685_rtc_ops = {
912 .proc = ds1685_rtc_proc,
913 .read_time = ds1685_rtc_read_time,
914 .set_time = ds1685_rtc_set_time,
915 .read_alarm = ds1685_rtc_read_alarm,
916 .set_alarm = ds1685_rtc_set_alarm,
917 .alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
918};
919/* ----------------------------------------------------------------------- */
920
921
922/* ----------------------------------------------------------------------- */
923/* SysFS interface */
924
925#ifdef CONFIG_SYSFS
926/**
927 * ds1685_rtc_sysfs_nvram_read - reads rtc nvram via sysfs.
928 * @file: pointer to file structure.
929 * @kobj: pointer to kobject structure.
930 * @bin_attr: pointer to bin_attribute structure.
931 * @buf: pointer to char array to hold the output.
932 * @pos: current file position pointer.
933 * @size: size of the data to read.
934 */
935static ssize_t
936ds1685_rtc_sysfs_nvram_read(struct file *filp, struct kobject *kobj,
937 struct bin_attribute *bin_attr, char *buf,
938 loff_t pos, size_t size)
939{
940 struct platform_device *pdev =
941 to_platform_device(container_of(kobj, struct device, kobj));
942 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
943 ssize_t count;
944 unsigned long flags = 0;
945
946 spin_lock_irqsave(&rtc->lock, flags);
947 ds1685_rtc_switch_to_bank0(rtc);
948
949 /* Read NVRAM in time and bank0 registers. */
950 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
951 count++, size--) {
952 if (count < NVRAM_SZ_TIME)
953 *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
954 else
955 *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
956 }
957
958#ifndef CONFIG_RTC_DRV_DS1689
959 if (size > 0) {
960 ds1685_rtc_switch_to_bank1(rtc);
961
962#ifndef CONFIG_RTC_DRV_DS1685
963 /* Enable burst-mode on DS17x85/DS17x87 */
964 rtc->write(rtc, RTC_EXT_CTRL_4A,
965 (rtc->read(rtc, RTC_EXT_CTRL_4A) |
966 RTC_CTRL_4A_BME));
967
968 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
969 * reading with burst-mode */
970 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
971 (pos - NVRAM_TOTAL_SZ_BANK0));
972#endif
973
974 /* Read NVRAM in bank1 registers. */
975 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
976 count++, size--) {
977#ifdef CONFIG_RTC_DRV_DS1685
978 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
979 * before each read. */
980 rtc->write(rtc, RTC_BANK1_RAM_ADDR,
981 (pos - NVRAM_TOTAL_SZ_BANK0));
982#endif
983 *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
984 pos++;
985 }
986
987#ifndef CONFIG_RTC_DRV_DS1685
988 /* Disable burst-mode on DS17x85/DS17x87 */
989 rtc->write(rtc, RTC_EXT_CTRL_4A,
990 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
991 ~(RTC_CTRL_4A_BME)));
992#endif
993 ds1685_rtc_switch_to_bank0(rtc);
994 }
995#endif /* !CONFIG_RTC_DRV_DS1689 */
996 spin_unlock_irqrestore(&rtc->lock, flags);
997
998 /*
999 * XXX: Bug? this appears to cause the function to get executed
1000 * several times in succession. But it's the only way to actually get
1001 * data written out to a file.
1002 */
1003 return count;
1004}
1005
1006/**
1007 * ds1685_rtc_sysfs_nvram_write - writes rtc nvram via sysfs.
1008 * @file: pointer to file structure.
1009 * @kobj: pointer to kobject structure.
1010 * @bin_attr: pointer to bin_attribute structure.
1011 * @buf: pointer to char array to hold the input.
1012 * @pos: current file position pointer.
1013 * @size: size of the data to write.
1014 */
1015static ssize_t
1016ds1685_rtc_sysfs_nvram_write(struct file *filp, struct kobject *kobj,
1017 struct bin_attribute *bin_attr, char *buf,
1018 loff_t pos, size_t size)
1019{
1020 struct platform_device *pdev =
1021 to_platform_device(container_of(kobj, struct device, kobj));
1022 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1023 ssize_t count;
1024 unsigned long flags = 0;
1025
1026 spin_lock_irqsave(&rtc->lock, flags);
1027 ds1685_rtc_switch_to_bank0(rtc);
1028
1029 /* Write NVRAM in time and bank0 registers. */
1030 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
1031 count++, size--)
1032 if (count < NVRAM_SZ_TIME)
1033 rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
1034 *buf++);
1035 else
1036 rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
1037
1038#ifndef CONFIG_RTC_DRV_DS1689
1039 if (size > 0) {
1040 ds1685_rtc_switch_to_bank1(rtc);
1041
1042#ifndef CONFIG_RTC_DRV_DS1685
1043 /* Enable burst-mode on DS17x85/DS17x87 */
1044 rtc->write(rtc, RTC_EXT_CTRL_4A,
1045 (rtc->read(rtc, RTC_EXT_CTRL_4A) |
1046 RTC_CTRL_4A_BME));
1047
1048 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
1049 * writing with burst-mode */
1050 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
1051 (pos - NVRAM_TOTAL_SZ_BANK0));
1052#endif
1053
1054 /* Write NVRAM in bank1 registers. */
1055 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
1056 count++, size--) {
1057#ifdef CONFIG_RTC_DRV_DS1685
1058 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
1059 * before each read. */
1060 rtc->write(rtc, RTC_BANK1_RAM_ADDR,
1061 (pos - NVRAM_TOTAL_SZ_BANK0));
1062#endif
1063 rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
1064 pos++;
1065 }
1066
1067#ifndef CONFIG_RTC_DRV_DS1685
1068 /* Disable burst-mode on DS17x85/DS17x87 */
1069 rtc->write(rtc, RTC_EXT_CTRL_4A,
1070 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
1071 ~(RTC_CTRL_4A_BME)));
1072#endif
1073 ds1685_rtc_switch_to_bank0(rtc);
1074 }
1075#endif /* !CONFIG_RTC_DRV_DS1689 */
1076 spin_unlock_irqrestore(&rtc->lock, flags);
1077
1078 return count;
1079}
1080
1081/**
1082 * struct ds1685_rtc_sysfs_nvram_attr - sysfs attributes for rtc nvram.
1083 * @attr: nvram attributes.
1084 * @read: nvram read function.
1085 * @write: nvram write function.
1086 * @size: nvram total size (bank0 + extended).
1087 */
1088static struct bin_attribute
1089ds1685_rtc_sysfs_nvram_attr = {
1090 .attr = {
1091 .name = "nvram",
1092 .mode = S_IRUGO | S_IWUSR,
1093 },
1094 .read = ds1685_rtc_sysfs_nvram_read,
1095 .write = ds1685_rtc_sysfs_nvram_write,
1096 .size = NVRAM_TOTAL_SZ
1097};
1098
1099/**
1100 * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
1101 * @dev: pointer to device structure.
1102 * @attr: pointer to device_attribute structure.
1103 * @buf: pointer to char array to hold the output.
1104 */
1105static ssize_t
1106ds1685_rtc_sysfs_battery_show(struct device *dev,
1107 struct device_attribute *attr, char *buf)
1108{
1109 struct platform_device *pdev = to_platform_device(dev);
1110 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1111 u8 ctrld;
1112
1113 ctrld = rtc->read(rtc, RTC_CTRL_D);
1114
9c25a106 1115 return sprintf(buf, "%s\n",
aaaf5fbf
JK		 1116 (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
1117}
1118static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
1119
1120/**
1121 * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
1122 * @dev: pointer to device structure.
1123 * @attr: pointer to device_attribute structure.
1124 * @buf: pointer to char array to hold the output.
1125 */
1126static ssize_t
1127ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
1128 struct device_attribute *attr, char *buf)
1129{
1130 struct platform_device *pdev = to_platform_device(dev);
1131 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1132 u8 ctrl4a;
1133
1134 ds1685_rtc_switch_to_bank1(rtc);
1135 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1136 ds1685_rtc_switch_to_bank0(rtc);
1137
9c25a106 1138 return sprintf(buf, "%s\n",
aaaf5fbf
JK		 1139 (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
1140}
1141static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
1142
1143/**
1144 * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
1145 * @dev: pointer to device structure.
1146 * @attr: pointer to device_attribute structure.
1147 * @buf: pointer to char array to hold the output.
1148 */
1149static ssize_t
1150ds1685_rtc_sysfs_serial_show(struct device *dev,
1151 struct device_attribute *attr, char *buf)
1152{
1153 struct platform_device *pdev = to_platform_device(dev);
1154 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1155 u8 ssn[8];
1156
1157 ds1685_rtc_switch_to_bank1(rtc);
1158 ds1685_rtc_get_ssn(rtc, ssn);
1159 ds1685_rtc_switch_to_bank0(rtc);
1160
9c25a106 1161 return sprintf(buf, "%8phC\n", ssn);
aaaf5fbf
JK		 1162}
1163static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
1164
1165/**
1166 * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
1167 */
1168static struct attribute*
1169ds1685_rtc_sysfs_misc_attrs[] = {
1170 &dev_attr_battery.attr,
1171 &dev_attr_auxbatt.attr,
1172 &dev_attr_serial.attr,
1173 NULL,
1174};
1175
1176/**
1177 * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
1178 */
1179static const struct attribute_group
1180ds1685_rtc_sysfs_misc_grp = {
1181 .name = "misc",
1182 .attrs = ds1685_rtc_sysfs_misc_attrs,
1183};
1184
1185#ifdef CONFIG_RTC_DS1685_SYSFS_REGS
1186/**
1187 * struct ds1685_rtc_ctrl_regs.
1188 * @name: char pointer for the bit name.
1189 * @reg: control register the bit is in.
1190 * @bit: the bit's offset in the register.
1191 */
1192struct ds1685_rtc_ctrl_regs {
1193 const char *name;
1194 const u8 reg;
1195 const u8 bit;
1196};
1197
1198/*
1199 * Ctrl register bit lookup table.
1200 */
1201static const struct ds1685_rtc_ctrl_regs
1202ds1685_ctrl_regs_table[] = {
1203 { "uip", RTC_CTRL_A, RTC_CTRL_A_UIP },
1204 { "dv2", RTC_CTRL_A, RTC_CTRL_A_DV2 },
1205 { "dv1", RTC_CTRL_A, RTC_CTRL_A_DV1 },
1206 { "dv0", RTC_CTRL_A, RTC_CTRL_A_DV0 },
1207 { "rs3", RTC_CTRL_A, RTC_CTRL_A_RS3 },
1208 { "rs2", RTC_CTRL_A, RTC_CTRL_A_RS2 },
1209 { "rs1", RTC_CTRL_A, RTC_CTRL_A_RS1 },
1210 { "rs0", RTC_CTRL_A, RTC_CTRL_A_RS0 },
1211 { "set", RTC_CTRL_B, RTC_CTRL_B_SET },
1212 { "pie", RTC_CTRL_B, RTC_CTRL_B_PIE },
1213 { "aie", RTC_CTRL_B, RTC_CTRL_B_AIE },
1214 { "uie", RTC_CTRL_B, RTC_CTRL_B_UIE },
1215 { "sqwe", RTC_CTRL_B, RTC_CTRL_B_SQWE },
1216 { "dm", RTC_CTRL_B, RTC_CTRL_B_DM },
1217 { "2412", RTC_CTRL_B, RTC_CTRL_B_2412 },
1218 { "dse", RTC_CTRL_B, RTC_CTRL_B_DSE },
1219 { "irqf", RTC_CTRL_C, RTC_CTRL_C_IRQF },
1220 { "pf", RTC_CTRL_C, RTC_CTRL_C_PF },
1221 { "af", RTC_CTRL_C, RTC_CTRL_C_AF },
1222 { "uf", RTC_CTRL_C, RTC_CTRL_C_UF },
1223 { "vrt", RTC_CTRL_D, RTC_CTRL_D_VRT },
1224 { "vrt2", RTC_EXT_CTRL_4A, RTC_CTRL_4A_VRT2 },
1225 { "incr", RTC_EXT_CTRL_4A, RTC_CTRL_4A_INCR },
1226 { "pab", RTC_EXT_CTRL_4A, RTC_CTRL_4A_PAB },
1227 { "rf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_RF },
1228 { "wf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_WF },
1229 { "kf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_KF },
1230#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
1231 { "bme", RTC_EXT_CTRL_4A, RTC_CTRL_4A_BME },
1232#endif
1233 { "abe", RTC_EXT_CTRL_4B, RTC_CTRL_4B_ABE },
1234 { "e32k", RTC_EXT_CTRL_4B, RTC_CTRL_4B_E32K },
1235 { "cs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_CS },
1236 { "rce", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RCE },
1237 { "prs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_PRS },
1238 { "rie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RIE },
1239 { "wie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_WIE },
1240 { "kse", RTC_EXT_CTRL_4B, RTC_CTRL_4B_KSE },
1241 { NULL, 0, 0 },
1242};
1243
1244/**
1245 * ds1685_rtc_sysfs_ctrl_regs_lookup - ctrl register bit lookup function.
1246 * @name: ctrl register bit to look up in ds1685_ctrl_regs_table.
1247 */
1248static const struct ds1685_rtc_ctrl_regs*
1249ds1685_rtc_sysfs_ctrl_regs_lookup(const char *name)
1250{
1251 const struct ds1685_rtc_ctrl_regs *p = ds1685_ctrl_regs_table;
1252
1253 for (; p->name != NULL; ++p)
1254 if (strcmp(p->name, name) == 0)
1255 return p;
1256
1257 return NULL;
1258}
1259
1260/**
1261 * ds1685_rtc_sysfs_ctrl_regs_show - reads a ctrl register bit via sysfs.
1262 * @dev: pointer to device structure.
1263 * @attr: pointer to device_attribute structure.
1264 * @buf: pointer to char array to hold the output.
1265 */
1266static ssize_t
1267ds1685_rtc_sysfs_ctrl_regs_show(struct device *dev,
1268 struct device_attribute *attr, char *buf)
1269{
1270 u8 tmp;
1271 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1272 const struct ds1685_rtc_ctrl_regs *reg_info =
1273 ds1685_rtc_sysfs_ctrl_regs_lookup(attr->attr.name);
1274
1275 /* Make sure we actually matched something. */
1276 if (!reg_info)
1277 return -EINVAL;
1278
1279 /* No spinlock during a read -- mutex is already held. */
1280 ds1685_rtc_switch_to_bank1(rtc);
1281 tmp = rtc->read(rtc, reg_info->reg) & reg_info->bit;
1282 ds1685_rtc_switch_to_bank0(rtc);
1283
9c25a106 1284 return sprintf(buf, "%d\n", (tmp ? 1 : 0));
aaaf5fbf
JK		 1285}
1286
1287/**
1288 * ds1685_rtc_sysfs_ctrl_regs_store - writes a ctrl register bit via sysfs.
1289 * @dev: pointer to device structure.
1290 * @attr: pointer to device_attribute structure.
1291 * @buf: pointer to char array to hold the output.
1292 * @count: number of bytes written.
1293 */
1294static ssize_t
1295ds1685_rtc_sysfs_ctrl_regs_store(struct device *dev,
1296 struct device_attribute *attr,
1297 const char *buf, size_t count)
1298{
1299 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1300 u8 reg = 0, bit = 0, tmp;
8c09b9fd 1301 unsigned long flags;
aaaf5fbf
JK		 1302 long int val = 0;
1303 const struct ds1685_rtc_ctrl_regs *reg_info =
1304 ds1685_rtc_sysfs_ctrl_regs_lookup(attr->attr.name);
1305
1306 /* We only accept numbers. */
1307 if (kstrtol(buf, 10, &val) < 0)
1308 return -EINVAL;
1309
1310 /* bits are binary, 0 or 1 only. */
1311 if ((val != 0) && (val != 1))
1312 return -ERANGE;
1313
1314 /* Make sure we actually matched something. */
1315 if (!reg_info)
1316 return -EINVAL;
1317
1318 reg = reg_info->reg;
1319 bit = reg_info->bit;
1320
1321 /* Safe to spinlock during a write. */
8c09b9fd 1322 ds1685_rtc_begin_ctrl_access(rtc, &flags);
aaaf5fbf
JK		 1323 tmp = rtc->read(rtc, reg);
1324 rtc->write(rtc, reg, (val ? (tmp | bit) : (tmp & ~(bit))));
1325 ds1685_rtc_end_ctrl_access(rtc, flags);
1326
1327 return count;
1328}
1329
1330/**
1331 * DS1685_RTC_SYSFS_CTRL_REG_RO - device_attribute for read-only register bit.
1332 * @bit: bit to read.
1333 */
1334#define DS1685_RTC_SYSFS_CTRL_REG_RO(bit) \
1335 static DEVICE_ATTR(bit, S_IRUGO, \
1336 ds1685_rtc_sysfs_ctrl_regs_show, NULL)
1337
1338/**
1339 * DS1685_RTC_SYSFS_CTRL_REG_RW - device_attribute for read-write register bit.
1340 * @bit: bit to read or write.
1341 */
1342#define DS1685_RTC_SYSFS_CTRL_REG_RW(bit) \
1343 static DEVICE_ATTR(bit, S_IRUGO | S_IWUSR, \
1344 ds1685_rtc_sysfs_ctrl_regs_show, \
1345 ds1685_rtc_sysfs_ctrl_regs_store)
1346
1347/*
1348 * Control Register A bits.
1349 */
1350DS1685_RTC_SYSFS_CTRL_REG_RO(uip);
1351DS1685_RTC_SYSFS_CTRL_REG_RW(dv2);
1352DS1685_RTC_SYSFS_CTRL_REG_RW(dv1);
1353DS1685_RTC_SYSFS_CTRL_REG_RO(dv0);
1354DS1685_RTC_SYSFS_CTRL_REG_RW(rs3);
1355DS1685_RTC_SYSFS_CTRL_REG_RW(rs2);
1356DS1685_RTC_SYSFS_CTRL_REG_RW(rs1);
1357DS1685_RTC_SYSFS_CTRL_REG_RW(rs0);
1358
1359static struct attribute*
1360ds1685_rtc_sysfs_ctrla_attrs[] = {
1361 &dev_attr_uip.attr,
1362 &dev_attr_dv2.attr,
1363 &dev_attr_dv1.attr,
1364 &dev_attr_dv0.attr,
1365 &dev_attr_rs3.attr,
1366 &dev_attr_rs2.attr,
1367 &dev_attr_rs1.attr,
1368 &dev_attr_rs0.attr,
1369 NULL,
1370};
1371
1372static const struct attribute_group
1373ds1685_rtc_sysfs_ctrla_grp = {
1374 .name = "ctrla",
1375 .attrs = ds1685_rtc_sysfs_ctrla_attrs,
1376};
1377
1378
1379/*
1380 * Control Register B bits.
1381 */
1382DS1685_RTC_SYSFS_CTRL_REG_RO(set);
1383DS1685_RTC_SYSFS_CTRL_REG_RW(pie);
1384DS1685_RTC_SYSFS_CTRL_REG_RW(aie);
1385DS1685_RTC_SYSFS_CTRL_REG_RW(uie);
1386DS1685_RTC_SYSFS_CTRL_REG_RW(sqwe);
1387DS1685_RTC_SYSFS_CTRL_REG_RO(dm);
1388DS1685_RTC_SYSFS_CTRL_REG_RO(2412);
1389DS1685_RTC_SYSFS_CTRL_REG_RO(dse);
1390
1391static struct attribute*
1392ds1685_rtc_sysfs_ctrlb_attrs[] = {
1393 &dev_attr_set.attr,
1394 &dev_attr_pie.attr,
1395 &dev_attr_aie.attr,
1396 &dev_attr_uie.attr,
1397 &dev_attr_sqwe.attr,
1398 &dev_attr_dm.attr,
1399 &dev_attr_2412.attr,
1400 &dev_attr_dse.attr,
1401 NULL,
1402};
1403
1404static const struct attribute_group
1405ds1685_rtc_sysfs_ctrlb_grp = {
1406 .name = "ctrlb",
1407 .attrs = ds1685_rtc_sysfs_ctrlb_attrs,
1408};
1409
1410/*
1411 * Control Register C bits.
1412 *
1413 * Reading Control C clears these bits! Reading them individually can
1414 * possibly cause an interrupt to be missed. Use the /proc interface
1415 * to see all the bits in this register simultaneously.
1416 */
1417DS1685_RTC_SYSFS_CTRL_REG_RO(irqf);
1418DS1685_RTC_SYSFS_CTRL_REG_RO(pf);
1419DS1685_RTC_SYSFS_CTRL_REG_RO(af);
1420DS1685_RTC_SYSFS_CTRL_REG_RO(uf);
1421
1422static struct attribute*
1423ds1685_rtc_sysfs_ctrlc_attrs[] = {
1424 &dev_attr_irqf.attr,
1425 &dev_attr_pf.attr,
1426 &dev_attr_af.attr,
1427 &dev_attr_uf.attr,
1428 NULL,
1429};
1430
1431static const struct attribute_group
1432ds1685_rtc_sysfs_ctrlc_grp = {
1433 .name = "ctrlc",
1434 .attrs = ds1685_rtc_sysfs_ctrlc_attrs,
1435};
1436
1437/*
1438 * Control Register D bits.
1439 */
1440DS1685_RTC_SYSFS_CTRL_REG_RO(vrt);
1441
1442static struct attribute*
1443ds1685_rtc_sysfs_ctrld_attrs[] = {
1444 &dev_attr_vrt.attr,
1445 NULL,
1446};
1447
1448static const struct attribute_group
1449ds1685_rtc_sysfs_ctrld_grp = {
1450 .name = "ctrld",
1451 .attrs = ds1685_rtc_sysfs_ctrld_attrs,
1452};
1453
1454/*
1455 * Control Register 4A bits.
1456 */
1457DS1685_RTC_SYSFS_CTRL_REG_RO(vrt2);
1458DS1685_RTC_SYSFS_CTRL_REG_RO(incr);
1459DS1685_RTC_SYSFS_CTRL_REG_RW(pab);
1460DS1685_RTC_SYSFS_CTRL_REG_RW(rf);
1461DS1685_RTC_SYSFS_CTRL_REG_RW(wf);
1462DS1685_RTC_SYSFS_CTRL_REG_RW(kf);
1463#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
1464DS1685_RTC_SYSFS_CTRL_REG_RO(bme);
1465#endif
1466
1467static struct attribute*
1468ds1685_rtc_sysfs_ctrl4a_attrs[] = {
1469 &dev_attr_vrt2.attr,
1470 &dev_attr_incr.attr,
1471 &dev_attr_pab.attr,
1472 &dev_attr_rf.attr,
1473 &dev_attr_wf.attr,
1474 &dev_attr_kf.attr,
1475#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
1476 &dev_attr_bme.attr,
1477#endif
1478 NULL,
1479};
1480
1481static const struct attribute_group
1482ds1685_rtc_sysfs_ctrl4a_grp = {
1483 .name = "ctrl4a",
1484 .attrs = ds1685_rtc_sysfs_ctrl4a_attrs,
1485};
1486
1487/*
1488 * Control Register 4B bits.
1489 */
1490DS1685_RTC_SYSFS_CTRL_REG_RW(abe);
1491DS1685_RTC_SYSFS_CTRL_REG_RW(e32k);
1492DS1685_RTC_SYSFS_CTRL_REG_RO(cs);
1493DS1685_RTC_SYSFS_CTRL_REG_RW(rce);
1494DS1685_RTC_SYSFS_CTRL_REG_RW(prs);
1495DS1685_RTC_SYSFS_CTRL_REG_RW(rie);
1496DS1685_RTC_SYSFS_CTRL_REG_RW(wie);
1497DS1685_RTC_SYSFS_CTRL_REG_RW(kse);
1498
1499static struct attribute*
1500ds1685_rtc_sysfs_ctrl4b_attrs[] = {
1501 &dev_attr_abe.attr,
1502 &dev_attr_e32k.attr,
1503 &dev_attr_cs.attr,
1504 &dev_attr_rce.attr,
1505 &dev_attr_prs.attr,
1506 &dev_attr_rie.attr,
1507 &dev_attr_wie.attr,
1508 &dev_attr_kse.attr,
1509 NULL,
1510};
1511
1512static const struct attribute_group
1513ds1685_rtc_sysfs_ctrl4b_grp = {
1514 .name = "ctrl4b",
1515 .attrs = ds1685_rtc_sysfs_ctrl4b_attrs,
1516};
1517
1518
1519/**
1520 * struct ds1685_rtc_ctrl_regs.
1521 * @name: char pointer for the bit name.
1522 * @reg: control register the bit is in.
1523 * @bit: the bit's offset in the register.
1524 */
1525struct ds1685_rtc_time_regs {
1526 const char *name;
1527 const u8 reg;
1528 const u8 mask;
1529 const u8 min;
1530 const u8 max;
1531};
1532
1533/*
1534 * Time/Date register lookup tables.
1535 */
1536static const struct ds1685_rtc_time_regs
1537ds1685_time_regs_bcd_table[] = {
1538 { "seconds", RTC_SECS, RTC_SECS_BCD_MASK, 0, 59 },
1539 { "minutes", RTC_MINS, RTC_MINS_BCD_MASK, 0, 59 },
1540 { "hours", RTC_HRS, RTC_HRS_24_BCD_MASK, 0, 23 },
1541 { "wday", RTC_WDAY, RTC_WDAY_MASK, 1, 7 },
1542 { "mday", RTC_MDAY, RTC_MDAY_BCD_MASK, 1, 31 },
1543 { "month", RTC_MONTH, RTC_MONTH_BCD_MASK, 1, 12 },
1544 { "year", RTC_YEAR, RTC_YEAR_BCD_MASK, 0, 99 },
1545 { "century", RTC_CENTURY, RTC_CENTURY_MASK, 0, 99 },
1546 { "alarm_seconds", RTC_SECS_ALARM, RTC_SECS_BCD_MASK, 0, 59 },
1547 { "alarm_minutes", RTC_MINS_ALARM, RTC_MINS_BCD_MASK, 0, 59 },
1548 { "alarm_hours", RTC_HRS_ALARM, RTC_HRS_24_BCD_MASK, 0, 23 },
1549 { "alarm_mday", RTC_MDAY_ALARM, RTC_MDAY_ALARM_MASK, 1, 31 },
1550 { NULL, 0, 0, 0, 0 },
1551};
1552
1553static const struct ds1685_rtc_time_regs
1554ds1685_time_regs_bin_table[] = {
1555 { "seconds", RTC_SECS, RTC_SECS_BIN_MASK, 0x00, 0x3b },
1556 { "minutes", RTC_MINS, RTC_MINS_BIN_MASK, 0x00, 0x3b },
1557 { "hours", RTC_HRS, RTC_HRS_24_BIN_MASK, 0x00, 0x17 },
1558 { "wday", RTC_WDAY, RTC_WDAY_MASK, 0x01, 0x07 },
1559 { "mday", RTC_MDAY, RTC_MDAY_BIN_MASK, 0x01, 0x1f },
1560 { "month", RTC_MONTH, RTC_MONTH_BIN_MASK, 0x01, 0x0c },
1561 { "year", RTC_YEAR, RTC_YEAR_BIN_MASK, 0x00, 0x63 },
1562 { "century", RTC_CENTURY, RTC_CENTURY_MASK, 0x00, 0x63 },
1563 { "alarm_seconds", RTC_SECS_ALARM, RTC_SECS_BIN_MASK, 0x00, 0x3b },
1564 { "alarm_minutes", RTC_MINS_ALARM, RTC_MINS_BIN_MASK, 0x00, 0x3b },
1565 { "alarm_hours", RTC_HRS_ALARM, RTC_HRS_24_BIN_MASK, 0x00, 0x17 },
1566 { "alarm_mday", RTC_MDAY_ALARM, RTC_MDAY_ALARM_MASK, 0x01, 0x1f },
1567 { NULL, 0, 0, 0x00, 0x00 },
1568};
1569
1570/**
1571 * ds1685_rtc_sysfs_time_regs_bcd_lookup - time/date reg bit lookup function.
1572 * @name: register bit to look up in ds1685_time_regs_bcd_table.
1573 */
1574static const struct ds1685_rtc_time_regs*
1575ds1685_rtc_sysfs_time_regs_lookup(const char *name, bool bcd_mode)
1576{
1577 const struct ds1685_rtc_time_regs *p;
1578
1579 if (bcd_mode)
1580 p = ds1685_time_regs_bcd_table;
1581 else
1582 p = ds1685_time_regs_bin_table;
1583
1584 for (; p->name != NULL; ++p)
1585 if (strcmp(p->name, name) == 0)
1586 return p;
1587
1588 return NULL;
1589}
1590
1591/**
1592 * ds1685_rtc_sysfs_time_regs_show - reads a time/date register via sysfs.
1593 * @dev: pointer to device structure.
1594 * @attr: pointer to device_attribute structure.
1595 * @buf: pointer to char array to hold the output.
1596 */
1597static ssize_t
1598ds1685_rtc_sysfs_time_regs_show(struct device *dev,
1599 struct device_attribute *attr, char *buf)
1600{
1601 u8 tmp;
1602 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1603 const struct ds1685_rtc_time_regs *bcd_reg_info =
1604 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, true);
1605 const struct ds1685_rtc_time_regs *bin_reg_info =
1606 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false);
1607
1608 /* Make sure we actually matched something. */
b00eeaed 1609 if (!bcd_reg_info || !bin_reg_info)
aaaf5fbf
JK		 1610 return -EINVAL;
1611
1612 /* bcd_reg_info->reg == bin_reg_info->reg. */
1613 ds1685_rtc_begin_data_access(rtc);
1614 tmp = rtc->read(rtc, bcd_reg_info->reg);
1615 ds1685_rtc_end_data_access(rtc);
1616
1617 tmp = ds1685_rtc_bcd2bin(rtc, tmp, bcd_reg_info->mask,
1618 bin_reg_info->mask);
1619
9c25a106 1620 return sprintf(buf, "%d\n", tmp);
aaaf5fbf
JK		 1621}
1622
1623/**
1624 * ds1685_rtc_sysfs_time_regs_store - writes a time/date register via sysfs.
1625 * @dev: pointer to device structure.
1626 * @attr: pointer to device_attribute structure.
1627 * @buf: pointer to char array to hold the output.
1628 * @count: number of bytes written.
1629 */
1630static ssize_t
1631ds1685_rtc_sysfs_time_regs_store(struct device *dev,
1632 struct device_attribute *attr,
1633 const char *buf, size_t count)
1634{
1635 long int val = 0;
1636 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1637 const struct ds1685_rtc_time_regs *bcd_reg_info =
1638 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, true);
1639 const struct ds1685_rtc_time_regs *bin_reg_info =
1640 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false);
1641
1642 /* We only accept numbers. */
1643 if (kstrtol(buf, 10, &val) < 0)
1644 return -EINVAL;
1645
1646 /* Make sure we actually matched something. */
b00eeaed 1647 if (!bcd_reg_info || !bin_reg_info)
aaaf5fbf
JK		 1648 return -EINVAL;
1649
1650 /* Check for a valid range. */
1651 if (rtc->bcd_mode) {
1652 if ((val < bcd_reg_info->min) || (val > bcd_reg_info->max))
1653 return -ERANGE;
1654 } else {
1655 if ((val < bin_reg_info->min) || (val > bin_reg_info->max))
1656 return -ERANGE;
1657 }
1658
1659 val = ds1685_rtc_bin2bcd(rtc, val, bin_reg_info->mask,
1660 bcd_reg_info->mask);
1661
1662 /* bcd_reg_info->reg == bin_reg_info->reg. */
1663 ds1685_rtc_begin_data_access(rtc);
1664 rtc->write(rtc, bcd_reg_info->reg, val);
1665 ds1685_rtc_end_data_access(rtc);
1666
1667 return count;
1668}
1669
1670/**
1671 * DS1685_RTC_SYSFS_REG_RW - device_attribute for a read-write time register.
1672 * @reg: time/date register to read or write.
1673 */
1674#define DS1685_RTC_SYSFS_TIME_REG_RW(reg) \
1675 static DEVICE_ATTR(reg, S_IRUGO | S_IWUSR, \
1676 ds1685_rtc_sysfs_time_regs_show, \
1677 ds1685_rtc_sysfs_time_regs_store)
1678
1679/*
1680 * Time/Date Register bits.
1681 */
1682DS1685_RTC_SYSFS_TIME_REG_RW(seconds);
1683DS1685_RTC_SYSFS_TIME_REG_RW(minutes);
1684DS1685_RTC_SYSFS_TIME_REG_RW(hours);
1685DS1685_RTC_SYSFS_TIME_REG_RW(wday);
1686DS1685_RTC_SYSFS_TIME_REG_RW(mday);
1687DS1685_RTC_SYSFS_TIME_REG_RW(month);
1688DS1685_RTC_SYSFS_TIME_REG_RW(year);
1689DS1685_RTC_SYSFS_TIME_REG_RW(century);
1690DS1685_RTC_SYSFS_TIME_REG_RW(alarm_seconds);
1691DS1685_RTC_SYSFS_TIME_REG_RW(alarm_minutes);
1692DS1685_RTC_SYSFS_TIME_REG_RW(alarm_hours);
1693DS1685_RTC_SYSFS_TIME_REG_RW(alarm_mday);
1694
1695static struct attribute*
1696ds1685_rtc_sysfs_time_attrs[] = {
1697 &dev_attr_seconds.attr,
1698 &dev_attr_minutes.attr,
1699 &dev_attr_hours.attr,
1700 &dev_attr_wday.attr,
1701 &dev_attr_mday.attr,
1702 &dev_attr_month.attr,
1703 &dev_attr_year.attr,
1704 &dev_attr_century.attr,
1705 NULL,
1706};
1707
1708static const struct attribute_group
1709ds1685_rtc_sysfs_time_grp = {
1710 .name = "datetime",
1711 .attrs = ds1685_rtc_sysfs_time_attrs,
1712};
1713
1714static struct attribute*
1715ds1685_rtc_sysfs_alarm_attrs[] = {
1716 &dev_attr_alarm_seconds.attr,
1717 &dev_attr_alarm_minutes.attr,
1718 &dev_attr_alarm_hours.attr,
1719 &dev_attr_alarm_mday.attr,
1720 NULL,
1721};
1722
1723static const struct attribute_group
1724ds1685_rtc_sysfs_alarm_grp = {
1725 .name = "alarm",
1726 .attrs = ds1685_rtc_sysfs_alarm_attrs,
1727};
1728#endif /* CONFIG_RTC_DS1685_SYSFS_REGS */
1729
1730
1731/**
1732 * ds1685_rtc_sysfs_register - register sysfs files.
1733 * @dev: pointer to device structure.
1734 */
1735static int
1736ds1685_rtc_sysfs_register(struct device *dev)
1737{
1738 int ret = 0;
1739
1740 sysfs_bin_attr_init(&ds1685_rtc_sysfs_nvram_attr);
1741 ret = sysfs_create_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr);
1742 if (ret)
1743 return ret;
1744
1745 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp);
1746 if (ret)
1747 return ret;
1748
1749#ifdef CONFIG_RTC_DS1685_SYSFS_REGS
1750 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp);
1751 if (ret)
1752 return ret;
1753
1754 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp);
1755 if (ret)
1756 return ret;
1757
1758 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp);
1759 if (ret)
1760 return ret;
1761
1762 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp);
1763 if (ret)
1764 return ret;
1765
1766 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp);
1767 if (ret)
1768 return ret;
1769
1770 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp);
1771 if (ret)
1772 return ret;
1773
1774 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_time_grp);
1775 if (ret)
1776 return ret;
1777
1778 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_alarm_grp);
1779 if (ret)
1780 return ret;
1781#endif
1782 return 0;
1783}
1784
1785/**
1786 * ds1685_rtc_sysfs_unregister - unregister sysfs files.
1787 * @dev: pointer to device structure.
1788 */
1789static int
1790ds1685_rtc_sysfs_unregister(struct device *dev)
1791{
1792 sysfs_remove_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr);
1793 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp);
1794
1795#ifdef CONFIG_RTC_DS1685_SYSFS_REGS
1796 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp);
1797 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp);
1798 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp);
1799 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp);
1800 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp);
1801 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp);
1802 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_time_grp);
1803 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_alarm_grp);
1804#endif
1805
1806 return 0;
1807}
1808#endif /* CONFIG_SYSFS */
1809
1810
1811
1812/* ----------------------------------------------------------------------- */
1813/* Driver Probe/Removal */
1814
1815/**
1816 * ds1685_rtc_probe - initializes rtc driver.
1817 * @pdev: pointer to platform_device structure.
1818 */
1819static int
1820ds1685_rtc_probe(struct platform_device *pdev)
1821{
1822 struct rtc_device *rtc_dev;
1823 struct resource *res;
1824 struct ds1685_priv *rtc;
1825 struct ds1685_rtc_platform_data *pdata;
1826 u8 ctrla, ctrlb, hours;
1827 unsigned char am_pm;
1828 int ret = 0;
1829
1830 /* Get the platform data. */
1831 pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
1832 if (!pdata)
1833 return -ENODEV;
1834
1835 /* Allocate memory for the rtc device. */
1836 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
1837 if (!rtc)
1838 return -ENOMEM;
1839
1840 /*
1841 * Allocate/setup any IORESOURCE_MEM resources, if required. Not all
1842 * platforms put the RTC in an easy-access place. Like the SGI Octane,
1843 * which attaches the RTC to a "ByteBus", hooked to a SuperIO chip
1844 * that sits behind the IOC3 PCI metadevice.
1845 */
1846 if (pdata->alloc_io_resources) {
1847 /* Get the platform resources. */
1848 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1849 if (!res)
1850 return -ENXIO;
1851 rtc->size = resource_size(res);
1852
1853 /* Request a memory region. */
1854 /* XXX: mmio-only for now. */
1855 if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size,
1856 pdev->name))
1857 return -EBUSY;
1858
1859 /*
1860 * Set the base address for the rtc, and ioremap its
1861 * registers.
1862 */
1863 rtc->baseaddr = res->start;
1864 rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size);
1865 if (!rtc->regs)
1866 return -ENOMEM;
1867 }
1868 rtc->alloc_io_resources = pdata->alloc_io_resources;
1869
1870 /* Get the register step size. */
1871 if (pdata->regstep > 0)
1872 rtc->regstep = pdata->regstep;
1873 else
1874 rtc->regstep = 1;
1875
1876 /* Platform read function, else default if mmio setup */
1877 if (pdata->plat_read)
1878 rtc->read = pdata->plat_read;
1879 else
1880 if (pdata->alloc_io_resources)
1881 rtc->read = ds1685_read;
1882 else
1883 return -ENXIO;
1884
1885 /* Platform write function, else default if mmio setup */
1886 if (pdata->plat_write)
1887 rtc->write = pdata->plat_write;
1888 else
1889 if (pdata->alloc_io_resources)
1890 rtc->write = ds1685_write;
1891 else
1892 return -ENXIO;
1893
1894 /* Platform pre-shutdown function, if defined. */
1895 if (pdata->plat_prepare_poweroff)
1896 rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
1897
1898 /* Platform wake_alarm function, if defined. */
1899 if (pdata->plat_wake_alarm)
1900 rtc->wake_alarm = pdata->plat_wake_alarm;
1901
1902 /* Platform post_ram_clear function, if defined. */
1903 if (pdata->plat_post_ram_clear)
1904 rtc->post_ram_clear = pdata->plat_post_ram_clear;
1905
1906 /* Init the spinlock, workqueue, & set the driver data. */
1907 spin_lock_init(&rtc->lock);
1908 INIT_WORK(&rtc->work, ds1685_rtc_work_queue);
1909 platform_set_drvdata(pdev, rtc);
1910
1911 /* Turn the oscillator on if is not already on (DV1 = 1). */
1912 ctrla = rtc->read(rtc, RTC_CTRL_A);
1913 if (!(ctrla & RTC_CTRL_A_DV1))
1914 ctrla |= RTC_CTRL_A_DV1;
1915
1916 /* Enable the countdown chain (DV2 = 0) */
1917 ctrla &= ~(RTC_CTRL_A_DV2);
1918
1919 /* Clear RS3-RS0 in Control A. */
1920 ctrla &= ~(RTC_CTRL_A_RS_MASK);
1921
1922 /*
1923 * All done with Control A. Switch to Bank 1 for the remainder of
1924 * the RTC setup so we have access to the extended functions.
1925 */
1926 ctrla |= RTC_CTRL_A_DV0;
1927 rtc->write(rtc, RTC_CTRL_A, ctrla);
1928
1929 /* Default to 32768kHz output. */
1930 rtc->write(rtc, RTC_EXT_CTRL_4B,
1931 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
1932
1933 /* Set the SET bit in Control B so we can do some housekeeping. */
1934 rtc->write(rtc, RTC_CTRL_B,
1935 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
1936
1937 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
1938 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
1939 cpu_relax();
1940
1941 /*
1942 * If the platform supports BCD mode, then set DM=0 in Control B.
1943 * Otherwise, set DM=1 for BIN mode.
1944 */
1945 ctrlb = rtc->read(rtc, RTC_CTRL_B);
1946 if (pdata->bcd_mode)
1947 ctrlb &= ~(RTC_CTRL_B_DM);
1948 else
1949 ctrlb |= RTC_CTRL_B_DM;
1950 rtc->bcd_mode = pdata->bcd_mode;
1951
1952 /*
1953 * Disable Daylight Savings Time (DSE = 0).
1954 * The RTC has hardcoded timezone information that is rendered
1955 * obselete. We'll let the OS deal with DST settings instead.
1956 */
1957 if (ctrlb & RTC_CTRL_B_DSE)
1958 ctrlb &= ~(RTC_CTRL_B_DSE);
1959
1960 /* Force 24-hour mode (2412 = 1). */
1961 if (!(ctrlb & RTC_CTRL_B_2412)) {
1962 /* Reinitialize the time hours. */
1963 hours = rtc->read(rtc, RTC_HRS);
1964 am_pm = hours & RTC_HRS_AMPM_MASK;
1965 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1966 RTC_HRS_12_BIN_MASK);
1967 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1968
1969 /* Enable 24-hour mode. */
1970 ctrlb |= RTC_CTRL_B_2412;
1971
1972 /* Write back to Control B, including DM & DSE bits. */
1973 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1974
1975 /* Write the time hours back. */
1976 rtc->write(rtc, RTC_HRS,
1977 ds1685_rtc_bin2bcd(rtc, hours,
1978 RTC_HRS_24_BIN_MASK,
1979 RTC_HRS_24_BCD_MASK));
1980
1981 /* Reinitialize the alarm hours. */
1982 hours = rtc->read(rtc, RTC_HRS_ALARM);
1983 am_pm = hours & RTC_HRS_AMPM_MASK;
1984 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1985 RTC_HRS_12_BIN_MASK);
1986 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1987
1988 /* Write the alarm hours back. */
1989 rtc->write(rtc, RTC_HRS_ALARM,
1990 ds1685_rtc_bin2bcd(rtc, hours,
1991 RTC_HRS_24_BIN_MASK,
1992 RTC_HRS_24_BCD_MASK));
1993 } else {
1994 /* 24-hour mode is already set, so write Control B back. */
1995 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1996 }
1997
1998 /* Unset the SET bit in Control B so the RTC can update. */
1999 rtc->write(rtc, RTC_CTRL_B,
2000 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
2001
2002 /* Check the main battery. */
2003 if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
2004 dev_warn(&pdev->dev,
2005 "Main battery is exhausted! RTC may be invalid!\n");
2006
2007 /* Check the auxillary battery. It is optional. */
2008 if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
2009 dev_warn(&pdev->dev,
2010 "Aux battery is exhausted or not available.\n");
2011
2012 /* Read Ctrl B and clear PIE/AIE/UIE. */
2013 rtc->write(rtc, RTC_CTRL_B,
2014 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
2015
2016 /* Reading Ctrl C auto-clears PF/AF/UF. */
2017 rtc->read(rtc, RTC_CTRL_C);
2018
2019 /* Read Ctrl 4B and clear RIE/WIE/KSE. */
2020 rtc->write(rtc, RTC_EXT_CTRL_4B,
2021 (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
2022
2023 /* Clear RF/WF/KF in Ctrl 4A. */
2024 rtc->write(rtc, RTC_EXT_CTRL_4A,
2025 (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
2026
2027 /*
2028 * Re-enable KSE to handle power button events. We do not enable
2029 * WIE or RIE by default.
2030 */
2031 rtc->write(rtc, RTC_EXT_CTRL_4B,
2032 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
2033
2034 /*
2035 * Fetch the IRQ and setup the interrupt handler.
2036 *
2037 * Not all platforms have the IRQF pin tied to something. If not, the
2038 * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
2039 * there won't be an automatic way of notifying the kernel about it,
2040 * unless ctrlc is explicitly polled.
2041 */
2042 if (!pdata->no_irq) {
2043 ret = platform_get_irq(pdev, 0);
2044 if (ret > 0) {
2045 rtc->irq_num = ret;
2046
2047 /* Request an IRQ. */
2048 ret = devm_request_irq(&pdev->dev, rtc->irq_num,
2049 ds1685_rtc_irq_handler,
2050 IRQF_SHARED, pdev->name, pdev);
2051
2052 /* Check to see if something came back. */
2053 if (unlikely(ret)) {
2054 dev_warn(&pdev->dev,
2055 "RTC interrupt not available\n");
2056 rtc->irq_num = 0;
2057 }
2058 } else
2059 return ret;
2060 }
2061 rtc->no_irq = pdata->no_irq;
2062
2063 /* Setup complete. */
2064 ds1685_rtc_switch_to_bank0(rtc);
2065
2066 /* Register the device as an RTC. */
2067 rtc_dev = rtc_device_register(pdev->name, &pdev->dev,
2068 &ds1685_rtc_ops, THIS_MODULE);
2069
2070 /* Success? */
2071 if (IS_ERR(rtc_dev))
2072 return PTR_ERR(rtc_dev);
2073
2074 /* Maximum periodic rate is 8192Hz (0.122070ms). */
2075 rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
2076
2077 /* See if the platform doesn't support UIE. */
2078 if (pdata->uie_unsupported)
2079 rtc_dev->uie_unsupported = 1;
2080 rtc->uie_unsupported = pdata->uie_unsupported;
2081
2082 rtc->dev = rtc_dev;
2083
2084#ifdef CONFIG_SYSFS
2085 ret = ds1685_rtc_sysfs_register(&pdev->dev);
2086 if (ret)
2087 rtc_device_unregister(rtc->dev);
2088#endif
2089
2090 /* Done! */
2091 return ret;
2092}
2093
2094/**
2095 * ds1685_rtc_remove - removes rtc driver.
2096 * @pdev: pointer to platform_device structure.
2097 */
2098static int
2099ds1685_rtc_remove(struct platform_device *pdev)
2100{
2101 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
2102
2103#ifdef CONFIG_SYSFS
2104 ds1685_rtc_sysfs_unregister(&pdev->dev);
2105#endif
2106
2107 rtc_device_unregister(rtc->dev);
2108
2109 /* Read Ctrl B and clear PIE/AIE/UIE. */
2110 rtc->write(rtc, RTC_CTRL_B,
2111 (rtc->read(rtc, RTC_CTRL_B) &
2112 ~(RTC_CTRL_B_PAU_MASK)));
2113
2114 /* Reading Ctrl C auto-clears PF/AF/UF. */
2115 rtc->read(rtc, RTC_CTRL_C);
2116
2117 /* Read Ctrl 4B and clear RIE/WIE/KSE. */
2118 rtc->write(rtc, RTC_EXT_CTRL_4B,
2119 (rtc->read(rtc, RTC_EXT_CTRL_4B) &
2120 ~(RTC_CTRL_4B_RWK_MASK)));
2121
2122 /* Manually clear RF/WF/KF in Ctrl 4A. */
2123 rtc->write(rtc, RTC_EXT_CTRL_4A,
2124 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
2125 ~(RTC_CTRL_4A_RWK_MASK)));
2126
2127 cancel_work_sync(&rtc->work);
2128
2129 return 0;
2130}
2131
2132/**
2133 * ds1685_rtc_driver - rtc driver properties.
2134 */
2135static struct platform_driver ds1685_rtc_driver = {
2136 .driver = {
2137 .name = "rtc-ds1685",
aaaf5fbf
JK		 2138 },
2139 .probe = ds1685_rtc_probe,
2140 .remove = ds1685_rtc_remove,
2141};
508db592 2142module_platform_driver(ds1685_rtc_driver);
aaaf5fbf
JK		 2143/* ----------------------------------------------------------------------- */
2144
2145
2146/* ----------------------------------------------------------------------- */
2147/* Poweroff function */
2148
2149/**
2150 * ds1685_rtc_poweroff - uses the RTC chip to power the system off.
2151 * @pdev: pointer to platform_device structure.
2152 */
52ef84d5 2153void __noreturn
aaaf5fbf
JK		 2154ds1685_rtc_poweroff(struct platform_device *pdev)
2155{
2156 u8 ctrla, ctrl4a, ctrl4b;
2157 struct ds1685_priv *rtc;
2158
2159 /* Check for valid RTC data, else, spin forever. */
2160 if (unlikely(!pdev)) {
a737e835 2161 pr_emerg("platform device data not available, spinning forever ...\n");
361c6ed6 2162 while(1);
aaaf5fbf
JK		 2163 unreachable();
2164 } else {
2165 /* Get the rtc data. */
2166 rtc = platform_get_drvdata(pdev);
2167
2168 /*
2169 * Disable our IRQ. We're powering down, so we're not
2170 * going to worry about cleaning up. Most of that should
2171 * have been taken care of by the shutdown scripts and this
2172 * is the final function call.
2173 */
2174 if (!rtc->no_irq)
2175 disable_irq_nosync(rtc->irq_num);
2176
2177 /* Oscillator must be on and the countdown chain enabled. */
2178 ctrla = rtc->read(rtc, RTC_CTRL_A);
2179 ctrla |= RTC_CTRL_A_DV1;
2180 ctrla &= ~(RTC_CTRL_A_DV2);
2181 rtc->write(rtc, RTC_CTRL_A, ctrla);
2182
2183 /*
2184 * Read Control 4A and check the status of the auxillary
2185 * battery. This must be present and working (VRT2 = 1)
2186 * for wakeup and kickstart functionality to be useful.
2187 */
2188 ds1685_rtc_switch_to_bank1(rtc);
2189 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
2190 if (ctrl4a & RTC_CTRL_4A_VRT2) {
2191 /* Clear all of the interrupt flags on Control 4A. */
2192 ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
2193 rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
2194
2195 /*
2196 * The auxillary battery is present and working.
2197 * Enable extended functions (ABE=1), enable
2198 * wake-up (WIE=1), and enable kickstart (KSE=1)
2199 * in Control 4B.
2200 */
2201 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
2202 ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
2203 RTC_CTRL_4B_KSE);
2204 rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
2205 }
2206
2207 /* Set PAB to 1 in Control 4A to power the system down. */
2208 dev_warn(&pdev->dev, "Powerdown.\n");
2209 msleep(20);
2210 rtc->write(rtc, RTC_EXT_CTRL_4A,
2211 (ctrl4a | RTC_CTRL_4A_PAB));
2212
2213 /* Spin ... we do not switch back to bank0. */
19105f42 2214 while(1);
aaaf5fbf
JK		 2215 unreachable();
2216 }
2217}
2218EXPORT_SYMBOL(ds1685_rtc_poweroff);
2219/* ----------------------------------------------------------------------- */
2220
2221
2222MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>");
2223MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>");
2224MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
2225MODULE_LICENSE("GPL");
aaaf5fbf 2226MODULE_ALIAS("platform:rtc-ds1685");
Linux 6.x block layer and io_uring tree(s)