[linux-2.6-block.git] / drivers / reset / reset-socfpga.c

/*
 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
 *
 * based on
 * Allwinner SoCs Reset Controller driver
 *
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#define NR_BANKS		4

struct socfpga_reset_data {
	spinlock_t			lock;
	void __iomem			*membase;
	struct reset_controller_dev	rcdev;
};

static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
				unsigned long id)
{
	struct socfpga_reset_data *data = container_of(rcdev,
						     struct socfpga_reset_data,
						     rcdev);
	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&data->lock, flags);

	reg = readl(data->membase + (bank * NR_BANKS));
	writel(reg | BIT(offset), data->membase + (bank * NR_BANKS));
	spin_unlock_irqrestore(&data->lock, flags);

	return 0;
}

static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
				  unsigned long id)
{
	struct socfpga_reset_data *data = container_of(rcdev,
						     struct socfpga_reset_data,
						     rcdev);

	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&data->lock, flags);

	reg = readl(data->membase + (bank * NR_BANKS));
	writel(reg & ~BIT(offset), data->membase + (bank * NR_BANKS));

	spin_unlock_irqrestore(&data->lock, flags);

	return 0;
}

static int socfpga_reset_status(struct reset_controller_dev *rcdev,
				unsigned long id)
{
	struct socfpga_reset_data *data = container_of(rcdev,
						struct socfpga_reset_data, rcdev);
	int bank = id / BITS_PER_LONG;
	int offset = id % BITS_PER_LONG;
	u32 reg;

	reg = readl(data->membase + (bank * NR_BANKS));

	return !(reg & BIT(offset));
}

static const struct reset_control_ops socfpga_reset_ops = {
	.assert		= socfpga_reset_assert,
	.deassert	= socfpga_reset_deassert,
	.status		= socfpga_reset_status,
};

static int socfpga_reset_probe(struct platform_device *pdev)
{
	struct socfpga_reset_data *data;
	struct resource *res;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	u32 modrst_offset;

	/*
	 * The binding was mainlined without the required property.
	 * Do not continue, when we encounter an old DT.
	 */
	if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
		dev_err(&pdev->dev, "%s missing #reset-cells property\n",
			pdev->dev.of_node->full_name);
		return -EINVAL;
	}

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->membase = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(data->membase))
		return PTR_ERR(data->membase);

	if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
		dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
		modrst_offset = 0x10;
	}
	data->membase += modrst_offset;

	spin_lock_init(&data->lock);

	data->rcdev.owner = THIS_MODULE;
	data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
	data->rcdev.ops = &socfpga_reset_ops;
	data->rcdev.of_node = pdev->dev.of_node;

	return devm_reset_controller_register(dev, &data->rcdev);
}

static const struct of_device_id socfpga_reset_dt_ids[] = {
	{ .compatible = "altr,rst-mgr", },
	{ /* sentinel */ },
};

static struct platform_driver socfpga_reset_driver = {
	.probe	= socfpga_reset_probe,
	.driver = {
		.name		= "socfpga-reset",
		.of_match_table	= socfpga_reset_dt_ids,
	},
};
module_platform_driver(socfpga_reset_driver);

MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de");
MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
a39a4939 ST	1	/*
	2	* Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
	3	*
	4	* based on
	5	* Allwinner SoCs Reset Controller driver
	6	*
	7	* Copyright 2013 Maxime Ripard
	8	*
	9	* Maxime Ripard <maxime.ripard@free-electrons.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#include <linux/err.h>
	18	#include <linux/io.h>
	19	#include <linux/module.h>
	20	#include <linux/of.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/reset-controller.h>
	23	#include <linux/spinlock.h>
	24	#include <linux/types.h>
	25
	26	#define NR_BANKS 4
a39a4939 ST	27
	28	struct socfpga_reset_data {
	29	spinlock_t lock;
	30	void __iomem *membase;
	31	struct reset_controller_dev rcdev;
	32	};
	33
	34	static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
	35	unsigned long id)
	36	{
	37	struct socfpga_reset_data *data = container_of(rcdev,
	38	struct socfpga_reset_data,
	39	rcdev);
	40	int bank = id / BITS_PER_LONG;
	41	int offset = id % BITS_PER_LONG;
	42	unsigned long flags;
	43	u32 reg;
	44
	45	spin_lock_irqsave(&data->lock, flags);
	46
6b37d3e9 PZ	47	reg = readl(data->membase + (bank * NR_BANKS));
6b37d3e9 PZ	48	writel(reg \| BIT(offset), data->membase + (bank * NR_BANKS));
a39a4939 ST	49	spin_unlock_irqrestore(&data->lock, flags);
	50
	51	return 0;
	52	}
	53
	54	static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
	55	unsigned long id)
	56	{
	57	struct socfpga_reset_data *data = container_of(rcdev,
	58	struct socfpga_reset_data,
	59	rcdev);
	60
	61	int bank = id / BITS_PER_LONG;
	62	int offset = id % BITS_PER_LONG;
	63	unsigned long flags;
	64	u32 reg;
	65
	66	spin_lock_irqsave(&data->lock, flags);
	67
6b37d3e9 PZ	68	reg = readl(data->membase + (bank * NR_BANKS));
6b37d3e9 PZ	69	writel(reg & ~BIT(offset), data->membase + (bank * NR_BANKS));
a39a4939 ST	70
	71	spin_unlock_irqrestore(&data->lock, flags);
	72
	73	return 0;
	74	}
	75
f200890f DN	76	static int socfpga_reset_status(struct reset_controller_dev *rcdev,
	77	unsigned long id)
	78	{
	79	struct socfpga_reset_data *data = container_of(rcdev,
	80	struct socfpga_reset_data, rcdev);
	81	int bank = id / BITS_PER_LONG;
	82	int offset = id % BITS_PER_LONG;
	83	u32 reg;
	84
6b37d3e9	85	reg = readl(data->membase + (bank * NR_BANKS));
f200890f DN	86
	87	return !(reg & BIT(offset));
	88	}
	89
387eb3f3	90	static const struct reset_control_ops socfpga_reset_ops = {
a39a4939 ST	91	.assert = socfpga_reset_assert,
a39a4939 ST	92	.deassert = socfpga_reset_deassert,
f200890f	93	.status = socfpga_reset_status,
a39a4939 ST	94	};
	95
	96	static int socfpga_reset_probe(struct platform_device *pdev)
	97	{
	98	struct socfpga_reset_data *data;
	99	struct resource *res;
27e44646 DN	100	struct device *dev = &pdev->dev;
27e44646 DN	101	struct device_node *np = dev->of_node;
6b37d3e9	102	u32 modrst_offset;
a39a4939 ST	103
	104	/*
	105	* The binding was mainlined without the required property.
	106	* Do not continue, when we encounter an old DT.
	107	*/
	108	if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
	109	dev_err(&pdev->dev, "%s missing #reset-cells property\n",
	110	pdev->dev.of_node->full_name);
	111	return -EINVAL;
	112	}
	113
	114	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	115	if (!data)
	116	return -ENOMEM;
	117
	118	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	119	data->membase = devm_ioremap_resource(&pdev->dev, res);
	120	if (IS_ERR(data->membase))
	121	return PTR_ERR(data->membase);
	122
6b37d3e9	123	if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
27e44646	124	dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
6b37d3e9	125	modrst_offset = 0x10;
27e44646	126	}
6b37d3e9	127	data->membase += modrst_offset;
27e44646	128
a39a4939 ST	129	spin_lock_init(&data->lock);
	130
	131	data->rcdev.owner = THIS_MODULE;
	132	data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
	133	data->rcdev.ops = &socfpga_reset_ops;
	134	data->rcdev.of_node = pdev->dev.of_node;
a39a4939	135
dc22e08e	136	return devm_reset_controller_register(dev, &data->rcdev);
a39a4939 ST	137	}
	138
	139	static const struct of_device_id socfpga_reset_dt_ids[] = {
	140	{ .compatible = "altr,rst-mgr", },
	141	{ /* sentinel */ },
	142	};
	143
	144	static struct platform_driver socfpga_reset_driver = {
	145	.probe = socfpga_reset_probe,
a39a4939 ST	146	.driver = {
a39a4939 ST	147	.name = "socfpga-reset",
a39a4939 ST	148	.of_match_table = socfpga_reset_dt_ids,
	149	},
	150	};
	151	module_platform_driver(socfpga_reset_driver);
	152
	153	MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de");
	154	MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
	155	MODULE_LICENSE("GPL");