projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
cw1200: drop useless LIST_HEAD
[linux-2.6-block.git] / drivers / regulator / s5m8767.c
CommitLineData
4f3fb287
KK		 1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (c) 2011 Samsung Electronics Co., Ltd
4// http://www.samsung.com
9767ec7f 5
9767ec7f 6#include <linux/err.h>
26aec009 7#include <linux/of_gpio.h>
9ae5cc75 8#include <linux/gpio/consumer.h>
9767ec7f
SK		 9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/regulator/driver.h>
12#include <linux/regulator/machine.h>
54227bcf
SK		 13#include <linux/mfd/samsung/core.h>
14#include <linux/mfd/samsung/s5m8767.h>
26aec009 15#include <linux/regulator/of_regulator.h>
d13733f4 16#include <linux/regmap.h>
26aec009
ADK		 17
18#define S5M8767_OPMODE_NORMAL_MODE 0x1
9767ec7f
SK		 19
20struct s5m8767_info {
21 struct device *dev;
63063bfb 22 struct sec_pmic_dev *iodev;
9767ec7f 23 int num_regulators;
63063bfb 24 struct sec_opmode_data *opmode;
9767ec7f
SK		 25
26 int ramp_delay;
27 bool buck2_ramp;
28 bool buck3_ramp;
29 bool buck4_ramp;
30
31 bool buck2_gpiodvs;
32 bool buck3_gpiodvs;
33 bool buck4_gpiodvs;
34 u8 buck2_vol[8];
35 u8 buck3_vol[8];
36 u8 buck4_vol[8];
37 int buck_gpios[3];
c848bc85 38 int buck_ds[3];
9767ec7f
SK		 39 int buck_gpioindex;
40};
41
63063bfb 42struct sec_voltage_desc {
9767ec7f
SK		 43 int max;
44 int min;
45 int step;
46};
47
63063bfb 48static const struct sec_voltage_desc buck_voltage_val1 = {
9767ec7f
SK		 49 .max = 2225000,
50 .min = 650000,
51 .step = 6250,
52};
53
63063bfb 54static const struct sec_voltage_desc buck_voltage_val2 = {
9767ec7f
SK		 55 .max = 1600000,
56 .min = 600000,
57 .step = 6250,
58};
59
63063bfb 60static const struct sec_voltage_desc buck_voltage_val3 = {
9767ec7f
SK		 61 .max = 3000000,
62 .min = 750000,
63 .step = 12500,
64};
65
63063bfb 66static const struct sec_voltage_desc ldo_voltage_val1 = {
9767ec7f
SK		 67 .max = 3950000,
68 .min = 800000,
69 .step = 50000,
70};
71
63063bfb 72static const struct sec_voltage_desc ldo_voltage_val2 = {
9767ec7f
SK		 73 .max = 2375000,
74 .min = 800000,
75 .step = 25000,
76};
77
63063bfb 78static const struct sec_voltage_desc *reg_voltage_map[] = {
9767ec7f
SK		 79 [S5M8767_LDO1] = &ldo_voltage_val2,
80 [S5M8767_LDO2] = &ldo_voltage_val2,
81 [S5M8767_LDO3] = &ldo_voltage_val1,
82 [S5M8767_LDO4] = &ldo_voltage_val1,
83 [S5M8767_LDO5] = &ldo_voltage_val1,
84 [S5M8767_LDO6] = &ldo_voltage_val2,
85 [S5M8767_LDO7] = &ldo_voltage_val2,
86 [S5M8767_LDO8] = &ldo_voltage_val2,
87 [S5M8767_LDO9] = &ldo_voltage_val1,
88 [S5M8767_LDO10] = &ldo_voltage_val1,
89 [S5M8767_LDO11] = &ldo_voltage_val1,
90 [S5M8767_LDO12] = &ldo_voltage_val1,
91 [S5M8767_LDO13] = &ldo_voltage_val1,
92 [S5M8767_LDO14] = &ldo_voltage_val1,
93 [S5M8767_LDO15] = &ldo_voltage_val2,
94 [S5M8767_LDO16] = &ldo_voltage_val1,
95 [S5M8767_LDO17] = &ldo_voltage_val1,
96 [S5M8767_LDO18] = &ldo_voltage_val1,
97 [S5M8767_LDO19] = &ldo_voltage_val1,
98 [S5M8767_LDO20] = &ldo_voltage_val1,
99 [S5M8767_LDO21] = &ldo_voltage_val1,
100 [S5M8767_LDO22] = &ldo_voltage_val1,
101 [S5M8767_LDO23] = &ldo_voltage_val1,
102 [S5M8767_LDO24] = &ldo_voltage_val1,
103 [S5M8767_LDO25] = &ldo_voltage_val1,
104 [S5M8767_LDO26] = &ldo_voltage_val1,
105 [S5M8767_LDO27] = &ldo_voltage_val1,
106 [S5M8767_LDO28] = &ldo_voltage_val1,
107 [S5M8767_BUCK1] = &buck_voltage_val1,
108 [S5M8767_BUCK2] = &buck_voltage_val2,
109 [S5M8767_BUCK3] = &buck_voltage_val2,
110 [S5M8767_BUCK4] = &buck_voltage_val2,
111 [S5M8767_BUCK5] = &buck_voltage_val1,
112 [S5M8767_BUCK6] = &buck_voltage_val1,
463616ea
KK		 113 [S5M8767_BUCK7] = &buck_voltage_val3,
114 [S5M8767_BUCK8] = &buck_voltage_val3,
9767ec7f
SK		 115 [S5M8767_BUCK9] = &buck_voltage_val3,
116};
117
5ceba7ba 118static unsigned int s5m8767_opmode_reg[][4] = {
7e44bb83
SK		 119 /* {OFF, ON, LOWPOWER, SUSPEND} */
120 /* LDO1 ... LDO28 */
121 {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
122 {0x0, 0x3, 0x2, 0x1},
123 {0x0, 0x3, 0x2, 0x1},
124 {0x0, 0x0, 0x0, 0x0},
125 {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
126 {0x0, 0x3, 0x2, 0x1},
127 {0x0, 0x3, 0x2, 0x1},
128 {0x0, 0x3, 0x2, 0x1},
129 {0x0, 0x3, 0x2, 0x1},
130 {0x0, 0x3, 0x2, 0x1}, /* LDO10 */
131 {0x0, 0x3, 0x2, 0x1},
132 {0x0, 0x3, 0x2, 0x1},
133 {0x0, 0x3, 0x2, 0x1},
134 {0x0, 0x3, 0x2, 0x1},
135 {0x0, 0x3, 0x2, 0x1}, /* LDO15 */
136 {0x0, 0x3, 0x2, 0x1},
137 {0x0, 0x3, 0x2, 0x1},
138 {0x0, 0x0, 0x0, 0x0},
139 {0x0, 0x3, 0x2, 0x1},
140 {0x0, 0x3, 0x2, 0x1}, /* LDO20 */
141 {0x0, 0x3, 0x2, 0x1},
142 {0x0, 0x3, 0x2, 0x1},
143 {0x0, 0x0, 0x0, 0x0},
144 {0x0, 0x3, 0x2, 0x1},
145 {0x0, 0x3, 0x2, 0x1}, /* LDO25 */
146 {0x0, 0x3, 0x2, 0x1},
147 {0x0, 0x3, 0x2, 0x1},
148 {0x0, 0x3, 0x2, 0x1}, /* LDO28 */
149
150 /* BUCK1 ... BUCK9 */
151 {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */
152 {0x0, 0x3, 0x1, 0x1},
153 {0x0, 0x3, 0x1, 0x1},
154 {0x0, 0x3, 0x1, 0x1},
155 {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */
156 {0x0, 0x3, 0x1, 0x1},
157 {0x0, 0x3, 0x1, 0x1},
158 {0x0, 0x3, 0x1, 0x1},
159 {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */
160};
161
9c4c6055
AL		 162static int s5m8767_get_register(struct s5m8767_info *s5m8767, int reg_id,
163 int *reg, int *enable_ctrl)
9767ec7f 164{
9c4c6055 165 int i;
7e44bb83 166 unsigned int mode;
9767ec7f
SK		 167
168 switch (reg_id) {
169 case S5M8767_LDO1 ... S5M8767_LDO2:
170 *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
171 break;
172 case S5M8767_LDO3 ... S5M8767_LDO28:
173 *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
174 break;
175 case S5M8767_BUCK1:
176 *reg = S5M8767_REG_BUCK1CTRL1;
177 break;
178 case S5M8767_BUCK2 ... S5M8767_BUCK4:
179 *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9;
180 break;
181 case S5M8767_BUCK5:
182 *reg = S5M8767_REG_BUCK5CTRL1;
183 break;
184 case S5M8767_BUCK6 ... S5M8767_BUCK9:
185 *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2;
186 break;
187 default:
188 return -EINVAL;
189 }
190
9bb096ff
ADK		 191 for (i = 0; i < s5m8767->num_regulators; i++) {
192 if (s5m8767->opmode[i].id == reg_id) {
193 mode = s5m8767->opmode[i].mode;
194 break;
195 }
196 }
197
e07ff943
AB		 198 if (i >= s5m8767->num_regulators)
199 return -EINVAL;
200
201 *enable_ctrl = s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT;
9bb096ff 202
9767ec7f
SK		 203 return 0;
204}
205
31a932e1 206static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767)
9767ec7f 207{
9767ec7f
SK		 208 int reg;
209
210 switch (reg_id) {
211 case S5M8767_LDO1 ... S5M8767_LDO2:
212 reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
213 break;
214 case S5M8767_LDO3 ... S5M8767_LDO28:
215 reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
216 break;
217 case S5M8767_BUCK1:
218 reg = S5M8767_REG_BUCK1CTRL2;
219 break;
220 case S5M8767_BUCK2:
da130ab2 221 reg = S5M8767_REG_BUCK2DVS1;
0a41685f
AL		 222 if (s5m8767->buck2_gpiodvs)
223 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 224 break;
225 case S5M8767_BUCK3:
da130ab2 226 reg = S5M8767_REG_BUCK3DVS1;
0a41685f
AL		 227 if (s5m8767->buck3_gpiodvs)
228 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 229 break;
230 case S5M8767_BUCK4:
da130ab2 231 reg = S5M8767_REG_BUCK4DVS1;
0a41685f
AL		 232 if (s5m8767->buck4_gpiodvs)
233 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 234 break;
235 case S5M8767_BUCK5:
236 reg = S5M8767_REG_BUCK5CTRL2;
237 break;
238 case S5M8767_BUCK6 ... S5M8767_BUCK9:
239 reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2;
240 break;
241 default:
242 return -EINVAL;
243 }
244
31a932e1 245 return reg;
9767ec7f
SK		 246}
247
854f73ec
AL		 248static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc,
249 int min_vol)
9767ec7f 250{
5b5e977c 251 int selector = 0;
9767ec7f
SK		 252
253 if (desc == NULL)
254 return -EINVAL;
255
854f73ec 256 if (min_vol > desc->max)
9767ec7f
SK		 257 return -EINVAL;
258
94e85a3c
AL		 259 if (min_vol < desc->min)
260 min_vol = desc->min;
261
262 selector = DIV_ROUND_UP(min_vol - desc->min, desc->step);
9767ec7f 263
854f73ec 264 if (desc->min + desc->step * selector > desc->max)
9767ec7f
SK		 265 return -EINVAL;
266
5b5e977c 267 return selector;
9767ec7f
SK		 268}
269
df2643cf 270static inline int s5m8767_set_high(struct s5m8767_info *s5m8767)
321d2aba
AL		 271{
272 int temp_index = s5m8767->buck_gpioindex;
273
274 gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
275 gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
276 gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
df2643cf
SK		 277
278 return 0;
321d2aba
AL		 279}
280
df2643cf 281static inline int s5m8767_set_low(struct s5m8767_info *s5m8767)
321d2aba
AL		 282{
283 int temp_index = s5m8767->buck_gpioindex;
284
285 gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
286 gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
287 gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
df2643cf
SK		 288
289 return 0;
321d2aba
AL		 290}
291
df2643cf
SK		 292static int s5m8767_set_voltage_sel(struct regulator_dev *rdev,
293 unsigned selector)
9767ec7f
SK		 294{
295 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
20a14b84 296 int reg_id = rdev_get_id(rdev);
31a932e1 297 int old_index, index = 0;
321d2aba 298 u8 *buck234_vol = NULL;
9767ec7f
SK		 299
300 switch (reg_id) {
301 case S5M8767_LDO1 ... S5M8767_LDO28:
9767ec7f
SK		 302 break;
303 case S5M8767_BUCK1 ... S5M8767_BUCK6:
321d2aba
AL		 304 if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs)
305 buck234_vol = &s5m8767->buck2_vol[0];
306 else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs)
307 buck234_vol = &s5m8767->buck3_vol[0];
308 else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs)
309 buck234_vol = &s5m8767->buck4_vol[0];
9767ec7f
SK		 310 break;
311 case S5M8767_BUCK7 ... S5M8767_BUCK8:
312 return -EINVAL;
313 case S5M8767_BUCK9:
9767ec7f
SK		 314 break;
315 default:
316 return -EINVAL;
317 }
318
321d2aba
AL		 319 /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */
320 if (buck234_vol) {
df2643cf 321 while (*buck234_vol != selector) {
321d2aba
AL		 322 buck234_vol++;
323 index++;
324 }
325 old_index = s5m8767->buck_gpioindex;
326 s5m8767->buck_gpioindex = index;
327
328 if (index > old_index)
df2643cf 329 return s5m8767_set_high(s5m8767);
321d2aba 330 else
df2643cf 331 return s5m8767_set_low(s5m8767);
321d2aba 332 } else {
31a932e1 333 return regulator_set_voltage_sel_regmap(rdev, selector);
321d2aba 334 }
9767ec7f
SK		 335}
336
9767ec7f
SK		 337static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev,
338 unsigned int old_sel,
339 unsigned int new_sel)
340{
341 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
63063bfb 342 const struct sec_voltage_desc *desc;
20a14b84 343 int reg_id = rdev_get_id(rdev);
9767ec7f 344
9767ec7f
SK		 345 desc = reg_voltage_map[reg_id];
346
9d88fc0b 347 if ((old_sel < new_sel) && s5m8767->ramp_delay)
89e0f0e4 348 return DIV_ROUND_UP(desc->step * (new_sel - old_sel),
0f8b9c77 349 s5m8767->ramp_delay * 1000);
89e0f0e4 350 return 0;
9767ec7f
SK		 351}
352
8a05eb19 353static const struct regulator_ops s5m8767_ops = {
e2eb169b 354 .list_voltage = regulator_list_voltage_linear,
9c4c6055
AL		 355 .is_enabled = regulator_is_enabled_regmap,
356 .enable = regulator_enable_regmap,
357 .disable = regulator_disable_regmap,
31a932e1 358 .get_voltage_sel = regulator_get_voltage_sel_regmap,
df2643cf 359 .set_voltage_sel = s5m8767_set_voltage_sel,
9767ec7f
SK		 360 .set_voltage_time_sel = s5m8767_set_voltage_time_sel,
361};
362
8a05eb19 363static const struct regulator_ops s5m8767_buck78_ops = {
463616ea 364 .list_voltage = regulator_list_voltage_linear,
9c4c6055
AL		 365 .is_enabled = regulator_is_enabled_regmap,
366 .enable = regulator_enable_regmap,
367 .disable = regulator_disable_regmap,
463616ea
KK		 368 .get_voltage_sel = regulator_get_voltage_sel_regmap,
369 .set_voltage_sel = regulator_set_voltage_sel_regmap,
e2eb169b
AL		 370};
371
65896e73
AL		 372#define s5m8767_regulator_desc(_name) { \
373 .name = #_name, \
374 .id = S5M8767_##_name, \
375 .ops = &s5m8767_ops, \
9767ec7f
SK		 376 .type = REGULATOR_VOLTAGE, \
377 .owner = THIS_MODULE, \
378}
379
e2eb169b
AL		 380#define s5m8767_regulator_buck78_desc(_name) { \
381 .name = #_name, \
382 .id = S5M8767_##_name, \
383 .ops = &s5m8767_buck78_ops, \
384 .type = REGULATOR_VOLTAGE, \
385 .owner = THIS_MODULE, \
386}
387
9767ec7f 388static struct regulator_desc regulators[] = {
65896e73
AL		 389 s5m8767_regulator_desc(LDO1),
390 s5m8767_regulator_desc(LDO2),
391 s5m8767_regulator_desc(LDO3),
392 s5m8767_regulator_desc(LDO4),
393 s5m8767_regulator_desc(LDO5),
394 s5m8767_regulator_desc(LDO6),
395 s5m8767_regulator_desc(LDO7),
396 s5m8767_regulator_desc(LDO8),
397 s5m8767_regulator_desc(LDO9),
398 s5m8767_regulator_desc(LDO10),
399 s5m8767_regulator_desc(LDO11),
400 s5m8767_regulator_desc(LDO12),
401 s5m8767_regulator_desc(LDO13),
402 s5m8767_regulator_desc(LDO14),
403 s5m8767_regulator_desc(LDO15),
404 s5m8767_regulator_desc(LDO16),
405 s5m8767_regulator_desc(LDO17),
406 s5m8767_regulator_desc(LDO18),
407 s5m8767_regulator_desc(LDO19),
408 s5m8767_regulator_desc(LDO20),
409 s5m8767_regulator_desc(LDO21),
410 s5m8767_regulator_desc(LDO22),
411 s5m8767_regulator_desc(LDO23),
412 s5m8767_regulator_desc(LDO24),
413 s5m8767_regulator_desc(LDO25),
414 s5m8767_regulator_desc(LDO26),
415 s5m8767_regulator_desc(LDO27),
416 s5m8767_regulator_desc(LDO28),
417 s5m8767_regulator_desc(BUCK1),
418 s5m8767_regulator_desc(BUCK2),
419 s5m8767_regulator_desc(BUCK3),
420 s5m8767_regulator_desc(BUCK4),
421 s5m8767_regulator_desc(BUCK5),
422 s5m8767_regulator_desc(BUCK6),
e2eb169b
AL		 423 s5m8767_regulator_buck78_desc(BUCK7),
424 s5m8767_regulator_buck78_desc(BUCK8),
65896e73 425 s5m8767_regulator_desc(BUCK9),
9767ec7f
SK		 426};
427
ee1e0994
KK		 428/*
429 * Enable GPIO control over BUCK9 in regulator_config for that regulator.
430 */
431static void s5m8767_regulator_config_ext_control(struct s5m8767_info *s5m8767,
432 struct sec_regulator_data *rdata,
433 struct regulator_config *config)
434{
435 int i, mode = 0;
436
437 if (rdata->id != S5M8767_BUCK9)
438 return;
439
440 /* Check if opmode for regulator matches S5M8767_ENCTRL_USE_GPIO */
441 for (i = 0; i < s5m8767->num_regulators; i++) {
442 const struct sec_opmode_data *opmode = &s5m8767->opmode[i];
443 if (opmode->id == rdata->id) {
444 mode = s5m8767_opmode_reg[rdata->id][opmode->mode];
445 break;
446 }
447 }
448 if (mode != S5M8767_ENCTRL_USE_GPIO) {
449 dev_warn(s5m8767->dev,
0c9721a5
RH		 450 "ext-control for %pOFn: mismatched op_mode (%x), ignoring\n",
451 rdata->reg_node, mode);
ee1e0994
KK		 452 return;
453 }
454
9ae5cc75 455 if (!rdata->ext_control_gpiod) {
ee1e0994 456 dev_warn(s5m8767->dev,
0c9721a5
RH		 457 "ext-control for %pOFn: GPIO not valid, ignoring\n",
458 rdata->reg_node);
ee1e0994
KK		 459 return;
460 }
461
9ae5cc75 462 config->ena_gpiod = rdata->ext_control_gpiod;
ee1e0994
KK		 463}
464
465/*
466 * Turn on GPIO control over BUCK9.
467 */
468static int s5m8767_enable_ext_control(struct s5m8767_info *s5m8767,
469 struct regulator_dev *rdev)
470{
9c4c6055 471 int id = rdev_get_id(rdev);
ee1e0994
KK		 472 int ret, reg, enable_ctrl;
473
9c4c6055 474 if (id != S5M8767_BUCK9)
ee1e0994
KK		 475 return -EINVAL;
476
9c4c6055 477 ret = s5m8767_get_register(s5m8767, id, &reg, &enable_ctrl);
ee1e0994
KK		 478 if (ret)
479 return ret;
480
481 return regmap_update_bits(s5m8767->iodev->regmap_pmic,
482 reg, S5M8767_ENCTRL_MASK,
483 S5M8767_ENCTRL_USE_GPIO << S5M8767_ENCTRL_SHIFT);
484}
485
486
26aec009
ADK		 487#ifdef CONFIG_OF
488static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev,
489 struct sec_platform_data *pdata,
490 struct device_node *pmic_np)
491{
492 int i, gpio;
493
494 for (i = 0; i < 3; i++) {
495 gpio = of_get_named_gpio(pmic_np,
496 "s5m8767,pmic-buck-dvs-gpios", i);
497 if (!gpio_is_valid(gpio)) {
498 dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
499 return -EINVAL;
500 }
501 pdata->buck_gpios[i] = gpio;
502 }
503 return 0;
504}
505
506static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev,
507 struct sec_platform_data *pdata,
508 struct device_node *pmic_np)
509{
510 int i, gpio;
511
512 for (i = 0; i < 3; i++) {
513 gpio = of_get_named_gpio(pmic_np,
514 "s5m8767,pmic-buck-ds-gpios", i);
515 if (!gpio_is_valid(gpio)) {
516 dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
517 return -EINVAL;
518 }
519 pdata->buck_ds[i] = gpio;
520 }
521 return 0;
522}
523
cbb0ed49 524static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
26aec009
ADK		 525 struct sec_platform_data *pdata)
526{
cbb0ed49 527 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
26aec009
ADK		 528 struct device_node *pmic_np, *regulators_np, *reg_np;
529 struct sec_regulator_data *rdata;
530 struct sec_opmode_data *rmode;
04f9f068 531 unsigned int i, dvs_voltage_nr = 8, ret;
26aec009
ADK		 532
533 pmic_np = iodev->dev->of_node;
534 if (!pmic_np) {
535 dev_err(iodev->dev, "could not find pmic sub-node\n");
536 return -ENODEV;
537 }
538
4e52c03d 539 regulators_np = of_get_child_by_name(pmic_np, "regulators");
26aec009
ADK		 540 if (!regulators_np) {
541 dev_err(iodev->dev, "could not find regulators sub-node\n");
542 return -EINVAL;
543 }
544
545 /* count the number of regulators to be supported in pmic */
1f91b6f6 546 pdata->num_regulators = of_get_child_count(regulators_np);
26aec009 547
a86854d0
KC		 548 rdata = devm_kcalloc(&pdev->dev,
549 pdata->num_regulators, sizeof(*rdata),
550 GFP_KERNEL);
4754b421 551 if (!rdata)
26aec009 552 return -ENOMEM;
26aec009 553
a86854d0
KC		 554 rmode = devm_kcalloc(&pdev->dev,
555 pdata->num_regulators, sizeof(*rmode),
556 GFP_KERNEL);
4754b421 557 if (!rmode)
26aec009 558 return -ENOMEM;
26aec009
ADK		 559
560 pdata->regulators = rdata;
561 pdata->opmode = rmode;
562 for_each_child_of_node(regulators_np, reg_np) {
563 for (i = 0; i < ARRAY_SIZE(regulators); i++)
c32569e3 564 if (of_node_name_eq(reg_np, regulators[i].name))
26aec009
ADK		 565 break;
566
567 if (i == ARRAY_SIZE(regulators)) {
568 dev_warn(iodev->dev,
0c9721a5
RH		 569 "don't know how to configure regulator %pOFn\n",
570 reg_np);
26aec009
ADK		 571 continue;
572 }
573
63239e4b
LW		 574 rdata->ext_control_gpiod = devm_gpiod_get_from_of_node(
575 &pdev->dev,
576 reg_np,
577 "s5m8767,pmic-ext-control-gpios",
578 0,
579 GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
580 "s5m8767");
9ae5cc75
LW		 581 if (IS_ERR(rdata->ext_control_gpiod))
582 return PTR_ERR(rdata->ext_control_gpiod);
ee1e0994 583
26aec009
ADK		 584 rdata->id = i;
585 rdata->initdata = of_get_regulator_init_data(
072e78b1
JMC		 586 &pdev->dev, reg_np,
587 &regulators[i]);
26aec009
ADK		 588 rdata->reg_node = reg_np;
589 rdata++;
590 rmode->id = i;
591 if (of_property_read_u32(reg_np, "op_mode",
592 &rmode->mode)) {
593 dev_warn(iodev->dev,
7799167b
RH		 594 "no op_mode property property at %pOF\n",
595 reg_np);
26aec009
ADK		 596
597 rmode->mode = S5M8767_OPMODE_NORMAL_MODE;
598 }
599 rmode++;
600 }
601
b7db01f3
SK		 602 of_node_put(regulators_np);
603
04f9f068 604 if (of_get_property(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs", NULL)) {
26aec009
ADK		 605 pdata->buck2_gpiodvs = true;
606
04f9f068
CC		 607 if (of_property_read_u32_array(pmic_np,
608 "s5m8767,pmic-buck2-dvs-voltage",
609 pdata->buck2_voltage, dvs_voltage_nr)) {
610 dev_err(iodev->dev, "buck2 voltages not specified\n");
611 return -EINVAL;
612 }
613 }
614
615 if (of_get_property(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs", NULL)) {
26aec009
ADK		 616 pdata->buck3_gpiodvs = true;
617
04f9f068
CC		 618 if (of_property_read_u32_array(pmic_np,
619 "s5m8767,pmic-buck3-dvs-voltage",
620 pdata->buck3_voltage, dvs_voltage_nr)) {
621 dev_err(iodev->dev, "buck3 voltages not specified\n");
622 return -EINVAL;
623 }
624 }
625
626 if (of_get_property(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs", NULL)) {
26aec009
ADK		 627 pdata->buck4_gpiodvs = true;
628
04f9f068
CC		 629 if (of_property_read_u32_array(pmic_np,
630 "s5m8767,pmic-buck4-dvs-voltage",
631 pdata->buck4_voltage, dvs_voltage_nr)) {
632 dev_err(iodev->dev, "buck4 voltages not specified\n");
633 return -EINVAL;
634 }
635 }
636
26aec009
ADK		 637 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
638 pdata->buck4_gpiodvs) {
639 ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
640 if (ret)
641 return -EINVAL;
642
643 if (of_property_read_u32(pmic_np,
644 "s5m8767,pmic-buck-default-dvs-idx",
645 &pdata->buck_default_idx)) {
646 pdata->buck_default_idx = 0;
647 } else {
648 if (pdata->buck_default_idx >= 8) {
649 pdata->buck_default_idx = 0;
650 dev_info(iodev->dev,
651 "invalid value for default dvs index, use 0\n");
652 }
653 }
26aec009
ADK		 654 }
655
656 ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np);
657 if (ret)
658 return -EINVAL;
659
033054e8
CC		 660 if (of_get_property(pmic_np, "s5m8767,pmic-buck2-ramp-enable", NULL))
661 pdata->buck2_ramp_enable = true;
26aec009 662
033054e8
CC		 663 if (of_get_property(pmic_np, "s5m8767,pmic-buck3-ramp-enable", NULL))
664 pdata->buck3_ramp_enable = true;
26aec009 665
033054e8
CC		 666 if (of_get_property(pmic_np, "s5m8767,pmic-buck4-ramp-enable", NULL))
667 pdata->buck4_ramp_enable = true;
668
669 if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable
670 || pdata->buck4_ramp_enable) {
671 if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay",
672 &pdata->buck_ramp_delay))
673 pdata->buck_ramp_delay = 0;
26aec009
ADK		 674 }
675
676 return 0;
677}
678#else
cbb0ed49 679static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
26aec009
ADK		 680 struct sec_platform_data *pdata)
681{
682 return 0;
683}
684#endif /* CONFIG_OF */
685
a5023574 686static int s5m8767_pmic_probe(struct platform_device *pdev)
9767ec7f 687{
63063bfb 688 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
26aec009 689 struct sec_platform_data *pdata = iodev->pdata;
c172708d 690 struct regulator_config config = { };
9767ec7f 691 struct s5m8767_info *s5m8767;
0a3ade7e 692 int i, ret, buck_init;
9767ec7f 693
e81d7bc8
AL		 694 if (!pdata) {
695 dev_err(pdev->dev.parent, "Platform data not supplied\n");
696 return -ENODEV;
697 }
698
26aec009 699 if (iodev->dev->of_node) {
cbb0ed49 700 ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata);
26aec009
ADK		 701 if (ret)
702 return ret;
703 }
704
6c4efe24
AL		 705 if (pdata->buck2_gpiodvs) {
706 if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) {
707 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
708 return -EINVAL;
709 }
710 }
711
712 if (pdata->buck3_gpiodvs) {
713 if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) {
714 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
715 return -EINVAL;
716 }
717 }
718
719 if (pdata->buck4_gpiodvs) {
720 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) {
721 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
722 return -EINVAL;
723 }
724 }
725
9767ec7f
SK		 726 s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info),
727 GFP_KERNEL);
728 if (!s5m8767)
729 return -ENOMEM;
730
9767ec7f
SK		 731 s5m8767->dev = &pdev->dev;
732 s5m8767->iodev = iodev;
9bb096ff 733 s5m8767->num_regulators = pdata->num_regulators;
9767ec7f 734 platform_set_drvdata(pdev, s5m8767);
9767ec7f
SK		 735
736 s5m8767->buck_gpioindex = pdata->buck_default_idx;
737 s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs;
738 s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs;
739 s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs;
740 s5m8767->buck_gpios[0] = pdata->buck_gpios[0];
741 s5m8767->buck_gpios[1] = pdata->buck_gpios[1];
742 s5m8767->buck_gpios[2] = pdata->buck_gpios[2];
c848bc85
SK		 743 s5m8767->buck_ds[0] = pdata->buck_ds[0];
744 s5m8767->buck_ds[1] = pdata->buck_ds[1];
745 s5m8767->buck_ds[2] = pdata->buck_ds[2];
746
9767ec7f
SK		 747 s5m8767->ramp_delay = pdata->buck_ramp_delay;
748 s5m8767->buck2_ramp = pdata->buck2_ramp_enable;
749 s5m8767->buck3_ramp = pdata->buck3_ramp_enable;
750 s5m8767->buck4_ramp = pdata->buck4_ramp_enable;
7e44bb83 751 s5m8767->opmode = pdata->opmode;
9767ec7f 752
c848bc85 753 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 754 pdata->buck2_init);
c848bc85 755
d13733f4
KK		 756 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK2DVS2,
757 buck_init);
c848bc85
SK		 758
759 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 760 pdata->buck3_init);
c848bc85 761
d13733f4
KK		 762 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK3DVS2,
763 buck_init);
c848bc85
SK		 764
765 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 766 pdata->buck4_init);
c848bc85 767
d13733f4
KK		 768 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK4DVS2,
769 buck_init);
c848bc85 770
9767ec7f
SK		 771 for (i = 0; i < 8; i++) {
772 if (s5m8767->buck2_gpiodvs) {
773 s5m8767->buck2_vol[i] =
5b5e977c 774 s5m8767_convert_voltage_to_sel(
9767ec7f 775 &buck_voltage_val2,
854f73ec 776 pdata->buck2_voltage[i]);
9767ec7f
SK		 777 }
778
779 if (s5m8767->buck3_gpiodvs) {
780 s5m8767->buck3_vol[i] =
5b5e977c 781 s5m8767_convert_voltage_to_sel(
9767ec7f 782 &buck_voltage_val2,
854f73ec 783 pdata->buck3_voltage[i]);
9767ec7f
SK		 784 }
785
786 if (s5m8767->buck4_gpiodvs) {
787 s5m8767->buck4_vol[i] =
5b5e977c 788 s5m8767_convert_voltage_to_sel(
9767ec7f 789 &buck_voltage_val2,
854f73ec 790 pdata->buck4_voltage[i]);
9767ec7f
SK		 791 }
792 }
793
76c854d1
ADK		 794 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
795 pdata->buck4_gpiodvs) {
796
797 if (!gpio_is_valid(pdata->buck_gpios[0]) ||
798 !gpio_is_valid(pdata->buck_gpios[1]) ||
799 !gpio_is_valid(pdata->buck_gpios[2])) {
800 dev_err(&pdev->dev, "GPIO NOT VALID\n");
801 return -EINVAL;
802 }
803
5febb3c9
AL		 804 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0],
805 "S5M8767 SET1");
806 if (ret)
807 return ret;
808
809 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1],
810 "S5M8767 SET2");
811 if (ret)
812 return ret;
813
814 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2],
815 "S5M8767 SET3");
816 if (ret)
817 return ret;
818
c848bc85
SK		 819 /* SET1 GPIO */
820 gpio_direction_output(pdata->buck_gpios[0],
821 (s5m8767->buck_gpioindex >> 2) & 0x1);
822 /* SET2 GPIO */
823 gpio_direction_output(pdata->buck_gpios[1],
824 (s5m8767->buck_gpioindex >> 1) & 0x1);
825 /* SET3 GPIO */
826 gpio_direction_output(pdata->buck_gpios[2],
827 (s5m8767->buck_gpioindex >> 0) & 0x1);
9767ec7f
SK		 828 }
829
5febb3c9
AL		 830 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2");
831 if (ret)
832 return ret;
c848bc85 833
5febb3c9
AL		 834 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3");
835 if (ret)
836 return ret;
c848bc85 837
5febb3c9
AL		 838 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4");
839 if (ret)
840 return ret;
c848bc85
SK		 841
842 /* DS2 GPIO */
843 gpio_direction_output(pdata->buck_ds[0], 0x0);
844 /* DS3 GPIO */
845 gpio_direction_output(pdata->buck_ds[1], 0x0);
846 /* DS4 GPIO */
847 gpio_direction_output(pdata->buck_ds[2], 0x0);
848
849 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
850 pdata->buck4_gpiodvs) {
d13733f4
KK		 851 regmap_update_bits(s5m8767->iodev->regmap_pmic,
852 S5M8767_REG_BUCK2CTRL, 1 << 1,
853 (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1));
854 regmap_update_bits(s5m8767->iodev->regmap_pmic,
855 S5M8767_REG_BUCK3CTRL, 1 << 1,
856 (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1));
857 regmap_update_bits(s5m8767->iodev->regmap_pmic,
858 S5M8767_REG_BUCK4CTRL, 1 << 1,
859 (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1));
c848bc85 860 }
9767ec7f
SK		 861
862 /* Initialize GPIO DVS registers */
863 for (i = 0; i < 8; i++) {
864 if (s5m8767->buck2_gpiodvs) {
d13733f4
KK		 865 regmap_write(s5m8767->iodev->regmap_pmic,
866 S5M8767_REG_BUCK2DVS1 + i,
867 s5m8767->buck2_vol[i]);
9767ec7f
SK		 868 }
869
870 if (s5m8767->buck3_gpiodvs) {
d13733f4
KK		 871 regmap_write(s5m8767->iodev->regmap_pmic,
872 S5M8767_REG_BUCK3DVS1 + i,
873 s5m8767->buck3_vol[i]);
9767ec7f
SK		 874 }
875
876 if (s5m8767->buck4_gpiodvs) {
d13733f4
KK		 877 regmap_write(s5m8767->iodev->regmap_pmic,
878 S5M8767_REG_BUCK4DVS1 + i,
879 s5m8767->buck4_vol[i]);
9767ec7f
SK		 880 }
881 }
9767ec7f
SK		 882
883 if (s5m8767->buck2_ramp)
d13733f4
KK		 884 regmap_update_bits(s5m8767->iodev->regmap_pmic,
885 S5M8767_REG_DVSRAMP, 0x08, 0x08);
9767ec7f
SK		 886
887 if (s5m8767->buck3_ramp)
d13733f4
KK		 888 regmap_update_bits(s5m8767->iodev->regmap_pmic,
889 S5M8767_REG_DVSRAMP, 0x04, 0x04);
9767ec7f
SK		 890
891 if (s5m8767->buck4_ramp)
d13733f4
KK		 892 regmap_update_bits(s5m8767->iodev->regmap_pmic,
893 S5M8767_REG_DVSRAMP, 0x02, 0x02);
9767ec7f
SK		 894
895 if (s5m8767->buck2_ramp || s5m8767->buck3_ramp
896 || s5m8767->buck4_ramp) {
f37ff6b6 897 unsigned int val;
9767ec7f 898 switch (s5m8767->ramp_delay) {
1af142c6 899 case 5:
f37ff6b6 900 val = S5M8767_DVS_BUCK_RAMP_5;
1af142c6
SK		 901 break;
902 case 10:
f37ff6b6 903 val = S5M8767_DVS_BUCK_RAMP_10;
047ec220 904 break;
9767ec7f 905 case 25:
f37ff6b6 906 val = S5M8767_DVS_BUCK_RAMP_25;
047ec220 907 break;
9767ec7f 908 case 50:
f37ff6b6 909 val = S5M8767_DVS_BUCK_RAMP_50;
047ec220 910 break;
9767ec7f 911 case 100:
f37ff6b6 912 val = S5M8767_DVS_BUCK_RAMP_100;
047ec220 913 break;
9767ec7f 914 default:
f37ff6b6 915 val = S5M8767_DVS_BUCK_RAMP_10;
9767ec7f 916 }
d13733f4
KK		 917 regmap_update_bits(s5m8767->iodev->regmap_pmic,
918 S5M8767_REG_DVSRAMP,
919 S5M8767_DVS_BUCK_RAMP_MASK,
920 val << S5M8767_DVS_BUCK_RAMP_SHIFT);
9767ec7f
SK		 921 }
922
923 for (i = 0; i < pdata->num_regulators; i++) {
63063bfb 924 const struct sec_voltage_desc *desc;
9767ec7f 925 int id = pdata->regulators[i].id;
9c4c6055 926 int enable_reg, enable_val;
e80fb721 927 struct regulator_dev *rdev;
9767ec7f
SK		 928
929 desc = reg_voltage_map[id];
e2eb169b 930 if (desc) {
9767ec7f
SK		 931 regulators[id].n_voltages =
932 (desc->max - desc->min) / desc->step + 1;
e2eb169b
AL		 933 regulators[id].min_uV = desc->min;
934 regulators[id].uV_step = desc->step;
31a932e1
AL		 935 regulators[id].vsel_reg =
936 s5m8767_get_vsel_reg(id, s5m8767);
937 if (id < S5M8767_BUCK1)
938 regulators[id].vsel_mask = 0x3f;
939 else
940 regulators[id].vsel_mask = 0xff;
9c4c6055 941
e07ff943 942 ret = s5m8767_get_register(s5m8767, id, &enable_reg,
9c4c6055 943 &enable_val);
e07ff943
AB		 944 if (ret) {
945 dev_err(s5m8767->dev, "error reading registers\n");
946 return ret;
947 }
9c4c6055
AL		 948 regulators[id].enable_reg = enable_reg;
949 regulators[id].enable_mask = S5M8767_ENCTRL_MASK;
950 regulators[id].enable_val = enable_val;
e2eb169b 951 }
9767ec7f 952
c172708d
MB		 953 config.dev = s5m8767->dev;
954 config.init_data = pdata->regulators[i].initdata;
955 config.driver_data = s5m8767;
3e1e4a5f 956 config.regmap = iodev->regmap_pmic;
26aec009 957 config.of_node = pdata->regulators[i].reg_node;
9ae5cc75 958 config.ena_gpiod = NULL;
1f5163fc
LW		 959 if (pdata->regulators[i].ext_control_gpiod) {
960 /* Assigns config.ena_gpiod */
ee1e0994
KK		 961 s5m8767_regulator_config_ext_control(s5m8767,
962 &pdata->regulators[i], &config);
c172708d 963
1f5163fc
LW		 964 /*
965 * Hand the GPIO descriptor management over to the
966 * regulator core, remove it from devres management.
967 */
968 devm_gpiod_unhinge(s5m8767->dev, config.ena_gpiod);
969 }
e80fb721 970 rdev = devm_regulator_register(&pdev->dev, &regulators[id],
f0db475d 971 &config);
e80fb721
KK		 972 if (IS_ERR(rdev)) {
973 ret = PTR_ERR(rdev);
9767ec7f
SK		 974 dev_err(s5m8767->dev, "regulator init failed for %d\n",
975 id);
f0db475d 976 return ret;
9767ec7f 977 }
ee1e0994 978
9ae5cc75 979 if (pdata->regulators[i].ext_control_gpiod) {
e80fb721 980 ret = s5m8767_enable_ext_control(s5m8767, rdev);
ee1e0994
KK		 981 if (ret < 0) {
982 dev_err(s5m8767->dev,
983 "failed to enable gpio control over %s: %d\n",
e80fb721 984 rdev->desc->name, ret);
ee1e0994
KK		 985 return ret;
986 }
987 }
9767ec7f
SK		 988 }
989
9767ec7f
SK		 990 return 0;
991}
992
993static const struct platform_device_id s5m8767_pmic_id[] = {
994 { "s5m8767-pmic", 0},
995 { },
996};
997MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id);
998
999static struct platform_driver s5m8767_pmic_driver = {
1000 .driver = {
1001 .name = "s5m8767-pmic",
9767ec7f
SK		 1002 },
1003 .probe = s5m8767_pmic_probe,
9767ec7f
SK		 1004 .id_table = s5m8767_pmic_id,
1005};
1006
1007static int __init s5m8767_pmic_init(void)
1008{
1009 return platform_driver_register(&s5m8767_pmic_driver);
1010}
1011subsys_initcall(s5m8767_pmic_init);
1012
1013static void __exit s5m8767_pmic_exit(void)
1014{
1015 platform_driver_unregister(&s5m8767_pmic_driver);
1016}
1017module_exit(s5m8767_pmic_exit);
1018
1019/* Module information */
1020MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
1021MODULE_DESCRIPTION("SAMSUNG S5M8767 Regulator Driver");
1022MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)