[linux-2.6-block.git] / drivers / pwm / pwm-mxs.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/stmp_device.h>

#define SET	0x4
#define CLR	0x8
#define TOG	0xc

#define PWM_CTRL		0x0
#define PWM_ACTIVE0		0x10
#define PWM_PERIOD0		0x20
#define  PERIOD_PERIOD(p)	((p) & 0xffff)
#define  PERIOD_PERIOD_MAX	0x10000
#define  PERIOD_ACTIVE_HIGH	(3 << 16)
#define  PERIOD_INACTIVE_LOW	(2 << 18)
#define  PERIOD_CDIV(div)	(((div) & 0x7) << 20)
#define  PERIOD_CDIV_MAX	8

static const unsigned int cdiv[PERIOD_CDIV_MAX] = {
	1, 2, 4, 8, 16, 64, 256, 1024
};

struct mxs_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	void __iomem *base;
};

#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)

static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  int duty_ns, int period_ns)
{
	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	int ret, div = 0;
	unsigned int period_cycles, duty_cycles;
	unsigned long rate;
	unsigned long long c;

	rate = clk_get_rate(mxs->clk);
	while (1) {
		c = rate / cdiv[div];
		c = c * period_ns;
		do_div(c, 1000000000);
		if (c < PERIOD_PERIOD_MAX)
			break;
		div++;
		if (div >= PERIOD_CDIV_MAX)
			return -EINVAL;
	}

	period_cycles = c;
	c *= duty_ns;
	do_div(c, period_ns);
	duty_cycles = c;

	/*
	 * If the PWM channel is disabled, make sure to turn on the clock
	 * before writing the register. Otherwise, keep it enabled.
	 */
	if (!pwm_is_enabled(pwm)) {
		ret = clk_prepare_enable(mxs->clk);
		if (ret)
			return ret;
	}

	writel(duty_cycles << 16,
			mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
	writel(PERIOD_PERIOD(period_cycles) | PERIOD_ACTIVE_HIGH |
	       PERIOD_INACTIVE_LOW | PERIOD_CDIV(div),
			mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);

	/*
	 * If the PWM is not enabled, turn the clock off again to save power.
	 */
	if (!pwm_is_enabled(pwm))
		clk_disable_unprepare(mxs->clk);

	return 0;
}

static int mxs_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	int ret;

	ret = clk_prepare_enable(mxs->clk);
	if (ret)
		return ret;

	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);

	return 0;
}

static void mxs_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);

	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);

	clk_disable_unprepare(mxs->clk);
}

static const struct pwm_ops mxs_pwm_ops = {
	.config = mxs_pwm_config,
	.enable = mxs_pwm_enable,
	.disable = mxs_pwm_disable,
	.owner = THIS_MODULE,
};

static int mxs_pwm_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mxs_pwm_chip *mxs;
	struct resource *res;
	int ret;

	mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
	if (!mxs)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mxs->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mxs->base))
		return PTR_ERR(mxs->base);

	mxs->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(mxs->clk))
		return PTR_ERR(mxs->clk);

	mxs->chip.dev = &pdev->dev;
	mxs->chip.ops = &mxs_pwm_ops;
	mxs->chip.base = -1;

	ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
		return ret;
	}

	ret = pwmchip_add(&mxs->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, mxs);

	ret = stmp_reset_block(mxs->base);
	if (ret)
		goto pwm_remove;

	return 0;

pwm_remove:
	pwmchip_remove(&mxs->chip);
	return ret;
}

static int mxs_pwm_remove(struct platform_device *pdev)
{
	struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);

	return pwmchip_remove(&mxs->chip);
}

static const struct of_device_id mxs_pwm_dt_ids[] = {
	{ .compatible = "fsl,imx23-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);

static struct platform_driver mxs_pwm_driver = {
	.driver = {
		.name = "mxs-pwm",
		.of_match_table = mxs_pwm_dt_ids,
	},
	.probe = mxs_pwm_probe,
	.remove = mxs_pwm_remove,
};
module_platform_driver(mxs_pwm_driver);

MODULE_ALIAS("platform:mxs-pwm");
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale MXS PWM Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
19ad2b75	1	// SPDX-License-Identifier: GPL-2.0+
4dce82c1 SG	2	/*
4dce82c1 SG	3	* Copyright 2012 Freescale Semiconductor, Inc.
4dce82c1 SG	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/err.h>
	8	#include <linux/io.h>
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/of.h>
	12	#include <linux/of_address.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/pwm.h>
	15	#include <linux/slab.h>
01bf32e9	16	#include <linux/stmp_device.h>
4dce82c1 SG	17
	18	#define SET 0x4
	19	#define CLR 0x8
	20	#define TOG 0xc
	21
	22	#define PWM_CTRL 0x0
	23	#define PWM_ACTIVE0 0x10
	24	#define PWM_PERIOD0 0x20
	25	#define PERIOD_PERIOD(p) ((p) & 0xffff)
	26	#define PERIOD_PERIOD_MAX 0x10000
	27	#define PERIOD_ACTIVE_HIGH (3 << 16)
	28	#define PERIOD_INACTIVE_LOW (2 << 18)
	29	#define PERIOD_CDIV(div) (((div) & 0x7) << 20)
	30	#define PERIOD_CDIV_MAX 8
	31
24ccea1c GH	32	static const unsigned int cdiv[PERIOD_CDIV_MAX] = {
	33	1, 2, 4, 8, 16, 64, 256, 1024
	34	};
	35
4dce82c1 SG	36	struct mxs_pwm_chip {
4dce82c1 SG	37	struct pwm_chip chip;
4dce82c1 SG	38	struct clk *clk;
	39	void __iomem *base;
	40	};
	41
	42	#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
	43
	44	static int mxs_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	45	int duty_ns, int period_ns)
	46	{
	47	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	48	int ret, div = 0;
	49	unsigned int period_cycles, duty_cycles;
	50	unsigned long rate;
	51	unsigned long long c;
	52
	53	rate = clk_get_rate(mxs->clk);
	54	while (1) {
24ccea1c	55	c = rate / cdiv[div];
4dce82c1 SG	56	c = c * period_ns;
	57	do_div(c, 1000000000);
	58	if (c < PERIOD_PERIOD_MAX)
	59	break;
	60	div++;
24ccea1c	61	if (div >= PERIOD_CDIV_MAX)
4dce82c1 SG	62	return -EINVAL;
	63	}
	64
	65	period_cycles = c;
	66	c *= duty_ns;
	67	do_div(c, period_ns);
	68	duty_cycles = c;
	69
	70	/*
	71	* If the PWM channel is disabled, make sure to turn on the clock
	72	* before writing the register. Otherwise, keep it enabled.
	73	*/
5c31252c	74	if (!pwm_is_enabled(pwm)) {
4dce82c1 SG	75	ret = clk_prepare_enable(mxs->clk);
	76	if (ret)
	77	return ret;
	78	}
	79
	80	writel(duty_cycles << 16,
	81	mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
	82	writel(PERIOD_PERIOD(period_cycles) \| PERIOD_ACTIVE_HIGH \|
	83	PERIOD_INACTIVE_LOW \| PERIOD_CDIV(div),
	84	mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
	85
	86	/*
	87	* If the PWM is not enabled, turn the clock off again to save power.
	88	*/
5c31252c	89	if (!pwm_is_enabled(pwm))
4dce82c1 SG	90	clk_disable_unprepare(mxs->clk);
	91
	92	return 0;
	93	}
	94
	95	static int mxs_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	96	{
	97	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	98	int ret;
	99
	100	ret = clk_prepare_enable(mxs->clk);
	101	if (ret)
	102	return ret;
	103
	104	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
	105
	106	return 0;
	107	}
	108
	109	static void mxs_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	110	{
	111	struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
	112
	113	writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
	114
	115	clk_disable_unprepare(mxs->clk);
	116	}
	117
	118	static const struct pwm_ops mxs_pwm_ops = {
	119	.config = mxs_pwm_config,
	120	.enable = mxs_pwm_enable,
	121	.disable = mxs_pwm_disable,
	122	.owner = THIS_MODULE,
	123	};
	124
	125	static int mxs_pwm_probe(struct platform_device *pdev)
	126	{
	127	struct device_node *np = pdev->dev.of_node;
	128	struct mxs_pwm_chip *mxs;
22d260bd	129	struct resource *res;
4dce82c1 SG	130	int ret;
	131
	132	mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
	133	if (!mxs)
	134	return -ENOMEM;
	135
22d260bd	136	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6d4294d1 TR	137	mxs->base = devm_ioremap_resource(&pdev->dev, res);
	138	if (IS_ERR(mxs->base))
	139	return PTR_ERR(mxs->base);
4dce82c1	140
22d260bd SG	141	mxs->clk = devm_clk_get(&pdev->dev, NULL);
	142	if (IS_ERR(mxs->clk))
	143	return PTR_ERR(mxs->clk);
4dce82c1 SG	144
	145	mxs->chip.dev = &pdev->dev;
	146	mxs->chip.ops = &mxs_pwm_ops;
	147	mxs->chip.base = -1;
8c0216f3	148
4dce82c1 SG	149	ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
	150	if (ret < 0) {
	151	dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
22d260bd	152	return ret;
4dce82c1 SG	153	}
	154
	155	ret = pwmchip_add(&mxs->chip);
	156	if (ret < 0) {
	157	dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
22d260bd	158	return ret;
4dce82c1 SG	159	}
4dce82c1 SG	160
4dce82c1 SG	161	platform_set_drvdata(pdev, mxs);
4dce82c1 SG	162
cfb9e4c4 FE	163	ret = stmp_reset_block(mxs->base);
	164	if (ret)
	165	goto pwm_remove;
4dce82c1 SG	166
4dce82c1 SG	167	return 0;
cfb9e4c4 FE	168
	169	pwm_remove:
	170	pwmchip_remove(&mxs->chip);
	171	return ret;
4dce82c1 SG	172	}
4dce82c1 SG	173
77f37917	174	static int mxs_pwm_remove(struct platform_device *pdev)
4dce82c1 SG	175	{
	176	struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);
	177
457fd768	178	return pwmchip_remove(&mxs->chip);
4dce82c1 SG	179	}
4dce82c1 SG	180
f1a8870a	181	static const struct of_device_id mxs_pwm_dt_ids[] = {
071407ee	182	{ .compatible = "fsl,imx23-pwm", },
4dce82c1 SG	183	{ /* sentinel */ }
	184	};
	185	MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
	186
	187	static struct platform_driver mxs_pwm_driver = {
	188	.driver = {
	189	.name = "mxs-pwm",
de02cb88	190	.of_match_table = mxs_pwm_dt_ids,
4dce82c1 SG	191	},
4dce82c1 SG	192	.probe = mxs_pwm_probe,
fd109112	193	.remove = mxs_pwm_remove,
4dce82c1 SG	194	};
	195	module_platform_driver(mxs_pwm_driver);
	196
	197	MODULE_ALIAS("platform:mxs-pwm");
	198	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	199	MODULE_DESCRIPTION("Freescale MXS PWM Driver");
	200	MODULE_LICENSE("GPL v2");