[linux-2.6-block.git] / drivers / pnp / quirks.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  This file contains quirk handling code for PnP devices
 *  Some devices do not report all their resources, and need to have extra
 *  resources added. This is most easily accomplished at initialisation time
 *  when building up the resource structure for the first time.
 *
 *  Copyright (c) 2000 Peter Denison <peterd@pnd-pc.demon.co.uk>
 *  Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
 *	Bjorn Helgaas <bjorn.helgaas@hp.com>
 *
 *  Heavily based on PCI quirks handling which is
 *
 *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/pnp.h>
#include <linux/io.h>
#include <linux/kallsyms.h>
#include "base.h"

static void quirk_awe32_add_ports(struct pnp_dev *dev,
				  struct pnp_option *option,
				  unsigned int offset)
{
	struct pnp_option *new_option;

	new_option = kmalloc(sizeof(struct pnp_option), GFP_KERNEL);
	if (!new_option) {
		dev_err(&dev->dev, "couldn't add ioport region to option set "
			"%d\n", pnp_option_set(option));
		return;
	}

	*new_option = *option;
	new_option->u.port.min += offset;
	new_option->u.port.max += offset;
	list_add(&new_option->list, &option->list);

	dev_info(&dev->dev, "added ioport region %#llx-%#llx to set %d\n",
		(unsigned long long) new_option->u.port.min,
		(unsigned long long) new_option->u.port.max,
		pnp_option_set(option));
}

static void quirk_awe32_resources(struct pnp_dev *dev)
{
	struct pnp_option *option;
	unsigned int set = ~0;

	/*
	 * Add two extra ioport regions (at offset 0x400 and 0x800 from the
	 * one given) to every dependent option set.
	 */
	list_for_each_entry(option, &dev->options, list) {
		if (pnp_option_is_dependent(option) &&
		    pnp_option_set(option) != set) {
			set = pnp_option_set(option);
			quirk_awe32_add_ports(dev, option, 0x800);
			quirk_awe32_add_ports(dev, option, 0x400);
		}
	}
}

static void quirk_cmi8330_resources(struct pnp_dev *dev)
{
	struct pnp_option *option;
	struct pnp_irq *irq;
	struct pnp_dma *dma;

	list_for_each_entry(option, &dev->options, list) {
		if (!pnp_option_is_dependent(option))
			continue;

		if (option->type == IORESOURCE_IRQ) {
			irq = &option->u.irq;
			bitmap_zero(irq->map.bits, PNP_IRQ_NR);
			__set_bit(5, irq->map.bits);
			__set_bit(7, irq->map.bits);
			__set_bit(10, irq->map.bits);
			dev_info(&dev->dev, "set possible IRQs in "
				 "option set %d to 5, 7, 10\n",
				 pnp_option_set(option));
		} else if (option->type == IORESOURCE_DMA) {
			dma = &option->u.dma;
			if ((dma->flags & IORESOURCE_DMA_TYPE_MASK) ==
						IORESOURCE_DMA_8BIT &&
			    dma->map != 0x0A) {
				dev_info(&dev->dev, "changing possible "
					 "DMA channel mask in option set %d "
					 "from %#02x to 0x0A (1, 3)\n",
					 pnp_option_set(option), dma->map);
				dma->map = 0x0A;
			}
		}
	}
}

static void quirk_sb16audio_resources(struct pnp_dev *dev)
{
	struct pnp_option *option;
	unsigned int prev_option_flags = ~0, n = 0;
	struct pnp_port *port;

	/*
	 * The default range on the OPL port for these devices is 0x388-0x388.
	 * Here we increase that range so that two such cards can be
	 * auto-configured.
	 */
	list_for_each_entry(option, &dev->options, list) {
		if (prev_option_flags != option->flags) {
			prev_option_flags = option->flags;
			n = 0;
		}

		if (pnp_option_is_dependent(option) &&
		    option->type == IORESOURCE_IO) {
			n++;
			port = &option->u.port;
			if (n == 3 && port->min == port->max) {
				port->max += 0x70;
				dev_info(&dev->dev, "increased option port "
					 "range from %#llx-%#llx to "
					 "%#llx-%#llx\n",
					 (unsigned long long) port->min,
					 (unsigned long long) port->min,
					 (unsigned long long) port->min,
					 (unsigned long long) port->max);
			}
		}
	}
}

static struct pnp_option *pnp_clone_dependent_set(struct pnp_dev *dev,
						  unsigned int set)
{
	struct pnp_option *tail = NULL, *first_new_option = NULL;
	struct pnp_option *option, *new_option;
	unsigned int flags;

	list_for_each_entry(option, &dev->options, list) {
		if (pnp_option_is_dependent(option))
			tail = option;
	}
	if (!tail) {
		dev_err(&dev->dev, "no dependent option sets\n");
		return NULL;
	}

	flags = pnp_new_dependent_set(dev, PNP_RES_PRIORITY_FUNCTIONAL);
	list_for_each_entry(option, &dev->options, list) {
		if (pnp_option_is_dependent(option) &&
		    pnp_option_set(option) == set) {
			new_option = kmalloc(sizeof(struct pnp_option),
					     GFP_KERNEL);
			if (!new_option) {
				dev_err(&dev->dev, "couldn't clone dependent "
					"set %d\n", set);
				return NULL;
			}

			*new_option = *option;
			new_option->flags = flags;
			if (!first_new_option)
				first_new_option = new_option;

			list_add(&new_option->list, &tail->list);
			tail = new_option;
		}
	}

	return first_new_option;
}


static void quirk_add_irq_optional_dependent_sets(struct pnp_dev *dev)
{
	struct pnp_option *new_option;
	unsigned int num_sets, i, set;
	struct pnp_irq *irq;

	num_sets = dev->num_dependent_sets;
	for (i = 0; i < num_sets; i++) {
		new_option = pnp_clone_dependent_set(dev, i);
		if (!new_option)
			return;

		set = pnp_option_set(new_option);
		while (new_option && pnp_option_set(new_option) == set) {
			if (new_option->type == IORESOURCE_IRQ) {
				irq = &new_option->u.irq;
				irq->flags |= IORESOURCE_IRQ_OPTIONAL;
			}
			dbg_pnp_show_option(dev, new_option);
			new_option = list_entry(new_option->list.next,
						struct pnp_option, list);
		}

		dev_info(&dev->dev, "added dependent option set %d (same as "
			 "set %d except IRQ optional)\n", set, i);
	}
}

static void quirk_ad1815_mpu_resources(struct pnp_dev *dev)
{
	struct pnp_option *option;
	struct pnp_irq *irq = NULL;
	unsigned int independent_irqs = 0;

	list_for_each_entry(option, &dev->options, list) {
		if (option->type == IORESOURCE_IRQ &&
		    !pnp_option_is_dependent(option)) {
			independent_irqs++;
			irq = &option->u.irq;
		}
	}

	if (independent_irqs != 1)
		return;

	irq->flags |= IORESOURCE_IRQ_OPTIONAL;
	dev_info(&dev->dev, "made independent IRQ optional\n");
}

#include <linux/pci.h>

static void quirk_system_pci_resources(struct pnp_dev *dev)
{
	struct pci_dev *pdev = NULL;
	struct resource *res;
	resource_size_t pnp_start, pnp_end, pci_start, pci_end;
	int i, j;

	/*
	 * Some BIOSes have PNP motherboard devices with resources that
	 * partially overlap PCI BARs.  The PNP system driver claims these
	 * motherboard resources, which prevents the normal PCI driver from
	 * requesting them later.
	 *
	 * This patch disables the PNP resources that conflict with PCI BARs
	 * so they won't be claimed by the PNP system driver.
	 */
	for_each_pci_dev(pdev) {
		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			unsigned long flags, type;

			flags = pci_resource_flags(pdev, i);
			type = flags & (IORESOURCE_IO | IORESOURCE_MEM);
			if (!type || pci_resource_len(pdev, i) == 0)
				continue;

			if (flags & IORESOURCE_UNSET)
				continue;

			pci_start = pci_resource_start(pdev, i);
			pci_end = pci_resource_end(pdev, i);
			for (j = 0;
			     (res = pnp_get_resource(dev, type, j)); j++) {
				if (res->start == 0 && res->end == 0)
					continue;

				pnp_start = res->start;
				pnp_end = res->end;

				/*
				 * If the PNP region doesn't overlap the PCI
				 * region at all, there's no problem.
				 */
				if (pnp_end < pci_start || pnp_start > pci_end)
					continue;

				/*
				 * If the PNP region completely encloses (or is
				 * at least as large as) the PCI region, that's
				 * also OK.  For example, this happens when the
				 * PNP device describes a bridge with PCI
				 * behind it.
				 */
				if (pnp_start <= pci_start &&
				    pnp_end >= pci_end)
					continue;

				/*
				 * Otherwise, the PNP region overlaps *part* of
				 * the PCI region, and that might prevent a PCI
				 * driver from requesting its resources.
				 */
				dev_warn(&dev->dev,
					 "disabling %pR because it overlaps "
					 "%s BAR %d %pR\n", res,
					 pci_name(pdev), i, &pdev->resource[i]);
				res->flags |= IORESOURCE_DISABLED;
			}
		}
	}
}

#ifdef CONFIG_AMD_NB

#include <asm/amd_nb.h>

static void quirk_amd_mmconfig_area(struct pnp_dev *dev)
{
	resource_size_t start, end;
	struct pnp_resource *pnp_res;
	struct resource *res;
	struct resource mmconfig_res, *mmconfig;

	mmconfig = amd_get_mmconfig_range(&mmconfig_res);
	if (!mmconfig)
		return;

	list_for_each_entry(pnp_res, &dev->resources, list) {
		res = &pnp_res->res;
		if (res->end < mmconfig->start || res->start > mmconfig->end ||
		    (res->start == mmconfig->start && res->end == mmconfig->end))
			continue;

		dev_info(&dev->dev, FW_BUG
			 "%pR covers only part of AMD MMCONFIG area %pR; adding more reservations\n",
			 res, mmconfig);
		if (mmconfig->start < res->start) {
			start = mmconfig->start;
			end = res->start - 1;
			pnp_add_mem_resource(dev, start, end, 0);
		}
		if (mmconfig->end > res->end) {
			start = res->end + 1;
			end = mmconfig->end;
			pnp_add_mem_resource(dev, start, end, 0);
		}
		break;
	}
}
#endif

#ifdef CONFIG_PCI
/* Device IDs of parts that have 32KB MCH space */
static const unsigned int mch_quirk_devices[] = {
	0x0154,	/* Ivy Bridge */
	0x0a04, /* Haswell-ULT */
	0x0c00,	/* Haswell */
	0x1604, /* Broadwell */
};

static struct pci_dev *get_intel_host(void)
{
	int i;
	struct pci_dev *host;

	for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) {
		host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i],
				      NULL);
		if (host)
			return host;
	}
	return NULL;
}

static void quirk_intel_mch(struct pnp_dev *dev)
{
	struct pci_dev *host;
	u32 addr_lo, addr_hi;
	struct pci_bus_region region;
	struct resource mch;
	struct pnp_resource *pnp_res;
	struct resource *res;

	host = get_intel_host();
	if (!host)
		return;

	/*
	 * MCHBAR is not an architected PCI BAR, so MCH space is usually
	 * reported as a PNP0C02 resource.  The MCH space was originally
	 * 16KB, but is 32KB in newer parts.  Some BIOSes still report a
	 * PNP0C02 resource that is only 16KB, which means the rest of the
	 * MCH space is consumed but unreported.
	 */

	/*
	 * Read MCHBAR for Host Member Mapped Register Range Base
	 * https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet
	 * Sec 3.1.12.
	 */
	pci_read_config_dword(host, 0x48, &addr_lo);
	region.start = addr_lo & ~0x7fff;
	pci_read_config_dword(host, 0x4c, &addr_hi);
	region.start |= (u64) addr_hi << 32;
	region.end = region.start + 32*1024 - 1;

	memset(&mch, 0, sizeof(mch));
	mch.flags = IORESOURCE_MEM;
	pcibios_bus_to_resource(host->bus, &mch, &region);

	list_for_each_entry(pnp_res, &dev->resources, list) {
		res = &pnp_res->res;
		if (res->end < mch.start || res->start > mch.end)
			continue;	/* no overlap */
		if (res->start == mch.start && res->end == mch.end)
			continue;	/* exact match */

		dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n",
			 res, pci_name(host), &mch);
		res->start = mch.start;
		res->end = mch.end;
		break;
	}

	pci_dev_put(host);
}
#endif

/*
 *  PnP Quirks
 *  Cards or devices that need some tweaking due to incomplete resource info
 */

static struct pnp_fixup pnp_fixups[] = {
	/* Soundblaster awe io port quirk */
	{"CTL0021", quirk_awe32_resources},
	{"CTL0022", quirk_awe32_resources},
	{"CTL0023", quirk_awe32_resources},
	/* CMI 8330 interrupt and dma fix */
	{"@X@0001", quirk_cmi8330_resources},
	/* Soundblaster audio device io port range quirk */
	{"CTL0001", quirk_sb16audio_resources},
	{"CTL0031", quirk_sb16audio_resources},
	{"CTL0041", quirk_sb16audio_resources},
	{"CTL0042", quirk_sb16audio_resources},
	{"CTL0043", quirk_sb16audio_resources},
	{"CTL0044", quirk_sb16audio_resources},
	{"CTL0045", quirk_sb16audio_resources},
	/* Add IRQ-optional MPU options */
	{"ADS7151", quirk_ad1815_mpu_resources},
	{"ADS7181", quirk_add_irq_optional_dependent_sets},
	{"AZT0002", quirk_add_irq_optional_dependent_sets},
	/* PnP resources that might overlap PCI BARs */
	{"PNP0c01", quirk_system_pci_resources},
	{"PNP0c02", quirk_system_pci_resources},
#ifdef CONFIG_AMD_NB
	{"PNP0c01", quirk_amd_mmconfig_area},
#endif
#ifdef CONFIG_PCI
	{"PNP0c02", quirk_intel_mch},
#endif
	{""}
};

void pnp_fixup_device(struct pnp_dev *dev)
{
	struct pnp_fixup *f;

	for (f = pnp_fixups; *f->id; f++) {
		if (!compare_pnp_id(dev->id, f->id))
			continue;
		pnp_dbg(&dev->dev, "%s: calling %pF\n", f->id,
			f->quirk_function);
		f->quirk_function(dev);
	}
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* This file contains quirk handling code for PnP devices
	4	* Some devices do not report all their resources, and need to have extra
	5	* resources added. This is most easily accomplished at initialisation time
	6	* when building up the resource structure for the first time.
	7	*
	8	* Copyright (c) 2000 Peter Denison <peterd@pnd-pc.demon.co.uk>
1f32ca31 BH	9	* Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
1f32ca31 BH	10	* Bjorn Helgaas <bjorn.helgaas@hp.com>
1da177e4 LT	11	*
	12	* Heavily based on PCI quirks handling which is
	13	*
	14	* Copyright (c) 1999 Martin Mares <mj@ucw.cz>
	15	*/
	16
1da177e4 LT	17	#include <linux/types.h>
1da177e4 LT	18	#include <linux/kernel.h>
cb171f7a	19	#include <linux/pci.h>
1da177e4 LT	20	#include <linux/string.h>
1da177e4 LT	21	#include <linux/slab.h>
1da177e4	22	#include <linux/pnp.h>
a1e7e636	23	#include <linux/io.h>
a05d0781	24	#include <linux/kallsyms.h>
1da177e4 LT	25	#include "base.h"
1da177e4 LT	26
1f32ca31 BH	27	static void quirk_awe32_add_ports(struct pnp_dev *dev,
	28	struct pnp_option *option,
	29	unsigned int offset)
	30	{
	31	struct pnp_option *new_option;
	32
	33	new_option = kmalloc(sizeof(struct pnp_option), GFP_KERNEL);
	34	if (!new_option) {
	35	dev_err(&dev->dev, "couldn't add ioport region to option set "
	36	"%d\n", pnp_option_set(option));
	37	return;
	38	}
	39
	40	new_option = option;
	41	new_option->u.port.min += offset;
	42	new_option->u.port.max += offset;
	43	list_add(&new_option->list, &option->list);
	44
	45	dev_info(&dev->dev, "added ioport region %#llx-%#llx to set %d\n",
	46	(unsigned long long) new_option->u.port.min,
	47	(unsigned long long) new_option->u.port.max,
	48	pnp_option_set(option));
	49	}
	50
1da177e4 LT	51	static void quirk_awe32_resources(struct pnp_dev *dev)
1da177e4 LT	52	{
1f32ca31 BH	53	struct pnp_option *option;
1f32ca31 BH	54	unsigned int set = ~0;
1da177e4 LT	55
1da177e4 LT	56	/*
1f32ca31 BH	57	* Add two extra ioport regions (at offset 0x400 and 0x800 from the
1f32ca31 BH	58	* one given) to every dependent option set.
1da177e4	59	*/
1f32ca31 BH	60	list_for_each_entry(option, &dev->options, list) {
	61	if (pnp_option_is_dependent(option) &&
	62	pnp_option_set(option) != set) {
	63	set = pnp_option_set(option);
	64	quirk_awe32_add_ports(dev, option, 0x800);
	65	quirk_awe32_add_ports(dev, option, 0x400);
1da177e4	66	}
1da177e4	67	}
1da177e4 LT	68	}
	69
	70	static void quirk_cmi8330_resources(struct pnp_dev *dev)
	71	{
1f32ca31 BH	72	struct pnp_option *option;
	73	struct pnp_irq *irq;
	74	struct pnp_dma *dma;
1da177e4	75
1f32ca31 BH	76	list_for_each_entry(option, &dev->options, list) {
	77	if (!pnp_option_is_dependent(option))
	78	continue;
1da177e4	79
1f32ca31 BH	80	if (option->type == IORESOURCE_IRQ) {
	81	irq = &option->u.irq;
	82	bitmap_zero(irq->map.bits, PNP_IRQ_NR);
	83	__set_bit(5, irq->map.bits);
	84	__set_bit(7, irq->map.bits);
	85	__set_bit(10, irq->map.bits);
	86	dev_info(&dev->dev, "set possible IRQs in "
	87	"option set %d to 5, 7, 10\n",
	88	pnp_option_set(option));
	89	} else if (option->type == IORESOURCE_DMA) {
	90	dma = &option->u.dma;
9dd78466	91	if ((dma->flags & IORESOURCE_DMA_TYPE_MASK) ==
1f32ca31 BH	92	IORESOURCE_DMA_8BIT &&
	93	dma->map != 0x0A) {
	94	dev_info(&dev->dev, "changing possible "
	95	"DMA channel mask in option set %d "
	96	"from %#02x to 0x0A (1, 3)\n",
	97	pnp_option_set(option), dma->map);
	98	dma->map = 0x0A;
	99	}
7aefff51	100	}
1da177e4	101	}
1da177e4 LT	102	}
	103
	104	static void quirk_sb16audio_resources(struct pnp_dev *dev)
	105	{
1f32ca31 BH	106	struct pnp_option *option;
1f32ca31 BH	107	unsigned int prev_option_flags = ~0, n = 0;
1da177e4	108	struct pnp_port *port;
1da177e4 LT	109
1da177e4 LT	110	/*
1f32ca31	111	* The default range on the OPL port for these devices is 0x388-0x388.
1da177e4 LT	112	* Here we increase that range so that two such cards can be
	113	* auto-configured.
	114	*/
1f32ca31 BH	115	list_for_each_entry(option, &dev->options, list) {
	116	if (prev_option_flags != option->flags) {
	117	prev_option_flags = option->flags;
	118	n = 0;
	119	}
1da177e4	120
1f32ca31 BH	121	if (pnp_option_is_dependent(option) &&
	122	option->type == IORESOURCE_IO) {
	123	n++;
	124	port = &option->u.port;
	125	if (n == 3 && port->min == port->max) {
	126	port->max += 0x70;
	127	dev_info(&dev->dev, "increased option port "
	128	"range from %#llx-%#llx to "
	129	"%#llx-%#llx\n",
	130	(unsigned long long) port->min,
	131	(unsigned long long) port->min,
	132	(unsigned long long) port->min,
	133	(unsigned long long) port->max);
	134	}
	135	}
1da177e4	136	}
1da177e4 LT	137	}
1da177e4 LT	138
1f32ca31 BH	139	static struct pnp_option pnp_clone_dependent_set(struct pnp_dev dev,
1f32ca31 BH	140	unsigned int set)
3b73a223	141	{
1f32ca31 BH	142	struct pnp_option tail = NULL, first_new_option = NULL;
	143	struct pnp_option option, new_option;
	144	unsigned int flags;
3b73a223	145
1f32ca31 BH	146	list_for_each_entry(option, &dev->options, list) {
	147	if (pnp_option_is_dependent(option))
	148	tail = option;
	149	}
	150	if (!tail) {
	151	dev_err(&dev->dev, "no dependent option sets\n");
	152	return NULL;
	153	}
d5ebde6e	154
1f32ca31 BH	155	flags = pnp_new_dependent_set(dev, PNP_RES_PRIORITY_FUNCTIONAL);
	156	list_for_each_entry(option, &dev->options, list) {
	157	if (pnp_option_is_dependent(option) &&
	158	pnp_option_set(option) == set) {
	159	new_option = kmalloc(sizeof(struct pnp_option),
	160	GFP_KERNEL);
	161	if (!new_option) {
	162	dev_err(&dev->dev, "couldn't clone dependent "
	163	"set %d\n", set);
	164	return NULL;
	165	}
3b73a223	166
1f32ca31 BH	167	new_option = option;
	168	new_option->flags = flags;
	169	if (!first_new_option)
	170	first_new_option = new_option;
3b73a223	171
1f32ca31 BH	172	list_add(&new_option->list, &tail->list);
1f32ca31 BH	173	tail = new_option;
3b73a223	174	}
3b73a223	175	}
3b73a223	176
1f32ca31	177	return first_new_option;
3b73a223 RH	178	}
3b73a223 RH	179
1f32ca31 BH	180
1f32ca31 BH	181	static void quirk_add_irq_optional_dependent_sets(struct pnp_dev *dev)
3b73a223	182	{
1f32ca31 BH	183	struct pnp_option *new_option;
1f32ca31 BH	184	unsigned int num_sets, i, set;
3b73a223 RH	185	struct pnp_irq *irq;
3b73a223 RH	186
1f32ca31 BH	187	num_sets = dev->num_dependent_sets;
	188	for (i = 0; i < num_sets; i++) {
	189	new_option = pnp_clone_dependent_set(dev, i);
	190	if (!new_option)
	191	return;
3b73a223	192
1f32ca31 BH	193	set = pnp_option_set(new_option);
	194	while (new_option && pnp_option_set(new_option) == set) {
	195	if (new_option->type == IORESOURCE_IRQ) {
	196	irq = &new_option->u.irq;
	197	irq->flags \|= IORESOURCE_IRQ_OPTIONAL;
	198	}
	199	dbg_pnp_show_option(dev, new_option);
	200	new_option = list_entry(new_option->list.next,
	201	struct pnp_option, list);
	202	}
3b73a223	203
1f32ca31 BH	204	dev_info(&dev->dev, "added dependent option set %d (same as "
	205	"set %d except IRQ optional)\n", set, i);
	206	}
3b73a223 RH	207	}
3b73a223 RH	208
1f32ca31	209	static void quirk_ad1815_mpu_resources(struct pnp_dev *dev)
3b73a223	210	{
1f32ca31 BH	211	struct pnp_option *option;
	212	struct pnp_irq *irq = NULL;
	213	unsigned int independent_irqs = 0;
	214
	215	list_for_each_entry(option, &dev->options, list) {
	216	if (option->type == IORESOURCE_IRQ &&
	217	!pnp_option_is_dependent(option)) {
	218	independent_irqs++;
	219	irq = &option->u.irq;
	220	}
	221	}
3b73a223	222
1f32ca31	223	if (independent_irqs != 1)
3b73a223 RH	224	return;
3b73a223 RH	225
1f32ca31 BH	226	irq->flags \|= IORESOURCE_IRQ_OPTIONAL;
1f32ca31 BH	227	dev_info(&dev->dev, "made independent IRQ optional\n");
3b73a223	228	}
0509ad5e BH	229
	230	#include <linux/pci.h>
	231
	232	static void quirk_system_pci_resources(struct pnp_dev *dev)
	233	{
	234	struct pci_dev *pdev = NULL;
53052feb	235	struct resource *res;
0509ad5e BH	236	resource_size_t pnp_start, pnp_end, pci_start, pci_end;
	237	int i, j;
	238
	239	/*
	240	* Some BIOSes have PNP motherboard devices with resources that
	241	* partially overlap PCI BARs. The PNP system driver claims these
	242	* motherboard resources, which prevents the normal PCI driver from
	243	* requesting them later.
	244	*
	245	* This patch disables the PNP resources that conflict with PCI BARs
	246	* so they won't be claimed by the PNP system driver.
	247	*/
	248	for_each_pci_dev(pdev) {
	249	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
f7834c09	250	unsigned long flags, type;
999ed65a	251
f7834c09 BH	252	flags = pci_resource_flags(pdev, i);
f7834c09 BH	253	type = flags & (IORESOURCE_IO \| IORESOURCE_MEM);
999ed65a	254	if (!type \|\| pci_resource_len(pdev, i) == 0)
0509ad5e BH	255	continue;
0509ad5e BH	256
f7834c09 BH	257	if (flags & IORESOURCE_UNSET)
	258	continue;
	259
0509ad5e BH	260	pci_start = pci_resource_start(pdev, i);
0509ad5e BH	261	pci_end = pci_resource_end(pdev, i);
95ab3669	262	for (j = 0;
999ed65a	263	(res = pnp_get_resource(dev, type, j)); j++) {
aee3ad81	264	if (res->start == 0 && res->end == 0)
0509ad5e BH	265	continue;
0509ad5e BH	266
95ab3669 BH	267	pnp_start = res->start;
95ab3669 BH	268	pnp_end = res->end;
0509ad5e BH	269
	270	/*
	271	* If the PNP region doesn't overlap the PCI
	272	* region at all, there's no problem.
	273	*/
	274	if (pnp_end < pci_start \|\| pnp_start > pci_end)
	275	continue;
	276
	277	/*
	278	* If the PNP region completely encloses (or is
	279	* at least as large as) the PCI region, that's
	280	* also OK. For example, this happens when the
	281	* PNP device describes a bridge with PCI
	282	* behind it.
	283	*/
	284	if (pnp_start <= pci_start &&
	285	pnp_end >= pci_end)
	286	continue;
	287
	288	/*
	289	* Otherwise, the PNP region overlaps part of
	290	* the PCI region, and that might prevent a PCI
	291	* driver from requesting its resources.
	292	*/
c7dabef8 BH	293	dev_warn(&dev->dev,
	294	"disabling %pR because it overlaps "
	295	"%s BAR %d %pR\n", res,
9a007b37	296	pci_name(pdev), i, &pdev->resource[i]);
4b34fe15	297	res->flags \|= IORESOURCE_DISABLED;
0509ad5e BH	298	}
	299	}
	300	}
	301	}
	302
eb31aae8 BH	303	#ifdef CONFIG_AMD_NB
	304
	305	#include <asm/amd_nb.h>
	306
	307	static void quirk_amd_mmconfig_area(struct pnp_dev *dev)
	308	{
	309	resource_size_t start, end;
	310	struct pnp_resource *pnp_res;
	311	struct resource *res;
	312	struct resource mmconfig_res, *mmconfig;
	313
	314	mmconfig = amd_get_mmconfig_range(&mmconfig_res);
	315	if (!mmconfig)
	316	return;
	317
	318	list_for_each_entry(pnp_res, &dev->resources, list) {
	319	res = &pnp_res->res;
	320	if (res->end < mmconfig->start \|\| res->start > mmconfig->end \|\|
	321	(res->start == mmconfig->start && res->end == mmconfig->end))
	322	continue;
	323
	324	dev_info(&dev->dev, FW_BUG
	325	"%pR covers only part of AMD MMCONFIG area %pR; adding more reservations\n",
	326	res, mmconfig);
	327	if (mmconfig->start < res->start) {
	328	start = mmconfig->start;
	329	end = res->start - 1;
	330	pnp_add_mem_resource(dev, start, end, 0);
	331	}
	332	if (mmconfig->end > res->end) {
	333	start = res->end + 1;
	334	end = mmconfig->end;
	335	pnp_add_mem_resource(dev, start, end, 0);
	336	}
	337	break;
	338	}
	339	}
	340	#endif
	341
b3413afb	342	#ifdef CONFIG_PCI
cb171f7a BH	343	/* Device IDs of parts that have 32KB MCH space */
	344	static const unsigned int mch_quirk_devices[] = {
	345	0x0154, /* Ivy Bridge */
ed1f0eee	346	0x0a04, /* Haswell-ULT */
cb171f7a	347	0x0c00, /* Haswell */
a77060f0	348	0x1604, /* Broadwell */
cb171f7a BH	349	};
	350
	351	static struct pci_dev *get_intel_host(void)
	352	{
	353	int i;
	354	struct pci_dev *host;
	355
	356	for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) {
	357	host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i],
	358	NULL);
	359	if (host)
	360	return host;
	361	}
	362	return NULL;
	363	}
	364
	365	static void quirk_intel_mch(struct pnp_dev *dev)
	366	{
	367	struct pci_dev *host;
	368	u32 addr_lo, addr_hi;
	369	struct pci_bus_region region;
	370	struct resource mch;
	371	struct pnp_resource *pnp_res;
	372	struct resource *res;
	373
	374	host = get_intel_host();
	375	if (!host)
	376	return;
	377
	378	/*
	379	* MCHBAR is not an architected PCI BAR, so MCH space is usually
	380	* reported as a PNP0C02 resource. The MCH space was originally
	381	* 16KB, but is 32KB in newer parts. Some BIOSes still report a
	382	* PNP0C02 resource that is only 16KB, which means the rest of the
	383	* MCH space is consumed but unreported.
	384	*/
	385
	386	/*
	387	* Read MCHBAR for Host Member Mapped Register Range Base
	388	* https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet
	389	* Sec 3.1.12.
	390	*/
	391	pci_read_config_dword(host, 0x48, &addr_lo);
	392	region.start = addr_lo & ~0x7fff;
	393	pci_read_config_dword(host, 0x4c, &addr_hi);
	394	region.start \|= (u64) addr_hi << 32;
	395	region.end = region.start + 32*1024 - 1;
	396
	397	memset(&mch, 0, sizeof(mch));
	398	mch.flags = IORESOURCE_MEM;
	399	pcibios_bus_to_resource(host->bus, &mch, &region);
	400
	401	list_for_each_entry(pnp_res, &dev->resources, list) {
	402	res = &pnp_res->res;
	403	if (res->end < mch.start \|\| res->start > mch.end)
	404	continue; /* no overlap */
	405	if (res->start == mch.start && res->end == mch.end)
	406	continue; /* exact match */
	407
	408	dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n",
	409	res, pci_name(host), &mch);
	410	res->start = mch.start;
	411	res->end = mch.end;
	412	break;
413	}
414
415	pci_dev_put(host);
416	}
417	#endif
418
1da177e4 LT	419	/*
	420	* PnP Quirks
	421	* Cards or devices that need some tweaking due to incomplete resource info
	422	*/
	423
	424	static struct pnp_fixup pnp_fixups[] = {
	425	/* Soundblaster awe io port quirk */
9dd78466 BH	426	{"CTL0021", quirk_awe32_resources},
	427	{"CTL0022", quirk_awe32_resources},
	428	{"CTL0023", quirk_awe32_resources},
1da177e4	429	/* CMI 8330 interrupt and dma fix */
9dd78466	430	{"@X@0001", quirk_cmi8330_resources},
1da177e4	431	/* Soundblaster audio device io port range quirk */
9dd78466 BH	432	{"CTL0001", quirk_sb16audio_resources},
	433	{"CTL0031", quirk_sb16audio_resources},
	434	{"CTL0041", quirk_sb16audio_resources},
	435	{"CTL0042", quirk_sb16audio_resources},
	436	{"CTL0043", quirk_sb16audio_resources},
	437	{"CTL0044", quirk_sb16audio_resources},
	438	{"CTL0045", quirk_sb16audio_resources},
1f32ca31	439	/* Add IRQ-optional MPU options */
3b73a223	440	{"ADS7151", quirk_ad1815_mpu_resources},
1f32ca31 BH	441	{"ADS7181", quirk_add_irq_optional_dependent_sets},
1f32ca31 BH	442	{"AZT0002", quirk_add_irq_optional_dependent_sets},
3b73a223	443	/* PnP resources that might overlap PCI BARs */
0509ad5e BH	444	{"PNP0c01", quirk_system_pci_resources},
0509ad5e BH	445	{"PNP0c02", quirk_system_pci_resources},
eb31aae8 BH	446	#ifdef CONFIG_AMD_NB
eb31aae8 BH	447	{"PNP0c01", quirk_amd_mmconfig_area},
cb171f7a	448	#endif
b3413afb	449	#ifdef CONFIG_PCI
cb171f7a	450	{"PNP0c02", quirk_intel_mch},
eb31aae8	451	#endif
9dd78466	452	{""}
1da177e4 LT	453	};
	454
	455	void pnp_fixup_device(struct pnp_dev *dev)
	456	{
726a7a3d	457	struct pnp_fixup *f;
a05d0781	458
726a7a3d RH	459	for (f = pnp_fixups; *f->id; f++) {
	460	if (!compare_pnp_id(dev->id, f->id))
	461	continue;
2f53432c	462	pnp_dbg(&dev->dev, "%s: calling %pF\n", f->id,
668b21de	463	f->quirk_function);
726a7a3d	464	f->quirk_function(dev);
1da177e4 LT	465	}
1da177e4 LT	466	}