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9a58a333 SD |
1 | /* |
2 | * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism | |
3 | * | |
4 | * (C) Copyright 2008-2010 Intel Corporation | |
5 | * Author: Sreedhara DS (sreedhara.ds@intel.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
c8440336 | 12 | * SCU running in ARC processor communicates with other entity running in IA |
9a58a333 SD |
13 | * core through IPC mechanism which in turn messaging between IA core ad SCU. |
14 | * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and | |
15 | * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with | |
16 | * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC) | |
17 | * along with other APIs. | |
18 | */ | |
19 | #include <linux/delay.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/init.h> | |
edbaa603 | 22 | #include <linux/device.h> |
9a58a333 SD |
23 | #include <linux/pm.h> |
24 | #include <linux/pci.h> | |
25 | #include <linux/interrupt.h> | |
209009b2 | 26 | #include <linux/sfi.h> |
7c52d551 | 27 | #include <linux/module.h> |
05454c26 | 28 | #include <asm/intel-mid.h> |
9a58a333 SD |
29 | #include <asm/intel_scu_ipc.h> |
30 | ||
31 | /* IPC defines the following message types */ | |
32 | #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */ | |
33 | #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */ | |
34 | #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */ | |
35 | #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */ | |
36 | #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */ | |
37 | ||
38 | /* Command id associated with message IPCMSG_PCNTRL */ | |
39 | #define IPC_CMD_PCNTRL_W 0 /* Register write */ | |
40 | #define IPC_CMD_PCNTRL_R 1 /* Register read */ | |
41 | #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */ | |
42 | ||
9a58a333 SD |
43 | /* |
44 | * IPC register summary | |
45 | * | |
46 | * IPC register blocks are memory mapped at fixed address of 0xFF11C000 | |
47 | * To read or write information to the SCU, driver writes to IPC-1 memory | |
48 | * mapped registers (base address 0xFF11C000). The following is the IPC | |
49 | * mechanism | |
50 | * | |
51 | * 1. IA core cDMI interface claims this transaction and converts it to a | |
52 | * Transaction Layer Packet (TLP) message which is sent across the cDMI. | |
53 | * | |
54 | * 2. South Complex cDMI block receives this message and writes it to | |
55 | * the IPC-1 register block, causing an interrupt to the SCU | |
56 | * | |
57 | * 3. SCU firmware decodes this interrupt and IPC message and the appropriate | |
58 | * message handler is called within firmware. | |
59 | */ | |
60 | ||
51cd525d AV |
61 | #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */ |
62 | #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */ | |
ed12f295 | 63 | #define IPC_IOC 0x100 /* IPC command register IOC bit */ |
e97a1c98 | 64 | |
e97a1c98 KS |
65 | /* intel scu ipc driver data*/ |
66 | struct intel_scu_ipc_pdata_t { | |
67 | u32 ipc_base; | |
68 | u32 i2c_base; | |
69 | u32 ipc_len; | |
70 | u32 i2c_len; | |
ed12f295 | 71 | u8 irq_mode; |
e97a1c98 KS |
72 | }; |
73 | ||
694e523c DC |
74 | static struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = { |
75 | .ipc_base = 0xff11c000, | |
76 | .i2c_base = 0xff12b000, | |
77 | .ipc_len = 0x100, | |
78 | .i2c_len = 0x10, | |
79 | .irq_mode = 0, | |
80 | }; | |
81 | ||
82 | /* Penwell and Cloverview */ | |
83 | static struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = { | |
84 | .ipc_base = 0xff11c000, | |
85 | .i2c_base = 0xff12b000, | |
86 | .ipc_len = 0x100, | |
87 | .i2c_len = 0x10, | |
88 | .irq_mode = 1, | |
89 | }; | |
90 | ||
91 | static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = { | |
92 | .ipc_base = 0xff009000, | |
93 | .i2c_base = 0xff00d000, | |
94 | .ipc_len = 0x100, | |
95 | .i2c_len = 0x10, | |
96 | .irq_mode = 0, | |
e97a1c98 | 97 | }; |
9a58a333 SD |
98 | |
99 | static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id); | |
100 | static void ipc_remove(struct pci_dev *pdev); | |
101 | ||
102 | struct intel_scu_ipc_dev { | |
103 | struct pci_dev *pdev; | |
104 | void __iomem *ipc_base; | |
105 | void __iomem *i2c_base; | |
ed12f295 KS |
106 | struct completion cmd_complete; |
107 | u8 irq_mode; | |
9a58a333 SD |
108 | }; |
109 | ||
110 | static struct intel_scu_ipc_dev ipcdev; /* Only one for now */ | |
111 | ||
14d10f0a | 112 | static int platform; /* Platform type */ |
9a58a333 SD |
113 | |
114 | /* | |
115 | * IPC Read Buffer (Read Only): | |
116 | * 16 byte buffer for receiving data from SCU, if IPC command | |
117 | * processing results in response data | |
118 | */ | |
119 | #define IPC_READ_BUFFER 0x90 | |
120 | ||
121 | #define IPC_I2C_CNTRL_ADDR 0 | |
122 | #define I2C_DATA_ADDR 0x04 | |
123 | ||
124 | static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */ | |
125 | ||
126 | /* | |
127 | * Command Register (Write Only): | |
128 | * A write to this register results in an interrupt to the SCU core processor | |
129 | * Format: | |
130 | * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)| | |
131 | */ | |
132 | static inline void ipc_command(u32 cmd) /* Send ipc command */ | |
133 | { | |
ed12f295 KS |
134 | if (ipcdev.irq_mode) { |
135 | reinit_completion(&ipcdev.cmd_complete); | |
136 | writel(cmd | IPC_IOC, ipcdev.ipc_base); | |
137 | } | |
9a58a333 SD |
138 | writel(cmd, ipcdev.ipc_base); |
139 | } | |
140 | ||
141 | /* | |
142 | * IPC Write Buffer (Write Only): | |
143 | * 16-byte buffer for sending data associated with IPC command to | |
144 | * SCU. Size of the data is specified in the IPC_COMMAND_REG register | |
145 | */ | |
146 | static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */ | |
147 | { | |
148 | writel(data, ipcdev.ipc_base + 0x80 + offset); | |
149 | } | |
150 | ||
9a58a333 SD |
151 | /* |
152 | * Status Register (Read Only): | |
153 | * Driver will read this register to get the ready/busy status of the IPC | |
154 | * block and error status of the IPC command that was just processed by SCU | |
155 | * Format: | |
156 | * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)| | |
157 | */ | |
158 | ||
159 | static inline u8 ipc_read_status(void) | |
160 | { | |
161 | return __raw_readl(ipcdev.ipc_base + 0x04); | |
162 | } | |
163 | ||
164 | static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */ | |
165 | { | |
166 | return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
167 | } | |
168 | ||
e3359fd5 | 169 | static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */ |
9a58a333 SD |
170 | { |
171 | return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
172 | } | |
173 | ||
174 | static inline int busy_loop(void) /* Wait till scu status is busy */ | |
175 | { | |
176 | u32 status = 0; | |
177 | u32 loop_count = 0; | |
178 | ||
179 | status = ipc_read_status(); | |
180 | while (status & 1) { | |
181 | udelay(1); /* scu processing time is in few u secods */ | |
182 | status = ipc_read_status(); | |
183 | loop_count++; | |
184 | /* break if scu doesn't reset busy bit after huge retry */ | |
185 | if (loop_count > 100000) { | |
186 | dev_err(&ipcdev.pdev->dev, "IPC timed out"); | |
187 | return -ETIMEDOUT; | |
188 | } | |
189 | } | |
77e01d6d HL |
190 | if ((status >> 1) & 1) |
191 | return -EIO; | |
192 | ||
193 | return 0; | |
9a58a333 SD |
194 | } |
195 | ||
ed12f295 KS |
196 | /* Wait till ipc ioc interrupt is received or timeout in 3 HZ */ |
197 | static inline int ipc_wait_for_interrupt(void) | |
198 | { | |
199 | int status; | |
200 | ||
201 | if (!wait_for_completion_timeout(&ipcdev.cmd_complete, 3 * HZ)) { | |
202 | struct device *dev = &ipcdev.pdev->dev; | |
203 | dev_err(dev, "IPC timed out\n"); | |
204 | return -ETIMEDOUT; | |
205 | } | |
206 | ||
207 | status = ipc_read_status(); | |
208 | ||
209 | if ((status >> 1) & 1) | |
210 | return -EIO; | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | int intel_scu_ipc_check_status(void) | |
216 | { | |
217 | return ipcdev.irq_mode ? ipc_wait_for_interrupt() : busy_loop(); | |
218 | } | |
219 | ||
9a58a333 SD |
220 | /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */ |
221 | static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id) | |
222 | { | |
4707375f | 223 | int nc; |
9a58a333 | 224 | u32 offset = 0; |
ecb5646c | 225 | int err; |
e3359fd5 | 226 | u8 cbuf[IPC_WWBUF_SIZE] = { }; |
9a58a333 SD |
227 | u32 *wbuf = (u32 *)&cbuf; |
228 | ||
229 | mutex_lock(&ipclock); | |
e3359fd5 | 230 | |
ed6f2b4d AV |
231 | memset(cbuf, 0, sizeof(cbuf)); |
232 | ||
9a58a333 SD |
233 | if (ipcdev.pdev == NULL) { |
234 | mutex_unlock(&ipclock); | |
235 | return -ENODEV; | |
236 | } | |
237 | ||
4707375f AC |
238 | for (nc = 0; nc < count; nc++, offset += 2) { |
239 | cbuf[offset] = addr[nc]; | |
240 | cbuf[offset + 1] = addr[nc] >> 8; | |
241 | } | |
9a58a333 | 242 | |
4707375f AC |
243 | if (id == IPC_CMD_PCNTRL_R) { |
244 | for (nc = 0, offset = 0; nc < count; nc++, offset += 4) | |
245 | ipc_data_writel(wbuf[nc], offset); | |
246 | ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op); | |
247 | } else if (id == IPC_CMD_PCNTRL_W) { | |
248 | for (nc = 0; nc < count; nc++, offset += 1) | |
249 | cbuf[offset] = data[nc]; | |
250 | for (nc = 0, offset = 0; nc < count; nc++, offset += 4) | |
251 | ipc_data_writel(wbuf[nc], offset); | |
252 | ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op); | |
253 | } else if (id == IPC_CMD_PCNTRL_M) { | |
254 | cbuf[offset] = data[0]; | |
255 | cbuf[offset + 1] = data[1]; | |
256 | ipc_data_writel(wbuf[0], 0); /* Write wbuff */ | |
257 | ipc_command(4 << 16 | id << 12 | 0 << 8 | op); | |
e3359fd5 | 258 | } |
9a58a333 | 259 | |
ed12f295 | 260 | err = intel_scu_ipc_check_status(); |
c7094d1d | 261 | if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */ |
9a58a333 | 262 | /* Workaround: values are read as 0 without memcpy_fromio */ |
e3359fd5 | 263 | memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16); |
4707375f AC |
264 | for (nc = 0; nc < count; nc++) |
265 | data[nc] = ipc_data_readb(nc); | |
9a58a333 SD |
266 | } |
267 | mutex_unlock(&ipclock); | |
268 | return err; | |
269 | } | |
270 | ||
271 | /** | |
272 | * intel_scu_ipc_ioread8 - read a word via the SCU | |
273 | * @addr: register on SCU | |
274 | * @data: return pointer for read byte | |
275 | * | |
276 | * Read a single register. Returns 0 on success or an error code. All | |
277 | * locking between SCU accesses is handled for the caller. | |
278 | * | |
279 | * This function may sleep. | |
280 | */ | |
281 | int intel_scu_ipc_ioread8(u16 addr, u8 *data) | |
282 | { | |
283 | return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
284 | } | |
285 | EXPORT_SYMBOL(intel_scu_ipc_ioread8); | |
286 | ||
287 | /** | |
288 | * intel_scu_ipc_ioread16 - read a word via the SCU | |
289 | * @addr: register on SCU | |
290 | * @data: return pointer for read word | |
291 | * | |
292 | * Read a register pair. Returns 0 on success or an error code. All | |
293 | * locking between SCU accesses is handled for the caller. | |
294 | * | |
295 | * This function may sleep. | |
296 | */ | |
297 | int intel_scu_ipc_ioread16(u16 addr, u16 *data) | |
298 | { | |
299 | u16 x[2] = {addr, addr + 1 }; | |
300 | return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
301 | } | |
302 | EXPORT_SYMBOL(intel_scu_ipc_ioread16); | |
303 | ||
304 | /** | |
305 | * intel_scu_ipc_ioread32 - read a dword via the SCU | |
306 | * @addr: register on SCU | |
307 | * @data: return pointer for read dword | |
308 | * | |
309 | * Read four registers. Returns 0 on success or an error code. All | |
310 | * locking between SCU accesses is handled for the caller. | |
311 | * | |
312 | * This function may sleep. | |
313 | */ | |
314 | int intel_scu_ipc_ioread32(u16 addr, u32 *data) | |
315 | { | |
316 | u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; | |
317 | return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
318 | } | |
319 | EXPORT_SYMBOL(intel_scu_ipc_ioread32); | |
320 | ||
321 | /** | |
322 | * intel_scu_ipc_iowrite8 - write a byte via the SCU | |
323 | * @addr: register on SCU | |
324 | * @data: byte to write | |
325 | * | |
326 | * Write a single register. Returns 0 on success or an error code. All | |
327 | * locking between SCU accesses is handled for the caller. | |
328 | * | |
329 | * This function may sleep. | |
330 | */ | |
331 | int intel_scu_ipc_iowrite8(u16 addr, u8 data) | |
332 | { | |
333 | return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
334 | } | |
335 | EXPORT_SYMBOL(intel_scu_ipc_iowrite8); | |
336 | ||
337 | /** | |
338 | * intel_scu_ipc_iowrite16 - write a word via the SCU | |
339 | * @addr: register on SCU | |
340 | * @data: word to write | |
341 | * | |
342 | * Write two registers. Returns 0 on success or an error code. All | |
343 | * locking between SCU accesses is handled for the caller. | |
344 | * | |
345 | * This function may sleep. | |
346 | */ | |
347 | int intel_scu_ipc_iowrite16(u16 addr, u16 data) | |
348 | { | |
349 | u16 x[2] = {addr, addr + 1 }; | |
350 | return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
351 | } | |
352 | EXPORT_SYMBOL(intel_scu_ipc_iowrite16); | |
353 | ||
354 | /** | |
355 | * intel_scu_ipc_iowrite32 - write a dword via the SCU | |
356 | * @addr: register on SCU | |
357 | * @data: dword to write | |
358 | * | |
359 | * Write four registers. Returns 0 on success or an error code. All | |
360 | * locking between SCU accesses is handled for the caller. | |
361 | * | |
362 | * This function may sleep. | |
363 | */ | |
364 | int intel_scu_ipc_iowrite32(u16 addr, u32 data) | |
365 | { | |
366 | u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; | |
367 | return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
368 | } | |
369 | EXPORT_SYMBOL(intel_scu_ipc_iowrite32); | |
370 | ||
371 | /** | |
372 | * intel_scu_ipc_readvv - read a set of registers | |
373 | * @addr: register list | |
374 | * @data: bytes to return | |
375 | * @len: length of array | |
376 | * | |
377 | * Read registers. Returns 0 on success or an error code. All | |
378 | * locking between SCU accesses is handled for the caller. | |
379 | * | |
380 | * The largest array length permitted by the hardware is 5 items. | |
381 | * | |
382 | * This function may sleep. | |
383 | */ | |
384 | int intel_scu_ipc_readv(u16 *addr, u8 *data, int len) | |
385 | { | |
386 | return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
387 | } | |
388 | EXPORT_SYMBOL(intel_scu_ipc_readv); | |
389 | ||
390 | /** | |
391 | * intel_scu_ipc_writev - write a set of registers | |
392 | * @addr: register list | |
393 | * @data: bytes to write | |
394 | * @len: length of array | |
395 | * | |
396 | * Write registers. Returns 0 on success or an error code. All | |
397 | * locking between SCU accesses is handled for the caller. | |
398 | * | |
399 | * The largest array length permitted by the hardware is 5 items. | |
400 | * | |
401 | * This function may sleep. | |
402 | * | |
403 | */ | |
404 | int intel_scu_ipc_writev(u16 *addr, u8 *data, int len) | |
405 | { | |
406 | return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
407 | } | |
408 | EXPORT_SYMBOL(intel_scu_ipc_writev); | |
409 | ||
410 | ||
411 | /** | |
412 | * intel_scu_ipc_update_register - r/m/w a register | |
413 | * @addr: register address | |
414 | * @bits: bits to update | |
415 | * @mask: mask of bits to update | |
416 | * | |
417 | * Read-modify-write power control unit register. The first data argument | |
418 | * must be register value and second is mask value | |
419 | * mask is a bitmap that indicates which bits to update. | |
420 | * 0 = masked. Don't modify this bit, 1 = modify this bit. | |
421 | * returns 0 on success or an error code. | |
422 | * | |
423 | * This function may sleep. Locking between SCU accesses is handled | |
424 | * for the caller. | |
425 | */ | |
426 | int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask) | |
427 | { | |
428 | u8 data[2] = { bits, mask }; | |
429 | return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M); | |
430 | } | |
431 | EXPORT_SYMBOL(intel_scu_ipc_update_register); | |
432 | ||
9a58a333 SD |
433 | /** |
434 | * intel_scu_ipc_simple_command - send a simple command | |
435 | * @cmd: command | |
436 | * @sub: sub type | |
437 | * | |
438 | * Issue a simple command to the SCU. Do not use this interface if | |
439 | * you must then access data as any data values may be overwritten | |
440 | * by another SCU access by the time this function returns. | |
441 | * | |
442 | * This function may sleep. Locking for SCU accesses is handled for | |
443 | * the caller. | |
444 | */ | |
445 | int intel_scu_ipc_simple_command(int cmd, int sub) | |
446 | { | |
ecb5646c | 447 | int err; |
9a58a333 SD |
448 | |
449 | mutex_lock(&ipclock); | |
450 | if (ipcdev.pdev == NULL) { | |
451 | mutex_unlock(&ipclock); | |
452 | return -ENODEV; | |
453 | } | |
b4fd4f89 | 454 | ipc_command(sub << 12 | cmd); |
ed12f295 | 455 | err = intel_scu_ipc_check_status(); |
9a58a333 SD |
456 | mutex_unlock(&ipclock); |
457 | return err; | |
458 | } | |
459 | EXPORT_SYMBOL(intel_scu_ipc_simple_command); | |
460 | ||
461 | /** | |
462 | * intel_scu_ipc_command - command with data | |
463 | * @cmd: command | |
464 | * @sub: sub type | |
465 | * @in: input data | |
b4fd4f89 | 466 | * @inlen: input length in dwords |
9a58a333 | 467 | * @out: output data |
b4fd4f89 | 468 | * @outlein: output length in dwords |
9a58a333 SD |
469 | * |
470 | * Issue a command to the SCU which involves data transfers. Do the | |
471 | * data copies under the lock but leave it for the caller to interpret | |
472 | */ | |
473 | ||
474 | int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, | |
475 | u32 *out, int outlen) | |
476 | { | |
ecb5646c | 477 | int i, err; |
9a58a333 SD |
478 | |
479 | mutex_lock(&ipclock); | |
480 | if (ipcdev.pdev == NULL) { | |
481 | mutex_unlock(&ipclock); | |
482 | return -ENODEV; | |
483 | } | |
484 | ||
485 | for (i = 0; i < inlen; i++) | |
486 | ipc_data_writel(*in++, 4 * i); | |
487 | ||
5aa06930 | 488 | ipc_command((inlen << 16) | (sub << 12) | cmd); |
ed12f295 | 489 | err = intel_scu_ipc_check_status(); |
9a58a333 | 490 | |
c7094d1d KS |
491 | if (!err) { |
492 | for (i = 0; i < outlen; i++) | |
493 | *out++ = ipc_data_readl(4 * i); | |
494 | } | |
9a58a333 SD |
495 | |
496 | mutex_unlock(&ipclock); | |
497 | return err; | |
498 | } | |
499 | EXPORT_SYMBOL(intel_scu_ipc_command); | |
500 | ||
501 | /*I2C commands */ | |
502 | #define IPC_I2C_WRITE 1 /* I2C Write command */ | |
503 | #define IPC_I2C_READ 2 /* I2C Read command */ | |
504 | ||
505 | /** | |
506 | * intel_scu_ipc_i2c_cntrl - I2C read/write operations | |
507 | * @addr: I2C address + command bits | |
508 | * @data: data to read/write | |
509 | * | |
510 | * Perform an an I2C read/write operation via the SCU. All locking is | |
511 | * handled for the caller. This function may sleep. | |
512 | * | |
513 | * Returns an error code or 0 on success. | |
514 | * | |
515 | * This has to be in the IPC driver for the locking. | |
516 | */ | |
517 | int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data) | |
518 | { | |
519 | u32 cmd = 0; | |
520 | ||
521 | mutex_lock(&ipclock); | |
b4fd4f89 SD |
522 | if (ipcdev.pdev == NULL) { |
523 | mutex_unlock(&ipclock); | |
524 | return -ENODEV; | |
525 | } | |
9a58a333 SD |
526 | cmd = (addr >> 24) & 0xFF; |
527 | if (cmd == IPC_I2C_READ) { | |
528 | writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); | |
529 | /* Write not getting updated without delay */ | |
530 | mdelay(1); | |
531 | *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR); | |
532 | } else if (cmd == IPC_I2C_WRITE) { | |
32e2f63b | 533 | writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR); |
9a58a333 SD |
534 | mdelay(1); |
535 | writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); | |
536 | } else { | |
537 | dev_err(&ipcdev.pdev->dev, | |
538 | "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd); | |
539 | ||
540 | mutex_unlock(&ipclock); | |
5369c02d | 541 | return -EIO; |
9a58a333 SD |
542 | } |
543 | mutex_unlock(&ipclock); | |
544 | return 0; | |
545 | } | |
546 | EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl); | |
547 | ||
9a58a333 SD |
548 | /* |
549 | * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1 | |
550 | * When ioc bit is set to 1, caller api must wait for interrupt handler called | |
551 | * which in turn unlocks the caller api. Currently this is not used | |
552 | * | |
553 | * This is edge triggered so we need take no action to clear anything | |
554 | */ | |
555 | static irqreturn_t ioc(int irq, void *dev_id) | |
556 | { | |
ed12f295 KS |
557 | if (ipcdev.irq_mode) |
558 | complete(&ipcdev.cmd_complete); | |
559 | ||
9a58a333 SD |
560 | return IRQ_HANDLED; |
561 | } | |
562 | ||
563 | /** | |
564 | * ipc_probe - probe an Intel SCU IPC | |
565 | * @dev: the PCI device matching | |
566 | * @id: entry in the match table | |
567 | * | |
568 | * Enable and install an intel SCU IPC. This appears in the PCI space | |
569 | * but uses some hard coded addresses as well. | |
570 | */ | |
571 | static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
572 | { | |
694e523c | 573 | int err; |
e97a1c98 | 574 | struct intel_scu_ipc_pdata_t *pdata; |
9a58a333 SD |
575 | resource_size_t pci_resource; |
576 | ||
577 | if (ipcdev.pdev) /* We support only one SCU */ | |
578 | return -EBUSY; | |
579 | ||
694e523c | 580 | pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data; |
e97a1c98 | 581 | |
9a58a333 | 582 | ipcdev.pdev = pci_dev_get(dev); |
ed12f295 | 583 | ipcdev.irq_mode = pdata->irq_mode; |
9a58a333 SD |
584 | |
585 | err = pci_enable_device(dev); | |
586 | if (err) | |
587 | return err; | |
588 | ||
589 | err = pci_request_regions(dev, "intel_scu_ipc"); | |
590 | if (err) | |
591 | return err; | |
592 | ||
593 | pci_resource = pci_resource_start(dev, 0); | |
594 | if (!pci_resource) | |
595 | return -ENOMEM; | |
596 | ||
ed12f295 KS |
597 | init_completion(&ipcdev.cmd_complete); |
598 | ||
9a58a333 SD |
599 | if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev)) |
600 | return -EBUSY; | |
601 | ||
e97a1c98 | 602 | ipcdev.ipc_base = ioremap_nocache(pdata->ipc_base, pdata->ipc_len); |
9a58a333 SD |
603 | if (!ipcdev.ipc_base) |
604 | return -ENOMEM; | |
605 | ||
e97a1c98 | 606 | ipcdev.i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len); |
9a58a333 SD |
607 | if (!ipcdev.i2c_base) { |
608 | iounmap(ipcdev.ipc_base); | |
609 | return -ENOMEM; | |
610 | } | |
1da4b1c6 FT |
611 | |
612 | intel_scu_devices_create(); | |
613 | ||
9a58a333 SD |
614 | return 0; |
615 | } | |
616 | ||
617 | /** | |
618 | * ipc_remove - remove a bound IPC device | |
619 | * @pdev: PCI device | |
620 | * | |
621 | * In practice the SCU is not removable but this function is also | |
622 | * called for each device on a module unload or cleanup which is the | |
623 | * path that will get used. | |
624 | * | |
625 | * Free up the mappings and release the PCI resources | |
626 | */ | |
627 | static void ipc_remove(struct pci_dev *pdev) | |
628 | { | |
629 | free_irq(pdev->irq, &ipcdev); | |
630 | pci_release_regions(pdev); | |
631 | pci_dev_put(ipcdev.pdev); | |
632 | iounmap(ipcdev.ipc_base); | |
633 | iounmap(ipcdev.i2c_base); | |
634 | ipcdev.pdev = NULL; | |
1da4b1c6 | 635 | intel_scu_devices_destroy(); |
9a58a333 SD |
636 | } |
637 | ||
daa77696 | 638 | static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { |
694e523c DC |
639 | { |
640 | PCI_VDEVICE(INTEL, 0x082a), | |
641 | (kernel_ulong_t)&intel_scu_ipc_lincroft_pdata, | |
642 | }, { | |
643 | PCI_VDEVICE(INTEL, 0x080e), | |
644 | (kernel_ulong_t)&intel_scu_ipc_penwell_pdata, | |
645 | }, { | |
646 | PCI_VDEVICE(INTEL, 0x08ea), | |
647 | (kernel_ulong_t)&intel_scu_ipc_penwell_pdata, | |
648 | }, { | |
649 | PCI_VDEVICE(INTEL, 0x11a0), | |
650 | (kernel_ulong_t)&intel_scu_ipc_tangier_pdata, | |
651 | }, { | |
652 | 0, | |
653 | } | |
9a58a333 SD |
654 | }; |
655 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
656 | ||
657 | static struct pci_driver ipc_driver = { | |
658 | .name = "intel_scu_ipc", | |
659 | .id_table = pci_ids, | |
660 | .probe = ipc_probe, | |
661 | .remove = ipc_remove, | |
662 | }; | |
663 | ||
664 | ||
665 | static int __init intel_scu_ipc_init(void) | |
666 | { | |
712b6aa8 | 667 | platform = intel_mid_identify_cpu(); |
9dd3adeb AC |
668 | if (platform == 0) |
669 | return -ENODEV; | |
9a58a333 SD |
670 | return pci_register_driver(&ipc_driver); |
671 | } | |
672 | ||
673 | static void __exit intel_scu_ipc_exit(void) | |
674 | { | |
675 | pci_unregister_driver(&ipc_driver); | |
676 | } | |
677 | ||
678 | MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>"); | |
679 | MODULE_DESCRIPTION("Intel SCU IPC driver"); | |
680 | MODULE_LICENSE("GPL"); | |
681 | ||
682 | module_init(intel_scu_ipc_init); | |
683 | module_exit(intel_scu_ipc_exit); |