[linux-2.6-block.git] / drivers / pinctrl / sunxi / pinctrl-sunxi.h

/*
 * Allwinner A1X SoCs pinctrl driver.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __PINCTRL_SUNXI_H
#define __PINCTRL_SUNXI_H

#include <linux/kernel.h>
#include <linux/spinlock.h>

#define PA_BASE	0
#define PB_BASE	32
#define PC_BASE	64
#define PD_BASE	96
#define PE_BASE	128
#define PF_BASE	160
#define PG_BASE	192
#define PH_BASE	224
#define PI_BASE	256
#define PL_BASE	352
#define PM_BASE	384
#define PN_BASE	416

#define SUNXI_PINCTRL_PIN(bank, pin)		\
	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)

#define SUNXI_PIN_NAME_MAX_LEN	5

#define BANK_MEM_SIZE		0x24
#define MUX_REGS_OFFSET		0x0
#define MUX_FIELD_WIDTH		4
#define DATA_REGS_OFFSET	0x10
#define DATA_FIELD_WIDTH	1
#define DLEVEL_REGS_OFFSET	0x14
#define DLEVEL_FIELD_WIDTH	2
#define PULL_REGS_OFFSET	0x1c
#define PULL_FIELD_WIDTH	2

#define D1_BANK_MEM_SIZE	0x30
#define D1_DLEVEL_FIELD_WIDTH	4
#define D1_PULL_REGS_OFFSET	0x24

#define PINS_PER_BANK		32

#define IRQ_PER_BANK		32

#define IRQ_CFG_REG		0x200
#define IRQ_CFG_IRQ_PER_REG		8
#define IRQ_CFG_IRQ_BITS		4
#define IRQ_CFG_IRQ_MASK		((1 << IRQ_CFG_IRQ_BITS) - 1)
#define IRQ_CTRL_REG		0x210
#define IRQ_CTRL_IRQ_PER_REG		32
#define IRQ_CTRL_IRQ_BITS		1
#define IRQ_CTRL_IRQ_MASK		((1 << IRQ_CTRL_IRQ_BITS) - 1)
#define IRQ_STATUS_REG		0x214
#define IRQ_STATUS_IRQ_PER_REG		32
#define IRQ_STATUS_IRQ_BITS		1
#define IRQ_STATUS_IRQ_MASK		((1 << IRQ_STATUS_IRQ_BITS) - 1)

#define IRQ_DEBOUNCE_REG	0x218

#define IRQ_MEM_SIZE		0x20

#define IRQ_EDGE_RISING		0x00
#define IRQ_EDGE_FALLING	0x01
#define IRQ_LEVEL_HIGH		0x02
#define IRQ_LEVEL_LOW		0x03
#define IRQ_EDGE_BOTH		0x04

#define GRP_CFG_REG		0x300

#define IO_BIAS_MASK		GENMASK(3, 0)

#define SUN4I_FUNC_INPUT	0
#define SUN4I_FUNC_IRQ		6

#define PINCTRL_SUN5I_A10S	BIT(1)
#define PINCTRL_SUN5I_A13	BIT(2)
#define PINCTRL_SUN5I_GR8	BIT(3)
#define PINCTRL_SUN6I_A31	BIT(4)
#define PINCTRL_SUN6I_A31S	BIT(5)
#define PINCTRL_SUN4I_A10	BIT(6)
#define PINCTRL_SUN7I_A20	BIT(7)
#define PINCTRL_SUN8I_R40	BIT(8)
#define PINCTRL_SUN8I_V3	BIT(9)
#define PINCTRL_SUN8I_V3S	BIT(10)
/* Variants below here have an updated register layout. */
#define PINCTRL_SUN20I_D1	BIT(11)

#define PIO_POW_MOD_SEL_REG	0x340
#define PIO_POW_MOD_CTL_REG	0x344

enum sunxi_desc_bias_voltage {
	BIAS_VOLTAGE_NONE,
	/*
	 * Bias voltage configuration is done through
	 * Pn_GRP_CONFIG registers, as seen on A80 SoC.
	 */
	BIAS_VOLTAGE_GRP_CONFIG,
	/*
	 * Bias voltage is set through PIO_POW_MOD_SEL_REG
	 * register, as seen on H6 SoC, for example.
	 */
	BIAS_VOLTAGE_PIO_POW_MODE_SEL,
	/*
	 * Bias voltage is set through PIO_POW_MOD_SEL_REG
	 * and PIO_POW_MOD_CTL_REG register, as seen on
	 * A100 and D1 SoC, for example.
	 */
	BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};

struct sunxi_desc_function {
	unsigned long	variant;
	const char	*name;
	u8		muxval;
	u8		irqbank;
	u8		irqnum;
};

struct sunxi_desc_pin {
	struct pinctrl_pin_desc		pin;
	unsigned long			variant;
	struct sunxi_desc_function	*functions;
};

struct sunxi_pinctrl_desc {
	const struct sunxi_desc_pin	*pins;
	int				npins;
	unsigned			pin_base;
	unsigned			irq_banks;
	const unsigned int		*irq_bank_map;
	bool				irq_read_needs_mux;
	bool				disable_strict_mode;
	enum sunxi_desc_bias_voltage	io_bias_cfg_variant;
};

struct sunxi_pinctrl_function {
	const char	*name;
	const char	**groups;
	unsigned	ngroups;
};

struct sunxi_pinctrl_group {
	const char	*name;
	unsigned	pin;
};

struct sunxi_pinctrl_regulator {
	struct regulator	*regulator;
	refcount_t		refcount;
};

struct sunxi_pinctrl {
	void __iomem			*membase;
	struct gpio_chip		*chip;
	const struct sunxi_pinctrl_desc	*desc;
	struct device			*dev;
	struct sunxi_pinctrl_regulator	regulators[9];
	struct irq_domain		*domain;
	struct sunxi_pinctrl_function	*functions;
	unsigned			nfunctions;
	struct sunxi_pinctrl_group	*groups;
	unsigned			ngroups;
	int				*irq;
	unsigned			*irq_array;
	raw_spinlock_t			lock;
	struct pinctrl_dev		*pctl_dev;
	unsigned long			variant;
	u32				bank_mem_size;
	u32				pull_regs_offset;
	u32				dlevel_field_width;
};

#define SUNXI_PIN(_pin, ...)					\
	{							\
		.pin = _pin,					\
		.functions = (struct sunxi_desc_function[]){	\
			__VA_ARGS__, { } },			\
	}

#define SUNXI_PIN_VARIANT(_pin, _variant, ...)			\
	{							\
		.pin = _pin,					\
		.variant = _variant,				\
		.functions = (struct sunxi_desc_function[]){	\
			__VA_ARGS__, { } },			\
	}

#define SUNXI_FUNCTION(_val, _name)				\
	{							\
		.name = _name,					\
		.muxval = _val,					\
	}

#define SUNXI_FUNCTION_VARIANT(_val, _name, _variant)		\
	{							\
		.name = _name,					\
		.muxval = _val,					\
		.variant = _variant,				\
	}

#define SUNXI_FUNCTION_IRQ(_val, _irq)				\
	{							\
		.name = "irq",					\
		.muxval = _val,					\
		.irqnum = _irq,					\
	}

#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq)		\
	{							\
		.name = "irq",					\
		.muxval = _val,					\
		.irqbank = _bank,				\
		.irqnum = _irq,					\
	}

static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	if (!desc->irq_bank_map)
		return bank;
	else
		return desc->irq_bank_map[bank];
}

static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
				    u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;
	u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;

	return IRQ_CFG_REG +
	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
}

static inline u32 sunxi_irq_cfg_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
	return irq_num * IRQ_CFG_IRQ_BITS;
}

static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
				     u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;

	return sunxi_irq_ctrl_reg_from_bank(desc, bank);
}

static inline u32 sunxi_irq_ctrl_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
	return irq_num * IRQ_CTRL_IRQ_BITS;
}

static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	return IRQ_DEBOUNCE_REG +
	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	return IRQ_STATUS_REG +
	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
				       u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;

	return sunxi_irq_status_reg_from_bank(desc, bank);
}

static inline u32 sunxi_irq_status_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
	return irq_num * IRQ_STATUS_IRQ_BITS;
}

static inline u32 sunxi_grp_config_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;

	return GRP_CFG_REG + bank * 0x4;
}

int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
				    const struct sunxi_pinctrl_desc *desc,
				    unsigned long variant);

#define sunxi_pinctrl_init(_dev, _desc) \
	sunxi_pinctrl_init_with_variant(_dev, _desc, 0)

#endif /* __PINCTRL_SUNXI_H */
Commit	Line	Data
0e37f88d MR	1	/*
	2	* Allwinner A1X SoCs pinctrl driver.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#ifndef __PINCTRL_SUNXI_H
	14	#define __PINCTRL_SUNXI_H
	15
	16	#include <linux/kernel.h>
1bee963d	17	#include <linux/spinlock.h>
0e37f88d MR	18
	19	#define PA_BASE 0
	20	#define PB_BASE 32
	21	#define PC_BASE 64
	22	#define PD_BASE 96
	23	#define PE_BASE 128
	24	#define PF_BASE 160
	25	#define PG_BASE 192
9f5b6b30 MR	26	#define PH_BASE 224
9f5b6b30 MR	27	#define PI_BASE 256
0aba6178 BB	28	#define PL_BASE 352
0aba6178 BB	29	#define PM_BASE 384
4f6bd5cf	30	#define PN_BASE 416
0e37f88d	31
d10acc63 MR	32	#define SUNXI_PINCTRL_PIN(bank, pin) \
d10acc63 MR	33	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
0aba6178	34
08e9e614 MR	35	#define SUNXI_PIN_NAME_MAX_LEN 5
08e9e614 MR	36
0e37f88d MR	37	#define BANK_MEM_SIZE 0x24
0e37f88d MR	38	#define MUX_REGS_OFFSET 0x0
0bb95ae2	39	#define MUX_FIELD_WIDTH 4
08e9e614	40	#define DATA_REGS_OFFSET 0x10
0bb95ae2	41	#define DATA_FIELD_WIDTH 1
0e37f88d	42	#define DLEVEL_REGS_OFFSET 0x14
0bb95ae2	43	#define DLEVEL_FIELD_WIDTH 2
0e37f88d	44	#define PULL_REGS_OFFSET 0x1c
0bb95ae2	45	#define PULL_FIELD_WIDTH 2
0e37f88d	46
0569af48 SH	47	#define D1_BANK_MEM_SIZE 0x30
	48	#define D1_DLEVEL_FIELD_WIDTH 4
	49	#define D1_PULL_REGS_OFFSET 0x24
	50
0e37f88d	51	#define PINS_PER_BANK 32
0e37f88d	52
aebdc8ab	53	#define IRQ_PER_BANK 32
60242db1 MR	54
	55	#define IRQ_CFG_REG 0x200
	56	#define IRQ_CFG_IRQ_PER_REG 8
	57	#define IRQ_CFG_IRQ_BITS 4
	58	#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
	59	#define IRQ_CTRL_REG 0x210
	60	#define IRQ_CTRL_IRQ_PER_REG 32
	61	#define IRQ_CTRL_IRQ_BITS 1
	62	#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
	63	#define IRQ_STATUS_REG 0x214
	64	#define IRQ_STATUS_IRQ_PER_REG 32
	65	#define IRQ_STATUS_IRQ_BITS 1
	66	#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
	67
7c926492 MR	68	#define IRQ_DEBOUNCE_REG 0x218
7c926492 MR	69
aebdc8ab MR	70	#define IRQ_MEM_SIZE 0x20
aebdc8ab MR	71
60242db1 MR	72	#define IRQ_EDGE_RISING 0x00
	73	#define IRQ_EDGE_FALLING 0x01
	74	#define IRQ_LEVEL_HIGH 0x02
	75	#define IRQ_LEVEL_LOW 0x03
	76	#define IRQ_EDGE_BOTH 0x04
	77
402bfb3c CYT	78	#define GRP_CFG_REG 0x300
	79
	80	#define IO_BIAS_MASK GENMASK(3, 0)
	81
ef6d24cc HG	82	#define SUN4I_FUNC_INPUT 0
	83	#define SUN4I_FUNC_IRQ 6
	84
858f559f MR	85	#define PINCTRL_SUN5I_A10S BIT(1)
	86	#define PINCTRL_SUN5I_A13 BIT(2)
	87	#define PINCTRL_SUN5I_GR8 BIT(3)
4924982e CYT	88	#define PINCTRL_SUN6I_A31 BIT(4)
4924982e CYT	89	#define PINCTRL_SUN6I_A31S BIT(5)
88798ba2 IZ	90	#define PINCTRL_SUN4I_A10 BIT(6)
	91	#define PINCTRL_SUN7I_A20 BIT(7)
	92	#define PINCTRL_SUN8I_R40 BIT(8)
fb18f188 IZ	93	#define PINCTRL_SUN8I_V3 BIT(9)
fb18f188 IZ	94	#define PINCTRL_SUN8I_V3S BIT(10)
0569af48 SH	95	/* Variants below here have an updated register layout. */
0569af48 SH	96	#define PINCTRL_SUN20I_D1 BIT(11)
858f559f	97
cc62383f	98	#define PIO_POW_MOD_SEL_REG 0x340
88df36f2	99	#define PIO_POW_MOD_CTL_REG 0x344
cc62383f	100
f7275345 OJ	101	enum sunxi_desc_bias_voltage {
	102	BIAS_VOLTAGE_NONE,
	103	/*
	104	* Bias voltage configuration is done through
	105	* Pn_GRP_CONFIG registers, as seen on A80 SoC.
	106	*/
	107	BIAS_VOLTAGE_GRP_CONFIG,
cc62383f OJ	108	/*
	109	* Bias voltage is set through PIO_POW_MOD_SEL_REG
	110	* register, as seen on H6 SoC, for example.
	111	*/
	112	BIAS_VOLTAGE_PIO_POW_MODE_SEL,
88df36f2 SH	113	/*
	114	* Bias voltage is set through PIO_POW_MOD_SEL_REG
	115	* and PIO_POW_MOD_CTL_REG register, as seen on
	116	* A100 and D1 SoC, for example.
	117	*/
	118	BIAS_VOLTAGE_PIO_POW_MODE_CTL,
f7275345 OJ	119	};
f7275345 OJ	120
0e37f88d	121	struct sunxi_desc_function {
578db85f	122	unsigned long variant;
0e37f88d MR	123	const char *name;
0e37f88d MR	124	u8 muxval;
6e1c3023	125	u8 irqbank;
60242db1	126	u8 irqnum;
0e37f88d MR	127	};
	128
	129	struct sunxi_desc_pin {
	130	struct pinctrl_pin_desc pin;
578db85f	131	unsigned long variant;
0e37f88d MR	132	struct sunxi_desc_function *functions;
	133	};
	134
	135	struct sunxi_pinctrl_desc {
	136	const struct sunxi_desc_pin *pins;
	137	int npins;
d83c82ce	138	unsigned pin_base;
8966ada2	139	unsigned irq_banks;
35817d34	140	const unsigned int *irq_bank_map;
ef6d24cc	141	bool irq_read_needs_mux;
aae842a3	142	bool disable_strict_mode;
f7275345	143	enum sunxi_desc_bias_voltage io_bias_cfg_variant;
0e37f88d MR	144	};
	145
	146	struct sunxi_pinctrl_function {
	147	const char *name;
	148	const char **groups;
	149	unsigned ngroups;
	150	};
	151
	152	struct sunxi_pinctrl_group {
	153	const char *name;
0e37f88d MR	154	unsigned pin;
	155	};
	156
9a2a566a MR	157	struct sunxi_pinctrl_regulator {
	158	struct regulator *regulator;
	159	refcount_t refcount;
	160	};
	161
0e37f88d MR	162	struct sunxi_pinctrl {
0e37f88d MR	163	void __iomem *membase;
08e9e614	164	struct gpio_chip *chip;
d39bd845	165	const struct sunxi_pinctrl_desc *desc;
0e37f88d	166	struct device *dev;
ca443844	167	struct sunxi_pinctrl_regulator regulators[9];
60242db1	168	struct irq_domain *domain;
0e37f88d MR	169	struct sunxi_pinctrl_function *functions;
	170	unsigned nfunctions;
	171	struct sunxi_pinctrl_group *groups;
	172	unsigned ngroups;
aebdc8ab MR	173	int *irq;
aebdc8ab MR	174	unsigned *irq_array;
f658ed36	175	raw_spinlock_t lock;
0e37f88d	176	struct pinctrl_dev *pctl_dev;
578db85f	177	unsigned long variant;
622b681e SH	178	u32 bank_mem_size;
	179	u32 pull_regs_offset;
	180	u32 dlevel_field_width;
0e37f88d MR	181	};
	182
	183	#define SUNXI_PIN(_pin, ...) \
	184	{ \
	185	.pin = _pin, \
	186	.functions = (struct sunxi_desc_function[]){ \
	187	__VA_ARGS__, { } }, \
	188	}
	189
578db85f MR	190	#define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
	191	{ \
	192	.pin = _pin, \
	193	.variant = _variant, \
	194	.functions = (struct sunxi_desc_function[]){ \
	195	__VA_ARGS__, { } }, \
	196	}
	197
0e37f88d MR	198	#define SUNXI_FUNCTION(_val, _name) \
	199	{ \
	200	.name = _name, \
	201	.muxval = _val, \
	202	}
	203
578db85f MR	204	#define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
	205	{ \
	206	.name = _name, \
	207	.muxval = _val, \
	208	.variant = _variant, \
	209	}
	210
60242db1 MR	211	#define SUNXI_FUNCTION_IRQ(_val, _irq) \
	212	{ \
	213	.name = "irq", \
	214	.muxval = _val, \
	215	.irqnum = _irq, \
	216	}
	217
6e1c3023 MR	218	#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
	219	{ \
	220	.name = "irq", \
	221	.muxval = _val, \
	222	.irqbank = _bank, \
	223	.irqnum = _irq, \
	224	}
	225
29dfc6bb IZ	226	static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
29dfc6bb IZ	227	{
35817d34 IZ	228	if (!desc->irq_bank_map)
	229	return bank;
	230	else
	231	return desc->irq_bank_map[bank];
29dfc6bb IZ	232	}
29dfc6bb IZ	233
4b0d6c5a IZ	234	static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
4b0d6c5a IZ	235	u16 irq)
60242db1	236	{
aebdc8ab MR	237	u8 bank = irq / IRQ_PER_BANK;
	238	u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
	239
29dfc6bb IZ	240	return IRQ_CFG_REG +
29dfc6bb IZ	241	sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
60242db1 MR	242	}
	243
	244	static inline u32 sunxi_irq_cfg_offset(u16 irq)
	245	{
	246	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
	247	return irq_num * IRQ_CFG_IRQ_BITS;
	248	}
	249
4b0d6c5a	250	static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
aebdc8ab	251	{
29dfc6bb	252	return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
aebdc8ab MR	253	}
aebdc8ab MR	254
4b0d6c5a IZ	255	static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
4b0d6c5a IZ	256	u16 irq)
60242db1	257	{
aebdc8ab MR	258	u8 bank = irq / IRQ_PER_BANK;
aebdc8ab MR	259
4b0d6c5a	260	return sunxi_irq_ctrl_reg_from_bank(desc, bank);
60242db1 MR	261	}
	262
	263	static inline u32 sunxi_irq_ctrl_offset(u16 irq)
	264	{
	265	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
	266	return irq_num * IRQ_CTRL_IRQ_BITS;
	267	}
	268
4b0d6c5a	269	static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
7c926492	270	{
29dfc6bb IZ	271	return IRQ_DEBOUNCE_REG +
29dfc6bb IZ	272	sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
7c926492 MR	273	}
7c926492 MR	274
4b0d6c5a	275	static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
aebdc8ab	276	{
29dfc6bb IZ	277	return IRQ_STATUS_REG +
29dfc6bb IZ	278	sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
aebdc8ab MR	279	}
aebdc8ab MR	280
4b0d6c5a IZ	281	static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
4b0d6c5a IZ	282	u16 irq)
60242db1	283	{
aebdc8ab MR	284	u8 bank = irq / IRQ_PER_BANK;
aebdc8ab MR	285
4b0d6c5a	286	return sunxi_irq_status_reg_from_bank(desc, bank);
60242db1 MR	287	}
	288
	289	static inline u32 sunxi_irq_status_offset(u16 irq)
	290	{
	291	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
	292	return irq_num * IRQ_STATUS_IRQ_BITS;
	293	}
	294
402bfb3c CYT	295	static inline u32 sunxi_grp_config_reg(u16 pin)
	296	{
	297	u8 bank = pin / PINS_PER_BANK;
	298
	299	return GRP_CFG_REG + bank * 0x4;
	300	}
	301
578db85f MR	302	int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
	303	const struct sunxi_pinctrl_desc *desc,
	304	unsigned long variant);
	305
	306	#define sunxi_pinctrl_init(_dev, _desc) \
	307	sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
2284ba6b	308
0e37f88d	309	#endif /* __PINCTRL_SUNXI_H */