[linux-2.6-block.git] / drivers / pinctrl / sunxi / pinctrl-sunxi.h

/*
 * Allwinner A1X SoCs pinctrl driver.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __PINCTRL_SUNXI_H
#define __PINCTRL_SUNXI_H

#include <linux/kernel.h>
#include <linux/spinlock.h>

#define PA_BASE	0
#define PB_BASE	32
#define PC_BASE	64
#define PD_BASE	96
#define PE_BASE	128
#define PF_BASE	160
#define PG_BASE	192
#define PH_BASE	224
#define PI_BASE	256
#define PL_BASE	352
#define PM_BASE	384
#define PN_BASE	416

#define SUNXI_PINCTRL_PIN(bank, pin)		\
	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)

#define SUNXI_PIN_NAME_MAX_LEN	5

#define BANK_MEM_SIZE		0x24
#define MUX_REGS_OFFSET		0x0
#define DATA_REGS_OFFSET	0x10
#define DLEVEL_REGS_OFFSET	0x14
#define PULL_REGS_OFFSET	0x1c

#define PINS_PER_BANK		32
#define MUX_PINS_PER_REG	8
#define MUX_PINS_BITS		4
#define MUX_PINS_MASK		0x0f
#define DATA_PINS_PER_REG	32
#define DATA_PINS_BITS		1
#define DATA_PINS_MASK		0x01
#define DLEVEL_PINS_PER_REG	16
#define DLEVEL_PINS_BITS	2
#define DLEVEL_PINS_MASK	0x03
#define PULL_PINS_PER_REG	16
#define PULL_PINS_BITS		2
#define PULL_PINS_MASK		0x03

#define IRQ_PER_BANK		32

#define IRQ_CFG_REG		0x200
#define IRQ_CFG_IRQ_PER_REG		8
#define IRQ_CFG_IRQ_BITS		4
#define IRQ_CFG_IRQ_MASK		((1 << IRQ_CFG_IRQ_BITS) - 1)
#define IRQ_CTRL_REG		0x210
#define IRQ_CTRL_IRQ_PER_REG		32
#define IRQ_CTRL_IRQ_BITS		1
#define IRQ_CTRL_IRQ_MASK		((1 << IRQ_CTRL_IRQ_BITS) - 1)
#define IRQ_STATUS_REG		0x214
#define IRQ_STATUS_IRQ_PER_REG		32
#define IRQ_STATUS_IRQ_BITS		1
#define IRQ_STATUS_IRQ_MASK		((1 << IRQ_STATUS_IRQ_BITS) - 1)

#define IRQ_MEM_SIZE		0x20

#define IRQ_EDGE_RISING		0x00
#define IRQ_EDGE_FALLING	0x01
#define IRQ_LEVEL_HIGH		0x02
#define IRQ_LEVEL_LOW		0x03
#define IRQ_EDGE_BOTH		0x04

struct sunxi_desc_function {
	const char	*name;
	u8		muxval;
	u8		irqbank;
	u8		irqnum;
};

struct sunxi_desc_pin {
	struct pinctrl_pin_desc		pin;
	struct sunxi_desc_function	*functions;
};

struct sunxi_pinctrl_desc {
	const struct sunxi_desc_pin	*pins;
	int				npins;
	unsigned			pin_base;
	unsigned			irq_banks;
};

struct sunxi_pinctrl_function {
	const char	*name;
	const char	**groups;
	unsigned	ngroups;
};

struct sunxi_pinctrl_group {
	const char	*name;
	unsigned long	config;
	unsigned	pin;
};

struct sunxi_pinctrl {
	void __iomem			*membase;
	struct gpio_chip		*chip;
	const struct sunxi_pinctrl_desc	*desc;
	struct device			*dev;
	struct irq_domain		*domain;
	struct sunxi_pinctrl_function	*functions;
	unsigned			nfunctions;
	struct sunxi_pinctrl_group	*groups;
	unsigned			ngroups;
	int				*irq;
	unsigned			*irq_array;
	spinlock_t			lock;
	struct pinctrl_dev		*pctl_dev;
};

#define SUNXI_PIN(_pin, ...)					\
	{							\
		.pin = _pin,					\
		.functions = (struct sunxi_desc_function[]){	\
			__VA_ARGS__, { } },			\
	}

#define SUNXI_FUNCTION(_val, _name)				\
	{							\
		.name = _name,					\
		.muxval = _val,					\
	}

#define SUNXI_FUNCTION_IRQ(_val, _irq)				\
	{							\
		.name = "irq",					\
		.muxval = _val,					\
		.irqnum = _irq,					\
	}

#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq)		\
	{							\
		.name = "irq",					\
		.muxval = _val,					\
		.irqbank = _bank,				\
		.irqnum = _irq,					\
	}

/*
 * The sunXi PIO registers are organized as is:
 * 0x00 - 0x0c	Muxing values.
 *		8 pins per register, each pin having a 4bits value
 * 0x10		Pin values
 *		32 bits per register, each pin corresponding to one bit
 * 0x14 - 0x18	Drive level
 *		16 pins per register, each pin having a 2bits value
 * 0x1c - 0x20	Pull-Up values
 *		16 pins per register, each pin having a 2bits value
 *
 * This is for the first bank. Each bank will have the same layout,
 * with an offset being a multiple of 0x24.
 *
 * The following functions calculate from the pin number the register
 * and the bit offset that we should access.
 */
static inline u32 sunxi_mux_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += MUX_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_mux_offset(u16 pin)
{
	u32 pin_num = pin % MUX_PINS_PER_REG;
	return pin_num * MUX_PINS_BITS;
}

static inline u32 sunxi_data_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += DATA_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_data_offset(u16 pin)
{
	u32 pin_num = pin % DATA_PINS_PER_REG;
	return pin_num * DATA_PINS_BITS;
}

static inline u32 sunxi_dlevel_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += DLEVEL_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_dlevel_offset(u16 pin)
{
	u32 pin_num = pin % DLEVEL_PINS_PER_REG;
	return pin_num * DLEVEL_PINS_BITS;
}

static inline u32 sunxi_pull_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += PULL_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_pull_offset(u16 pin)
{
	u32 pin_num = pin % PULL_PINS_PER_REG;
	return pin_num * PULL_PINS_BITS;
}

static inline u32 sunxi_irq_cfg_reg(u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;
	u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;

	return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
}

static inline u32 sunxi_irq_cfg_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
	return irq_num * IRQ_CFG_IRQ_BITS;
}

static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
{
	return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_ctrl_reg(u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;

	return sunxi_irq_ctrl_reg_from_bank(bank);
}

static inline u32 sunxi_irq_ctrl_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
	return irq_num * IRQ_CTRL_IRQ_BITS;
}

static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
{
	return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_status_reg(u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;

	return sunxi_irq_status_reg_from_bank(bank);
}

static inline u32 sunxi_irq_status_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
	return irq_num * IRQ_STATUS_IRQ_BITS;
}

int sunxi_pinctrl_init(struct platform_device *pdev,
		       const struct sunxi_pinctrl_desc *desc);

#endif /* __PINCTRL_SUNXI_H */
Commit	Line	Data
0e37f88d MR	1	/*
	2	* Allwinner A1X SoCs pinctrl driver.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#ifndef __PINCTRL_SUNXI_H
	14	#define __PINCTRL_SUNXI_H
	15
	16	#include <linux/kernel.h>
1bee963d	17	#include <linux/spinlock.h>
0e37f88d MR	18
	19	#define PA_BASE 0
	20	#define PB_BASE 32
	21	#define PC_BASE 64
	22	#define PD_BASE 96
	23	#define PE_BASE 128
	24	#define PF_BASE 160
	25	#define PG_BASE 192
9f5b6b30 MR	26	#define PH_BASE 224
9f5b6b30 MR	27	#define PI_BASE 256
0aba6178 BB	28	#define PL_BASE 352
0aba6178 BB	29	#define PM_BASE 384
4f6bd5cf	30	#define PN_BASE 416
0e37f88d	31
d10acc63 MR	32	#define SUNXI_PINCTRL_PIN(bank, pin) \
d10acc63 MR	33	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
0aba6178	34
08e9e614 MR	35	#define SUNXI_PIN_NAME_MAX_LEN 5
08e9e614 MR	36
0e37f88d MR	37	#define BANK_MEM_SIZE 0x24
0e37f88d MR	38	#define MUX_REGS_OFFSET 0x0
08e9e614	39	#define DATA_REGS_OFFSET 0x10
0e37f88d MR	40	#define DLEVEL_REGS_OFFSET 0x14
	41	#define PULL_REGS_OFFSET 0x1c
	42
	43	#define PINS_PER_BANK 32
	44	#define MUX_PINS_PER_REG 8
	45	#define MUX_PINS_BITS 4
	46	#define MUX_PINS_MASK 0x0f
08e9e614 MR	47	#define DATA_PINS_PER_REG 32
	48	#define DATA_PINS_BITS 1
	49	#define DATA_PINS_MASK 0x01
0e37f88d MR	50	#define DLEVEL_PINS_PER_REG 16
	51	#define DLEVEL_PINS_BITS 2
	52	#define DLEVEL_PINS_MASK 0x03
	53	#define PULL_PINS_PER_REG 16
	54	#define PULL_PINS_BITS 2
	55	#define PULL_PINS_MASK 0x03
	56
aebdc8ab	57	#define IRQ_PER_BANK 32
60242db1 MR	58
	59	#define IRQ_CFG_REG 0x200
	60	#define IRQ_CFG_IRQ_PER_REG 8
	61	#define IRQ_CFG_IRQ_BITS 4
	62	#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
	63	#define IRQ_CTRL_REG 0x210
	64	#define IRQ_CTRL_IRQ_PER_REG 32
	65	#define IRQ_CTRL_IRQ_BITS 1
	66	#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
	67	#define IRQ_STATUS_REG 0x214
	68	#define IRQ_STATUS_IRQ_PER_REG 32
	69	#define IRQ_STATUS_IRQ_BITS 1
	70	#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
	71
aebdc8ab MR	72	#define IRQ_MEM_SIZE 0x20
aebdc8ab MR	73
60242db1 MR	74	#define IRQ_EDGE_RISING 0x00
	75	#define IRQ_EDGE_FALLING 0x01
	76	#define IRQ_LEVEL_HIGH 0x02
	77	#define IRQ_LEVEL_LOW 0x03
	78	#define IRQ_EDGE_BOTH 0x04
	79
0e37f88d MR	80	struct sunxi_desc_function {
	81	const char *name;
	82	u8 muxval;
6e1c3023	83	u8 irqbank;
60242db1	84	u8 irqnum;
0e37f88d MR	85	};
	86
	87	struct sunxi_desc_pin {
	88	struct pinctrl_pin_desc pin;
	89	struct sunxi_desc_function *functions;
	90	};
	91
	92	struct sunxi_pinctrl_desc {
	93	const struct sunxi_desc_pin *pins;
	94	int npins;
d83c82ce	95	unsigned pin_base;
8966ada2	96	unsigned irq_banks;
0e37f88d MR	97	};
	98
	99	struct sunxi_pinctrl_function {
	100	const char *name;
	101	const char **groups;
	102	unsigned ngroups;
	103	};
	104
	105	struct sunxi_pinctrl_group {
	106	const char *name;
	107	unsigned long config;
	108	unsigned pin;
	109	};
	110
	111	struct sunxi_pinctrl {
	112	void __iomem *membase;
08e9e614	113	struct gpio_chip *chip;
d39bd845	114	const struct sunxi_pinctrl_desc *desc;
0e37f88d	115	struct device *dev;
60242db1	116	struct irq_domain *domain;
0e37f88d MR	117	struct sunxi_pinctrl_function *functions;
	118	unsigned nfunctions;
	119	struct sunxi_pinctrl_group *groups;
	120	unsigned ngroups;
aebdc8ab MR	121	int *irq;
aebdc8ab MR	122	unsigned *irq_array;
1bee963d	123	spinlock_t lock;
0e37f88d MR	124	struct pinctrl_dev *pctl_dev;
	125	};
	126
	127	#define SUNXI_PIN(_pin, ...) \
	128	{ \
	129	.pin = _pin, \
	130	.functions = (struct sunxi_desc_function[]){ \
	131	__VA_ARGS__, { } }, \
	132	}
	133
	134	#define SUNXI_FUNCTION(_val, _name) \
	135	{ \
	136	.name = _name, \
	137	.muxval = _val, \
	138	}
	139
60242db1 MR	140	#define SUNXI_FUNCTION_IRQ(_val, _irq) \
	141	{ \
	142	.name = "irq", \
	143	.muxval = _val, \
	144	.irqnum = _irq, \
	145	}
	146
6e1c3023 MR	147	#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
	148	{ \
	149	.name = "irq", \
	150	.muxval = _val, \
	151	.irqbank = _bank, \
	152	.irqnum = _irq, \
	153	}
	154
0e37f88d MR	155	/*
	156	* The sunXi PIO registers are organized as is:
	157	* 0x00 - 0x0c Muxing values.
	158	* 8 pins per register, each pin having a 4bits value
	159	* 0x10 Pin values
	160	* 32 bits per register, each pin corresponding to one bit
	161	* 0x14 - 0x18 Drive level
	162	* 16 pins per register, each pin having a 2bits value
	163	* 0x1c - 0x20 Pull-Up values
	164	* 16 pins per register, each pin having a 2bits value
	165	*
	166	* This is for the first bank. Each bank will have the same layout,
	167	* with an offset being a multiple of 0x24.
	168	*
	169	* The following functions calculate from the pin number the register
	170	* and the bit offset that we should access.
	171	*/
	172	static inline u32 sunxi_mux_reg(u16 pin)
	173	{
	174	u8 bank = pin / PINS_PER_BANK;
	175	u32 offset = bank * BANK_MEM_SIZE;
	176	offset += MUX_REGS_OFFSET;
	177	offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
	178	return round_down(offset, 4);
	179	}
	180
	181	static inline u32 sunxi_mux_offset(u16 pin)
	182	{
	183	u32 pin_num = pin % MUX_PINS_PER_REG;
	184	return pin_num * MUX_PINS_BITS;
	185	}
	186
08e9e614 MR	187	static inline u32 sunxi_data_reg(u16 pin)
	188	{
	189	u8 bank = pin / PINS_PER_BANK;
	190	u32 offset = bank * BANK_MEM_SIZE;
	191	offset += DATA_REGS_OFFSET;
	192	offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
	193	return round_down(offset, 4);
	194	}
	195
	196	static inline u32 sunxi_data_offset(u16 pin)
	197	{
	198	u32 pin_num = pin % DATA_PINS_PER_REG;
	199	return pin_num * DATA_PINS_BITS;
	200	}
	201
0e37f88d MR	202	static inline u32 sunxi_dlevel_reg(u16 pin)
	203	{
	204	u8 bank = pin / PINS_PER_BANK;
	205	u32 offset = bank * BANK_MEM_SIZE;
	206	offset += DLEVEL_REGS_OFFSET;
	207	offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
	208	return round_down(offset, 4);
	209	}
	210
	211	static inline u32 sunxi_dlevel_offset(u16 pin)
	212	{
	213	u32 pin_num = pin % DLEVEL_PINS_PER_REG;
	214	return pin_num * DLEVEL_PINS_BITS;
	215	}
	216
	217	static inline u32 sunxi_pull_reg(u16 pin)
	218	{
	219	u8 bank = pin / PINS_PER_BANK;
	220	u32 offset = bank * BANK_MEM_SIZE;
	221	offset += PULL_REGS_OFFSET;
	222	offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
	223	return round_down(offset, 4);
	224	}
	225
	226	static inline u32 sunxi_pull_offset(u16 pin)
	227	{
	228	u32 pin_num = pin % PULL_PINS_PER_REG;
	229	return pin_num * PULL_PINS_BITS;
	230	}
	231
60242db1 MR	232	static inline u32 sunxi_irq_cfg_reg(u16 irq)
60242db1 MR	233	{
aebdc8ab MR	234	u8 bank = irq / IRQ_PER_BANK;
	235	u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
	236
	237	return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
60242db1 MR	238	}
	239
	240	static inline u32 sunxi_irq_cfg_offset(u16 irq)
	241	{
	242	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
	243	return irq_num * IRQ_CFG_IRQ_BITS;
	244	}
	245
aebdc8ab MR	246	static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
	247	{
	248	return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
	249	}
	250
60242db1 MR	251	static inline u32 sunxi_irq_ctrl_reg(u16 irq)
60242db1 MR	252	{
aebdc8ab MR	253	u8 bank = irq / IRQ_PER_BANK;
	254
	255	return sunxi_irq_ctrl_reg_from_bank(bank);
60242db1 MR	256	}
	257
	258	static inline u32 sunxi_irq_ctrl_offset(u16 irq)
	259	{
	260	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
	261	return irq_num * IRQ_CTRL_IRQ_BITS;
	262	}
	263
aebdc8ab MR	264	static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
	265	{
	266	return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
	267	}
	268
60242db1 MR	269	static inline u32 sunxi_irq_status_reg(u16 irq)
60242db1 MR	270	{
aebdc8ab MR	271	u8 bank = irq / IRQ_PER_BANK;
	272
	273	return sunxi_irq_status_reg_from_bank(bank);
60242db1 MR	274	}
	275
	276	static inline u32 sunxi_irq_status_offset(u16 irq)
	277	{
	278	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
	279	return irq_num * IRQ_STATUS_IRQ_BITS;
	280	}
	281
2284ba6b MR	282	int sunxi_pinctrl_init(struct platform_device *pdev,
	283	const struct sunxi_pinctrl_desc *desc);
	284
0e37f88d	285	#endif /* __PINCTRL_SUNXI_H */