[linux-2.6-block.git] / drivers / pinctrl / sunxi / pinctrl-sunxi.h

/*
 * Allwinner A1X SoCs pinctrl driver.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __PINCTRL_SUNXI_H
#define __PINCTRL_SUNXI_H

#include <linux/kernel.h>
#include <linux/spinlock.h>

#define PA_BASE	0
#define PB_BASE	32
#define PC_BASE	64
#define PD_BASE	96
#define PE_BASE	128
#define PF_BASE	160
#define PG_BASE	192
#define PH_BASE	224
#define PI_BASE	256
#define PL_BASE	352
#define PM_BASE	384

#define SUNXI_PINCTRL_PIN(bank, pin)		\
	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)

#define SUNXI_PIN_NAME_MAX_LEN	5

#define BANK_MEM_SIZE		0x24
#define MUX_REGS_OFFSET		0x0
#define DATA_REGS_OFFSET	0x10
#define DLEVEL_REGS_OFFSET	0x14
#define PULL_REGS_OFFSET	0x1c

#define PINS_PER_BANK		32
#define MUX_PINS_PER_REG	8
#define MUX_PINS_BITS		4
#define MUX_PINS_MASK		0x0f
#define DATA_PINS_PER_REG	32
#define DATA_PINS_BITS		1
#define DATA_PINS_MASK		0x01
#define DLEVEL_PINS_PER_REG	16
#define DLEVEL_PINS_BITS	2
#define DLEVEL_PINS_MASK	0x03
#define PULL_PINS_PER_REG	16
#define PULL_PINS_BITS		2
#define PULL_PINS_MASK		0x03

#define SUNXI_IRQ_NUMBER	32

#define IRQ_CFG_REG		0x200
#define IRQ_CFG_IRQ_PER_REG		8
#define IRQ_CFG_IRQ_BITS		4
#define IRQ_CFG_IRQ_MASK		((1 << IRQ_CFG_IRQ_BITS) - 1)
#define IRQ_CTRL_REG		0x210
#define IRQ_CTRL_IRQ_PER_REG		32
#define IRQ_CTRL_IRQ_BITS		1
#define IRQ_CTRL_IRQ_MASK		((1 << IRQ_CTRL_IRQ_BITS) - 1)
#define IRQ_STATUS_REG		0x214
#define IRQ_STATUS_IRQ_PER_REG		32
#define IRQ_STATUS_IRQ_BITS		1
#define IRQ_STATUS_IRQ_MASK		((1 << IRQ_STATUS_IRQ_BITS) - 1)

#define IRQ_EDGE_RISING		0x00
#define IRQ_EDGE_FALLING	0x01
#define IRQ_LEVEL_HIGH		0x02
#define IRQ_LEVEL_LOW		0x03
#define IRQ_EDGE_BOTH		0x04

struct sunxi_desc_function {
	const char	*name;
	u8		muxval;
	u8		irqbank;
	u8		irqnum;
};

struct sunxi_desc_pin {
	struct pinctrl_pin_desc		pin;
	struct sunxi_desc_function	*functions;
};

struct sunxi_pinctrl_desc {
	const struct sunxi_desc_pin	*pins;
	int				npins;
	unsigned			pin_base;
};

struct sunxi_pinctrl_function {
	const char	*name;
	const char	**groups;
	unsigned	ngroups;
};

struct sunxi_pinctrl_group {
	const char	*name;
	unsigned long	config;
	unsigned	pin;
};

struct sunxi_pinctrl {
	void __iomem			*membase;
	struct gpio_chip		*chip;
	const struct sunxi_pinctrl_desc	*desc;
	struct device			*dev;
	struct irq_domain		*domain;
	struct sunxi_pinctrl_function	*functions;
	unsigned			nfunctions;
	struct sunxi_pinctrl_group	*groups;
	unsigned			ngroups;
	int				irq;
	int				irq_array[SUNXI_IRQ_NUMBER];
	spinlock_t			lock;
	struct pinctrl_dev		*pctl_dev;
};

#define SUNXI_PIN(_pin, ...)					\
	{							\
		.pin = _pin,					\
		.functions = (struct sunxi_desc_function[]){	\
			__VA_ARGS__, { } },			\
	}

#define SUNXI_FUNCTION(_val, _name)				\
	{							\
		.name = _name,					\
		.muxval = _val,					\
	}

#define SUNXI_FUNCTION_IRQ(_val, _irq)				\
	{							\
		.name = "irq",					\
		.muxval = _val,					\
		.irqnum = _irq,					\
	}

#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq)		\
	{							\
		.name = "irq",					\
		.muxval = _val,					\
		.irqbank = _bank,				\
		.irqnum = _irq,					\
	}

/*
 * The sunXi PIO registers are organized as is:
 * 0x00 - 0x0c	Muxing values.
 *		8 pins per register, each pin having a 4bits value
 * 0x10		Pin values
 *		32 bits per register, each pin corresponding to one bit
 * 0x14 - 0x18	Drive level
 *		16 pins per register, each pin having a 2bits value
 * 0x1c - 0x20	Pull-Up values
 *		16 pins per register, each pin having a 2bits value
 *
 * This is for the first bank. Each bank will have the same layout,
 * with an offset being a multiple of 0x24.
 *
 * The following functions calculate from the pin number the register
 * and the bit offset that we should access.
 */
static inline u32 sunxi_mux_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += MUX_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_mux_offset(u16 pin)
{
	u32 pin_num = pin % MUX_PINS_PER_REG;
	return pin_num * MUX_PINS_BITS;
}

static inline u32 sunxi_data_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += DATA_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_data_offset(u16 pin)
{
	u32 pin_num = pin % DATA_PINS_PER_REG;
	return pin_num * DATA_PINS_BITS;
}

static inline u32 sunxi_dlevel_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += DLEVEL_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_dlevel_offset(u16 pin)
{
	u32 pin_num = pin % DLEVEL_PINS_PER_REG;
	return pin_num * DLEVEL_PINS_BITS;
}

static inline u32 sunxi_pull_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += PULL_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_pull_offset(u16 pin)
{
	u32 pin_num = pin % PULL_PINS_PER_REG;
	return pin_num * PULL_PINS_BITS;
}

static inline u32 sunxi_irq_cfg_reg(u16 irq)
{
	u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
	return reg + IRQ_CFG_REG;
}

static inline u32 sunxi_irq_cfg_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
	return irq_num * IRQ_CFG_IRQ_BITS;
}

static inline u32 sunxi_irq_ctrl_reg(u16 irq)
{
	u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
	return reg + IRQ_CTRL_REG;
}

static inline u32 sunxi_irq_ctrl_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
	return irq_num * IRQ_CTRL_IRQ_BITS;
}

static inline u32 sunxi_irq_status_reg(u16 irq)
{
	u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
	return reg + IRQ_STATUS_REG;
}

static inline u32 sunxi_irq_status_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
	return irq_num * IRQ_STATUS_IRQ_BITS;
}

int sunxi_pinctrl_init(struct platform_device *pdev,
		       const struct sunxi_pinctrl_desc *desc);

#endif /* __PINCTRL_SUNXI_H */
Commit	Line	Data
0e37f88d MR	1	/*
	2	* Allwinner A1X SoCs pinctrl driver.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#ifndef __PINCTRL_SUNXI_H
	14	#define __PINCTRL_SUNXI_H
	15
	16	#include <linux/kernel.h>
1bee963d	17	#include <linux/spinlock.h>
0e37f88d MR	18
	19	#define PA_BASE 0
	20	#define PB_BASE 32
	21	#define PC_BASE 64
	22	#define PD_BASE 96
	23	#define PE_BASE 128
	24	#define PF_BASE 160
	25	#define PG_BASE 192
9f5b6b30 MR	26	#define PH_BASE 224
9f5b6b30 MR	27	#define PI_BASE 256
0aba6178 BB	28	#define PL_BASE 352
0aba6178 BB	29	#define PM_BASE 384
0e37f88d	30
d10acc63 MR	31	#define SUNXI_PINCTRL_PIN(bank, pin) \
d10acc63 MR	32	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
0aba6178	33
08e9e614 MR	34	#define SUNXI_PIN_NAME_MAX_LEN 5
08e9e614 MR	35
0e37f88d MR	36	#define BANK_MEM_SIZE 0x24
0e37f88d MR	37	#define MUX_REGS_OFFSET 0x0
08e9e614	38	#define DATA_REGS_OFFSET 0x10
0e37f88d MR	39	#define DLEVEL_REGS_OFFSET 0x14
	40	#define PULL_REGS_OFFSET 0x1c
	41
	42	#define PINS_PER_BANK 32
	43	#define MUX_PINS_PER_REG 8
	44	#define MUX_PINS_BITS 4
	45	#define MUX_PINS_MASK 0x0f
08e9e614 MR	46	#define DATA_PINS_PER_REG 32
	47	#define DATA_PINS_BITS 1
	48	#define DATA_PINS_MASK 0x01
0e37f88d MR	49	#define DLEVEL_PINS_PER_REG 16
	50	#define DLEVEL_PINS_BITS 2
	51	#define DLEVEL_PINS_MASK 0x03
	52	#define PULL_PINS_PER_REG 16
	53	#define PULL_PINS_BITS 2
	54	#define PULL_PINS_MASK 0x03
	55
60242db1 MR	56	#define SUNXI_IRQ_NUMBER 32
	57
	58	#define IRQ_CFG_REG 0x200
	59	#define IRQ_CFG_IRQ_PER_REG 8
	60	#define IRQ_CFG_IRQ_BITS 4
	61	#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
	62	#define IRQ_CTRL_REG 0x210
	63	#define IRQ_CTRL_IRQ_PER_REG 32
	64	#define IRQ_CTRL_IRQ_BITS 1
	65	#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
	66	#define IRQ_STATUS_REG 0x214
	67	#define IRQ_STATUS_IRQ_PER_REG 32
	68	#define IRQ_STATUS_IRQ_BITS 1
	69	#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
	70
	71	#define IRQ_EDGE_RISING 0x00
	72	#define IRQ_EDGE_FALLING 0x01
	73	#define IRQ_LEVEL_HIGH 0x02
	74	#define IRQ_LEVEL_LOW 0x03
	75	#define IRQ_EDGE_BOTH 0x04
	76
0e37f88d MR	77	struct sunxi_desc_function {
	78	const char *name;
	79	u8 muxval;
6e1c3023	80	u8 irqbank;
60242db1	81	u8 irqnum;
0e37f88d MR	82	};
	83
	84	struct sunxi_desc_pin {
	85	struct pinctrl_pin_desc pin;
	86	struct sunxi_desc_function *functions;
	87	};
	88
	89	struct sunxi_pinctrl_desc {
	90	const struct sunxi_desc_pin *pins;
	91	int npins;
d83c82ce	92	unsigned pin_base;
0e37f88d MR	93	};
	94
	95	struct sunxi_pinctrl_function {
	96	const char *name;
	97	const char **groups;
	98	unsigned ngroups;
	99	};
	100
	101	struct sunxi_pinctrl_group {
	102	const char *name;
	103	unsigned long config;
	104	unsigned pin;
	105	};
	106
	107	struct sunxi_pinctrl {
	108	void __iomem *membase;
08e9e614	109	struct gpio_chip *chip;
d39bd845	110	const struct sunxi_pinctrl_desc *desc;
0e37f88d	111	struct device *dev;
60242db1	112	struct irq_domain *domain;
0e37f88d MR	113	struct sunxi_pinctrl_function *functions;
	114	unsigned nfunctions;
	115	struct sunxi_pinctrl_group *groups;
	116	unsigned ngroups;
60242db1 MR	117	int irq;
60242db1 MR	118	int irq_array[SUNXI_IRQ_NUMBER];
1bee963d	119	spinlock_t lock;
0e37f88d MR	120	struct pinctrl_dev *pctl_dev;
	121	};
	122
	123	#define SUNXI_PIN(_pin, ...) \
	124	{ \
	125	.pin = _pin, \
	126	.functions = (struct sunxi_desc_function[]){ \
	127	__VA_ARGS__, { } }, \
	128	}
	129
	130	#define SUNXI_FUNCTION(_val, _name) \
	131	{ \
	132	.name = _name, \
	133	.muxval = _val, \
	134	}
	135
60242db1 MR	136	#define SUNXI_FUNCTION_IRQ(_val, _irq) \
	137	{ \
	138	.name = "irq", \
	139	.muxval = _val, \
	140	.irqnum = _irq, \
	141	}
	142
6e1c3023 MR	143	#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
	144	{ \
	145	.name = "irq", \
	146	.muxval = _val, \
	147	.irqbank = _bank, \
	148	.irqnum = _irq, \
	149	}
	150
0e37f88d MR	151	/*
	152	* The sunXi PIO registers are organized as is:
	153	* 0x00 - 0x0c Muxing values.
	154	* 8 pins per register, each pin having a 4bits value
	155	* 0x10 Pin values
	156	* 32 bits per register, each pin corresponding to one bit
	157	* 0x14 - 0x18 Drive level
	158	* 16 pins per register, each pin having a 2bits value
	159	* 0x1c - 0x20 Pull-Up values
	160	* 16 pins per register, each pin having a 2bits value
	161	*
	162	* This is for the first bank. Each bank will have the same layout,
	163	* with an offset being a multiple of 0x24.
	164	*
	165	* The following functions calculate from the pin number the register
	166	* and the bit offset that we should access.
	167	*/
	168	static inline u32 sunxi_mux_reg(u16 pin)
	169	{
	170	u8 bank = pin / PINS_PER_BANK;
	171	u32 offset = bank * BANK_MEM_SIZE;
	172	offset += MUX_REGS_OFFSET;
	173	offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
	174	return round_down(offset, 4);
	175	}
	176
	177	static inline u32 sunxi_mux_offset(u16 pin)
	178	{
	179	u32 pin_num = pin % MUX_PINS_PER_REG;
	180	return pin_num * MUX_PINS_BITS;
	181	}
	182
08e9e614 MR	183	static inline u32 sunxi_data_reg(u16 pin)
	184	{
	185	u8 bank = pin / PINS_PER_BANK;
	186	u32 offset = bank * BANK_MEM_SIZE;
	187	offset += DATA_REGS_OFFSET;
	188	offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
	189	return round_down(offset, 4);
	190	}
	191
	192	static inline u32 sunxi_data_offset(u16 pin)
	193	{
	194	u32 pin_num = pin % DATA_PINS_PER_REG;
	195	return pin_num * DATA_PINS_BITS;
	196	}
	197
0e37f88d MR	198	static inline u32 sunxi_dlevel_reg(u16 pin)
	199	{
	200	u8 bank = pin / PINS_PER_BANK;
	201	u32 offset = bank * BANK_MEM_SIZE;
	202	offset += DLEVEL_REGS_OFFSET;
	203	offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
	204	return round_down(offset, 4);
	205	}
	206
	207	static inline u32 sunxi_dlevel_offset(u16 pin)
	208	{
	209	u32 pin_num = pin % DLEVEL_PINS_PER_REG;
	210	return pin_num * DLEVEL_PINS_BITS;
	211	}
	212
	213	static inline u32 sunxi_pull_reg(u16 pin)
	214	{
	215	u8 bank = pin / PINS_PER_BANK;
	216	u32 offset = bank * BANK_MEM_SIZE;
	217	offset += PULL_REGS_OFFSET;
	218	offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
	219	return round_down(offset, 4);
	220	}
	221
	222	static inline u32 sunxi_pull_offset(u16 pin)
	223	{
	224	u32 pin_num = pin % PULL_PINS_PER_REG;
	225	return pin_num * PULL_PINS_BITS;
	226	}
	227
60242db1 MR	228	static inline u32 sunxi_irq_cfg_reg(u16 irq)
60242db1 MR	229	{
ef5aff05	230	u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
60242db1 MR	231	return reg + IRQ_CFG_REG;
	232	}
	233
	234	static inline u32 sunxi_irq_cfg_offset(u16 irq)
	235	{
	236	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
	237	return irq_num * IRQ_CFG_IRQ_BITS;
	238	}
	239
	240	static inline u32 sunxi_irq_ctrl_reg(u16 irq)
	241	{
ef5aff05	242	u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
60242db1 MR	243	return reg + IRQ_CTRL_REG;
	244	}
	245
	246	static inline u32 sunxi_irq_ctrl_offset(u16 irq)
	247	{
	248	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
	249	return irq_num * IRQ_CTRL_IRQ_BITS;
	250	}
	251
	252	static inline u32 sunxi_irq_status_reg(u16 irq)
	253	{
ef5aff05	254	u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
60242db1 MR	255	return reg + IRQ_STATUS_REG;
	256	}
	257
	258	static inline u32 sunxi_irq_status_offset(u16 irq)
	259	{
	260	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
	261	return irq_num * IRQ_STATUS_IRQ_BITS;
	262	}
	263
2284ba6b MR	264	int sunxi_pinctrl_init(struct platform_device *pdev,
	265	const struct sunxi_pinctrl_desc *desc);
	266
0e37f88d	267	#endif /* __PINCTRL_SUNXI_H */