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pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
CommitLineData
63b6d7e7 1// SPDX-License-Identifier: GPL-2.0
0b0ffc96 2/*
b205914c 3 * R8A7795 ES2.0+ processor support - PFC hardware block.
0b0ffc96 4 *
740a4a3a 5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
0b0ffc96
TK		 6 */
7
2f9f5094 8#include <linux/errno.h>
0b0ffc96 9#include <linux/kernel.h>
b205914c 10#include <linux/sys_soc.h>
0b0ffc96
TK		 11
12#include "core.h"
13#include "sh_pfc.h"
14
56065524
UH		 15#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
16 SH_PFC_PIN_CFG_PULL_UP | \
17 SH_PFC_PIN_CFG_PULL_DOWN)
18
0b0ffc96 19#define CPU_ALL_PORT(fn, sfx) \
56065524 20 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
82d2de5a 21 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
56065524
UH		 22 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
24 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
0b0ffc96
TK		 32/*
33 * F_() : just information
34 * FM() : macro for FN_xxx / xxx_MARK
35 */
36
37/* GPSR0 */
38#define GPSR0_15 F_(D15, IP7_11_8)
39#define GPSR0_14 F_(D14, IP7_7_4)
40#define GPSR0_13 F_(D13, IP7_3_0)
41#define GPSR0_12 F_(D12, IP6_31_28)
42#define GPSR0_11 F_(D11, IP6_27_24)
43#define GPSR0_10 F_(D10, IP6_23_20)
44#define GPSR0_9 F_(D9, IP6_19_16)
45#define GPSR0_8 F_(D8, IP6_15_12)
46#define GPSR0_7 F_(D7, IP6_11_8)
47#define GPSR0_6 F_(D6, IP6_7_4)
48#define GPSR0_5 F_(D5, IP6_3_0)
49#define GPSR0_4 F_(D4, IP5_31_28)
50#define GPSR0_3 F_(D3, IP5_27_24)
51#define GPSR0_2 F_(D2, IP5_23_20)
52#define GPSR0_1 F_(D1, IP5_19_16)
53#define GPSR0_0 F_(D0, IP5_15_12)
54
55/* GPSR1 */
82d2de5a 56#define GPSR1_28 FM(CLKOUT)
0b0ffc96
TK		 57#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
58#define GPSR1_26 F_(WE1_N, IP5_7_4)
59#define GPSR1_25 F_(WE0_N, IP5_3_0)
60#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
61#define GPSR1_23 F_(RD_N, IP4_27_24)
62#define GPSR1_22 F_(BS_N, IP4_23_20)
fc8fd9be 63#define GPSR1_21 F_(CS1_N, IP4_19_16)
0b0ffc96
TK		 64#define GPSR1_20 F_(CS0_N, IP4_15_12)
65#define GPSR1_19 F_(A19, IP4_11_8)
66#define GPSR1_18 F_(A18, IP4_7_4)
67#define GPSR1_17 F_(A17, IP4_3_0)
68#define GPSR1_16 F_(A16, IP3_31_28)
69#define GPSR1_15 F_(A15, IP3_27_24)
70#define GPSR1_14 F_(A14, IP3_23_20)
71#define GPSR1_13 F_(A13, IP3_19_16)
72#define GPSR1_12 F_(A12, IP3_15_12)
73#define GPSR1_11 F_(A11, IP3_11_8)
74#define GPSR1_10 F_(A10, IP3_7_4)
75#define GPSR1_9 F_(A9, IP3_3_0)
76#define GPSR1_8 F_(A8, IP2_31_28)
77#define GPSR1_7 F_(A7, IP2_27_24)
78#define GPSR1_6 F_(A6, IP2_23_20)
79#define GPSR1_5 F_(A5, IP2_19_16)
80#define GPSR1_4 F_(A4, IP2_15_12)
81#define GPSR1_3 F_(A3, IP2_11_8)
82#define GPSR1_2 F_(A2, IP2_7_4)
83#define GPSR1_1 F_(A1, IP2_3_0)
84#define GPSR1_0 F_(A0, IP1_31_28)
85
86/* GPSR2 */
87#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
88#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
89#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
90#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
91#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
92#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
93#define GPSR2_8 F_(PWM2_A, IP1_27_24)
94#define GPSR2_7 F_(PWM1_A, IP1_23_20)
95#define GPSR2_6 F_(PWM0, IP1_19_16)
96#define GPSR2_5 F_(IRQ5, IP1_15_12)
97#define GPSR2_4 F_(IRQ4, IP1_11_8)
98#define GPSR2_3 F_(IRQ3, IP1_7_4)
99#define GPSR2_2 F_(IRQ2, IP1_3_0)
100#define GPSR2_1 F_(IRQ1, IP0_31_28)
101#define GPSR2_0 F_(IRQ0, IP0_27_24)
102
103/* GPSR3 */
b205914c
GU		 104#define GPSR3_15 F_(SD1_WP, IP11_23_20)
105#define GPSR3_14 F_(SD1_CD, IP11_19_16)
106#define GPSR3_13 F_(SD0_WP, IP11_15_12)
107#define GPSR3_12 F_(SD0_CD, IP11_11_8)
0b0ffc96
TK		 108#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
109#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
110#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
111#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
112#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
113#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
114#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
115#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
116#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
117#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
118#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
119#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
120
121/* GPSR4 */
b205914c
GU		 122#define GPSR4_17 F_(SD3_DS, IP11_7_4)
123#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
124#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
125#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
126#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
127#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
128#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
129#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
130#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
131#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
132#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
133#define GPSR4_6 F_(SD2_DS, IP9_27_24)
134#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
135#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
136#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
137#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
138#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
0b0ffc96
TK		 139#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
140
141/* GPSR5 */
b205914c
GU		 142#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
143#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
144#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
0b0ffc96 145#define GPSR5_22 FM(MSIOF0_RXD)
b205914c 146#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
0b0ffc96 147#define GPSR5_20 FM(MSIOF0_TXD)
b205914c
GU		 148#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
149#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
0b0ffc96 150#define GPSR5_17 FM(MSIOF0_SCK)
b205914c
GU		 151#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
152#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
153#define GPSR5_14 F_(HTX0, IP13_19_16)
154#define GPSR5_13 F_(HRX0, IP13_15_12)
155#define GPSR5_12 F_(HSCK0, IP13_11_8)
156#define GPSR5_11 F_(RX2_A, IP13_7_4)
157#define GPSR5_10 F_(TX2_A, IP13_3_0)
158#define GPSR5_9 F_(SCK2, IP12_31_28)
8714a9c1 159#define GPSR5_8 F_(RTS1_N, IP12_27_24)
b205914c
GU		 160#define GPSR5_7 F_(CTS1_N, IP12_23_20)
161#define GPSR5_6 F_(TX1_A, IP12_19_16)
162#define GPSR5_5 F_(RX1_A, IP12_15_12)
8714a9c1 163#define GPSR5_4 F_(RTS0_N, IP12_11_8)
b205914c
GU		 164#define GPSR5_3 F_(CTS0_N, IP12_7_4)
165#define GPSR5_2 F_(TX0, IP12_3_0)
166#define GPSR5_1 F_(RX0, IP11_31_28)
167#define GPSR5_0 F_(SCK0, IP11_27_24)
0b0ffc96
TK		 168
169/* GPSR6 */
f9d13080
YS		 170#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
171#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
b205914c
GU		 172#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
173#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
174#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
175#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
176#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
177#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
178#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
179#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
180#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
181#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
182#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
183#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
184#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
185#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
186#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
187#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
0b0ffc96
TK		 188#define GPSR6_13 FM(SSI_SDATA5)
189#define GPSR6_12 FM(SSI_WS5)
190#define GPSR6_11 FM(SSI_SCK5)
b205914c
GU		 191#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
192#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
193#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
194#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
68e63892
KM		 195#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
196#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
b205914c
GU		 197#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
198#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
199#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
200#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
201#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
0b0ffc96
TK		 202
203/* GPSR7 */
5671f8e0
TK		 204#define GPSR7_3 FM(GP7_03)
205#define GPSR7_2 FM(GP7_02)
0b0ffc96
TK		 206#define GPSR7_1 FM(AVS2)
207#define GPSR7_0 FM(AVS1)
208
209
210/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
211#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 215#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 216#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
e2ab1770
TK		 217#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 219#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
7716c51b
TK		 220#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 226#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230
231/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
232#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 238#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 239#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
fc8fd9be 249#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 250#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 254#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 255#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 267#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 268#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 272#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273
274/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
275#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 281#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 286#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 304#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 305
306/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
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GU		 307#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 314#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 315#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 318#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 319#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
328#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335
336/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
337#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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KM		 340#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 342#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
662dc924 354#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 355#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
357#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
358#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
359#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
360#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
361#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 362#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
363#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
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TK		 364
365#define PINMUX_GPSR \
366\
367 GPSR6_31 \
368 GPSR6_30 \
369 GPSR6_29 \
82d2de5a 370 GPSR1_28 GPSR6_28 \
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TK		 371 GPSR1_27 GPSR6_27 \
372 GPSR1_26 GPSR6_26 \
373 GPSR1_25 GPSR5_25 GPSR6_25 \
374 GPSR1_24 GPSR5_24 GPSR6_24 \
375 GPSR1_23 GPSR5_23 GPSR6_23 \
376 GPSR1_22 GPSR5_22 GPSR6_22 \
377 GPSR1_21 GPSR5_21 GPSR6_21 \
378 GPSR1_20 GPSR5_20 GPSR6_20 \
379 GPSR1_19 GPSR5_19 GPSR6_19 \
380 GPSR1_18 GPSR5_18 GPSR6_18 \
381 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
382 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
383GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
384GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
385GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
386GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
387GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
388GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
389GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
390GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
391GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
392GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
393GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
394GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
395GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
396GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
397GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
398GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
399
400#define PINMUX_IPSR \
401\
402FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
403FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
404FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
405FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
406FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
407FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
408FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
409FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
410\
411FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
412FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
413FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
30cd1c46 414FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
0b0ffc96
TK		 415FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
416FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
417FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
418FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
419\
420FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
421FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
422FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
423FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
424FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
425FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
426FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
427FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
428\
429FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
430FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
431FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
432FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
433FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
434FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
435FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
436FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
437\
b205914c
GU		 438FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
439FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
440FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
441FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
442FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
443FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
444FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
445FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
0b0ffc96
TK		 446
447/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
b205914c 448#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 449#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
450#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
451#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
452#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
b205914c
GU		 453#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
454#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
455#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
456#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
457#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
458#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
459#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
460#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
461#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
462#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
463#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
464#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
465#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
0b0ffc96
TK		 466
467/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
468#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
469#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
ae03c4ec 470#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
0b0ffc96
TK		 471#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
472#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
740a4a3a 473#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
0b0ffc96
TK		 474#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
475#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
476#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
477#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
478#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
479#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
480#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
eada11ac 481#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
0b0ffc96
TK		 482#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
483#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
484#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
485#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
486#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
487#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
488#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
489#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
490
491/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
492#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
493#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
494#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
b205914c
GU		 495#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
496#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
497#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 498#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
499#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
500#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
501#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
502#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
0b0ffc96
TK		 503#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
504
b205914c 505#define PINMUX_MOD_SELS \
0b0ffc96 506\
b205914c
GU		 507MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
508 MOD_SEL2_30 \
0b0ffc96 509 MOD_SEL1_29_28_27 MOD_SEL2_29 \
b205914c
GU		 510MOD_SEL0_28_27 MOD_SEL2_28_27 \
511MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
512 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
0b0ffc96 513MOD_SEL0_23 MOD_SEL1_23_22_21 \
3c612d2c 514MOD_SEL0_22 \
b205914c
GU		 515MOD_SEL0_21 MOD_SEL2_21 \
516MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
517MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
518MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
519 MOD_SEL2_17 \
520MOD_SEL0_16 MOD_SEL1_16 \
0b0ffc96 521 MOD_SEL1_15_14 \
b205914c
GU		 522MOD_SEL0_14_13 \
523 MOD_SEL1_13 \
0b0ffc96
TK		 524MOD_SEL0_12 MOD_SEL1_12 \
525MOD_SEL0_11 MOD_SEL1_11 \
526MOD_SEL0_10 MOD_SEL1_10 \
b205914c 527MOD_SEL0_9_8 MOD_SEL1_9 \
0b0ffc96
TK		 528MOD_SEL0_7_6 \
529 MOD_SEL1_6 \
b205914c
GU		 530MOD_SEL0_5 MOD_SEL1_5 \
531MOD_SEL0_4_3 MOD_SEL1_4 \
532 MOD_SEL1_3 \
533 MOD_SEL1_2 \
0b0ffc96
TK		 534 MOD_SEL1_1 \
535 MOD_SEL1_0 MOD_SEL2_0
536
ea9c7405
NS		 537/*
538 * These pins are not able to be muxed but have other properties
539 * that can be set, such as drive-strength or pull-up/pull-down enable.
540 */
541#define PINMUX_STATIC \
542 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
543 FM(QSPI0_IO2) FM(QSPI0_IO3) \
544 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
545 FM(QSPI1_IO2) FM(QSPI1_IO3) \
546 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
547 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
548 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
549 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
82d2de5a 550 FM(PRESETOUT) \
ea9c7405 551 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
4c2fb44d 552 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
0b0ffc96 553
100431b6
TK		 554#define PINMUX_PHYS \
555 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
556
0b0ffc96
TK		 557enum {
558 PINMUX_RESERVED = 0,
559
560 PINMUX_DATA_BEGIN,
561 GP_ALL(DATA),
562 PINMUX_DATA_END,
563
564#define F_(x, y)
565#define FM(x) FN_##x,
566 PINMUX_FUNCTION_BEGIN,
567 GP_ALL(FN),
568 PINMUX_GPSR
569 PINMUX_IPSR
570 PINMUX_MOD_SELS
571 PINMUX_FUNCTION_END,
572#undef F_
573#undef FM
574
575#define F_(x, y)
576#define FM(x) x##_MARK,
577 PINMUX_MARK_BEGIN,
578 PINMUX_GPSR
579 PINMUX_IPSR
580 PINMUX_MOD_SELS
ea9c7405 581 PINMUX_STATIC
100431b6 582 PINMUX_PHYS
0b0ffc96
TK		 583 PINMUX_MARK_END,
584#undef F_
585#undef FM
586};
587
588static const u16 pinmux_data[] = {
589 PINMUX_DATA_GP_ALL(),
590
8d4df573
GU		 591 PINMUX_SINGLE(AVS1),
592 PINMUX_SINGLE(AVS2),
82d2de5a 593 PINMUX_SINGLE(CLKOUT),
5671f8e0
TK		 594 PINMUX_SINGLE(GP7_02),
595 PINMUX_SINGLE(GP7_03),
8d4df573
GU		 596 PINMUX_SINGLE(MSIOF0_RXD),
597 PINMUX_SINGLE(MSIOF0_SCK),
598 PINMUX_SINGLE(MSIOF0_TXD),
8d4df573
GU		 599 PINMUX_SINGLE(SSI_SCK5),
600 PINMUX_SINGLE(SSI_SDATA5),
601 PINMUX_SINGLE(SSI_WS5),
602
0b0ffc96 603 /* IPSR0 */
e01678e3 604 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 605 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
606
e01678e3 607 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 608 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
609 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
610
e01678e3 611 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 612 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
613 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
614
e01678e3 615 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 616 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
617 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
618
100431b6
TK		 619 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
620 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
621 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
622 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
623 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
0b0ffc96 624
100431b6
TK		 625 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
626 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
627 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
628 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
0b0ffc96 629
e01678e3
GU		 630 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
631 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
632 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 633 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
b205914c 636 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
0b0ffc96 637
e01678e3
GU		 638 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
639 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
640 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 641 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
b205914c 644 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
0b0ffc96
TK		 645
646 /* IPSR1 */
e01678e3
GU		 647 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
648 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
649 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 650 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
651 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
b205914c 652 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
0b0ffc96 653
e01678e3
GU		 654 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
655 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
e01678e3 656 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 657 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
b205914c 659 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
0b0ffc96 660
e01678e3
GU		 661 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
662 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
e01678e3 663 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 664 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
665 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
b205914c 666 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
0b0ffc96 667
e01678e3
GU		 668 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
669 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
e01678e3 670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
b205914c
GU		 673 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
0b0ffc96 675
e01678e3
GU		 676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
0b0ffc96
TK		 678 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
680
100431b6
TK		 681 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
682 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
683 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
684 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
685 PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
0b0ffc96 686
100431b6
TK		 687 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
688 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
689 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
690 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
0b0ffc96 691
e01678e3
GU		 692 PINMUX_IPSR_GPSR(IP1_31_28, A0),
693 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 694 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 695 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
696 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 697 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
698
699 /* IPSR2 */
e01678e3
GU		 700 PINMUX_IPSR_GPSR(IP2_3_0, A1),
701 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 702 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 703 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
704 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 705 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
706
e01678e3
GU		 707 PINMUX_IPSR_GPSR(IP2_7_4, A2),
708 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 709 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 710 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
711 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 712 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
713
e01678e3
GU		 714 PINMUX_IPSR_GPSR(IP2_11_8, A3),
715 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 716 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 717 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
718 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 719 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
720
e01678e3
GU		 721 PINMUX_IPSR_GPSR(IP2_15_12, A4),
722 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 723 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 724 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
725 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
726 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 727
e01678e3
GU		 728 PINMUX_IPSR_GPSR(IP2_19_16, A5),
729 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 730 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
731 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 732 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
733 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
734 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 735
e01678e3
GU		 736 PINMUX_IPSR_GPSR(IP2_23_20, A6),
737 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 738 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
739 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 740 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
741 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
742 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 743
e01678e3
GU		 744 PINMUX_IPSR_GPSR(IP2_27_24, A7),
745 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 746 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
747 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 748 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
749 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
750 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 751
e01678e3 752 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 753 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
754 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
755 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
756 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
757 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
758 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
759
760 /* IPSR3 */
e01678e3 761 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 762 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
763 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 764 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 765
e01678e3 766 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96 767 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
8714a9c1 768 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
e01678e3 769 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 770
e01678e3 771 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 772 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
773 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
774 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 775 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
776 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 777 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
778 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
779 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
780
e01678e3
GU		 781 PINMUX_IPSR_GPSR(IP3_15_12, A12),
782 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 783 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
784 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 785 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
786 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 787
e01678e3
GU		 788 PINMUX_IPSR_GPSR(IP3_19_16, A13),
789 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 790 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
791 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 792 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
793 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 794
e01678e3
GU		 795 PINMUX_IPSR_GPSR(IP3_23_20, A14),
796 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 797 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 798 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
799 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
800 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 801
e01678e3
GU		 802 PINMUX_IPSR_GPSR(IP3_27_24, A15),
803 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 804 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 805 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
806 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
807 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 808
e01678e3
GU		 809 PINMUX_IPSR_GPSR(IP3_31_28, A16),
810 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
811 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
812 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 813
814 /* IPSR4 */
e01678e3
GU		 815 PINMUX_IPSR_GPSR(IP4_3_0, A17),
816 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
817 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
818 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
819
820 PINMUX_IPSR_GPSR(IP4_7_4, A18),
821 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
822 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
823 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
824
825 PINMUX_IPSR_GPSR(IP4_11_8, A19),
826 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
827 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
828 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
829
830 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
831 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
832
fc8fd9be 833 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
e01678e3 834 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 835 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
836
e01678e3
GU		 837 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
838 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 839 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 840 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
841 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
842 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
843 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 844 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
845
e01678e3 846 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 847 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
848 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
849 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
850 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
851 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
852
e01678e3 853 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 854 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
855 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
856 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
857 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
858 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
859
860 /* IPSR5 */
e01678e3 861 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 862 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 863 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
864 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 865 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 866 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 867 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
868
e01678e3 869 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 870 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
8714a9c1 871 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
e01678e3 872 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 873 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 874 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
875 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 876 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
877
878 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 879 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
880 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
881 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 882
e01678e3 883 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 884 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
885 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 886 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
887 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 888
e01678e3 889 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 890 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
891 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 892 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
893 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 894
e01678e3 895 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 896 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 897 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
898 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 899
e01678e3 900 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 901 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 902 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
903 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 904
e01678e3 905 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 906 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 907 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
908 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 909
910 /* IPSR6 */
e01678e3 911 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 912 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 913 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
914 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 915
b205914c
GU		 916 PINMUX_IPSR_GPSR(IP6_7_4, D6),
917 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
918 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
919 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
c33a7fe3 920
b205914c
GU		 921 PINMUX_IPSR_GPSR(IP6_11_8, D7),
922 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
923 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
924 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
819fd4bf 925
b205914c
GU		 926 PINMUX_IPSR_GPSR(IP6_15_12, D8),
927 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
928 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
929 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
930 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
931 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
a4d9791f 932
b205914c
GU		 933 PINMUX_IPSR_GPSR(IP6_19_16, D9),
934 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
935 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
936 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
937 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
a4d9791f 938
b205914c
GU		 939 PINMUX_IPSR_GPSR(IP6_23_20, D10),
940 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
941 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
942 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
943 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
944 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
945 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
a4d9791f 946
b205914c
GU		 947 PINMUX_IPSR_GPSR(IP6_27_24, D11),
948 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
949 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
950 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
951 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
8714a9c1 952 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
b205914c 953 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
4412bb5d 954
b205914c
GU		 955 PINMUX_IPSR_GPSR(IP6_31_28, D12),
956 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
957 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
958 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
959 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
960 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
4412bb5d 961
b205914c
GU		 962 /* IPSR7 */
963 PINMUX_IPSR_GPSR(IP7_3_0, D13),
964 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
965 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
966 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
967 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
968 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
2d775831 969
b205914c
GU		 970 PINMUX_IPSR_GPSR(IP7_7_4, D14),
971 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
972 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
973 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
974 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
975 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
976 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
2d775831 977
b205914c
GU		 978 PINMUX_IPSR_GPSR(IP7_11_8, D15),
979 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
980 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
981 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
982 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
983 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
984 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
2d775831 985
b205914c
GU		 986 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
987 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
988 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
7955dac1 989
b205914c
GU		 990 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
991 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
992 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
a56069c4 993
b205914c
GU		 994 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
995 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
996 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
997 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
a56069c4 998
b205914c
GU		 999 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1000 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1001 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1002 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
a56069c4 1003
b205914c
GU		 1004 /* IPSR8 */
1005 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1006 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1007 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1008 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
a56069c4 1009
b205914c
GU		 1010 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1011 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1012 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1013 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
a56069c4 1014
b205914c
GU		 1015 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1016 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1017 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
2544ef72 1018
b205914c
GU		 1019 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1020 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
3c612d2c 1021 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
b205914c
GU		 1022 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1023 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
2544ef72 1024
b205914c
GU		 1025 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1026 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1027 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
3c612d2c 1028 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
b205914c
GU		 1029 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1030 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
2544ef72 1031
b205914c
GU		 1032 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1033 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1034 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
3c612d2c 1035 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
b205914c
GU		 1036 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1037 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
bb46f6f3 1038
b205914c
GU		 1039 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1040 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1041 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
3c612d2c 1042 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
b205914c
GU		 1043 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1044 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
e7419b81 1045
b205914c
GU		 1046 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1047 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1048 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
3c612d2c 1049 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
b205914c
GU		 1050 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1051 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
e7419b81 1052
b205914c
GU		 1053 /* IPSR9 */
1054 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1055 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
e7419b81 1056
b205914c
GU		 1057 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1058 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
e7419b81 1059
b205914c
GU		 1060 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1061 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
4ca88cf6 1062
b205914c
GU		 1063 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1064 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
4ca88cf6 1065
b205914c
GU		 1066 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1067 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
4ca88cf6 1068
b205914c
GU		 1069 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1070 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
4ca88cf6 1071
b205914c
GU		 1072 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1073 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1074 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
4ca88cf6 1075
b205914c
GU		 1076 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1077 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
4ca88cf6 1078
b205914c
GU		 1079 /* IPSR10 */
1080 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1081 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
4ca88cf6 1082
b205914c
GU		 1083 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1084 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
b332da51 1085
b205914c
GU		 1086 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1087 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
b332da51 1088
b205914c
GU		 1089 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1090 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
34dc4e16 1091
b205914c
GU		 1092 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1093 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
ff8459a5 1094
b205914c
GU		 1095 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1096 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1097 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
ff8459a5 1098
b205914c
GU		 1099 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1100 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1101 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
ff8459a5 1102
b205914c
GU		 1103 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1104 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1105 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
ff8459a5 1106
b205914c
GU		 1107 /* IPSR11 */
1108 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1109 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1110 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1111
1112 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1113 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1114
1115 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1116 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1117 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1118
1119 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1120 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1121
100431b6
TK		 1122 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1123 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1124 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
b205914c 1125
100431b6
TK		 1126 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1127 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1128 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
b205914c
GU		 1129
1130 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1131 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1135 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1137 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1138 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1139 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1140
1141 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1142 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1143 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1145 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
ff8459a5 1146
b205914c
GU		 1147 /* IPSR12 */
1148 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1149 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1150 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1152 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1153
1154 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1155 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1157 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1159 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1160 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1161 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1162
8714a9c1 1163 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
b205914c
GU		 1164 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1167 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1168 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1169 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1170 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1171
1172 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1176 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1177
1178 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1182 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1183
1184 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1185 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1186 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1187 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1189 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1190 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1191
8714a9c1 1192 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
b205914c
GU		 1193 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1194 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1195 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1197 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1198 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1199
1200 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
eada11ac 1201 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
b205914c
GU		 1202 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1203 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1205 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1206 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
0b0ffc96 1207
b205914c
GU		 1208 /* IPSR13 */
1209 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1211 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1214 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1215
1216 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1218 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1221 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1222
1223 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1224 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1225 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
740a4a3a 1226 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
b205914c
GU		 1227 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1230 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1231
1232 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1233 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
740a4a3a 1234 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
b205914c
GU		 1235 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1238
1239 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1240 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
740a4a3a 1241 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
b205914c
GU		 1242 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1245
1246 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1247 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1248 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
740a4a3a 1249 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
b205914c
GU		 1250 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1253 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1254
1255 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1256 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1257 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
740a4a3a 1258 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
b205914c
GU		 1259 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1260 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1261 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1262
1263 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1264 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1265 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1266 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
f27200f9 1267
b205914c
GU		 1268 /* IPSR14 */
1269 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1270 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
3c612d2c 1271 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
b205914c 1272 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
740a4a3a 1273 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
b205914c
GU		 1274 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1275 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
ae03c4ec 1276 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
b205914c
GU		 1277
1278 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1279 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1280 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1281 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
740a4a3a 1282 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
b205914c
GU		 1283 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1284 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1285 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1286
1287 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1288 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1289 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1290
1291 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1292 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1293 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1294 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1295
1296 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1297 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1298 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1299
1300 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1301 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1302
1303 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1304 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1305
1306 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1307 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
20cacae1 1308
b205914c 1309 /* IPSR15 */
740a4a3a 1310 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
b205914c 1311
740a4a3a
TK		 1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1313 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
b205914c 1314
68e63892 1315 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
b205914c
GU		 1316 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1317 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1318
68e63892 1319 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
b205914c
GU		 1320 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1322 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1323
1324 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1325 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1331
1332 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1333 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1339
1340 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1341 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1347
1348 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1349 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
20cacae1 1355
b205914c
GU		 1356 /* IPSR16 */
1357 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1358 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1359 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1360
1361 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1362 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1363 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1364
1365 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1366 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1367 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1368
1369 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1370 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1371 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1372 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1375 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1376
1377 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1378 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1379 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1380 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1383 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1384
1385 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1386 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1387 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1388 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1391 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
ae03c4ec 1392 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
b205914c
GU		 1393
1394 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1395 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1396 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1397 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1400 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1401
740a4a3a 1402 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
b205914c
GU		 1403 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1404 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1405 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
740a4a3a 1406 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
b205914c
GU		 1407 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1408 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
712f36fb 1409 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
20cacae1 1410
b205914c
GU		 1411 /* IPSR17 */
1412 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
b205914c
GU		 1413
1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
eada11ac 1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
b205914c
GU		 1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
ae03c4ec 1418 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
b205914c
GU		 1419
1420 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1421 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1422 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1426 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1427
1428 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1429 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1430 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1432 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1433 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1434
1435 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
740a4a3a 1437 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
b205914c
GU		 1438 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1442 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1443 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1444
1445 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1446 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
740a4a3a 1447 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
b205914c
GU		 1448 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1450 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1454
1455 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1456 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
740a4a3a 1457 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
b205914c 1458 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
50d83156 1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
b205914c
GU		 1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
ae03c4ec 1462 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
b205914c
GU		 1463 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1464 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1465 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1466
1467 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1468 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
740a4a3a 1469 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
b205914c
GU		 1470 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1472 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1473 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1474 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1475 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1476
1477 /* IPSR18 */
f9d13080 1478 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
b205914c 1479 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
740a4a3a 1480 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
b205914c
GU		 1481 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1483 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1484 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1487
f9d13080 1488 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
b205914c 1489 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
740a4a3a 1490 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
b205914c
GU		 1491 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1493 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1496 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
20cacae1 1497
b205914c
GU		 1498/*
1499 * Static pins can not be muxed between different functions but
db701f4b 1500 * still need mark entries in the pinmux list. Add each static
b205914c 1501 * pin to the list without an associated function. The sh-pfc
db701f4b
GU		 1502 * core will do the right thing and skip trying to mux the pin
1503 * while still applying configuration to it.
b205914c
GU		 1504 */
1505#define FM(x) PINMUX_DATA(x##_MARK, 0),
1506 PINMUX_STATIC
1507#undef FM
9b132ba3
KM		 1508};
1509
b205914c 1510/*
ecd54509 1511 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
b205914c
GU		 1512 * Physical layout rows: A - AW, cols: 1 - 39.
1513 */
1514#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1515#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1516#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
6f4b74f3 1517#define PIN_NONE U16_MAX
b205914c
GU		 1518
1519static const struct sh_pfc_pin pinmux_pins[] = {
1520 PINMUX_GPIO_GP_ALL(),
76250a6c 1521
b205914c
GU		 1522 /*
1523 * Pins not associated with a GPIO port.
1524 *
1525 * The pin positions are different between different r8a7795
1526 * packages, all that is needed for the pfc driver is a unique
1527 * number for each pin. To this end use the pin layout from
1528 * R-Car H3SiP to calculate a unique number for each pin.
1529 */
1530 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
b205914c
GU		 1545 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
76250a6c
TK		 1573};
1574
55bfea9f
KM		 1575/* - AUDIO CLOCK ------------------------------------------------------------ */
1576static const unsigned int audio_clk_a_a_pins[] = {
1577 /* CLK A */
1578 RCAR_GP_PIN(6, 22),
1579};
1580static const unsigned int audio_clk_a_a_mux[] = {
1581 AUDIO_CLKA_A_MARK,
1582};
1583static const unsigned int audio_clk_a_b_pins[] = {
1584 /* CLK A */
1585 RCAR_GP_PIN(5, 4),
1586};
1587static const unsigned int audio_clk_a_b_mux[] = {
1588 AUDIO_CLKA_B_MARK,
1589};
1590static const unsigned int audio_clk_a_c_pins[] = {
1591 /* CLK A */
1592 RCAR_GP_PIN(5, 19),
1593};
1594static const unsigned int audio_clk_a_c_mux[] = {
1595 AUDIO_CLKA_C_MARK,
1596};
1597static const unsigned int audio_clk_b_a_pins[] = {
1598 /* CLK B */
1599 RCAR_GP_PIN(5, 12),
1600};
1601static const unsigned int audio_clk_b_a_mux[] = {
1602 AUDIO_CLKB_A_MARK,
1603};
1604static const unsigned int audio_clk_b_b_pins[] = {
1605 /* CLK B */
1606 RCAR_GP_PIN(6, 23),
1607};
1608static const unsigned int audio_clk_b_b_mux[] = {
1609 AUDIO_CLKB_B_MARK,
1610};
1611static const unsigned int audio_clk_c_a_pins[] = {
1612 /* CLK C */
1613 RCAR_GP_PIN(5, 21),
1614};
1615static const unsigned int audio_clk_c_a_mux[] = {
1616 AUDIO_CLKC_A_MARK,
1617};
1618static const unsigned int audio_clk_c_b_pins[] = {
1619 /* CLK C */
1620 RCAR_GP_PIN(5, 0),
1621};
1622static const unsigned int audio_clk_c_b_mux[] = {
1623 AUDIO_CLKC_B_MARK,
1624};
1625static const unsigned int audio_clkout_a_pins[] = {
1626 /* CLKOUT */
1627 RCAR_GP_PIN(5, 18),
1628};
1629static const unsigned int audio_clkout_a_mux[] = {
1630 AUDIO_CLKOUT_A_MARK,
1631};
1632static const unsigned int audio_clkout_b_pins[] = {
1633 /* CLKOUT */
1634 RCAR_GP_PIN(6, 28),
1635};
1636static const unsigned int audio_clkout_b_mux[] = {
1637 AUDIO_CLKOUT_B_MARK,
1638};
1639static const unsigned int audio_clkout_c_pins[] = {
1640 /* CLKOUT */
1641 RCAR_GP_PIN(5, 3),
1642};
1643static const unsigned int audio_clkout_c_mux[] = {
1644 AUDIO_CLKOUT_C_MARK,
1645};
1646static const unsigned int audio_clkout_d_pins[] = {
1647 /* CLKOUT */
1648 RCAR_GP_PIN(5, 21),
1649};
1650static const unsigned int audio_clkout_d_mux[] = {
1651 AUDIO_CLKOUT_D_MARK,
1652};
1653static const unsigned int audio_clkout1_a_pins[] = {
1654 /* CLKOUT1 */
1655 RCAR_GP_PIN(5, 15),
1656};
1657static const unsigned int audio_clkout1_a_mux[] = {
1658 AUDIO_CLKOUT1_A_MARK,
1659};
1660static const unsigned int audio_clkout1_b_pins[] = {
1661 /* CLKOUT1 */
1662 RCAR_GP_PIN(6, 29),
1663};
1664static const unsigned int audio_clkout1_b_mux[] = {
1665 AUDIO_CLKOUT1_B_MARK,
1666};
1667static const unsigned int audio_clkout2_a_pins[] = {
1668 /* CLKOUT2 */
1669 RCAR_GP_PIN(5, 16),
1670};
1671static const unsigned int audio_clkout2_a_mux[] = {
1672 AUDIO_CLKOUT2_A_MARK,
1673};
1674static const unsigned int audio_clkout2_b_pins[] = {
1675 /* CLKOUT2 */
1676 RCAR_GP_PIN(6, 30),
1677};
1678static const unsigned int audio_clkout2_b_mux[] = {
1679 AUDIO_CLKOUT2_B_MARK,
1680};
1681static const unsigned int audio_clkout3_a_pins[] = {
1682 /* CLKOUT3 */
1683 RCAR_GP_PIN(5, 19),
1684};
1685static const unsigned int audio_clkout3_a_mux[] = {
1686 AUDIO_CLKOUT3_A_MARK,
1687};
1688static const unsigned int audio_clkout3_b_pins[] = {
1689 /* CLKOUT3 */
1690 RCAR_GP_PIN(6, 31),
1691};
1692static const unsigned int audio_clkout3_b_mux[] = {
1693 AUDIO_CLKOUT3_B_MARK,
1694};
1695
30c078de
GU		 1696/* - EtherAVB --------------------------------------------------------------- */
1697static const unsigned int avb_link_pins[] = {
1698 /* AVB_LINK */
1699 RCAR_GP_PIN(2, 12),
1700};
1701static const unsigned int avb_link_mux[] = {
1702 AVB_LINK_MARK,
1703};
1704static const unsigned int avb_magic_pins[] = {
1705 /* AVB_MAGIC_ */
1706 RCAR_GP_PIN(2, 10),
1707};
1708static const unsigned int avb_magic_mux[] = {
1709 AVB_MAGIC_MARK,
1710};
1711static const unsigned int avb_phy_int_pins[] = {
1712 /* AVB_PHY_INT */
1713 RCAR_GP_PIN(2, 11),
1714};
1715static const unsigned int avb_phy_int_mux[] = {
1716 AVB_PHY_INT_MARK,
1717};
cbe0dd9a 1718static const unsigned int avb_mdio_pins[] = {
30c078de
GU		 1719 /* AVB_MDC, AVB_MDIO */
1720 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1721};
cbe0dd9a 1722static const unsigned int avb_mdio_mux[] = {
30c078de
GU		 1723 AVB_MDC_MARK, AVB_MDIO_MARK,
1724};
1725static const unsigned int avb_mii_pins[] = {
1726 /*
1727 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1728 * AVB_TD1, AVB_TD2, AVB_TD3,
1729 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1730 * AVB_RD1, AVB_RD2, AVB_RD3,
1731 * AVB_TXCREFCLK
1732 */
1733 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1734 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1735 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1736 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1737 PIN_NUMBER('A', 12),
1738
1739};
1740static const unsigned int avb_mii_mux[] = {
1741 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1742 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1743 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1744 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1745 AVB_TXCREFCLK_MARK,
1746};
1747static const unsigned int avb_avtp_pps_pins[] = {
1748 /* AVB_AVTP_PPS */
1749 RCAR_GP_PIN(2, 6),
1750};
1751static const unsigned int avb_avtp_pps_mux[] = {
1752 AVB_AVTP_PPS_MARK,
1753};
1754static const unsigned int avb_avtp_match_a_pins[] = {
1755 /* AVB_AVTP_MATCH_A */
1756 RCAR_GP_PIN(2, 13),
1757};
1758static const unsigned int avb_avtp_match_a_mux[] = {
1759 AVB_AVTP_MATCH_A_MARK,
1760};
1761static const unsigned int avb_avtp_capture_a_pins[] = {
1762 /* AVB_AVTP_CAPTURE_A */
1763 RCAR_GP_PIN(2, 14),
1764};
1765static const unsigned int avb_avtp_capture_a_mux[] = {
1766 AVB_AVTP_CAPTURE_A_MARK,
1767};
1768static const unsigned int avb_avtp_match_b_pins[] = {
1769 /* AVB_AVTP_MATCH_B */
1770 RCAR_GP_PIN(1, 8),
1771};
1772static const unsigned int avb_avtp_match_b_mux[] = {
1773 AVB_AVTP_MATCH_B_MARK,
1774};
1775static const unsigned int avb_avtp_capture_b_pins[] = {
1776 /* AVB_AVTP_CAPTURE_B */
1777 RCAR_GP_PIN(1, 11),
1778};
1779static const unsigned int avb_avtp_capture_b_mux[] = {
1780 AVB_AVTP_CAPTURE_B_MARK,
1781};
1782
a678abfe
RS		 1783/* - CAN ------------------------------------------------------------------ */
1784static const unsigned int can0_data_a_pins[] = {
1785 /* TX, RX */
1786 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1787};
1788static const unsigned int can0_data_a_mux[] = {
1789 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1790};
1791static const unsigned int can0_data_b_pins[] = {
1792 /* TX, RX */
1793 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1794};
1795static const unsigned int can0_data_b_mux[] = {
1796 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1797};
1798static const unsigned int can1_data_pins[] = {
1799 /* TX, RX */
1800 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1801};
1802static const unsigned int can1_data_mux[] = {
1803 CAN1_TX_MARK, CAN1_RX_MARK,
1804};
1805
1806/* - CAN Clock -------------------------------------------------------------- */
1807static const unsigned int can_clk_pins[] = {
1808 /* CLK */
1809 RCAR_GP_PIN(1, 25),
1810};
1811static const unsigned int can_clk_mux[] = {
1812 CAN_CLK_MARK,
1813};
1814
0e1c7a94
RS		 1815/* - CAN FD --------------------------------------------------------------- */
1816static const unsigned int canfd0_data_a_pins[] = {
1817 /* TX, RX */
1818 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1819};
1820static const unsigned int canfd0_data_a_mux[] = {
1821 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1822};
1823static const unsigned int canfd0_data_b_pins[] = {
1824 /* TX, RX */
1825 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1826};
1827static const unsigned int canfd0_data_b_mux[] = {
1828 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1829};
1830static const unsigned int canfd1_data_pins[] = {
1831 /* TX, RX */
1832 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1833};
1834static const unsigned int canfd1_data_mux[] = {
1835 CANFD1_TX_MARK, CANFD1_RX_MARK,
1836};
1837
641b0ab8
DB		 1838/* - DRIF0 --------------------------------------------------------------- */
1839static const unsigned int drif0_ctrl_a_pins[] = {
1840 /* CLK, SYNC */
1841 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1842};
1843static const unsigned int drif0_ctrl_a_mux[] = {
1844 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1845};
1846static const unsigned int drif0_data0_a_pins[] = {
1847 /* D0 */
1848 RCAR_GP_PIN(6, 10),
1849};
1850static const unsigned int drif0_data0_a_mux[] = {
1851 RIF0_D0_A_MARK,
1852};
1853static const unsigned int drif0_data1_a_pins[] = {
1854 /* D1 */
1855 RCAR_GP_PIN(6, 7),
1856};
1857static const unsigned int drif0_data1_a_mux[] = {
1858 RIF0_D1_A_MARK,
1859};
1860static const unsigned int drif0_ctrl_b_pins[] = {
1861 /* CLK, SYNC */
1862 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1863};
1864static const unsigned int drif0_ctrl_b_mux[] = {
1865 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1866};
1867static const unsigned int drif0_data0_b_pins[] = {
1868 /* D0 */
1869 RCAR_GP_PIN(5, 1),
1870};
1871static const unsigned int drif0_data0_b_mux[] = {
1872 RIF0_D0_B_MARK,
1873};
1874static const unsigned int drif0_data1_b_pins[] = {
1875 /* D1 */
1876 RCAR_GP_PIN(5, 2),
1877};
1878static const unsigned int drif0_data1_b_mux[] = {
1879 RIF0_D1_B_MARK,
1880};
1881static const unsigned int drif0_ctrl_c_pins[] = {
1882 /* CLK, SYNC */
1883 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1884};
1885static const unsigned int drif0_ctrl_c_mux[] = {
1886 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1887};
1888static const unsigned int drif0_data0_c_pins[] = {
1889 /* D0 */
1890 RCAR_GP_PIN(5, 13),
1891};
1892static const unsigned int drif0_data0_c_mux[] = {
1893 RIF0_D0_C_MARK,
1894};
1895static const unsigned int drif0_data1_c_pins[] = {
1896 /* D1 */
1897 RCAR_GP_PIN(5, 14),
1898};
1899static const unsigned int drif0_data1_c_mux[] = {
1900 RIF0_D1_C_MARK,
1901};
1902/* - DRIF1 --------------------------------------------------------------- */
1903static const unsigned int drif1_ctrl_a_pins[] = {
1904 /* CLK, SYNC */
1905 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1906};
1907static const unsigned int drif1_ctrl_a_mux[] = {
1908 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1909};
1910static const unsigned int drif1_data0_a_pins[] = {
1911 /* D0 */
1912 RCAR_GP_PIN(6, 19),
1913};
1914static const unsigned int drif1_data0_a_mux[] = {
1915 RIF1_D0_A_MARK,
1916};
1917static const unsigned int drif1_data1_a_pins[] = {
1918 /* D1 */
1919 RCAR_GP_PIN(6, 20),
1920};
1921static const unsigned int drif1_data1_a_mux[] = {
1922 RIF1_D1_A_MARK,
1923};
1924static const unsigned int drif1_ctrl_b_pins[] = {
1925 /* CLK, SYNC */
1926 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1927};
1928static const unsigned int drif1_ctrl_b_mux[] = {
1929 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1930};
1931static const unsigned int drif1_data0_b_pins[] = {
1932 /* D0 */
1933 RCAR_GP_PIN(5, 7),
1934};
1935static const unsigned int drif1_data0_b_mux[] = {
1936 RIF1_D0_B_MARK,
1937};
1938static const unsigned int drif1_data1_b_pins[] = {
1939 /* D1 */
1940 RCAR_GP_PIN(5, 8),
1941};
1942static const unsigned int drif1_data1_b_mux[] = {
1943 RIF1_D1_B_MARK,
1944};
1945static const unsigned int drif1_ctrl_c_pins[] = {
1946 /* CLK, SYNC */
1947 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1948};
1949static const unsigned int drif1_ctrl_c_mux[] = {
1950 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1951};
1952static const unsigned int drif1_data0_c_pins[] = {
1953 /* D0 */
1954 RCAR_GP_PIN(5, 6),
1955};
1956static const unsigned int drif1_data0_c_mux[] = {
1957 RIF1_D0_C_MARK,
1958};
1959static const unsigned int drif1_data1_c_pins[] = {
1960 /* D1 */
1961 RCAR_GP_PIN(5, 10),
1962};
1963static const unsigned int drif1_data1_c_mux[] = {
1964 RIF1_D1_C_MARK,
1965};
1966/* - DRIF2 --------------------------------------------------------------- */
1967static const unsigned int drif2_ctrl_a_pins[] = {
1968 /* CLK, SYNC */
1969 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1970};
1971static const unsigned int drif2_ctrl_a_mux[] = {
1972 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1973};
1974static const unsigned int drif2_data0_a_pins[] = {
1975 /* D0 */
1976 RCAR_GP_PIN(6, 7),
1977};
1978static const unsigned int drif2_data0_a_mux[] = {
1979 RIF2_D0_A_MARK,
1980};
1981static const unsigned int drif2_data1_a_pins[] = {
1982 /* D1 */
1983 RCAR_GP_PIN(6, 10),
1984};
1985static const unsigned int drif2_data1_a_mux[] = {
1986 RIF2_D1_A_MARK,
1987};
1988static const unsigned int drif2_ctrl_b_pins[] = {
1989 /* CLK, SYNC */
1990 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1991};
1992static const unsigned int drif2_ctrl_b_mux[] = {
1993 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1994};
1995static const unsigned int drif2_data0_b_pins[] = {
1996 /* D0 */
1997 RCAR_GP_PIN(6, 30),
1998};
1999static const unsigned int drif2_data0_b_mux[] = {
2000 RIF2_D0_B_MARK,
2001};
2002static const unsigned int drif2_data1_b_pins[] = {
2003 /* D1 */
2004 RCAR_GP_PIN(6, 31),
2005};
2006static const unsigned int drif2_data1_b_mux[] = {
2007 RIF2_D1_B_MARK,
2008};
2009/* - DRIF3 --------------------------------------------------------------- */
2010static const unsigned int drif3_ctrl_a_pins[] = {
2011 /* CLK, SYNC */
2012 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2013};
2014static const unsigned int drif3_ctrl_a_mux[] = {
2015 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2016};
2017static const unsigned int drif3_data0_a_pins[] = {
2018 /* D0 */
2019 RCAR_GP_PIN(6, 19),
2020};
2021static const unsigned int drif3_data0_a_mux[] = {
2022 RIF3_D0_A_MARK,
2023};
2024static const unsigned int drif3_data1_a_pins[] = {
2025 /* D1 */
2026 RCAR_GP_PIN(6, 20),
2027};
2028static const unsigned int drif3_data1_a_mux[] = {
2029 RIF3_D1_A_MARK,
2030};
2031static const unsigned int drif3_ctrl_b_pins[] = {
2032 /* CLK, SYNC */
2033 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2034};
2035static const unsigned int drif3_ctrl_b_mux[] = {
2036 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2037};
2038static const unsigned int drif3_data0_b_pins[] = {
2039 /* D0 */
2040 RCAR_GP_PIN(6, 28),
2041};
2042static const unsigned int drif3_data0_b_mux[] = {
2043 RIF3_D0_B_MARK,
2044};
2045static const unsigned int drif3_data1_b_pins[] = {
2046 /* D1 */
2047 RCAR_GP_PIN(6, 29),
2048};
2049static const unsigned int drif3_data1_b_mux[] = {
2050 RIF3_D1_B_MARK,
2051};
2052
a20a6585
LP		 2053/* - DU --------------------------------------------------------------------- */
2054static const unsigned int du_rgb666_pins[] = {
2055 /* R[7:2], G[7:2], B[7:2] */
2056 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2057 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2058 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2059 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2060 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2061 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2062};
2063static const unsigned int du_rgb666_mux[] = {
2064 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2065 DU_DR3_MARK, DU_DR2_MARK,
2066 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2067 DU_DG3_MARK, DU_DG2_MARK,
2068 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2069 DU_DB3_MARK, DU_DB2_MARK,
2070};
2071static const unsigned int du_rgb888_pins[] = {
2072 /* R[7:0], G[7:0], B[7:0] */
2073 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2074 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2075 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2076 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2077 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2078 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2079 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2080 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2081 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2082};
2083static const unsigned int du_rgb888_mux[] = {
2084 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2085 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2086 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2087 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2088 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2089 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2090};
2091static const unsigned int du_clk_out_0_pins[] = {
2092 /* CLKOUT */
2093 RCAR_GP_PIN(1, 27),
2094};
2095static const unsigned int du_clk_out_0_mux[] = {
2096 DU_DOTCLKOUT0_MARK
2097};
2098static const unsigned int du_clk_out_1_pins[] = {
2099 /* CLKOUT */
2100 RCAR_GP_PIN(2, 3),
2101};
2102static const unsigned int du_clk_out_1_mux[] = {
2103 DU_DOTCLKOUT1_MARK
2104};
2105static const unsigned int du_sync_pins[] = {
2106 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2107 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2108};
2109static const unsigned int du_sync_mux[] = {
2110 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2111};
2112static const unsigned int du_oddf_pins[] = {
2113 /* EXDISP/EXODDF/EXCDE */
2114 RCAR_GP_PIN(2, 2),
2115};
2116static const unsigned int du_oddf_mux[] = {
2117 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2118};
2119static const unsigned int du_cde_pins[] = {
2120 /* CDE */
2121 RCAR_GP_PIN(2, 0),
2122};
2123static const unsigned int du_cde_mux[] = {
2124 DU_CDE_MARK,
2125};
2126static const unsigned int du_disp_pins[] = {
2127 /* DISP */
2128 RCAR_GP_PIN(2, 1),
2129};
2130static const unsigned int du_disp_mux[] = {
2131 DU_DISP_MARK,
2132};
2133
7a362e34
WS		 2134/* - HSCIF0 ----------------------------------------------------------------- */
2135static const unsigned int hscif0_data_pins[] = {
2136 /* RX, TX */
2137 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2138};
2139static const unsigned int hscif0_data_mux[] = {
2140 HRX0_MARK, HTX0_MARK,
2141};
2142static const unsigned int hscif0_clk_pins[] = {
2143 /* SCK */
2144 RCAR_GP_PIN(5, 12),
2145};
2146static const unsigned int hscif0_clk_mux[] = {
2147 HSCK0_MARK,
2148};
2149static const unsigned int hscif0_ctrl_pins[] = {
2150 /* RTS, CTS */
2151 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2152};
2153static const unsigned int hscif0_ctrl_mux[] = {
2154 HRTS0_N_MARK, HCTS0_N_MARK,
2155};
2156/* - HSCIF1 ----------------------------------------------------------------- */
2157static const unsigned int hscif1_data_a_pins[] = {
2158 /* RX, TX */
2159 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2160};
2161static const unsigned int hscif1_data_a_mux[] = {
2162 HRX1_A_MARK, HTX1_A_MARK,
2163};
2164static const unsigned int hscif1_clk_a_pins[] = {
2165 /* SCK */
2166 RCAR_GP_PIN(6, 21),
2167};
2168static const unsigned int hscif1_clk_a_mux[] = {
2169 HSCK1_A_MARK,
2170};
2171static const unsigned int hscif1_ctrl_a_pins[] = {
2172 /* RTS, CTS */
2173 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2174};
2175static const unsigned int hscif1_ctrl_a_mux[] = {
2176 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2177};
2178
2179static const unsigned int hscif1_data_b_pins[] = {
2180 /* RX, TX */
2181 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2182};
2183static const unsigned int hscif1_data_b_mux[] = {
2184 HRX1_B_MARK, HTX1_B_MARK,
2185};
2186static const unsigned int hscif1_clk_b_pins[] = {
2187 /* SCK */
2188 RCAR_GP_PIN(5, 0),
2189};
2190static const unsigned int hscif1_clk_b_mux[] = {
2191 HSCK1_B_MARK,
2192};
2193static const unsigned int hscif1_ctrl_b_pins[] = {
2194 /* RTS, CTS */
2195 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2196};
2197static const unsigned int hscif1_ctrl_b_mux[] = {
2198 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2199};
2200/* - HSCIF2 ----------------------------------------------------------------- */
2201static const unsigned int hscif2_data_a_pins[] = {
2202 /* RX, TX */
2203 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2204};
2205static const unsigned int hscif2_data_a_mux[] = {
2206 HRX2_A_MARK, HTX2_A_MARK,
2207};
2208static const unsigned int hscif2_clk_a_pins[] = {
2209 /* SCK */
2210 RCAR_GP_PIN(6, 10),
2211};
2212static const unsigned int hscif2_clk_a_mux[] = {
2213 HSCK2_A_MARK,
2214};
2215static const unsigned int hscif2_ctrl_a_pins[] = {
2216 /* RTS, CTS */
2217 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2218};
2219static const unsigned int hscif2_ctrl_a_mux[] = {
2220 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2221};
2222
2223static const unsigned int hscif2_data_b_pins[] = {
2224 /* RX, TX */
2225 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2226};
2227static const unsigned int hscif2_data_b_mux[] = {
2228 HRX2_B_MARK, HTX2_B_MARK,
2229};
2230static const unsigned int hscif2_clk_b_pins[] = {
2231 /* SCK */
2232 RCAR_GP_PIN(6, 21),
2233};
2234static const unsigned int hscif2_clk_b_mux[] = {
2235 HSCK2_B_MARK,
2236};
2237static const unsigned int hscif2_ctrl_b_pins[] = {
2238 /* RTS, CTS */
2239 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2240};
2241static const unsigned int hscif2_ctrl_b_mux[] = {
2242 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2243};
2244
2245static const unsigned int hscif2_data_c_pins[] = {
2246 /* RX, TX */
2247 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2248};
2249static const unsigned int hscif2_data_c_mux[] = {
2250 HRX2_C_MARK, HTX2_C_MARK,
2251};
2252static const unsigned int hscif2_clk_c_pins[] = {
2253 /* SCK */
2254 RCAR_GP_PIN(6, 24),
2255};
2256static const unsigned int hscif2_clk_c_mux[] = {
2257 HSCK2_C_MARK,
2258};
2259static const unsigned int hscif2_ctrl_c_pins[] = {
2260 /* RTS, CTS */
2261 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2262};
2263static const unsigned int hscif2_ctrl_c_mux[] = {
2264 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2265};
2266/* - HSCIF3 ----------------------------------------------------------------- */
2267static const unsigned int hscif3_data_a_pins[] = {
2268 /* RX, TX */
2269 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2270};
2271static const unsigned int hscif3_data_a_mux[] = {
2272 HRX3_A_MARK, HTX3_A_MARK,
2273};
2274static const unsigned int hscif3_clk_pins[] = {
2275 /* SCK */
2276 RCAR_GP_PIN(1, 22),
2277};
2278static const unsigned int hscif3_clk_mux[] = {
2279 HSCK3_MARK,
2280};
2281static const unsigned int hscif3_ctrl_pins[] = {
2282 /* RTS, CTS */
2283 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2284};
2285static const unsigned int hscif3_ctrl_mux[] = {
2286 HRTS3_N_MARK, HCTS3_N_MARK,
2287};
2288
2289static const unsigned int hscif3_data_b_pins[] = {
2290 /* RX, TX */
2291 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2292};
2293static const unsigned int hscif3_data_b_mux[] = {
2294 HRX3_B_MARK, HTX3_B_MARK,
2295};
2296static const unsigned int hscif3_data_c_pins[] = {
2297 /* RX, TX */
2298 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2299};
2300static const unsigned int hscif3_data_c_mux[] = {
2301 HRX3_C_MARK, HTX3_C_MARK,
2302};
2303static const unsigned int hscif3_data_d_pins[] = {
2304 /* RX, TX */
2305 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2306};
2307static const unsigned int hscif3_data_d_mux[] = {
2308 HRX3_D_MARK, HTX3_D_MARK,
2309};
2310/* - HSCIF4 ----------------------------------------------------------------- */
2311static const unsigned int hscif4_data_a_pins[] = {
2312 /* RX, TX */
2313 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2314};
2315static const unsigned int hscif4_data_a_mux[] = {
2316 HRX4_A_MARK, HTX4_A_MARK,
2317};
2318static const unsigned int hscif4_clk_pins[] = {
2319 /* SCK */
2320 RCAR_GP_PIN(1, 11),
2321};
2322static const unsigned int hscif4_clk_mux[] = {
2323 HSCK4_MARK,
2324};
2325static const unsigned int hscif4_ctrl_pins[] = {
2326 /* RTS, CTS */
2327 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2328};
2329static const unsigned int hscif4_ctrl_mux[] = {
2330 HRTS4_N_MARK, HCTS4_N_MARK,
2331};
2332
2333static const unsigned int hscif4_data_b_pins[] = {
2334 /* RX, TX */
2335 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2336};
2337static const unsigned int hscif4_data_b_mux[] = {
2338 HRX4_B_MARK, HTX4_B_MARK,
2339};
2340
f62d4c9e 2341/* - I2C -------------------------------------------------------------------- */
100431b6
TK		 2342static const unsigned int i2c0_pins[] = {
2343 /* SCL, SDA */
2344 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2345};
2346
2347static const unsigned int i2c0_mux[] = {
2348 SCL0_MARK, SDA0_MARK,
2349};
2350
f62d4c9e
WS		 2351static const unsigned int i2c1_a_pins[] = {
2352 /* SDA, SCL */
2353 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2354};
2355static const unsigned int i2c1_a_mux[] = {
2356 SDA1_A_MARK, SCL1_A_MARK,
2357};
2358static const unsigned int i2c1_b_pins[] = {
2359 /* SDA, SCL */
2360 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2361};
2362static const unsigned int i2c1_b_mux[] = {
2363 SDA1_B_MARK, SCL1_B_MARK,
2364};
2365static const unsigned int i2c2_a_pins[] = {
2366 /* SDA, SCL */
2367 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2368};
2369static const unsigned int i2c2_a_mux[] = {
2370 SDA2_A_MARK, SCL2_A_MARK,
2371};
2372static const unsigned int i2c2_b_pins[] = {
2373 /* SDA, SCL */
2374 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2375};
2376static const unsigned int i2c2_b_mux[] = {
2377 SDA2_B_MARK, SCL2_B_MARK,
2378};
100431b6
TK		 2379
2380static const unsigned int i2c3_pins[] = {
2381 /* SCL, SDA */
2382 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2383};
2384
2385static const unsigned int i2c3_mux[] = {
2386 SCL3_MARK, SDA3_MARK,
2387};
2388
2389static const unsigned int i2c5_pins[] = {
2390 /* SCL, SDA */
2391 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2392};
2393
2394static const unsigned int i2c5_mux[] = {
2395 SCL5_MARK, SDA5_MARK,
2396};
2397
f62d4c9e
WS		 2398static const unsigned int i2c6_a_pins[] = {
2399 /* SDA, SCL */
2400 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2401};
2402static const unsigned int i2c6_a_mux[] = {
2403 SDA6_A_MARK, SCL6_A_MARK,
2404};
2405static const unsigned int i2c6_b_pins[] = {
2406 /* SDA, SCL */
2407 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2408};
2409static const unsigned int i2c6_b_mux[] = {
2410 SDA6_B_MARK, SCL6_B_MARK,
2411};
2412static const unsigned int i2c6_c_pins[] = {
2413 /* SDA, SCL */
2414 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2415};
2416static const unsigned int i2c6_c_mux[] = {
2417 SDA6_C_MARK, SCL6_C_MARK,
2418};
2419
8480e6ca
GU		 2420/* - INTC-EX ---------------------------------------------------------------- */
2421static const unsigned int intc_ex_irq0_pins[] = {
2422 /* IRQ0 */
2423 RCAR_GP_PIN(2, 0),
2424};
2425static const unsigned int intc_ex_irq0_mux[] = {
2426 IRQ0_MARK,
2427};
2428static const unsigned int intc_ex_irq1_pins[] = {
2429 /* IRQ1 */
2430 RCAR_GP_PIN(2, 1),
2431};
2432static const unsigned int intc_ex_irq1_mux[] = {
2433 IRQ1_MARK,
2434};
2435static const unsigned int intc_ex_irq2_pins[] = {
2436 /* IRQ2 */
2437 RCAR_GP_PIN(2, 2),
2438};
2439static const unsigned int intc_ex_irq2_mux[] = {
2440 IRQ2_MARK,
2441};
2442static const unsigned int intc_ex_irq3_pins[] = {
2443 /* IRQ3 */
2444 RCAR_GP_PIN(2, 3),
2445};
2446static const unsigned int intc_ex_irq3_mux[] = {
2447 IRQ3_MARK,
2448};
2449static const unsigned int intc_ex_irq4_pins[] = {
2450 /* IRQ4 */
2451 RCAR_GP_PIN(2, 4),
2452};
2453static const unsigned int intc_ex_irq4_mux[] = {
2454 IRQ4_MARK,
2455};
2456static const unsigned int intc_ex_irq5_pins[] = {
2457 /* IRQ5 */
2458 RCAR_GP_PIN(2, 5),
2459};
2460static const unsigned int intc_ex_irq5_mux[] = {
2461 IRQ5_MARK,
2462};
2463
3e6c7727
GU		 2464/* - MSIOF0 ----------------------------------------------------------------- */
2465static const unsigned int msiof0_clk_pins[] = {
2466 /* SCK */
2467 RCAR_GP_PIN(5, 17),
2468};
2469static const unsigned int msiof0_clk_mux[] = {
2470 MSIOF0_SCK_MARK,
2471};
2472static const unsigned int msiof0_sync_pins[] = {
2473 /* SYNC */
2474 RCAR_GP_PIN(5, 18),
2475};
2476static const unsigned int msiof0_sync_mux[] = {
2477 MSIOF0_SYNC_MARK,
2478};
2479static const unsigned int msiof0_ss1_pins[] = {
2480 /* SS1 */
2481 RCAR_GP_PIN(5, 19),
2482};
2483static const unsigned int msiof0_ss1_mux[] = {
2484 MSIOF0_SS1_MARK,
2485};
2486static const unsigned int msiof0_ss2_pins[] = {
2487 /* SS2 */
2488 RCAR_GP_PIN(5, 21),
2489};
2490static const unsigned int msiof0_ss2_mux[] = {
2491 MSIOF0_SS2_MARK,
2492};
2493static const unsigned int msiof0_txd_pins[] = {
2494 /* TXD */
2495 RCAR_GP_PIN(5, 20),
2496};
2497static const unsigned int msiof0_txd_mux[] = {
2498 MSIOF0_TXD_MARK,
2499};
2500static const unsigned int msiof0_rxd_pins[] = {
2501 /* RXD */
2502 RCAR_GP_PIN(5, 22),
2503};
2504static const unsigned int msiof0_rxd_mux[] = {
2505 MSIOF0_RXD_MARK,
2506};
2507/* - MSIOF1 ----------------------------------------------------------------- */
2508static const unsigned int msiof1_clk_a_pins[] = {
2509 /* SCK */
2510 RCAR_GP_PIN(6, 8),
2511};
2512static const unsigned int msiof1_clk_a_mux[] = {
2513 MSIOF1_SCK_A_MARK,
2514};
2515static const unsigned int msiof1_sync_a_pins[] = {
2516 /* SYNC */
2517 RCAR_GP_PIN(6, 9),
2518};
2519static const unsigned int msiof1_sync_a_mux[] = {
2520 MSIOF1_SYNC_A_MARK,
2521};
2522static const unsigned int msiof1_ss1_a_pins[] = {
2523 /* SS1 */
2524 RCAR_GP_PIN(6, 5),
2525};
2526static const unsigned int msiof1_ss1_a_mux[] = {
2527 MSIOF1_SS1_A_MARK,
2528};
2529static const unsigned int msiof1_ss2_a_pins[] = {
2530 /* SS2 */
2531 RCAR_GP_PIN(6, 6),
2532};
2533static const unsigned int msiof1_ss2_a_mux[] = {
2534 MSIOF1_SS2_A_MARK,
2535};
2536static const unsigned int msiof1_txd_a_pins[] = {
2537 /* TXD */
2538 RCAR_GP_PIN(6, 7),
2539};
2540static const unsigned int msiof1_txd_a_mux[] = {
2541 MSIOF1_TXD_A_MARK,
2542};
2543static const unsigned int msiof1_rxd_a_pins[] = {
2544 /* RXD */
2545 RCAR_GP_PIN(6, 10),
2546};
2547static const unsigned int msiof1_rxd_a_mux[] = {
2548 MSIOF1_RXD_A_MARK,
2549};
2550static const unsigned int msiof1_clk_b_pins[] = {
2551 /* SCK */
2552 RCAR_GP_PIN(5, 9),
2553};
2554static const unsigned int msiof1_clk_b_mux[] = {
2555 MSIOF1_SCK_B_MARK,
2556};
2557static const unsigned int msiof1_sync_b_pins[] = {
2558 /* SYNC */
2559 RCAR_GP_PIN(5, 3),
2560};
2561static const unsigned int msiof1_sync_b_mux[] = {
2562 MSIOF1_SYNC_B_MARK,
2563};
2564static const unsigned int msiof1_ss1_b_pins[] = {
2565 /* SS1 */
2566 RCAR_GP_PIN(5, 4),
2567};
2568static const unsigned int msiof1_ss1_b_mux[] = {
2569 MSIOF1_SS1_B_MARK,
2570};
2571static const unsigned int msiof1_ss2_b_pins[] = {
2572 /* SS2 */
2573 RCAR_GP_PIN(5, 0),
2574};
2575static const unsigned int msiof1_ss2_b_mux[] = {
2576 MSIOF1_SS2_B_MARK,
2577};
2578static const unsigned int msiof1_txd_b_pins[] = {
2579 /* TXD */
2580 RCAR_GP_PIN(5, 8),
2581};
2582static const unsigned int msiof1_txd_b_mux[] = {
2583 MSIOF1_TXD_B_MARK,
2584};
2585static const unsigned int msiof1_rxd_b_pins[] = {
2586 /* RXD */
2587 RCAR_GP_PIN(5, 7),
2588};
2589static const unsigned int msiof1_rxd_b_mux[] = {
2590 MSIOF1_RXD_B_MARK,
2591};
2592static const unsigned int msiof1_clk_c_pins[] = {
2593 /* SCK */
2594 RCAR_GP_PIN(6, 17),
2595};
2596static const unsigned int msiof1_clk_c_mux[] = {
2597 MSIOF1_SCK_C_MARK,
2598};
2599static const unsigned int msiof1_sync_c_pins[] = {
2600 /* SYNC */
2601 RCAR_GP_PIN(6, 18),
2602};
2603static const unsigned int msiof1_sync_c_mux[] = {
2604 MSIOF1_SYNC_C_MARK,
2605};
2606static const unsigned int msiof1_ss1_c_pins[] = {
2607 /* SS1 */
2608 RCAR_GP_PIN(6, 21),
2609};
2610static const unsigned int msiof1_ss1_c_mux[] = {
2611 MSIOF1_SS1_C_MARK,
2612};
2613static const unsigned int msiof1_ss2_c_pins[] = {
2614 /* SS2 */
2615 RCAR_GP_PIN(6, 27),
2616};
2617static const unsigned int msiof1_ss2_c_mux[] = {
2618 MSIOF1_SS2_C_MARK,
2619};
2620static const unsigned int msiof1_txd_c_pins[] = {
2621 /* TXD */
2622 RCAR_GP_PIN(6, 20),
2623};
2624static const unsigned int msiof1_txd_c_mux[] = {
2625 MSIOF1_TXD_C_MARK,
2626};
2627static const unsigned int msiof1_rxd_c_pins[] = {
2628 /* RXD */
2629 RCAR_GP_PIN(6, 19),
2630};
2631static const unsigned int msiof1_rxd_c_mux[] = {
2632 MSIOF1_RXD_C_MARK,
2633};
2634static const unsigned int msiof1_clk_d_pins[] = {
2635 /* SCK */
2636 RCAR_GP_PIN(5, 12),
2637};
2638static const unsigned int msiof1_clk_d_mux[] = {
2639 MSIOF1_SCK_D_MARK,
2640};
2641static const unsigned int msiof1_sync_d_pins[] = {
2642 /* SYNC */
2643 RCAR_GP_PIN(5, 15),
2644};
2645static const unsigned int msiof1_sync_d_mux[] = {
2646 MSIOF1_SYNC_D_MARK,
2647};
2648static const unsigned int msiof1_ss1_d_pins[] = {
2649 /* SS1 */
2650 RCAR_GP_PIN(5, 16),
2651};
2652static const unsigned int msiof1_ss1_d_mux[] = {
2653 MSIOF1_SS1_D_MARK,
2654};
2655static const unsigned int msiof1_ss2_d_pins[] = {
2656 /* SS2 */
2657 RCAR_GP_PIN(5, 21),
2658};
2659static const unsigned int msiof1_ss2_d_mux[] = {
2660 MSIOF1_SS2_D_MARK,
2661};
2662static const unsigned int msiof1_txd_d_pins[] = {
2663 /* TXD */
2664 RCAR_GP_PIN(5, 14),
2665};
2666static const unsigned int msiof1_txd_d_mux[] = {
2667 MSIOF1_TXD_D_MARK,
2668};
2669static const unsigned int msiof1_rxd_d_pins[] = {
2670 /* RXD */
2671 RCAR_GP_PIN(5, 13),
2672};
2673static const unsigned int msiof1_rxd_d_mux[] = {
2674 MSIOF1_RXD_D_MARK,
2675};
2676static const unsigned int msiof1_clk_e_pins[] = {
2677 /* SCK */
2678 RCAR_GP_PIN(3, 0),
2679};
2680static const unsigned int msiof1_clk_e_mux[] = {
2681 MSIOF1_SCK_E_MARK,
2682};
2683static const unsigned int msiof1_sync_e_pins[] = {
2684 /* SYNC */
2685 RCAR_GP_PIN(3, 1),
2686};
2687static const unsigned int msiof1_sync_e_mux[] = {
2688 MSIOF1_SYNC_E_MARK,
2689};
2690static const unsigned int msiof1_ss1_e_pins[] = {
2691 /* SS1 */
2692 RCAR_GP_PIN(3, 4),
2693};
2694static const unsigned int msiof1_ss1_e_mux[] = {
2695 MSIOF1_SS1_E_MARK,
2696};
2697static const unsigned int msiof1_ss2_e_pins[] = {
2698 /* SS2 */
2699 RCAR_GP_PIN(3, 5),
2700};
2701static const unsigned int msiof1_ss2_e_mux[] = {
2702 MSIOF1_SS2_E_MARK,
2703};
2704static const unsigned int msiof1_txd_e_pins[] = {
2705 /* TXD */
2706 RCAR_GP_PIN(3, 3),
2707};
2708static const unsigned int msiof1_txd_e_mux[] = {
2709 MSIOF1_TXD_E_MARK,
2710};
2711static const unsigned int msiof1_rxd_e_pins[] = {
2712 /* RXD */
2713 RCAR_GP_PIN(3, 2),
2714};
2715static const unsigned int msiof1_rxd_e_mux[] = {
2716 MSIOF1_RXD_E_MARK,
2717};
2718static const unsigned int msiof1_clk_f_pins[] = {
2719 /* SCK */
2720 RCAR_GP_PIN(5, 23),
2721};
2722static const unsigned int msiof1_clk_f_mux[] = {
2723 MSIOF1_SCK_F_MARK,
2724};
2725static const unsigned int msiof1_sync_f_pins[] = {
2726 /* SYNC */
2727 RCAR_GP_PIN(5, 24),
2728};
2729static const unsigned int msiof1_sync_f_mux[] = {
2730 MSIOF1_SYNC_F_MARK,
2731};
2732static const unsigned int msiof1_ss1_f_pins[] = {
2733 /* SS1 */
2734 RCAR_GP_PIN(6, 1),
2735};
2736static const unsigned int msiof1_ss1_f_mux[] = {
2737 MSIOF1_SS1_F_MARK,
2738};
2739static const unsigned int msiof1_ss2_f_pins[] = {
2740 /* SS2 */
2741 RCAR_GP_PIN(6, 2),
2742};
2743static const unsigned int msiof1_ss2_f_mux[] = {
2744 MSIOF1_SS2_F_MARK,
2745};
2746static const unsigned int msiof1_txd_f_pins[] = {
2747 /* TXD */
2748 RCAR_GP_PIN(6, 0),
2749};
2750static const unsigned int msiof1_txd_f_mux[] = {
2751 MSIOF1_TXD_F_MARK,
2752};
2753static const unsigned int msiof1_rxd_f_pins[] = {
2754 /* RXD */
2755 RCAR_GP_PIN(5, 25),
2756};
2757static const unsigned int msiof1_rxd_f_mux[] = {
2758 MSIOF1_RXD_F_MARK,
2759};
2760static const unsigned int msiof1_clk_g_pins[] = {
2761 /* SCK */
2762 RCAR_GP_PIN(3, 6),
2763};
2764static const unsigned int msiof1_clk_g_mux[] = {
2765 MSIOF1_SCK_G_MARK,
2766};
2767static const unsigned int msiof1_sync_g_pins[] = {
2768 /* SYNC */
2769 RCAR_GP_PIN(3, 7),
2770};
2771static const unsigned int msiof1_sync_g_mux[] = {
2772 MSIOF1_SYNC_G_MARK,
2773};
2774static const unsigned int msiof1_ss1_g_pins[] = {
2775 /* SS1 */
2776 RCAR_GP_PIN(3, 10),
2777};
2778static const unsigned int msiof1_ss1_g_mux[] = {
2779 MSIOF1_SS1_G_MARK,
2780};
2781static const unsigned int msiof1_ss2_g_pins[] = {
2782 /* SS2 */
2783 RCAR_GP_PIN(3, 11),
2784};
2785static const unsigned int msiof1_ss2_g_mux[] = {
2786 MSIOF1_SS2_G_MARK,
2787};
2788static const unsigned int msiof1_txd_g_pins[] = {
2789 /* TXD */
2790 RCAR_GP_PIN(3, 9),
2791};
2792static const unsigned int msiof1_txd_g_mux[] = {
2793 MSIOF1_TXD_G_MARK,
2794};
2795static const unsigned int msiof1_rxd_g_pins[] = {
2796 /* RXD */
2797 RCAR_GP_PIN(3, 8),
2798};
2799static const unsigned int msiof1_rxd_g_mux[] = {
2800 MSIOF1_RXD_G_MARK,
2801};
2802/* - MSIOF2 ----------------------------------------------------------------- */
2803static const unsigned int msiof2_clk_a_pins[] = {
2804 /* SCK */
2805 RCAR_GP_PIN(1, 9),
2806};
2807static const unsigned int msiof2_clk_a_mux[] = {
2808 MSIOF2_SCK_A_MARK,
2809};
2810static const unsigned int msiof2_sync_a_pins[] = {
2811 /* SYNC */
2812 RCAR_GP_PIN(1, 8),
2813};
2814static const unsigned int msiof2_sync_a_mux[] = {
2815 MSIOF2_SYNC_A_MARK,
2816};
2817static const unsigned int msiof2_ss1_a_pins[] = {
2818 /* SS1 */
2819 RCAR_GP_PIN(1, 6),
2820};
2821static const unsigned int msiof2_ss1_a_mux[] = {
2822 MSIOF2_SS1_A_MARK,
2823};
2824static const unsigned int msiof2_ss2_a_pins[] = {
2825 /* SS2 */
2826 RCAR_GP_PIN(1, 7),
2827};
2828static const unsigned int msiof2_ss2_a_mux[] = {
2829 MSIOF2_SS2_A_MARK,
2830};
2831static const unsigned int msiof2_txd_a_pins[] = {
2832 /* TXD */
2833 RCAR_GP_PIN(1, 11),
2834};
2835static const unsigned int msiof2_txd_a_mux[] = {
2836 MSIOF2_TXD_A_MARK,
2837};
2838static const unsigned int msiof2_rxd_a_pins[] = {
2839 /* RXD */
2840 RCAR_GP_PIN(1, 10),
2841};
2842static const unsigned int msiof2_rxd_a_mux[] = {
2843 MSIOF2_RXD_A_MARK,
2844};
2845static const unsigned int msiof2_clk_b_pins[] = {
2846 /* SCK */
2847 RCAR_GP_PIN(0, 4),
2848};
2849static const unsigned int msiof2_clk_b_mux[] = {
2850 MSIOF2_SCK_B_MARK,
2851};
2852static const unsigned int msiof2_sync_b_pins[] = {
2853 /* SYNC */
2854 RCAR_GP_PIN(0, 5),
2855};
2856static const unsigned int msiof2_sync_b_mux[] = {
2857 MSIOF2_SYNC_B_MARK,
2858};
2859static const unsigned int msiof2_ss1_b_pins[] = {
2860 /* SS1 */
2861 RCAR_GP_PIN(0, 0),
2862};
2863static const unsigned int msiof2_ss1_b_mux[] = {
2864 MSIOF2_SS1_B_MARK,
2865};
2866static const unsigned int msiof2_ss2_b_pins[] = {
2867 /* SS2 */
2868 RCAR_GP_PIN(0, 1),
2869};
2870static const unsigned int msiof2_ss2_b_mux[] = {
2871 MSIOF2_SS2_B_MARK,
2872};
2873static const unsigned int msiof2_txd_b_pins[] = {
2874 /* TXD */
2875 RCAR_GP_PIN(0, 7),
2876};
2877static const unsigned int msiof2_txd_b_mux[] = {
2878 MSIOF2_TXD_B_MARK,
2879};
2880static const unsigned int msiof2_rxd_b_pins[] = {
2881 /* RXD */
2882 RCAR_GP_PIN(0, 6),
2883};
2884static const unsigned int msiof2_rxd_b_mux[] = {
2885 MSIOF2_RXD_B_MARK,
2886};
2887static const unsigned int msiof2_clk_c_pins[] = {
2888 /* SCK */
2889 RCAR_GP_PIN(2, 12),
2890};
2891static const unsigned int msiof2_clk_c_mux[] = {
2892 MSIOF2_SCK_C_MARK,
2893};
2894static const unsigned int msiof2_sync_c_pins[] = {
2895 /* SYNC */
2896 RCAR_GP_PIN(2, 11),
2897};
2898static const unsigned int msiof2_sync_c_mux[] = {
2899 MSIOF2_SYNC_C_MARK,
2900};
2901static const unsigned int msiof2_ss1_c_pins[] = {
2902 /* SS1 */
2903 RCAR_GP_PIN(2, 10),
2904};
2905static const unsigned int msiof2_ss1_c_mux[] = {
2906 MSIOF2_SS1_C_MARK,
2907};
2908static const unsigned int msiof2_ss2_c_pins[] = {
2909 /* SS2 */
2910 RCAR_GP_PIN(2, 9),
2911};
2912static const unsigned int msiof2_ss2_c_mux[] = {
2913 MSIOF2_SS2_C_MARK,
2914};
2915static const unsigned int msiof2_txd_c_pins[] = {
2916 /* TXD */
2917 RCAR_GP_PIN(2, 14),
2918};
2919static const unsigned int msiof2_txd_c_mux[] = {
2920 MSIOF2_TXD_C_MARK,
2921};
2922static const unsigned int msiof2_rxd_c_pins[] = {
2923 /* RXD */
2924 RCAR_GP_PIN(2, 13),
2925};
2926static const unsigned int msiof2_rxd_c_mux[] = {
2927 MSIOF2_RXD_C_MARK,
2928};
2929static const unsigned int msiof2_clk_d_pins[] = {
2930 /* SCK */
2931 RCAR_GP_PIN(0, 8),
2932};
2933static const unsigned int msiof2_clk_d_mux[] = {
2934 MSIOF2_SCK_D_MARK,
2935};
2936static const unsigned int msiof2_sync_d_pins[] = {
2937 /* SYNC */
2938 RCAR_GP_PIN(0, 9),
2939};
2940static const unsigned int msiof2_sync_d_mux[] = {
2941 MSIOF2_SYNC_D_MARK,
2942};
2943static const unsigned int msiof2_ss1_d_pins[] = {
2944 /* SS1 */
2945 RCAR_GP_PIN(0, 12),
2946};
2947static const unsigned int msiof2_ss1_d_mux[] = {
2948 MSIOF2_SS1_D_MARK,
2949};
2950static const unsigned int msiof2_ss2_d_pins[] = {
2951 /* SS2 */
2952 RCAR_GP_PIN(0, 13),
2953};
2954static const unsigned int msiof2_ss2_d_mux[] = {
2955 MSIOF2_SS2_D_MARK,
2956};
2957static const unsigned int msiof2_txd_d_pins[] = {
2958 /* TXD */
2959 RCAR_GP_PIN(0, 11),
2960};
2961static const unsigned int msiof2_txd_d_mux[] = {
2962 MSIOF2_TXD_D_MARK,
2963};
2964static const unsigned int msiof2_rxd_d_pins[] = {
2965 /* RXD */
2966 RCAR_GP_PIN(0, 10),
2967};
2968static const unsigned int msiof2_rxd_d_mux[] = {
2969 MSIOF2_RXD_D_MARK,
2970};
2971/* - MSIOF3 ----------------------------------------------------------------- */
2972static const unsigned int msiof3_clk_a_pins[] = {
2973 /* SCK */
2974 RCAR_GP_PIN(0, 0),
2975};
2976static const unsigned int msiof3_clk_a_mux[] = {
2977 MSIOF3_SCK_A_MARK,
2978};
2979static const unsigned int msiof3_sync_a_pins[] = {
2980 /* SYNC */
2981 RCAR_GP_PIN(0, 1),
2982};
2983static const unsigned int msiof3_sync_a_mux[] = {
2984 MSIOF3_SYNC_A_MARK,
2985};
2986static const unsigned int msiof3_ss1_a_pins[] = {
2987 /* SS1 */
2988 RCAR_GP_PIN(0, 14),
2989};
2990static const unsigned int msiof3_ss1_a_mux[] = {
2991 MSIOF3_SS1_A_MARK,
2992};
2993static const unsigned int msiof3_ss2_a_pins[] = {
2994 /* SS2 */
2995 RCAR_GP_PIN(0, 15),
2996};
2997static const unsigned int msiof3_ss2_a_mux[] = {
2998 MSIOF3_SS2_A_MARK,
2999};
3000static const unsigned int msiof3_txd_a_pins[] = {
3001 /* TXD */
3002 RCAR_GP_PIN(0, 3),
3003};
3004static const unsigned int msiof3_txd_a_mux[] = {
3005 MSIOF3_TXD_A_MARK,
3006};
3007static const unsigned int msiof3_rxd_a_pins[] = {
3008 /* RXD */
3009 RCAR_GP_PIN(0, 2),
3010};
3011static const unsigned int msiof3_rxd_a_mux[] = {
3012 MSIOF3_RXD_A_MARK,
3013};
3014static const unsigned int msiof3_clk_b_pins[] = {
3015 /* SCK */
3016 RCAR_GP_PIN(1, 2),
3017};
3018static const unsigned int msiof3_clk_b_mux[] = {
3019 MSIOF3_SCK_B_MARK,
3020};
3021static const unsigned int msiof3_sync_b_pins[] = {
3022 /* SYNC */
3023 RCAR_GP_PIN(1, 0),
3024};
3025static const unsigned int msiof3_sync_b_mux[] = {
3026 MSIOF3_SYNC_B_MARK,
3027};
3028static const unsigned int msiof3_ss1_b_pins[] = {
3029 /* SS1 */
3030 RCAR_GP_PIN(1, 4),
3031};
3032static const unsigned int msiof3_ss1_b_mux[] = {
3033 MSIOF3_SS1_B_MARK,
3034};
3035static const unsigned int msiof3_ss2_b_pins[] = {
3036 /* SS2 */
3037 RCAR_GP_PIN(1, 5),
3038};
3039static const unsigned int msiof3_ss2_b_mux[] = {
3040 MSIOF3_SS2_B_MARK,
3041};
3042static const unsigned int msiof3_txd_b_pins[] = {
3043 /* TXD */
3044 RCAR_GP_PIN(1, 1),
3045};
3046static const unsigned int msiof3_txd_b_mux[] = {
3047 MSIOF3_TXD_B_MARK,
3048};
3049static const unsigned int msiof3_rxd_b_pins[] = {
3050 /* RXD */
3051 RCAR_GP_PIN(1, 3),
3052};
3053static const unsigned int msiof3_rxd_b_mux[] = {
3054 MSIOF3_RXD_B_MARK,
3055};
3056static const unsigned int msiof3_clk_c_pins[] = {
3057 /* SCK */
3058 RCAR_GP_PIN(1, 12),
3059};
3060static const unsigned int msiof3_clk_c_mux[] = {
3061 MSIOF3_SCK_C_MARK,
3062};
3063static const unsigned int msiof3_sync_c_pins[] = {
3064 /* SYNC */
3065 RCAR_GP_PIN(1, 13),
3066};
3067static const unsigned int msiof3_sync_c_mux[] = {
3068 MSIOF3_SYNC_C_MARK,
3069};
3070static const unsigned int msiof3_txd_c_pins[] = {
3071 /* TXD */
3072 RCAR_GP_PIN(1, 15),
3073};
3074static const unsigned int msiof3_txd_c_mux[] = {
3075 MSIOF3_TXD_C_MARK,
3076};
3077static const unsigned int msiof3_rxd_c_pins[] = {
3078 /* RXD */
3079 RCAR_GP_PIN(1, 14),
3080};
3081static const unsigned int msiof3_rxd_c_mux[] = {
3082 MSIOF3_RXD_C_MARK,
3083};
3084static const unsigned int msiof3_clk_d_pins[] = {
3085 /* SCK */
3086 RCAR_GP_PIN(1, 22),
3087};
3088static const unsigned int msiof3_clk_d_mux[] = {
3089 MSIOF3_SCK_D_MARK,
3090};
3091static const unsigned int msiof3_sync_d_pins[] = {
3092 /* SYNC */
3093 RCAR_GP_PIN(1, 23),
3094};
3095static const unsigned int msiof3_sync_d_mux[] = {
3096 MSIOF3_SYNC_D_MARK,
3097};
3098static const unsigned int msiof3_ss1_d_pins[] = {
3099 /* SS1 */
3100 RCAR_GP_PIN(1, 26),
3101};
3102static const unsigned int msiof3_ss1_d_mux[] = {
3103 MSIOF3_SS1_D_MARK,
3104};
3105static const unsigned int msiof3_txd_d_pins[] = {
3106 /* TXD */
3107 RCAR_GP_PIN(1, 25),
3108};
3109static const unsigned int msiof3_txd_d_mux[] = {
3110 MSIOF3_TXD_D_MARK,
3111};
3112static const unsigned int msiof3_rxd_d_pins[] = {
3113 /* RXD */
3114 RCAR_GP_PIN(1, 24),
3115};
3116static const unsigned int msiof3_rxd_d_mux[] = {
3117 MSIOF3_RXD_D_MARK,
3118};
3119static const unsigned int msiof3_clk_e_pins[] = {
3120 /* SCK */
3121 RCAR_GP_PIN(2, 3),
3122};
3123static const unsigned int msiof3_clk_e_mux[] = {
3124 MSIOF3_SCK_E_MARK,
3125};
3126static const unsigned int msiof3_sync_e_pins[] = {
3127 /* SYNC */
3128 RCAR_GP_PIN(2, 2),
3129};
3130static const unsigned int msiof3_sync_e_mux[] = {
3131 MSIOF3_SYNC_E_MARK,
3132};
3133static const unsigned int msiof3_ss1_e_pins[] = {
3134 /* SS1 */
3135 RCAR_GP_PIN(2, 1),
3136};
3137static const unsigned int msiof3_ss1_e_mux[] = {
3138 MSIOF3_SS1_E_MARK,
3139};
3140static const unsigned int msiof3_ss2_e_pins[] = {
37880512 3141 /* SS2 */
3e6c7727
GU		 3142 RCAR_GP_PIN(2, 0),
3143};
3144static const unsigned int msiof3_ss2_e_mux[] = {
3145 MSIOF3_SS2_E_MARK,
3146};
3147static const unsigned int msiof3_txd_e_pins[] = {
3148 /* TXD */
3149 RCAR_GP_PIN(2, 5),
3150};
3151static const unsigned int msiof3_txd_e_mux[] = {
3152 MSIOF3_TXD_E_MARK,
3153};
3154static const unsigned int msiof3_rxd_e_pins[] = {
3155 /* RXD */
3156 RCAR_GP_PIN(2, 4),
3157};
3158static const unsigned int msiof3_rxd_e_mux[] = {
3159 MSIOF3_RXD_E_MARK,
3160};
3161
c03a133b
LP		 3162/* - PWM0 --------------------------------------------------------------------*/
3163static const unsigned int pwm0_pins[] = {
3164 /* PWM */
3165 RCAR_GP_PIN(2, 6),
3166};
3167static const unsigned int pwm0_mux[] = {
3168 PWM0_MARK,
3169};
3170/* - PWM1 --------------------------------------------------------------------*/
3171static const unsigned int pwm1_a_pins[] = {
3172 /* PWM */
3173 RCAR_GP_PIN(2, 7),
3174};
3175static const unsigned int pwm1_a_mux[] = {
3176 PWM1_A_MARK,
3177};
3178static const unsigned int pwm1_b_pins[] = {
3179 /* PWM */
3180 RCAR_GP_PIN(1, 8),
3181};
3182static const unsigned int pwm1_b_mux[] = {
3183 PWM1_B_MARK,
3184};
3185/* - PWM2 --------------------------------------------------------------------*/
3186static const unsigned int pwm2_a_pins[] = {
3187 /* PWM */
3188 RCAR_GP_PIN(2, 8),
3189};
3190static const unsigned int pwm2_a_mux[] = {
3191 PWM2_A_MARK,
3192};
3193static const unsigned int pwm2_b_pins[] = {
3194 /* PWM */
3195 RCAR_GP_PIN(1, 11),
3196};
3197static const unsigned int pwm2_b_mux[] = {
3198 PWM2_B_MARK,
3199};
3200/* - PWM3 --------------------------------------------------------------------*/
3201static const unsigned int pwm3_a_pins[] = {
3202 /* PWM */
3203 RCAR_GP_PIN(1, 0),
3204};
3205static const unsigned int pwm3_a_mux[] = {
3206 PWM3_A_MARK,
3207};
3208static const unsigned int pwm3_b_pins[] = {
3209 /* PWM */
3210 RCAR_GP_PIN(2, 2),
3211};
3212static const unsigned int pwm3_b_mux[] = {
3213 PWM3_B_MARK,
3214};
3215/* - PWM4 --------------------------------------------------------------------*/
3216static const unsigned int pwm4_a_pins[] = {
3217 /* PWM */
3218 RCAR_GP_PIN(1, 1),
3219};
3220static const unsigned int pwm4_a_mux[] = {
3221 PWM4_A_MARK,
3222};
3223static const unsigned int pwm4_b_pins[] = {
3224 /* PWM */
3225 RCAR_GP_PIN(2, 3),
3226};
3227static const unsigned int pwm4_b_mux[] = {
3228 PWM4_B_MARK,
3229};
3230/* - PWM5 --------------------------------------------------------------------*/
3231static const unsigned int pwm5_a_pins[] = {
3232 /* PWM */
3233 RCAR_GP_PIN(1, 2),
3234};
3235static const unsigned int pwm5_a_mux[] = {
3236 PWM5_A_MARK,
3237};
3238static const unsigned int pwm5_b_pins[] = {
3239 /* PWM */
3240 RCAR_GP_PIN(2, 4),
3241};
3242static const unsigned int pwm5_b_mux[] = {
3243 PWM5_B_MARK,
3244};
3245/* - PWM6 --------------------------------------------------------------------*/
3246static const unsigned int pwm6_a_pins[] = {
3247 /* PWM */
3248 RCAR_GP_PIN(1, 3),
3249};
3250static const unsigned int pwm6_a_mux[] = {
3251 PWM6_A_MARK,
3252};
3253static const unsigned int pwm6_b_pins[] = {
3254 /* PWM */
3255 RCAR_GP_PIN(2, 5),
3256};
3257static const unsigned int pwm6_b_mux[] = {
3258 PWM6_B_MARK,
3259};
3260
297e5b2b
WS		 3261/* - SATA --------------------------------------------------------------------*/
3262static const unsigned int sata0_devslp_a_pins[] = {
3263 /* DEVSLP */
3264 RCAR_GP_PIN(6, 16),
3265};
3266static const unsigned int sata0_devslp_a_mux[] = {
3267 SATA_DEVSLP_A_MARK,
3268};
3269static const unsigned int sata0_devslp_b_pins[] = {
3270 /* DEVSLP */
3271 RCAR_GP_PIN(4, 6),
3272};
3273static const unsigned int sata0_devslp_b_mux[] = {
3274 SATA_DEVSLP_B_MARK,
3275};
3276
e7ad4d3c
GU		 3277/* - SCIF0 ------------------------------------------------------------------ */
3278static const unsigned int scif0_data_pins[] = {
3279 /* RX, TX */
3280 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3281};
3282static const unsigned int scif0_data_mux[] = {
3283 RX0_MARK, TX0_MARK,
3284};
3285static const unsigned int scif0_clk_pins[] = {
3286 /* SCK */
3287 RCAR_GP_PIN(5, 0),
3288};
3289static const unsigned int scif0_clk_mux[] = {
3290 SCK0_MARK,
3291};
3292static const unsigned int scif0_ctrl_pins[] = {
3293 /* RTS, CTS */
3294 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3295};
3296static const unsigned int scif0_ctrl_mux[] = {
8714a9c1 3297 RTS0_N_MARK, CTS0_N_MARK,
e7ad4d3c
GU		 3298};
3299/* - SCIF1 ------------------------------------------------------------------ */
3300static const unsigned int scif1_data_a_pins[] = {
3301 /* RX, TX */
3302 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3303};
3304static const unsigned int scif1_data_a_mux[] = {
3305 RX1_A_MARK, TX1_A_MARK,
3306};
3307static const unsigned int scif1_clk_pins[] = {
3308 /* SCK */
3309 RCAR_GP_PIN(6, 21),
3310};
3311static const unsigned int scif1_clk_mux[] = {
3312 SCK1_MARK,
3313};
3314static const unsigned int scif1_ctrl_pins[] = {
3315 /* RTS, CTS */
3316 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3317};
3318static const unsigned int scif1_ctrl_mux[] = {
8714a9c1 3319 RTS1_N_MARK, CTS1_N_MARK,
e7ad4d3c
GU		 3320};
3321
3322static const unsigned int scif1_data_b_pins[] = {
3323 /* RX, TX */
3324 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3325};
3326static const unsigned int scif1_data_b_mux[] = {
3327 RX1_B_MARK, TX1_B_MARK,
3328};
3329/* - SCIF2 ------------------------------------------------------------------ */
3330static const unsigned int scif2_data_a_pins[] = {
3331 /* RX, TX */
3332 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3333};
3334static const unsigned int scif2_data_a_mux[] = {
3335 RX2_A_MARK, TX2_A_MARK,
3336};
3337static const unsigned int scif2_clk_pins[] = {
3338 /* SCK */
3339 RCAR_GP_PIN(5, 9),
3340};
3341static const unsigned int scif2_clk_mux[] = {
3342 SCK2_MARK,
3343};
3344static const unsigned int scif2_data_b_pins[] = {
3345 /* RX, TX */
3346 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3347};
3348static const unsigned int scif2_data_b_mux[] = {
3349 RX2_B_MARK, TX2_B_MARK,
3350};
3351/* - SCIF3 ------------------------------------------------------------------ */
3352static const unsigned int scif3_data_a_pins[] = {
3353 /* RX, TX */
3354 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3355};
3356static const unsigned int scif3_data_a_mux[] = {
3357 RX3_A_MARK, TX3_A_MARK,
3358};
3359static const unsigned int scif3_clk_pins[] = {
3360 /* SCK */
3361 RCAR_GP_PIN(1, 22),
3362};
3363static const unsigned int scif3_clk_mux[] = {
3364 SCK3_MARK,
3365};
3366static const unsigned int scif3_ctrl_pins[] = {
3367 /* RTS, CTS */
3368 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3369};
3370static const unsigned int scif3_ctrl_mux[] = {
8714a9c1 3371 RTS3_N_MARK, CTS3_N_MARK,
e7ad4d3c
GU		 3372};
3373static const unsigned int scif3_data_b_pins[] = {
3374 /* RX, TX */
3375 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3376};
3377static const unsigned int scif3_data_b_mux[] = {
3378 RX3_B_MARK, TX3_B_MARK,
3379};
3380/* - SCIF4 ------------------------------------------------------------------ */
3381static const unsigned int scif4_data_a_pins[] = {
3382 /* RX, TX */
3383 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3384};
3385static const unsigned int scif4_data_a_mux[] = {
3386 RX4_A_MARK, TX4_A_MARK,
3387};
3388static const unsigned int scif4_clk_a_pins[] = {
3389 /* SCK */
3390 RCAR_GP_PIN(2, 10),
3391};
3392static const unsigned int scif4_clk_a_mux[] = {
3393 SCK4_A_MARK,
3394};
3395static const unsigned int scif4_ctrl_a_pins[] = {
3396 /* RTS, CTS */
3397 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3398};
3399static const unsigned int scif4_ctrl_a_mux[] = {
8714a9c1 3400 RTS4_N_A_MARK, CTS4_N_A_MARK,
e7ad4d3c
GU		 3401};
3402static const unsigned int scif4_data_b_pins[] = {
3403 /* RX, TX */
3404 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3405};
3406static const unsigned int scif4_data_b_mux[] = {
3407 RX4_B_MARK, TX4_B_MARK,
3408};
3409static const unsigned int scif4_clk_b_pins[] = {
3410 /* SCK */
3411 RCAR_GP_PIN(1, 5),
3412};
3413static const unsigned int scif4_clk_b_mux[] = {
3414 SCK4_B_MARK,
3415};
3416static const unsigned int scif4_ctrl_b_pins[] = {
3417 /* RTS, CTS */
3418 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3419};
3420static const unsigned int scif4_ctrl_b_mux[] = {
8714a9c1 3421 RTS4_N_B_MARK, CTS4_N_B_MARK,
e7ad4d3c
GU		 3422};
3423static const unsigned int scif4_data_c_pins[] = {
3424 /* RX, TX */
3425 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3426};
3427static const unsigned int scif4_data_c_mux[] = {
3428 RX4_C_MARK, TX4_C_MARK,
3429};
3430static const unsigned int scif4_clk_c_pins[] = {
3431 /* SCK */
3432 RCAR_GP_PIN(0, 8),
3433};
3434static const unsigned int scif4_clk_c_mux[] = {
3435 SCK4_C_MARK,
3436};
3437static const unsigned int scif4_ctrl_c_pins[] = {
3438 /* RTS, CTS */
3439 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3440};
3441static const unsigned int scif4_ctrl_c_mux[] = {
8714a9c1 3442 RTS4_N_C_MARK, CTS4_N_C_MARK,
e7ad4d3c
GU		 3443};
3444/* - SCIF5 ------------------------------------------------------------------ */
3445static const unsigned int scif5_data_a_pins[] = {
3446 /* RX, TX */
3447 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3448};
3449static const unsigned int scif5_data_a_mux[] = {
3450 RX5_A_MARK, TX5_A_MARK,
3451};
3452static const unsigned int scif5_clk_a_pins[] = {
3453 /* SCK */
3454 RCAR_GP_PIN(6, 21),
3455};
3456static const unsigned int scif5_clk_a_mux[] = {
3457 SCK5_A_MARK,
3458};
3459static const unsigned int scif5_data_b_pins[] = {
3460 /* RX, TX */
3461 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3462};
3463static const unsigned int scif5_data_b_mux[] = {
3464 RX5_B_MARK, TX5_B_MARK,
3465};
3466static const unsigned int scif5_clk_b_pins[] = {
3467 /* SCK */
3468 RCAR_GP_PIN(5, 0),
3469};
3470static const unsigned int scif5_clk_b_mux[] = {
3471 SCK5_B_MARK,
3472};
3473
b4062b46
GU		 3474/* - SCIF Clock ------------------------------------------------------------- */
3475static const unsigned int scif_clk_a_pins[] = {
3476 /* SCIF_CLK */
3477 RCAR_GP_PIN(6, 23),
3478};
3479static const unsigned int scif_clk_a_mux[] = {
3480 SCIF_CLK_A_MARK,
3481};
3482static const unsigned int scif_clk_b_pins[] = {
3483 /* SCIF_CLK */
3484 RCAR_GP_PIN(5, 9),
3485};
3486static const unsigned int scif_clk_b_mux[] = {
3487 SCIF_CLK_B_MARK,
3488};
3489
9ed13958
TK		 3490/* - SDHI0 ------------------------------------------------------------------ */
3491static const unsigned int sdhi0_data1_pins[] = {
3492 /* D0 */
3493 RCAR_GP_PIN(3, 2),
3494};
3495static const unsigned int sdhi0_data1_mux[] = {
3496 SD0_DAT0_MARK,
3497};
3498static const unsigned int sdhi0_data4_pins[] = {
3499 /* D[0:3] */
3500 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3501 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3502};
3503static const unsigned int sdhi0_data4_mux[] = {
3504 SD0_DAT0_MARK, SD0_DAT1_MARK,
3505 SD0_DAT2_MARK, SD0_DAT3_MARK,
3506};
3507static const unsigned int sdhi0_ctrl_pins[] = {
3508 /* CLK, CMD */
3509 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3510};
3511static const unsigned int sdhi0_ctrl_mux[] = {
3512 SD0_CLK_MARK, SD0_CMD_MARK,
3513};
3514static const unsigned int sdhi0_cd_pins[] = {
3515 /* CD */
3516 RCAR_GP_PIN(3, 12),
3517};
3518static const unsigned int sdhi0_cd_mux[] = {
3519 SD0_CD_MARK,
3520};
3521static const unsigned int sdhi0_wp_pins[] = {
3522 /* WP */
3523 RCAR_GP_PIN(3, 13),
3524};
3525static const unsigned int sdhi0_wp_mux[] = {
3526 SD0_WP_MARK,
3527};
3528/* - SDHI1 ------------------------------------------------------------------ */
3529static const unsigned int sdhi1_data1_pins[] = {
3530 /* D0 */
3531 RCAR_GP_PIN(3, 8),
3532};
3533static const unsigned int sdhi1_data1_mux[] = {
3534 SD1_DAT0_MARK,
3535};
3536static const unsigned int sdhi1_data4_pins[] = {
3537 /* D[0:3] */
3538 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3539 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3540};
3541static const unsigned int sdhi1_data4_mux[] = {
3542 SD1_DAT0_MARK, SD1_DAT1_MARK,
3543 SD1_DAT2_MARK, SD1_DAT3_MARK,
3544};
3545static const unsigned int sdhi1_ctrl_pins[] = {
3546 /* CLK, CMD */
3547 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3548};
3549static const unsigned int sdhi1_ctrl_mux[] = {
3550 SD1_CLK_MARK, SD1_CMD_MARK,
3551};
3552static const unsigned int sdhi1_cd_pins[] = {
3553 /* CD */
3554 RCAR_GP_PIN(3, 14),
3555};
3556static const unsigned int sdhi1_cd_mux[] = {
3557 SD1_CD_MARK,
3558};
3559static const unsigned int sdhi1_wp_pins[] = {
3560 /* WP */
3561 RCAR_GP_PIN(3, 15),
3562};
3563static const unsigned int sdhi1_wp_mux[] = {
3564 SD1_WP_MARK,
3565};
3566/* - SDHI2 ------------------------------------------------------------------ */
3567static const unsigned int sdhi2_data1_pins[] = {
3568 /* D0 */
3569 RCAR_GP_PIN(4, 2),
3570};
3571static const unsigned int sdhi2_data1_mux[] = {
3572 SD2_DAT0_MARK,
3573};
3574static const unsigned int sdhi2_data4_pins[] = {
3575 /* D[0:3] */
3576 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3577 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3578};
3579static const unsigned int sdhi2_data4_mux[] = {
3580 SD2_DAT0_MARK, SD2_DAT1_MARK,
3581 SD2_DAT2_MARK, SD2_DAT3_MARK,
3582};
3583static const unsigned int sdhi2_data8_pins[] = {
3584 /* D[0:7] */
3585 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3586 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3587 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3588 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3589};
3590static const unsigned int sdhi2_data8_mux[] = {
3591 SD2_DAT0_MARK, SD2_DAT1_MARK,
3592 SD2_DAT2_MARK, SD2_DAT3_MARK,
3593 SD2_DAT4_MARK, SD2_DAT5_MARK,
3594 SD2_DAT6_MARK, SD2_DAT7_MARK,
3595};
3596static const unsigned int sdhi2_ctrl_pins[] = {
3597 /* CLK, CMD */
3598 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3599};
3600static const unsigned int sdhi2_ctrl_mux[] = {
3601 SD2_CLK_MARK, SD2_CMD_MARK,
3602};
3603static const unsigned int sdhi2_cd_a_pins[] = {
3604 /* CD */
3605 RCAR_GP_PIN(4, 13),
3606};
3607static const unsigned int sdhi2_cd_a_mux[] = {
3608 SD2_CD_A_MARK,
3609};
3610static const unsigned int sdhi2_cd_b_pins[] = {
3611 /* CD */
3612 RCAR_GP_PIN(5, 10),
3613};
3614static const unsigned int sdhi2_cd_b_mux[] = {
3615 SD2_CD_B_MARK,
3616};
3617static const unsigned int sdhi2_wp_a_pins[] = {
3618 /* WP */
3619 RCAR_GP_PIN(4, 14),
3620};
3621static const unsigned int sdhi2_wp_a_mux[] = {
3622 SD2_WP_A_MARK,
3623};
3624static const unsigned int sdhi2_wp_b_pins[] = {
3625 /* WP */
3626 RCAR_GP_PIN(5, 11),
3627};
3628static const unsigned int sdhi2_wp_b_mux[] = {
3629 SD2_WP_B_MARK,
3630};
3631static const unsigned int sdhi2_ds_pins[] = {
3632 /* DS */
3633 RCAR_GP_PIN(4, 6),
3634};
3635static const unsigned int sdhi2_ds_mux[] = {
3636 SD2_DS_MARK,
3637};
3638/* - SDHI3 ------------------------------------------------------------------ */
3639static const unsigned int sdhi3_data1_pins[] = {
3640 /* D0 */
3641 RCAR_GP_PIN(4, 9),
3642};
3643static const unsigned int sdhi3_data1_mux[] = {
3644 SD3_DAT0_MARK,
3645};
3646static const unsigned int sdhi3_data4_pins[] = {
3647 /* D[0:3] */
3648 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3649 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3650};
3651static const unsigned int sdhi3_data4_mux[] = {
3652 SD3_DAT0_MARK, SD3_DAT1_MARK,
3653 SD3_DAT2_MARK, SD3_DAT3_MARK,
3654};
3655static const unsigned int sdhi3_data8_pins[] = {
3656 /* D[0:7] */
3657 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3658 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3659 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3660 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3661};
3662static const unsigned int sdhi3_data8_mux[] = {
3663 SD3_DAT0_MARK, SD3_DAT1_MARK,
3664 SD3_DAT2_MARK, SD3_DAT3_MARK,
3665 SD3_DAT4_MARK, SD3_DAT5_MARK,
3666 SD3_DAT6_MARK, SD3_DAT7_MARK,
3667};
3668static const unsigned int sdhi3_ctrl_pins[] = {
3669 /* CLK, CMD */
3670 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3671};
3672static const unsigned int sdhi3_ctrl_mux[] = {
3673 SD3_CLK_MARK, SD3_CMD_MARK,
3674};
3675static const unsigned int sdhi3_cd_pins[] = {
3676 /* CD */
3677 RCAR_GP_PIN(4, 15),
3678};
3679static const unsigned int sdhi3_cd_mux[] = {
3680 SD3_CD_MARK,
3681};
3682static const unsigned int sdhi3_wp_pins[] = {
3683 /* WP */
3684 RCAR_GP_PIN(4, 16),
3685};
3686static const unsigned int sdhi3_wp_mux[] = {
3687 SD3_WP_MARK,
3688};
3689static const unsigned int sdhi3_ds_pins[] = {
3690 /* DS */
3691 RCAR_GP_PIN(4, 17),
3692};
3693static const unsigned int sdhi3_ds_mux[] = {
3694 SD3_DS_MARK,
3695};
3696
0526234d
KM		 3697/* - SSI -------------------------------------------------------------------- */
3698static const unsigned int ssi0_data_pins[] = {
3699 /* SDATA */
3700 RCAR_GP_PIN(6, 2),
3701};
3702static const unsigned int ssi0_data_mux[] = {
3703 SSI_SDATA0_MARK,
3704};
3705static const unsigned int ssi01239_ctrl_pins[] = {
3706 /* SCK, WS */
3707 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3708};
3709static const unsigned int ssi01239_ctrl_mux[] = {
3710 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3711};
3712static const unsigned int ssi1_data_a_pins[] = {
3713 /* SDATA */
3714 RCAR_GP_PIN(6, 3),
3715};
3716static const unsigned int ssi1_data_a_mux[] = {
3717 SSI_SDATA1_A_MARK,
3718};
3719static const unsigned int ssi1_data_b_pins[] = {
3720 /* SDATA */
3721 RCAR_GP_PIN(5, 12),
3722};
3723static const unsigned int ssi1_data_b_mux[] = {
3724 SSI_SDATA1_B_MARK,
3725};
3726static const unsigned int ssi1_ctrl_a_pins[] = {
3727 /* SCK, WS */
3728 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3729};
3730static const unsigned int ssi1_ctrl_a_mux[] = {
3731 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3732};
3733static const unsigned int ssi1_ctrl_b_pins[] = {
3734 /* SCK, WS */
3735 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3736};
3737static const unsigned int ssi1_ctrl_b_mux[] = {
3738 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3739};
3740static const unsigned int ssi2_data_a_pins[] = {
3741 /* SDATA */
3742 RCAR_GP_PIN(6, 4),
3743};
3744static const unsigned int ssi2_data_a_mux[] = {
3745 SSI_SDATA2_A_MARK,
3746};
3747static const unsigned int ssi2_data_b_pins[] = {
3748 /* SDATA */
3749 RCAR_GP_PIN(5, 13),
3750};
3751static const unsigned int ssi2_data_b_mux[] = {
3752 SSI_SDATA2_B_MARK,
3753};
3754static const unsigned int ssi2_ctrl_a_pins[] = {
3755 /* SCK, WS */
3756 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3757};
3758static const unsigned int ssi2_ctrl_a_mux[] = {
3759 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3760};
3761static const unsigned int ssi2_ctrl_b_pins[] = {
3762 /* SCK, WS */
3763 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3764};
3765static const unsigned int ssi2_ctrl_b_mux[] = {
3766 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3767};
3768static const unsigned int ssi3_data_pins[] = {
3769 /* SDATA */
3770 RCAR_GP_PIN(6, 7),
3771};
3772static const unsigned int ssi3_data_mux[] = {
3773 SSI_SDATA3_MARK,
3774};
3775static const unsigned int ssi349_ctrl_pins[] = {
3776 /* SCK, WS */
3777 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3778};
3779static const unsigned int ssi349_ctrl_mux[] = {
3780 SSI_SCK349_MARK, SSI_WS349_MARK,
3781};
3782static const unsigned int ssi4_data_pins[] = {
3783 /* SDATA */
3784 RCAR_GP_PIN(6, 10),
3785};
3786static const unsigned int ssi4_data_mux[] = {
3787 SSI_SDATA4_MARK,
3788};
3789static const unsigned int ssi4_ctrl_pins[] = {
3790 /* SCK, WS */
3791 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3792};
3793static const unsigned int ssi4_ctrl_mux[] = {
3794 SSI_SCK4_MARK, SSI_WS4_MARK,
3795};
3796static const unsigned int ssi5_data_pins[] = {
3797 /* SDATA */
3798 RCAR_GP_PIN(6, 13),
3799};
3800static const unsigned int ssi5_data_mux[] = {
3801 SSI_SDATA5_MARK,
3802};
3803static const unsigned int ssi5_ctrl_pins[] = {
3804 /* SCK, WS */
3805 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3806};
3807static const unsigned int ssi5_ctrl_mux[] = {
3808 SSI_SCK5_MARK, SSI_WS5_MARK,
3809};
3810static const unsigned int ssi6_data_pins[] = {
3811 /* SDATA */
3812 RCAR_GP_PIN(6, 16),
3813};
3814static const unsigned int ssi6_data_mux[] = {
3815 SSI_SDATA6_MARK,
3816};
3817static const unsigned int ssi6_ctrl_pins[] = {
3818 /* SCK, WS */
3819 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3820};
3821static const unsigned int ssi6_ctrl_mux[] = {
3822 SSI_SCK6_MARK, SSI_WS6_MARK,
3823};
3824static const unsigned int ssi7_data_pins[] = {
3825 /* SDATA */
3826 RCAR_GP_PIN(6, 19),
3827};
3828static const unsigned int ssi7_data_mux[] = {
3829 SSI_SDATA7_MARK,
3830};
3831static const unsigned int ssi78_ctrl_pins[] = {
3832 /* SCK, WS */
3833 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3834};
3835static const unsigned int ssi78_ctrl_mux[] = {
3836 SSI_SCK78_MARK, SSI_WS78_MARK,
3837};
3838static const unsigned int ssi8_data_pins[] = {
3839 /* SDATA */
3840 RCAR_GP_PIN(6, 20),
3841};
3842static const unsigned int ssi8_data_mux[] = {
3843 SSI_SDATA8_MARK,
3844};
3845static const unsigned int ssi9_data_a_pins[] = {
3846 /* SDATA */
3847 RCAR_GP_PIN(6, 21),
3848};
3849static const unsigned int ssi9_data_a_mux[] = {
3850 SSI_SDATA9_A_MARK,
3851};
3852static const unsigned int ssi9_data_b_pins[] = {
3853 /* SDATA */
3854 RCAR_GP_PIN(5, 14),
3855};
3856static const unsigned int ssi9_data_b_mux[] = {
3857 SSI_SDATA9_B_MARK,
3858};
3859static const unsigned int ssi9_ctrl_a_pins[] = {
3860 /* SCK, WS */
3861 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3862};
3863static const unsigned int ssi9_ctrl_a_mux[] = {
3864 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3865};
3866static const unsigned int ssi9_ctrl_b_pins[] = {
3867 /* SCK, WS */
3868 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3869};
3870static const unsigned int ssi9_ctrl_b_mux[] = {
3871 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3872};
3873
edcc14c8
TK		 3874/* - TMU -------------------------------------------------------------------- */
3875static const unsigned int tmu_tclk1_a_pins[] = {
3876 /* TCLK */
3877 RCAR_GP_PIN(6, 23),
3878};
3879static const unsigned int tmu_tclk1_a_mux[] = {
3880 TCLK1_A_MARK,
3881};
3882static const unsigned int tmu_tclk1_b_pins[] = {
3883 /* TCLK */
3884 RCAR_GP_PIN(5, 19),
3885};
3886static const unsigned int tmu_tclk1_b_mux[] = {
3887 TCLK1_B_MARK,
3888};
3889static const unsigned int tmu_tclk2_a_pins[] = {
3890 /* TCLK */
3891 RCAR_GP_PIN(6, 19),
3892};
3893static const unsigned int tmu_tclk2_a_mux[] = {
3894 TCLK2_A_MARK,
3895};
3896static const unsigned int tmu_tclk2_b_pins[] = {
3897 /* TCLK */
3898 RCAR_GP_PIN(6, 28),
3899};
3900static const unsigned int tmu_tclk2_b_mux[] = {
3901 TCLK2_B_MARK,
3902};
3903
933ddbe5
YS		 3904/* - USB0 ------------------------------------------------------------------- */
3905static const unsigned int usb0_pins[] = {
3906 /* PWEN, OVC */
3907 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3908};
3909static const unsigned int usb0_mux[] = {
3910 USB0_PWEN_MARK, USB0_OVC_MARK,
3911};
3912/* - USB1 ------------------------------------------------------------------- */
3913static const unsigned int usb1_pins[] = {
3914 /* PWEN, OVC */
3915 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3916};
3917static const unsigned int usb1_mux[] = {
3918 USB1_PWEN_MARK, USB1_OVC_MARK,
3919};
3920/* - USB2 ------------------------------------------------------------------- */
3921static const unsigned int usb2_pins[] = {
3922 /* PWEN, OVC */
3923 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3924};
3925static const unsigned int usb2_mux[] = {
3926 USB2_PWEN_MARK, USB2_OVC_MARK,
3927};
3928/* - USB2_CH3 --------------------------------------------------------------- */
3929static const unsigned int usb2_ch3_pins[] = {
3930 /* PWEN, OVC */
3931 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3932};
3933static const unsigned int usb2_ch3_mux[] = {
3934 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3935};
3936
5ec8a41a
TK		 3937/* - USB30 ------------------------------------------------------------------ */
3938static const unsigned int usb30_pins[] = {
3939 /* PWEN, OVC */
3940 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3941};
3942static const unsigned int usb30_mux[] = {
3943 USB30_PWEN_MARK, USB30_OVC_MARK,
3944};
3945
6b4de408 3946/* - VIN4 ------------------------------------------------------------------- */
6b4de408 3947static const unsigned int vin4_data18_a_pins[] = {
6b4de408
UH		 3948 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3949 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3950 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
6b4de408
UH		 3951 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3952 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3953 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
b538dc5b
UH		 3954 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3955 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3956 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
6b4de408
UH		 3957};
3958static const unsigned int vin4_data18_a_mux[] = {
6b4de408
UH		 3959 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3960 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3961 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
6b4de408
UH		 3962 VI4_DATA10_MARK, VI4_DATA11_MARK,
3963 VI4_DATA12_MARK, VI4_DATA13_MARK,
3964 VI4_DATA14_MARK, VI4_DATA15_MARK,
b538dc5b
UH		 3965 VI4_DATA18_MARK, VI4_DATA19_MARK,
3966 VI4_DATA20_MARK, VI4_DATA21_MARK,
3967 VI4_DATA22_MARK, VI4_DATA23_MARK,
6b4de408
UH		 3968};
3969static const unsigned int vin4_data18_b_pins[] = {
6b4de408
UH		 3970 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3971 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3972 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
6b4de408
UH		 3973 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3974 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3975 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
b538dc5b
UH		 3976 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3977 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3978 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
6b4de408
UH		 3979};
3980static const unsigned int vin4_data18_b_mux[] = {
6b4de408
UH		 3981 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3982 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3983 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
6b4de408
UH		 3984 VI4_DATA10_MARK, VI4_DATA11_MARK,
3985 VI4_DATA12_MARK, VI4_DATA13_MARK,
3986 VI4_DATA14_MARK, VI4_DATA15_MARK,
b538dc5b
UH		 3987 VI4_DATA18_MARK, VI4_DATA19_MARK,
3988 VI4_DATA20_MARK, VI4_DATA21_MARK,
3989 VI4_DATA22_MARK, VI4_DATA23_MARK,
6b4de408 3990};
9942a5b5
UH		 3991static const union vin_data vin4_data_a_pins = {
3992 .data24 = {
3993 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3994 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3995 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3996 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3997 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3998 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3999 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4000 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4001 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4002 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4003 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4004 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4005 },
4006};
4007static const union vin_data vin4_data_a_mux = {
4008 .data24 = {
4009 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4010 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4011 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4012 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4013 VI4_DATA8_MARK, VI4_DATA9_MARK,
4014 VI4_DATA10_MARK, VI4_DATA11_MARK,
4015 VI4_DATA12_MARK, VI4_DATA13_MARK,
4016 VI4_DATA14_MARK, VI4_DATA15_MARK,
4017 VI4_DATA16_MARK, VI4_DATA17_MARK,
4018 VI4_DATA18_MARK, VI4_DATA19_MARK,
4019 VI4_DATA20_MARK, VI4_DATA21_MARK,
4020 VI4_DATA22_MARK, VI4_DATA23_MARK,
4021 },
4022};
4023static const union vin_data vin4_data_b_pins = {
4024 .data24 = {
4025 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4026 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4027 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4028 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4029 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4030 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4031 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4032 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4033 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4034 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4035 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4036 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4037 },
4038};
4039static const union vin_data vin4_data_b_mux = {
4040 .data24 = {
4041 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4042 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4043 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4044 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4045 VI4_DATA8_MARK, VI4_DATA9_MARK,
4046 VI4_DATA10_MARK, VI4_DATA11_MARK,
4047 VI4_DATA12_MARK, VI4_DATA13_MARK,
4048 VI4_DATA14_MARK, VI4_DATA15_MARK,
4049 VI4_DATA16_MARK, VI4_DATA17_MARK,
4050 VI4_DATA18_MARK, VI4_DATA19_MARK,
4051 VI4_DATA20_MARK, VI4_DATA21_MARK,
4052 VI4_DATA22_MARK, VI4_DATA23_MARK,
4053 },
6b4de408
UH		 4054};
4055static const unsigned int vin4_sync_pins[] = {
4056 /* HSYNC#, VSYNC# */
4057 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4058};
4059static const unsigned int vin4_sync_mux[] = {
4060 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4061};
4062static const unsigned int vin4_field_pins[] = {
4063 /* FIELD */
4064 RCAR_GP_PIN(1, 16),
4065};
4066static const unsigned int vin4_field_mux[] = {
4067 VI4_FIELD_MARK,
4068};
4069static const unsigned int vin4_clkenb_pins[] = {
4070 /* CLKENB */
4071 RCAR_GP_PIN(1, 19),
4072};
4073static const unsigned int vin4_clkenb_mux[] = {
4074 VI4_CLKENB_MARK,
4075};
4076static const unsigned int vin4_clk_pins[] = {
4077 /* CLK */
4078 RCAR_GP_PIN(1, 27),
4079};
4080static const unsigned int vin4_clk_mux[] = {
4081 VI4_CLK_MARK,
4082};
4083
4084/* - VIN5 ------------------------------------------------------------------- */
99fdb920
GU		 4085static const union vin_data16 vin5_data_pins = {
4086 .data16 = {
4087 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4088 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4089 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4090 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4091 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4092 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4093 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4094 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4095 },
6b4de408 4096};
99fdb920
GU		 4097static const union vin_data16 vin5_data_mux = {
4098 .data16 = {
4099 VI5_DATA0_MARK, VI5_DATA1_MARK,
4100 VI5_DATA2_MARK, VI5_DATA3_MARK,
4101 VI5_DATA4_MARK, VI5_DATA5_MARK,
4102 VI5_DATA6_MARK, VI5_DATA7_MARK,
4103 VI5_DATA8_MARK, VI5_DATA9_MARK,
4104 VI5_DATA10_MARK, VI5_DATA11_MARK,
4105 VI5_DATA12_MARK, VI5_DATA13_MARK,
4106 VI5_DATA14_MARK, VI5_DATA15_MARK,
4107 },
6b4de408
UH		 4108};
4109static const unsigned int vin5_sync_pins[] = {
4110 /* HSYNC#, VSYNC# */
4111 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4112};
4113static const unsigned int vin5_sync_mux[] = {
4114 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4115};
4116static const unsigned int vin5_field_pins[] = {
4117 RCAR_GP_PIN(1, 11),
4118};
4119static const unsigned int vin5_field_mux[] = {
4120 /* FIELD */
4121 VI5_FIELD_MARK,
4122};
4123static const unsigned int vin5_clkenb_pins[] = {
4124 RCAR_GP_PIN(1, 20),
4125};
4126static const unsigned int vin5_clkenb_mux[] = {
4127 /* CLKENB */
4128 VI5_CLKENB_MARK,
4129};
4130static const unsigned int vin5_clk_pins[] = {
4131 RCAR_GP_PIN(1, 21),
4132};
4133static const unsigned int vin5_clk_mux[] = {
4134 /* CLK */
4135 VI5_CLK_MARK,
4136};
4137
b205914c 4138static const struct sh_pfc_pin_group pinmux_groups[] = {
55bfea9f
KM		 4139 SH_PFC_PIN_GROUP(audio_clk_a_a),
4140 SH_PFC_PIN_GROUP(audio_clk_a_b),
4141 SH_PFC_PIN_GROUP(audio_clk_a_c),
4142 SH_PFC_PIN_GROUP(audio_clk_b_a),
4143 SH_PFC_PIN_GROUP(audio_clk_b_b),
4144 SH_PFC_PIN_GROUP(audio_clk_c_a),
4145 SH_PFC_PIN_GROUP(audio_clk_c_b),
4146 SH_PFC_PIN_GROUP(audio_clkout_a),
4147 SH_PFC_PIN_GROUP(audio_clkout_b),
4148 SH_PFC_PIN_GROUP(audio_clkout_c),
4149 SH_PFC_PIN_GROUP(audio_clkout_d),
4150 SH_PFC_PIN_GROUP(audio_clkout1_a),
4151 SH_PFC_PIN_GROUP(audio_clkout1_b),
4152 SH_PFC_PIN_GROUP(audio_clkout2_a),
4153 SH_PFC_PIN_GROUP(audio_clkout2_b),
4154 SH_PFC_PIN_GROUP(audio_clkout3_a),
4155 SH_PFC_PIN_GROUP(audio_clkout3_b),
30c078de
GU		 4156 SH_PFC_PIN_GROUP(avb_link),
4157 SH_PFC_PIN_GROUP(avb_magic),
4158 SH_PFC_PIN_GROUP(avb_phy_int),
cbe0dd9a
GU		 4159 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4160 SH_PFC_PIN_GROUP(avb_mdio),
30c078de
GU		 4161 SH_PFC_PIN_GROUP(avb_mii),
4162 SH_PFC_PIN_GROUP(avb_avtp_pps),
4163 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4164 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4165 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4166 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a678abfe
RS		 4167 SH_PFC_PIN_GROUP(can0_data_a),
4168 SH_PFC_PIN_GROUP(can0_data_b),
4169 SH_PFC_PIN_GROUP(can1_data),
4170 SH_PFC_PIN_GROUP(can_clk),
0e1c7a94
RS		 4171 SH_PFC_PIN_GROUP(canfd0_data_a),
4172 SH_PFC_PIN_GROUP(canfd0_data_b),
4173 SH_PFC_PIN_GROUP(canfd1_data),
641b0ab8
DB		 4174 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4175 SH_PFC_PIN_GROUP(drif0_data0_a),
4176 SH_PFC_PIN_GROUP(drif0_data1_a),
4177 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4178 SH_PFC_PIN_GROUP(drif0_data0_b),
4179 SH_PFC_PIN_GROUP(drif0_data1_b),
4180 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4181 SH_PFC_PIN_GROUP(drif0_data0_c),
4182 SH_PFC_PIN_GROUP(drif0_data1_c),
4183 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4184 SH_PFC_PIN_GROUP(drif1_data0_a),
4185 SH_PFC_PIN_GROUP(drif1_data1_a),
4186 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4187 SH_PFC_PIN_GROUP(drif1_data0_b),
4188 SH_PFC_PIN_GROUP(drif1_data1_b),
4189 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4190 SH_PFC_PIN_GROUP(drif1_data0_c),
4191 SH_PFC_PIN_GROUP(drif1_data1_c),
4192 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4193 SH_PFC_PIN_GROUP(drif2_data0_a),
4194 SH_PFC_PIN_GROUP(drif2_data1_a),
4195 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4196 SH_PFC_PIN_GROUP(drif2_data0_b),
4197 SH_PFC_PIN_GROUP(drif2_data1_b),
4198 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4199 SH_PFC_PIN_GROUP(drif3_data0_a),
4200 SH_PFC_PIN_GROUP(drif3_data1_a),
4201 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4202 SH_PFC_PIN_GROUP(drif3_data0_b),
4203 SH_PFC_PIN_GROUP(drif3_data1_b),
a20a6585
LP		 4204 SH_PFC_PIN_GROUP(du_rgb666),
4205 SH_PFC_PIN_GROUP(du_rgb888),
4206 SH_PFC_PIN_GROUP(du_clk_out_0),
4207 SH_PFC_PIN_GROUP(du_clk_out_1),
4208 SH_PFC_PIN_GROUP(du_sync),
4209 SH_PFC_PIN_GROUP(du_oddf),
4210 SH_PFC_PIN_GROUP(du_cde),
4211 SH_PFC_PIN_GROUP(du_disp),
7a362e34
WS		 4212 SH_PFC_PIN_GROUP(hscif0_data),
4213 SH_PFC_PIN_GROUP(hscif0_clk),
4214 SH_PFC_PIN_GROUP(hscif0_ctrl),
4215 SH_PFC_PIN_GROUP(hscif1_data_a),
4216 SH_PFC_PIN_GROUP(hscif1_clk_a),
4217 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4218 SH_PFC_PIN_GROUP(hscif1_data_b),
4219 SH_PFC_PIN_GROUP(hscif1_clk_b),
4220 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4221 SH_PFC_PIN_GROUP(hscif2_data_a),
4222 SH_PFC_PIN_GROUP(hscif2_clk_a),
4223 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4224 SH_PFC_PIN_GROUP(hscif2_data_b),
4225 SH_PFC_PIN_GROUP(hscif2_clk_b),
4226 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4227 SH_PFC_PIN_GROUP(hscif2_data_c),
4228 SH_PFC_PIN_GROUP(hscif2_clk_c),
4229 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4230 SH_PFC_PIN_GROUP(hscif3_data_a),
4231 SH_PFC_PIN_GROUP(hscif3_clk),
4232 SH_PFC_PIN_GROUP(hscif3_ctrl),
4233 SH_PFC_PIN_GROUP(hscif3_data_b),
4234 SH_PFC_PIN_GROUP(hscif3_data_c),
4235 SH_PFC_PIN_GROUP(hscif3_data_d),
4236 SH_PFC_PIN_GROUP(hscif4_data_a),
4237 SH_PFC_PIN_GROUP(hscif4_clk),
4238 SH_PFC_PIN_GROUP(hscif4_ctrl),
4239 SH_PFC_PIN_GROUP(hscif4_data_b),
100431b6 4240 SH_PFC_PIN_GROUP(i2c0),
f62d4c9e
WS		 4241 SH_PFC_PIN_GROUP(i2c1_a),
4242 SH_PFC_PIN_GROUP(i2c1_b),
4243 SH_PFC_PIN_GROUP(i2c2_a),
4244 SH_PFC_PIN_GROUP(i2c2_b),
100431b6
TK		 4245 SH_PFC_PIN_GROUP(i2c3),
4246 SH_PFC_PIN_GROUP(i2c5),
f62d4c9e
WS		 4247 SH_PFC_PIN_GROUP(i2c6_a),
4248 SH_PFC_PIN_GROUP(i2c6_b),
4249 SH_PFC_PIN_GROUP(i2c6_c),
8480e6ca
GU		 4250 SH_PFC_PIN_GROUP(intc_ex_irq0),
4251 SH_PFC_PIN_GROUP(intc_ex_irq1),
4252 SH_PFC_PIN_GROUP(intc_ex_irq2),
4253 SH_PFC_PIN_GROUP(intc_ex_irq3),
4254 SH_PFC_PIN_GROUP(intc_ex_irq4),
4255 SH_PFC_PIN_GROUP(intc_ex_irq5),
3e6c7727
GU		 4256 SH_PFC_PIN_GROUP(msiof0_clk),
4257 SH_PFC_PIN_GROUP(msiof0_sync),
4258 SH_PFC_PIN_GROUP(msiof0_ss1),
4259 SH_PFC_PIN_GROUP(msiof0_ss2),
4260 SH_PFC_PIN_GROUP(msiof0_txd),
4261 SH_PFC_PIN_GROUP(msiof0_rxd),
4262 SH_PFC_PIN_GROUP(msiof1_clk_a),
4263 SH_PFC_PIN_GROUP(msiof1_sync_a),
4264 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4265 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4266 SH_PFC_PIN_GROUP(msiof1_txd_a),
4267 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4268 SH_PFC_PIN_GROUP(msiof1_clk_b),
4269 SH_PFC_PIN_GROUP(msiof1_sync_b),
4270 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4271 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4272 SH_PFC_PIN_GROUP(msiof1_txd_b),
4273 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4274 SH_PFC_PIN_GROUP(msiof1_clk_c),
4275 SH_PFC_PIN_GROUP(msiof1_sync_c),
4276 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4277 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4278 SH_PFC_PIN_GROUP(msiof1_txd_c),
4279 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4280 SH_PFC_PIN_GROUP(msiof1_clk_d),
4281 SH_PFC_PIN_GROUP(msiof1_sync_d),
4282 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4283 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4284 SH_PFC_PIN_GROUP(msiof1_txd_d),
4285 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4286 SH_PFC_PIN_GROUP(msiof1_clk_e),
4287 SH_PFC_PIN_GROUP(msiof1_sync_e),
4288 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4289 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4290 SH_PFC_PIN_GROUP(msiof1_txd_e),
4291 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4292 SH_PFC_PIN_GROUP(msiof1_clk_f),
4293 SH_PFC_PIN_GROUP(msiof1_sync_f),
4294 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4295 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4296 SH_PFC_PIN_GROUP(msiof1_txd_f),
4297 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4298 SH_PFC_PIN_GROUP(msiof1_clk_g),
4299 SH_PFC_PIN_GROUP(msiof1_sync_g),
4300 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4301 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4302 SH_PFC_PIN_GROUP(msiof1_txd_g),
4303 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4304 SH_PFC_PIN_GROUP(msiof2_clk_a),
4305 SH_PFC_PIN_GROUP(msiof2_sync_a),
4306 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4307 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4308 SH_PFC_PIN_GROUP(msiof2_txd_a),
4309 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4310 SH_PFC_PIN_GROUP(msiof2_clk_b),
4311 SH_PFC_PIN_GROUP(msiof2_sync_b),
4312 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4313 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4314 SH_PFC_PIN_GROUP(msiof2_txd_b),
4315 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4316 SH_PFC_PIN_GROUP(msiof2_clk_c),
4317 SH_PFC_PIN_GROUP(msiof2_sync_c),
4318 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4319 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4320 SH_PFC_PIN_GROUP(msiof2_txd_c),
4321 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4322 SH_PFC_PIN_GROUP(msiof2_clk_d),
4323 SH_PFC_PIN_GROUP(msiof2_sync_d),
4324 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4325 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4326 SH_PFC_PIN_GROUP(msiof2_txd_d),
4327 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4328 SH_PFC_PIN_GROUP(msiof3_clk_a),
4329 SH_PFC_PIN_GROUP(msiof3_sync_a),
4330 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4331 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4332 SH_PFC_PIN_GROUP(msiof3_txd_a),
4333 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4334 SH_PFC_PIN_GROUP(msiof3_clk_b),
4335 SH_PFC_PIN_GROUP(msiof3_sync_b),
4336 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4337 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4338 SH_PFC_PIN_GROUP(msiof3_txd_b),
4339 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4340 SH_PFC_PIN_GROUP(msiof3_clk_c),
4341 SH_PFC_PIN_GROUP(msiof3_sync_c),
4342 SH_PFC_PIN_GROUP(msiof3_txd_c),
4343 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4344 SH_PFC_PIN_GROUP(msiof3_clk_d),
4345 SH_PFC_PIN_GROUP(msiof3_sync_d),
4346 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4347 SH_PFC_PIN_GROUP(msiof3_txd_d),
4348 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4349 SH_PFC_PIN_GROUP(msiof3_clk_e),
4350 SH_PFC_PIN_GROUP(msiof3_sync_e),
4351 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4352 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4353 SH_PFC_PIN_GROUP(msiof3_txd_e),
4354 SH_PFC_PIN_GROUP(msiof3_rxd_e),
c03a133b
LP		 4355 SH_PFC_PIN_GROUP(pwm0),
4356 SH_PFC_PIN_GROUP(pwm1_a),
4357 SH_PFC_PIN_GROUP(pwm1_b),
4358 SH_PFC_PIN_GROUP(pwm2_a),
4359 SH_PFC_PIN_GROUP(pwm2_b),
4360 SH_PFC_PIN_GROUP(pwm3_a),
4361 SH_PFC_PIN_GROUP(pwm3_b),
4362 SH_PFC_PIN_GROUP(pwm4_a),
4363 SH_PFC_PIN_GROUP(pwm4_b),
4364 SH_PFC_PIN_GROUP(pwm5_a),
4365 SH_PFC_PIN_GROUP(pwm5_b),
4366 SH_PFC_PIN_GROUP(pwm6_a),
4367 SH_PFC_PIN_GROUP(pwm6_b),
297e5b2b
WS		 4368 SH_PFC_PIN_GROUP(sata0_devslp_a),
4369 SH_PFC_PIN_GROUP(sata0_devslp_b),
e7ad4d3c
GU		 4370 SH_PFC_PIN_GROUP(scif0_data),
4371 SH_PFC_PIN_GROUP(scif0_clk),
4372 SH_PFC_PIN_GROUP(scif0_ctrl),
4373 SH_PFC_PIN_GROUP(scif1_data_a),
4374 SH_PFC_PIN_GROUP(scif1_clk),
4375 SH_PFC_PIN_GROUP(scif1_ctrl),
4376 SH_PFC_PIN_GROUP(scif1_data_b),
4377 SH_PFC_PIN_GROUP(scif2_data_a),
4378 SH_PFC_PIN_GROUP(scif2_clk),
4379 SH_PFC_PIN_GROUP(scif2_data_b),
4380 SH_PFC_PIN_GROUP(scif3_data_a),
4381 SH_PFC_PIN_GROUP(scif3_clk),
4382 SH_PFC_PIN_GROUP(scif3_ctrl),
4383 SH_PFC_PIN_GROUP(scif3_data_b),
4384 SH_PFC_PIN_GROUP(scif4_data_a),
4385 SH_PFC_PIN_GROUP(scif4_clk_a),
4386 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4387 SH_PFC_PIN_GROUP(scif4_data_b),
4388 SH_PFC_PIN_GROUP(scif4_clk_b),
4389 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4390 SH_PFC_PIN_GROUP(scif4_data_c),
4391 SH_PFC_PIN_GROUP(scif4_clk_c),
4392 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4393 SH_PFC_PIN_GROUP(scif5_data_a),
4394 SH_PFC_PIN_GROUP(scif5_clk_a),
4395 SH_PFC_PIN_GROUP(scif5_data_b),
4396 SH_PFC_PIN_GROUP(scif5_clk_b),
d14a39ed
GU		 4397 SH_PFC_PIN_GROUP(scif_clk_a),
4398 SH_PFC_PIN_GROUP(scif_clk_b),
9ed13958
TK		 4399 SH_PFC_PIN_GROUP(sdhi0_data1),
4400 SH_PFC_PIN_GROUP(sdhi0_data4),
4401 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4402 SH_PFC_PIN_GROUP(sdhi0_cd),
4403 SH_PFC_PIN_GROUP(sdhi0_wp),
4404 SH_PFC_PIN_GROUP(sdhi1_data1),
4405 SH_PFC_PIN_GROUP(sdhi1_data4),
4406 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4407 SH_PFC_PIN_GROUP(sdhi1_cd),
4408 SH_PFC_PIN_GROUP(sdhi1_wp),
4409 SH_PFC_PIN_GROUP(sdhi2_data1),
4410 SH_PFC_PIN_GROUP(sdhi2_data4),
4411 SH_PFC_PIN_GROUP(sdhi2_data8),
4412 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4413 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4414 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4415 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4416 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4417 SH_PFC_PIN_GROUP(sdhi2_ds),
4418 SH_PFC_PIN_GROUP(sdhi3_data1),
4419 SH_PFC_PIN_GROUP(sdhi3_data4),
4420 SH_PFC_PIN_GROUP(sdhi3_data8),
4421 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4422 SH_PFC_PIN_GROUP(sdhi3_cd),
4423 SH_PFC_PIN_GROUP(sdhi3_wp),
4424 SH_PFC_PIN_GROUP(sdhi3_ds),
0526234d
KM		 4425 SH_PFC_PIN_GROUP(ssi0_data),
4426 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4427 SH_PFC_PIN_GROUP(ssi1_data_a),
4428 SH_PFC_PIN_GROUP(ssi1_data_b),
4429 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4430 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4431 SH_PFC_PIN_GROUP(ssi2_data_a),
4432 SH_PFC_PIN_GROUP(ssi2_data_b),
4433 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4434 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4435 SH_PFC_PIN_GROUP(ssi3_data),
4436 SH_PFC_PIN_GROUP(ssi349_ctrl),
4437 SH_PFC_PIN_GROUP(ssi4_data),
4438 SH_PFC_PIN_GROUP(ssi4_ctrl),
4439 SH_PFC_PIN_GROUP(ssi5_data),
4440 SH_PFC_PIN_GROUP(ssi5_ctrl),
4441 SH_PFC_PIN_GROUP(ssi6_data),
4442 SH_PFC_PIN_GROUP(ssi6_ctrl),
4443 SH_PFC_PIN_GROUP(ssi7_data),
4444 SH_PFC_PIN_GROUP(ssi78_ctrl),
4445 SH_PFC_PIN_GROUP(ssi8_data),
4446 SH_PFC_PIN_GROUP(ssi9_data_a),
4447 SH_PFC_PIN_GROUP(ssi9_data_b),
4448 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4449 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
edcc14c8
TK		 4450 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4451 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4452 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4453 SH_PFC_PIN_GROUP(tmu_tclk2_b),
933ddbe5
YS		 4454 SH_PFC_PIN_GROUP(usb0),
4455 SH_PFC_PIN_GROUP(usb1),
4456 SH_PFC_PIN_GROUP(usb2),
4457 SH_PFC_PIN_GROUP(usb2_ch3),
5ec8a41a 4458 SH_PFC_PIN_GROUP(usb30),
184844cc
JM		 4459 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4460 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4461 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4462 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
6b4de408 4463 SH_PFC_PIN_GROUP(vin4_data18_a),
184844cc
JM		 4464 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4465 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4466 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4467 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4468 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4469 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
6b4de408 4470 SH_PFC_PIN_GROUP(vin4_data18_b),
184844cc
JM		 4471 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4472 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
6b4de408
UH		 4473 SH_PFC_PIN_GROUP(vin4_sync),
4474 SH_PFC_PIN_GROUP(vin4_field),
4475 SH_PFC_PIN_GROUP(vin4_clkenb),
4476 SH_PFC_PIN_GROUP(vin4_clk),
99fdb920
GU		 4477 VIN_DATA_PIN_GROUP(vin5_data, 8),
4478 VIN_DATA_PIN_GROUP(vin5_data, 10),
4479 VIN_DATA_PIN_GROUP(vin5_data, 12),
4480 VIN_DATA_PIN_GROUP(vin5_data, 16),
6b4de408
UH		 4481 SH_PFC_PIN_GROUP(vin5_sync),
4482 SH_PFC_PIN_GROUP(vin5_field),
4483 SH_PFC_PIN_GROUP(vin5_clkenb),
4484 SH_PFC_PIN_GROUP(vin5_clk),
e7ad4d3c
GU		 4485};
4486
55bfea9f
KM		 4487static const char * const audio_clk_groups[] = {
4488 "audio_clk_a_a",
4489 "audio_clk_a_b",
4490 "audio_clk_a_c",
4491 "audio_clk_b_a",
4492 "audio_clk_b_b",
4493 "audio_clk_c_a",
4494 "audio_clk_c_b",
4495 "audio_clkout_a",
4496 "audio_clkout_b",
4497 "audio_clkout_c",
4498 "audio_clkout_d",
4499 "audio_clkout1_a",
4500 "audio_clkout1_b",
4501 "audio_clkout2_a",
4502 "audio_clkout2_b",
4503 "audio_clkout3_a",
4504 "audio_clkout3_b",
4505};
4506
30c078de
GU		 4507static const char * const avb_groups[] = {
4508 "avb_link",
4509 "avb_magic",
4510 "avb_phy_int",
cbe0dd9a
GU		 4511 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4512 "avb_mdio",
30c078de
GU		 4513 "avb_mii",
4514 "avb_avtp_pps",
4515 "avb_avtp_match_a",
4516 "avb_avtp_capture_a",
4517 "avb_avtp_match_b",
4518 "avb_avtp_capture_b",
4519};
4520
a678abfe
RS		 4521static const char * const can0_groups[] = {
4522 "can0_data_a",
4523 "can0_data_b",
4524};
4525
4526static const char * const can1_groups[] = {
4527 "can1_data",
4528};
4529
4530static const char * const can_clk_groups[] = {
4531 "can_clk",
4532};
4533
0e1c7a94
RS		 4534static const char * const canfd0_groups[] = {
4535 "canfd0_data_a",
4536 "canfd0_data_b",
4537};
4538
4539static const char * const canfd1_groups[] = {
4540 "canfd1_data",
4541};
4542
641b0ab8
DB		 4543static const char * const drif0_groups[] = {
4544 "drif0_ctrl_a",
4545 "drif0_data0_a",
4546 "drif0_data1_a",
4547 "drif0_ctrl_b",
4548 "drif0_data0_b",
4549 "drif0_data1_b",
4550 "drif0_ctrl_c",
4551 "drif0_data0_c",
4552 "drif0_data1_c",
4553};
4554
4555static const char * const drif1_groups[] = {
4556 "drif1_ctrl_a",
4557 "drif1_data0_a",
4558 "drif1_data1_a",
4559 "drif1_ctrl_b",
4560 "drif1_data0_b",
4561 "drif1_data1_b",
4562 "drif1_ctrl_c",
4563 "drif1_data0_c",
4564 "drif1_data1_c",
4565};
4566
4567static const char * const drif2_groups[] = {
4568 "drif2_ctrl_a",
4569 "drif2_data0_a",
4570 "drif2_data1_a",
4571 "drif2_ctrl_b",
4572 "drif2_data0_b",
4573 "drif2_data1_b",
4574};
4575
4576static const char * const drif3_groups[] = {
4577 "drif3_ctrl_a",
4578 "drif3_data0_a",
4579 "drif3_data1_a",
4580 "drif3_ctrl_b",
4581 "drif3_data0_b",
4582 "drif3_data1_b",
4583};
4584
a20a6585
LP		 4585static const char * const du_groups[] = {
4586 "du_rgb666",
4587 "du_rgb888",
4588 "du_clk_out_0",
4589 "du_clk_out_1",
4590 "du_sync",
4591 "du_oddf",
4592 "du_cde",
4593 "du_disp",
4594};
4595
7a362e34
WS		 4596static const char * const hscif0_groups[] = {
4597 "hscif0_data",
4598 "hscif0_clk",
4599 "hscif0_ctrl",
4600};
4601
4602static const char * const hscif1_groups[] = {
4603 "hscif1_data_a",
4604 "hscif1_clk_a",
4605 "hscif1_ctrl_a",
4606 "hscif1_data_b",
4607 "hscif1_clk_b",
4608 "hscif1_ctrl_b",
4609};
4610
4611static const char * const hscif2_groups[] = {
4612 "hscif2_data_a",
4613 "hscif2_clk_a",
4614 "hscif2_ctrl_a",
4615 "hscif2_data_b",
4616 "hscif2_clk_b",
4617 "hscif2_ctrl_b",
4618 "hscif2_data_c",
4619 "hscif2_clk_c",
4620 "hscif2_ctrl_c",
4621};
4622
4623static const char * const hscif3_groups[] = {
4624 "hscif3_data_a",
4625 "hscif3_clk",
4626 "hscif3_ctrl",
4627 "hscif3_data_b",
4628 "hscif3_data_c",
4629 "hscif3_data_d",
4630};
4631
4632static const char * const hscif4_groups[] = {
4633 "hscif4_data_a",
4634 "hscif4_clk",
4635 "hscif4_ctrl",
4636 "hscif4_data_b",
4637};
4638
100431b6
TK		 4639static const char * const i2c0_groups[] = {
4640 "i2c0",
4641};
4642
f62d4c9e
WS		 4643static const char * const i2c1_groups[] = {
4644 "i2c1_a",
4645 "i2c1_b",
4646};
4647
4648static const char * const i2c2_groups[] = {
4649 "i2c2_a",
4650 "i2c2_b",
4651};
4652
100431b6
TK		 4653static const char * const i2c3_groups[] = {
4654 "i2c3",
4655};
4656
4657static const char * const i2c5_groups[] = {
4658 "i2c5",
4659};
4660
f62d4c9e
WS		 4661static const char * const i2c6_groups[] = {
4662 "i2c6_a",
4663 "i2c6_b",
4664 "i2c6_c",
4665};
4666
8480e6ca
GU		 4667static const char * const intc_ex_groups[] = {
4668 "intc_ex_irq0",
4669 "intc_ex_irq1",
4670 "intc_ex_irq2",
4671 "intc_ex_irq3",
4672 "intc_ex_irq4",
4673 "intc_ex_irq5",
4674};
4675
3e6c7727
GU		 4676static const char * const msiof0_groups[] = {
4677 "msiof0_clk",
4678 "msiof0_sync",
4679 "msiof0_ss1",
4680 "msiof0_ss2",
4681 "msiof0_txd",
4682 "msiof0_rxd",
4683};
4684
4685static const char * const msiof1_groups[] = {
4686 "msiof1_clk_a",
4687 "msiof1_sync_a",
4688 "msiof1_ss1_a",
4689 "msiof1_ss2_a",
4690 "msiof1_txd_a",
4691 "msiof1_rxd_a",
4692 "msiof1_clk_b",
4693 "msiof1_sync_b",
4694 "msiof1_ss1_b",
4695 "msiof1_ss2_b",
4696 "msiof1_txd_b",
4697 "msiof1_rxd_b",
4698 "msiof1_clk_c",
4699 "msiof1_sync_c",
4700 "msiof1_ss1_c",
4701 "msiof1_ss2_c",
4702 "msiof1_txd_c",
4703 "msiof1_rxd_c",
4704 "msiof1_clk_d",
4705 "msiof1_sync_d",
4706 "msiof1_ss1_d",
4707 "msiof1_ss2_d",
4708 "msiof1_txd_d",
4709 "msiof1_rxd_d",
4710 "msiof1_clk_e",
4711 "msiof1_sync_e",
4712 "msiof1_ss1_e",
4713 "msiof1_ss2_e",
4714 "msiof1_txd_e",
4715 "msiof1_rxd_e",
4716 "msiof1_clk_f",
4717 "msiof1_sync_f",
4718 "msiof1_ss1_f",
4719 "msiof1_ss2_f",
4720 "msiof1_txd_f",
4721 "msiof1_rxd_f",
4722 "msiof1_clk_g",
4723 "msiof1_sync_g",
4724 "msiof1_ss1_g",
4725 "msiof1_ss2_g",
4726 "msiof1_txd_g",
4727 "msiof1_rxd_g",
4728};
4729
4730static const char * const msiof2_groups[] = {
4731 "msiof2_clk_a",
4732 "msiof2_sync_a",
4733 "msiof2_ss1_a",
4734 "msiof2_ss2_a",
4735 "msiof2_txd_a",
4736 "msiof2_rxd_a",
4737 "msiof2_clk_b",
4738 "msiof2_sync_b",
4739 "msiof2_ss1_b",
4740 "msiof2_ss2_b",
4741 "msiof2_txd_b",
4742 "msiof2_rxd_b",
4743 "msiof2_clk_c",
4744 "msiof2_sync_c",
4745 "msiof2_ss1_c",
4746 "msiof2_ss2_c",
4747 "msiof2_txd_c",
4748 "msiof2_rxd_c",
4749 "msiof2_clk_d",
4750 "msiof2_sync_d",
4751 "msiof2_ss1_d",
4752 "msiof2_ss2_d",
4753 "msiof2_txd_d",
4754 "msiof2_rxd_d",
4755};
4756
4757static const char * const msiof3_groups[] = {
4758 "msiof3_clk_a",
4759 "msiof3_sync_a",
4760 "msiof3_ss1_a",
4761 "msiof3_ss2_a",
4762 "msiof3_txd_a",
4763 "msiof3_rxd_a",
4764 "msiof3_clk_b",
4765 "msiof3_sync_b",
4766 "msiof3_ss1_b",
4767 "msiof3_ss2_b",
4768 "msiof3_txd_b",
4769 "msiof3_rxd_b",
4770 "msiof3_clk_c",
4771 "msiof3_sync_c",
4772 "msiof3_txd_c",
4773 "msiof3_rxd_c",
4774 "msiof3_clk_d",
4775 "msiof3_sync_d",
4776 "msiof3_ss1_d",
4777 "msiof3_txd_d",
4778 "msiof3_rxd_d",
4779 "msiof3_clk_e",
4780 "msiof3_sync_e",
4781 "msiof3_ss1_e",
4782 "msiof3_ss2_e",
4783 "msiof3_txd_e",
4784 "msiof3_rxd_e",
4785};
4786
c03a133b
LP		 4787static const char * const pwm0_groups[] = {
4788 "pwm0",
4789};
4790
4791static const char * const pwm1_groups[] = {
4792 "pwm1_a",
4793 "pwm1_b",
4794};
4795
4796static const char * const pwm2_groups[] = {
4797 "pwm2_a",
4798 "pwm2_b",
4799};
4800
4801static const char * const pwm3_groups[] = {
4802 "pwm3_a",
4803 "pwm3_b",
4804};
4805
4806static const char * const pwm4_groups[] = {
4807 "pwm4_a",
4808 "pwm4_b",
4809};
4810
4811static const char * const pwm5_groups[] = {
4812 "pwm5_a",
4813 "pwm5_b",
4814};
4815
4816static const char * const pwm6_groups[] = {
4817 "pwm6_a",
4818 "pwm6_b",
4819};
4820
297e5b2b
WS		 4821static const char * const sata0_groups[] = {
4822 "sata0_devslp_a",
4823 "sata0_devslp_b",
4824};
4825
e7ad4d3c
GU		 4826static const char * const scif0_groups[] = {
4827 "scif0_data",
4828 "scif0_clk",
4829 "scif0_ctrl",
4830};
4831
4832static const char * const scif1_groups[] = {
4833 "scif1_data_a",
4834 "scif1_clk",
4835 "scif1_ctrl",
4836 "scif1_data_b",
4837};
4838
4839static const char * const scif2_groups[] = {
4840 "scif2_data_a",
4841 "scif2_clk",
4842 "scif2_data_b",
4843};
4844
4845static const char * const scif3_groups[] = {
4846 "scif3_data_a",
4847 "scif3_clk",
4848 "scif3_ctrl",
4849 "scif3_data_b",
4850};
4851
4852static const char * const scif4_groups[] = {
4853 "scif4_data_a",
4854 "scif4_clk_a",
4855 "scif4_ctrl_a",
4856 "scif4_data_b",
4857 "scif4_clk_b",
4858 "scif4_ctrl_b",
4859 "scif4_data_c",
4860 "scif4_clk_c",
4861 "scif4_ctrl_c",
4862};
4863
4864static const char * const scif5_groups[] = {
4865 "scif5_data_a",
4866 "scif5_clk_a",
4867 "scif5_data_b",
4868 "scif5_clk_b",
76250a6c
TK		 4869};
4870
d14a39ed
GU		 4871static const char * const scif_clk_groups[] = {
4872 "scif_clk_a",
4873 "scif_clk_b",
4874};
4875
9ed13958
TK		 4876static const char * const sdhi0_groups[] = {
4877 "sdhi0_data1",
4878 "sdhi0_data4",
4879 "sdhi0_ctrl",
4880 "sdhi0_cd",
4881 "sdhi0_wp",
4882};
4883
4884static const char * const sdhi1_groups[] = {
4885 "sdhi1_data1",
4886 "sdhi1_data4",
4887 "sdhi1_ctrl",
4888 "sdhi1_cd",
4889 "sdhi1_wp",
4890};
4891
4892static const char * const sdhi2_groups[] = {
4893 "sdhi2_data1",
4894 "sdhi2_data4",
4895 "sdhi2_data8",
4896 "sdhi2_ctrl",
4897 "sdhi2_cd_a",
4898 "sdhi2_wp_a",
4899 "sdhi2_cd_b",
4900 "sdhi2_wp_b",
4901 "sdhi2_ds",
4902};
4903
4904static const char * const sdhi3_groups[] = {
4905 "sdhi3_data1",
4906 "sdhi3_data4",
4907 "sdhi3_data8",
4908 "sdhi3_ctrl",
4909 "sdhi3_cd",
4910 "sdhi3_wp",
4911 "sdhi3_ds",
4912};
4913
0526234d
KM		 4914static const char * const ssi_groups[] = {
4915 "ssi0_data",
4916 "ssi01239_ctrl",
4917 "ssi1_data_a",
4918 "ssi1_data_b",
4919 "ssi1_ctrl_a",
4920 "ssi1_ctrl_b",
4921 "ssi2_data_a",
4922 "ssi2_data_b",
4923 "ssi2_ctrl_a",
4924 "ssi2_ctrl_b",
4925 "ssi3_data",
4926 "ssi349_ctrl",
4927 "ssi4_data",
4928 "ssi4_ctrl",
4929 "ssi5_data",
4930 "ssi5_ctrl",
4931 "ssi6_data",
4932 "ssi6_ctrl",
4933 "ssi7_data",
4934 "ssi78_ctrl",
4935 "ssi8_data",
4936 "ssi9_data_a",
4937 "ssi9_data_b",
4938 "ssi9_ctrl_a",
4939 "ssi9_ctrl_b",
4940};
4941
edcc14c8
TK		 4942static const char * const tmu_groups[] = {
4943 "tmu_tclk1_a",
4944 "tmu_tclk1_b",
4945 "tmu_tclk2_a",
4946 "tmu_tclk2_b",
4947};
4948
933ddbe5
YS		 4949static const char * const usb0_groups[] = {
4950 "usb0",
4951};
4952
4953static const char * const usb1_groups[] = {
4954 "usb1",
4955};
4956
4957static const char * const usb2_groups[] = {
4958 "usb2",
4959};
4960
4961static const char * const usb2_ch3_groups[] = {
4962 "usb2_ch3",
4963};
4964
5ec8a41a
TK		 4965static const char * const usb30_groups[] = {
4966 "usb30",
4967};
4968
6b4de408
UH		 4969static const char * const vin4_groups[] = {
4970 "vin4_data8_a",
4971 "vin4_data10_a",
4972 "vin4_data12_a",
4973 "vin4_data16_a",
4974 "vin4_data18_a",
4975 "vin4_data20_a",
4976 "vin4_data24_a",
4977 "vin4_data8_b",
4978 "vin4_data10_b",
4979 "vin4_data12_b",
4980 "vin4_data16_b",
4981 "vin4_data18_b",
4982 "vin4_data20_b",
4983 "vin4_data24_b",
4984 "vin4_sync",
4985 "vin4_field",
4986 "vin4_clkenb",
4987 "vin4_clk",
4988};
4989
4990static const char * const vin5_groups[] = {
4991 "vin5_data8",
4992 "vin5_data10",
4993 "vin5_data12",
4994 "vin5_data16",
4995 "vin5_sync",
4996 "vin5_field",
4997 "vin5_clkenb",
4998 "vin5_clk",
4999};
5000
0b0ffc96 5001static const struct sh_pfc_function pinmux_functions[] = {
55bfea9f 5002 SH_PFC_FUNCTION(audio_clk),
30c078de 5003 SH_PFC_FUNCTION(avb),
a678abfe
RS		 5004 SH_PFC_FUNCTION(can0),
5005 SH_PFC_FUNCTION(can1),
5006 SH_PFC_FUNCTION(can_clk),
0e1c7a94
RS		 5007 SH_PFC_FUNCTION(canfd0),
5008 SH_PFC_FUNCTION(canfd1),
641b0ab8
DB		 5009 SH_PFC_FUNCTION(drif0),
5010 SH_PFC_FUNCTION(drif1),
5011 SH_PFC_FUNCTION(drif2),
5012 SH_PFC_FUNCTION(drif3),
a20a6585 5013 SH_PFC_FUNCTION(du),
7a362e34
WS		 5014 SH_PFC_FUNCTION(hscif0),
5015 SH_PFC_FUNCTION(hscif1),
5016 SH_PFC_FUNCTION(hscif2),
5017 SH_PFC_FUNCTION(hscif3),
5018 SH_PFC_FUNCTION(hscif4),
100431b6 5019 SH_PFC_FUNCTION(i2c0),
f62d4c9e
WS		 5020 SH_PFC_FUNCTION(i2c1),
5021 SH_PFC_FUNCTION(i2c2),
100431b6
TK		 5022 SH_PFC_FUNCTION(i2c3),
5023 SH_PFC_FUNCTION(i2c5),
f62d4c9e 5024 SH_PFC_FUNCTION(i2c6),
8480e6ca 5025 SH_PFC_FUNCTION(intc_ex),
3e6c7727
GU		 5026 SH_PFC_FUNCTION(msiof0),
5027 SH_PFC_FUNCTION(msiof1),
5028 SH_PFC_FUNCTION(msiof2),
5029 SH_PFC_FUNCTION(msiof3),
c03a133b
LP		 5030 SH_PFC_FUNCTION(pwm0),
5031 SH_PFC_FUNCTION(pwm1),
5032 SH_PFC_FUNCTION(pwm2),
5033 SH_PFC_FUNCTION(pwm3),
5034 SH_PFC_FUNCTION(pwm4),
5035 SH_PFC_FUNCTION(pwm5),
5036 SH_PFC_FUNCTION(pwm6),
297e5b2b 5037 SH_PFC_FUNCTION(sata0),
e7ad4d3c
GU		 5038 SH_PFC_FUNCTION(scif0),
5039 SH_PFC_FUNCTION(scif1),
5040 SH_PFC_FUNCTION(scif2),
5041 SH_PFC_FUNCTION(scif3),
5042 SH_PFC_FUNCTION(scif4),
5043 SH_PFC_FUNCTION(scif5),
d14a39ed 5044 SH_PFC_FUNCTION(scif_clk),
9ed13958
TK		 5045 SH_PFC_FUNCTION(sdhi0),
5046 SH_PFC_FUNCTION(sdhi1),
5047 SH_PFC_FUNCTION(sdhi2),
5048 SH_PFC_FUNCTION(sdhi3),
0526234d 5049 SH_PFC_FUNCTION(ssi),
edcc14c8 5050 SH_PFC_FUNCTION(tmu),
933ddbe5
YS		 5051 SH_PFC_FUNCTION(usb0),
5052 SH_PFC_FUNCTION(usb1),
5053 SH_PFC_FUNCTION(usb2),
5054 SH_PFC_FUNCTION(usb2_ch3),
5ec8a41a 5055 SH_PFC_FUNCTION(usb30),
6b4de408
UH		 5056 SH_PFC_FUNCTION(vin4),
5057 SH_PFC_FUNCTION(vin5),
0b0ffc96
TK		 5058};
5059
5060static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5061#define F_(x, y) FN_##y
5062#define FM(x) FN_##x
efca8da0 5063 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0b0ffc96
TK		 5064 0, 0,
5065 0, 0,
5066 0, 0,
5067 0, 0,
5068 0, 0,
5069 0, 0,
5070 0, 0,
5071 0, 0,
5072 0, 0,
5073 0, 0,
5074 0, 0,
5075 0, 0,
5076 0, 0,
5077 0, 0,
5078 0, 0,
5079 0, 0,
5080 GP_0_15_FN, GPSR0_15,
5081 GP_0_14_FN, GPSR0_14,
5082 GP_0_13_FN, GPSR0_13,
5083 GP_0_12_FN, GPSR0_12,
5084 GP_0_11_FN, GPSR0_11,
5085 GP_0_10_FN, GPSR0_10,
5086 GP_0_9_FN, GPSR0_9,
5087 GP_0_8_FN, GPSR0_8,
5088 GP_0_7_FN, GPSR0_7,
5089 GP_0_6_FN, GPSR0_6,
5090 GP_0_5_FN, GPSR0_5,
5091 GP_0_4_FN, GPSR0_4,
5092 GP_0_3_FN, GPSR0_3,
5093 GP_0_2_FN, GPSR0_2,
5094 GP_0_1_FN, GPSR0_1,
efca8da0 5095 GP_0_0_FN, GPSR0_0, ))
0b0ffc96 5096 },
efca8da0 5097 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0b0ffc96
TK		 5098 0, 0,
5099 0, 0,
5100 0, 0,
82d2de5a 5101 GP_1_28_FN, GPSR1_28,
0b0ffc96
TK		 5102 GP_1_27_FN, GPSR1_27,
5103 GP_1_26_FN, GPSR1_26,
5104 GP_1_25_FN, GPSR1_25,
5105 GP_1_24_FN, GPSR1_24,
5106 GP_1_23_FN, GPSR1_23,
5107 GP_1_22_FN, GPSR1_22,
5108 GP_1_21_FN, GPSR1_21,
5109 GP_1_20_FN, GPSR1_20,
5110 GP_1_19_FN, GPSR1_19,
5111 GP_1_18_FN, GPSR1_18,
5112 GP_1_17_FN, GPSR1_17,
5113 GP_1_16_FN, GPSR1_16,
5114 GP_1_15_FN, GPSR1_15,
5115 GP_1_14_FN, GPSR1_14,
5116 GP_1_13_FN, GPSR1_13,
5117 GP_1_12_FN, GPSR1_12,
5118 GP_1_11_FN, GPSR1_11,
5119 GP_1_10_FN, GPSR1_10,
5120 GP_1_9_FN, GPSR1_9,
5121 GP_1_8_FN, GPSR1_8,
5122 GP_1_7_FN, GPSR1_7,
5123 GP_1_6_FN, GPSR1_6,
5124 GP_1_5_FN, GPSR1_5,
5125 GP_1_4_FN, GPSR1_4,
5126 GP_1_3_FN, GPSR1_3,
5127 GP_1_2_FN, GPSR1_2,
5128 GP_1_1_FN, GPSR1_1,
efca8da0 5129 GP_1_0_FN, GPSR1_0, ))
0b0ffc96 5130 },
efca8da0 5131 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0b0ffc96
TK		 5132 0, 0,
5133 0, 0,
5134 0, 0,
5135 0, 0,
5136 0, 0,
5137 0, 0,
5138 0, 0,
5139 0, 0,
5140 0, 0,
5141 0, 0,
5142 0, 0,
5143 0, 0,
5144 0, 0,
5145 0, 0,
5146 0, 0,
5147 0, 0,
5148 0, 0,
5149 GP_2_14_FN, GPSR2_14,
5150 GP_2_13_FN, GPSR2_13,
5151 GP_2_12_FN, GPSR2_12,
5152 GP_2_11_FN, GPSR2_11,
5153 GP_2_10_FN, GPSR2_10,
5154 GP_2_9_FN, GPSR2_9,
5155 GP_2_8_FN, GPSR2_8,
5156 GP_2_7_FN, GPSR2_7,
5157 GP_2_6_FN, GPSR2_6,
5158 GP_2_5_FN, GPSR2_5,
5159 GP_2_4_FN, GPSR2_4,
5160 GP_2_3_FN, GPSR2_3,
5161 GP_2_2_FN, GPSR2_2,
5162 GP_2_1_FN, GPSR2_1,
efca8da0 5163 GP_2_0_FN, GPSR2_0, ))
0b0ffc96 5164 },
efca8da0 5165 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0b0ffc96
TK		 5166 0, 0,
5167 0, 0,
5168 0, 0,
5169 0, 0,
5170 0, 0,
5171 0, 0,
5172 0, 0,
5173 0, 0,
5174 0, 0,
5175 0, 0,
5176 0, 0,
5177 0, 0,
5178 0, 0,
5179 0, 0,
5180 0, 0,
5181 0, 0,
5182 GP_3_15_FN, GPSR3_15,
5183 GP_3_14_FN, GPSR3_14,
5184 GP_3_13_FN, GPSR3_13,
5185 GP_3_12_FN, GPSR3_12,
5186 GP_3_11_FN, GPSR3_11,
5187 GP_3_10_FN, GPSR3_10,
5188 GP_3_9_FN, GPSR3_9,
5189 GP_3_8_FN, GPSR3_8,
5190 GP_3_7_FN, GPSR3_7,
5191 GP_3_6_FN, GPSR3_6,
5192 GP_3_5_FN, GPSR3_5,
5193 GP_3_4_FN, GPSR3_4,
5194 GP_3_3_FN, GPSR3_3,
5195 GP_3_2_FN, GPSR3_2,
5196 GP_3_1_FN, GPSR3_1,
efca8da0 5197 GP_3_0_FN, GPSR3_0, ))
0b0ffc96 5198 },
efca8da0 5199 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0b0ffc96
TK		 5200 0, 0,
5201 0, 0,
5202 0, 0,
5203 0, 0,
5204 0, 0,
5205 0, 0,
5206 0, 0,
5207 0, 0,
5208 0, 0,
5209 0, 0,
5210 0, 0,
5211 0, 0,
5212 0, 0,
5213 0, 0,
5214 GP_4_17_FN, GPSR4_17,
5215 GP_4_16_FN, GPSR4_16,
5216 GP_4_15_FN, GPSR4_15,
5217 GP_4_14_FN, GPSR4_14,
5218 GP_4_13_FN, GPSR4_13,
5219 GP_4_12_FN, GPSR4_12,
5220 GP_4_11_FN, GPSR4_11,
5221 GP_4_10_FN, GPSR4_10,
5222 GP_4_9_FN, GPSR4_9,
5223 GP_4_8_FN, GPSR4_8,
5224 GP_4_7_FN, GPSR4_7,
5225 GP_4_6_FN, GPSR4_6,
5226 GP_4_5_FN, GPSR4_5,
5227 GP_4_4_FN, GPSR4_4,
5228 GP_4_3_FN, GPSR4_3,
5229 GP_4_2_FN, GPSR4_2,
5230 GP_4_1_FN, GPSR4_1,
efca8da0 5231 GP_4_0_FN, GPSR4_0, ))
0b0ffc96 5232 },
efca8da0 5233 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0b0ffc96
TK		 5234 0, 0,
5235 0, 0,
5236 0, 0,
5237 0, 0,
5238 0, 0,
5239 0, 0,
5240 GP_5_25_FN, GPSR5_25,
5241 GP_5_24_FN, GPSR5_24,
5242 GP_5_23_FN, GPSR5_23,
5243 GP_5_22_FN, GPSR5_22,
5244 GP_5_21_FN, GPSR5_21,
5245 GP_5_20_FN, GPSR5_20,
5246 GP_5_19_FN, GPSR5_19,
5247 GP_5_18_FN, GPSR5_18,
5248 GP_5_17_FN, GPSR5_17,
5249 GP_5_16_FN, GPSR5_16,
5250 GP_5_15_FN, GPSR5_15,
5251 GP_5_14_FN, GPSR5_14,
5252 GP_5_13_FN, GPSR5_13,
5253 GP_5_12_FN, GPSR5_12,
5254 GP_5_11_FN, GPSR5_11,
5255 GP_5_10_FN, GPSR5_10,
5256 GP_5_9_FN, GPSR5_9,
5257 GP_5_8_FN, GPSR5_8,
5258 GP_5_7_FN, GPSR5_7,
5259 GP_5_6_FN, GPSR5_6,
5260 GP_5_5_FN, GPSR5_5,
5261 GP_5_4_FN, GPSR5_4,
5262 GP_5_3_FN, GPSR5_3,
5263 GP_5_2_FN, GPSR5_2,
5264 GP_5_1_FN, GPSR5_1,
efca8da0 5265 GP_5_0_FN, GPSR5_0, ))
0b0ffc96 5266 },
efca8da0 5267 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
0b0ffc96
TK		 5268 GP_6_31_FN, GPSR6_31,
5269 GP_6_30_FN, GPSR6_30,
5270 GP_6_29_FN, GPSR6_29,
5271 GP_6_28_FN, GPSR6_28,
5272 GP_6_27_FN, GPSR6_27,
5273 GP_6_26_FN, GPSR6_26,
5274 GP_6_25_FN, GPSR6_25,
5275 GP_6_24_FN, GPSR6_24,
5276 GP_6_23_FN, GPSR6_23,
5277 GP_6_22_FN, GPSR6_22,
5278 GP_6_21_FN, GPSR6_21,
5279 GP_6_20_FN, GPSR6_20,
5280 GP_6_19_FN, GPSR6_19,
5281 GP_6_18_FN, GPSR6_18,
5282 GP_6_17_FN, GPSR6_17,
5283 GP_6_16_FN, GPSR6_16,
5284 GP_6_15_FN, GPSR6_15,
5285 GP_6_14_FN, GPSR6_14,
5286 GP_6_13_FN, GPSR6_13,
5287 GP_6_12_FN, GPSR6_12,
5288 GP_6_11_FN, GPSR6_11,
5289 GP_6_10_FN, GPSR6_10,
5290 GP_6_9_FN, GPSR6_9,
5291 GP_6_8_FN, GPSR6_8,
5292 GP_6_7_FN, GPSR6_7,
5293 GP_6_6_FN, GPSR6_6,
5294 GP_6_5_FN, GPSR6_5,
5295 GP_6_4_FN, GPSR6_4,
5296 GP_6_3_FN, GPSR6_3,
5297 GP_6_2_FN, GPSR6_2,
5298 GP_6_1_FN, GPSR6_1,
efca8da0 5299 GP_6_0_FN, GPSR6_0, ))
0b0ffc96 5300 },
efca8da0 5301 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0b0ffc96
TK		 5302 0, 0,
5303 0, 0,
5304 0, 0,
5305 0, 0,
5306 0, 0,
5307 0, 0,
5308 0, 0,
5309 0, 0,
5310 0, 0,
5311 0, 0,
5312 0, 0,
5313 0, 0,
5314 0, 0,
5315 0, 0,
5316 0, 0,
5317 0, 0,
5318 0, 0,
5319 0, 0,
5320 0, 0,
5321 0, 0,
5322 0, 0,
5323 0, 0,
5324 0, 0,
5325 0, 0,
5326 0, 0,
5327 0, 0,
5328 0, 0,
5329 0, 0,
5330 GP_7_3_FN, GPSR7_3,
5331 GP_7_2_FN, GPSR7_2,
5332 GP_7_1_FN, GPSR7_1,
efca8da0 5333 GP_7_0_FN, GPSR7_0, ))
0b0ffc96
TK		 5334 },
5335#undef F_
5336#undef FM
5337
5338#define F_(x, y) x,
5339#define FM(x) FN_##x,
efca8da0 5340 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
0b0ffc96
TK		 5341 IP0_31_28
5342 IP0_27_24
5343 IP0_23_20
5344 IP0_19_16
5345 IP0_15_12
5346 IP0_11_8
5347 IP0_7_4
efca8da0 5348 IP0_3_0 ))
0b0ffc96 5349 },
efca8da0 5350 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
0b0ffc96
TK		 5351 IP1_31_28
5352 IP1_27_24
5353 IP1_23_20
5354 IP1_19_16
5355 IP1_15_12
5356 IP1_11_8
5357 IP1_7_4
efca8da0 5358 IP1_3_0 ))
0b0ffc96 5359 },
efca8da0 5360 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
0b0ffc96
TK		 5361 IP2_31_28
5362 IP2_27_24
5363 IP2_23_20
5364 IP2_19_16
5365 IP2_15_12
5366 IP2_11_8
5367 IP2_7_4
efca8da0 5368 IP2_3_0 ))
0b0ffc96 5369 },
efca8da0 5370 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
0b0ffc96
TK		 5371 IP3_31_28
5372 IP3_27_24
5373 IP3_23_20
5374 IP3_19_16
5375 IP3_15_12
5376 IP3_11_8
5377 IP3_7_4
efca8da0 5378 IP3_3_0 ))
0b0ffc96 5379 },
efca8da0 5380 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
0b0ffc96
TK		 5381 IP4_31_28
5382 IP4_27_24
5383 IP4_23_20
5384 IP4_19_16
5385 IP4_15_12
5386 IP4_11_8
5387 IP4_7_4
efca8da0 5388 IP4_3_0 ))
0b0ffc96 5389 },
efca8da0 5390 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
0b0ffc96
TK		 5391 IP5_31_28
5392 IP5_27_24
5393 IP5_23_20
5394 IP5_19_16
5395 IP5_15_12
5396 IP5_11_8
5397 IP5_7_4
efca8da0 5398 IP5_3_0 ))
0b0ffc96 5399 },
efca8da0 5400 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
0b0ffc96
TK		 5401 IP6_31_28
5402 IP6_27_24
5403 IP6_23_20
5404 IP6_19_16
5405 IP6_15_12
5406 IP6_11_8
5407 IP6_7_4
efca8da0 5408 IP6_3_0 ))
0b0ffc96 5409 },
efca8da0 5410 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
0b0ffc96
TK		 5411 IP7_31_28
5412 IP7_27_24
5413 IP7_23_20
5414 IP7_19_16
30cd1c46 5415 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 5416 IP7_11_8
5417 IP7_7_4
efca8da0 5418 IP7_3_0 ))
0b0ffc96 5419 },
efca8da0 5420 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
0b0ffc96
TK		 5421 IP8_31_28
5422 IP8_27_24
5423 IP8_23_20
5424 IP8_19_16
5425 IP8_15_12
5426 IP8_11_8
5427 IP8_7_4
efca8da0 5428 IP8_3_0 ))
0b0ffc96 5429 },
efca8da0 5430 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
0b0ffc96
TK		 5431 IP9_31_28
5432 IP9_27_24
5433 IP9_23_20
5434 IP9_19_16
5435 IP9_15_12
5436 IP9_11_8
5437 IP9_7_4
efca8da0 5438 IP9_3_0 ))
0b0ffc96 5439 },
efca8da0 5440 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
0b0ffc96
TK		 5441 IP10_31_28
5442 IP10_27_24
5443 IP10_23_20
5444 IP10_19_16
5445 IP10_15_12
5446 IP10_11_8
5447 IP10_7_4
efca8da0 5448 IP10_3_0 ))
0b0ffc96 5449 },
efca8da0 5450 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
0b0ffc96
TK		 5451 IP11_31_28
5452 IP11_27_24
5453 IP11_23_20
5454 IP11_19_16
5455 IP11_15_12
5456 IP11_11_8
5457 IP11_7_4
efca8da0 5458 IP11_3_0 ))
0b0ffc96 5459 },
efca8da0 5460 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
0b0ffc96
TK		 5461 IP12_31_28
5462 IP12_27_24
5463 IP12_23_20
5464 IP12_19_16
5465 IP12_15_12
5466 IP12_11_8
5467 IP12_7_4
efca8da0 5468 IP12_3_0 ))
0b0ffc96 5469 },
efca8da0 5470 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
0b0ffc96
TK		 5471 IP13_31_28
5472 IP13_27_24
5473 IP13_23_20
5474 IP13_19_16
5475 IP13_15_12
5476 IP13_11_8
5477 IP13_7_4
efca8da0 5478 IP13_3_0 ))
0b0ffc96 5479 },
efca8da0 5480 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
0b0ffc96
TK		 5481 IP14_31_28
5482 IP14_27_24
5483 IP14_23_20
5484 IP14_19_16
5485 IP14_15_12
5486 IP14_11_8
5487 IP14_7_4
efca8da0 5488 IP14_3_0 ))
0b0ffc96 5489 },
efca8da0 5490 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
0b0ffc96
TK		 5491 IP15_31_28
5492 IP15_27_24
5493 IP15_23_20
5494 IP15_19_16
5495 IP15_15_12
5496 IP15_11_8
5497 IP15_7_4
efca8da0 5498 IP15_3_0 ))
0b0ffc96 5499 },
efca8da0 5500 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
0b0ffc96
TK		 5501 IP16_31_28
5502 IP16_27_24
5503 IP16_23_20
5504 IP16_19_16
5505 IP16_15_12
5506 IP16_11_8
5507 IP16_7_4
efca8da0 5508 IP16_3_0 ))
0b0ffc96 5509 },
efca8da0 5510 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
b205914c
GU		 5511 IP17_31_28
5512 IP17_27_24
5513 IP17_23_20
5514 IP17_19_16
5515 IP17_15_12
5516 IP17_11_8
0b0ffc96 5517 IP17_7_4
efca8da0 5518 IP17_3_0 ))
0b0ffc96 5519 },
efca8da0 5520 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
b205914c
GU		 5521 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5522 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5523 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5524 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5525 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5526 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5527 IP18_7_4
efca8da0 5528 IP18_3_0 ))
b205914c 5529 },
0b0ffc96
TK		 5530#undef F_
5531#undef FM
5532
5533#define F_(x, y) x,
5534#define FM(x) FN_##x,
5535 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
69f7be1c
GU		 5536 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5537 1, 1, 1, 2, 2, 1, 2, 3),
5538 GROUP(
b205914c 5539 MOD_SEL0_31_30_29
0b0ffc96
TK		 5540 MOD_SEL0_28_27
5541 MOD_SEL0_26_25_24
5542 MOD_SEL0_23
5543 MOD_SEL0_22
b205914c
GU		 5544 MOD_SEL0_21
5545 MOD_SEL0_20
0b0ffc96 5546 MOD_SEL0_19
b205914c
GU		 5547 MOD_SEL0_18_17
5548 MOD_SEL0_16
5549 0, 0, /* RESERVED 15 */
5550 MOD_SEL0_14_13
0b0ffc96
TK		 5551 MOD_SEL0_12
5552 MOD_SEL0_11
5553 MOD_SEL0_10
b205914c 5554 MOD_SEL0_9_8
0b0ffc96 5555 MOD_SEL0_7_6
b205914c
GU		 5556 MOD_SEL0_5
5557 MOD_SEL0_4_3
5558 /* RESERVED 2, 1, 0 */
69f7be1c 5559 0, 0, 0, 0, 0, 0, 0, 0 ))
0b0ffc96
TK		 5560 },
5561 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
69f7be1c
GU		 5562 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5563 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5564 GROUP(
0b0ffc96
TK		 5565 MOD_SEL1_31_30
5566 MOD_SEL1_29_28_27
5567 MOD_SEL1_26
5568 MOD_SEL1_25_24
5569 MOD_SEL1_23_22_21
5570 MOD_SEL1_20
5571 MOD_SEL1_19
5572 MOD_SEL1_18_17
5573 MOD_SEL1_16
5574 MOD_SEL1_15_14
5575 MOD_SEL1_13
5576 MOD_SEL1_12
5577 MOD_SEL1_11
5578 MOD_SEL1_10
5579 MOD_SEL1_9
5580 0, 0, 0, 0, /* RESERVED 8, 7 */
5581 MOD_SEL1_6
5582 MOD_SEL1_5
5583 MOD_SEL1_4
5584 MOD_SEL1_3
5585 MOD_SEL1_2
5586 MOD_SEL1_1
69f7be1c 5587 MOD_SEL1_0 ))
0b0ffc96
TK		 5588 },
5589 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
69f7be1c
GU		 5590 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5591 1, 4, 4, 4, 3, 1),
5592 GROUP(
0b0ffc96
TK		 5593 MOD_SEL2_31
5594 MOD_SEL2_30
5595 MOD_SEL2_29
b205914c
GU		 5596 MOD_SEL2_28_27
5597 MOD_SEL2_26
5598 MOD_SEL2_25_24_23
3c612d2c
TK		 5599 /* RESERVED 22 */
5600 0, 0,
b205914c
GU		 5601 MOD_SEL2_21
5602 MOD_SEL2_20
5603 MOD_SEL2_19
5604 MOD_SEL2_18
5605 MOD_SEL2_17
5606 /* RESERVED 16 */
0b0ffc96 5607 0, 0,
0b0ffc96
TK		 5608 /* RESERVED 15, 14, 13, 12 */
5609 0, 0, 0, 0, 0, 0, 0, 0,
5610 0, 0, 0, 0, 0, 0, 0, 0,
5611 /* RESERVED 11, 10, 9, 8 */
5612 0, 0, 0, 0, 0, 0, 0, 0,
5613 0, 0, 0, 0, 0, 0, 0, 0,
5614 /* RESERVED 7, 6, 5, 4 */
5615 0, 0, 0, 0, 0, 0, 0, 0,
5616 0, 0, 0, 0, 0, 0, 0, 0,
b205914c
GU		 5617 /* RESERVED 3, 2, 1 */
5618 0, 0, 0, 0, 0, 0, 0, 0,
69f7be1c 5619 MOD_SEL2_0 ))
0b0ffc96
TK		 5620 },
5621 { },
5622};
5623
92e6d9a2 5624static const struct pinmux_drive_reg pinmux_drive_regs[] = {
ea9c7405
NS		 5625 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5626 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5627 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5628 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5629 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5630 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5631 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5632 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5633 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5634 } },
5635 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5636 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5637 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5638 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5639 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5640 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5641 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5642 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5643 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5644 } },
5645 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5646 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5647 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5648 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5649 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5650 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5651 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5652 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5653 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5654 } },
92e6d9a2 5655 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
ea9c7405
NS		 5656 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5657 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5658 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5659 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5660 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5661 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5662 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5663 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
92e6d9a2
LP		 5664 } },
5665 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5666 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5667 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5668 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5669 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5670 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5671 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5672 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5673 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5674 } },
5675 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5676 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5677 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5678 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5679 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5680 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5681 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5682 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5683 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5684 } },
5685 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5686 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5687 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5688 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5689 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5690 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5691 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5692 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5693 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5694 } },
5695 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5696 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5697 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5698 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5699 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5700 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5701 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5702 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5703 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5704 } },
5705 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
82d2de5a 5706 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
92e6d9a2
LP		 5707 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5708 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5709 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5710 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5711 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5712 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5713 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5714 } },
5715 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5716 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
ea9c7405 5717 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
92e6d9a2
LP		 5718 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5719 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5720 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5721 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5722 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5723 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5724 } },
5725 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5726 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5727 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5728 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5729 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5730 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5731 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5732 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5733 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5734 } },
5735 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
ea9c7405
NS		 5736 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5737 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5738 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5739 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5671f8e0
TK		 5740 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5741 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
ea9c7405
NS		 5742 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5743 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5744 } },
5745 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5746 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5747 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5748 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5749 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
92e6d9a2
LP		 5750 } },
5751 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
ea9c7405
NS		 5752 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5753 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5754 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5755 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5756 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5757 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5758 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5759 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
92e6d9a2
LP		 5760 } },
5761 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5762 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5763 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5764 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5765 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5766 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5767 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5768 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5769 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5770 } },
5771 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5772 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5773 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5774 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5775 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5776 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5777 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5778 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5779 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5780 } },
5781 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5782 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5783 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5784 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5785 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5786 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5787 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5788 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5789 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5790 } },
5791 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5792 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5793 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5794 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5795 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5796 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5797 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5798 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5799 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5800 } },
5801 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
8714a9c1 5802 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
92e6d9a2
LP		 5803 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5804 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5805 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
8714a9c1 5806 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
92e6d9a2
LP		 5807 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5808 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5809 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5810 } },
5811 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5812 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5813 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5814 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5815 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5816 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5817 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5818 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5819 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5820 } },
5821 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5822 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5823 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5824 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5825 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5826 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5827 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
ea9c7405 5828 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
92e6d9a2
LP		 5829 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5830 } },
5831 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5832 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5833 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5834 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5835 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
68e63892
KM		 5836 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5837 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
92e6d9a2
LP		 5838 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5839 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5840 } },
5841 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5842 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5843 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5844 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5845 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5846 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5847 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5848 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5849 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5850 } },
5851 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5852 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5853 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5854 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5855 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5856 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5857 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5858 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5859 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5860 } },
5861 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5862 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5863 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5864 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5865 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5866 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
f9d13080
YS		 5867 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5868 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
92e6d9a2
LP		 5869 } },
5870 { },
5871};
5872
e2aad846
GU		 5873enum ioctrl_regs {
5874 POCCTRL,
d92ee9cf 5875 TDSELCTRL,
e2aad846
GU		 5876};
5877
5878static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5879 [POCCTRL] = { 0xe6060380, },
d92ee9cf 5880 [TDSELCTRL] = { 0xe60603c0, },
e2aad846
GU		 5881 { /* sentinel */ },
5882};
5883
e9eace32
WS		 5884static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5885{
5886 int bit = -EINVAL;
5887
e2aad846 5888 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
e9eace32
WS		 5889
5890 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5891 bit = pin & 0x1f;
5892
5893 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5894 bit = (pin & 0x1f) + 12;
5895
5896 return bit;
5897}
5898
6f4b74f3
GU		 5899static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5900 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5901 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5902 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5903 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5904 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5905 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5906 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5907 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5908 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5909 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5910 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5911 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5912 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5913 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5914 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5915 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5916 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5917 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5918 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5919 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5920 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5921 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5922 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5923 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5924 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5925 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5926 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5927 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5928 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5929 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5930 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5931 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5932 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5933 } },
5934 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5935 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5936 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5937 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5938 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5939 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5940 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5941 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5942 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5943 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5944 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5945 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5946 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5947 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5948 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5949 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5950 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5951 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5952 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5953 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5954 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5955 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5956 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5957 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5958 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5959 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5960 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5961 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5962 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5963 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5964 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5965 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5966 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5967 } },
5968 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
82d2de5a 5969 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6f4b74f3
GU		 5970 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5971 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5972 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5973 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5974 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5975 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5976 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5977 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5978 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5979 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5980 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5981 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5982 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5983 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5984 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5985 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5986 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5987 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5988 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5989 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5990 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5991 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5992 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5993 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5994 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5995 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5996 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5671f8e0
TK		 5997 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5998 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
6f4b74f3
GU		 5999 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6000 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6001 } },
6002 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6003 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
6004 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
6005 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
6006 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6007 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6008 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6009 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6010 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6011 [ 8] = PIN_NONE,
6012 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6013 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6014 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6015 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6016 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6017 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6018 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6019 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6020 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6021 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6022 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6023 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6024 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6025 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6026 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6027 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6028 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6029 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6030 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6031 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6032 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6033 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6034 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6035 } },
6036 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6037 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6038 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6039 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6040 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6041 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6042 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6043 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6044 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6045 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6046 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6047 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6048 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6049 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6050 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6051 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6052 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
8714a9c1 6053 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6f4b74f3
GU		 6054 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6055 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6056 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
8714a9c1 6057 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6f4b74f3
GU		 6058 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6059 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6060 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6061 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6062 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6063 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6064 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6065 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6066 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6067 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6068 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6069 } },
6070 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6071 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6072 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6073 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6074 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6075 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6076 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6077 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6078 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6079 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6080 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6081 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6082 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6083 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6084 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6085 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6086 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6087 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6088 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6089 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6090 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6091 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6092 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6093 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6094 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6095 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6096 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6097 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6098 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6099 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6100 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6101 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6102 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6103 } },
6104 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6105 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6106 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6107 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6108 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6109 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6110 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6111 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
6112 [ 7] = PIN_NONE,
6113 [ 8] = PIN_NONE,
6114 [ 9] = PIN_NONE,
6115 [10] = PIN_NONE,
6116 [11] = PIN_NONE,
6117 [12] = PIN_NONE,
6118 [13] = PIN_NONE,
6119 [14] = PIN_NONE,
6120 [15] = PIN_NONE,
6121 [16] = PIN_NONE,
6122 [17] = PIN_NONE,
6123 [18] = PIN_NONE,
6124 [19] = PIN_NONE,
6125 [20] = PIN_NONE,
6126 [21] = PIN_NONE,
6127 [22] = PIN_NONE,
6128 [23] = PIN_NONE,
6129 [24] = PIN_NONE,
6130 [25] = PIN_NONE,
6131 [26] = PIN_NONE,
6132 [27] = PIN_NONE,
6133 [28] = PIN_NONE,
6134 [29] = PIN_NONE,
6135 [30] = PIN_NONE,
6136 [31] = PIN_NONE,
6137 } },
6138 { /* sentinel */ },
56065524
UH		 6139};
6140
6141static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
6142 unsigned int pin)
6143{
6f4b74f3
GU		 6144 const struct pinmux_bias_reg *reg;
6145 unsigned int bit;
56065524 6146
6f4b74f3
GU		 6147 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6148 if (!reg)
56065524
UH		 6149 return PIN_CONFIG_BIAS_DISABLE;
6150
6f4b74f3 6151 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
56065524 6152 return PIN_CONFIG_BIAS_DISABLE;
6f4b74f3 6153 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
42831cf9
NS		 6154 return PIN_CONFIG_BIAS_PULL_UP;
6155 else
6156 return PIN_CONFIG_BIAS_PULL_DOWN;
56065524
UH		 6157}
6158
6159static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6160 unsigned int bias)
6161{
6f4b74f3 6162 const struct pinmux_bias_reg *reg;
56065524 6163 u32 enable, updown;
6f4b74f3 6164 unsigned int bit;
56065524 6165
6f4b74f3
GU		 6166 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6167 if (!reg)
56065524
UH		 6168 return;
6169
6f4b74f3 6170 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
56065524 6171 if (bias != PIN_CONFIG_BIAS_DISABLE)
6f4b74f3 6172 enable |= BIT(bit);
56065524 6173
6f4b74f3 6174 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
56065524 6175 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6f4b74f3 6176 updown |= BIT(bit);
56065524 6177
6f4b74f3
GU		 6178 sh_pfc_write(pfc, reg->pud, updown);
6179 sh_pfc_write(pfc, reg->puen, enable);
56065524
UH		 6180}
6181
b205914c
GU		 6182static const struct soc_device_attribute r8a7795es1[] = {
6183 { .soc_id = "r8a7795", .revision = "ES1.*" },
6184 { /* sentinel */ }
6185};
6186
6187static int r8a7795_pinmux_init(struct sh_pfc *pfc)
6188{
6189 if (soc_device_match(r8a7795es1))
6190 pfc->info = &r8a7795es1_pinmux_info;
6191
6192 return 0;
6193}
6194
e9eace32 6195static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
b205914c 6196 .init = r8a7795_pinmux_init,
e9eace32 6197 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
56065524
UH		 6198 .get_bias = r8a7795_pinmux_get_bias,
6199 .set_bias = r8a7795_pinmux_set_bias,
e9eace32
WS		 6200};
6201
0b0ffc96 6202const struct sh_pfc_soc_info r8a7795_pinmux_info = {
b205914c 6203 .name = "r8a77951_pfc",
e9eace32 6204 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 6205 .unlock_reg = 0xe6060000, /* PMMR */
6206
6207 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6208
6209 .pins = pinmux_pins,
6210 .nr_pins = ARRAY_SIZE(pinmux_pins),
6211 .groups = pinmux_groups,
6212 .nr_groups = ARRAY_SIZE(pinmux_groups),
6213 .functions = pinmux_functions,
6214 .nr_functions = ARRAY_SIZE(pinmux_functions),
6215
6216 .cfg_regs = pinmux_config_regs,
92e6d9a2 6217 .drive_regs = pinmux_drive_regs,
6f4b74f3 6218 .bias_regs = pinmux_bias_regs,
e2aad846 6219 .ioctrl_regs = pinmux_ioctrl_regs,
0b0ffc96 6220
b8b47d67
GU		 6221 .pinmux_data = pinmux_data,
6222 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 6223};
Linux 6.x block layer and io_uring tree(s)