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ACPI / debugger: Fix regression introduced by IS_ERR_VALUE() removal
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-rockchip.c
CommitLineData
d3e51161
HS		 1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
7e865abb 39#include <linux/clk.h>
751a99ab 40#include <linux/regmap.h>
14dee867 41#include <linux/mfd/syscon.h>
d3e51161
HS		 42#include <dt-bindings/pinctrl/rockchip.h>
43
44#include "core.h"
45#include "pinconf.h"
46
47/* GPIO control registers */
48#define GPIO_SWPORT_DR 0x00
49#define GPIO_SWPORT_DDR 0x04
50#define GPIO_INTEN 0x30
51#define GPIO_INTMASK 0x34
52#define GPIO_INTTYPE_LEVEL 0x38
53#define GPIO_INT_POLARITY 0x3c
54#define GPIO_INT_STATUS 0x40
55#define GPIO_INT_RAWSTATUS 0x44
56#define GPIO_DEBOUNCE 0x48
57#define GPIO_PORTS_EOI 0x4c
58#define GPIO_EXT_PORT 0x50
59#define GPIO_LS_SYNC 0x60
60
a282926d
HS		 61enum rockchip_pinctrl_type {
62 RK2928,
63 RK3066B,
64 RK3188,
66d750e1 65 RK3288,
daecdc66 66 RK3368,
b6c23275 67 RK3399,
a282926d
HS		 68};
69
fc72c923
HS		 70/**
71 * Encode variants of iomux registers into a type variable
72 */
73#define IOMUX_GPIO_ONLY BIT(0)
03716e1d 74#define IOMUX_WIDTH_4BIT BIT(1)
95ec8ae4 75#define IOMUX_SOURCE_PMU BIT(2)
62f49226 76#define IOMUX_UNROUTED BIT(3)
fc72c923
HS		 77
78/**
79 * @type: iomux variant using IOMUX_* constants
6bc0d121
HS		 80 * @offset: if initialized to -1 it will be autocalculated, by specifying
81 * an initial offset value the relevant source offset can be reset
82 * to a new value for autocalculating the following iomux registers.
fc72c923
HS		 83 */
84struct rockchip_iomux {
85 int type;
6bc0d121 86 int offset;
65fca613
HS		 87};
88
b6c23275
DW		 89/**
90 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
91 */
92enum rockchip_pin_drv_type {
93 DRV_TYPE_IO_DEFAULT = 0,
94 DRV_TYPE_IO_1V8_OR_3V0,
95 DRV_TYPE_IO_1V8_ONLY,
96 DRV_TYPE_IO_1V8_3V0_AUTO,
97 DRV_TYPE_IO_3V3_ONLY,
98 DRV_TYPE_MAX
99};
100
3ba6767a
DW		 101/**
102 * enum type index corresponding to rockchip_pull_list arrays index.
103 */
104enum rockchip_pin_pull_type {
105 PULL_TYPE_IO_DEFAULT = 0,
106 PULL_TYPE_IO_1V8_ONLY,
107 PULL_TYPE_MAX
108};
109
b6c23275
DW		 110/**
111 * @drv_type: drive strength variant using rockchip_perpin_drv_type
112 * @offset: if initialized to -1 it will be autocalculated, by specifying
113 * an initial offset value the relevant source offset can be reset
114 * to a new value for autocalculating the following drive strength
115 * registers. if used chips own cal_drv func instead to calculate
116 * registers offset, the variant could be ignored.
117 */
118struct rockchip_drv {
119 enum rockchip_pin_drv_type drv_type;
120 int offset;
121};
122
d3e51161
HS		 123/**
124 * @reg_base: register base of the gpio bank
6ca5274d 125 * @reg_pull: optional separate register for additional pull settings
d3e51161
HS		 126 * @clk: clock of the gpio bank
127 * @irq: interrupt of the gpio bank
5ae0c7ad 128 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
d3e51161
HS		 129 * @pin_base: first pin number
130 * @nr_pins: number of pins in this bank
131 * @name: name of the bank
132 * @bank_num: number of the bank, to account for holes
fc72c923 133 * @iomux: array describing the 4 iomux sources of the bank
b6c23275 134 * @drv: array describing the 4 drive strength sources of the bank
3ba6767a 135 * @pull_type: array describing the 4 pull type sources of the bank
d3e51161
HS		 136 * @valid: are all necessary informations present
137 * @of_node: dt node of this bank
138 * @drvdata: common pinctrl basedata
139 * @domain: irqdomain of the gpio bank
140 * @gpio_chip: gpiolib chip
141 * @grange: gpio range
142 * @slock: spinlock for the gpio bank
143 */
144struct rockchip_pin_bank {
145 void __iomem *reg_base;
751a99ab 146 struct regmap *regmap_pull;
d3e51161
HS		 147 struct clk *clk;
148 int irq;
5ae0c7ad 149 u32 saved_masks;
d3e51161
HS		 150 u32 pin_base;
151 u8 nr_pins;
152 char *name;
153 u8 bank_num;
fc72c923 154 struct rockchip_iomux iomux[4];
b6c23275 155 struct rockchip_drv drv[4];
3ba6767a 156 enum rockchip_pin_pull_type pull_type[4];
d3e51161
HS		 157 bool valid;
158 struct device_node *of_node;
159 struct rockchip_pinctrl *drvdata;
160 struct irq_domain *domain;
161 struct gpio_chip gpio_chip;
162 struct pinctrl_gpio_range grange;
163 spinlock_t slock;
5a927501 164 u32 toggle_edge_mode;
d3e51161
HS		 165};
166
167#define PIN_BANK(id, pins, label) \
168 { \
169 .bank_num = id, \
170 .nr_pins = pins, \
171 .name = label, \
6bc0d121
HS		 172 .iomux = { \
173 { .offset = -1 }, \
174 { .offset = -1 }, \
175 { .offset = -1 }, \
176 { .offset = -1 }, \
177 }, \
d3e51161
HS		 178 }
179
fc72c923
HS		 180#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
181 { \
182 .bank_num = id, \
183 .nr_pins = pins, \
184 .name = label, \
185 .iomux = { \
6bc0d121
HS		 186 { .type = iom0, .offset = -1 }, \
187 { .type = iom1, .offset = -1 }, \
188 { .type = iom2, .offset = -1 }, \
189 { .type = iom3, .offset = -1 }, \
fc72c923
HS		 190 }, \
191 }
192
b6c23275
DW		 193#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
194 { \
195 .bank_num = id, \
196 .nr_pins = pins, \
197 .name = label, \
198 .iomux = { \
199 { .offset = -1 }, \
200 { .offset = -1 }, \
201 { .offset = -1 }, \
202 { .offset = -1 }, \
203 }, \
204 .drv = { \
205 { .drv_type = type0, .offset = -1 }, \
206 { .drv_type = type1, .offset = -1 }, \
207 { .drv_type = type2, .offset = -1 }, \
208 { .drv_type = type3, .offset = -1 }, \
209 }, \
210 }
211
3ba6767a
DW		 212#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
213 drv2, drv3, pull0, pull1, \
214 pull2, pull3) \
215 { \
216 .bank_num = id, \
217 .nr_pins = pins, \
218 .name = label, \
219 .iomux = { \
220 { .offset = -1 }, \
221 { .offset = -1 }, \
222 { .offset = -1 }, \
223 { .offset = -1 }, \
224 }, \
225 .drv = { \
226 { .drv_type = drv0, .offset = -1 }, \
227 { .drv_type = drv1, .offset = -1 }, \
228 { .drv_type = drv2, .offset = -1 }, \
229 { .drv_type = drv3, .offset = -1 }, \
230 }, \
231 .pull_type[0] = pull0, \
232 .pull_type[1] = pull1, \
233 .pull_type[2] = pull2, \
234 .pull_type[3] = pull3, \
235 }
236
b6c23275
DW		 237#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
238 iom2, iom3, drv0, drv1, drv2, \
239 drv3, offset0, offset1, \
240 offset2, offset3) \
241 { \
242 .bank_num = id, \
243 .nr_pins = pins, \
244 .name = label, \
245 .iomux = { \
246 { .type = iom0, .offset = -1 }, \
247 { .type = iom1, .offset = -1 }, \
248 { .type = iom2, .offset = -1 }, \
249 { .type = iom3, .offset = -1 }, \
250 }, \
251 .drv = { \
252 { .drv_type = drv0, .offset = offset0 }, \
253 { .drv_type = drv1, .offset = offset1 }, \
254 { .drv_type = drv2, .offset = offset2 }, \
255 { .drv_type = drv3, .offset = offset3 }, \
256 }, \
257 }
258
3ba6767a
DW		 259#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
260 label, iom0, iom1, iom2, \
261 iom3, drv0, drv1, drv2, \
262 drv3, offset0, offset1, \
263 offset2, offset3, pull0, \
264 pull1, pull2, pull3) \
265 { \
266 .bank_num = id, \
267 .nr_pins = pins, \
268 .name = label, \
269 .iomux = { \
270 { .type = iom0, .offset = -1 }, \
271 { .type = iom1, .offset = -1 }, \
272 { .type = iom2, .offset = -1 }, \
273 { .type = iom3, .offset = -1 }, \
274 }, \
275 .drv = { \
276 { .drv_type = drv0, .offset = offset0 }, \
277 { .drv_type = drv1, .offset = offset1 }, \
278 { .drv_type = drv2, .offset = offset2 }, \
279 { .drv_type = drv3, .offset = offset3 }, \
280 }, \
281 .pull_type[0] = pull0, \
282 .pull_type[1] = pull1, \
283 .pull_type[2] = pull2, \
284 .pull_type[3] = pull3, \
285 }
286
d3e51161 287/**
d3e51161
HS		 288 */
289struct rockchip_pin_ctrl {
290 struct rockchip_pin_bank *pin_banks;
291 u32 nr_banks;
292 u32 nr_pins;
293 char *label;
a282926d 294 enum rockchip_pinctrl_type type;
95ec8ae4
HS		 295 int grf_mux_offset;
296 int pmu_mux_offset;
b6c23275
DW		 297 int grf_drv_offset;
298 int pmu_drv_offset;
299
751a99ab
HS		 300 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
301 int pin_num, struct regmap **regmap,
302 int *reg, u8 *bit);
ef17f69f
HS		 303 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
304 int pin_num, struct regmap **regmap,
305 int *reg, u8 *bit);
d3e51161
HS		 306};
307
308struct rockchip_pin_config {
309 unsigned int func;
310 unsigned long *configs;
311 unsigned int nconfigs;
312};
313
314/**
315 * struct rockchip_pin_group: represent group of pins of a pinmux function.
316 * @name: name of the pin group, used to lookup the group.
317 * @pins: the pins included in this group.
318 * @npins: number of pins included in this group.
319 * @func: the mux function number to be programmed when selected.
320 * @configs: the config values to be set for each pin
321 * @nconfigs: number of configs for each pin
322 */
323struct rockchip_pin_group {
324 const char *name;
325 unsigned int npins;
326 unsigned int *pins;
327 struct rockchip_pin_config *data;
328};
329
330/**
331 * struct rockchip_pmx_func: represent a pin function.
332 * @name: name of the pin function, used to lookup the function.
333 * @groups: one or more names of pin groups that provide this function.
334 * @num_groups: number of groups included in @groups.
335 */
336struct rockchip_pmx_func {
337 const char *name;
338 const char **groups;
339 u8 ngroups;
340};
341
342struct rockchip_pinctrl {
751a99ab 343 struct regmap *regmap_base;
bfc7a42a 344 int reg_size;
751a99ab 345 struct regmap *regmap_pull;
14dee867 346 struct regmap *regmap_pmu;
d3e51161
HS		 347 struct device *dev;
348 struct rockchip_pin_ctrl *ctrl;
349 struct pinctrl_desc pctl;
350 struct pinctrl_dev *pctl_dev;
351 struct rockchip_pin_group *groups;
352 unsigned int ngroups;
353 struct rockchip_pmx_func *functions;
354 unsigned int nfunctions;
355};
356
751a99ab
HS		 357static struct regmap_config rockchip_regmap_config = {
358 .reg_bits = 32,
359 .val_bits = 32,
360 .reg_stride = 4,
361};
362
d3e51161
HS		 363static const inline struct rockchip_pin_group *pinctrl_name_to_group(
364 const struct rockchip_pinctrl *info,
365 const char *name)
366{
d3e51161
HS		 367 int i;
368
369 for (i = 0; i < info->ngroups; i++) {
1cb95395
AL		 370 if (!strcmp(info->groups[i].name, name))
371 return &info->groups[i];
d3e51161
HS		 372 }
373
1cb95395 374 return NULL;
d3e51161
HS		 375}
376
377/*
378 * given a pin number that is local to a pin controller, find out the pin bank
379 * and the register base of the pin bank.
380 */
381static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
382 unsigned pin)
383{
384 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
385
51578b9b 386 while (pin >= (b->pin_base + b->nr_pins))
d3e51161
HS		 387 b++;
388
389 return b;
390}
391
392static struct rockchip_pin_bank *bank_num_to_bank(
393 struct rockchip_pinctrl *info,
394 unsigned num)
395{
396 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
397 int i;
398
1cb95395 399 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
d3e51161 400 if (b->bank_num == num)
1cb95395 401 return b;
d3e51161
HS		 402 }
403
1cb95395 404 return ERR_PTR(-EINVAL);
d3e51161
HS		 405}
406
407/*
408 * Pinctrl_ops handling
409 */
410
411static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
412{
413 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
414
415 return info->ngroups;
416}
417
418static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
419 unsigned selector)
420{
421 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
422
423 return info->groups[selector].name;
424}
425
426static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
427 unsigned selector, const unsigned **pins,
428 unsigned *npins)
429{
430 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
431
432 if (selector >= info->ngroups)
433 return -EINVAL;
434
435 *pins = info->groups[selector].pins;
436 *npins = info->groups[selector].npins;
437
438 return 0;
439}
440
441static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
442 struct device_node *np,
443 struct pinctrl_map **map, unsigned *num_maps)
444{
445 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
446 const struct rockchip_pin_group *grp;
447 struct pinctrl_map *new_map;
448 struct device_node *parent;
449 int map_num = 1;
450 int i;
451
452 /*
453 * first find the group of this node and check if we need to create
454 * config maps for pins
455 */
456 grp = pinctrl_name_to_group(info, np->name);
457 if (!grp) {
458 dev_err(info->dev, "unable to find group for node %s\n",
459 np->name);
460 return -EINVAL;
461 }
462
463 map_num += grp->npins;
464 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
465 GFP_KERNEL);
466 if (!new_map)
467 return -ENOMEM;
468
469 *map = new_map;
470 *num_maps = map_num;
471
472 /* create mux map */
473 parent = of_get_parent(np);
474 if (!parent) {
475 devm_kfree(pctldev->dev, new_map);
476 return -EINVAL;
477 }
478 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
479 new_map[0].data.mux.function = parent->name;
480 new_map[0].data.mux.group = np->name;
481 of_node_put(parent);
482
483 /* create config map */
484 new_map++;
485 for (i = 0; i < grp->npins; i++) {
486 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
487 new_map[i].data.configs.group_or_pin =
488 pin_get_name(pctldev, grp->pins[i]);
489 new_map[i].data.configs.configs = grp->data[i].configs;
490 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
491 }
492
493 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
494 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
495
496 return 0;
497}
498
499static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
500 struct pinctrl_map *map, unsigned num_maps)
501{
502}
503
504static const struct pinctrl_ops rockchip_pctrl_ops = {
505 .get_groups_count = rockchip_get_groups_count,
506 .get_group_name = rockchip_get_group_name,
507 .get_group_pins = rockchip_get_group_pins,
508 .dt_node_to_map = rockchip_dt_node_to_map,
509 .dt_free_map = rockchip_dt_free_map,
510};
511
512/*
513 * Hardware access
514 */
515
a076e2ed
HS		 516static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
517{
518 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 519 int iomux_num = (pin / 8);
95ec8ae4 520 struct regmap *regmap;
751a99ab 521 unsigned int val;
03716e1d 522 int reg, ret, mask;
a076e2ed
HS		 523 u8 bit;
524
fc72c923
HS		 525 if (iomux_num > 3)
526 return -EINVAL;
527
62f49226
HS		 528 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
529 dev_err(info->dev, "pin %d is unrouted\n", pin);
530 return -EINVAL;
531 }
532
fc72c923 533 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
a076e2ed
HS		 534 return RK_FUNC_GPIO;
535
95ec8ae4
HS		 536 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
537 ? info->regmap_pmu : info->regmap_base;
538
a076e2ed 539 /* get basic quadrupel of mux registers and the correct reg inside */
03716e1d 540 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
6bc0d121 541 reg = bank->iomux[iomux_num].offset;
03716e1d
HS		 542 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
543 if ((pin % 8) >= 4)
544 reg += 0x4;
545 bit = (pin % 4) * 4;
546 } else {
547 bit = (pin % 8) * 2;
548 }
a076e2ed 549
95ec8ae4 550 ret = regmap_read(regmap, reg, &val);
751a99ab
HS		 551 if (ret)
552 return ret;
553
03716e1d 554 return ((val >> bit) & mask);
a076e2ed
HS		 555}
556
d3e51161
HS		 557/*
558 * Set a new mux function for a pin.
559 *
560 * The register is divided into the upper and lower 16 bit. When changing
561 * a value, the previous register value is not read and changed. Instead
562 * it seems the changed bits are marked in the upper 16 bit, while the
563 * changed value gets set in the same offset in the lower 16 bit.
564 * All pin settings seem to be 2 bit wide in both the upper and lower
565 * parts.
566 * @bank: pin bank to change
567 * @pin: pin to change
568 * @mux: new mux function to set
569 */
14797189 570static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
d3e51161
HS		 571{
572 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 573 int iomux_num = (pin / 8);
95ec8ae4 574 struct regmap *regmap;
03716e1d 575 int reg, ret, mask;
d3e51161
HS		 576 unsigned long flags;
577 u8 bit;
99e872d9 578 u32 data, rmask;
d3e51161 579
fc72c923
HS		 580 if (iomux_num > 3)
581 return -EINVAL;
582
62f49226
HS		 583 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
584 dev_err(info->dev, "pin %d is unrouted\n", pin);
585 return -EINVAL;
586 }
587
fc72c923 588 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
c4a532de
HS		 589 if (mux != RK_FUNC_GPIO) {
590 dev_err(info->dev,
591 "pin %d only supports a gpio mux\n", pin);
592 return -ENOTSUPP;
593 } else {
594 return 0;
595 }
596 }
597
d3e51161
HS		 598 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
599 bank->bank_num, pin, mux);
600
95ec8ae4
HS		 601 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
602 ? info->regmap_pmu : info->regmap_base;
603
d3e51161 604 /* get basic quadrupel of mux registers and the correct reg inside */
03716e1d 605 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
6bc0d121 606 reg = bank->iomux[iomux_num].offset;
03716e1d
HS		 607 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
608 if ((pin % 8) >= 4)
609 reg += 0x4;
610 bit = (pin % 4) * 4;
611 } else {
612 bit = (pin % 8) * 2;
613 }
d3e51161
HS		 614
615 spin_lock_irqsave(&bank->slock, flags);
616
03716e1d 617 data = (mask << (bit + 16));
99e872d9 618 rmask = data | (data >> 16);
03716e1d 619 data |= (mux & mask) << bit;
99e872d9 620 ret = regmap_update_bits(regmap, reg, rmask, data);
d3e51161
HS		 621
622 spin_unlock_irqrestore(&bank->slock, flags);
14797189 623
751a99ab 624 return ret;
d3e51161
HS		 625}
626
a282926d
HS		 627#define RK2928_PULL_OFFSET 0x118
628#define RK2928_PULL_PINS_PER_REG 16
629#define RK2928_PULL_BANK_STRIDE 8
630
631static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 632 int pin_num, struct regmap **regmap,
633 int *reg, u8 *bit)
a282926d
HS		 634{
635 struct rockchip_pinctrl *info = bank->drvdata;
636
751a99ab
HS		 637 *regmap = info->regmap_base;
638 *reg = RK2928_PULL_OFFSET;
a282926d
HS		 639 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
640 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
641
642 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
643};
644
bfc7a42a 645#define RK3188_PULL_OFFSET 0x164
6ca5274d
HS		 646#define RK3188_PULL_BITS_PER_PIN 2
647#define RK3188_PULL_PINS_PER_REG 8
648#define RK3188_PULL_BANK_STRIDE 16
14dee867 649#define RK3188_PULL_PMU_OFFSET 0x64
6ca5274d
HS		 650
651static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 652 int pin_num, struct regmap **regmap,
653 int *reg, u8 *bit)
6ca5274d
HS		 654{
655 struct rockchip_pinctrl *info = bank->drvdata;
656
657 /* The first 12 pins of the first bank are located elsewhere */
fc72c923 658 if (bank->bank_num == 0 && pin_num < 12) {
14dee867
HS		 659 *regmap = info->regmap_pmu ? info->regmap_pmu
660 : bank->regmap_pull;
661 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
751a99ab 662 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
6ca5274d
HS		 663 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
664 *bit *= RK3188_PULL_BITS_PER_PIN;
665 } else {
751a99ab
HS		 666 *regmap = info->regmap_pull ? info->regmap_pull
667 : info->regmap_base;
668 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
669
bfc7a42a
HS		 670 /* correct the offset, as it is the 2nd pull register */
671 *reg -= 4;
6ca5274d
HS		 672 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
673 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
674
675 /*
676 * The bits in these registers have an inverse ordering
677 * with the lowest pin being in bits 15:14 and the highest
678 * pin in bits 1:0
679 */
680 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
681 *bit *= RK3188_PULL_BITS_PER_PIN;
682 }
683}
684
304f077d
HS		 685#define RK3288_PULL_OFFSET 0x140
686static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
687 int pin_num, struct regmap **regmap,
688 int *reg, u8 *bit)
689{
690 struct rockchip_pinctrl *info = bank->drvdata;
691
692 /* The first 24 pins of the first bank are located in PMU */
693 if (bank->bank_num == 0) {
694 *regmap = info->regmap_pmu;
695 *reg = RK3188_PULL_PMU_OFFSET;
696
697 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
698 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
699 *bit *= RK3188_PULL_BITS_PER_PIN;
700 } else {
701 *regmap = info->regmap_base;
702 *reg = RK3288_PULL_OFFSET;
703
704 /* correct the offset, as we're starting with the 2nd bank */
705 *reg -= 0x10;
706 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
707 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
708
709 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
710 *bit *= RK3188_PULL_BITS_PER_PIN;
711 }
712}
713
b547c800
HS		 714#define RK3288_DRV_PMU_OFFSET 0x70
715#define RK3288_DRV_GRF_OFFSET 0x1c0
716#define RK3288_DRV_BITS_PER_PIN 2
717#define RK3288_DRV_PINS_PER_REG 8
718#define RK3288_DRV_BANK_STRIDE 16
b547c800
HS		 719
720static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
721 int pin_num, struct regmap **regmap,
722 int *reg, u8 *bit)
723{
724 struct rockchip_pinctrl *info = bank->drvdata;
725
726 /* The first 24 pins of the first bank are located in PMU */
727 if (bank->bank_num == 0) {
728 *regmap = info->regmap_pmu;
729 *reg = RK3288_DRV_PMU_OFFSET;
730
731 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
732 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
733 *bit *= RK3288_DRV_BITS_PER_PIN;
734 } else {
735 *regmap = info->regmap_base;
736 *reg = RK3288_DRV_GRF_OFFSET;
737
738 /* correct the offset, as we're starting with the 2nd bank */
739 *reg -= 0x10;
740 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
741 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
742
743 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
744 *bit *= RK3288_DRV_BITS_PER_PIN;
745 }
746}
747
fea0fe60
JC		 748#define RK3228_PULL_OFFSET 0x100
749
750static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751 int pin_num, struct regmap **regmap,
752 int *reg, u8 *bit)
753{
754 struct rockchip_pinctrl *info = bank->drvdata;
755
756 *regmap = info->regmap_base;
757 *reg = RK3228_PULL_OFFSET;
758 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
759 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
760
761 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
762 *bit *= RK3188_PULL_BITS_PER_PIN;
763}
764
765#define RK3228_DRV_GRF_OFFSET 0x200
766
767static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
768 int pin_num, struct regmap **regmap,
769 int *reg, u8 *bit)
770{
771 struct rockchip_pinctrl *info = bank->drvdata;
772
773 *regmap = info->regmap_base;
774 *reg = RK3228_DRV_GRF_OFFSET;
775 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
776 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
777
778 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
779 *bit *= RK3288_DRV_BITS_PER_PIN;
780}
781
daecdc66
HS		 782#define RK3368_PULL_GRF_OFFSET 0x100
783#define RK3368_PULL_PMU_OFFSET 0x10
784
785static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
786 int pin_num, struct regmap **regmap,
787 int *reg, u8 *bit)
788{
789 struct rockchip_pinctrl *info = bank->drvdata;
790
791 /* The first 32 pins of the first bank are located in PMU */
792 if (bank->bank_num == 0) {
793 *regmap = info->regmap_pmu;
794 *reg = RK3368_PULL_PMU_OFFSET;
795
796 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
797 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
798 *bit *= RK3188_PULL_BITS_PER_PIN;
799 } else {
800 *regmap = info->regmap_base;
801 *reg = RK3368_PULL_GRF_OFFSET;
802
803 /* correct the offset, as we're starting with the 2nd bank */
804 *reg -= 0x10;
805 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
806 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
807
808 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
809 *bit *= RK3188_PULL_BITS_PER_PIN;
810 }
811}
812
813#define RK3368_DRV_PMU_OFFSET 0x20
814#define RK3368_DRV_GRF_OFFSET 0x200
815
816static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
817 int pin_num, struct regmap **regmap,
818 int *reg, u8 *bit)
819{
820 struct rockchip_pinctrl *info = bank->drvdata;
821
822 /* The first 32 pins of the first bank are located in PMU */
823 if (bank->bank_num == 0) {
824 *regmap = info->regmap_pmu;
825 *reg = RK3368_DRV_PMU_OFFSET;
826
827 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
828 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
829 *bit *= RK3288_DRV_BITS_PER_PIN;
830 } else {
831 *regmap = info->regmap_base;
832 *reg = RK3368_DRV_GRF_OFFSET;
833
834 /* correct the offset, as we're starting with the 2nd bank */
835 *reg -= 0x10;
836 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
837 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
838
839 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
840 *bit *= RK3288_DRV_BITS_PER_PIN;
841 }
842}
843
b6c23275
DW		 844#define RK3399_PULL_GRF_OFFSET 0xe040
845#define RK3399_PULL_PMU_OFFSET 0x40
846#define RK3399_DRV_3BITS_PER_PIN 3
847
848static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
849 int pin_num, struct regmap **regmap,
850 int *reg, u8 *bit)
851{
852 struct rockchip_pinctrl *info = bank->drvdata;
853
854 /* The bank0:16 and bank1:32 pins are located in PMU */
855 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
856 *regmap = info->regmap_pmu;
857 *reg = RK3399_PULL_PMU_OFFSET;
858
859 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
860
861 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
862 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
863 *bit *= RK3188_PULL_BITS_PER_PIN;
864 } else {
865 *regmap = info->regmap_base;
866 *reg = RK3399_PULL_GRF_OFFSET;
867
868 /* correct the offset, as we're starting with the 3rd bank */
869 *reg -= 0x20;
870 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
871 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
872
873 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
874 *bit *= RK3188_PULL_BITS_PER_PIN;
875 }
876}
877
878static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
879 int pin_num, struct regmap **regmap,
880 int *reg, u8 *bit)
881{
882 struct rockchip_pinctrl *info = bank->drvdata;
883 int drv_num = (pin_num / 8);
884
885 /* The bank0:16 and bank1:32 pins are located in PMU */
886 if ((bank->bank_num == 0) || (bank->bank_num == 1))
887 *regmap = info->regmap_pmu;
888 else
889 *regmap = info->regmap_base;
890
891 *reg = bank->drv[drv_num].offset;
892 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
893 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
894 *bit = (pin_num % 8) * 3;
895 else
896 *bit = (pin_num % 8) * 2;
897}
898
899static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
900 { 2, 4, 8, 12, -1, -1, -1, -1 },
901 { 3, 6, 9, 12, -1, -1, -1, -1 },
902 { 5, 10, 15, 20, -1, -1, -1, -1 },
903 { 4, 6, 8, 10, 12, 14, 16, 18 },
904 { 4, 7, 10, 13, 16, 19, 22, 26 }
905};
ef17f69f
HS		 906
907static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
908 int pin_num)
b547c800 909{
ef17f69f
HS		 910 struct rockchip_pinctrl *info = bank->drvdata;
911 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 912 struct regmap *regmap;
913 int reg, ret;
b6c23275 914 u32 data, temp, rmask_bits;
b547c800 915 u8 bit;
b6c23275 916 int drv_type = bank->drv[pin_num / 8].drv_type;
b547c800 917
ef17f69f 918 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800 919
b6c23275
DW		 920 switch (drv_type) {
921 case DRV_TYPE_IO_1V8_3V0_AUTO:
922 case DRV_TYPE_IO_3V3_ONLY:
923 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
924 switch (bit) {
925 case 0 ... 12:
926 /* regular case, nothing to do */
927 break;
928 case 15:
929 /*
930 * drive-strength offset is special, as it is
931 * spread over 2 registers
932 */
933 ret = regmap_read(regmap, reg, &data);
934 if (ret)
935 return ret;
936
937 ret = regmap_read(regmap, reg + 0x4, &temp);
938 if (ret)
939 return ret;
940
941 /*
942 * the bit data[15] contains bit 0 of the value
943 * while temp[1:0] contains bits 2 and 1
944 */
945 data >>= 15;
946 temp &= 0x3;
947 temp <<= 1;
948 data |= temp;
949
950 return rockchip_perpin_drv_list[drv_type][data];
951 case 18 ... 21:
952 /* setting fully enclosed in the second register */
953 reg += 4;
954 bit -= 16;
955 break;
956 default:
957 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
958 bit, drv_type);
959 return -EINVAL;
960 }
961
962 break;
963 case DRV_TYPE_IO_DEFAULT:
964 case DRV_TYPE_IO_1V8_OR_3V0:
965 case DRV_TYPE_IO_1V8_ONLY:
966 rmask_bits = RK3288_DRV_BITS_PER_PIN;
967 break;
968 default:
969 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
970 drv_type);
971 return -EINVAL;
972 }
973
b547c800
HS		 974 ret = regmap_read(regmap, reg, &data);
975 if (ret)
976 return ret;
977
978 data >>= bit;
b6c23275 979 data &= (1 << rmask_bits) - 1;
b547c800 980
b6c23275 981 return rockchip_perpin_drv_list[drv_type][data];
b547c800
HS		 982}
983
ef17f69f
HS		 984static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
985 int pin_num, int strength)
b547c800
HS		 986{
987 struct rockchip_pinctrl *info = bank->drvdata;
ef17f69f 988 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 989 struct regmap *regmap;
990 unsigned long flags;
991 int reg, ret, i;
b6c23275 992 u32 data, rmask, rmask_bits, temp;
b547c800 993 u8 bit;
b6c23275
DW		 994 int drv_type = bank->drv[pin_num / 8].drv_type;
995
996 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
997 bank->bank_num, pin_num, strength);
b547c800 998
ef17f69f 999 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800
HS		 1000
1001 ret = -EINVAL;
b6c23275
DW		 1002 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1003 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
b547c800
HS		 1004 ret = i;
1005 break;
b6c23275
DW		 1006 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1007 ret = rockchip_perpin_drv_list[drv_type][i];
1008 break;
b547c800
HS		 1009 }
1010 }
1011
1012 if (ret < 0) {
1013 dev_err(info->dev, "unsupported driver strength %d\n",
1014 strength);
1015 return ret;
1016 }
1017
1018 spin_lock_irqsave(&bank->slock, flags);
1019
b6c23275
DW		 1020 switch (drv_type) {
1021 case DRV_TYPE_IO_1V8_3V0_AUTO:
1022 case DRV_TYPE_IO_3V3_ONLY:
1023 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1024 switch (bit) {
1025 case 0 ... 12:
1026 /* regular case, nothing to do */
1027 break;
1028 case 15:
1029 /*
1030 * drive-strength offset is special, as it is spread
1031 * over 2 registers, the bit data[15] contains bit 0
1032 * of the value while temp[1:0] contains bits 2 and 1
1033 */
1034 data = (ret & 0x1) << 15;
1035 temp = (ret >> 0x1) & 0x3;
1036
1037 rmask = BIT(15) | BIT(31);
1038 data |= BIT(31);
1039 ret = regmap_update_bits(regmap, reg, rmask, data);
1040 if (ret) {
1041 spin_unlock_irqrestore(&bank->slock, flags);
1042 return ret;
1043 }
1044
1045 rmask = 0x3 | (0x3 << 16);
1046 temp |= (0x3 << 16);
1047 reg += 0x4;
1048 ret = regmap_update_bits(regmap, reg, rmask, temp);
1049
1050 spin_unlock_irqrestore(&bank->slock, flags);
1051 return ret;
1052 case 18 ... 21:
1053 /* setting fully enclosed in the second register */
1054 reg += 4;
1055 bit -= 16;
1056 break;
1057 default:
1058 spin_unlock_irqrestore(&bank->slock, flags);
1059 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1060 bit, drv_type);
1061 return -EINVAL;
1062 }
1063 break;
1064 case DRV_TYPE_IO_DEFAULT:
1065 case DRV_TYPE_IO_1V8_OR_3V0:
1066 case DRV_TYPE_IO_1V8_ONLY:
1067 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1068 break;
1069 default:
1070 spin_unlock_irqrestore(&bank->slock, flags);
1071 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1072 drv_type);
1073 return -EINVAL;
1074 }
1075
b547c800 1076 /* enable the write to the equivalent lower bits */
b6c23275 1077 data = ((1 << rmask_bits) - 1) << (bit + 16);
99e872d9 1078 rmask = data | (data >> 16);
b547c800
HS		 1079 data |= (ret << bit);
1080
99e872d9 1081 ret = regmap_update_bits(regmap, reg, rmask, data);
b547c800
HS		 1082 spin_unlock_irqrestore(&bank->slock, flags);
1083
1084 return ret;
1085}
1086
3ba6767a
DW		 1087static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1088 {
1089 PIN_CONFIG_BIAS_DISABLE,
1090 PIN_CONFIG_BIAS_PULL_UP,
1091 PIN_CONFIG_BIAS_PULL_DOWN,
1092 PIN_CONFIG_BIAS_BUS_HOLD
1093 },
1094 {
1095 PIN_CONFIG_BIAS_DISABLE,
1096 PIN_CONFIG_BIAS_PULL_DOWN,
1097 PIN_CONFIG_BIAS_DISABLE,
1098 PIN_CONFIG_BIAS_PULL_UP
1099 },
1100};
1101
d3e51161
HS		 1102static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1103{
1104 struct rockchip_pinctrl *info = bank->drvdata;
1105 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab 1106 struct regmap *regmap;
3ba6767a 1107 int reg, ret, pull_type;
d3e51161 1108 u8 bit;
6ca5274d 1109 u32 data;
d3e51161
HS		 1110
1111 /* rk3066b does support any pulls */
a282926d 1112 if (ctrl->type == RK3066B)
d3e51161
HS		 1113 return PIN_CONFIG_BIAS_DISABLE;
1114
751a99ab
HS		 1115 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1116
1117 ret = regmap_read(regmap, reg, &data);
1118 if (ret)
1119 return ret;
6ca5274d 1120
a282926d
HS		 1121 switch (ctrl->type) {
1122 case RK2928:
751a99ab 1123 return !(data & BIT(bit))
d3e51161
HS		 1124 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1125 : PIN_CONFIG_BIAS_DISABLE;
a282926d 1126 case RK3188:
66d750e1 1127 case RK3288:
daecdc66 1128 case RK3368:
b6c23275 1129 case RK3399:
3ba6767a 1130 pull_type = bank->pull_type[pin_num / 8];
751a99ab 1131 data >>= bit;
6ca5274d
HS		 1132 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1133
3ba6767a 1134 return rockchip_pull_list[pull_type][data];
a282926d
HS		 1135 default:
1136 dev_err(info->dev, "unsupported pinctrl type\n");
1137 return -EINVAL;
1138 };
d3e51161
HS		 1139}
1140
1141static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1142 int pin_num, int pull)
1143{
1144 struct rockchip_pinctrl *info = bank->drvdata;
1145 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab 1146 struct regmap *regmap;
3ba6767a 1147 int reg, ret, i, pull_type;
d3e51161
HS		 1148 unsigned long flags;
1149 u8 bit;
99e872d9 1150 u32 data, rmask;
d3e51161
HS		 1151
1152 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1153 bank->bank_num, pin_num, pull);
1154
1155 /* rk3066b does support any pulls */
a282926d 1156 if (ctrl->type == RK3066B)
d3e51161
HS		 1157 return pull ? -EINVAL : 0;
1158
751a99ab 1159 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
6ca5274d 1160
a282926d
HS		 1161 switch (ctrl->type) {
1162 case RK2928:
d3e51161
HS		 1163 spin_lock_irqsave(&bank->slock, flags);
1164
1165 data = BIT(bit + 16);
1166 if (pull == PIN_CONFIG_BIAS_DISABLE)
1167 data |= BIT(bit);
751a99ab 1168 ret = regmap_write(regmap, reg, data);
d3e51161
HS		 1169
1170 spin_unlock_irqrestore(&bank->slock, flags);
a282926d
HS		 1171 break;
1172 case RK3188:
66d750e1 1173 case RK3288:
daecdc66 1174 case RK3368:
b6c23275 1175 case RK3399:
3ba6767a
DW		 1176 pull_type = bank->pull_type[pin_num / 8];
1177 ret = -EINVAL;
1178 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1179 i++) {
1180 if (rockchip_pull_list[pull_type][i] == pull) {
1181 ret = i;
1182 break;
1183 }
1184 }
1185
1186 if (ret < 0) {
1187 dev_err(info->dev, "unsupported pull setting %d\n",
1188 pull);
1189 return ret;
1190 }
1191
6ca5274d
HS		 1192 spin_lock_irqsave(&bank->slock, flags);
1193
1194 /* enable the write to the equivalent lower bits */
1195 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
99e872d9 1196 rmask = data | (data >> 16);
3ba6767a 1197 data |= (ret << bit);
6ca5274d 1198
99e872d9 1199 ret = regmap_update_bits(regmap, reg, rmask, data);
6ca5274d
HS		 1200
1201 spin_unlock_irqrestore(&bank->slock, flags);
1202 break;
a282926d
HS		 1203 default:
1204 dev_err(info->dev, "unsupported pinctrl type\n");
1205 return -EINVAL;
d3e51161
HS		 1206 }
1207
751a99ab 1208 return ret;
d3e51161
HS		 1209}
1210
1211/*
1212 * Pinmux_ops handling
1213 */
1214
1215static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1216{
1217 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1218
1219 return info->nfunctions;
1220}
1221
1222static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1223 unsigned selector)
1224{
1225 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1226
1227 return info->functions[selector].name;
1228}
1229
1230static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1231 unsigned selector, const char * const **groups,
1232 unsigned * const num_groups)
1233{
1234 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1235
1236 *groups = info->functions[selector].groups;
1237 *num_groups = info->functions[selector].ngroups;
1238
1239 return 0;
1240}
1241
03e9f0ca
LW		 1242static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1243 unsigned group)
d3e51161
HS		 1244{
1245 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1246 const unsigned int *pins = info->groups[group].pins;
1247 const struct rockchip_pin_config *data = info->groups[group].data;
1248 struct rockchip_pin_bank *bank;
14797189 1249 int cnt, ret = 0;
d3e51161
HS		 1250
1251 dev_dbg(info->dev, "enable function %s group %s\n",
1252 info->functions[selector].name, info->groups[group].name);
1253
1254 /*
1255 * for each pin in the pin group selected, program the correspoding pin
1256 * pin function number in the config register.
1257 */
1258 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1259 bank = pin_to_bank(info, pins[cnt]);
14797189
HS		 1260 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1261 data[cnt].func);
1262 if (ret)
1263 break;
1264 }
1265
1266 if (ret) {
1267 /* revert the already done pin settings */
1268 for (cnt--; cnt >= 0; cnt--)
1269 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1270
1271 return ret;
d3e51161
HS		 1272 }
1273
1274 return 0;
1275}
1276
6ba20a00
CW		 1277static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1278{
1279 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1280 u32 data;
1281
1282 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1283
1284 return !(data & BIT(offset));
1285}
1286
d3e51161
HS		 1287/*
1288 * The calls to gpio_direction_output() and gpio_direction_input()
1289 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1290 * function called from the gpiolib interface).
1291 */
e5c2c9db
DA		 1292static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1293 int pin, bool input)
d3e51161 1294{
d3e51161 1295 struct rockchip_pin_bank *bank;
e5c2c9db 1296 int ret;
fab262f5 1297 unsigned long flags;
d3e51161
HS		 1298 u32 data;
1299
03bf81f1 1300 bank = gpiochip_get_data(chip);
d3e51161 1301
14797189
HS		 1302 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1303 if (ret < 0)
1304 return ret;
d3e51161 1305
07a06ae9 1306 clk_enable(bank->clk);
fab262f5
DA		 1307 spin_lock_irqsave(&bank->slock, flags);
1308
d3e51161
HS		 1309 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1310 /* set bit to 1 for output, 0 for input */
1311 if (!input)
1312 data |= BIT(pin);
1313 else
1314 data &= ~BIT(pin);
1315 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1316
fab262f5 1317 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1318 clk_disable(bank->clk);
fab262f5 1319
d3e51161
HS		 1320 return 0;
1321}
1322
e5c2c9db
DA		 1323static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1324 struct pinctrl_gpio_range *range,
1325 unsigned offset, bool input)
1326{
1327 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1328 struct gpio_chip *chip;
1329 int pin;
1330
1331 chip = range->gc;
1332 pin = offset - chip->base;
1333 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1334 offset, range->name, pin, input ? "input" : "output");
1335
1336 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1337 input);
1338}
1339
d3e51161
HS		 1340static const struct pinmux_ops rockchip_pmx_ops = {
1341 .get_functions_count = rockchip_pmx_get_funcs_count,
1342 .get_function_name = rockchip_pmx_get_func_name,
1343 .get_function_groups = rockchip_pmx_get_groups,
03e9f0ca 1344 .set_mux = rockchip_pmx_set,
d3e51161
HS		 1345 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
1346};
1347
1348/*
1349 * Pinconf_ops handling
1350 */
1351
44b6d930
HS		 1352static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1353 enum pin_config_param pull)
1354{
a282926d
HS		 1355 switch (ctrl->type) {
1356 case RK2928:
1357 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1358 pull == PIN_CONFIG_BIAS_DISABLE);
1359 case RK3066B:
44b6d930 1360 return pull ? false : true;
a282926d 1361 case RK3188:
66d750e1 1362 case RK3288:
daecdc66 1363 case RK3368:
b6c23275 1364 case RK3399:
a282926d 1365 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
44b6d930
HS		 1366 }
1367
a282926d 1368 return false;
44b6d930
HS		 1369}
1370
e5c2c9db 1371static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
a076e2ed
HS		 1372static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1373
d3e51161
HS		 1374/* set the pin config settings for a specified pin */
1375static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
03b054e9 1376 unsigned long *configs, unsigned num_configs)
d3e51161
HS		 1377{
1378 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1379 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
03b054e9
SY		 1380 enum pin_config_param param;
1381 u16 arg;
1382 int i;
1383 int rc;
1384
1385 for (i = 0; i < num_configs; i++) {
1386 param = pinconf_to_config_param(configs[i]);
1387 arg = pinconf_to_config_argument(configs[i]);
1388
1389 switch (param) {
1390 case PIN_CONFIG_BIAS_DISABLE:
1391 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1392 param);
1393 if (rc)
1394 return rc;
1395 break;
1396 case PIN_CONFIG_BIAS_PULL_UP:
1397 case PIN_CONFIG_BIAS_PULL_DOWN:
1398 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 1399 case PIN_CONFIG_BIAS_BUS_HOLD:
03b054e9
SY		 1400 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1401 return -ENOTSUPP;
1402
1403 if (!arg)
1404 return -EINVAL;
1405
1406 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1407 param);
1408 if (rc)
1409 return rc;
1410 break;
a076e2ed 1411 case PIN_CONFIG_OUTPUT:
e5c2c9db
DA		 1412 rockchip_gpio_set(&bank->gpio_chip,
1413 pin - bank->pin_base, arg);
1414 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1415 pin - bank->pin_base, false);
a076e2ed
HS		 1416 if (rc)
1417 return rc;
1418 break;
b547c800
HS		 1419 case PIN_CONFIG_DRIVE_STRENGTH:
1420 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 1421 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 1422 return -ENOTSUPP;
1423
ef17f69f
HS		 1424 rc = rockchip_set_drive_perpin(bank,
1425 pin - bank->pin_base, arg);
b547c800
HS		 1426 if (rc < 0)
1427 return rc;
1428 break;
03b054e9 1429 default:
44b6d930 1430 return -ENOTSUPP;
03b054e9
SY		 1431 break;
1432 }
1433 } /* for each config */
d3e51161
HS		 1434
1435 return 0;
1436}
1437
1438/* get the pin config settings for a specified pin */
1439static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1440 unsigned long *config)
1441{
1442 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1443 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1444 enum pin_config_param param = pinconf_to_config_param(*config);
dab3eba7 1445 u16 arg;
a076e2ed 1446 int rc;
d3e51161
HS		 1447
1448 switch (param) {
1449 case PIN_CONFIG_BIAS_DISABLE:
44b6d930
HS		 1450 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1451 return -EINVAL;
1452
dab3eba7 1453 arg = 0;
44b6d930 1454 break;
d3e51161
HS		 1455 case PIN_CONFIG_BIAS_PULL_UP:
1456 case PIN_CONFIG_BIAS_PULL_DOWN:
1457 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 1458 case PIN_CONFIG_BIAS_BUS_HOLD:
44b6d930
HS		 1459 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1460 return -ENOTSUPP;
d3e51161 1461
44b6d930 1462 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
d3e51161
HS		 1463 return -EINVAL;
1464
dab3eba7 1465 arg = 1;
d3e51161 1466 break;
a076e2ed
HS		 1467 case PIN_CONFIG_OUTPUT:
1468 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1469 if (rc != RK_FUNC_GPIO)
1470 return -EINVAL;
1471
1472 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1473 if (rc < 0)
1474 return rc;
1475
1476 arg = rc ? 1 : 0;
1477 break;
b547c800
HS		 1478 case PIN_CONFIG_DRIVE_STRENGTH:
1479 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 1480 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 1481 return -ENOTSUPP;
1482
ef17f69f 1483 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
b547c800
HS		 1484 if (rc < 0)
1485 return rc;
1486
1487 arg = rc;
1488 break;
d3e51161
HS		 1489 default:
1490 return -ENOTSUPP;
1491 break;
1492 }
1493
dab3eba7
HS		 1494 *config = pinconf_to_config_packed(param, arg);
1495
d3e51161
HS		 1496 return 0;
1497}
1498
1499static const struct pinconf_ops rockchip_pinconf_ops = {
1500 .pin_config_get = rockchip_pinconf_get,
1501 .pin_config_set = rockchip_pinconf_set,
ed62f2f2 1502 .is_generic = true,
d3e51161
HS		 1503};
1504
65fca613
HS		 1505static const struct of_device_id rockchip_bank_match[] = {
1506 { .compatible = "rockchip,gpio-bank" },
6ca5274d 1507 { .compatible = "rockchip,rk3188-gpio-bank0" },
65fca613
HS		 1508 {},
1509};
d3e51161
HS		 1510
1511static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1512 struct device_node *np)
1513{
1514 struct device_node *child;
1515
1516 for_each_child_of_node(np, child) {
65fca613 1517 if (of_match_node(rockchip_bank_match, child))
d3e51161
HS		 1518 continue;
1519
1520 info->nfunctions++;
1521 info->ngroups += of_get_child_count(child);
1522 }
1523}
1524
1525static int rockchip_pinctrl_parse_groups(struct device_node *np,
1526 struct rockchip_pin_group *grp,
1527 struct rockchip_pinctrl *info,
1528 u32 index)
1529{
1530 struct rockchip_pin_bank *bank;
1531 int size;
1532 const __be32 *list;
1533 int num;
1534 int i, j;
1535 int ret;
1536
1537 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1538
1539 /* Initialise group */
1540 grp->name = np->name;
1541
1542 /*
1543 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1544 * do sanity check and calculate pins number
1545 */
1546 list = of_get_property(np, "rockchip,pins", &size);
1547 /* we do not check return since it's safe node passed down */
1548 size /= sizeof(*list);
1549 if (!size || size % 4) {
1550 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1551 return -EINVAL;
1552 }
1553
1554 grp->npins = size / 4;
1555
1556 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1557 GFP_KERNEL);
1558 grp->data = devm_kzalloc(info->dev, grp->npins *
1559 sizeof(struct rockchip_pin_config),
1560 GFP_KERNEL);
1561 if (!grp->pins || !grp->data)
1562 return -ENOMEM;
1563
1564 for (i = 0, j = 0; i < size; i += 4, j++) {
1565 const __be32 *phandle;
1566 struct device_node *np_config;
1567
1568 num = be32_to_cpu(*list++);
1569 bank = bank_num_to_bank(info, num);
1570 if (IS_ERR(bank))
1571 return PTR_ERR(bank);
1572
1573 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1574 grp->data[j].func = be32_to_cpu(*list++);
1575
1576 phandle = list++;
1577 if (!phandle)
1578 return -EINVAL;
1579
1580 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
dd4d01f7 1581 ret = pinconf_generic_parse_dt_config(np_config, NULL,
d3e51161
HS		 1582 &grp->data[j].configs, &grp->data[j].nconfigs);
1583 if (ret)
1584 return ret;
1585 }
1586
1587 return 0;
1588}
1589
1590static int rockchip_pinctrl_parse_functions(struct device_node *np,
1591 struct rockchip_pinctrl *info,
1592 u32 index)
1593{
1594 struct device_node *child;
1595 struct rockchip_pmx_func *func;
1596 struct rockchip_pin_group *grp;
1597 int ret;
1598 static u32 grp_index;
1599 u32 i = 0;
1600
1601 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1602
1603 func = &info->functions[index];
1604
1605 /* Initialise function */
1606 func->name = np->name;
1607 func->ngroups = of_get_child_count(np);
1608 if (func->ngroups <= 0)
1609 return 0;
1610
1611 func->groups = devm_kzalloc(info->dev,
1612 func->ngroups * sizeof(char *), GFP_KERNEL);
1613 if (!func->groups)
1614 return -ENOMEM;
1615
1616 for_each_child_of_node(np, child) {
1617 func->groups[i] = child->name;
1618 grp = &info->groups[grp_index++];
1619 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
f7a81b7f
JL		 1620 if (ret) {
1621 of_node_put(child);
d3e51161 1622 return ret;
f7a81b7f 1623 }
d3e51161
HS		 1624 }
1625
1626 return 0;
1627}
1628
1629static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1630 struct rockchip_pinctrl *info)
1631{
1632 struct device *dev = &pdev->dev;
1633 struct device_node *np = dev->of_node;
1634 struct device_node *child;
1635 int ret;
1636 int i;
1637
1638 rockchip_pinctrl_child_count(info, np);
1639
1640 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1641 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1642
1643 info->functions = devm_kzalloc(dev, info->nfunctions *
1644 sizeof(struct rockchip_pmx_func),
1645 GFP_KERNEL);
1646 if (!info->functions) {
1647 dev_err(dev, "failed to allocate memory for function list\n");
1648 return -EINVAL;
1649 }
1650
1651 info->groups = devm_kzalloc(dev, info->ngroups *
1652 sizeof(struct rockchip_pin_group),
1653 GFP_KERNEL);
1654 if (!info->groups) {
1655 dev_err(dev, "failed allocate memory for ping group list\n");
1656 return -EINVAL;
1657 }
1658
1659 i = 0;
1660
1661 for_each_child_of_node(np, child) {
65fca613 1662 if (of_match_node(rockchip_bank_match, child))
d3e51161 1663 continue;
65fca613 1664
d3e51161
HS		 1665 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1666 if (ret) {
1667 dev_err(&pdev->dev, "failed to parse function\n");
f7a81b7f 1668 of_node_put(child);
d3e51161
HS		 1669 return ret;
1670 }
1671 }
1672
1673 return 0;
1674}
1675
1676static int rockchip_pinctrl_register(struct platform_device *pdev,
1677 struct rockchip_pinctrl *info)
1678{
1679 struct pinctrl_desc *ctrldesc = &info->pctl;
1680 struct pinctrl_pin_desc *pindesc, *pdesc;
1681 struct rockchip_pin_bank *pin_bank;
1682 int pin, bank, ret;
1683 int k;
1684
1685 ctrldesc->name = "rockchip-pinctrl";
1686 ctrldesc->owner = THIS_MODULE;
1687 ctrldesc->pctlops = &rockchip_pctrl_ops;
1688 ctrldesc->pmxops = &rockchip_pmx_ops;
1689 ctrldesc->confops = &rockchip_pinconf_ops;
1690
1691 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1692 info->ctrl->nr_pins, GFP_KERNEL);
1693 if (!pindesc) {
1694 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1695 return -ENOMEM;
1696 }
1697 ctrldesc->pins = pindesc;
1698 ctrldesc->npins = info->ctrl->nr_pins;
1699
1700 pdesc = pindesc;
1701 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1702 pin_bank = &info->ctrl->pin_banks[bank];
1703 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1704 pdesc->number = k;
1705 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1706 pin_bank->name, pin);
1707 pdesc++;
1708 }
1709 }
1710
0fb7dcb1
DA		 1711 ret = rockchip_pinctrl_parse_dt(pdev, info);
1712 if (ret)
1713 return ret;
1714
0085a2b4 1715 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
323de9ef 1716 if (IS_ERR(info->pctl_dev)) {
d3e51161 1717 dev_err(&pdev->dev, "could not register pinctrl driver\n");
323de9ef 1718 return PTR_ERR(info->pctl_dev);
d3e51161
HS		 1719 }
1720
1721 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1722 pin_bank = &info->ctrl->pin_banks[bank];
1723 pin_bank->grange.name = pin_bank->name;
1724 pin_bank->grange.id = bank;
1725 pin_bank->grange.pin_base = pin_bank->pin_base;
1726 pin_bank->grange.base = pin_bank->gpio_chip.base;
1727 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1728 pin_bank->grange.gc = &pin_bank->gpio_chip;
1729 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1730 }
1731
d3e51161
HS		 1732 return 0;
1733}
1734
1735/*
1736 * GPIO handling
1737 */
1738
1739static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1740{
03bf81f1 1741 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 1742 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1743 unsigned long flags;
1744 u32 data;
1745
07a06ae9 1746 clk_enable(bank->clk);
d3e51161
HS		 1747 spin_lock_irqsave(&bank->slock, flags);
1748
1749 data = readl(reg);
1750 data &= ~BIT(offset);
1751 if (value)
1752 data |= BIT(offset);
1753 writel(data, reg);
1754
1755 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1756 clk_disable(bank->clk);
d3e51161
HS		 1757}
1758
1759/*
1760 * Returns the level of the pin for input direction and setting of the DR
1761 * register for output gpios.
1762 */
1763static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1764{
03bf81f1 1765 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 1766 u32 data;
1767
07a06ae9 1768 clk_enable(bank->clk);
d3e51161 1769 data = readl(bank->reg_base + GPIO_EXT_PORT);
07a06ae9 1770 clk_disable(bank->clk);
d3e51161
HS		 1771 data >>= offset;
1772 data &= 1;
1773 return data;
1774}
1775
1776/*
1777 * gpiolib gpio_direction_input callback function. The setting of the pin
1778 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1779 * interface.
1780 */
1781static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1782{
1783 return pinctrl_gpio_direction_input(gc->base + offset);
1784}
1785
1786/*
1787 * gpiolib gpio_direction_output callback function. The setting of the pin
1788 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1789 * interface.
1790 */
1791static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1792 unsigned offset, int value)
1793{
1794 rockchip_gpio_set(gc, offset, value);
1795 return pinctrl_gpio_direction_output(gc->base + offset);
1796}
1797
1798/*
1799 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1800 * and a virtual IRQ, if not already present.
1801 */
1802static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1803{
03bf81f1 1804 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 1805 unsigned int virq;
1806
1807 if (!bank->domain)
1808 return -ENXIO;
1809
1810 virq = irq_create_mapping(bank->domain, offset);
1811
1812 return (virq) ? : -ENXIO;
1813}
1814
1815static const struct gpio_chip rockchip_gpiolib_chip = {
98c85d58
JG		 1816 .request = gpiochip_generic_request,
1817 .free = gpiochip_generic_free,
d3e51161
HS		 1818 .set = rockchip_gpio_set,
1819 .get = rockchip_gpio_get,
6ba20a00 1820 .get_direction = rockchip_gpio_get_direction,
d3e51161
HS		 1821 .direction_input = rockchip_gpio_direction_input,
1822 .direction_output = rockchip_gpio_direction_output,
1823 .to_irq = rockchip_gpio_to_irq,
1824 .owner = THIS_MODULE,
1825};
1826
1827/*
1828 * Interrupt handling
1829 */
1830
bd0b9ac4 1831static void rockchip_irq_demux(struct irq_desc *desc)
d3e51161 1832{
5663bb27
JL		 1833 struct irq_chip *chip = irq_desc_get_chip(desc);
1834 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
d3e51161
HS		 1835 u32 pend;
1836
1837 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1838
1839 chained_irq_enter(chip, desc);
1840
1841 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1842
1843 while (pend) {
415f748c 1844 unsigned int irq, virq;
d3e51161
HS		 1845
1846 irq = __ffs(pend);
1847 pend &= ~BIT(irq);
1848 virq = irq_linear_revmap(bank->domain, irq);
1849
1850 if (!virq) {
1851 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1852 continue;
1853 }
1854
1855 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1856
5a927501
HS		 1857 /*
1858 * Triggering IRQ on both rising and falling edge
1859 * needs manual intervention.
1860 */
1861 if (bank->toggle_edge_mode & BIT(irq)) {
53b1bfc7
DA		 1862 u32 data, data_old, polarity;
1863 unsigned long flags;
1864
1865 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1866 do {
1867 spin_lock_irqsave(&bank->slock, flags);
1868
1869 polarity = readl_relaxed(bank->reg_base +
1870 GPIO_INT_POLARITY);
1871 if (data & BIT(irq))
1872 polarity &= ~BIT(irq);
1873 else
1874 polarity |= BIT(irq);
1875 writel(polarity,
1876 bank->reg_base + GPIO_INT_POLARITY);
1877
1878 spin_unlock_irqrestore(&bank->slock, flags);
1879
1880 data_old = data;
1881 data = readl_relaxed(bank->reg_base +
1882 GPIO_EXT_PORT);
1883 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
5a927501
HS		 1884 }
1885
d3e51161
HS		 1886 generic_handle_irq(virq);
1887 }
1888
1889 chained_irq_exit(chip, desc);
1890}
1891
1892static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1893{
1894 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1895 struct rockchip_pin_bank *bank = gc->private;
1896 u32 mask = BIT(d->hwirq);
1897 u32 polarity;
1898 u32 level;
1899 u32 data;
fab262f5 1900 unsigned long flags;
14797189 1901 int ret;
d3e51161 1902
5a927501 1903 /* make sure the pin is configured as gpio input */
14797189
HS		 1904 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1905 if (ret < 0)
1906 return ret;
1907
07a06ae9 1908 clk_enable(bank->clk);
fab262f5
DA		 1909 spin_lock_irqsave(&bank->slock, flags);
1910
5a927501
HS		 1911 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1912 data &= ~mask;
1913 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1914
fab262f5
DA		 1915 spin_unlock_irqrestore(&bank->slock, flags);
1916
d3e51161 1917 if (type & IRQ_TYPE_EDGE_BOTH)
2dbf1bc5 1918 irq_set_handler_locked(d, handle_edge_irq);
d3e51161 1919 else
2dbf1bc5 1920 irq_set_handler_locked(d, handle_level_irq);
d3e51161 1921
fab262f5 1922 spin_lock_irqsave(&bank->slock, flags);
d3e51161
HS		 1923 irq_gc_lock(gc);
1924
1925 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1926 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1927
1928 switch (type) {
5a927501
HS		 1929 case IRQ_TYPE_EDGE_BOTH:
1930 bank->toggle_edge_mode |= mask;
1931 level |= mask;
1932
1933 /*
1934 * Determine gpio state. If 1 next interrupt should be falling
1935 * otherwise rising.
1936 */
1937 data = readl(bank->reg_base + GPIO_EXT_PORT);
1938 if (data & mask)
1939 polarity &= ~mask;
1940 else
1941 polarity |= mask;
1942 break;
d3e51161 1943 case IRQ_TYPE_EDGE_RISING:
5a927501 1944 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1945 level |= mask;
1946 polarity |= mask;
1947 break;
1948 case IRQ_TYPE_EDGE_FALLING:
5a927501 1949 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1950 level |= mask;
1951 polarity &= ~mask;
1952 break;
1953 case IRQ_TYPE_LEVEL_HIGH:
5a927501 1954 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1955 level &= ~mask;
1956 polarity |= mask;
1957 break;
1958 case IRQ_TYPE_LEVEL_LOW:
5a927501 1959 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1960 level &= ~mask;
1961 polarity &= ~mask;
1962 break;
1963 default:
7cc5f970 1964 irq_gc_unlock(gc);
fab262f5 1965 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1966 clk_disable(bank->clk);
d3e51161
HS		 1967 return -EINVAL;
1968 }
1969
1970 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1971 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1972
1973 irq_gc_unlock(gc);
fab262f5 1974 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1975 clk_disable(bank->clk);
d3e51161 1976
d3e51161
HS		 1977 return 0;
1978}
1979
68bda47c
DA		 1980static void rockchip_irq_suspend(struct irq_data *d)
1981{
1982 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1983 struct rockchip_pin_bank *bank = gc->private;
1984
07a06ae9 1985 clk_enable(bank->clk);
5ae0c7ad
DA		 1986 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1987 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
07a06ae9 1988 clk_disable(bank->clk);
68bda47c
DA		 1989}
1990
1991static void rockchip_irq_resume(struct irq_data *d)
1992{
1993 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1994 struct rockchip_pin_bank *bank = gc->private;
1995
07a06ae9 1996 clk_enable(bank->clk);
5ae0c7ad 1997 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
07a06ae9
LH		 1998 clk_disable(bank->clk);
1999}
2000
2001static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
2002{
2003 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2004 struct rockchip_pin_bank *bank = gc->private;
2005
2006 clk_enable(bank->clk);
2007 irq_gc_mask_clr_bit(d);
2008}
2009
2010void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
2011{
2012 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2013 struct rockchip_pin_bank *bank = gc->private;
2014
2015 irq_gc_mask_set_bit(d);
2016 clk_disable(bank->clk);
f2dd028c
DA		 2017}
2018
d3e51161
HS		 2019static int rockchip_interrupts_register(struct platform_device *pdev,
2020 struct rockchip_pinctrl *info)
2021{
2022 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2023 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2024 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2025 struct irq_chip_generic *gc;
2026 int ret;
07a06ae9 2027 int i, j;
d3e51161
HS		 2028
2029 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2030 if (!bank->valid) {
2031 dev_warn(&pdev->dev, "bank %s is not valid\n",
2032 bank->name);
2033 continue;
2034 }
2035
07a06ae9
LH		 2036 ret = clk_enable(bank->clk);
2037 if (ret) {
2038 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2039 bank->name);
2040 continue;
2041 }
2042
d3e51161
HS		 2043 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2044 &irq_generic_chip_ops, NULL);
2045 if (!bank->domain) {
2046 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2047 bank->name);
07a06ae9 2048 clk_disable(bank->clk);
d3e51161
HS		 2049 continue;
2050 }
2051
2052 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2053 "rockchip_gpio_irq", handle_level_irq,
2054 clr, 0, IRQ_GC_INIT_MASK_CACHE);
2055 if (ret) {
2056 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2057 bank->name);
2058 irq_domain_remove(bank->domain);
07a06ae9 2059 clk_disable(bank->clk);
d3e51161
HS		 2060 continue;
2061 }
2062
5ae0c7ad
DA		 2063 /*
2064 * Linux assumes that all interrupts start out disabled/masked.
2065 * Our driver only uses the concept of masked and always keeps
2066 * things enabled, so for us that's all masked and all enabled.
2067 */
2068 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2069 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2070
d3e51161
HS		 2071 gc = irq_get_domain_generic_chip(bank->domain, 0);
2072 gc->reg_base = bank->reg_base;
2073 gc->private = bank;
f2dd028c 2074 gc->chip_types[0].regs.mask = GPIO_INTMASK;
d3e51161
HS		 2075 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2076 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
07a06ae9
LH		 2077 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
2078 gc->chip_types[0].chip.irq_unmask =
2079 rockchip_irq_gc_mask_clr_bit;
d3e51161 2080 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
68bda47c
DA		 2081 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2082 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
d3e51161 2083 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
876d716b 2084 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
d3e51161 2085
03051bc2
TG		 2086 irq_set_chained_handler_and_data(bank->irq,
2087 rockchip_irq_demux, bank);
07a06ae9
LH		 2088
2089 /* map the gpio irqs here, when the clock is still running */
2090 for (j = 0 ; j < 32 ; j++)
2091 irq_create_mapping(bank->domain, j);
2092
2093 clk_disable(bank->clk);
d3e51161
HS		 2094 }
2095
2096 return 0;
2097}
2098
2099static int rockchip_gpiolib_register(struct platform_device *pdev,
2100 struct rockchip_pinctrl *info)
2101{
2102 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2103 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2104 struct gpio_chip *gc;
2105 int ret;
2106 int i;
2107
2108 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2109 if (!bank->valid) {
2110 dev_warn(&pdev->dev, "bank %s is not valid\n",
2111 bank->name);
2112 continue;
2113 }
2114
2115 bank->gpio_chip = rockchip_gpiolib_chip;
2116
2117 gc = &bank->gpio_chip;
2118 gc->base = bank->pin_base;
2119 gc->ngpio = bank->nr_pins;
58383c78 2120 gc->parent = &pdev->dev;
d3e51161
HS		 2121 gc->of_node = bank->of_node;
2122 gc->label = bank->name;
2123
03bf81f1 2124 ret = gpiochip_add_data(gc, bank);
d3e51161
HS		 2125 if (ret) {
2126 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2127 gc->label, ret);
2128 goto fail;
2129 }
2130 }
2131
2132 rockchip_interrupts_register(pdev, info);
2133
2134 return 0;
2135
2136fail:
2137 for (--i, --bank; i >= 0; --i, --bank) {
2138 if (!bank->valid)
2139 continue;
b4e7c55d 2140 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 2141 }
2142 return ret;
2143}
2144
2145static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2146 struct rockchip_pinctrl *info)
2147{
2148 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2149 struct rockchip_pin_bank *bank = ctrl->pin_banks;
d3e51161
HS		 2150 int i;
2151
b4e7c55d 2152 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
d3e51161
HS		 2153 if (!bank->valid)
2154 continue;
b4e7c55d 2155 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 2156 }
2157
b4e7c55d 2158 return 0;
d3e51161
HS		 2159}
2160
2161static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
622f3237 2162 struct rockchip_pinctrl *info)
d3e51161
HS		 2163{
2164 struct resource res;
751a99ab 2165 void __iomem *base;
d3e51161
HS		 2166
2167 if (of_address_to_resource(bank->of_node, 0, &res)) {
622f3237 2168 dev_err(info->dev, "cannot find IO resource for bank\n");
d3e51161
HS		 2169 return -ENOENT;
2170 }
2171
622f3237 2172 bank->reg_base = devm_ioremap_resource(info->dev, &res);
d3e51161
HS		 2173 if (IS_ERR(bank->reg_base))
2174 return PTR_ERR(bank->reg_base);
2175
6ca5274d
HS		 2176 /*
2177 * special case, where parts of the pull setting-registers are
2178 * part of the PMU register space
2179 */
2180 if (of_device_is_compatible(bank->of_node,
2181 "rockchip,rk3188-gpio-bank0")) {
a658efaa 2182 struct device_node *node;
bfc7a42a 2183
a658efaa
HS		 2184 node = of_parse_phandle(bank->of_node->parent,
2185 "rockchip,pmu", 0);
2186 if (!node) {
2187 if (of_address_to_resource(bank->of_node, 1, &res)) {
2188 dev_err(info->dev, "cannot find IO resource for bank\n");
2189 return -ENOENT;
2190 }
2191
2192 base = devm_ioremap_resource(info->dev, &res);
2193 if (IS_ERR(base))
2194 return PTR_ERR(base);
2195 rockchip_regmap_config.max_register =
2196 resource_size(&res) - 4;
2197 rockchip_regmap_config.name =
2198 "rockchip,rk3188-gpio-bank0-pull";
2199 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2200 base,
2201 &rockchip_regmap_config);
6ca5274d 2202 }
6ca5274d 2203 }
65fca613 2204
d3e51161
HS		 2205 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2206
2207 bank->clk = of_clk_get(bank->of_node, 0);
2208 if (IS_ERR(bank->clk))
2209 return PTR_ERR(bank->clk);
2210
07a06ae9 2211 return clk_prepare(bank->clk);
d3e51161
HS		 2212}
2213
2214static const struct of_device_id rockchip_pinctrl_dt_match[];
2215
2216/* retrieve the soc specific data */
2217static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2218 struct rockchip_pinctrl *d,
2219 struct platform_device *pdev)
2220{
2221 const struct of_device_id *match;
2222 struct device_node *node = pdev->dev.of_node;
2223 struct device_node *np;
2224 struct rockchip_pin_ctrl *ctrl;
2225 struct rockchip_pin_bank *bank;
b6c23275 2226 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
d3e51161
HS		 2227
2228 match = of_match_node(rockchip_pinctrl_dt_match, node);
2229 ctrl = (struct rockchip_pin_ctrl *)match->data;
2230
2231 for_each_child_of_node(node, np) {
2232 if (!of_find_property(np, "gpio-controller", NULL))
2233 continue;
2234
2235 bank = ctrl->pin_banks;
2236 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2237 if (!strcmp(bank->name, np->name)) {
2238 bank->of_node = np;
2239
622f3237 2240 if (!rockchip_get_bank_data(bank, d))
d3e51161
HS		 2241 bank->valid = true;
2242
2243 break;
2244 }
2245 }
2246 }
2247
95ec8ae4
HS		 2248 grf_offs = ctrl->grf_mux_offset;
2249 pmu_offs = ctrl->pmu_mux_offset;
b6c23275
DW		 2250 drv_pmu_offs = ctrl->pmu_drv_offset;
2251 drv_grf_offs = ctrl->grf_drv_offset;
d3e51161
HS		 2252 bank = ctrl->pin_banks;
2253 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
6bc0d121
HS		 2254 int bank_pins = 0;
2255
d3e51161
HS		 2256 spin_lock_init(&bank->slock);
2257 bank->drvdata = d;
2258 bank->pin_base = ctrl->nr_pins;
2259 ctrl->nr_pins += bank->nr_pins;
6bc0d121 2260
b6c23275 2261 /* calculate iomux and drv offsets */
6bc0d121
HS		 2262 for (j = 0; j < 4; j++) {
2263 struct rockchip_iomux *iom = &bank->iomux[j];
b6c23275 2264 struct rockchip_drv *drv = &bank->drv[j];
03716e1d 2265 int inc;
6bc0d121
HS		 2266
2267 if (bank_pins >= bank->nr_pins)
2268 break;
2269
b6c23275 2270 /* preset iomux offset value, set new start value */
6bc0d121 2271 if (iom->offset >= 0) {
95ec8ae4
HS		 2272 if (iom->type & IOMUX_SOURCE_PMU)
2273 pmu_offs = iom->offset;
2274 else
2275 grf_offs = iom->offset;
b6c23275 2276 } else { /* set current iomux offset */
95ec8ae4
HS		 2277 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2278 pmu_offs : grf_offs;
6bc0d121
HS		 2279 }
2280
b6c23275
DW		 2281 /* preset drv offset value, set new start value */
2282 if (drv->offset >= 0) {
2283 if (iom->type & IOMUX_SOURCE_PMU)
2284 drv_pmu_offs = drv->offset;
2285 else
2286 drv_grf_offs = drv->offset;
2287 } else { /* set current drv offset */
2288 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2289 drv_pmu_offs : drv_grf_offs;
2290 }
2291
2292 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2293 i, j, iom->offset, drv->offset);
6bc0d121
HS		 2294
2295 /*
2296 * Increase offset according to iomux width.
03716e1d 2297 * 4bit iomux'es are spread over two registers.
6bc0d121 2298 */
03716e1d 2299 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
95ec8ae4
HS		 2300 if (iom->type & IOMUX_SOURCE_PMU)
2301 pmu_offs += inc;
2302 else
2303 grf_offs += inc;
6bc0d121 2304
b6c23275
DW		 2305 /*
2306 * Increase offset according to drv width.
2307 * 3bit drive-strenth'es are spread over two registers.
2308 */
2309 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2310 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2311 inc = 8;
2312 else
2313 inc = 4;
2314
2315 if (iom->type & IOMUX_SOURCE_PMU)
2316 drv_pmu_offs += inc;
2317 else
2318 drv_grf_offs += inc;
2319
6bc0d121
HS		 2320 bank_pins += 8;
2321 }
d3e51161
HS		 2322 }
2323
2324 return ctrl;
2325}
2326
8dca9331
CZ		 2327#define RK3288_GRF_GPIO6C_IOMUX 0x64
2328#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2329
2330static u32 rk3288_grf_gpio6c_iomux;
2331
9198f509
CZ		 2332static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2333{
2334 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 2335 int ret = pinctrl_force_sleep(info->pctl_dev);
2336
2337 if (ret)
2338 return ret;
2339
2340 /*
2341 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2342 * the setting here, and restore it at resume.
2343 */
2344 if (info->ctrl->type == RK3288) {
2345 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2346 &rk3288_grf_gpio6c_iomux);
2347 if (ret) {
2348 pinctrl_force_default(info->pctl_dev);
2349 return ret;
2350 }
2351 }
9198f509 2352
8dca9331 2353 return 0;
9198f509
CZ		 2354}
2355
2356static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2357{
2358 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 2359 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2360 rk3288_grf_gpio6c_iomux |
2361 GPIO6C6_SEL_WRITE_ENABLE);
2362
2363 if (ret)
2364 return ret;
9198f509
CZ		 2365
2366 return pinctrl_force_default(info->pctl_dev);
2367}
2368
2369static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2370 rockchip_pinctrl_resume);
2371
d3e51161
HS		 2372static int rockchip_pinctrl_probe(struct platform_device *pdev)
2373{
2374 struct rockchip_pinctrl *info;
2375 struct device *dev = &pdev->dev;
2376 struct rockchip_pin_ctrl *ctrl;
14dee867 2377 struct device_node *np = pdev->dev.of_node, *node;
d3e51161 2378 struct resource *res;
751a99ab 2379 void __iomem *base;
d3e51161
HS		 2380 int ret;
2381
2382 if (!dev->of_node) {
2383 dev_err(dev, "device tree node not found\n");
2384 return -ENODEV;
2385 }
2386
2387 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2388 if (!info)
2389 return -ENOMEM;
2390
622f3237
HS		 2391 info->dev = dev;
2392
d3e51161
HS		 2393 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2394 if (!ctrl) {
2395 dev_err(dev, "driver data not available\n");
2396 return -EINVAL;
2397 }
2398 info->ctrl = ctrl;
d3e51161 2399
1e747e59
HS		 2400 node = of_parse_phandle(np, "rockchip,grf", 0);
2401 if (node) {
2402 info->regmap_base = syscon_node_to_regmap(node);
2403 if (IS_ERR(info->regmap_base))
2404 return PTR_ERR(info->regmap_base);
2405 } else {
2406 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
751a99ab
HS		 2407 base = devm_ioremap_resource(&pdev->dev, res);
2408 if (IS_ERR(base))
2409 return PTR_ERR(base);
2410
2411 rockchip_regmap_config.max_register = resource_size(res) - 4;
1e747e59
HS		 2412 rockchip_regmap_config.name = "rockchip,pinctrl";
2413 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2414 &rockchip_regmap_config);
2415
2416 /* to check for the old dt-bindings */
2417 info->reg_size = resource_size(res);
2418
2419 /* Honor the old binding, with pull registers as 2nd resource */
2420 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2421 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2422 base = devm_ioremap_resource(&pdev->dev, res);
2423 if (IS_ERR(base))
2424 return PTR_ERR(base);
2425
2426 rockchip_regmap_config.max_register =
2427 resource_size(res) - 4;
2428 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2429 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2430 base,
2431 &rockchip_regmap_config);
2432 }
6ca5274d
HS		 2433 }
2434
14dee867
HS		 2435 /* try to find the optional reference to the pmu syscon */
2436 node = of_parse_phandle(np, "rockchip,pmu", 0);
2437 if (node) {
2438 info->regmap_pmu = syscon_node_to_regmap(node);
2439 if (IS_ERR(info->regmap_pmu))
2440 return PTR_ERR(info->regmap_pmu);
2441 }
2442
d3e51161
HS		 2443 ret = rockchip_gpiolib_register(pdev, info);
2444 if (ret)
2445 return ret;
2446
2447 ret = rockchip_pinctrl_register(pdev, info);
2448 if (ret) {
2449 rockchip_gpiolib_unregister(pdev, info);
2450 return ret;
2451 }
2452
2453 platform_set_drvdata(pdev, info);
2454
2455 return 0;
2456}
2457
2458static struct rockchip_pin_bank rk2928_pin_banks[] = {
2459 PIN_BANK(0, 32, "gpio0"),
2460 PIN_BANK(1, 32, "gpio1"),
2461 PIN_BANK(2, 32, "gpio2"),
2462 PIN_BANK(3, 32, "gpio3"),
2463};
2464
2465static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2466 .pin_banks = rk2928_pin_banks,
2467 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2468 .label = "RK2928-GPIO",
a282926d 2469 .type = RK2928,
95ec8ae4 2470 .grf_mux_offset = 0xa8,
a282926d 2471 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 2472};
2473
c5ce7670
XZ		 2474static struct rockchip_pin_bank rk3036_pin_banks[] = {
2475 PIN_BANK(0, 32, "gpio0"),
2476 PIN_BANK(1, 32, "gpio1"),
2477 PIN_BANK(2, 32, "gpio2"),
2478};
2479
2480static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2481 .pin_banks = rk3036_pin_banks,
2482 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2483 .label = "RK3036-GPIO",
2484 .type = RK2928,
2485 .grf_mux_offset = 0xa8,
2486 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2487};
2488
d3e51161
HS		 2489static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2490 PIN_BANK(0, 32, "gpio0"),
2491 PIN_BANK(1, 32, "gpio1"),
2492 PIN_BANK(2, 32, "gpio2"),
2493 PIN_BANK(3, 32, "gpio3"),
2494 PIN_BANK(4, 32, "gpio4"),
2495 PIN_BANK(6, 16, "gpio6"),
2496};
2497
2498static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2499 .pin_banks = rk3066a_pin_banks,
2500 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2501 .label = "RK3066a-GPIO",
a282926d 2502 .type = RK2928,
95ec8ae4 2503 .grf_mux_offset = 0xa8,
a282926d 2504 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 2505};
2506
2507static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2508 PIN_BANK(0, 32, "gpio0"),
2509 PIN_BANK(1, 32, "gpio1"),
2510 PIN_BANK(2, 32, "gpio2"),
2511 PIN_BANK(3, 32, "gpio3"),
2512};
2513
2514static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2515 .pin_banks = rk3066b_pin_banks,
2516 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2517 .label = "RK3066b-GPIO",
a282926d 2518 .type = RK3066B,
95ec8ae4 2519 .grf_mux_offset = 0x60,
d3e51161
HS		 2520};
2521
2522static struct rockchip_pin_bank rk3188_pin_banks[] = {
fc72c923 2523 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
d3e51161
HS		 2524 PIN_BANK(1, 32, "gpio1"),
2525 PIN_BANK(2, 32, "gpio2"),
2526 PIN_BANK(3, 32, "gpio3"),
2527};
2528
2529static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2530 .pin_banks = rk3188_pin_banks,
2531 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2532 .label = "RK3188-GPIO",
a282926d 2533 .type = RK3188,
95ec8ae4 2534 .grf_mux_offset = 0x60,
6ca5274d 2535 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
d3e51161
HS		 2536};
2537
fea0fe60
JC		 2538static struct rockchip_pin_bank rk3228_pin_banks[] = {
2539 PIN_BANK(0, 32, "gpio0"),
2540 PIN_BANK(1, 32, "gpio1"),
2541 PIN_BANK(2, 32, "gpio2"),
2542 PIN_BANK(3, 32, "gpio3"),
2543};
2544
2545static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2546 .pin_banks = rk3228_pin_banks,
2547 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2548 .label = "RK3228-GPIO",
2549 .type = RK3288,
2550 .grf_mux_offset = 0x0,
2551 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2552 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2553};
2554
304f077d
HS		 2555static struct rockchip_pin_bank rk3288_pin_banks[] = {
2556 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2557 IOMUX_SOURCE_PMU,
2558 IOMUX_SOURCE_PMU,
2559 IOMUX_UNROUTED
2560 ),
2561 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2562 IOMUX_UNROUTED,
2563 IOMUX_UNROUTED,
2564 0
2565 ),
2566 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2567 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2568 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2569 IOMUX_WIDTH_4BIT,
2570 0,
2571 0
2572 ),
2573 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2574 0,
2575 0,
2576 IOMUX_UNROUTED
2577 ),
2578 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2579 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2580 0,
2581 IOMUX_WIDTH_4BIT,
2582 IOMUX_UNROUTED
2583 ),
2584 PIN_BANK(8, 16, "gpio8"),
2585};
2586
2587static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2588 .pin_banks = rk3288_pin_banks,
2589 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2590 .label = "RK3288-GPIO",
66d750e1 2591 .type = RK3288,
304f077d
HS		 2592 .grf_mux_offset = 0x0,
2593 .pmu_mux_offset = 0x84,
2594 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
ef17f69f 2595 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
304f077d
HS		 2596};
2597
daecdc66
HS		 2598static struct rockchip_pin_bank rk3368_pin_banks[] = {
2599 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2600 IOMUX_SOURCE_PMU,
2601 IOMUX_SOURCE_PMU,
2602 IOMUX_SOURCE_PMU
2603 ),
2604 PIN_BANK(1, 32, "gpio1"),
2605 PIN_BANK(2, 32, "gpio2"),
2606 PIN_BANK(3, 32, "gpio3"),
2607};
2608
2609static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2610 .pin_banks = rk3368_pin_banks,
2611 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
2612 .label = "RK3368-GPIO",
2613 .type = RK3368,
2614 .grf_mux_offset = 0x0,
2615 .pmu_mux_offset = 0x0,
2616 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
2617 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
2618};
2619
b6c23275 2620static struct rockchip_pin_bank rk3399_pin_banks[] = {
3ba6767a
DW		 2621 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
2622 IOMUX_SOURCE_PMU,
2623 IOMUX_SOURCE_PMU,
2624 IOMUX_SOURCE_PMU,
2625 IOMUX_SOURCE_PMU,
2626 DRV_TYPE_IO_1V8_ONLY,
2627 DRV_TYPE_IO_1V8_ONLY,
2628 DRV_TYPE_IO_DEFAULT,
2629 DRV_TYPE_IO_DEFAULT,
2630 0x0,
2631 0x8,
2632 -1,
2633 -1,
2634 PULL_TYPE_IO_1V8_ONLY,
2635 PULL_TYPE_IO_1V8_ONLY,
2636 PULL_TYPE_IO_DEFAULT,
2637 PULL_TYPE_IO_DEFAULT
2638 ),
b6c23275
DW		 2639 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
2640 IOMUX_SOURCE_PMU,
2641 IOMUX_SOURCE_PMU,
2642 IOMUX_SOURCE_PMU,
2643 DRV_TYPE_IO_1V8_OR_3V0,
2644 DRV_TYPE_IO_1V8_OR_3V0,
2645 DRV_TYPE_IO_1V8_OR_3V0,
2646 DRV_TYPE_IO_1V8_OR_3V0,
2647 0x20,
2648 0x28,
2649 0x30,
2650 0x38
2651 ),
3ba6767a
DW		 2652 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
2653 DRV_TYPE_IO_1V8_OR_3V0,
2654 DRV_TYPE_IO_1V8_ONLY,
2655 DRV_TYPE_IO_1V8_ONLY,
2656 PULL_TYPE_IO_DEFAULT,
2657 PULL_TYPE_IO_DEFAULT,
2658 PULL_TYPE_IO_1V8_ONLY,
2659 PULL_TYPE_IO_1V8_ONLY
2660 ),
b6c23275
DW		 2661 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
2662 DRV_TYPE_IO_3V3_ONLY,
2663 DRV_TYPE_IO_3V3_ONLY,
2664 DRV_TYPE_IO_1V8_OR_3V0
2665 ),
2666 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
2667 DRV_TYPE_IO_1V8_3V0_AUTO,
2668 DRV_TYPE_IO_1V8_OR_3V0,
2669 DRV_TYPE_IO_1V8_OR_3V0
2670 ),
2671};
2672
2673static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
2674 .pin_banks = rk3399_pin_banks,
2675 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
2676 .label = "RK3399-GPIO",
2677 .type = RK3399,
2678 .grf_mux_offset = 0xe000,
2679 .pmu_mux_offset = 0x0,
2680 .grf_drv_offset = 0xe100,
2681 .pmu_drv_offset = 0x80,
2682 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
2683 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
2684};
daecdc66 2685
d3e51161
HS		 2686static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2687 { .compatible = "rockchip,rk2928-pinctrl",
2688 .data = (void *)&rk2928_pin_ctrl },
c5ce7670
XZ		 2689 { .compatible = "rockchip,rk3036-pinctrl",
2690 .data = (void *)&rk3036_pin_ctrl },
d3e51161
HS		 2691 { .compatible = "rockchip,rk3066a-pinctrl",
2692 .data = (void *)&rk3066a_pin_ctrl },
2693 { .compatible = "rockchip,rk3066b-pinctrl",
2694 .data = (void *)&rk3066b_pin_ctrl },
2695 { .compatible = "rockchip,rk3188-pinctrl",
2696 .data = (void *)&rk3188_pin_ctrl },
fea0fe60
JC		 2697 { .compatible = "rockchip,rk3228-pinctrl",
2698 .data = (void *)&rk3228_pin_ctrl },
304f077d
HS		 2699 { .compatible = "rockchip,rk3288-pinctrl",
2700 .data = (void *)&rk3288_pin_ctrl },
daecdc66
HS		 2701 { .compatible = "rockchip,rk3368-pinctrl",
2702 .data = (void *)&rk3368_pin_ctrl },
b6c23275
DW		 2703 { .compatible = "rockchip,rk3399-pinctrl",
2704 .data = (void *)&rk3399_pin_ctrl },
d3e51161
HS		 2705 {},
2706};
2707MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2708
2709static struct platform_driver rockchip_pinctrl_driver = {
2710 .probe = rockchip_pinctrl_probe,
2711 .driver = {
2712 .name = "rockchip-pinctrl",
9198f509 2713 .pm = &rockchip_pinctrl_dev_pm_ops,
0be9e70d 2714 .of_match_table = rockchip_pinctrl_dt_match,
d3e51161
HS		 2715 },
2716};
2717
2718static int __init rockchip_pinctrl_drv_register(void)
2719{
2720 return platform_driver_register(&rockchip_pinctrl_driver);
2721}
2722postcore_initcall(rockchip_pinctrl_drv_register);
2723
2724MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2725MODULE_DESCRIPTION("Rockchip pinctrl driver");
2726MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)