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rtc: pcf8523: don't return invalid date when battery is low
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-at91.c
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6732ae5c
JCPV		 1/*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/init.h>
6732ae5c
JCPV		 12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/slab.h>
17#include <linux/interrupt.h>
6732ae5c 18#include <linux/io.h>
1c5fb66a 19#include <linux/gpio/driver.h>
6732ae5c
JCPV		 20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24/* Since we request GPIOs from ourself */
25#include <linux/pinctrl/consumer.h>
26
c654b6bf 27#include "pinctrl-at91.h"
6732ae5c
JCPV		 28#include "core.h"
29
94daf85e 30#define MAX_GPIO_BANKS 5
6732ae5c
JCPV		 31#define MAX_NB_GPIO_PER_BANK 32
32
33struct at91_pinctrl_mux_ops;
34
35struct at91_gpio_chip {
36 struct gpio_chip chip;
37 struct pinctrl_gpio_range range;
38 struct at91_gpio_chip *next; /* Bank sharing same clock */
39 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
40 int pioc_virq; /* PIO bank Linux virtual interrupt */
41 int pioc_idx; /* PIO bank index */
42 void __iomem *regbase; /* PIO bank virtual address */
43 struct clk *clock; /* associated clock */
6732ae5c
JCPV		 44 struct at91_pinctrl_mux_ops *ops; /* ops */
45};
46
6732ae5c
JCPV		 47static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
48
49static int gpio_banks;
50
525fae21 51#define PULL_UP (1 << 0)
6732ae5c 52#define MULTI_DRIVE (1 << 1)
7ebd7a3a
JCPV		 53#define DEGLITCH (1 << 2)
54#define PULL_DOWN (1 << 3)
55#define DIS_SCHMIT (1 << 4)
4334ac2d
MR		 56#define DRIVE_STRENGTH_SHIFT 5
57#define DRIVE_STRENGTH_MASK 0x3
58#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
96bb12de
BB		 59#define OUTPUT (1 << 7)
60#define OUTPUT_VAL_SHIFT 8
61#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
7ebd7a3a
JCPV		 62#define DEBOUNCE (1 << 16)
63#define DEBOUNCE_VAL_SHIFT 17
64#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
6732ae5c 65
4334ac2d
MR		 66/**
67 * These defines will translated the dt binding settings to our internal
68 * settings. They are not necessarily the same value as the register setting.
69 * The actual drive strength current of low, medium and high must be looked up
70 * from the corresponding device datasheet. This value is different for pins
71 * that are even in the same banks. It is also dependent on VCC.
72 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
73 * strength when there is no dt config for it.
74 */
75#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
76#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
77#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
78#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
79
6732ae5c
JCPV		 80/**
81 * struct at91_pmx_func - describes AT91 pinmux functions
82 * @name: the name of this specific function
83 * @groups: corresponding pin groups
84 * @ngroups: the number of groups
85 */
86struct at91_pmx_func {
87 const char *name;
88 const char **groups;
89 unsigned ngroups;
90};
91
92enum at91_mux {
93 AT91_MUX_GPIO = 0,
94 AT91_MUX_PERIPH_A = 1,
95 AT91_MUX_PERIPH_B = 2,
96 AT91_MUX_PERIPH_C = 3,
97 AT91_MUX_PERIPH_D = 4,
98};
99
100/**
101 * struct at91_pmx_pin - describes an At91 pin mux
102 * @bank: the bank of the pin
103 * @pin: the pin number in the @bank
104 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
105 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
106 */
107struct at91_pmx_pin {
108 uint32_t bank;
109 uint32_t pin;
110 enum at91_mux mux;
111 unsigned long conf;
112};
113
114/**
115 * struct at91_pin_group - describes an At91 pin group
116 * @name: the name of this specific pin group
117 * @pins_conf: the mux mode for each pin in this group. The size of this
118 * array is the same as pins.
119 * @pins: an array of discrete physical pins used in this group, taken
120 * from the driver-local pin enumeration space
121 * @npins: the number of pins in this group array, i.e. the number of
122 * elements in .pins so we can iterate over that array
123 */
124struct at91_pin_group {
125 const char *name;
126 struct at91_pmx_pin *pins_conf;
127 unsigned int *pins;
128 unsigned npins;
129};
130
131/**
c2eb9e7f 132 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
6732ae5c
JCPV		 133 * on new IP with support for periph C and D the way to mux in
134 * periph A and B has changed
135 * So provide the right call back
136 * if not present means the IP does not support it
137 * @get_periph: return the periph mode configured
138 * @mux_A_periph: mux as periph A
139 * @mux_B_periph: mux as periph B
140 * @mux_C_periph: mux as periph C
141 * @mux_D_periph: mux as periph D
7ebd7a3a
JCPV		 142 * @get_deglitch: get deglitch status
143 * @set_deglitch: enable/disable deglitch
144 * @get_debounce: get debounce status
145 * @set_debounce: enable/disable debounce
146 * @get_pulldown: get pulldown status
147 * @set_pulldown: enable/disable pulldown
148 * @get_schmitt_trig: get schmitt trigger status
149 * @disable_schmitt_trig: disable schmitt trigger
6732ae5c
JCPV		 150 * @irq_type: return irq type
151 */
152struct at91_pinctrl_mux_ops {
153 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
154 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
155 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
156 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
157 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
7ebd7a3a 158 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
77966ad7 159 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
7ebd7a3a 160 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
77966ad7 161 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
7ebd7a3a 162 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
77966ad7 163 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
7ebd7a3a
JCPV		 164 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
165 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
4334ac2d
MR		 166 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
167 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
168 u32 strength);
6732ae5c
JCPV		 169 /* irq */
170 int (*irq_type)(struct irq_data *d, unsigned type);
171};
172
173static int gpio_irq_type(struct irq_data *d, unsigned type);
174static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
175
176struct at91_pinctrl {
177 struct device *dev;
178 struct pinctrl_dev *pctl;
179
a0b957f3 180 int nactive_banks;
6732ae5c
JCPV		 181
182 uint32_t *mux_mask;
183 int nmux;
184
185 struct at91_pmx_func *functions;
186 int nfunctions;
187
188 struct at91_pin_group *groups;
189 int ngroups;
190
191 struct at91_pinctrl_mux_ops *ops;
192};
193
56411f3c 194static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
6732ae5c
JCPV		 195 const struct at91_pinctrl *info,
196 const char *name)
197{
198 const struct at91_pin_group *grp = NULL;
199 int i;
200
201 for (i = 0; i < info->ngroups; i++) {
202 if (strcmp(info->groups[i].name, name))
203 continue;
204
205 grp = &info->groups[i];
206 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
207 break;
208 }
209
210 return grp;
211}
212
213static int at91_get_groups_count(struct pinctrl_dev *pctldev)
214{
215 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
216
217 return info->ngroups;
218}
219
220static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
221 unsigned selector)
222{
223 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
224
225 return info->groups[selector].name;
226}
227
228static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
229 const unsigned **pins,
230 unsigned *npins)
231{
232 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
233
234 if (selector >= info->ngroups)
235 return -EINVAL;
236
237 *pins = info->groups[selector].pins;
238 *npins = info->groups[selector].npins;
239
240 return 0;
241}
242
243static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
244 unsigned offset)
245{
246 seq_printf(s, "%s", dev_name(pctldev->dev));
247}
248
249static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
250 struct device_node *np,
251 struct pinctrl_map **map, unsigned *num_maps)
252{
253 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
254 const struct at91_pin_group *grp;
255 struct pinctrl_map *new_map;
256 struct device_node *parent;
257 int map_num = 1;
258 int i;
6732ae5c
JCPV		 259
260 /*
61e310a1 261 * first find the group of this node and check if we need to create
6732ae5c
JCPV		 262 * config maps for pins
263 */
264 grp = at91_pinctrl_find_group_by_name(info, np->name);
265 if (!grp) {
94f4e54c
RH		 266 dev_err(info->dev, "unable to find group for node %pOFn\n",
267 np);
6732ae5c
JCPV		 268 return -EINVAL;
269 }
270
271 map_num += grp->npins;
a86854d0
KC		 272 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
273 GFP_KERNEL);
6732ae5c
JCPV		 274 if (!new_map)
275 return -ENOMEM;
276
277 *map = new_map;
278 *num_maps = map_num;
279
280 /* create mux map */
281 parent = of_get_parent(np);
282 if (!parent) {
c62b2b34 283 devm_kfree(pctldev->dev, new_map);
6732ae5c
JCPV		 284 return -EINVAL;
285 }
286 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
287 new_map[0].data.mux.function = parent->name;
288 new_map[0].data.mux.group = np->name;
289 of_node_put(parent);
290
291 /* create config map */
292 new_map++;
293 for (i = 0; i < grp->npins; i++) {
6732ae5c
JCPV		 294 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
295 new_map[i].data.configs.group_or_pin =
296 pin_get_name(pctldev, grp->pins[i]);
297 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
298 new_map[i].data.configs.num_configs = 1;
299 }
300
301 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
302 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
303
304 return 0;
305}
306
307static void at91_dt_free_map(struct pinctrl_dev *pctldev,
308 struct pinctrl_map *map, unsigned num_maps)
309{
310}
311
022ab148 312static const struct pinctrl_ops at91_pctrl_ops = {
6732ae5c
JCPV		 313 .get_groups_count = at91_get_groups_count,
314 .get_group_name = at91_get_group_name,
315 .get_group_pins = at91_get_group_pins,
316 .pin_dbg_show = at91_pin_dbg_show,
317 .dt_node_to_map = at91_dt_node_to_map,
318 .dt_free_map = at91_dt_free_map,
319};
320
3c93600d 321static void __iomem *pin_to_controller(struct at91_pinctrl *info,
6732ae5c
JCPV		 322 unsigned int bank)
323{
1ab36387
DD		 324 if (!gpio_chips[bank])
325 return NULL;
326
6732ae5c
JCPV		 327 return gpio_chips[bank]->regbase;
328}
329
330static inline int pin_to_bank(unsigned pin)
331{
332 return pin /= MAX_NB_GPIO_PER_BANK;
333}
334
335static unsigned pin_to_mask(unsigned int pin)
336{
337 return 1 << pin;
338}
339
4334ac2d
MR		 340static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
341{
342 /* return the shift value for a pin for "two bit" per pin registers,
343 * i.e. drive strength */
344 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
345 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
346}
347
348static unsigned sama5d3_get_drive_register(unsigned int pin)
349{
350 /* drive strength is split between two registers
351 * with two bits per pin */
352 return (pin >= MAX_NB_GPIO_PER_BANK/2)
353 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
354}
355
356static unsigned at91sam9x5_get_drive_register(unsigned int pin)
357{
358 /* drive strength is split between two registers
359 * with two bits per pin */
360 return (pin >= MAX_NB_GPIO_PER_BANK/2)
361 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
362}
363
6732ae5c
JCPV		 364static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
365{
366 writel_relaxed(mask, pio + PIO_IDR);
367}
368
369static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
370{
05d3534a 371 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
6732ae5c
JCPV		 372}
373
374static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
375{
3d784273
WY		 376 if (on)
377 writel_relaxed(mask, pio + PIO_PPDDR);
378
6732ae5c
JCPV		 379 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
380}
381
96bb12de
BB		 382static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
383{
384 *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
385 return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
386}
387
388static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
389 bool is_on, bool val)
390{
391 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
392 writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
393}
394
6732ae5c
JCPV		 395static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
396{
397 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
398}
399
400static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
401{
402 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
403}
404
405static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
406{
407 writel_relaxed(mask, pio + PIO_ASR);
408}
409
410static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
411{
412 writel_relaxed(mask, pio + PIO_BSR);
413}
414
415static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
416{
417
418 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
419 pio + PIO_ABCDSR1);
420 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
421 pio + PIO_ABCDSR2);
422}
423
424static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
425{
426 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
427 pio + PIO_ABCDSR1);
428 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
429 pio + PIO_ABCDSR2);
430}
431
432static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
433{
434 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
435 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
436}
437
438static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
439{
440 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
441 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
442}
443
444static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
445{
446 unsigned select;
447
448 if (readl_relaxed(pio + PIO_PSR) & mask)
449 return AT91_MUX_GPIO;
450
451 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
452 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
453
454 return select + 1;
455}
456
457static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
458{
459 unsigned select;
460
461 if (readl_relaxed(pio + PIO_PSR) & mask)
462 return AT91_MUX_GPIO;
463
464 select = readl_relaxed(pio + PIO_ABSR) & mask;
465
466 return select + 1;
467}
468
7ebd7a3a
JCPV		 469static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
470{
d480239b 471 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
7ebd7a3a
JCPV		 472}
473
474static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
475{
d480239b 476 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
7ebd7a3a
JCPV		 477}
478
c8dba02e
BB		 479static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
480{
d480239b
BD		 481 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
482 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
c8dba02e
BB		 483
484 return false;
485}
486
7ebd7a3a
JCPV		 487static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
488{
489 if (is_on)
d480239b 490 writel_relaxed(mask, pio + PIO_IFSCDR);
7ebd7a3a
JCPV		 491 at91_mux_set_deglitch(pio, mask, is_on);
492}
493
494static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
495{
d480239b 496 *div = readl_relaxed(pio + PIO_SCDR);
7ebd7a3a 497
d480239b
BD		 498 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
499 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
7ebd7a3a
JCPV		 500}
501
502static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
503 bool is_on, u32 div)
504{
505 if (is_on) {
d480239b
BD		 506 writel_relaxed(mask, pio + PIO_IFSCER);
507 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
508 writel_relaxed(mask, pio + PIO_IFER);
c8dba02e 509 } else
d480239b 510 writel_relaxed(mask, pio + PIO_IFSCDR);
7ebd7a3a
JCPV		 511}
512
513static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
514{
d480239b 515 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
7ebd7a3a
JCPV		 516}
517
518static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
519{
3d784273 520 if (is_on)
d480239b 521 writel_relaxed(mask, pio + PIO_PUDR);
3d784273 522
d480239b 523 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
7ebd7a3a
JCPV		 524}
525
526static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
527{
d480239b 528 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
7ebd7a3a
JCPV		 529}
530
531static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
532{
d480239b 533 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
7ebd7a3a
JCPV		 534}
535
4334ac2d
MR		 536static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
537{
d480239b 538 unsigned tmp = readl_relaxed(reg);
4334ac2d
MR		 539
540 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
541
542 return tmp & DRIVE_STRENGTH_MASK;
543}
544
545static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
546 unsigned pin)
547{
548 unsigned tmp = read_drive_strength(pio +
549 sama5d3_get_drive_register(pin), pin);
550
551 /* SAMA5 strength is 1:1 with our defines,
552 * except 0 is equivalent to low per datasheet */
553 if (!tmp)
554 tmp = DRIVE_STRENGTH_LOW;
555
556 return tmp;
557}
558
559static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
560 unsigned pin)
561{
562 unsigned tmp = read_drive_strength(pio +
563 at91sam9x5_get_drive_register(pin), pin);
564
565 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
566 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
567 tmp = DRIVE_STRENGTH_HI - tmp;
568
569 return tmp;
570}
571
572static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
573{
d480239b 574 unsigned tmp = readl_relaxed(reg);
4334ac2d
MR		 575 unsigned shift = two_bit_pin_value_shift_amount(pin);
576
577 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
578 tmp |= strength << shift;
579
d480239b 580 writel_relaxed(tmp, reg);
4334ac2d
MR		 581}
582
583static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
584 u32 setting)
585{
586 /* do nothing if setting is zero */
587 if (!setting)
588 return;
589
590 /* strength is 1 to 1 with setting for SAMA5 */
591 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
592}
593
594static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
595 u32 setting)
596{
597 /* do nothing if setting is zero */
598 if (!setting)
599 return;
600
601 /* strength is inverse on SAM9x5s with our defines
602 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
603 setting = DRIVE_STRENGTH_HI - setting;
604
605 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
606 setting);
607}
608
6732ae5c
JCPV		 609static struct at91_pinctrl_mux_ops at91rm9200_ops = {
610 .get_periph = at91_mux_get_periph,
611 .mux_A_periph = at91_mux_set_A_periph,
612 .mux_B_periph = at91_mux_set_B_periph,
7ebd7a3a
JCPV		 613 .get_deglitch = at91_mux_get_deglitch,
614 .set_deglitch = at91_mux_set_deglitch,
6732ae5c
JCPV		 615 .irq_type = gpio_irq_type,
616};
617
618static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
619 .get_periph = at91_mux_pio3_get_periph,
620 .mux_A_periph = at91_mux_pio3_set_A_periph,
621 .mux_B_periph = at91_mux_pio3_set_B_periph,
622 .mux_C_periph = at91_mux_pio3_set_C_periph,
623 .mux_D_periph = at91_mux_pio3_set_D_periph,
c8dba02e 624 .get_deglitch = at91_mux_pio3_get_deglitch,
7ebd7a3a
JCPV		 625 .set_deglitch = at91_mux_pio3_set_deglitch,
626 .get_debounce = at91_mux_pio3_get_debounce,
627 .set_debounce = at91_mux_pio3_set_debounce,
628 .get_pulldown = at91_mux_pio3_get_pulldown,
629 .set_pulldown = at91_mux_pio3_set_pulldown,
630 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
631 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
4334ac2d
MR		 632 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
633 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
634 .irq_type = alt_gpio_irq_type,
635};
636
637static struct at91_pinctrl_mux_ops sama5d3_ops = {
638 .get_periph = at91_mux_pio3_get_periph,
639 .mux_A_periph = at91_mux_pio3_set_A_periph,
640 .mux_B_periph = at91_mux_pio3_set_B_periph,
641 .mux_C_periph = at91_mux_pio3_set_C_periph,
642 .mux_D_periph = at91_mux_pio3_set_D_periph,
643 .get_deglitch = at91_mux_pio3_get_deglitch,
644 .set_deglitch = at91_mux_pio3_set_deglitch,
645 .get_debounce = at91_mux_pio3_get_debounce,
646 .set_debounce = at91_mux_pio3_set_debounce,
647 .get_pulldown = at91_mux_pio3_get_pulldown,
648 .set_pulldown = at91_mux_pio3_set_pulldown,
649 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
650 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
651 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
652 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
6732ae5c
JCPV		 653 .irq_type = alt_gpio_irq_type,
654};
655
656static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
657{
658 if (pin->mux) {
4b6fe45a 659 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
6732ae5c
JCPV		 660 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
661 } else {
4b6fe45a 662 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
6732ae5c
JCPV		 663 pin->bank + 'A', pin->pin, pin->conf);
664 }
665}
666
3c93600d 667static int pin_check_config(struct at91_pinctrl *info, const char *name,
6732ae5c
JCPV		 668 int index, const struct at91_pmx_pin *pin)
669{
670 int mux;
671
672 /* check if it's a valid config */
a0b957f3 673 if (pin->bank >= gpio_banks) {
6732ae5c 674 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
a0b957f3 675 name, index, pin->bank, gpio_banks);
6732ae5c
JCPV		 676 return -EINVAL;
677 }
678
a0b957f3
JCPV		 679 if (!gpio_chips[pin->bank]) {
680 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
681 name, index, pin->bank);
682 return -ENXIO;
683 }
684
6732ae5c
JCPV		 685 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
686 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
687 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
688 return -EINVAL;
689 }
690
691 if (!pin->mux)
692 return 0;
693
694 mux = pin->mux - 1;
695
696 if (mux >= info->nmux) {
697 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
698 name, index, mux, info->nmux);
699 return -EINVAL;
700 }
701
702 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
703 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
704 name, index, mux, pin->bank + 'A', pin->pin);
705 return -EINVAL;
706 }
707
708 return 0;
709}
710
711static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
712{
713 writel_relaxed(mask, pio + PIO_PDR);
714}
715
716static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
717{
718 writel_relaxed(mask, pio + PIO_PER);
719 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
720}
721
03e9f0ca
LW		 722static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
723 unsigned group)
6732ae5c
JCPV		 724{
725 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
726 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
727 const struct at91_pmx_pin *pin;
728 uint32_t npins = info->groups[group].npins;
729 int i, ret;
730 unsigned mask;
731 void __iomem *pio;
732
733 dev_dbg(info->dev, "enable function %s group %s\n",
734 info->functions[selector].name, info->groups[group].name);
735
736 /* first check that all the pins of the group are valid with a valid
61e310a1 737 * parameter */
6732ae5c
JCPV		 738 for (i = 0; i < npins; i++) {
739 pin = &pins_conf[i];
740 ret = pin_check_config(info, info->groups[group].name, i, pin);
741 if (ret)
742 return ret;
743 }
744
745 for (i = 0; i < npins; i++) {
746 pin = &pins_conf[i];
747 at91_pin_dbg(info->dev, pin);
748 pio = pin_to_controller(info, pin->bank);
1ab36387
DD		 749
750 if (!pio)
751 continue;
752
6732ae5c
JCPV		 753 mask = pin_to_mask(pin->pin);
754 at91_mux_disable_interrupt(pio, mask);
3c93600d 755 switch (pin->mux) {
6732ae5c
JCPV		 756 case AT91_MUX_GPIO:
757 at91_mux_gpio_enable(pio, mask, 1);
758 break;
759 case AT91_MUX_PERIPH_A:
760 info->ops->mux_A_periph(pio, mask);
761 break;
762 case AT91_MUX_PERIPH_B:
763 info->ops->mux_B_periph(pio, mask);
764 break;
765 case AT91_MUX_PERIPH_C:
766 if (!info->ops->mux_C_periph)
767 return -EINVAL;
768 info->ops->mux_C_periph(pio, mask);
769 break;
770 case AT91_MUX_PERIPH_D:
771 if (!info->ops->mux_D_periph)
772 return -EINVAL;
773 info->ops->mux_D_periph(pio, mask);
774 break;
775 }
776 if (pin->mux)
777 at91_mux_gpio_disable(pio, mask);
778 }
779
780 return 0;
781}
782
6732ae5c
JCPV		 783static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
784{
785 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
786
787 return info->nfunctions;
788}
789
790static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
791 unsigned selector)
792{
793 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
794
795 return info->functions[selector].name;
796}
797
798static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
799 const char * const **groups,
800 unsigned * const num_groups)
801{
802 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
803
804 *groups = info->functions[selector].groups;
805 *num_groups = info->functions[selector].ngroups;
806
807 return 0;
808}
809
f6f94f66
AL		 810static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
811 struct pinctrl_gpio_range *range,
812 unsigned offset)
6732ae5c
JCPV		 813{
814 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
815 struct at91_gpio_chip *at91_chip;
816 struct gpio_chip *chip;
817 unsigned mask;
818
819 if (!range) {
820 dev_err(npct->dev, "invalid range\n");
821 return -EINVAL;
822 }
823 if (!range->gc) {
824 dev_err(npct->dev, "missing GPIO chip in range\n");
825 return -EINVAL;
826 }
827 chip = range->gc;
370ea611 828 at91_chip = gpiochip_get_data(chip);
6732ae5c
JCPV		 829
830 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
831
832 mask = 1 << (offset - chip->base);
833
834 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
835 offset, 'A' + range->id, offset - chip->base, mask);
836
837 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
838
839 return 0;
840}
841
f6f94f66
AL		 842static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
843 struct pinctrl_gpio_range *range,
844 unsigned offset)
6732ae5c
JCPV		 845{
846 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
847
848 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
849 /* Set the pin to some default state, GPIO is usually default */
850}
851
022ab148 852static const struct pinmux_ops at91_pmx_ops = {
6732ae5c
JCPV		 853 .get_functions_count = at91_pmx_get_funcs_count,
854 .get_function_name = at91_pmx_get_func_name,
855 .get_function_groups = at91_pmx_get_groups,
03e9f0ca 856 .set_mux = at91_pmx_set,
6732ae5c
JCPV		 857 .gpio_request_enable = at91_gpio_request_enable,
858 .gpio_disable_free = at91_gpio_disable_free,
859};
860
861static int at91_pinconf_get(struct pinctrl_dev *pctldev,
862 unsigned pin_id, unsigned long *config)
863{
864 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
865 void __iomem *pio;
866 unsigned pin;
7ebd7a3a 867 int div;
96bb12de 868 bool out;
6732ae5c 869
1292e693
AB		 870 *config = 0;
871 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
6732ae5c 872 pio = pin_to_controller(info, pin_to_bank(pin_id));
1ab36387
DD		 873
874 if (!pio)
875 return -EINVAL;
876
6732ae5c
JCPV		 877 pin = pin_id % MAX_NB_GPIO_PER_BANK;
878
879 if (at91_mux_get_multidrive(pio, pin))
880 *config |= MULTI_DRIVE;
881
882 if (at91_mux_get_pullup(pio, pin))
883 *config |= PULL_UP;
884
7ebd7a3a
JCPV		 885 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
886 *config |= DEGLITCH;
887 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
888 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
889 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
890 *config |= PULL_DOWN;
891 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
892 *config |= DIS_SCHMIT;
4334ac2d
MR		 893 if (info->ops->get_drivestrength)
894 *config |= (info->ops->get_drivestrength(pio, pin)
895 << DRIVE_STRENGTH_SHIFT);
96bb12de
BB		 896 if (at91_mux_get_output(pio, pin, &out))
897 *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
7ebd7a3a 898
6732ae5c
JCPV		 899 return 0;
900}
901
902static int at91_pinconf_set(struct pinctrl_dev *pctldev,
03b054e9
SY		 903 unsigned pin_id, unsigned long *configs,
904 unsigned num_configs)
6732ae5c
JCPV		 905{
906 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
907 unsigned mask;
908 void __iomem *pio;
03b054e9
SY		 909 int i;
910 unsigned long config;
4334ac2d 911 unsigned pin;
03b054e9
SY		 912
913 for (i = 0; i < num_configs; i++) {
914 config = configs[i];
915
916 dev_dbg(info->dev,
917 "%s:%d, pin_id=%d, config=0x%lx",
918 __func__, __LINE__, pin_id, config);
919 pio = pin_to_controller(info, pin_to_bank(pin_id));
1ab36387
DD		 920
921 if (!pio)
922 return -EINVAL;
923
4334ac2d
MR		 924 pin = pin_id % MAX_NB_GPIO_PER_BANK;
925 mask = pin_to_mask(pin);
03b054e9
SY		 926
927 if (config & PULL_UP && config & PULL_DOWN)
928 return -EINVAL;
929
96bb12de
BB		 930 at91_mux_set_output(pio, mask, config & OUTPUT,
931 (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
03b054e9
SY		 932 at91_mux_set_pullup(pio, mask, config & PULL_UP);
933 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
934 if (info->ops->set_deglitch)
935 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
936 if (info->ops->set_debounce)
937 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
7ebd7a3a 938 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
03b054e9
SY		 939 if (info->ops->set_pulldown)
940 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
941 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
942 info->ops->disable_schmitt_trig(pio, mask);
4334ac2d
MR		 943 if (info->ops->set_drivestrength)
944 info->ops->set_drivestrength(pio, pin,
945 (config & DRIVE_STRENGTH)
946 >> DRIVE_STRENGTH_SHIFT);
03b054e9
SY		 947
948 } /* for each config */
7ebd7a3a 949
6732ae5c
JCPV		 950 return 0;
951}
952
4d9b8a8e
AB		 953#define DBG_SHOW_FLAG(flag) do { \
954 if (config & flag) { \
955 if (num_conf) \
956 seq_puts(s, "|"); \
957 seq_puts(s, #flag); \
958 num_conf++; \
959 } \
960} while (0)
961
4334ac2d
MR		 962#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
963 if ((config & mask) == flag) { \
964 if (num_conf) \
965 seq_puts(s, "|"); \
966 seq_puts(s, #flag); \
967 num_conf++; \
968 } \
969} while (0)
970
6732ae5c
JCPV		 971static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
972 struct seq_file *s, unsigned pin_id)
973{
4d9b8a8e 974 unsigned long config;
445d2026 975 int val, num_conf = 0;
4d9b8a8e 976
445d2026 977 at91_pinconf_get(pctldev, pin_id, &config);
4d9b8a8e
AB		 978
979 DBG_SHOW_FLAG(MULTI_DRIVE);
980 DBG_SHOW_FLAG(PULL_UP);
981 DBG_SHOW_FLAG(PULL_DOWN);
982 DBG_SHOW_FLAG(DIS_SCHMIT);
983 DBG_SHOW_FLAG(DEGLITCH);
4334ac2d
MR		 984 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
985 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
986 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
4d9b8a8e
AB		 987 DBG_SHOW_FLAG(DEBOUNCE);
988 if (config & DEBOUNCE) {
989 val = config >> DEBOUNCE_VAL_SHIFT;
990 seq_printf(s, "(%d)", val);
991 }
6732ae5c 992
4d9b8a8e 993 return;
6732ae5c
JCPV		 994}
995
996static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
997 struct seq_file *s, unsigned group)
998{
999}
1000
022ab148 1001static const struct pinconf_ops at91_pinconf_ops = {
6732ae5c
JCPV		 1002 .pin_config_get = at91_pinconf_get,
1003 .pin_config_set = at91_pinconf_set,
1004 .pin_config_dbg_show = at91_pinconf_dbg_show,
1005 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
1006};
1007
1008static struct pinctrl_desc at91_pinctrl_desc = {
1009 .pctlops = &at91_pctrl_ops,
1010 .pmxops = &at91_pmx_ops,
1011 .confops = &at91_pinconf_ops,
1012 .owner = THIS_MODULE,
1013};
1014
1015static const char *gpio_compat = "atmel,at91rm9200-gpio";
1016
150632b0
GKH		 1017static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1018 struct device_node *np)
6732ae5c
JCPV		 1019{
1020 struct device_node *child;
1021
1022 for_each_child_of_node(np, child) {
1023 if (of_device_is_compatible(child, gpio_compat)) {
a0b957f3
JCPV		 1024 if (of_device_is_available(child))
1025 info->nactive_banks++;
6732ae5c
JCPV		 1026 } else {
1027 info->nfunctions++;
1028 info->ngroups += of_get_child_count(child);
1029 }
1030 }
1031}
1032
150632b0
GKH		 1033static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1034 struct device_node *np)
6732ae5c
JCPV		 1035{
1036 int ret = 0;
1037 int size;
1164d73a 1038 const __be32 *list;
6732ae5c
JCPV		 1039
1040 list = of_get_property(np, "atmel,mux-mask", &size);
1041 if (!list) {
1042 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1043 return -EINVAL;
1044 }
1045
1046 size /= sizeof(*list);
a0b957f3
JCPV		 1047 if (!size || size % gpio_banks) {
1048 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
6732ae5c
JCPV		 1049 return -EINVAL;
1050 }
a0b957f3 1051 info->nmux = size / gpio_banks;
6732ae5c 1052
a86854d0
KC		 1053 info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
1054 GFP_KERNEL);
3da941b0 1055 if (!info->mux_mask)
6732ae5c 1056 return -ENOMEM;
6732ae5c
JCPV		 1057
1058 ret = of_property_read_u32_array(np, "atmel,mux-mask",
1059 info->mux_mask, size);
1060 if (ret)
1061 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1062 return ret;
1063}
1064
150632b0
GKH		 1065static int at91_pinctrl_parse_groups(struct device_node *np,
1066 struct at91_pin_group *grp,
1067 struct at91_pinctrl *info, u32 index)
6732ae5c
JCPV		 1068{
1069 struct at91_pmx_pin *pin;
1070 int size;
1164d73a 1071 const __be32 *list;
6732ae5c
JCPV		 1072 int i, j;
1073
94f4e54c 1074 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
6732ae5c
JCPV		 1075
1076 /* Initialise group */
1077 grp->name = np->name;
1078
1079 /*
1080 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1081 * do sanity check and calculate pins number
1082 */
1083 list = of_get_property(np, "atmel,pins", &size);
1084 /* we do not check return since it's safe node passed down */
1085 size /= sizeof(*list);
1086 if (!size || size % 4) {
1087 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1088 return -EINVAL;
1089 }
1090
1091 grp->npins = size / 4;
a86854d0
KC		 1092 pin = grp->pins_conf = devm_kcalloc(info->dev,
1093 grp->npins,
1094 sizeof(struct at91_pmx_pin),
1095 GFP_KERNEL);
1096 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
1097 GFP_KERNEL);
6732ae5c
JCPV		 1098 if (!grp->pins_conf || !grp->pins)
1099 return -ENOMEM;
1100
1101 for (i = 0, j = 0; i < size; i += 4, j++) {
1102 pin->bank = be32_to_cpu(*list++);
1103 pin->pin = be32_to_cpu(*list++);
1104 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1105 pin->mux = be32_to_cpu(*list++);
1106 pin->conf = be32_to_cpu(*list++);
1107
1108 at91_pin_dbg(info->dev, pin);
1109 pin++;
1110 }
1111
1112 return 0;
1113}
1114
150632b0
GKH		 1115static int at91_pinctrl_parse_functions(struct device_node *np,
1116 struct at91_pinctrl *info, u32 index)
6732ae5c
JCPV		 1117{
1118 struct device_node *child;
1119 struct at91_pmx_func *func;
1120 struct at91_pin_group *grp;
1121 int ret;
1122 static u32 grp_index;
1123 u32 i = 0;
1124
94f4e54c 1125 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
6732ae5c
JCPV		 1126
1127 func = &info->functions[index];
1128
1129 /* Initialise function */
1130 func->name = np->name;
1131 func->ngroups = of_get_child_count(np);
ca7162ad 1132 if (func->ngroups == 0) {
6732ae5c
JCPV		 1133 dev_err(info->dev, "no groups defined\n");
1134 return -EINVAL;
1135 }
a86854d0
KC		 1136 func->groups = devm_kcalloc(info->dev,
1137 func->ngroups, sizeof(char *), GFP_KERNEL);
6732ae5c
JCPV		 1138 if (!func->groups)
1139 return -ENOMEM;
1140
1141 for_each_child_of_node(np, child) {
1142 func->groups[i] = child->name;
1143 grp = &info->groups[grp_index++];
1144 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
d94b986a
JL		 1145 if (ret) {
1146 of_node_put(child);
6732ae5c 1147 return ret;
d94b986a 1148 }
6732ae5c
JCPV		 1149 }
1150
1151 return 0;
1152}
1153
baa9946e 1154static const struct of_device_id at91_pinctrl_of_match[] = {
4334ac2d 1155 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
6732ae5c
JCPV		 1156 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1157 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1158 { /* sentinel */ }
1159};
1160
150632b0
GKH		 1161static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1162 struct at91_pinctrl *info)
6732ae5c
JCPV		 1163{
1164 int ret = 0;
1165 int i, j;
1166 uint32_t *tmp;
1167 struct device_node *np = pdev->dev.of_node;
1168 struct device_node *child;
1169
1170 if (!np)
1171 return -ENODEV;
1172
1173 info->dev = &pdev->dev;
3c93600d 1174 info->ops = (struct at91_pinctrl_mux_ops *)
6732ae5c
JCPV		 1175 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1176 at91_pinctrl_child_count(info, np);
1177
a0b957f3 1178 if (gpio_banks < 1) {
61e310a1 1179 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
6732ae5c
JCPV		 1180 return -EINVAL;
1181 }
1182
1183 ret = at91_pinctrl_mux_mask(info, np);
1184 if (ret)
1185 return ret;
1186
1187 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1188
1189 dev_dbg(&pdev->dev, "mux-mask\n");
1190 tmp = info->mux_mask;
a0b957f3 1191 for (i = 0; i < gpio_banks; i++) {
6732ae5c
JCPV		 1192 for (j = 0; j < info->nmux; j++, tmp++) {
1193 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1194 }
1195 }
1196
1197 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1198 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
a86854d0
KC		 1199 info->functions = devm_kcalloc(&pdev->dev,
1200 info->nfunctions,
1201 sizeof(struct at91_pmx_func),
6732ae5c
JCPV		 1202 GFP_KERNEL);
1203 if (!info->functions)
1204 return -ENOMEM;
1205
a86854d0
KC		 1206 info->groups = devm_kcalloc(&pdev->dev,
1207 info->ngroups,
1208 sizeof(struct at91_pin_group),
6732ae5c
JCPV		 1209 GFP_KERNEL);
1210 if (!info->groups)
1211 return -ENOMEM;
1212
a0b957f3 1213 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
6732ae5c
JCPV		 1214 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1215 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1216
1217 i = 0;
1218
1219 for_each_child_of_node(np, child) {
1220 if (of_device_is_compatible(child, gpio_compat))
1221 continue;
1222 ret = at91_pinctrl_parse_functions(child, info, i++);
1223 if (ret) {
1224 dev_err(&pdev->dev, "failed to parse function\n");
d94b986a 1225 of_node_put(child);
6732ae5c
JCPV		 1226 return ret;
1227 }
1228 }
1229
1230 return 0;
1231}
1232
150632b0 1233static int at91_pinctrl_probe(struct platform_device *pdev)
6732ae5c
JCPV		 1234{
1235 struct at91_pinctrl *info;
1236 struct pinctrl_pin_desc *pdesc;
a0b957f3 1237 int ret, i, j, k, ngpio_chips_enabled = 0;
6732ae5c
JCPV		 1238
1239 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1240 if (!info)
1241 return -ENOMEM;
1242
1243 ret = at91_pinctrl_probe_dt(pdev, info);
1244 if (ret)
1245 return ret;
1246
1247 /*
1248 * We need all the GPIO drivers to probe FIRST, or we will not be able
1249 * to obtain references to the struct gpio_chip * for them, and we
1250 * need this to proceed.
1251 */
a0b957f3
JCPV		 1252 for (i = 0; i < gpio_banks; i++)
1253 if (gpio_chips[i])
1254 ngpio_chips_enabled++;
1255
1256 if (ngpio_chips_enabled < info->nactive_banks) {
1257 dev_warn(&pdev->dev,
1258 "All GPIO chips are not registered yet (%d/%d)\n",
1259 ngpio_chips_enabled, info->nactive_banks);
1260 devm_kfree(&pdev->dev, info);
1261 return -EPROBE_DEFER;
6732ae5c
JCPV		 1262 }
1263
1264 at91_pinctrl_desc.name = dev_name(&pdev->dev);
a0b957f3 1265 at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
6732ae5c 1266 at91_pinctrl_desc.pins = pdesc =
a86854d0
KC		 1267 devm_kcalloc(&pdev->dev,
1268 at91_pinctrl_desc.npins, sizeof(*pdesc),
1269 GFP_KERNEL);
6732ae5c
JCPV		 1270
1271 if (!at91_pinctrl_desc.pins)
1272 return -ENOMEM;
1273
a0b957f3 1274 for (i = 0, k = 0; i < gpio_banks; i++) {
6732ae5c
JCPV		 1275 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1276 pdesc->number = k;
1277 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1278 pdesc++;
1279 }
1280 }
1281
1282 platform_set_drvdata(pdev, info);
5c67425a
LD		 1283 info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
1284 info);
6732ae5c 1285
323de9ef 1286 if (IS_ERR(info->pctl)) {
6732ae5c 1287 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
323de9ef 1288 return PTR_ERR(info->pctl);
6732ae5c
JCPV		 1289 }
1290
1291 /* We will handle a range of GPIO pins */
a0b957f3
JCPV		 1292 for (i = 0; i < gpio_banks; i++)
1293 if (gpio_chips[i])
1294 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
6732ae5c
JCPV		 1295
1296 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1297
1298 return 0;
6732ae5c
JCPV		 1299}
1300
8af584b8
RG		 1301static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1302{
370ea611 1303 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
8af584b8
RG		 1304 void __iomem *pio = at91_gpio->regbase;
1305 unsigned mask = 1 << offset;
1306 u32 osr;
1307
1308 osr = readl_relaxed(pio + PIO_OSR);
1309 return !(osr & mask);
1310}
1311
6732ae5c
JCPV		 1312static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1313{
370ea611 1314 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
6732ae5c
JCPV		 1315 void __iomem *pio = at91_gpio->regbase;
1316 unsigned mask = 1 << offset;
1317
1318 writel_relaxed(mask, pio + PIO_ODR);
1319 return 0;
1320}
1321
1322static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1323{
370ea611 1324 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
6732ae5c
JCPV		 1325 void __iomem *pio = at91_gpio->regbase;
1326 unsigned mask = 1 << offset;
1327 u32 pdsr;
1328
1329 pdsr = readl_relaxed(pio + PIO_PDSR);
1330 return (pdsr & mask) != 0;
1331}
1332
1333static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1334 int val)
1335{
370ea611 1336 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
6732ae5c
JCPV		 1337 void __iomem *pio = at91_gpio->regbase;
1338 unsigned mask = 1 << offset;
1339
1340 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1341}
1342
1893b2cf
AS		 1343static void at91_gpio_set_multiple(struct gpio_chip *chip,
1344 unsigned long *mask, unsigned long *bits)
1345{
370ea611 1346 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1893b2cf
AS		 1347 void __iomem *pio = at91_gpio->regbase;
1348
1349#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1350 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1351 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1352 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1353
1354 writel_relaxed(set_mask, pio + PIO_SODR);
1355 writel_relaxed(clear_mask, pio + PIO_CODR);
1356}
1357
6732ae5c
JCPV		 1358static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1359 int val)
1360{
370ea611 1361 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
6732ae5c
JCPV		 1362 void __iomem *pio = at91_gpio->regbase;
1363 unsigned mask = 1 << offset;
1364
1365 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1366 writel_relaxed(mask, pio + PIO_OER);
1367
1368 return 0;
1369}
1370
6732ae5c
JCPV		 1371#ifdef CONFIG_DEBUG_FS
1372static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1373{
1374 enum at91_mux mode;
1375 int i;
370ea611 1376 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
6732ae5c
JCPV		 1377 void __iomem *pio = at91_gpio->regbase;
1378
1379 for (i = 0; i < chip->ngpio; i++) {
47f22716 1380 unsigned mask = pin_to_mask(i);
6732ae5c 1381 const char *gpio_label;
6732ae5c
JCPV		 1382
1383 gpio_label = gpiochip_is_requested(chip, i);
1384 if (!gpio_label)
1385 continue;
1386 mode = at91_gpio->ops->get_periph(pio, mask);
1387 seq_printf(s, "[%s] GPIO%s%d: ",
1388 gpio_label, chip->label, i);
1389 if (mode == AT91_MUX_GPIO) {
853b6bf0
MC		 1390 seq_printf(s, "[gpio] ");
1391 seq_printf(s, "%s ",
1392 readl_relaxed(pio + PIO_OSR) & mask ?
1393 "output" : "input");
1394 seq_printf(s, "%s\n",
1395 readl_relaxed(pio + PIO_PDSR) & mask ?
1396 "set" : "clear");
6732ae5c
JCPV		 1397 } else {
1398 seq_printf(s, "[periph %c]\n",
1399 mode + 'A' - 1);
1400 }
1401 }
1402}
1403#else
1404#define at91_gpio_dbg_show NULL
1405#endif
1406
1407/* Several AIC controller irqs are dispatched through this GPIO handler.
1408 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1409 * at91_set_gpio_input() then maybe enable its glitch filter.
1410 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1411 * handler.
1412 * First implementation always triggers on rising and falling edges
1413 * whereas the newer PIO3 can be additionally configured to trigger on
1414 * level, edge with any polarity.
1415 *
1416 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1417 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1418 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1419 */
1420
1421static void gpio_irq_mask(struct irq_data *d)
1422{
1423 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1424 void __iomem *pio = at91_gpio->regbase;
1425 unsigned mask = 1 << d->hwirq;
1426
1427 if (pio)
1428 writel_relaxed(mask, pio + PIO_IDR);
1429}
1430
1431static void gpio_irq_unmask(struct irq_data *d)
1432{
1433 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1434 void __iomem *pio = at91_gpio->regbase;
1435 unsigned mask = 1 << d->hwirq;
1436
1437 if (pio)
1438 writel_relaxed(mask, pio + PIO_IER);
1439}
1440
1441static int gpio_irq_type(struct irq_data *d, unsigned type)
1442{
1443 switch (type) {
1444 case IRQ_TYPE_NONE:
1445 case IRQ_TYPE_EDGE_BOTH:
1446 return 0;
1447 default:
1448 return -EINVAL;
1449 }
1450}
1451
1452/* Alternate irq type for PIO3 support */
1453static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1454{
1455 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1456 void __iomem *pio = at91_gpio->regbase;
1457 unsigned mask = 1 << d->hwirq;
1458
1459 switch (type) {
1460 case IRQ_TYPE_EDGE_RISING:
c639845b 1461 irq_set_handler_locked(d, handle_simple_irq);
6732ae5c
JCPV		 1462 writel_relaxed(mask, pio + PIO_ESR);
1463 writel_relaxed(mask, pio + PIO_REHLSR);
1464 break;
1465 case IRQ_TYPE_EDGE_FALLING:
c639845b 1466 irq_set_handler_locked(d, handle_simple_irq);
6732ae5c
JCPV		 1467 writel_relaxed(mask, pio + PIO_ESR);
1468 writel_relaxed(mask, pio + PIO_FELLSR);
1469 break;
1470 case IRQ_TYPE_LEVEL_LOW:
c639845b 1471 irq_set_handler_locked(d, handle_level_irq);
6732ae5c
JCPV		 1472 writel_relaxed(mask, pio + PIO_LSR);
1473 writel_relaxed(mask, pio + PIO_FELLSR);
1474 break;
1475 case IRQ_TYPE_LEVEL_HIGH:
c639845b 1476 irq_set_handler_locked(d, handle_level_irq);
6732ae5c
JCPV		 1477 writel_relaxed(mask, pio + PIO_LSR);
1478 writel_relaxed(mask, pio + PIO_REHLSR);
1479 break;
1480 case IRQ_TYPE_EDGE_BOTH:
1481 /*
1482 * disable additional interrupt modes:
1483 * fall back to default behavior
1484 */
c639845b 1485 irq_set_handler_locked(d, handle_simple_irq);
6732ae5c
JCPV		 1486 writel_relaxed(mask, pio + PIO_AIMDR);
1487 return 0;
1488 case IRQ_TYPE_NONE:
1489 default:
1c5fb66a 1490 pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
6732ae5c
JCPV		 1491 return -EINVAL;
1492 }
1493
1494 /* enable additional interrupt modes */
1495 writel_relaxed(mask, pio + PIO_AIMER);
1496
1497 return 0;
1498}
1499
80cc3732
AS		 1500static void gpio_irq_ack(struct irq_data *d)
1501{
1502 /* the interrupt is already cleared before by reading ISR */
1503}
1504
6732ae5c 1505#ifdef CONFIG_PM
647f8d94
LD		 1506
1507static u32 wakeups[MAX_GPIO_BANKS];
1508static u32 backups[MAX_GPIO_BANKS];
1509
6732ae5c
JCPV		 1510static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1511{
1512 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1513 unsigned bank = at91_gpio->pioc_idx;
647f8d94 1514 unsigned mask = 1 << d->hwirq;
6732ae5c
JCPV		 1515
1516 if (unlikely(bank >= MAX_GPIO_BANKS))
1517 return -EINVAL;
1518
647f8d94
LD		 1519 if (state)
1520 wakeups[bank] |= mask;
1521 else
1522 wakeups[bank] &= ~mask;
1523
6732ae5c
JCPV		 1524 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1525
1526 return 0;
1527}
647f8d94
LD		 1528
1529void at91_pinctrl_gpio_suspend(void)
1530{
1531 int i;
1532
1533 for (i = 0; i < gpio_banks; i++) {
1534 void __iomem *pio;
1535
1536 if (!gpio_chips[i])
1537 continue;
1538
1539 pio = gpio_chips[i]->regbase;
1540
d480239b
BD		 1541 backups[i] = readl_relaxed(pio + PIO_IMR);
1542 writel_relaxed(backups[i], pio + PIO_IDR);
1543 writel_relaxed(wakeups[i], pio + PIO_IER);
647f8d94 1544
795f9953
BB		 1545 if (!wakeups[i])
1546 clk_disable_unprepare(gpio_chips[i]->clock);
1547 else
647f8d94
LD		 1548 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1549 'A'+i, wakeups[i]);
647f8d94
LD		 1550 }
1551}
1552
1553void at91_pinctrl_gpio_resume(void)
1554{
1555 int i;
1556
1557 for (i = 0; i < gpio_banks; i++) {
1558 void __iomem *pio;
1559
1560 if (!gpio_chips[i])
1561 continue;
1562
1563 pio = gpio_chips[i]->regbase;
1564
37ef1d92
BB		 1565 if (!wakeups[i])
1566 clk_prepare_enable(gpio_chips[i]->clock);
647f8d94 1567
d480239b
BD		 1568 writel_relaxed(wakeups[i], pio + PIO_IDR);
1569 writel_relaxed(backups[i], pio + PIO_IER);
647f8d94
LD		 1570 }
1571}
1572
6732ae5c
JCPV		 1573#else
1574#define gpio_irq_set_wake NULL
647f8d94 1575#endif /* CONFIG_PM */
6732ae5c 1576
bd0b9ac4 1577static void gpio_irq_handler(struct irq_desc *desc)
6732ae5c 1578{
5663bb27 1579 struct irq_chip *chip = irq_desc_get_chip(desc);
80cc3732 1580 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
370ea611 1581 struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
6732ae5c
JCPV		 1582 void __iomem *pio = at91_gpio->regbase;
1583 unsigned long isr;
1584 int n;
1585
1586 chained_irq_enter(chip, desc);
1587 for (;;) {
1588 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
c2eb9e7f 1589 * When there are none pending, we're finished unless we need
6732ae5c
JCPV		 1590 * to process multiple banks (like ID_PIOCDE on sam9263).
1591 */
1592 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1593 if (!isr) {
1594 if (!at91_gpio->next)
1595 break;
1596 at91_gpio = at91_gpio->next;
1597 pio = at91_gpio->regbase;
cccb0c3e 1598 gpio_chip = &at91_gpio->chip;
6732ae5c
JCPV		 1599 continue;
1600 }
1601
05daa16a 1602 for_each_set_bit(n, &isr, BITS_PER_LONG) {
80cc3732 1603 generic_handle_irq(irq_find_mapping(
f0fbe7bc 1604 gpio_chip->irq.domain, n));
6732ae5c
JCPV		 1605 }
1606 }
1607 chained_irq_exit(chip, desc);
1608 /* now it may re-trigger */
1609}
1610
834e1678 1611static int at91_gpio_of_irq_setup(struct platform_device *pdev,
6732ae5c
JCPV		 1612 struct at91_gpio_chip *at91_gpio)
1613{
a0b957f3 1614 struct gpio_chip *gpiochip_prev = NULL;
cccb0c3e 1615 struct at91_gpio_chip *prev = NULL;
6732ae5c 1616 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
0c3dfa17 1617 struct irq_chip *gpio_irqchip;
a0b957f3 1618 int ret, i;
6732ae5c 1619
0c3dfa17
LD		 1620 gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), GFP_KERNEL);
1621 if (!gpio_irqchip)
1622 return -ENOMEM;
1623
6732ae5c
JCPV		 1624 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1625
0c3dfa17
LD		 1626 gpio_irqchip->name = "GPIO";
1627 gpio_irqchip->irq_ack = gpio_irq_ack;
1628 gpio_irqchip->irq_disable = gpio_irq_mask;
1629 gpio_irqchip->irq_mask = gpio_irq_mask;
1630 gpio_irqchip->irq_unmask = gpio_irq_unmask;
1631 gpio_irqchip->irq_set_wake = gpio_irq_set_wake,
1632 gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
6732ae5c
JCPV		 1633
1634 /* Disable irqs of this PIO controller */
1635 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1636
80cc3732
AS		 1637 /*
1638 * Let the generic code handle this edge IRQ, the the chained
1639 * handler will perform the actual work of handling the parent
1640 * interrupt.
1641 */
1642 ret = gpiochip_irqchip_add(&at91_gpio->chip,
0c3dfa17 1643 gpio_irqchip,
80cc3732
AS		 1644 0,
1645 handle_edge_irq,
5803348c 1646 IRQ_TYPE_NONE);
834e1678
PG		 1647 if (ret) {
1648 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
6732ae5c 1649 at91_gpio->pioc_idx);
834e1678
PG		 1650 return ret;
1651 }
6732ae5c 1652
cccb0c3e
AS		 1653 /* The top level handler handles one bank of GPIOs, except
1654 * on some SoC it can handle up to three...
1655 * We only set up the handler for the first of the list.
1656 */
a0b957f3
JCPV		 1657 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1658 if (!gpiochip_prev) {
1659 /* Then register the chain on the parent IRQ */
1660 gpiochip_set_chained_irqchip(&at91_gpio->chip,
0c3dfa17 1661 gpio_irqchip,
a0b957f3
JCPV		 1662 at91_gpio->pioc_virq,
1663 gpio_irq_handler);
cccb0c3e 1664 return 0;
a0b957f3 1665 }
cccb0c3e 1666
370ea611 1667 prev = gpiochip_get_data(gpiochip_prev);
6732ae5c 1668
a0b957f3
JCPV		 1669 /* we can only have 2 banks before */
1670 for (i = 0; i < 2; i++) {
1671 if (prev->next) {
1672 prev = prev->next;
1673 } else {
1674 prev->next = at91_gpio;
1675 return 0;
1676 }
1677 }
1678
1679 return -EINVAL;
6732ae5c
JCPV		 1680}
1681
1682/* This structure is replicated for each GPIO block allocated at probe time */
234b6513 1683static const struct gpio_chip at91_gpio_template = {
98c85d58
JG		 1684 .request = gpiochip_generic_request,
1685 .free = gpiochip_generic_free,
8af584b8 1686 .get_direction = at91_gpio_get_direction,
6732ae5c
JCPV		 1687 .direction_input = at91_gpio_direction_input,
1688 .get = at91_gpio_get,
1689 .direction_output = at91_gpio_direction_output,
1690 .set = at91_gpio_set,
1893b2cf 1691 .set_multiple = at91_gpio_set_multiple,
6732ae5c 1692 .dbg_show = at91_gpio_dbg_show,
9fb1f39e 1693 .can_sleep = false,
6732ae5c
JCPV		 1694 .ngpio = MAX_NB_GPIO_PER_BANK,
1695};
1696
baa9946e 1697static const struct of_device_id at91_gpio_of_match[] = {
6732ae5c
JCPV		 1698 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1699 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1700 { /* sentinel */ }
1701};
1702
150632b0 1703static int at91_gpio_probe(struct platform_device *pdev)
6732ae5c
JCPV		 1704{
1705 struct device_node *np = pdev->dev.of_node;
1706 struct resource *res;
1707 struct at91_gpio_chip *at91_chip = NULL;
1708 struct gpio_chip *chip;
1709 struct pinctrl_gpio_range *range;
1710 int ret = 0;
32b01a36 1711 int irq, i;
6732ae5c
JCPV		 1712 int alias_idx = of_alias_get_id(np, "gpio");
1713 uint32_t ngpio;
32b01a36 1714 char **names;
6732ae5c
JCPV		 1715
1716 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1717 if (gpio_chips[alias_idx]) {
1718 ret = -EBUSY;
1719 goto err;
1720 }
1721
6732ae5c
JCPV		 1722 irq = platform_get_irq(pdev, 0);
1723 if (irq < 0) {
1724 ret = irq;
1725 goto err;
1726 }
1727
1728 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1729 if (!at91_chip) {
1730 ret = -ENOMEM;
1731 goto err;
1732 }
1733
f50b9e12 1734 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9e0c1fb2
TR		 1735 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1736 if (IS_ERR(at91_chip->regbase)) {
1737 ret = PTR_ERR(at91_chip->regbase);
6732ae5c
JCPV		 1738 goto err;
1739 }
1740
3c93600d 1741 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
6732ae5c
JCPV		 1742 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1743 at91_chip->pioc_virq = irq;
1744 at91_chip->pioc_idx = alias_idx;
1745
02b837ff 1746 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
6732ae5c
JCPV		 1747 if (IS_ERR(at91_chip->clock)) {
1748 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
70e41974 1749 ret = PTR_ERR(at91_chip->clock);
6732ae5c
JCPV		 1750 goto err;
1751 }
1752
7d3a3fe6 1753 ret = clk_prepare_enable(at91_chip->clock);
70e41974 1754 if (ret) {
7d3a3fe6 1755 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
70e41974 1756 goto clk_enable_err;
6732ae5c
JCPV		 1757 }
1758
1759 at91_chip->chip = at91_gpio_template;
1760
1761 chip = &at91_chip->chip;
1762 chip->of_node = np;
1763 chip->label = dev_name(&pdev->dev);
58383c78 1764 chip->parent = &pdev->dev;
6732ae5c
JCPV		 1765 chip->owner = THIS_MODULE;
1766 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1767
1768 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1769 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1770 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1771 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1772 else
1773 chip->ngpio = ngpio;
1774 }
1775
a86854d0 1776 names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *),
3c93600d 1777 GFP_KERNEL);
32b01a36
JCPV		 1778
1779 if (!names) {
1780 ret = -ENOMEM;
70e41974 1781 goto clk_enable_err;
32b01a36
JCPV		 1782 }
1783
1784 for (i = 0; i < chip->ngpio; i++)
1785 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1786
3c93600d 1787 chip->names = (const char *const *)names;
32b01a36 1788
6732ae5c
JCPV		 1789 range = &at91_chip->range;
1790 range->name = chip->label;
1791 range->id = alias_idx;
1792 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1793
1794 range->npins = chip->ngpio;
1795 range->gc = chip;
1796
370ea611 1797 ret = gpiochip_add_data(chip, at91_chip);
6732ae5c 1798 if (ret)
70e41974 1799 goto gpiochip_add_err;
6732ae5c
JCPV		 1800
1801 gpio_chips[alias_idx] = at91_chip;
1802 gpio_banks = max(gpio_banks, alias_idx + 1);
1803
834e1678
PG		 1804 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1805 if (ret)
1806 goto irq_setup_err;
6732ae5c
JCPV		 1807
1808 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1809
1810 return 0;
1811
834e1678
PG		 1812irq_setup_err:
1813 gpiochip_remove(chip);
70e41974 1814gpiochip_add_err:
70e41974 1815clk_enable_err:
7d3a3fe6 1816 clk_disable_unprepare(at91_chip->clock);
6732ae5c
JCPV		 1817err:
1818 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1819
1820 return ret;
1821}
1822
1823static struct platform_driver at91_gpio_driver = {
1824 .driver = {
1825 .name = "gpio-at91",
606fca94 1826 .of_match_table = at91_gpio_of_match,
6732ae5c
JCPV		 1827 },
1828 .probe = at91_gpio_probe,
1829};
1830
1831static struct platform_driver at91_pinctrl_driver = {
1832 .driver = {
1833 .name = "pinctrl-at91",
606fca94 1834 .of_match_table = at91_pinctrl_of_match,
6732ae5c
JCPV		 1835 },
1836 .probe = at91_pinctrl_probe,
6732ae5c
JCPV		 1837};
1838
bab7f5a4
TR		 1839static struct platform_driver * const drivers[] = {
1840 &at91_gpio_driver,
1841 &at91_pinctrl_driver,
1842};
1843
6732ae5c
JCPV		 1844static int __init at91_pinctrl_init(void)
1845{
bab7f5a4 1846 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
6732ae5c
JCPV		 1847}
1848arch_initcall(at91_pinctrl_init);
Linux 6.x block layer and io_uring tree(s)