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1da177e4 LT |
1 | /* |
2 | * Driver for Intel I82092AA PCI-PCMCIA bridge. | |
3 | * | |
4 | * (C) 2001 Red Hat, Inc. | |
5 | * | |
6 | * Author: Arjan Van De Ven <arjanv@redhat.com> | |
7 | * Loosly based on i82365.c from the pcmcia-cs package | |
1da177e4 LT |
8 | */ |
9 | ||
10 | #include <linux/kernel.h> | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/pci.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/workqueue.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/device.h> | |
17 | ||
18 | #include <pcmcia/cs_types.h> | |
19 | #include <pcmcia/ss.h> | |
20 | #include <pcmcia/cs.h> | |
21 | ||
22 | #include <asm/system.h> | |
23 | #include <asm/io.h> | |
24 | ||
25 | #include "i82092aa.h" | |
26 | #include "i82365.h" | |
27 | ||
28 | MODULE_LICENSE("GPL"); | |
29 | ||
30 | /* PCI core routines */ | |
31 | static struct pci_device_id i82092aa_pci_ids[] = { | |
32 | { | |
33 | .vendor = PCI_VENDOR_ID_INTEL, | |
34 | .device = PCI_DEVICE_ID_INTEL_82092AA_0, | |
35 | .subvendor = PCI_ANY_ID, | |
36 | .subdevice = PCI_ANY_ID, | |
37 | }, | |
38 | {} | |
39 | }; | |
40 | MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); | |
41 | ||
f237de58 | 42 | #ifdef CONFIG_PM |
1da177e4 LT |
43 | static int i82092aa_socket_suspend (struct pci_dev *dev, pm_message_t state) |
44 | { | |
827b4649 | 45 | return pcmcia_socket_dev_suspend(&dev->dev); |
1da177e4 LT |
46 | } |
47 | ||
48 | static int i82092aa_socket_resume (struct pci_dev *dev) | |
49 | { | |
50 | return pcmcia_socket_dev_resume(&dev->dev); | |
51 | } | |
f237de58 | 52 | #endif |
1da177e4 | 53 | |
ba66ddfa | 54 | static struct pci_driver i82092aa_pci_driver = { |
1da177e4 LT |
55 | .name = "i82092aa", |
56 | .id_table = i82092aa_pci_ids, | |
57 | .probe = i82092aa_pci_probe, | |
58 | .remove = __devexit_p(i82092aa_pci_remove), | |
f237de58 | 59 | #ifdef CONFIG_PM |
1da177e4 LT |
60 | .suspend = i82092aa_socket_suspend, |
61 | .resume = i82092aa_socket_resume, | |
f237de58 | 62 | #endif |
1da177e4 LT |
63 | }; |
64 | ||
65 | ||
66 | /* the pccard structure and its functions */ | |
67 | static struct pccard_operations i82092aa_operations = { | |
68 | .init = i82092aa_init, | |
69 | .get_status = i82092aa_get_status, | |
1da177e4 LT |
70 | .set_socket = i82092aa_set_socket, |
71 | .set_io_map = i82092aa_set_io_map, | |
72 | .set_mem_map = i82092aa_set_mem_map, | |
73 | }; | |
74 | ||
75 | /* The card can do upto 4 sockets, allocate a structure for each of them */ | |
76 | ||
77 | struct socket_info { | |
78 | int number; | |
79 | int card_state; /* 0 = no socket, | |
80 | 1 = empty socket, | |
81 | 2 = card but not initialized, | |
82 | 3 = operational card */ | |
906da809 | 83 | unsigned int io_base; /* base io address of the socket */ |
1da177e4 LT |
84 | |
85 | struct pcmcia_socket socket; | |
86 | struct pci_dev *dev; /* The PCI device for the socket */ | |
87 | }; | |
88 | ||
89 | #define MAX_SOCKETS 4 | |
90 | static struct socket_info sockets[MAX_SOCKETS]; | |
91 | static int socket_count; /* shortcut */ | |
92 | ||
93 | ||
94 | static int __devinit i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
95 | { | |
96 | unsigned char configbyte; | |
97 | int i, ret; | |
98 | ||
99 | enter("i82092aa_pci_probe"); | |
100 | ||
101 | if ((ret = pci_enable_device(dev))) | |
102 | return ret; | |
103 | ||
104 | pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */ | |
105 | switch(configbyte&6) { | |
106 | case 0: | |
107 | socket_count = 2; | |
108 | break; | |
109 | case 2: | |
110 | socket_count = 1; | |
111 | break; | |
112 | case 4: | |
113 | case 6: | |
114 | socket_count = 4; | |
115 | break; | |
116 | ||
117 | default: | |
118 | printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n"); | |
119 | ret = -EIO; | |
120 | goto err_out_disable; | |
121 | } | |
122 | printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count); | |
123 | ||
124 | if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) { | |
125 | ret = -EBUSY; | |
126 | goto err_out_disable; | |
127 | } | |
128 | ||
129 | for (i = 0;i<socket_count;i++) { | |
130 | sockets[i].card_state = 1; /* 1 = present but empty */ | |
131 | sockets[i].io_base = pci_resource_start(dev, 0); | |
132 | sockets[i].socket.features |= SS_CAP_PCCARD; | |
133 | sockets[i].socket.map_size = 0x1000; | |
134 | sockets[i].socket.irq_mask = 0; | |
135 | sockets[i].socket.pci_irq = dev->irq; | |
7a96e87d | 136 | sockets[i].socket.cb_dev = dev; |
1da177e4 LT |
137 | sockets[i].socket.owner = THIS_MODULE; |
138 | ||
139 | sockets[i].number = i; | |
140 | ||
141 | if (card_present(i)) { | |
142 | sockets[i].card_state = 3; | |
143 | dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i); | |
144 | } else { | |
145 | dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i); | |
146 | } | |
147 | } | |
148 | ||
149 | /* Now, specifiy that all interrupts are to be done as PCI interrupts */ | |
150 | configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */ | |
151 | pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */ | |
152 | ||
153 | /* Register the interrupt handler */ | |
154 | dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq); | |
dace1453 | 155 | if ((ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, "i82092aa", i82092aa_interrupt))) { |
1da177e4 LT |
156 | printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq); |
157 | goto err_out_free_res; | |
158 | } | |
159 | ||
160 | pci_set_drvdata(dev, &sockets[i].socket); | |
161 | ||
162 | for (i = 0; i<socket_count; i++) { | |
87373318 | 163 | sockets[i].socket.dev.parent = &dev->dev; |
1da177e4 LT |
164 | sockets[i].socket.ops = &i82092aa_operations; |
165 | sockets[i].socket.resource_ops = &pccard_nonstatic_ops; | |
166 | ret = pcmcia_register_socket(&sockets[i].socket); | |
167 | if (ret) { | |
168 | goto err_out_free_sockets; | |
169 | } | |
170 | } | |
171 | ||
172 | leave("i82092aa_pci_probe"); | |
173 | return 0; | |
174 | ||
175 | err_out_free_sockets: | |
176 | if (i) { | |
177 | for (i--;i>=0;i--) { | |
178 | pcmcia_unregister_socket(&sockets[i].socket); | |
179 | } | |
180 | } | |
181 | free_irq(dev->irq, i82092aa_interrupt); | |
182 | err_out_free_res: | |
183 | release_region(pci_resource_start(dev, 0), 2); | |
184 | err_out_disable: | |
185 | pci_disable_device(dev); | |
186 | return ret; | |
187 | } | |
188 | ||
189 | static void __devexit i82092aa_pci_remove(struct pci_dev *dev) | |
190 | { | |
191 | struct pcmcia_socket *socket = pci_get_drvdata(dev); | |
192 | ||
193 | enter("i82092aa_pci_remove"); | |
194 | ||
195 | free_irq(dev->irq, i82092aa_interrupt); | |
196 | ||
197 | if (socket) | |
198 | pcmcia_unregister_socket(socket); | |
199 | ||
200 | leave("i82092aa_pci_remove"); | |
201 | } | |
202 | ||
203 | static DEFINE_SPINLOCK(port_lock); | |
204 | ||
205 | /* basic value read/write functions */ | |
206 | ||
207 | static unsigned char indirect_read(int socket, unsigned short reg) | |
208 | { | |
209 | unsigned short int port; | |
210 | unsigned char val; | |
211 | unsigned long flags; | |
212 | spin_lock_irqsave(&port_lock,flags); | |
213 | reg += socket * 0x40; | |
214 | port = sockets[socket].io_base; | |
215 | outb(reg,port); | |
216 | val = inb(port+1); | |
217 | spin_unlock_irqrestore(&port_lock,flags); | |
218 | return val; | |
219 | } | |
220 | ||
221 | #if 0 | |
222 | static unsigned short indirect_read16(int socket, unsigned short reg) | |
223 | { | |
224 | unsigned short int port; | |
225 | unsigned short tmp; | |
226 | unsigned long flags; | |
227 | spin_lock_irqsave(&port_lock,flags); | |
228 | reg = reg + socket * 0x40; | |
229 | port = sockets[socket].io_base; | |
230 | outb(reg,port); | |
231 | tmp = inb(port+1); | |
232 | reg++; | |
233 | outb(reg,port); | |
234 | tmp = tmp | (inb(port+1)<<8); | |
235 | spin_unlock_irqrestore(&port_lock,flags); | |
236 | return tmp; | |
237 | } | |
238 | #endif | |
239 | ||
240 | static void indirect_write(int socket, unsigned short reg, unsigned char value) | |
241 | { | |
242 | unsigned short int port; | |
243 | unsigned long flags; | |
244 | spin_lock_irqsave(&port_lock,flags); | |
245 | reg = reg + socket * 0x40; | |
246 | port = sockets[socket].io_base; | |
247 | outb(reg,port); | |
248 | outb(value,port+1); | |
249 | spin_unlock_irqrestore(&port_lock,flags); | |
250 | } | |
251 | ||
252 | static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) | |
253 | { | |
254 | unsigned short int port; | |
255 | unsigned char val; | |
256 | unsigned long flags; | |
257 | spin_lock_irqsave(&port_lock,flags); | |
258 | reg = reg + socket * 0x40; | |
259 | port = sockets[socket].io_base; | |
260 | outb(reg,port); | |
261 | val = inb(port+1); | |
262 | val |= mask; | |
263 | outb(reg,port); | |
264 | outb(val,port+1); | |
265 | spin_unlock_irqrestore(&port_lock,flags); | |
266 | } | |
267 | ||
268 | ||
269 | static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask) | |
270 | { | |
271 | unsigned short int port; | |
272 | unsigned char val; | |
273 | unsigned long flags; | |
274 | spin_lock_irqsave(&port_lock,flags); | |
275 | reg = reg + socket * 0x40; | |
276 | port = sockets[socket].io_base; | |
277 | outb(reg,port); | |
278 | val = inb(port+1); | |
279 | val &= ~mask; | |
280 | outb(reg,port); | |
281 | outb(val,port+1); | |
282 | spin_unlock_irqrestore(&port_lock,flags); | |
283 | } | |
284 | ||
285 | static void indirect_write16(int socket, unsigned short reg, unsigned short value) | |
286 | { | |
287 | unsigned short int port; | |
288 | unsigned char val; | |
289 | unsigned long flags; | |
290 | spin_lock_irqsave(&port_lock,flags); | |
291 | reg = reg + socket * 0x40; | |
292 | port = sockets[socket].io_base; | |
293 | ||
294 | outb(reg,port); | |
295 | val = value & 255; | |
296 | outb(val,port+1); | |
297 | ||
298 | reg++; | |
299 | ||
300 | outb(reg,port); | |
301 | val = value>>8; | |
302 | outb(val,port+1); | |
303 | spin_unlock_irqrestore(&port_lock,flags); | |
304 | } | |
305 | ||
306 | /* simple helper functions */ | |
307 | /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ | |
308 | static int cycle_time = 120; | |
309 | ||
310 | static int to_cycles(int ns) | |
311 | { | |
312 | if (cycle_time!=0) | |
313 | return ns/cycle_time; | |
314 | else | |
315 | return 0; | |
316 | } | |
317 | ||
318 | ||
319 | /* Interrupt handler functionality */ | |
320 | ||
7d12e780 | 321 | static irqreturn_t i82092aa_interrupt(int irq, void *dev) |
1da177e4 LT |
322 | { |
323 | int i; | |
324 | int loopcount = 0; | |
325 | int handled = 0; | |
326 | ||
327 | unsigned int events, active=0; | |
328 | ||
329 | /* enter("i82092aa_interrupt");*/ | |
330 | ||
331 | while (1) { | |
332 | loopcount++; | |
333 | if (loopcount>20) { | |
334 | printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n"); | |
335 | break; | |
336 | } | |
337 | ||
338 | active = 0; | |
339 | ||
340 | for (i=0;i<socket_count;i++) { | |
341 | int csc; | |
342 | if (sockets[i].card_state==0) /* Inactive socket, should not happen */ | |
343 | continue; | |
344 | ||
345 | csc = indirect_read(i,I365_CSC); /* card status change register */ | |
346 | ||
347 | if (csc==0) /* no events on this socket */ | |
348 | continue; | |
349 | handled = 1; | |
350 | events = 0; | |
351 | ||
352 | if (csc & I365_CSC_DETECT) { | |
353 | events |= SS_DETECT; | |
354 | printk("Card detected in socket %i!\n",i); | |
355 | } | |
356 | ||
357 | if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) { | |
358 | /* For IO/CARDS, bit 0 means "read the card" */ | |
359 | events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; | |
360 | } else { | |
361 | /* Check for battery/ready events */ | |
362 | events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; | |
363 | events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; | |
364 | events |= (csc & I365_CSC_READY) ? SS_READY : 0; | |
365 | } | |
366 | ||
367 | if (events) { | |
368 | pcmcia_parse_events(&sockets[i].socket, events); | |
369 | } | |
370 | active |= events; | |
371 | } | |
372 | ||
373 | if (active==0) /* no more events to handle */ | |
374 | break; | |
375 | ||
376 | } | |
377 | return IRQ_RETVAL(handled); | |
378 | /* leave("i82092aa_interrupt");*/ | |
379 | } | |
380 | ||
381 | ||
382 | ||
383 | /* socket functions */ | |
384 | ||
385 | static int card_present(int socketno) | |
386 | { | |
387 | unsigned int val; | |
388 | enter("card_present"); | |
389 | ||
390 | if ((socketno<0) || (socketno >= MAX_SOCKETS)) | |
391 | return 0; | |
392 | if (sockets[socketno].io_base == 0) | |
393 | return 0; | |
394 | ||
395 | ||
396 | val = indirect_read(socketno, 1); /* Interface status register */ | |
397 | if ((val&12)==12) { | |
398 | leave("card_present 1"); | |
399 | return 1; | |
400 | } | |
401 | ||
402 | leave("card_present 0"); | |
403 | return 0; | |
404 | } | |
405 | ||
406 | static void set_bridge_state(int sock) | |
407 | { | |
408 | enter("set_bridge_state"); | |
409 | indirect_write(sock, I365_GBLCTL,0x00); | |
410 | indirect_write(sock, I365_GENCTL,0x00); | |
411 | ||
412 | indirect_setbit(sock, I365_INTCTL,0x08); | |
413 | leave("set_bridge_state"); | |
414 | } | |
415 | ||
416 | ||
417 | ||
418 | ||
419 | ||
420 | ||
421 | static int i82092aa_init(struct pcmcia_socket *sock) | |
422 | { | |
423 | int i; | |
424 | struct resource res = { .start = 0, .end = 0x0fff }; | |
425 | pccard_io_map io = { 0, 0, 0, 0, 1 }; | |
426 | pccard_mem_map mem = { .res = &res, }; | |
427 | ||
428 | enter("i82092aa_init"); | |
429 | ||
430 | for (i = 0; i < 2; i++) { | |
431 | io.map = i; | |
432 | i82092aa_set_io_map(sock, &io); | |
433 | } | |
434 | for (i = 0; i < 5; i++) { | |
435 | mem.map = i; | |
436 | i82092aa_set_mem_map(sock, &mem); | |
437 | } | |
438 | ||
439 | leave("i82092aa_init"); | |
440 | return 0; | |
441 | } | |
442 | ||
443 | static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) | |
444 | { | |
445 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
446 | unsigned int status; | |
447 | ||
448 | enter("i82092aa_get_status"); | |
449 | ||
450 | status = indirect_read(sock,I365_STATUS); /* Interface Status Register */ | |
451 | *value = 0; | |
452 | ||
453 | if ((status & I365_CS_DETECT) == I365_CS_DETECT) { | |
454 | *value |= SS_DETECT; | |
455 | } | |
456 | ||
457 | /* IO cards have a different meaning of bits 0,1 */ | |
458 | /* Also notice the inverse-logic on the bits */ | |
459 | if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) { | |
460 | /* IO card */ | |
461 | if (!(status & I365_CS_STSCHG)) | |
462 | *value |= SS_STSCHG; | |
463 | } else { /* non I/O card */ | |
464 | if (!(status & I365_CS_BVD1)) | |
465 | *value |= SS_BATDEAD; | |
466 | if (!(status & I365_CS_BVD2)) | |
467 | *value |= SS_BATWARN; | |
468 | ||
469 | } | |
470 | ||
471 | if (status & I365_CS_WRPROT) | |
472 | (*value) |= SS_WRPROT; /* card is write protected */ | |
473 | ||
474 | if (status & I365_CS_READY) | |
475 | (*value) |= SS_READY; /* card is not busy */ | |
476 | ||
477 | if (status & I365_CS_POWERON) | |
478 | (*value) |= SS_POWERON; /* power is applied to the card */ | |
479 | ||
480 | ||
481 | leave("i82092aa_get_status"); | |
482 | return 0; | |
483 | } | |
484 | ||
485 | ||
1da177e4 LT |
486 | static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state) |
487 | { | |
488 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
489 | unsigned char reg; | |
490 | ||
491 | enter("i82092aa_set_socket"); | |
492 | ||
493 | /* First, set the global controller options */ | |
494 | ||
495 | set_bridge_state(sock); | |
496 | ||
497 | /* Values for the IGENC register */ | |
498 | ||
499 | reg = 0; | |
500 | if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */ | |
501 | reg = reg | I365_PC_RESET; | |
502 | if (state->flags & SS_IOCARD) | |
503 | reg = reg | I365_PC_IOCARD; | |
504 | ||
505 | indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */ | |
506 | ||
507 | /* Power registers */ | |
508 | ||
509 | reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ | |
510 | ||
511 | if (state->flags & SS_PWR_AUTO) { | |
512 | printk("Auto power\n"); | |
513 | reg |= I365_PWR_AUTO; /* automatic power mngmnt */ | |
514 | } | |
515 | if (state->flags & SS_OUTPUT_ENA) { | |
516 | printk("Power Enabled \n"); | |
517 | reg |= I365_PWR_OUT; /* enable power */ | |
518 | } | |
519 | ||
520 | switch (state->Vcc) { | |
521 | case 0: | |
522 | break; | |
523 | case 50: | |
524 | printk("setting voltage to Vcc to 5V on socket %i\n",sock); | |
525 | reg |= I365_VCC_5V; | |
526 | break; | |
527 | default: | |
528 | printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc); | |
529 | leave("i82092aa_set_socket"); | |
530 | return -EINVAL; | |
531 | } | |
532 | ||
533 | ||
534 | switch (state->Vpp) { | |
535 | case 0: | |
536 | printk("not setting Vpp on socket %i\n",sock); | |
537 | break; | |
538 | case 50: | |
539 | printk("setting Vpp to 5.0 for socket %i\n",sock); | |
540 | reg |= I365_VPP1_5V | I365_VPP2_5V; | |
541 | break; | |
542 | case 120: | |
543 | printk("setting Vpp to 12.0\n"); | |
544 | reg |= I365_VPP1_12V | I365_VPP2_12V; | |
545 | break; | |
546 | default: | |
547 | printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc); | |
548 | leave("i82092aa_set_socket"); | |
549 | return -EINVAL; | |
550 | } | |
551 | ||
552 | if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */ | |
553 | indirect_write(sock,I365_POWER,reg); | |
554 | ||
555 | /* Enable specific interrupt events */ | |
556 | ||
557 | reg = 0x00; | |
558 | if (state->csc_mask & SS_DETECT) { | |
559 | reg |= I365_CSC_DETECT; | |
560 | } | |
561 | if (state->flags & SS_IOCARD) { | |
562 | if (state->csc_mask & SS_STSCHG) | |
563 | reg |= I365_CSC_STSCHG; | |
564 | } else { | |
565 | if (state->csc_mask & SS_BATDEAD) | |
566 | reg |= I365_CSC_BVD1; | |
567 | if (state->csc_mask & SS_BATWARN) | |
568 | reg |= I365_CSC_BVD2; | |
569 | if (state->csc_mask & SS_READY) | |
570 | reg |= I365_CSC_READY; | |
571 | ||
572 | } | |
573 | ||
574 | /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/ | |
575 | ||
576 | indirect_write(sock,I365_CSCINT,reg); | |
577 | (void)indirect_read(sock,I365_CSC); | |
578 | ||
579 | leave("i82092aa_set_socket"); | |
580 | return 0; | |
581 | } | |
582 | ||
583 | static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io) | |
584 | { | |
585 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
586 | unsigned char map, ioctl; | |
587 | ||
588 | enter("i82092aa_set_io_map"); | |
589 | ||
590 | map = io->map; | |
591 | ||
592 | /* Check error conditions */ | |
593 | if (map > 1) { | |
594 | leave("i82092aa_set_io_map with invalid map"); | |
595 | return -EINVAL; | |
596 | } | |
597 | if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){ | |
598 | leave("i82092aa_set_io_map with invalid io"); | |
599 | return -EINVAL; | |
600 | } | |
601 | ||
602 | /* Turn off the window before changing anything */ | |
603 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map)) | |
604 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); | |
605 | ||
606 | /* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */ | |
607 | ||
608 | /* write the new values */ | |
609 | indirect_write16(sock,I365_IO(map)+I365_W_START,io->start); | |
610 | indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop); | |
611 | ||
612 | ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map); | |
613 | ||
614 | if (io->flags & (MAP_16BIT|MAP_AUTOSZ)) | |
615 | ioctl |= I365_IOCTL_16BIT(map); | |
616 | ||
617 | indirect_write(sock,I365_IOCTL,ioctl); | |
618 | ||
619 | /* Turn the window back on if needed */ | |
620 | if (io->flags & MAP_ACTIVE) | |
621 | indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map)); | |
622 | ||
623 | leave("i82092aa_set_io_map"); | |
624 | return 0; | |
625 | } | |
626 | ||
627 | static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem) | |
628 | { | |
629 | struct socket_info *sock_info = container_of(socket, struct socket_info, socket); | |
630 | unsigned int sock = sock_info->number; | |
631 | struct pci_bus_region region; | |
632 | unsigned short base, i; | |
633 | unsigned char map; | |
634 | ||
635 | enter("i82092aa_set_mem_map"); | |
636 | ||
637 | pcibios_resource_to_bus(sock_info->dev, ®ion, mem->res); | |
638 | ||
639 | map = mem->map; | |
640 | if (map > 4) { | |
641 | leave("i82092aa_set_mem_map: invalid map"); | |
642 | return -EINVAL; | |
643 | } | |
644 | ||
645 | ||
646 | if ( (mem->card_start > 0x3ffffff) || (region.start > region.end) || | |
647 | (mem->speed > 1000) ) { | |
648 | leave("i82092aa_set_mem_map: invalid address / speed"); | |
f96ee7a4 AM |
649 | printk("invalid mem map for socket %i: %llx to %llx with a " |
650 | "start of %x\n", | |
651 | sock, | |
652 | (unsigned long long)region.start, | |
653 | (unsigned long long)region.end, | |
654 | mem->card_start); | |
1da177e4 LT |
655 | return -EINVAL; |
656 | } | |
657 | ||
658 | /* Turn off the window before changing anything */ | |
659 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) | |
660 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); | |
661 | ||
662 | ||
663 | /* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, region.start,region.end,sock,mem->speed,mem->flags & MAP_ACTIVE); */ | |
664 | ||
665 | /* write the start address */ | |
666 | base = I365_MEM(map); | |
667 | i = (region.start >> 12) & 0x0fff; | |
668 | if (mem->flags & MAP_16BIT) | |
669 | i |= I365_MEM_16BIT; | |
670 | if (mem->flags & MAP_0WS) | |
671 | i |= I365_MEM_0WS; | |
672 | indirect_write16(sock,base+I365_W_START,i); | |
673 | ||
674 | /* write the stop address */ | |
675 | ||
676 | i= (region.end >> 12) & 0x0fff; | |
677 | switch (to_cycles(mem->speed)) { | |
678 | case 0: | |
679 | break; | |
680 | case 1: | |
681 | i |= I365_MEM_WS0; | |
682 | break; | |
683 | case 2: | |
684 | i |= I365_MEM_WS1; | |
685 | break; | |
686 | default: | |
687 | i |= I365_MEM_WS1 | I365_MEM_WS0; | |
688 | break; | |
689 | } | |
690 | ||
691 | indirect_write16(sock,base+I365_W_STOP,i); | |
692 | ||
693 | /* card start */ | |
694 | ||
695 | i = ((mem->card_start - region.start) >> 12) & 0x3fff; | |
696 | if (mem->flags & MAP_WRPROT) | |
697 | i |= I365_MEM_WRPROT; | |
698 | if (mem->flags & MAP_ATTRIB) { | |
699 | /* printk("requesting attribute memory for socket %i\n",sock);*/ | |
700 | i |= I365_MEM_REG; | |
701 | } else { | |
702 | /* printk("requesting normal memory for socket %i\n",sock);*/ | |
703 | } | |
704 | indirect_write16(sock,base+I365_W_OFF,i); | |
705 | ||
706 | /* Enable the window if necessary */ | |
707 | if (mem->flags & MAP_ACTIVE) | |
708 | indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); | |
709 | ||
710 | leave("i82092aa_set_mem_map"); | |
711 | return 0; | |
712 | } | |
713 | ||
714 | static int i82092aa_module_init(void) | |
715 | { | |
ba66ddfa | 716 | return pci_register_driver(&i82092aa_pci_driver); |
1da177e4 LT |
717 | } |
718 | ||
719 | static void i82092aa_module_exit(void) | |
720 | { | |
721 | enter("i82092aa_module_exit"); | |
ba66ddfa | 722 | pci_unregister_driver(&i82092aa_pci_driver); |
1da177e4 LT |
723 | if (sockets[0].io_base>0) |
724 | release_region(sockets[0].io_base, 2); | |
725 | leave("i82092aa_module_exit"); | |
726 | } | |
727 | ||
728 | module_init(i82092aa_module_init); | |
729 | module_exit(i82092aa_module_exit); | |
730 |