[linux-2.6-block.git] / drivers / pci / proc.c

/*
 *	Procfs interface for the PCI bus.
 *
 *	Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
 */

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/capability.h>
#include <asm/uaccess.h>
#include <asm/byteorder.h>
#include "pci.h"

static int proc_initialized;	/* = 0 */

static loff_t
proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
{
	loff_t new = -1;
	struct inode *inode = file_inode(file);

	mutex_lock(&inode->i_mutex);
	switch (whence) {
	case 0:
		new = off;
		break;
	case 1:
		new = file->f_pos + off;
		break;
	case 2:
		new = inode->i_size + off;
		break;
	}
	if (new < 0 || new > inode->i_size)
		new = -EINVAL;
	else
		file->f_pos = new;
	mutex_unlock(&inode->i_mutex);
	return new;
}

static ssize_t
proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
{
	const struct inode *ino = file_inode(file);
	const struct proc_dir_entry *dp = PDE(ino);
	struct pci_dev *dev = dp->data;
	unsigned int pos = *ppos;
	unsigned int cnt, size;

	/*
	 * Normal users can read only the standardized portion of the
	 * configuration space as several chips lock up when trying to read
	 * undefined locations (think of Intel PIIX4 as a typical example).
	 */

	if (capable(CAP_SYS_ADMIN))
		size = dp->size;
	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
		size = 128;
	else
		size = 64;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_WRITE, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		unsigned int val;
		pci_user_read_config_dword(dev, pos, &val);
		__put_user(cpu_to_le32(val), (__le32 __user *) buf);
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	return nbytes;
}

static ssize_t
proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, loff_t *ppos)
{
	struct inode *ino = file_inode(file);
	const struct proc_dir_entry *dp = PDE(ino);
	struct pci_dev *dev = dp->data;
	int pos = *ppos;
	int size = dp->size;
	int cnt;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_READ, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		__le32 val;
		__get_user(val, (__le32 __user *) buf);
		pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	i_size_write(ino, dp->size);
	return nbytes;
}

struct pci_filp_private {
	enum pci_mmap_state mmap_state;
	int write_combine;
};

static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
			       unsigned long arg)
{
	const struct proc_dir_entry *dp = PDE(file_inode(file));
	struct pci_dev *dev = dp->data;
#ifdef HAVE_PCI_MMAP
	struct pci_filp_private *fpriv = file->private_data;
#endif /* HAVE_PCI_MMAP */
	int ret = 0;

	switch (cmd) {
	case PCIIOC_CONTROLLER:
		ret = pci_domain_nr(dev->bus);
		break;

#ifdef HAVE_PCI_MMAP
	case PCIIOC_MMAP_IS_IO:
		fpriv->mmap_state = pci_mmap_io;
		break;

	case PCIIOC_MMAP_IS_MEM:
		fpriv->mmap_state = pci_mmap_mem;
		break;

	case PCIIOC_WRITE_COMBINE:
		if (arg)
			fpriv->write_combine = 1;
		else
			fpriv->write_combine = 0;
		break;

#endif /* HAVE_PCI_MMAP */

	default:
		ret = -EINVAL;
		break;
	};

	return ret;
}

#ifdef HAVE_PCI_MMAP
static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
{
	struct inode *inode = file_inode(file);
	const struct proc_dir_entry *dp = PDE(inode);
	struct pci_dev *dev = dp->data;
	struct pci_filp_private *fpriv = file->private_data;
	int i, ret;

	if (!capable(CAP_SYS_RAWIO))
		return -EPERM;

	/* Make sure the caller is mapping a real resource for this device */
	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
		if (pci_mmap_fits(dev, i, vma,  PCI_MMAP_PROCFS))
			break;
	}

	if (i >= PCI_ROM_RESOURCE)
		return -ENODEV;

	ret = pci_mmap_page_range(dev, vma,
				  fpriv->mmap_state,
				  fpriv->write_combine);
	if (ret < 0)
		return ret;

	return 0;
}

static int proc_bus_pci_open(struct inode *inode, struct file *file)
{
	struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);

	if (!fpriv)
		return -ENOMEM;

	fpriv->mmap_state = pci_mmap_io;
	fpriv->write_combine = 0;

	file->private_data = fpriv;

	return 0;
}

static int proc_bus_pci_release(struct inode *inode, struct file *file)
{
	kfree(file->private_data);
	file->private_data = NULL;

	return 0;
}
#endif /* HAVE_PCI_MMAP */

static const struct file_operations proc_bus_pci_operations = {
	.owner		= THIS_MODULE,
	.llseek		= proc_bus_pci_lseek,
	.read		= proc_bus_pci_read,
	.write		= proc_bus_pci_write,
	.unlocked_ioctl	= proc_bus_pci_ioctl,
	.compat_ioctl	= proc_bus_pci_ioctl,
#ifdef HAVE_PCI_MMAP
	.open		= proc_bus_pci_open,
	.release	= proc_bus_pci_release,
	.mmap		= proc_bus_pci_mmap,
#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	.get_unmapped_area = get_pci_unmapped_area,
#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
#endif /* HAVE_PCI_MMAP */
};

/* iterator */
static void *pci_seq_start(struct seq_file *m, loff_t *pos)
{
	struct pci_dev *dev = NULL;
	loff_t n = *pos;

	for_each_pci_dev(dev) {
		if (!n--)
			break;
	}
	return dev;
}

static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
{
	struct pci_dev *dev = v;

	(*pos)++;
	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	return dev;
}

static void pci_seq_stop(struct seq_file *m, void *v)
{
	if (v) {
		struct pci_dev *dev = v;
		pci_dev_put(dev);
	}
}

static int show_device(struct seq_file *m, void *v)
{
	const struct pci_dev *dev = v;
	const struct pci_driver *drv;
	int i;

	if (dev == NULL)
		return 0;

	drv = pci_dev_driver(dev);
	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
			dev->bus->number,
			dev->devfn,
			dev->vendor,
			dev->device,
			dev->irq);

	/* only print standard and ROM resources to preserve compatibility */
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			(unsigned long long)(start |
			(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
	}
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			dev->resource[i].start < dev->resource[i].end ?
			(unsigned long long)(end - start) + 1 : 0);
	}
	seq_putc(m, '\t');
	if (drv)
		seq_printf(m, "%s", drv->name);
	seq_putc(m, '\n');
	return 0;
}

static const struct seq_operations proc_bus_pci_devices_op = {
	.start	= pci_seq_start,
	.next	= pci_seq_next,
	.stop	= pci_seq_stop,
	.show	= show_device
};

static struct proc_dir_entry *proc_bus_pci_dir;

int pci_proc_attach_device(struct pci_dev *dev)
{
	struct pci_bus *bus = dev->bus;
	struct proc_dir_entry *e;
	char name[16];

	if (!proc_initialized)
		return -EACCES;

	if (!bus->procdir) {
		if (pci_proc_domain(bus)) {
			sprintf(name, "%04x:%02x", pci_domain_nr(bus),
					bus->number);
		} else {
			sprintf(name, "%02x", bus->number);
		}
		bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
		if (!bus->procdir)
			return -ENOMEM;
	}

	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
			     &proc_bus_pci_operations, dev);
	if (!e)
		return -ENOMEM;
	e->size = dev->cfg_size;
	dev->procent = e;

	return 0;
}

int pci_proc_detach_device(struct pci_dev *dev)
{
	struct proc_dir_entry *e;

	if ((e = dev->procent)) {
		remove_proc_entry(e->name, dev->bus->procdir);
		dev->procent = NULL;
	}
	return 0;
}

int pci_proc_detach_bus(struct pci_bus* bus)
{
	struct proc_dir_entry *de = bus->procdir;
	if (de)
		remove_proc_entry(de->name, proc_bus_pci_dir);
	return 0;
}

static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
{
	return seq_open(file, &proc_bus_pci_devices_op);
}
static const struct file_operations proc_bus_pci_dev_operations = {
	.owner		= THIS_MODULE,
	.open		= proc_bus_pci_dev_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= seq_release,
};

static int __init pci_proc_init(void)
{
	struct pci_dev *dev = NULL;
	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
	proc_create("devices", 0, proc_bus_pci_dir,
		    &proc_bus_pci_dev_operations);
	proc_initialized = 1;
	for_each_pci_dev(dev)
		pci_proc_attach_device(dev);

	return 0;
}

device_initcall(pci_proc_init);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Procfs interface for the PCI bus.
	3	*
	4	* Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#include <linux/init.h>
	8	#include <linux/pci.h>
5a0e3ad6	9	#include <linux/slab.h>
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/proc_fs.h>
	12	#include <linux/seq_file.h>
aa0ac365	13	#include <linux/capability.h>
1da177e4 LT	14	#include <asm/uaccess.h>
1da177e4 LT	15	#include <asm/byteorder.h>
bc56b9e0	16	#include "pci.h"
1da177e4 LT	17
	18	static int proc_initialized; /* = 0 */
	19
	20	static loff_t
	21	proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
	22	{
	23	loff_t new = -1;
496ad9aa	24	struct inode *inode = file_inode(file);
1da177e4	25
1b1dcc1b	26	mutex_lock(&inode->i_mutex);
1da177e4 LT	27	switch (whence) {
	28	case 0:
	29	new = off;
	30	break;
	31	case 1:
	32	new = file->f_pos + off;
	33	break;
	34	case 2:
	35	new = inode->i_size + off;
	36	break;
	37	}
	38	if (new < 0 \|\| new > inode->i_size)
	39	new = -EINVAL;
	40	else
	41	file->f_pos = new;
1b1dcc1b	42	mutex_unlock(&inode->i_mutex);
1da177e4 LT	43	return new;
	44	}
	45
	46	static ssize_t
	47	proc_bus_pci_read(struct file file, char __user buf, size_t nbytes, loff_t *ppos)
	48	{
496ad9aa	49	const struct inode *ino = file_inode(file);
1da177e4 LT	50	const struct proc_dir_entry *dp = PDE(ino);
	51	struct pci_dev *dev = dp->data;
	52	unsigned int pos = *ppos;
	53	unsigned int cnt, size;
	54
	55	/*
	56	* Normal users can read only the standardized portion of the
	57	* configuration space as several chips lock up when trying to read
	58	* undefined locations (think of Intel PIIX4 as a typical example).
	59	*/
	60
	61	if (capable(CAP_SYS_ADMIN))
cd68602f	62	size = dp->size;
1da177e4 LT	63	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
	64	size = 128;
	65	else
	66	size = 64;
	67
	68	if (pos >= size)
	69	return 0;
	70	if (nbytes >= size)
	71	nbytes = size;
	72	if (pos + nbytes > size)
	73	nbytes = size - pos;
	74	cnt = nbytes;
	75
	76	if (!access_ok(VERIFY_WRITE, buf, cnt))
	77	return -EINVAL;
	78
b3c32c4f HY	79	pci_config_pm_runtime_get(dev);
b3c32c4f HY	80
1da177e4 LT	81	if ((pos & 1) && cnt) {
1da177e4 LT	82	unsigned char val;
e04b0ea2	83	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	84	__put_user(val, buf);
	85	buf++;
	86	pos++;
	87	cnt--;
	88	}
	89
	90	if ((pos & 3) && cnt > 2) {
	91	unsigned short val;
e04b0ea2	92	pci_user_read_config_word(dev, pos, &val);
f17a077e	93	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	94	buf += 2;
	95	pos += 2;
	96	cnt -= 2;
	97	}
	98
	99	while (cnt >= 4) {
	100	unsigned int val;
e04b0ea2	101	pci_user_read_config_dword(dev, pos, &val);
f17a077e	102	__put_user(cpu_to_le32(val), (__le32 __user *) buf);
1da177e4 LT	103	buf += 4;
	104	pos += 4;
	105	cnt -= 4;
	106	}
	107
	108	if (cnt >= 2) {
	109	unsigned short val;
e04b0ea2	110	pci_user_read_config_word(dev, pos, &val);
f17a077e	111	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	112	buf += 2;
	113	pos += 2;
	114	cnt -= 2;
	115	}
	116
	117	if (cnt) {
	118	unsigned char val;
e04b0ea2	119	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	120	__put_user(val, buf);
	121	buf++;
	122	pos++;
	123	cnt--;
	124	}
	125
b3c32c4f HY	126	pci_config_pm_runtime_put(dev);
b3c32c4f HY	127
1da177e4 LT	128	*ppos = pos;
	129	return nbytes;
	130	}
	131
	132	static ssize_t
	133	proc_bus_pci_write(struct file file, const char __user buf, size_t nbytes, loff_t *ppos)
	134	{
496ad9aa	135	struct inode *ino = file_inode(file);
1da177e4 LT	136	const struct proc_dir_entry *dp = PDE(ino);
	137	struct pci_dev *dev = dp->data;
	138	int pos = *ppos;
cd68602f	139	int size = dp->size;
1da177e4 LT	140	int cnt;
	141
	142	if (pos >= size)
	143	return 0;
	144	if (nbytes >= size)
	145	nbytes = size;
	146	if (pos + nbytes > size)
	147	nbytes = size - pos;
	148	cnt = nbytes;
	149
	150	if (!access_ok(VERIFY_READ, buf, cnt))
	151	return -EINVAL;
	152
b3c32c4f HY	153	pci_config_pm_runtime_get(dev);
b3c32c4f HY	154
1da177e4 LT	155	if ((pos & 1) && cnt) {
	156	unsigned char val;
	157	__get_user(val, buf);
e04b0ea2	158	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	159	buf++;
	160	pos++;
	161	cnt--;
	162	}
	163
	164	if ((pos & 3) && cnt > 2) {
f17a077e HH	165	__le16 val;
f17a077e HH	166	__get_user(val, (__le16 __user *) buf);
e04b0ea2	167	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	168	buf += 2;
	169	pos += 2;
	170	cnt -= 2;
	171	}
	172
	173	while (cnt >= 4) {
f17a077e HH	174	__le32 val;
f17a077e HH	175	__get_user(val, (__le32 __user *) buf);
e04b0ea2	176	pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
1da177e4 LT	177	buf += 4;
	178	pos += 4;
	179	cnt -= 4;
	180	}
	181
	182	if (cnt >= 2) {
f17a077e HH	183	__le16 val;
f17a077e HH	184	__get_user(val, (__le16 __user *) buf);
e04b0ea2	185	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	186	buf += 2;
	187	pos += 2;
	188	cnt -= 2;
	189	}
	190
	191	if (cnt) {
	192	unsigned char val;
	193	__get_user(val, buf);
e04b0ea2	194	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	195	buf++;
	196	pos++;
	197	cnt--;
	198	}
	199
b3c32c4f HY	200	pci_config_pm_runtime_put(dev);
b3c32c4f HY	201
1da177e4	202	*ppos = pos;
ecb39080	203	i_size_write(ino, dp->size);
1da177e4 LT	204	return nbytes;
	205	}
	206
	207	struct pci_filp_private {
	208	enum pci_mmap_state mmap_state;
	209	int write_combine;
	210	};
	211
add77184 MS	212	static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
add77184 MS	213	unsigned long arg)
1da177e4	214	{
496ad9aa	215	const struct proc_dir_entry *dp = PDE(file_inode(file));
1da177e4 LT	216	struct pci_dev *dev = dp->data;
	217	#ifdef HAVE_PCI_MMAP
	218	struct pci_filp_private *fpriv = file->private_data;
	219	#endif /* HAVE_PCI_MMAP */
	220	int ret = 0;
	221
	222	switch (cmd) {
	223	case PCIIOC_CONTROLLER:
	224	ret = pci_domain_nr(dev->bus);
	225	break;
	226
	227	#ifdef HAVE_PCI_MMAP
	228	case PCIIOC_MMAP_IS_IO:
	229	fpriv->mmap_state = pci_mmap_io;
	230	break;
	231
	232	case PCIIOC_MMAP_IS_MEM:
	233	fpriv->mmap_state = pci_mmap_mem;
	234	break;
	235
	236	case PCIIOC_WRITE_COMBINE:
	237	if (arg)
	238	fpriv->write_combine = 1;
	239	else
	240	fpriv->write_combine = 0;
	241	break;
	242
	243	#endif /* HAVE_PCI_MMAP */
	244
	245	default:
	246	ret = -EINVAL;
	247	break;
	248	};
	249
	250	return ret;
	251	}
	252
	253	#ifdef HAVE_PCI_MMAP
	254	static int proc_bus_pci_mmap(struct file file, struct vm_area_struct vma)
	255	{
496ad9aa	256	struct inode *inode = file_inode(file);
1da177e4 LT	257	const struct proc_dir_entry *dp = PDE(inode);
	258	struct pci_dev *dev = dp->data;
	259	struct pci_filp_private *fpriv = file->private_data;
9eff02e2	260	int i, ret;
1da177e4 LT	261
	262	if (!capable(CAP_SYS_RAWIO))
	263	return -EPERM;
	264
9eff02e2 JB	265	/* Make sure the caller is mapping a real resource for this device */
9eff02e2 JB	266	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
3b519e4e	267	if (pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
9eff02e2 JB	268	break;
	269	}
	270
	271	if (i >= PCI_ROM_RESOURCE)
	272	return -ENODEV;
	273
1da177e4 LT	274	ret = pci_mmap_page_range(dev, vma,
	275	fpriv->mmap_state,
	276	fpriv->write_combine);
	277	if (ret < 0)
	278	return ret;
	279
	280	return 0;
	281	}
	282
	283	static int proc_bus_pci_open(struct inode inode, struct file file)
	284	{
	285	struct pci_filp_private fpriv = kmalloc(sizeof(fpriv), GFP_KERNEL);
	286
	287	if (!fpriv)
	288	return -ENOMEM;
	289
	290	fpriv->mmap_state = pci_mmap_io;
	291	fpriv->write_combine = 0;
	292
	293	file->private_data = fpriv;
	294
	295	return 0;
	296	}
	297
	298	static int proc_bus_pci_release(struct inode inode, struct file file)
	299	{
	300	kfree(file->private_data);
	301	file->private_data = NULL;
	302
	303	return 0;
	304	}
	305	#endif /* HAVE_PCI_MMAP */
	306
d54b1fdb	307	static const struct file_operations proc_bus_pci_operations = {
c7705f34	308	.owner = THIS_MODULE,
1da177e4 LT	309	.llseek = proc_bus_pci_lseek,
	310	.read = proc_bus_pci_read,
	311	.write = proc_bus_pci_write,
add77184	312	.unlocked_ioctl = proc_bus_pci_ioctl,
991f7395	313	.compat_ioctl = proc_bus_pci_ioctl,
1da177e4 LT	314	#ifdef HAVE_PCI_MMAP
	315	.open = proc_bus_pci_open,
	316	.release = proc_bus_pci_release,
	317	.mmap = proc_bus_pci_mmap,
	318	#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	319	.get_unmapped_area = get_pci_unmapped_area,
	320	#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
	321	#endif /* HAVE_PCI_MMAP */
	322	};
	323
1da177e4 LT	324	/* iterator */
	325	static void pci_seq_start(struct seq_file m, loff_t *pos)
	326	{
	327	struct pci_dev *dev = NULL;
	328	loff_t n = *pos;
	329
	330	for_each_pci_dev(dev) {
	331	if (!n--)
	332	break;
	333	}
	334	return dev;
	335	}
	336
	337	static void pci_seq_next(struct seq_file m, void v, loff_t pos)
	338	{
	339	struct pci_dev *dev = v;
	340
	341	(*pos)++;
	342	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	343	return dev;
	344	}
	345
	346	static void pci_seq_stop(struct seq_file m, void v)
	347	{
	348	if (v) {
	349	struct pci_dev *dev = v;
	350	pci_dev_put(dev);
	351	}
	352	}
	353
	354	static int show_device(struct seq_file m, void v)
	355	{
	356	const struct pci_dev *dev = v;
	357	const struct pci_driver *drv;
	358	int i;
	359
	360	if (dev == NULL)
	361	return 0;
	362
	363	drv = pci_dev_driver(dev);
	364	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
	365	dev->bus->number,
	366	dev->devfn,
	367	dev->vendor,
	368	dev->device,
	369	dev->irq);
fde09c6d YZ	370
	371	/* only print standard and ROM resources to preserve compatibility */
	372	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	373	resource_size_t start, end;
2311b1f2	374	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3 GKH	375	seq_printf(m, "\t%16llx",
	376	(unsigned long long)(start \|
	377	(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
2311b1f2	378	}
fde09c6d	379	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	380	resource_size_t start, end;
2311b1f2	381	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3	382	seq_printf(m, "\t%16llx",
1da177e4	383	dev->resource[i].start < dev->resource[i].end ?
1396a8c3	384	(unsigned long long)(end - start) + 1 : 0);
2311b1f2	385	}
1da177e4 LT	386	seq_putc(m, '\t');
	387	if (drv)
	388	seq_printf(m, "%s", drv->name);
	389	seq_putc(m, '\n');
	390	return 0;
	391	}
	392
02d90fc3	393	static const struct seq_operations proc_bus_pci_devices_op = {
1da177e4 LT	394	.start = pci_seq_start,
	395	.next = pci_seq_next,
	396	.stop = pci_seq_stop,
	397	.show = show_device
	398	};
	399
	400	static struct proc_dir_entry *proc_bus_pci_dir;
	401
	402	int pci_proc_attach_device(struct pci_dev *dev)
	403	{
	404	struct pci_bus *bus = dev->bus;
	405	struct proc_dir_entry *e;
	406	char name[16];
	407
	408	if (!proc_initialized)
	409	return -EACCES;
	410
	411	if (!bus->procdir) {
	412	if (pci_proc_domain(bus)) {
	413	sprintf(name, "%04x:%02x", pci_domain_nr(bus),
	414	bus->number);
	415	} else {
	416	sprintf(name, "%02x", bus->number);
	417	}
	418	bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
	419	if (!bus->procdir)
	420	return -ENOMEM;
	421	}
	422
	423	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
c7705f34 DL	424	e = proc_create_data(name, S_IFREG \| S_IRUGO \| S_IWUSR, bus->procdir,
c7705f34 DL	425	&proc_bus_pci_operations, dev);
1da177e4 LT	426	if (!e)
1da177e4 LT	427	return -ENOMEM;
1da177e4 LT	428	e->size = dev->cfg_size;
	429	dev->procent = e;
	430
	431	return 0;
	432	}
	433
	434	int pci_proc_detach_device(struct pci_dev *dev)
	435	{
	436	struct proc_dir_entry *e;
	437
	438	if ((e = dev->procent)) {
1da177e4 LT	439	remove_proc_entry(e->name, dev->bus->procdir);
	440	dev->procent = NULL;
	441	}
	442	return 0;
	443	}
	444
1da177e4 LT	445	int pci_proc_detach_bus(struct pci_bus* bus)
	446	{
	447	struct proc_dir_entry *de = bus->procdir;
	448	if (de)
	449	remove_proc_entry(de->name, proc_bus_pci_dir);
	450	return 0;
	451	}
	452
1da177e4 LT	453	static int proc_bus_pci_dev_open(struct inode inode, struct file file)
	454	{
	455	return seq_open(file, &proc_bus_pci_devices_op);
	456	}
d54b1fdb	457	static const struct file_operations proc_bus_pci_dev_operations = {
c7705f34	458	.owner = THIS_MODULE,
1da177e4 LT	459	.open = proc_bus_pci_dev_open,
	460	.read = seq_read,
	461	.llseek = seq_lseek,
	462	.release = seq_release,
	463	};
	464
	465	static int __init pci_proc_init(void)
	466	{
1da177e4	467	struct pci_dev *dev = NULL;
9c37066d	468	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
c7705f34 DL	469	proc_create("devices", 0, proc_bus_pci_dir,
c7705f34 DL	470	&proc_bus_pci_dev_operations);
1da177e4	471	proc_initialized = 1;
4e344b1c	472	for_each_pci_dev(dev)
1da177e4	473	pci_proc_attach_device(dev);
4e344b1c	474
1da177e4 LT	475	return 0;
	476	}
	477
eaf61142	478	device_initcall(pci_proc_init);
1da177e4	479