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Merge branch 'pm-cpufreq'
[linux-2.6-block.git] / drivers / pci / host / pcie-rcar.c
CommitLineData
c25da477
PE		 1/*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
290c1fb3
PE		 18#include <linux/irq.h>
19#include <linux/irqdomain.h>
c25da477
PE		 20#include <linux/kernel.h>
21#include <linux/module.h>
290c1fb3 22#include <linux/msi.h>
c25da477
PE		 23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/of_pci.h>
26#include <linux/of_platform.h>
27#include <linux/pci.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30
31#define DRV_NAME "rcar-pcie"
32
33#define PCIECAR 0x000010
34#define PCIECCTLR 0x000018
35#define CONFIG_SEND_ENABLE (1 << 31)
36#define TYPE0 (0 << 8)
37#define TYPE1 (1 << 8)
38#define PCIECDR 0x000020
39#define PCIEMSR 0x000028
40#define PCIEINTXR 0x000400
290c1fb3 41#define PCIEMSITXR 0x000840
c25da477
PE		 42
43/* Transfer control */
44#define PCIETCTLR 0x02000
45#define CFINIT 1
46#define PCIETSTR 0x02004
47#define DATA_LINK_ACTIVE 1
48#define PCIEERRFR 0x02020
49#define UNSUPPORTED_REQUEST (1 << 4)
290c1fb3
PE		 50#define PCIEMSIFR 0x02044
51#define PCIEMSIALR 0x02048
52#define MSIFE 1
53#define PCIEMSIAUR 0x0204c
54#define PCIEMSIIER 0x02050
c25da477
PE		 55
56/* root port address */
57#define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
58
59/* local address reg & mask */
60#define PCIELAR(x) (0x02200 + ((x) * 0x20))
61#define PCIELAMR(x) (0x02208 + ((x) * 0x20))
62#define LAM_PREFETCH (1 << 3)
63#define LAM_64BIT (1 << 2)
64#define LAR_ENABLE (1 << 1)
65
66/* PCIe address reg & mask */
ecd06305
NI		 67#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
68#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
c25da477
PE		 69#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
70#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
71#define PAR_ENABLE (1 << 31)
72#define IO_SPACE (1 << 8)
73
74/* Configuration */
75#define PCICONF(x) (0x010000 + ((x) * 0x4))
76#define PMCAP(x) (0x010040 + ((x) * 0x4))
77#define EXPCAP(x) (0x010070 + ((x) * 0x4))
78#define VCCAP(x) (0x010100 + ((x) * 0x4))
79
80/* link layer */
81#define IDSETR1 0x011004
82#define TLCTLR 0x011048
83#define MACSR 0x011054
84#define MACCTLR 0x011058
85#define SCRAMBLE_DISABLE (1 << 27)
86
87/* R-Car H1 PHY */
88#define H1_PCIEPHYADRR 0x04000c
89#define WRITE_CMD (1 << 16)
90#define PHY_ACK (1 << 24)
91#define RATE_POS 12
92#define LANE_POS 8
93#define ADR_POS 0
94#define H1_PCIEPHYDOUTR 0x040014
95#define H1_PCIEPHYSR 0x040018
96
290c1fb3
PE		 97#define INT_PCI_MSI_NR 32
98
c25da477
PE		 99#define RCONF(x) (PCICONF(0)+(x))
100#define RPMCAP(x) (PMCAP(0)+(x))
101#define REXPCAP(x) (EXPCAP(0)+(x))
102#define RVCCAP(x) (VCCAP(0)+(x))
103
104#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
105#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
106#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
107
b7718849 108#define RCAR_PCI_MAX_RESOURCES 4
c25da477
PE		 109#define MAX_NR_INBOUND_MAPS 6
110
290c1fb3
PE		 111struct rcar_msi {
112 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
113 struct irq_domain *domain;
c2791b80 114 struct msi_controller chip;
290c1fb3
PE		 115 unsigned long pages;
116 struct mutex lock;
117 int irq1;
118 int irq2;
119};
120
c2791b80 121static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
290c1fb3
PE		 122{
123 return container_of(chip, struct rcar_msi, chip);
124}
125
c25da477
PE		 126/* Structure representing the PCIe interface */
127struct rcar_pcie {
128 struct device *dev;
129 void __iomem *base;
b7718849 130 struct resource res[RCAR_PCI_MAX_RESOURCES];
c25da477
PE		 131 struct resource busn;
132 int root_bus_nr;
133 struct clk *clk;
134 struct clk *bus_clk;
290c1fb3 135 struct rcar_msi msi;
c25da477
PE		 136};
137
138static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
139{
140 return sys->private_data;
141}
142
b7718849
PE		 143static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
144 unsigned long reg)
c25da477
PE		 145{
146 writel(val, pcie->base + reg);
147}
148
b7718849
PE		 149static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
150 unsigned long reg)
c25da477
PE		 151{
152 return readl(pcie->base + reg);
153}
154
155enum {
b7718849
PE		 156 RCAR_PCI_ACCESS_READ,
157 RCAR_PCI_ACCESS_WRITE,
c25da477
PE		 158};
159
160static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
161{
162 int shift = 8 * (where & 3);
b7718849 163 u32 val = rcar_pci_read_reg(pcie, where & ~3);
c25da477
PE		 164
165 val &= ~(mask << shift);
166 val |= data << shift;
b7718849 167 rcar_pci_write_reg(pcie, val, where & ~3);
c25da477
PE		 168}
169
170static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
171{
172 int shift = 8 * (where & 3);
b7718849 173 u32 val = rcar_pci_read_reg(pcie, where & ~3);
c25da477
PE		 174
175 return val >> shift;
176}
177
178/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
179static int rcar_pcie_config_access(struct rcar_pcie *pcie,
180 unsigned char access_type, struct pci_bus *bus,
181 unsigned int devfn, int where, u32 *data)
182{
183 int dev, func, reg, index;
184
185 dev = PCI_SLOT(devfn);
186 func = PCI_FUNC(devfn);
187 reg = where & ~3;
188 index = reg / 4;
189
190 /*
191 * While each channel has its own memory-mapped extended config
192 * space, it's generally only accessible when in endpoint mode.
193 * When in root complex mode, the controller is unable to target
194 * itself with either type 0 or type 1 accesses, and indeed, any
195 * controller initiated target transfer to its own config space
196 * result in a completer abort.
197 *
198 * Each channel effectively only supports a single device, but as
199 * the same channel <-> device access works for any PCI_SLOT()
200 * value, we cheat a bit here and bind the controller's config
201 * space to devfn 0 in order to enable self-enumeration. In this
202 * case the regular ECAR/ECDR path is sidelined and the mangled
203 * config access itself is initiated as an internal bus transaction.
204 */
205 if (pci_is_root_bus(bus)) {
206 if (dev != 0)
207 return PCIBIOS_DEVICE_NOT_FOUND;
208
b7718849
PE		 209 if (access_type == RCAR_PCI_ACCESS_READ) {
210 *data = rcar_pci_read_reg(pcie, PCICONF(index));
c25da477
PE		 211 } else {
212 /* Keep an eye out for changes to the root bus number */
213 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
214 pcie->root_bus_nr = *data & 0xff;
215
b7718849 216 rcar_pci_write_reg(pcie, *data, PCICONF(index));
c25da477
PE		 217 }
218
219 return PCIBIOS_SUCCESSFUL;
220 }
221
222 if (pcie->root_bus_nr < 0)
223 return PCIBIOS_DEVICE_NOT_FOUND;
224
225 /* Clear errors */
b7718849 226 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
c25da477
PE		 227
228 /* Set the PIO address */
b7718849
PE		 229 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
230 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
c25da477
PE		 231
232 /* Enable the configuration access */
233 if (bus->parent->number == pcie->root_bus_nr)
b7718849 234 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
c25da477 235 else
b7718849 236 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
c25da477
PE		 237
238 /* Check for errors */
b7718849 239 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
c25da477
PE		 240 return PCIBIOS_DEVICE_NOT_FOUND;
241
242 /* Check for master and target aborts */
243 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
244 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
245 return PCIBIOS_DEVICE_NOT_FOUND;
246
b7718849
PE		 247 if (access_type == RCAR_PCI_ACCESS_READ)
248 *data = rcar_pci_read_reg(pcie, PCIECDR);
c25da477 249 else
b7718849 250 rcar_pci_write_reg(pcie, *data, PCIECDR);
c25da477
PE		 251
252 /* Disable the configuration access */
b7718849 253 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
c25da477
PE		 254
255 return PCIBIOS_SUCCESSFUL;
256}
257
258static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 *val)
260{
261 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
262 int ret;
263
b7718849 264 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
c25da477
PE		 265 bus, devfn, where, val);
266 if (ret != PCIBIOS_SUCCESSFUL) {
267 *val = 0xffffffff;
268 return ret;
269 }
270
271 if (size == 1)
272 *val = (*val >> (8 * (where & 3))) & 0xff;
273 else if (size == 2)
274 *val = (*val >> (8 * (where & 2))) & 0xffff;
275
227f0647
RD		 276 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
277 bus->number, devfn, where, size, (unsigned long)*val);
c25da477
PE		 278
279 return ret;
280}
281
282/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
283static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
284 int where, int size, u32 val)
285{
286 struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
287 int shift, ret;
288 u32 data;
289
b7718849 290 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
c25da477
PE		 291 bus, devfn, where, &data);
292 if (ret != PCIBIOS_SUCCESSFUL)
293 return ret;
294
227f0647
RD		 295 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
296 bus->number, devfn, where, size, (unsigned long)val);
c25da477
PE		 297
298 if (size == 1) {
299 shift = 8 * (where & 3);
300 data &= ~(0xff << shift);
301 data |= ((val & 0xff) << shift);
302 } else if (size == 2) {
303 shift = 8 * (where & 2);
304 data &= ~(0xffff << shift);
305 data |= ((val & 0xffff) << shift);
306 } else
307 data = val;
308
b7718849 309 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
c25da477
PE		 310 bus, devfn, where, &data);
311
312 return ret;
313}
314
315static struct pci_ops rcar_pcie_ops = {
316 .read = rcar_pcie_read_conf,
317 .write = rcar_pcie_write_conf,
318};
319
0549252a 320static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
c25da477 321{
0549252a
PE		 322 struct resource *res = &pcie->res[win];
323
c25da477
PE		 324 /* Setup PCIe address space mappings for each resource */
325 resource_size_t size;
0b0b0893 326 resource_size_t res_start;
c25da477
PE		 327 u32 mask;
328
b7718849 329 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
c25da477
PE		 330
331 /*
332 * The PAMR mask is calculated in units of 128Bytes, which
333 * keeps things pretty simple.
334 */
335 size = resource_size(res);
336 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
b7718849 337 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
c25da477 338
0b0b0893
LD		 339 if (res->flags & IORESOURCE_IO)
340 res_start = pci_pio_to_address(res->start);
341 else
342 res_start = res->start;
343
ecd06305 344 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
2ea2a273 345 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
ecd06305 346 PCIEPALR(win));
c25da477
PE		 347
348 /* First resource is for IO */
349 mask = PAR_ENABLE;
350 if (res->flags & IORESOURCE_IO)
351 mask |= IO_SPACE;
352
b7718849 353 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
c25da477
PE		 354}
355
356static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
357{
358 struct rcar_pcie *pcie = sys_to_pcie(sys);
359 struct resource *res;
360 int i;
361
362 pcie->root_bus_nr = -1;
363
364 /* Setup PCI resources */
b7718849 365 for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
c25da477
PE		 366
367 res = &pcie->res[i];
368 if (!res->flags)
369 continue;
370
0549252a 371 rcar_pcie_setup_window(i, pcie);
c25da477 372
0b0b0893
LD		 373 if (res->flags & IORESOURCE_IO) {
374 phys_addr_t io_start = pci_pio_to_address(res->start);
375 pci_ioremap_io(nr * SZ_64K, io_start);
376 } else
c25da477
PE		 377 pci_add_resource(&sys->resources, res);
378 }
379 pci_add_resource(&sys->resources, &pcie->busn);
380
381 return 1;
382}
383
3c70637f 384static struct hw_pci rcar_pci = {
c25da477
PE		 385 .setup = rcar_pcie_setup,
386 .map_irq = of_irq_parse_and_map_pci,
387 .ops = &rcar_pcie_ops,
388};
389
390static void rcar_pcie_enable(struct rcar_pcie *pcie)
391{
392 struct platform_device *pdev = to_platform_device(pcie->dev);
393
394 rcar_pci.nr_controllers = 1;
395 rcar_pci.private_data = (void **)&pcie;
7840cba8
YW		 396#ifdef CONFIG_PCI_MSI
397 rcar_pci.msi_ctrl = &pcie->msi.chip;
398#endif
c25da477
PE		 399
400 pci_common_init_dev(&pdev->dev, &rcar_pci);
c25da477
PE		 401}
402
403static int phy_wait_for_ack(struct rcar_pcie *pcie)
404{
405 unsigned int timeout = 100;
406
407 while (timeout--) {
b7718849 408 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
c25da477
PE		 409 return 0;
410
411 udelay(100);
412 }
413
414 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
415
416 return -ETIMEDOUT;
417}
418
419static void phy_write_reg(struct rcar_pcie *pcie,
420 unsigned int rate, unsigned int addr,
421 unsigned int lane, unsigned int data)
422{
423 unsigned long phyaddr;
424
425 phyaddr = WRITE_CMD |
426 ((rate & 1) << RATE_POS) |
427 ((lane & 0xf) << LANE_POS) |
428 ((addr & 0xff) << ADR_POS);
429
430 /* Set write data */
b7718849
PE		 431 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
432 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
c25da477
PE		 433
434 /* Ignore errors as they will be dealt with if the data link is down */
435 phy_wait_for_ack(pcie);
436
437 /* Clear command */
b7718849
PE		 438 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
439 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
c25da477
PE		 440
441 /* Ignore errors as they will be dealt with if the data link is down */
442 phy_wait_for_ack(pcie);
443}
444
445static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
446{
447 unsigned int timeout = 10;
448
449 while (timeout--) {
b7718849 450 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
c25da477
PE		 451 return 0;
452
453 msleep(5);
454 }
455
456 return -ETIMEDOUT;
457}
458
459static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
460{
461 int err;
462
463 /* Begin initialization */
b7718849 464 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
c25da477
PE		 465
466 /* Set mode */
b7718849 467 rcar_pci_write_reg(pcie, 1, PCIEMSR);
c25da477
PE		 468
469 /*
470 * Initial header for port config space is type 1, set the device
471 * class to match. Hardware takes care of propagating the IDSETR
472 * settings, so there is no need to bother with a quirk.
473 */
b7718849 474 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
c25da477
PE		 475
476 /*
477 * Setup Secondary Bus Number & Subordinate Bus Number, even though
478 * they aren't used, to avoid bridge being detected as broken.
479 */
480 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
481 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
482
483 /* Initialize default capabilities. */
2c3fd4c9 484 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
c25da477
PE		 485 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
486 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
487 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
488 PCI_HEADER_TYPE_BRIDGE);
489
490 /* Enable data link layer active state reporting */
2c3fd4c9
PE		 491 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
492 PCI_EXP_LNKCAP_DLLLARC);
c25da477
PE		 493
494 /* Write out the physical slot number = 0 */
495 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
496
497 /* Set the completion timer timeout to the maximum 50ms. */
b7718849 498 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
c25da477
PE		 499
500 /* Terminate list of capabilities (Next Capability Offset=0) */
2c3fd4c9 501 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
c25da477 502
290c1fb3
PE		 503 /* Enable MSI */
504 if (IS_ENABLED(CONFIG_PCI_MSI))
1fc6aa96 505 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
290c1fb3 506
c25da477 507 /* Finish initialization - establish a PCI Express link */
b7718849 508 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
c25da477
PE		 509
510 /* This will timeout if we don't have a link. */
511 err = rcar_pcie_wait_for_dl(pcie);
512 if (err)
513 return err;
514
515 /* Enable INTx interrupts */
516 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
517
c25da477
PE		 518 wmb();
519
520 return 0;
521}
522
523static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
524{
525 unsigned int timeout = 10;
526
527 /* Initialize the phy */
528 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
529 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
530 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
531 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
532 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
533 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
534 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
535 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
536 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
537 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
538 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
539 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
540
541 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
542 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
543 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
544
545 while (timeout--) {
b7718849 546 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
c25da477
PE		 547 return rcar_pcie_hw_init(pcie);
548
549 msleep(5);
550 }
551
552 return -ETIMEDOUT;
553}
554
290c1fb3
PE		 555static int rcar_msi_alloc(struct rcar_msi *chip)
556{
557 int msi;
558
559 mutex_lock(&chip->lock);
560
561 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
562 if (msi < INT_PCI_MSI_NR)
563 set_bit(msi, chip->used);
564 else
565 msi = -ENOSPC;
566
567 mutex_unlock(&chip->lock);
568
569 return msi;
570}
571
572static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
573{
574 mutex_lock(&chip->lock);
575 clear_bit(irq, chip->used);
576 mutex_unlock(&chip->lock);
577}
578
579static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
580{
581 struct rcar_pcie *pcie = data;
582 struct rcar_msi *msi = &pcie->msi;
583 unsigned long reg;
584
b7718849 585 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
290c1fb3
PE		 586
587 /* MSI & INTx share an interrupt - we only handle MSI here */
588 if (!reg)
589 return IRQ_NONE;
590
591 while (reg) {
592 unsigned int index = find_first_bit(&reg, 32);
593 unsigned int irq;
594
595 /* clear the interrupt */
b7718849 596 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
290c1fb3
PE		 597
598 irq = irq_find_mapping(msi->domain, index);
599 if (irq) {
600 if (test_bit(index, msi->used))
601 generic_handle_irq(irq);
602 else
603 dev_info(pcie->dev, "unhandled MSI\n");
604 } else {
605 /* Unknown MSI, just clear it */
606 dev_dbg(pcie->dev, "unexpected MSI\n");
607 }
608
609 /* see if there's any more pending in this vector */
b7718849 610 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
290c1fb3
PE		 611 }
612
613 return IRQ_HANDLED;
614}
615
c2791b80 616static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
290c1fb3
PE		 617 struct msi_desc *desc)
618{
619 struct rcar_msi *msi = to_rcar_msi(chip);
620 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
621 struct msi_msg msg;
622 unsigned int irq;
623 int hwirq;
624
625 hwirq = rcar_msi_alloc(msi);
626 if (hwirq < 0)
627 return hwirq;
628
629 irq = irq_create_mapping(msi->domain, hwirq);
630 if (!irq) {
631 rcar_msi_free(msi, hwirq);
632 return -EINVAL;
633 }
634
635 irq_set_msi_desc(irq, desc);
636
b7718849
PE		 637 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
638 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
290c1fb3
PE		 639 msg.data = hwirq;
640
83a18912 641 pci_write_msi_msg(irq, &msg);
290c1fb3
PE		 642
643 return 0;
644}
645
c2791b80 646static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
290c1fb3
PE		 647{
648 struct rcar_msi *msi = to_rcar_msi(chip);
649 struct irq_data *d = irq_get_irq_data(irq);
650
651 rcar_msi_free(msi, d->hwirq);
652}
653
654static struct irq_chip rcar_msi_irq_chip = {
655 .name = "R-Car PCIe MSI",
280510f1
TG		 656 .irq_enable = pci_msi_unmask_irq,
657 .irq_disable = pci_msi_mask_irq,
658 .irq_mask = pci_msi_mask_irq,
659 .irq_unmask = pci_msi_unmask_irq,
290c1fb3
PE		 660};
661
662static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
663 irq_hw_number_t hwirq)
664{
665 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
666 irq_set_chip_data(irq, domain->host_data);
290c1fb3
PE		 667
668 return 0;
669}
670
671static const struct irq_domain_ops msi_domain_ops = {
672 .map = rcar_msi_map,
673};
674
675static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
676{
677 struct platform_device *pdev = to_platform_device(pcie->dev);
678 struct rcar_msi *msi = &pcie->msi;
679 unsigned long base;
680 int err;
681
682 mutex_init(&msi->lock);
683
684 msi->chip.dev = pcie->dev;
685 msi->chip.setup_irq = rcar_msi_setup_irq;
686 msi->chip.teardown_irq = rcar_msi_teardown_irq;
687
688 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
689 &msi_domain_ops, &msi->chip);
690 if (!msi->domain) {
691 dev_err(&pdev->dev, "failed to create IRQ domain\n");
692 return -ENOMEM;
693 }
694
695 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
696 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
697 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
698 if (err < 0) {
699 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
700 goto err;
701 }
702
703 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
704 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
705 if (err < 0) {
706 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
707 goto err;
708 }
709
710 /* setup MSI data target */
711 msi->pages = __get_free_pages(GFP_KERNEL, 0);
712 base = virt_to_phys((void *)msi->pages);
713
b7718849
PE		 714 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
715 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
290c1fb3
PE		 716
717 /* enable all MSI interrupts */
b7718849 718 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
290c1fb3
PE		 719
720 return 0;
721
722err:
723 irq_domain_remove(msi->domain);
724 return err;
725}
726
c25da477
PE		 727static int rcar_pcie_get_resources(struct platform_device *pdev,
728 struct rcar_pcie *pcie)
729{
730 struct resource res;
290c1fb3 731 int err, i;
c25da477
PE		 732
733 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
734 if (err)
735 return err;
736
737 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
738 if (IS_ERR(pcie->clk)) {
739 dev_err(pcie->dev, "cannot get platform clock\n");
740 return PTR_ERR(pcie->clk);
741 }
742 err = clk_prepare_enable(pcie->clk);
743 if (err)
744 goto fail_clk;
745
746 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
747 if (IS_ERR(pcie->bus_clk)) {
748 dev_err(pcie->dev, "cannot get pcie bus clock\n");
749 err = PTR_ERR(pcie->bus_clk);
750 goto fail_clk;
751 }
752 err = clk_prepare_enable(pcie->bus_clk);
753 if (err)
754 goto err_map_reg;
755
290c1fb3 756 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
c51d411f 757 if (!i) {
290c1fb3
PE		 758 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
759 err = -ENOENT;
760 goto err_map_reg;
761 }
762 pcie->msi.irq1 = i;
763
764 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
c51d411f 765 if (!i) {
290c1fb3
PE		 766 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
767 err = -ENOENT;
768 goto err_map_reg;
769 }
770 pcie->msi.irq2 = i;
771
c25da477
PE		 772 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
773 if (IS_ERR(pcie->base)) {
774 err = PTR_ERR(pcie->base);
775 goto err_map_reg;
776 }
777
778 return 0;
779
780err_map_reg:
781 clk_disable_unprepare(pcie->bus_clk);
782fail_clk:
783 clk_disable_unprepare(pcie->clk);
784
785 return err;
786}
787
788static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
789 struct of_pci_range *range,
790 int *index)
791{
792 u64 restype = range->flags;
793 u64 cpu_addr = range->cpu_addr;
794 u64 cpu_end = range->cpu_addr + range->size;
795 u64 pci_addr = range->pci_addr;
796 u32 flags = LAM_64BIT | LAR_ENABLE;
797 u64 mask;
798 u64 size;
799 int idx = *index;
800
801 if (restype & IORESOURCE_PREFETCH)
802 flags |= LAM_PREFETCH;
803
804 /*
805 * If the size of the range is larger than the alignment of the start
806 * address, we have to use multiple entries to perform the mapping.
807 */
808 if (cpu_addr > 0) {
809 unsigned long nr_zeros = __ffs64(cpu_addr);
810 u64 alignment = 1ULL << nr_zeros;
b7718849 811
c25da477
PE		 812 size = min(range->size, alignment);
813 } else {
814 size = range->size;
815 }
816 /* Hardware supports max 4GiB inbound region */
817 size = min(size, 1ULL << 32);
818
819 mask = roundup_pow_of_two(size) - 1;
820 mask &= ~0xf;
821
822 while (cpu_addr < cpu_end) {
823 /*
824 * Set up 64-bit inbound regions as the range parser doesn't
825 * distinguish between 32 and 64-bit types.
826 */
b7718849
PE		 827 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
828 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
829 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
c25da477 830
b7718849
PE		 831 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
832 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
833 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
c25da477
PE		 834
835 pci_addr += size;
836 cpu_addr += size;
837 idx += 2;
838
839 if (idx > MAX_NR_INBOUND_MAPS) {
840 dev_err(pcie->dev, "Failed to map inbound regions!\n");
841 return -EINVAL;
842 }
843 }
844 *index = idx;
845
846 return 0;
847}
848
849static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
850 struct device_node *node)
851{
852 const int na = 3, ns = 2;
853 int rlen;
854
855 parser->node = node;
856 parser->pna = of_n_addr_cells(node);
857 parser->np = parser->pna + na + ns;
858
859 parser->range = of_get_property(node, "dma-ranges", &rlen);
860 if (!parser->range)
861 return -ENOENT;
862
863 parser->end = parser->range + rlen / sizeof(__be32);
864 return 0;
865}
866
867static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
868 struct device_node *np)
869{
870 struct of_pci_range range;
871 struct of_pci_range_parser parser;
872 int index = 0;
873 int err;
874
875 if (pci_dma_range_parser_init(&parser, np))
876 return -EINVAL;
877
878 /* Get the dma-ranges from DT */
879 for_each_of_pci_range(&parser, &range) {
880 u64 end = range.cpu_addr + range.size - 1;
881 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
882 range.flags, range.cpu_addr, end, range.pci_addr);
883
884 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
885 if (err)
886 return err;
887 }
888
889 return 0;
890}
891
892static const struct of_device_id rcar_pcie_of_match[] = {
893 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
894 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
895 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
896 {},
897};
898MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
899
900static int rcar_pcie_probe(struct platform_device *pdev)
901{
902 struct rcar_pcie *pcie;
903 unsigned int data;
904 struct of_pci_range range;
905 struct of_pci_range_parser parser;
906 const struct of_device_id *of_id;
907 int err, win = 0;
908 int (*hw_init_fn)(struct rcar_pcie *);
909
910 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
911 if (!pcie)
912 return -ENOMEM;
913
914 pcie->dev = &pdev->dev;
915 platform_set_drvdata(pdev, pcie);
916
917 /* Get the bus range */
918 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
919 dev_err(&pdev->dev, "failed to parse bus-range property\n");
920 return -EINVAL;
921 }
922
923 if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
924 dev_err(&pdev->dev, "missing ranges property\n");
925 return -EINVAL;
926 }
927
928 err = rcar_pcie_get_resources(pdev, pcie);
929 if (err < 0) {
930 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
931 return err;
932 }
933
934 for_each_of_pci_range(&parser, &range) {
0b0b0893 935 err = of_pci_range_to_resource(&range, pdev->dev.of_node,
c25da477 936 &pcie->res[win++]);
0b0b0893
LD		 937 if (err < 0)
938 return err;
c25da477 939
b7718849 940 if (win > RCAR_PCI_MAX_RESOURCES)
c25da477
PE		 941 break;
942 }
943
944 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
945 if (err)
946 return err;
947
290c1fb3
PE		 948 if (IS_ENABLED(CONFIG_PCI_MSI)) {
949 err = rcar_pcie_enable_msi(pcie);
950 if (err < 0) {
951 dev_err(&pdev->dev,
952 "failed to enable MSI support: %d\n",
953 err);
954 return err;
955 }
956 }
957
c25da477
PE		 958 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
959 if (!of_id || !of_id->data)
960 return -EINVAL;
961 hw_init_fn = of_id->data;
962
963 /* Failure to get a link might just be that no cards are inserted */
964 err = hw_init_fn(pcie);
965 if (err) {
966 dev_info(&pdev->dev, "PCIe link down\n");
967 return 0;
968 }
969
b7718849 970 data = rcar_pci_read_reg(pcie, MACSR);
c25da477
PE		 971 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
972
973 rcar_pcie_enable(pcie);
974
975 return 0;
976}
977
978static struct platform_driver rcar_pcie_driver = {
979 .driver = {
980 .name = DRV_NAME,
c25da477
PE		 981 .of_match_table = rcar_pcie_of_match,
982 .suppress_bind_attrs = true,
983 },
984 .probe = rcar_pcie_probe,
985};
986module_platform_driver(rcar_pcie_driver);
987
988MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
989MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
68947eb1 990MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)