Commit | Line | Data |
---|---|---|
340cba60 | 1 | /* |
4b1ced84 | 2 | * Synopsys Designware PCIe host controller driver |
340cba60 JH |
3 | * |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Author: Jingoo Han <jg1.han@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
f342d940 JH |
14 | #include <linux/irq.h> |
15 | #include <linux/irqdomain.h> | |
340cba60 | 16 | #include <linux/kernel.h> |
340cba60 | 17 | #include <linux/module.h> |
f342d940 | 18 | #include <linux/msi.h> |
340cba60 | 19 | #include <linux/of_address.h> |
804f57b1 | 20 | #include <linux/of_pci.h> |
340cba60 JH |
21 | #include <linux/pci.h> |
22 | #include <linux/pci_regs.h> | |
4dd964df | 23 | #include <linux/platform_device.h> |
340cba60 JH |
24 | #include <linux/types.h> |
25 | ||
4b1ced84 | 26 | #include "pcie-designware.h" |
340cba60 JH |
27 | |
28 | /* Synopsis specific PCIE configuration registers */ | |
29 | #define PCIE_PORT_LINK_CONTROL 0x710 | |
30 | #define PORT_LINK_MODE_MASK (0x3f << 16) | |
4b1ced84 JH |
31 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) |
32 | #define PORT_LINK_MODE_2_LANES (0x3 << 16) | |
340cba60 | 33 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) |
5b0f0738 | 34 | #define PORT_LINK_MODE_8_LANES (0xf << 16) |
340cba60 JH |
35 | |
36 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C | |
37 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) | |
38 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) | |
4b1ced84 JH |
39 | #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) |
40 | #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) | |
41 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) | |
5b0f0738 | 42 | #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) |
340cba60 JH |
43 | |
44 | #define PCIE_MSI_ADDR_LO 0x820 | |
45 | #define PCIE_MSI_ADDR_HI 0x824 | |
46 | #define PCIE_MSI_INTR0_ENABLE 0x828 | |
47 | #define PCIE_MSI_INTR0_MASK 0x82C | |
48 | #define PCIE_MSI_INTR0_STATUS 0x830 | |
49 | ||
50 | #define PCIE_ATU_VIEWPORT 0x900 | |
51 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) | |
52 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) | |
53 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) | |
54 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) | |
55 | #define PCIE_ATU_CR1 0x904 | |
56 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) | |
57 | #define PCIE_ATU_TYPE_IO (0x2 << 0) | |
58 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) | |
59 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) | |
60 | #define PCIE_ATU_CR2 0x908 | |
61 | #define PCIE_ATU_ENABLE (0x1 << 31) | |
62 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) | |
63 | #define PCIE_ATU_LOWER_BASE 0x90C | |
64 | #define PCIE_ATU_UPPER_BASE 0x910 | |
65 | #define PCIE_ATU_LIMIT 0x914 | |
66 | #define PCIE_ATU_LOWER_TARGET 0x918 | |
67 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) | |
68 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) | |
69 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) | |
70 | #define PCIE_ATU_UPPER_TARGET 0x91C | |
71 | ||
4b1ced84 JH |
72 | static struct hw_pci dw_pci; |
73 | ||
73e40850 | 74 | static unsigned long global_io_offset; |
340cba60 JH |
75 | |
76 | static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) | |
77 | { | |
84a263f3 LS |
78 | BUG_ON(!sys->private_data); |
79 | ||
340cba60 JH |
80 | return sys->private_data; |
81 | } | |
82 | ||
a01ef59e | 83 | int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) |
340cba60 JH |
84 | { |
85 | *val = readl(addr); | |
86 | ||
87 | if (size == 1) | |
88 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
89 | else if (size == 2) | |
90 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
91 | else if (size != 4) | |
92 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
93 | ||
94 | return PCIBIOS_SUCCESSFUL; | |
95 | } | |
96 | ||
a01ef59e | 97 | int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val) |
340cba60 JH |
98 | { |
99 | if (size == 4) | |
100 | writel(val, addr); | |
101 | else if (size == 2) | |
102 | writew(val, addr + (where & 2)); | |
103 | else if (size == 1) | |
104 | writeb(val, addr + (where & 3)); | |
105 | else | |
106 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
107 | ||
108 | return PCIBIOS_SUCCESSFUL; | |
109 | } | |
110 | ||
f7b7868c | 111 | static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) |
340cba60 | 112 | { |
4b1ced84 | 113 | if (pp->ops->readl_rc) |
f7b7868c | 114 | pp->ops->readl_rc(pp, pp->dbi_base + reg, val); |
4b1ced84 | 115 | else |
f7b7868c | 116 | *val = readl(pp->dbi_base + reg); |
340cba60 JH |
117 | } |
118 | ||
f7b7868c | 119 | static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) |
340cba60 | 120 | { |
4b1ced84 | 121 | if (pp->ops->writel_rc) |
f7b7868c | 122 | pp->ops->writel_rc(pp, val, pp->dbi_base + reg); |
4b1ced84 | 123 | else |
f7b7868c | 124 | writel(val, pp->dbi_base + reg); |
340cba60 JH |
125 | } |
126 | ||
73e40850 BH |
127 | static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
128 | u32 *val) | |
340cba60 JH |
129 | { |
130 | int ret; | |
131 | ||
4b1ced84 JH |
132 | if (pp->ops->rd_own_conf) |
133 | ret = pp->ops->rd_own_conf(pp, where, size, val); | |
134 | else | |
a01ef59e PA |
135 | ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, |
136 | size, val); | |
4b1ced84 | 137 | |
340cba60 JH |
138 | return ret; |
139 | } | |
140 | ||
73e40850 BH |
141 | static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
142 | u32 val) | |
340cba60 JH |
143 | { |
144 | int ret; | |
145 | ||
4b1ced84 JH |
146 | if (pp->ops->wr_own_conf) |
147 | ret = pp->ops->wr_own_conf(pp, where, size, val); | |
148 | else | |
a01ef59e PA |
149 | ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, |
150 | size, val); | |
4b1ced84 | 151 | |
340cba60 JH |
152 | return ret; |
153 | } | |
154 | ||
63503c87 JZ |
155 | static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, |
156 | int type, u64 cpu_addr, u64 pci_addr, u32 size) | |
157 | { | |
158 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, | |
159 | PCIE_ATU_VIEWPORT); | |
160 | dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE); | |
161 | dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE); | |
162 | dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1), | |
163 | PCIE_ATU_LIMIT); | |
164 | dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET); | |
165 | dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET); | |
166 | dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); | |
167 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | |
168 | } | |
169 | ||
f342d940 JH |
170 | static struct irq_chip dw_msi_irq_chip = { |
171 | .name = "PCI-MSI", | |
280510f1 TG |
172 | .irq_enable = pci_msi_unmask_irq, |
173 | .irq_disable = pci_msi_mask_irq, | |
174 | .irq_mask = pci_msi_mask_irq, | |
175 | .irq_unmask = pci_msi_unmask_irq, | |
f342d940 JH |
176 | }; |
177 | ||
178 | /* MSI int handler */ | |
7f4f16ee | 179 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) |
f342d940 JH |
180 | { |
181 | unsigned long val; | |
904d0e78 | 182 | int i, pos, irq; |
7f4f16ee | 183 | irqreturn_t ret = IRQ_NONE; |
f342d940 JH |
184 | |
185 | for (i = 0; i < MAX_MSI_CTRLS; i++) { | |
186 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, | |
187 | (u32 *)&val); | |
188 | if (val) { | |
7f4f16ee | 189 | ret = IRQ_HANDLED; |
f342d940 JH |
190 | pos = 0; |
191 | while ((pos = find_next_bit(&val, 32, pos)) != 32) { | |
904d0e78 PA |
192 | irq = irq_find_mapping(pp->irq_domain, |
193 | i * 32 + pos); | |
ca165892 HH |
194 | dw_pcie_wr_own_conf(pp, |
195 | PCIE_MSI_INTR0_STATUS + i * 12, | |
196 | 4, 1 << pos); | |
904d0e78 | 197 | generic_handle_irq(irq); |
f342d940 JH |
198 | pos++; |
199 | } | |
200 | } | |
f342d940 | 201 | } |
7f4f16ee LS |
202 | |
203 | return ret; | |
f342d940 JH |
204 | } |
205 | ||
206 | void dw_pcie_msi_init(struct pcie_port *pp) | |
207 | { | |
208 | pp->msi_data = __get_free_pages(GFP_KERNEL, 0); | |
209 | ||
210 | /* program the msi_data */ | |
211 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, | |
212 | virt_to_phys((void *)pp->msi_data)); | |
213 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); | |
214 | } | |
215 | ||
2f37c5a8 MK |
216 | static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) |
217 | { | |
218 | unsigned int res, bit, val; | |
219 | ||
220 | res = (irq / 32) * 12; | |
221 | bit = irq % 32; | |
222 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | |
223 | val &= ~(1 << bit); | |
224 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); | |
225 | } | |
226 | ||
be3f48cb | 227 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, |
58275f2f | 228 | unsigned int nvec, unsigned int pos) |
be3f48cb | 229 | { |
2f37c5a8 | 230 | unsigned int i; |
be3f48cb | 231 | |
0b8cfb6a | 232 | for (i = 0; i < nvec; i++) { |
be3f48cb | 233 | irq_set_msi_desc_off(irq_base, i, NULL); |
58275f2f | 234 | /* Disable corresponding interrupt on MSI controller */ |
2f37c5a8 MK |
235 | if (pp->ops->msi_clear_irq) |
236 | pp->ops->msi_clear_irq(pp, pos + i); | |
237 | else | |
238 | dw_pcie_msi_clear_irq(pp, pos + i); | |
be3f48cb | 239 | } |
c8df6ac9 LS |
240 | |
241 | bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec)); | |
be3f48cb BEN |
242 | } |
243 | ||
2f37c5a8 MK |
244 | static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) |
245 | { | |
246 | unsigned int res, bit, val; | |
247 | ||
248 | res = (irq / 32) * 12; | |
249 | bit = irq % 32; | |
250 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | |
251 | val |= 1 << bit; | |
252 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); | |
253 | } | |
254 | ||
f342d940 JH |
255 | static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) |
256 | { | |
c8df6ac9 | 257 | int irq, pos0, i; |
f342d940 JH |
258 | struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); |
259 | ||
c8df6ac9 LS |
260 | pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, |
261 | order_base_2(no_irqs)); | |
262 | if (pos0 < 0) | |
263 | goto no_valid_irq; | |
f342d940 | 264 | |
904d0e78 PA |
265 | irq = irq_find_mapping(pp->irq_domain, pos0); |
266 | if (!irq) | |
f342d940 JH |
267 | goto no_valid_irq; |
268 | ||
be3f48cb BEN |
269 | /* |
270 | * irq_create_mapping (called from dw_pcie_host_init) pre-allocates | |
271 | * descs so there is no need to allocate descs here. We can therefore | |
272 | * assume that if irq_find_mapping above returns non-zero, then the | |
273 | * descs are also successfully allocated. | |
274 | */ | |
275 | ||
0b8cfb6a | 276 | for (i = 0; i < no_irqs; i++) { |
be3f48cb BEN |
277 | if (irq_set_msi_desc_off(irq, i, desc) != 0) { |
278 | clear_irq_range(pp, irq, i, pos0); | |
279 | goto no_valid_irq; | |
280 | } | |
f342d940 | 281 | /*Enable corresponding interrupt in MSI interrupt controller */ |
2f37c5a8 MK |
282 | if (pp->ops->msi_set_irq) |
283 | pp->ops->msi_set_irq(pp, pos0 + i); | |
284 | else | |
285 | dw_pcie_msi_set_irq(pp, pos0 + i); | |
f342d940 JH |
286 | } |
287 | ||
288 | *pos = pos0; | |
289 | return irq; | |
290 | ||
291 | no_valid_irq: | |
292 | *pos = pos0; | |
293 | return -ENOSPC; | |
294 | } | |
295 | ||
c2791b80 | 296 | static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, |
f342d940 JH |
297 | struct msi_desc *desc) |
298 | { | |
91f8ae82 | 299 | int irq, pos; |
f342d940 JH |
300 | struct msi_msg msg; |
301 | struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); | |
302 | ||
19c5392e LS |
303 | if (desc->msi_attrib.is_msix) |
304 | return -EINVAL; | |
305 | ||
91f8ae82 | 306 | irq = assign_irq(1, desc, &pos); |
f342d940 JH |
307 | if (irq < 0) |
308 | return irq; | |
309 | ||
450e344e ML |
310 | if (pp->ops->get_msi_addr) |
311 | msg.address_lo = pp->ops->get_msi_addr(pp); | |
2f37c5a8 MK |
312 | else |
313 | msg.address_lo = virt_to_phys((void *)pp->msi_data); | |
f342d940 | 314 | msg.address_hi = 0x0; |
24832b4d ML |
315 | |
316 | if (pp->ops->get_msi_data) | |
317 | msg.data = pp->ops->get_msi_data(pp, pos); | |
318 | else | |
319 | msg.data = pos; | |
320 | ||
83a18912 | 321 | pci_write_msi_msg(irq, &msg); |
f342d940 JH |
322 | |
323 | return 0; | |
324 | } | |
325 | ||
c2791b80 | 326 | static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) |
f342d940 | 327 | { |
91f8ae82 LS |
328 | struct irq_data *data = irq_get_irq_data(irq); |
329 | struct msi_desc *msi = irq_data_get_msi(data); | |
330 | struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata); | |
331 | ||
332 | clear_irq_range(pp, irq, 1, data->hwirq); | |
f342d940 JH |
333 | } |
334 | ||
c2791b80 | 335 | static struct msi_controller dw_pcie_msi_chip = { |
f342d940 JH |
336 | .setup_irq = dw_msi_setup_irq, |
337 | .teardown_irq = dw_msi_teardown_irq, | |
338 | }; | |
339 | ||
4b1ced84 JH |
340 | int dw_pcie_link_up(struct pcie_port *pp) |
341 | { | |
342 | if (pp->ops->link_up) | |
343 | return pp->ops->link_up(pp); | |
344 | else | |
345 | return 0; | |
346 | } | |
347 | ||
f342d940 JH |
348 | static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |
349 | irq_hw_number_t hwirq) | |
350 | { | |
351 | irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); | |
352 | irq_set_chip_data(irq, domain->host_data); | |
353 | set_irq_flags(irq, IRQF_VALID); | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static const struct irq_domain_ops msi_domain_ops = { | |
359 | .map = dw_pcie_msi_map, | |
360 | }; | |
361 | ||
a43f32d6 | 362 | int dw_pcie_host_init(struct pcie_port *pp) |
4b1ced84 JH |
363 | { |
364 | struct device_node *np = pp->dev->of_node; | |
4dd964df | 365 | struct platform_device *pdev = to_platform_device(pp->dev); |
4b1ced84 JH |
366 | struct of_pci_range range; |
367 | struct of_pci_range_parser parser; | |
4dd964df | 368 | struct resource *cfg_res; |
f4c55c5a KVA |
369 | u32 val, na, ns; |
370 | const __be32 *addrp; | |
b14a3d17 | 371 | int i, index, ret; |
f4c55c5a KVA |
372 | |
373 | /* Find the address cell size and the number of cells in order to get | |
374 | * the untranslated address. | |
375 | */ | |
376 | of_property_read_u32(np, "#address-cells", &na); | |
377 | ns = of_n_size_cells(np); | |
f342d940 | 378 | |
4dd964df KVA |
379 | cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); |
380 | if (cfg_res) { | |
adf70fc0 PA |
381 | pp->cfg0_size = resource_size(cfg_res)/2; |
382 | pp->cfg1_size = resource_size(cfg_res)/2; | |
4dd964df | 383 | pp->cfg0_base = cfg_res->start; |
adf70fc0 | 384 | pp->cfg1_base = cfg_res->start + pp->cfg0_size; |
f4c55c5a KVA |
385 | |
386 | /* Find the untranslated configuration space address */ | |
387 | index = of_property_match_string(np, "reg-names", "config"); | |
9f0dbe08 | 388 | addrp = of_get_address(np, index, NULL, NULL); |
f4c55c5a | 389 | pp->cfg0_mod_base = of_read_number(addrp, ns); |
adf70fc0 | 390 | pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size; |
4dd964df KVA |
391 | } else { |
392 | dev_err(pp->dev, "missing *config* reg space\n"); | |
393 | } | |
394 | ||
4b1ced84 JH |
395 | if (of_pci_range_parser_init(&parser, np)) { |
396 | dev_err(pp->dev, "missing ranges property\n"); | |
397 | return -EINVAL; | |
398 | } | |
399 | ||
400 | /* Get the I/O and memory ranges from DT */ | |
401 | for_each_of_pci_range(&parser, &range) { | |
402 | unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; | |
2c992f37 | 403 | |
4b1ced84 JH |
404 | if (restype == IORESOURCE_IO) { |
405 | of_pci_range_to_resource(&range, np, &pp->io); | |
406 | pp->io.name = "I/O"; | |
407 | pp->io.start = max_t(resource_size_t, | |
408 | PCIBIOS_MIN_IO, | |
409 | range.pci_addr + global_io_offset); | |
410 | pp->io.end = min_t(resource_size_t, | |
411 | IO_SPACE_LIMIT, | |
412 | range.pci_addr + range.size | |
0c61ea77 | 413 | + global_io_offset - 1); |
adf70fc0 PA |
414 | pp->io_size = resource_size(&pp->io); |
415 | pp->io_bus_addr = range.pci_addr; | |
fce8591f | 416 | pp->io_base = range.cpu_addr; |
f4c55c5a KVA |
417 | |
418 | /* Find the untranslated IO space address */ | |
419 | pp->io_mod_base = of_read_number(parser.range - | |
420 | parser.np + na, ns); | |
4b1ced84 JH |
421 | } |
422 | if (restype == IORESOURCE_MEM) { | |
423 | of_pci_range_to_resource(&range, np, &pp->mem); | |
424 | pp->mem.name = "MEM"; | |
adf70fc0 PA |
425 | pp->mem_size = resource_size(&pp->mem); |
426 | pp->mem_bus_addr = range.pci_addr; | |
f4c55c5a KVA |
427 | |
428 | /* Find the untranslated MEM space address */ | |
429 | pp->mem_mod_base = of_read_number(parser.range - | |
430 | parser.np + na, ns); | |
4b1ced84 JH |
431 | } |
432 | if (restype == 0) { | |
433 | of_pci_range_to_resource(&range, np, &pp->cfg); | |
adf70fc0 PA |
434 | pp->cfg0_size = resource_size(&pp->cfg)/2; |
435 | pp->cfg1_size = resource_size(&pp->cfg)/2; | |
4dd964df | 436 | pp->cfg0_base = pp->cfg.start; |
adf70fc0 | 437 | pp->cfg1_base = pp->cfg.start + pp->cfg0_size; |
f4c55c5a KVA |
438 | |
439 | /* Find the untranslated configuration space address */ | |
440 | pp->cfg0_mod_base = of_read_number(parser.range - | |
441 | parser.np + na, ns); | |
442 | pp->cfg1_mod_base = pp->cfg0_mod_base + | |
adf70fc0 | 443 | pp->cfg0_size; |
4b1ced84 JH |
444 | } |
445 | } | |
446 | ||
4f2ebe00 LS |
447 | ret = of_pci_parse_bus_range(np, &pp->busn); |
448 | if (ret < 0) { | |
449 | pp->busn.name = np->name; | |
450 | pp->busn.start = 0; | |
451 | pp->busn.end = 0xff; | |
452 | pp->busn.flags = IORESOURCE_BUS; | |
453 | dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n", | |
454 | ret, &pp->busn); | |
455 | } | |
456 | ||
4b1ced84 JH |
457 | if (!pp->dbi_base) { |
458 | pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, | |
459 | resource_size(&pp->cfg)); | |
460 | if (!pp->dbi_base) { | |
461 | dev_err(pp->dev, "error with ioremap\n"); | |
462 | return -ENOMEM; | |
463 | } | |
464 | } | |
465 | ||
4b1ced84 JH |
466 | pp->mem_base = pp->mem.start; |
467 | ||
4b1ced84 | 468 | if (!pp->va_cfg0_base) { |
b14a3d17 | 469 | pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, |
adf70fc0 | 470 | pp->cfg0_size); |
b14a3d17 MK |
471 | if (!pp->va_cfg0_base) { |
472 | dev_err(pp->dev, "error with ioremap in function\n"); | |
473 | return -ENOMEM; | |
474 | } | |
4b1ced84 | 475 | } |
b14a3d17 | 476 | |
4b1ced84 | 477 | if (!pp->va_cfg1_base) { |
b14a3d17 | 478 | pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, |
adf70fc0 | 479 | pp->cfg1_size); |
b14a3d17 MK |
480 | if (!pp->va_cfg1_base) { |
481 | dev_err(pp->dev, "error with ioremap\n"); | |
482 | return -ENOMEM; | |
483 | } | |
4b1ced84 JH |
484 | } |
485 | ||
486 | if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { | |
487 | dev_err(pp->dev, "Failed to parse the number of lanes\n"); | |
488 | return -EINVAL; | |
489 | } | |
490 | ||
f342d940 | 491 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
b14a3d17 MK |
492 | if (!pp->ops->msi_host_init) { |
493 | pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, | |
494 | MAX_MSI_IRQS, &msi_domain_ops, | |
495 | &dw_pcie_msi_chip); | |
496 | if (!pp->irq_domain) { | |
497 | dev_err(pp->dev, "irq domain init failed\n"); | |
498 | return -ENXIO; | |
499 | } | |
f342d940 | 500 | |
b14a3d17 MK |
501 | for (i = 0; i < MAX_MSI_IRQS; i++) |
502 | irq_create_mapping(pp->irq_domain, i); | |
503 | } else { | |
504 | ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); | |
505 | if (ret < 0) | |
506 | return ret; | |
507 | } | |
f342d940 JH |
508 | } |
509 | ||
4b1ced84 JH |
510 | if (pp->ops->host_init) |
511 | pp->ops->host_init(pp); | |
512 | ||
513 | dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); | |
514 | ||
515 | /* program correct class for RC */ | |
516 | dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); | |
517 | ||
518 | dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); | |
519 | val |= PORT_LOGIC_SPEED_CHANGE; | |
520 | dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); | |
521 | ||
0815f957 YW |
522 | #ifdef CONFIG_PCI_MSI |
523 | dw_pcie_msi_chip.dev = pp->dev; | |
524 | dw_pci.msi_ctrl = &dw_pcie_msi_chip; | |
525 | #endif | |
526 | ||
4b1ced84 JH |
527 | dw_pci.nr_controllers = 1; |
528 | dw_pci.private_data = (void **)&pp; | |
529 | ||
804f57b1 | 530 | pci_common_init_dev(pp->dev, &dw_pci); |
4b1ced84 JH |
531 | |
532 | return 0; | |
533 | } | |
534 | ||
4b1ced84 | 535 | static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
340cba60 JH |
536 | u32 devfn, int where, int size, u32 *val) |
537 | { | |
538 | int ret = PCIBIOS_SUCCESSFUL; | |
539 | u32 address, busdev; | |
540 | ||
541 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | | |
542 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | |
543 | address = where & ~0x3; | |
544 | ||
545 | if (bus->parent->number == pp->root_bus_nr) { | |
63503c87 JZ |
546 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
547 | PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base, | |
548 | busdev, pp->cfg0_size); | |
a01ef59e PA |
549 | ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size, |
550 | val); | |
63503c87 JZ |
551 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
552 | PCIE_ATU_TYPE_MEM, pp->mem_mod_base, | |
553 | pp->mem_bus_addr, pp->mem_size); | |
340cba60 | 554 | } else { |
63503c87 JZ |
555 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, |
556 | PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base, | |
557 | busdev, pp->cfg1_size); | |
a01ef59e PA |
558 | ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size, |
559 | val); | |
63503c87 JZ |
560 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, |
561 | PCIE_ATU_TYPE_IO, pp->io_mod_base, | |
562 | pp->io_bus_addr, pp->io_size); | |
340cba60 JH |
563 | } |
564 | ||
565 | return ret; | |
566 | } | |
567 | ||
4b1ced84 | 568 | static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
340cba60 JH |
569 | u32 devfn, int where, int size, u32 val) |
570 | { | |
571 | int ret = PCIBIOS_SUCCESSFUL; | |
572 | u32 address, busdev; | |
573 | ||
574 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | | |
575 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | |
576 | address = where & ~0x3; | |
577 | ||
578 | if (bus->parent->number == pp->root_bus_nr) { | |
63503c87 JZ |
579 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
580 | PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base, | |
581 | busdev, pp->cfg0_size); | |
a01ef59e PA |
582 | ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size, |
583 | val); | |
63503c87 JZ |
584 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
585 | PCIE_ATU_TYPE_MEM, pp->mem_mod_base, | |
586 | pp->mem_bus_addr, pp->mem_size); | |
340cba60 | 587 | } else { |
63503c87 JZ |
588 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, |
589 | PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base, | |
590 | busdev, pp->cfg1_size); | |
a01ef59e PA |
591 | ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size, |
592 | val); | |
63503c87 JZ |
593 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, |
594 | PCIE_ATU_TYPE_IO, pp->io_mod_base, | |
595 | pp->io_bus_addr, pp->io_size); | |
340cba60 JH |
596 | } |
597 | ||
598 | return ret; | |
599 | } | |
600 | ||
4b1ced84 | 601 | static int dw_pcie_valid_config(struct pcie_port *pp, |
340cba60 JH |
602 | struct pci_bus *bus, int dev) |
603 | { | |
604 | /* If there is no link, then there is no device */ | |
605 | if (bus->number != pp->root_bus_nr) { | |
4b1ced84 | 606 | if (!dw_pcie_link_up(pp)) |
340cba60 JH |
607 | return 0; |
608 | } | |
609 | ||
610 | /* access only one slot on each root port */ | |
611 | if (bus->number == pp->root_bus_nr && dev > 0) | |
612 | return 0; | |
613 | ||
614 | /* | |
615 | * do not read more than one device on the bus directly attached | |
616 | * to RC's (Virtual Bridge's) DS side. | |
617 | */ | |
618 | if (bus->primary == pp->root_bus_nr && dev > 0) | |
619 | return 0; | |
620 | ||
621 | return 1; | |
622 | } | |
623 | ||
4b1ced84 | 624 | static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
340cba60 JH |
625 | int size, u32 *val) |
626 | { | |
627 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); | |
340cba60 JH |
628 | int ret; |
629 | ||
4b1ced84 | 630 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { |
340cba60 JH |
631 | *val = 0xffffffff; |
632 | return PCIBIOS_DEVICE_NOT_FOUND; | |
633 | } | |
634 | ||
340cba60 | 635 | if (bus->number != pp->root_bus_nr) |
a1c0ae9c MK |
636 | if (pp->ops->rd_other_conf) |
637 | ret = pp->ops->rd_other_conf(pp, bus, devfn, | |
638 | where, size, val); | |
639 | else | |
640 | ret = dw_pcie_rd_other_conf(pp, bus, devfn, | |
340cba60 JH |
641 | where, size, val); |
642 | else | |
4b1ced84 | 643 | ret = dw_pcie_rd_own_conf(pp, where, size, val); |
340cba60 JH |
644 | |
645 | return ret; | |
646 | } | |
647 | ||
4b1ced84 | 648 | static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
340cba60 JH |
649 | int where, int size, u32 val) |
650 | { | |
651 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); | |
340cba60 JH |
652 | int ret; |
653 | ||
4b1ced84 | 654 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) |
340cba60 JH |
655 | return PCIBIOS_DEVICE_NOT_FOUND; |
656 | ||
340cba60 | 657 | if (bus->number != pp->root_bus_nr) |
a1c0ae9c MK |
658 | if (pp->ops->wr_other_conf) |
659 | ret = pp->ops->wr_other_conf(pp, bus, devfn, | |
660 | where, size, val); | |
661 | else | |
662 | ret = dw_pcie_wr_other_conf(pp, bus, devfn, | |
340cba60 JH |
663 | where, size, val); |
664 | else | |
4b1ced84 | 665 | ret = dw_pcie_wr_own_conf(pp, where, size, val); |
340cba60 JH |
666 | |
667 | return ret; | |
668 | } | |
669 | ||
4b1ced84 JH |
670 | static struct pci_ops dw_pcie_ops = { |
671 | .read = dw_pcie_rd_conf, | |
672 | .write = dw_pcie_wr_conf, | |
340cba60 JH |
673 | }; |
674 | ||
73e40850 | 675 | static int dw_pcie_setup(int nr, struct pci_sys_data *sys) |
4b1ced84 JH |
676 | { |
677 | struct pcie_port *pp; | |
678 | ||
679 | pp = sys_to_pcie(sys); | |
680 | ||
adf70fc0 PA |
681 | if (global_io_offset < SZ_1M && pp->io_size > 0) { |
682 | sys->io_offset = global_io_offset - pp->io_bus_addr; | |
fce8591f | 683 | pci_ioremap_io(global_io_offset, pp->io_base); |
4b1ced84 JH |
684 | global_io_offset += SZ_64K; |
685 | pci_add_resource_offset(&sys->resources, &pp->io, | |
686 | sys->io_offset); | |
687 | } | |
688 | ||
adf70fc0 | 689 | sys->mem_offset = pp->mem.start - pp->mem_bus_addr; |
4b1ced84 | 690 | pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); |
4f2ebe00 | 691 | pci_add_resource(&sys->resources, &pp->busn); |
4b1ced84 JH |
692 | |
693 | return 1; | |
694 | } | |
695 | ||
73e40850 | 696 | static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) |
340cba60 JH |
697 | { |
698 | struct pci_bus *bus; | |
699 | struct pcie_port *pp = sys_to_pcie(sys); | |
700 | ||
92483df2 LS |
701 | pp->root_bus_nr = sys->busnr; |
702 | bus = pci_create_root_bus(pp->dev, sys->busnr, | |
703 | &dw_pcie_ops, sys, &sys->resources); | |
704 | if (!bus) | |
705 | return NULL; | |
706 | ||
707 | pci_scan_child_bus(bus); | |
340cba60 | 708 | |
b14a3d17 MK |
709 | if (bus && pp->ops->scan_bus) |
710 | pp->ops->scan_bus(pp); | |
711 | ||
340cba60 JH |
712 | return bus; |
713 | } | |
714 | ||
73e40850 | 715 | static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
340cba60 JH |
716 | { |
717 | struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); | |
804f57b1 | 718 | int irq; |
340cba60 | 719 | |
804f57b1 LS |
720 | irq = of_irq_parse_and_map_pci(dev, slot, pin); |
721 | if (!irq) | |
722 | irq = pp->irq; | |
340cba60 | 723 | |
804f57b1 | 724 | return irq; |
340cba60 JH |
725 | } |
726 | ||
4b1ced84 JH |
727 | static struct hw_pci dw_pci = { |
728 | .setup = dw_pcie_setup, | |
729 | .scan = dw_pcie_scan_bus, | |
730 | .map_irq = dw_pcie_map_irq, | |
340cba60 JH |
731 | }; |
732 | ||
4b1ced84 | 733 | void dw_pcie_setup_rc(struct pcie_port *pp) |
340cba60 | 734 | { |
340cba60 JH |
735 | u32 val; |
736 | u32 membase; | |
737 | u32 memlimit; | |
738 | ||
66c5c34b | 739 | /* set the number of lanes */ |
f7b7868c | 740 | dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); |
340cba60 | 741 | val &= ~PORT_LINK_MODE_MASK; |
4b1ced84 JH |
742 | switch (pp->lanes) { |
743 | case 1: | |
744 | val |= PORT_LINK_MODE_1_LANES; | |
745 | break; | |
746 | case 2: | |
747 | val |= PORT_LINK_MODE_2_LANES; | |
748 | break; | |
749 | case 4: | |
750 | val |= PORT_LINK_MODE_4_LANES; | |
751 | break; | |
5b0f0738 ZW |
752 | case 8: |
753 | val |= PORT_LINK_MODE_8_LANES; | |
754 | break; | |
4b1ced84 | 755 | } |
f7b7868c | 756 | dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); |
340cba60 JH |
757 | |
758 | /* set link width speed control register */ | |
f7b7868c | 759 | dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); |
340cba60 | 760 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; |
4b1ced84 JH |
761 | switch (pp->lanes) { |
762 | case 1: | |
763 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; | |
764 | break; | |
765 | case 2: | |
766 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; | |
767 | break; | |
768 | case 4: | |
769 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; | |
770 | break; | |
5b0f0738 ZW |
771 | case 8: |
772 | val |= PORT_LOGIC_LINK_WIDTH_8_LANES; | |
773 | break; | |
4b1ced84 | 774 | } |
f7b7868c | 775 | dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); |
340cba60 JH |
776 | |
777 | /* setup RC BARs */ | |
f7b7868c | 778 | dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); |
dbffdd68 | 779 | dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); |
340cba60 JH |
780 | |
781 | /* setup interrupt pins */ | |
f7b7868c | 782 | dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); |
340cba60 JH |
783 | val &= 0xffff00ff; |
784 | val |= 0x00000100; | |
f7b7868c | 785 | dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); |
340cba60 JH |
786 | |
787 | /* setup bus numbers */ | |
f7b7868c | 788 | dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); |
340cba60 JH |
789 | val &= 0xff000000; |
790 | val |= 0x00010100; | |
f7b7868c | 791 | dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); |
340cba60 JH |
792 | |
793 | /* setup memory base, memory limit */ | |
794 | membase = ((u32)pp->mem_base & 0xfff00000) >> 16; | |
adf70fc0 | 795 | memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000; |
340cba60 | 796 | val = memlimit | membase; |
f7b7868c | 797 | dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); |
340cba60 JH |
798 | |
799 | /* setup command register */ | |
f7b7868c | 800 | dw_pcie_readl_rc(pp, PCI_COMMAND, &val); |
340cba60 JH |
801 | val &= 0xffff0000; |
802 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
803 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; | |
f7b7868c | 804 | dw_pcie_writel_rc(pp, val, PCI_COMMAND); |
340cba60 | 805 | } |
340cba60 JH |
806 | |
807 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); | |
4b1ced84 | 808 | MODULE_DESCRIPTION("Designware PCIe host controller driver"); |
340cba60 | 809 | MODULE_LICENSE("GPL v2"); |