[linux-2.6-block.git] / drivers / pci / host / pci-imx6.c

/*
 * PCIe host controller driver for Freescale i.MX6 SoCs
 *
 * Copyright (C) 2013 Kosagi
 *		http://www.kosagi.com
 *
 * Author: Sean Cross <xobs@kosagi.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/resource.h>
#include <linux/signal.h>
#include <linux/types.h>
#include <linux/interrupt.h>

#include "pcie-designware.h"

#define to_imx6_pcie(x)	container_of(x, struct imx6_pcie, pp)

struct imx6_pcie {
	struct gpio_desc	*reset_gpio;
	struct clk		*pcie_bus;
	struct clk		*pcie_phy;
	struct clk		*pcie;
	struct pcie_port	pp;
	struct regmap		*iomuxc_gpr;
	void __iomem		*mem_base;
	u32			tx_deemph_gen1;
	u32			tx_deemph_gen2_3p5db;
	u32			tx_deemph_gen2_6db;
	u32			tx_swing_full;
	u32			tx_swing_low;
};

/* PCIe Root Complex registers (memory-mapped) */
#define PCIE_RC_LCR				0x7c
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1	0x1
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2	0x2
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK	0xf

#define PCIE_RC_LCSR				0x80

/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
#define PCIE_PL_PFLR_LINK_STATE_MASK		(0x3f << 16)
#define PCIE_PL_PFLR_FORCE_LINK			(1 << 15)
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING	(1 << 29)
#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP		(1 << 4)

#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
#define PCIE_PHY_CTRL_DATA_LOC 0
#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
#define PCIE_PHY_CTRL_WR_LOC 18
#define PCIE_PHY_CTRL_RD_LOC 19

#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
#define PCIE_PHY_STAT_ACK_LOC 16

#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)

/* PHY registers (not memory-mapped) */
#define PCIE_PHY_RX_ASIC_OUT 0x100D
#define PCIE_PHY_RX_ASIC_OUT_VALID	(1 << 0)

#define PHY_RX_OVRD_IN_LO 0x1005
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)

static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
{
	u32 val;
	u32 max_iterations = 10;
	u32 wait_counter = 0;

	do {
		val = readl(dbi_base + PCIE_PHY_STAT);
		val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
		wait_counter++;

		if (val == exp_val)
			return 0;

		udelay(1);
	} while (wait_counter < max_iterations);

	return -ETIMEDOUT;
}

static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
{
	u32 val;
	int ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	return pcie_phy_poll_ack(dbi_base, 0);
}

/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
static int pcie_phy_read(void __iomem *dbi_base, int addr, int *data)
{
	u32 val, phy_ctl;
	int ret;

	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	/* assert Read signal */
	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = readl(dbi_base + PCIE_PHY_STAT);
	*data = val & 0xffff;

	/* deassert Read signal */
	writel(0x00, dbi_base + PCIE_PHY_CTRL);

	return pcie_phy_poll_ack(dbi_base, 0);
}

static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
{
	u32 var;
	int ret;

	/* write addr */
	/* cap addr */
	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* capture data */
	var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
	writel(var, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert cap data */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	/* assert wr signal */
	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack */
	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert wr signal */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	writel(0x0, dbi_base + PCIE_PHY_CTRL);

	return 0;
}

static void imx6_pcie_reset_phy(struct pcie_port *pp)
{
	u32 tmp;

	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
	tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
		PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);

	usleep_range(2000, 3000);

	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
	tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
		  PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
}

/*  Added for PCI abort handling */
static int imx6q_pcie_abort_handler(unsigned long addr,
		unsigned int fsr, struct pt_regs *regs)
{
	return 0;
}

static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	u32 val, gpr1, gpr12;

	/*
	 * If the bootloader already enabled the link we need some special
	 * handling to get the core back into a state where it is safe to
	 * touch it for configuration.  As there is no dedicated reset signal
	 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
	 * state before completely disabling LTSSM, which is a prerequisite
	 * for core configuration.
	 *
	 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
	 * indication that the bootloader activated the link.
	 */
	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);

	if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
	    (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
		val = readl(pp->dbi_base + PCIE_PL_PFLR);
		val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
		val |= PCIE_PL_PFLR_FORCE_LINK;
		writel(val, pp->dbi_base + PCIE_PL_PFLR);

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
				IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	}

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);

	return 0;
}

static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	int ret;

	ret = clk_prepare_enable(imx6_pcie->pcie_phy);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_phy clock\n");
		goto err_pcie_phy;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie_bus);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_bus clock\n");
		goto err_pcie_bus;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie clock\n");
		goto err_pcie;
	}

	/* power up core phy and enable ref clock */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
	/*
	 * the async reset input need ref clock to sync internally,
	 * when the ref clock comes after reset, internal synced
	 * reset time is too short, cannot meet the requirement.
	 * add one ~10us delay here.
	 */
	udelay(10);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);

	/* allow the clocks to stabilize */
	usleep_range(200, 500);

	/* Some boards don't have PCIe reset GPIO. */
	if (imx6_pcie->reset_gpio) {
		gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 0);
		msleep(100);
		gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1);
	}
	return 0;

err_pcie:
	clk_disable_unprepare(imx6_pcie->pcie_bus);
err_pcie_bus:
	clk_disable_unprepare(imx6_pcie->pcie_phy);
err_pcie_phy:
	return ret;

}

static void imx6_pcie_init_phy(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);

	/* configure constant input signal to the pcie ctrl and phy */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_LOS_LEVEL, 9 << 4);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			   IMX6Q_GPR8_TX_DEEMPH_GEN1,
			   imx6_pcie->tx_deemph_gen1 << 0);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			   IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
			   imx6_pcie->tx_deemph_gen2_3p5db << 6);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			   IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
			   imx6_pcie->tx_deemph_gen2_6db << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			   IMX6Q_GPR8_TX_SWING_FULL,
			   imx6_pcie->tx_swing_full << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			   IMX6Q_GPR8_TX_SWING_LOW,
			   imx6_pcie->tx_swing_low << 25);
}

static int imx6_pcie_wait_for_link(struct pcie_port *pp)
{
	/* check if the link is up or not */
	if (!dw_pcie_wait_for_link(pp))
		return 0;

	dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
		readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
		readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
	return -ETIMEDOUT;
}

static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
{
	u32 tmp;
	unsigned int retries;

	for (retries = 0; retries < 200; retries++) {
		tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
		/* Test if the speed change finished. */
		if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
			return 0;
		usleep_range(100, 1000);
	}

	dev_err(pp->dev, "Speed change timeout\n");
	return -EINVAL;
}

static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
{
	struct pcie_port *pp = arg;

	return dw_handle_msi_irq(pp);
}

static int imx6_pcie_establish_link(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	u32 tmp;
	int ret;

	/*
	 * Force Gen1 operation when starting the link.  In case the link is
	 * started in Gen2 mode, there is a possibility the devices on the
	 * bus will not be detected at all.  This happens with PCIe switches.
	 */
	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
	writel(tmp, pp->dbi_base + PCIE_RC_LCR);

	/* Start LTSSM. */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);

	ret = imx6_pcie_wait_for_link(pp);
	if (ret) {
		dev_info(pp->dev, "Link never came up\n");
		goto err_reset_phy;
	}

	/* Allow Gen2 mode after the link is up. */
	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
	writel(tmp, pp->dbi_base + PCIE_RC_LCR);

	/*
	 * Start Directed Speed Change so the best possible speed both link
	 * partners support can be negotiated.
	 */
	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	tmp |= PORT_LOGIC_SPEED_CHANGE;
	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);

	ret = imx6_pcie_wait_for_speed_change(pp);
	if (ret) {
		dev_err(pp->dev, "Failed to bring link up!\n");
		goto err_reset_phy;
	}

	/* Make sure link training is finished as well! */
	ret = imx6_pcie_wait_for_link(pp);
	if (ret) {
		dev_err(pp->dev, "Failed to bring link up!\n");
		goto err_reset_phy;
	}

	tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
	dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);

	return 0;

err_reset_phy:
	dev_dbg(pp->dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
		readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
		readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
	imx6_pcie_reset_phy(pp);

	return ret;
}

static void imx6_pcie_host_init(struct pcie_port *pp)
{
	imx6_pcie_assert_core_reset(pp);

	imx6_pcie_init_phy(pp);

	imx6_pcie_deassert_core_reset(pp);

	dw_pcie_setup_rc(pp);

	imx6_pcie_establish_link(pp);

	if (IS_ENABLED(CONFIG_PCI_MSI))
		dw_pcie_msi_init(pp);
}

static int imx6_pcie_link_up(struct pcie_port *pp)
{
	return readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) &
			PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
}

static struct pcie_host_ops imx6_pcie_host_ops = {
	.link_up = imx6_pcie_link_up,
	.host_init = imx6_pcie_host_init,
};

static int __init imx6_add_pcie_port(struct pcie_port *pp,
			struct platform_device *pdev)
{
	int ret;

	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
		if (pp->msi_irq <= 0) {
			dev_err(&pdev->dev, "failed to get MSI irq\n");
			return -ENODEV;
		}

		ret = devm_request_irq(&pdev->dev, pp->msi_irq,
				       imx6_pcie_msi_handler,
				       IRQF_SHARED | IRQF_NO_THREAD,
				       "mx6-pcie-msi", pp);
		if (ret) {
			dev_err(&pdev->dev, "failed to request MSI irq\n");
			return ret;
		}
	}

	pp->root_bus_nr = -1;
	pp->ops = &imx6_pcie_host_ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init imx6_pcie_probe(struct platform_device *pdev)
{
	struct imx6_pcie *imx6_pcie;
	struct pcie_port *pp;
	struct resource *dbi_base;
	struct device_node *node = pdev->dev.of_node;
	int ret;

	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
	if (!imx6_pcie)
		return -ENOMEM;

	pp = &imx6_pcie->pp;
	pp->dev = &pdev->dev;

	/* Added for PCI abort handling */
	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
		"imprecise external abort");

	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
	if (IS_ERR(pp->dbi_base))
		return PTR_ERR(pp->dbi_base);

	/* Fetch GPIOs */
	imx6_pcie->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
							GPIOD_OUT_LOW);

	/* Fetch clocks */
	imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
	if (IS_ERR(imx6_pcie->pcie_phy)) {
		dev_err(&pdev->dev,
			"pcie_phy clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie_phy);
	}

	imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
	if (IS_ERR(imx6_pcie->pcie_bus)) {
		dev_err(&pdev->dev,
			"pcie_bus clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie_bus);
	}

	imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
	if (IS_ERR(imx6_pcie->pcie)) {
		dev_err(&pdev->dev,
			"pcie clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie);
	}

	/* Grab GPR config register range */
	imx6_pcie->iomuxc_gpr =
		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
		dev_err(&pdev->dev, "unable to find iomuxc registers\n");
		return PTR_ERR(imx6_pcie->iomuxc_gpr);
	}

	/* Grab PCIe PHY Tx Settings */
	if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
				 &imx6_pcie->tx_deemph_gen1))
		imx6_pcie->tx_deemph_gen1 = 0;

	if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
				 &imx6_pcie->tx_deemph_gen2_3p5db))
		imx6_pcie->tx_deemph_gen2_3p5db = 0;

	if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
				 &imx6_pcie->tx_deemph_gen2_6db))
		imx6_pcie->tx_deemph_gen2_6db = 20;

	if (of_property_read_u32(node, "fsl,tx-swing-full",
				 &imx6_pcie->tx_swing_full))
		imx6_pcie->tx_swing_full = 127;

	if (of_property_read_u32(node, "fsl,tx-swing-low",
				 &imx6_pcie->tx_swing_low))
		imx6_pcie->tx_swing_low = 127;

	ret = imx6_add_pcie_port(pp, pdev);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, imx6_pcie);
	return 0;
}

static void imx6_pcie_shutdown(struct platform_device *pdev)
{
	struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);

	/* bring down link, so bootloader gets clean state in case of reboot */
	imx6_pcie_assert_core_reset(&imx6_pcie->pp);
}

static const struct of_device_id imx6_pcie_of_match[] = {
	{ .compatible = "fsl,imx6q-pcie", },
	{},
};
MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);

static struct platform_driver imx6_pcie_driver = {
	.driver = {
		.name	= "imx6q-pcie",
		.of_match_table = imx6_pcie_of_match,
	},
	.shutdown = imx6_pcie_shutdown,
};

/* Freescale PCIe driver does not allow module unload */

static int __init imx6_pcie_init(void)
{
	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
}
module_init(imx6_pcie_init);

MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bb38919e SC	1	/*
	2	* PCIe host controller driver for Freescale i.MX6 SoCs
	3	*
	4	* Copyright (C) 2013 Kosagi
	5	* http://www.kosagi.com
	6	*
	7	* Author: Sean Cross <xobs@kosagi.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/delay.h>
	16	#include <linux/gpio.h>
	17	#include <linux/kernel.h>
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	20	#include <linux/module.h>
	21	#include <linux/of_gpio.h>
	22	#include <linux/pci.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/regmap.h>
	25	#include <linux/resource.h>
	26	#include <linux/signal.h>
	27	#include <linux/types.h>
d1dc9749	28	#include <linux/interrupt.h>
bb38919e SC	29
	30	#include "pcie-designware.h"
	31
	32	#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
	33
	34	struct imx6_pcie {
5c5fb40d	35	struct gpio_desc *reset_gpio;
57526136 LS	36	struct clk *pcie_bus;
	37	struct clk *pcie_phy;
	38	struct clk *pcie;
bb38919e SC	39	struct pcie_port pp;
	40	struct regmap *iomuxc_gpr;
	41	void __iomem *mem_base;
28e3abe5 JW	42	u32 tx_deemph_gen1;
	43	u32 tx_deemph_gen2_3p5db;
	44	u32 tx_deemph_gen2_6db;
	45	u32 tx_swing_full;
	46	u32 tx_swing_low;
bb38919e SC	47	};
bb38919e SC	48
fa33a6d8 MV	49	/* PCIe Root Complex registers (memory-mapped) */
	50	#define PCIE_RC_LCR 0x7c
	51	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
	52	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
	53	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
	54
2393f79c BH	55	#define PCIE_RC_LCSR 0x80
2393f79c BH	56
bb38919e SC	57	/* PCIe Port Logic registers (memory-mapped) */
bb38919e SC	58	#define PL_OFFSET 0x700
3e3e406e LS	59	#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
	60	#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
	61	#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
bb38919e SC	62	#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
bb38919e SC	63	#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
7f9f40c0 MV	64	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
7f9f40c0 MV	65	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
bb38919e SC	66
	67	#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
	68	#define PCIE_PHY_CTRL_DATA_LOC 0
	69	#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
	70	#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
	71	#define PCIE_PHY_CTRL_WR_LOC 18
	72	#define PCIE_PHY_CTRL_RD_LOC 19
	73
	74	#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
	75	#define PCIE_PHY_STAT_ACK_LOC 16
	76
fa33a6d8 MV	77	#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
	78	#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
	79
bb38919e SC	80	/* PHY registers (not memory-mapped) */
bb38919e SC	81	#define PCIE_PHY_RX_ASIC_OUT 0x100D
111feb7f	82	#define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
bb38919e SC	83
	84	#define PHY_RX_OVRD_IN_LO 0x1005
	85	#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
	86	#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
	87
	88	static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
	89	{
	90	u32 val;
	91	u32 max_iterations = 10;
	92	u32 wait_counter = 0;
	93
	94	do {
	95	val = readl(dbi_base + PCIE_PHY_STAT);
	96	val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
	97	wait_counter++;
	98
	99	if (val == exp_val)
	100	return 0;
	101
	102	udelay(1);
	103	} while (wait_counter < max_iterations);
	104
	105	return -ETIMEDOUT;
	106	}
	107
	108	static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
	109	{
	110	u32 val;
	111	int ret;
	112
	113	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	114	writel(val, dbi_base + PCIE_PHY_CTRL);
	115
	116	val \|= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	117	writel(val, dbi_base + PCIE_PHY_CTRL);
	118
	119	ret = pcie_phy_poll_ack(dbi_base, 1);
	120	if (ret)
	121	return ret;
	122
	123	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	124	writel(val, dbi_base + PCIE_PHY_CTRL);
	125
8d1ceb52	126	return pcie_phy_poll_ack(dbi_base, 0);
bb38919e SC	127	}
	128
	129	/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
ff3ce480	130	static int pcie_phy_read(void __iomem dbi_base, int addr, int data)
bb38919e SC	131	{
	132	u32 val, phy_ctl;
	133	int ret;
	134
	135	ret = pcie_phy_wait_ack(dbi_base, addr);
	136	if (ret)
	137	return ret;
	138
	139	/* assert Read signal */
	140	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
	141	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
	142
	143	ret = pcie_phy_poll_ack(dbi_base, 1);
	144	if (ret)
	145	return ret;
	146
	147	val = readl(dbi_base + PCIE_PHY_STAT);
	148	*data = val & 0xffff;
	149
	150	/* deassert Read signal */
	151	writel(0x00, dbi_base + PCIE_PHY_CTRL);
	152
8d1ceb52	153	return pcie_phy_poll_ack(dbi_base, 0);
bb38919e SC	154	}
	155
	156	static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
	157	{
	158	u32 var;
	159	int ret;
	160
	161	/* write addr */
	162	/* cap addr */
	163	ret = pcie_phy_wait_ack(dbi_base, addr);
	164	if (ret)
	165	return ret;
	166
	167	var = data << PCIE_PHY_CTRL_DATA_LOC;
	168	writel(var, dbi_base + PCIE_PHY_CTRL);
	169
	170	/* capture data */
	171	var \|= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
	172	writel(var, dbi_base + PCIE_PHY_CTRL);
	173
	174	ret = pcie_phy_poll_ack(dbi_base, 1);
	175	if (ret)
	176	return ret;
	177
	178	/* deassert cap data */
	179	var = data << PCIE_PHY_CTRL_DATA_LOC;
	180	writel(var, dbi_base + PCIE_PHY_CTRL);
	181
	182	/* wait for ack de-assertion */
	183	ret = pcie_phy_poll_ack(dbi_base, 0);
	184	if (ret)
	185	return ret;
	186
	187	/* assert wr signal */
	188	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
	189	writel(var, dbi_base + PCIE_PHY_CTRL);
	190
	191	/* wait for ack */
	192	ret = pcie_phy_poll_ack(dbi_base, 1);
	193	if (ret)
	194	return ret;
	195
	196	/* deassert wr signal */
	197	var = data << PCIE_PHY_CTRL_DATA_LOC;
	198	writel(var, dbi_base + PCIE_PHY_CTRL);
	199
	200	/* wait for ack de-assertion */
	201	ret = pcie_phy_poll_ack(dbi_base, 0);
	202	if (ret)
	203	return ret;
	204
	205	writel(0x0, dbi_base + PCIE_PHY_CTRL);
	206
	207	return 0;
	208	}
	209
53eeb48b LS	210	static void imx6_pcie_reset_phy(struct pcie_port *pp)
	211	{
	212	u32 tmp;
	213
	214	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
	215	tmp \|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN \|
	216	PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	217	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
	218
	219	usleep_range(2000, 3000);
	220
	221	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
	222	tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN \|
	223	PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	224	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
	225	}
	226
bb38919e SC	227	/* Added for PCI abort handling */
	228	static int imx6q_pcie_abort_handler(unsigned long addr,
	229	unsigned int fsr, struct pt_regs *regs)
	230	{
bb38919e SC	231	return 0;
	232	}
	233
	234	static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
	235	{
	236	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
3e3e406e LS	237	u32 val, gpr1, gpr12;
	238
	239	/*
	240	* If the bootloader already enabled the link we need some special
	241	* handling to get the core back into a state where it is safe to
	242	* touch it for configuration. As there is no dedicated reset signal
	243	* wired up for MX6QDL, we need to manually force LTSSM into "detect"
	244	* state before completely disabling LTSSM, which is a prerequisite
	245	* for core configuration.
	246	*
	247	* If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
	248	* indication that the bootloader activated the link.
	249	*/
	250	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
	251	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
	252
	253	if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
	254	(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
	255	val = readl(pp->dbi_base + PCIE_PL_PFLR);
	256	val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
	257	val \|= PCIE_PL_PFLR_FORCE_LINK;
	258	writel(val, pp->dbi_base + PCIE_PL_PFLR);
	259
	260	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	261	IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	262	}
bb38919e SC	263
	264	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	265	IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
bb38919e SC	266	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	267	IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
	268
bb38919e SC	269	return 0;
	270	}
	271
	272	static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
	273	{
	274	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	275	int ret;
	276
57526136	277	ret = clk_prepare_enable(imx6_pcie->pcie_phy);
bb38919e	278	if (ret) {
57526136 LS	279	dev_err(pp->dev, "unable to enable pcie_phy clock\n");
57526136 LS	280	goto err_pcie_phy;
bb38919e SC	281	}
bb38919e SC	282
57526136	283	ret = clk_prepare_enable(imx6_pcie->pcie_bus);
bb38919e	284	if (ret) {
57526136 LS	285	dev_err(pp->dev, "unable to enable pcie_bus clock\n");
57526136 LS	286	goto err_pcie_bus;
bb38919e SC	287	}
bb38919e SC	288
57526136	289	ret = clk_prepare_enable(imx6_pcie->pcie);
bb38919e	290	if (ret) {
57526136 LS	291	dev_err(pp->dev, "unable to enable pcie clock\n");
57526136 LS	292	goto err_pcie;
bb38919e SC	293	}
bb38919e SC	294
3fce0e88 TH	295	/* power up core phy and enable ref clock */
	296	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	297	IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
a2fa6f64 RZ	298	/*
	299	* the async reset input need ref clock to sync internally,
	300	* when the ref clock comes after reset, internal synced
	301	* reset time is too short, cannot meet the requirement.
	302	* add one ~10us delay here.
	303	*/
	304	udelay(10);
3fce0e88 TH	305	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	306	IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
	307
a2fa6f64 RZ	308	/* allow the clocks to stabilize */
	309	usleep_range(200, 500);
	310
bc9ef770	311	/* Some boards don't have PCIe reset GPIO. */
5c5fb40d PŠ	312	if (imx6_pcie->reset_gpio) {
5c5fb40d PŠ	313	gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 0);
bc9ef770	314	msleep(100);
5c5fb40d	315	gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1);
bc9ef770	316	}
bb38919e SC	317	return 0;
bb38919e SC	318
57526136 LS	319	err_pcie:
	320	clk_disable_unprepare(imx6_pcie->pcie_bus);
	321	err_pcie_bus:
	322	clk_disable_unprepare(imx6_pcie->pcie_phy);
	323	err_pcie_phy:
bb38919e SC	324	return ret;
	325
	326	}
	327
	328	static void imx6_pcie_init_phy(struct pcie_port *pp)
	329	{
	330	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	331
	332	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	333	IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	334
	335	/* configure constant input signal to the pcie ctrl and phy */
	336	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	337	IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
	338	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	339	IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
	340
	341	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
28e3abe5 JW	342	IMX6Q_GPR8_TX_DEEMPH_GEN1,
28e3abe5 JW	343	imx6_pcie->tx_deemph_gen1 << 0);
bb38919e	344	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
28e3abe5 JW	345	IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
28e3abe5 JW	346	imx6_pcie->tx_deemph_gen2_3p5db << 6);
bb38919e	347	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
28e3abe5 JW	348	IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
28e3abe5 JW	349	imx6_pcie->tx_deemph_gen2_6db << 12);
bb38919e	350	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
28e3abe5 JW	351	IMX6Q_GPR8_TX_SWING_FULL,
28e3abe5 JW	352	imx6_pcie->tx_swing_full << 18);
bb38919e	353	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
28e3abe5 JW	354	IMX6Q_GPR8_TX_SWING_LOW,
28e3abe5 JW	355	imx6_pcie->tx_swing_low << 25);
bb38919e SC	356	}
bb38919e SC	357
66a60f93 MV	358	static int imx6_pcie_wait_for_link(struct pcie_port *pp)
66a60f93 MV	359	{
886bc5ce JP	360	/* check if the link is up or not */
	361	if (!dw_pcie_wait_for_link(pp))
	362	return 0;
66a60f93	363
6cbb247e BH	364	dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
	365	readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
	366	readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
886bc5ce	367	return -ETIMEDOUT;
66a60f93 MV	368	}
66a60f93 MV	369
a0427464 TK	370	static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
a0427464 TK	371	{
1c7fae18	372	u32 tmp;
a0427464 TK	373	unsigned int retries;
	374
	375	for (retries = 0; retries < 200; retries++) {
	376	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	377	/* Test if the speed change finished. */
	378	if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
	379	return 0;
	380	usleep_range(100, 1000);
	381	}
	382
	383	dev_err(pp->dev, "Speed change timeout\n");
	384	return -EINVAL;
66a60f93 MV	385	}
66a60f93 MV	386
d1dc9749 LS	387	static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
	388	{
	389	struct pcie_port *pp = arg;
	390
	391	return dw_handle_msi_irq(pp);
	392	}
	393
fd5da208	394	static int imx6_pcie_establish_link(struct pcie_port *pp)
bb38919e	395	{
bb38919e	396	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
1c7fae18	397	u32 tmp;
a0427464	398	int ret;
fa33a6d8 MV	399
	400	/*
	401	* Force Gen1 operation when starting the link. In case the link is
	402	* started in Gen2 mode, there is a possibility the devices on the
	403	* bus will not be detected at all. This happens with PCIe switches.
	404	*/
	405	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	406	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	407	tmp \|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
	408	writel(tmp, pp->dbi_base + PCIE_RC_LCR);
	409
	410	/* Start LTSSM. */
	411	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	412	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
	413
	414	ret = imx6_pcie_wait_for_link(pp);
54a47a83 LS	415	if (ret) {
	416	dev_info(pp->dev, "Link never came up\n");
	417	goto err_reset_phy;
	418	}
fa33a6d8 MV	419
	420	/* Allow Gen2 mode after the link is up. */
	421	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	422	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	423	tmp \|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
	424	writel(tmp, pp->dbi_base + PCIE_RC_LCR);
	425
	426	/*
	427	* Start Directed Speed Change so the best possible speed both link
	428	* partners support can be negotiated.
	429	*/
	430	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	431	tmp \|= PORT_LOGIC_SPEED_CHANGE;
	432	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	433
a0427464 TK	434	ret = imx6_pcie_wait_for_speed_change(pp);
	435	if (ret) {
	436	dev_err(pp->dev, "Failed to bring link up!\n");
54a47a83	437	goto err_reset_phy;
fa33a6d8 MV	438	}
	439
	440	/* Make sure link training is finished as well! */
a0427464	441	ret = imx6_pcie_wait_for_link(pp);
fa33a6d8 MV	442	if (ret) {
fa33a6d8 MV	443	dev_err(pp->dev, "Failed to bring link up!\n");
54a47a83	444	goto err_reset_phy;
fa33a6d8 MV	445	}
fa33a6d8 MV	446
2393f79c	447	tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
a0427464	448	dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
54a47a83	449
a0427464	450	return 0;
54a47a83 LS	451
	452	err_reset_phy:
	453	dev_dbg(pp->dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
	454	readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
	455	readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
	456	imx6_pcie_reset_phy(pp);
	457
	458	return ret;
fa33a6d8 MV	459	}
	460
	461	static void imx6_pcie_host_init(struct pcie_port *pp)
	462	{
bb38919e SC	463	imx6_pcie_assert_core_reset(pp);
	464
	465	imx6_pcie_init_phy(pp);
	466
	467	imx6_pcie_deassert_core_reset(pp);
	468
	469	dw_pcie_setup_rc(pp);
	470
fd5da208	471	imx6_pcie_establish_link(pp);
d1dc9749 LS	472
	473	if (IS_ENABLED(CONFIG_PCI_MSI))
	474	dw_pcie_msi_init(pp);
bb38919e SC	475	}
	476
	477	static int imx6_pcie_link_up(struct pcie_port *pp)
	478	{
4d107d3b LS	479	return readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) &
4d107d3b LS	480	PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
bb38919e SC	481	}
	482
	483	static struct pcie_host_ops imx6_pcie_host_ops = {
	484	.link_up = imx6_pcie_link_up,
	485	.host_init = imx6_pcie_host_init,
	486	};
	487
44cb5e94	488	static int __init imx6_add_pcie_port(struct pcie_port *pp,
bb38919e SC	489	struct platform_device *pdev)
	490	{
	491	int ret;
	492
d1dc9749 LS	493	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	494	pp->msi_irq = platform_get_irq_byname(pdev, "msi");
	495	if (pp->msi_irq <= 0) {
	496	dev_err(&pdev->dev, "failed to get MSI irq\n");
	497	return -ENODEV;
	498	}
	499
	500	ret = devm_request_irq(&pdev->dev, pp->msi_irq,
d88a7ef9	501	imx6_pcie_msi_handler,
8ff0ef99 GS	502	IRQF_SHARED \| IRQF_NO_THREAD,
8ff0ef99 GS	503	"mx6-pcie-msi", pp);
d1dc9749 LS	504	if (ret) {
d1dc9749 LS	505	dev_err(&pdev->dev, "failed to request MSI irq\n");
89b2d4f1	506	return ret;
d1dc9749 LS	507	}
	508	}
	509
bb38919e SC	510	pp->root_bus_nr = -1;
	511	pp->ops = &imx6_pcie_host_ops;
	512
bb38919e SC	513	ret = dw_pcie_host_init(pp);
	514	if (ret) {
	515	dev_err(&pdev->dev, "failed to initialize host\n");
	516	return ret;
	517	}
	518
	519	return 0;
	520	}
	521
	522	static int __init imx6_pcie_probe(struct platform_device *pdev)
	523	{
	524	struct imx6_pcie *imx6_pcie;
	525	struct pcie_port *pp;
bb38919e	526	struct resource *dbi_base;
28e3abe5	527	struct device_node *node = pdev->dev.of_node;
bb38919e SC	528	int ret;
	529
	530	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
	531	if (!imx6_pcie)
	532	return -ENOMEM;
	533
	534	pp = &imx6_pcie->pp;
	535	pp->dev = &pdev->dev;
	536
	537	/* Added for PCI abort handling */
	538	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
	539	"imprecise external abort");
	540
	541	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bb38919e	542	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
b391bf31 FE	543	if (IS_ERR(pp->dbi_base))
b391bf31 FE	544	return PTR_ERR(pp->dbi_base);
bb38919e SC	545
bb38919e SC	546	/* Fetch GPIOs */
5c5fb40d PŠ	547	imx6_pcie->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
5c5fb40d PŠ	548	GPIOD_OUT_LOW);
bb38919e	549
bb38919e	550	/* Fetch clocks */
57526136 LS	551	imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
57526136 LS	552	if (IS_ERR(imx6_pcie->pcie_phy)) {
bb38919e	553	dev_err(&pdev->dev,
57526136 LS	554	"pcie_phy clock source missing or invalid\n");
57526136 LS	555	return PTR_ERR(imx6_pcie->pcie_phy);
bb38919e SC	556	}
bb38919e SC	557
57526136 LS	558	imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
57526136 LS	559	if (IS_ERR(imx6_pcie->pcie_bus)) {
bb38919e	560	dev_err(&pdev->dev,
57526136 LS	561	"pcie_bus clock source missing or invalid\n");
57526136 LS	562	return PTR_ERR(imx6_pcie->pcie_bus);
bb38919e SC	563	}
bb38919e SC	564
57526136 LS	565	imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
57526136 LS	566	if (IS_ERR(imx6_pcie->pcie)) {
bb38919e	567	dev_err(&pdev->dev,
57526136 LS	568	"pcie clock source missing or invalid\n");
57526136 LS	569	return PTR_ERR(imx6_pcie->pcie);
bb38919e SC	570	}
	571
	572	/* Grab GPR config register range */
	573	imx6_pcie->iomuxc_gpr =
	574	syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	575	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
	576	dev_err(&pdev->dev, "unable to find iomuxc registers\n");
b391bf31	577	return PTR_ERR(imx6_pcie->iomuxc_gpr);
bb38919e	578	}
28e3abe5 JW	579
	580	/* Grab PCIe PHY Tx Settings */
	581	if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
	582	&imx6_pcie->tx_deemph_gen1))
	583	imx6_pcie->tx_deemph_gen1 = 0;
	584
	585	if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
	586	&imx6_pcie->tx_deemph_gen2_3p5db))
	587	imx6_pcie->tx_deemph_gen2_3p5db = 0;
	588
	589	if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
	590	&imx6_pcie->tx_deemph_gen2_6db))
	591	imx6_pcie->tx_deemph_gen2_6db = 20;
	592
	593	if (of_property_read_u32(node, "fsl,tx-swing-full",
	594	&imx6_pcie->tx_swing_full))
	595	imx6_pcie->tx_swing_full = 127;
	596
	597	if (of_property_read_u32(node, "fsl,tx-swing-low",
	598	&imx6_pcie->tx_swing_low))
	599	imx6_pcie->tx_swing_low = 127;
bb38919e SC	600
	601	ret = imx6_add_pcie_port(pp, pdev);
	602	if (ret < 0)
b391bf31	603	return ret;
bb38919e SC	604
	605	platform_set_drvdata(pdev, imx6_pcie);
	606	return 0;
bb38919e SC	607	}
bb38919e SC	608
3e3e406e LS	609	static void imx6_pcie_shutdown(struct platform_device *pdev)
	610	{
	611	struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
	612
	613	/* bring down link, so bootloader gets clean state in case of reboot */
	614	imx6_pcie_assert_core_reset(&imx6_pcie->pp);
	615	}
	616
bb38919e SC	617	static const struct of_device_id imx6_pcie_of_match[] = {
	618	{ .compatible = "fsl,imx6q-pcie", },
	619	{},
	620	};
	621	MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
	622
	623	static struct platform_driver imx6_pcie_driver = {
	624	.driver = {
	625	.name = "imx6q-pcie",
8bcadbe1	626	.of_match_table = imx6_pcie_of_match,
bb38919e	627	},
3e3e406e	628	.shutdown = imx6_pcie_shutdown,
bb38919e SC	629	};
	630
	631	/* Freescale PCIe driver does not allow module unload */
	632
	633	static int __init imx6_pcie_init(void)
	634	{
	635	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
	636	}
61da50da	637	module_init(imx6_pcie_init);
bb38919e SC	638
	639	MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
	640	MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
	641	MODULE_LICENSE("GPL v2");