[linux-2.6-block.git] / drivers / pci / dwc / pcie-designware.h

/*
 * Synopsys Designware PCIe host controller driver
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Author: Jingoo Han <jg1.han@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _PCIE_DESIGNWARE_H
#define _PCIE_DESIGNWARE_H

/* Parameters for the waiting for link up routine */
#define LINK_WAIT_MAX_RETRIES		10
#define LINK_WAIT_USLEEP_MIN		90000
#define LINK_WAIT_USLEEP_MAX		100000

/* Parameters for the waiting for iATU enabled routine */
#define LINK_WAIT_MAX_IATU_RETRIES	5
#define LINK_WAIT_IATU_MIN		9000
#define LINK_WAIT_IATU_MAX		10000

/* Synopsys-specific PCIe configuration registers */
#define PCIE_PORT_LINK_CONTROL		0x710
#define PORT_LINK_MODE_MASK		(0x3f << 16)
#define PORT_LINK_MODE_1_LANES		(0x1 << 16)
#define PORT_LINK_MODE_2_LANES		(0x3 << 16)
#define PORT_LINK_MODE_4_LANES		(0x7 << 16)
#define PORT_LINK_MODE_8_LANES		(0xf << 16)

#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1f << 8)
#define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
#define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
#define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)
#define PORT_LOGIC_LINK_WIDTH_8_LANES	(0x8 << 8)

#define PCIE_MSI_ADDR_LO		0x820
#define PCIE_MSI_ADDR_HI		0x824
#define PCIE_MSI_INTR0_ENABLE		0x828
#define PCIE_MSI_INTR0_MASK		0x82C
#define PCIE_MSI_INTR0_STATUS		0x830

#define PCIE_ATU_VIEWPORT		0x900
#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
#define PCIE_ATU_REGION_INDEX2		(0x2 << 0)
#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
#define PCIE_ATU_CR1			0x904
#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
#define PCIE_ATU_TYPE_IO		(0x2 << 0)
#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
#define PCIE_ATU_CR2			0x908
#define PCIE_ATU_ENABLE			(0x1 << 31)
#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
#define PCIE_ATU_LOWER_BASE		0x90C
#define PCIE_ATU_UPPER_BASE		0x910
#define PCIE_ATU_LIMIT			0x914
#define PCIE_ATU_LOWER_TARGET		0x918
#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET		0x91C

/*
 * iATU Unroll-specific register definitions
 * From 4.80 core version the address translation will be made by unroll
 */
#define PCIE_ATU_UNR_REGION_CTRL1	0x00
#define PCIE_ATU_UNR_REGION_CTRL2	0x04
#define PCIE_ATU_UNR_LOWER_BASE		0x08
#define PCIE_ATU_UNR_UPPER_BASE		0x0C
#define PCIE_ATU_UNR_LIMIT		0x10
#define PCIE_ATU_UNR_LOWER_TARGET	0x14
#define PCIE_ATU_UNR_UPPER_TARGET	0x18

/* Register address builder */
#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)	\
			((0x3 << 20) | ((region) << 9))

/*
 * Maximum number of MSI IRQs can be 256 per controller. But keep
 * it 32 as of now. Probably we will never need more than 32. If needed,
 * then increment it in multiple of 32.
 */
#define MAX_MSI_IRQS			32
#define MAX_MSI_CTRLS			(MAX_MSI_IRQS / 32)

struct pcie_port;
struct dw_pcie;

struct dw_pcie_host_ops {
	int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
	int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
	int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
			     unsigned int devfn, int where, int size, u32 *val);
	int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
			     unsigned int devfn, int where, int size, u32 val);
	void (*host_init)(struct pcie_port *pp);
	void (*msi_set_irq)(struct pcie_port *pp, int irq);
	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
	phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
	void (*scan_bus)(struct pcie_port *pp);
	int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
};

struct pcie_port {
	u8			root_bus_nr;
	u64			cfg0_base;
	void __iomem		*va_cfg0_base;
	u32			cfg0_size;
	u64			cfg1_base;
	void __iomem		*va_cfg1_base;
	u32			cfg1_size;
	resource_size_t		io_base;
	phys_addr_t		io_bus_addr;
	u32			io_size;
	u64			mem_base;
	phys_addr_t		mem_bus_addr;
	u32			mem_size;
	struct resource		*cfg;
	struct resource		*io;
	struct resource		*mem;
	struct resource		*busn;
	int			irq;
	struct dw_pcie_host_ops	*ops;
	int			msi_irq;
	struct irq_domain	*irq_domain;
	unsigned long		msi_data;
	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
};

struct dw_pcie_ops {
	u32	(*readl_dbi)(struct dw_pcie *pcie, u32 reg);
	void	(*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
	int	(*link_up)(struct dw_pcie *pcie);
};

struct dw_pcie {
	struct device		*dev;
	void __iomem		*dbi_base;
	u32			num_viewport;
	u8			iatu_unroll_enabled;
	struct pcie_port	pp;
	const struct dw_pcie_ops *ops;
};

#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)

int dw_pcie_read(void __iomem *addr, int size, u32 *val);
int dw_pcie_write(void __iomem *addr, int size, u32 val);
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
void dw_pcie_msi_init(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);

u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
int dw_pcie_link_up(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
#endif /* _PCIE_DESIGNWARE_H */
Commit	Line	Data
4b1ced84 JH	1	/*
	2	* Synopsys Designware PCIe host controller driver
	3	*
	4	* Copyright (C) 2013 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Author: Jingoo Han <jg1.han@samsung.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
18edf451 SJ	14	#ifndef _PCIE_DESIGNWARE_H
	15	#define _PCIE_DESIGNWARE_H
	16
b90dc392 KVA	17	/* Parameters for the waiting for link up routine */
	18	#define LINK_WAIT_MAX_RETRIES 10
	19	#define LINK_WAIT_USLEEP_MIN 90000
	20	#define LINK_WAIT_USLEEP_MAX 100000
	21
	22	/* Parameters for the waiting for iATU enabled routine */
	23	#define LINK_WAIT_MAX_IATU_RETRIES 5
	24	#define LINK_WAIT_IATU_MIN 9000
	25	#define LINK_WAIT_IATU_MAX 10000
	26
	27	/* Synopsys-specific PCIe configuration registers */
	28	#define PCIE_PORT_LINK_CONTROL 0x710
	29	#define PORT_LINK_MODE_MASK (0x3f << 16)
	30	#define PORT_LINK_MODE_1_LANES (0x1 << 16)
	31	#define PORT_LINK_MODE_2_LANES (0x3 << 16)
	32	#define PORT_LINK_MODE_4_LANES (0x7 << 16)
	33	#define PORT_LINK_MODE_8_LANES (0xf << 16)
	34
	35	#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
	36	#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
	37	#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
	38	#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
	39	#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
	40	#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
	41	#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
	42
	43	#define PCIE_MSI_ADDR_LO 0x820
	44	#define PCIE_MSI_ADDR_HI 0x824
	45	#define PCIE_MSI_INTR0_ENABLE 0x828
	46	#define PCIE_MSI_INTR0_MASK 0x82C
	47	#define PCIE_MSI_INTR0_STATUS 0x830
	48
	49	#define PCIE_ATU_VIEWPORT 0x900
	50	#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
	51	#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
	52	#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
	53	#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
	54	#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
	55	#define PCIE_ATU_CR1 0x904
	56	#define PCIE_ATU_TYPE_MEM (0x0 << 0)
	57	#define PCIE_ATU_TYPE_IO (0x2 << 0)
	58	#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
	59	#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
	60	#define PCIE_ATU_CR2 0x908
	61	#define PCIE_ATU_ENABLE (0x1 << 31)
	62	#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
	63	#define PCIE_ATU_LOWER_BASE 0x90C
	64	#define PCIE_ATU_UPPER_BASE 0x910
	65	#define PCIE_ATU_LIMIT 0x914
	66	#define PCIE_ATU_LOWER_TARGET 0x918
	67	#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
	68	#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
	69	#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
	70	#define PCIE_ATU_UPPER_TARGET 0x91C
	71
	72	/*
	73	* iATU Unroll-specific register definitions
	74	* From 4.80 core version the address translation will be made by unroll
	75	*/
	76	#define PCIE_ATU_UNR_REGION_CTRL1 0x00
	77	#define PCIE_ATU_UNR_REGION_CTRL2 0x04
	78	#define PCIE_ATU_UNR_LOWER_BASE 0x08
	79	#define PCIE_ATU_UNR_UPPER_BASE 0x0C
	80	#define PCIE_ATU_UNR_LIMIT 0x10
81	#define PCIE_ATU_UNR_LOWER_TARGET 0x14
82	#define PCIE_ATU_UNR_UPPER_TARGET 0x18
83
84	/* Register address builder */
85	#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
86	((0x3 << 20) \| ((region) << 9))
87
f342d940 JH	88	/*
	89	* Maximum number of MSI IRQs can be 256 per controller. But keep
	90	* it 32 as of now. Probably we will never need more than 32. If needed,
	91	* then increment it in multiple of 32.
	92	*/
	93	#define MAX_MSI_IRQS 32
	94	#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
	95
442ec4c0 KVA	96	struct pcie_port;
	97	struct dw_pcie;
	98
	99	struct dw_pcie_host_ops {
	100	int (rd_own_conf)(struct pcie_port pp, int where, int size, u32 *val);
	101	int (wr_own_conf)(struct pcie_port pp, int where, int size, u32 val);
	102	int (rd_other_conf)(struct pcie_port pp, struct pci_bus *bus,
	103	unsigned int devfn, int where, int size, u32 *val);
	104	int (wr_other_conf)(struct pcie_port pp, struct pci_bus *bus,
	105	unsigned int devfn, int where, int size, u32 val);
	106	void (host_init)(struct pcie_port pp);
	107	void (msi_set_irq)(struct pcie_port pp, int irq);
	108	void (msi_clear_irq)(struct pcie_port pp, int irq);
	109	phys_addr_t (get_msi_addr)(struct pcie_port pp);
	110	u32 (get_msi_data)(struct pcie_port pp, int pos);
	111	void (scan_bus)(struct pcie_port pp);
	112	int (msi_host_init)(struct pcie_port pp, struct msi_controller *chip);
	113	};
	114
4b1ced84	115	struct pcie_port {
4b1ced84	116	u8 root_bus_nr;
4b1ced84 JH	117	u64 cfg0_base;
4b1ced84 JH	118	void __iomem *va_cfg0_base;
adf70fc0	119	u32 cfg0_size;
4b1ced84 JH	120	u64 cfg1_base;
4b1ced84 JH	121	void __iomem *va_cfg1_base;
adf70fc0	122	u32 cfg1_size;
0021d22b	123	resource_size_t io_base;
adf70fc0 PA	124	phys_addr_t io_bus_addr;
adf70fc0 PA	125	u32 io_size;
4b1ced84	126	u64 mem_base;
adf70fc0 PA	127	phys_addr_t mem_bus_addr;
adf70fc0 PA	128	u32 mem_size;
0021d22b ZW	129	struct resource *cfg;
	130	struct resource *io;
	131	struct resource *mem;
	132	struct resource *busn;
4b1ced84	133	int irq;
442ec4c0	134	struct dw_pcie_host_ops *ops;
f342d940	135	int msi_irq;
904d0e78	136	struct irq_domain *irq_domain;
f342d940 JH	137	unsigned long msi_data;
f342d940 JH	138	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
4b1ced84 JH	139	};
4b1ced84 JH	140
442ec4c0 KVA	141	struct dw_pcie_ops {
	142	u32 (readl_dbi)(struct dw_pcie pcie, u32 reg);
	143	void (writel_dbi)(struct dw_pcie pcie, u32 reg, u32 val);
	144	int (link_up)(struct dw_pcie pcie);
4b1ced84 JH	145	};
4b1ced84 JH	146
442ec4c0 KVA	147	struct dw_pcie {
	148	struct device *dev;
	149	void __iomem *dbi_base;
442ec4c0 KVA	150	u32 num_viewport;
	151	u8 iatu_unroll_enabled;
	152	struct pcie_port pp;
	153	const struct dw_pcie_ops *ops;
	154	};
	155
	156	#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
	157
19ce01cc KVA	158	int dw_pcie_read(void __iomem addr, int size, u32 val);
19ce01cc KVA	159	int dw_pcie_write(void __iomem *addr, int size, u32 val);
7f4f16ee	160	irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
f342d940	161	void dw_pcie_msi_init(struct pcie_port *pp);
4b1ced84 JH	162	void dw_pcie_setup_rc(struct pcie_port *pp);
4b1ced84 JH	163	int dw_pcie_host_init(struct pcie_port *pp);
18edf451	164
442ec4c0 KVA	165	u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
	166	void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
	167	int dw_pcie_link_up(struct dw_pcie *pci);
	168	int dw_pcie_wait_for_link(struct dw_pcie *pci);
18edf451	169	#endif /* _PCIE_DESIGNWARE_H */