Commit | Line | Data |
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fce8a7bb JM |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2012 Intel Corporation. All rights reserved. | |
e26a5843 | 8 | * Copyright (C) 2015 EMC Corporation. All Rights Reserved. |
fce8a7bb JM |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * BSD LICENSE | |
15 | * | |
16 | * Copyright(c) 2012 Intel Corporation. All rights reserved. | |
e26a5843 | 17 | * Copyright (C) 2015 EMC Corporation. All Rights Reserved. |
fce8a7bb JM |
18 | * |
19 | * Redistribution and use in source and binary forms, with or without | |
20 | * modification, are permitted provided that the following conditions | |
21 | * are met: | |
22 | * | |
23 | * * Redistributions of source code must retain the above copyright | |
24 | * notice, this list of conditions and the following disclaimer. | |
25 | * * Redistributions in binary form must reproduce the above copy | |
26 | * notice, this list of conditions and the following disclaimer in | |
27 | * the documentation and/or other materials provided with the | |
28 | * distribution. | |
29 | * * Neither the name of Intel Corporation nor the names of its | |
30 | * contributors may be used to endorse or promote products derived | |
31 | * from this software without specific prior written permission. | |
32 | * | |
33 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
34 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
35 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
36 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
37 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
38 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
39 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
40 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
41 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
42 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
43 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
44 | * | |
45 | * Intel PCIe NTB Linux driver | |
46 | * | |
47 | * Contact Information: | |
48 | * Jon Mason <jon.mason@intel.com> | |
49 | */ | |
e26a5843 | 50 | |
fce8a7bb | 51 | #include <linux/debugfs.h> |
113bf1c9 | 52 | #include <linux/delay.h> |
fce8a7bb JM |
53 | #include <linux/init.h> |
54 | #include <linux/interrupt.h> | |
55 | #include <linux/module.h> | |
56 | #include <linux/pci.h> | |
113bf1c9 | 57 | #include <linux/random.h> |
fce8a7bb | 58 | #include <linux/slab.h> |
e26a5843 AH |
59 | #include <linux/ntb.h> |
60 | ||
ec110bc7 | 61 | #include "ntb_hw_intel.h" |
fce8a7bb | 62 | |
e26a5843 AH |
63 | #define NTB_NAME "ntb_hw_intel" |
64 | #define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver" | |
65 | #define NTB_VER "2.0" | |
fce8a7bb | 66 | |
e26a5843 | 67 | MODULE_DESCRIPTION(NTB_DESC); |
fce8a7bb JM |
68 | MODULE_VERSION(NTB_VER); |
69 | MODULE_LICENSE("Dual BSD/GPL"); | |
70 | MODULE_AUTHOR("Intel Corporation"); | |
71 | ||
e26a5843 AH |
72 | #define bar0_off(base, bar) ((base) + ((bar) << 2)) |
73 | #define bar2_off(base, bar) bar0_off(base, (bar) - 2) | |
74 | ||
2f887b9a DJ |
75 | static const struct intel_ntb_reg atom_reg; |
76 | static const struct intel_ntb_alt_reg atom_pri_reg; | |
77 | static const struct intel_ntb_alt_reg atom_sec_reg; | |
78 | static const struct intel_ntb_alt_reg atom_b2b_reg; | |
79 | static const struct intel_ntb_xlat_reg atom_pri_xlat; | |
80 | static const struct intel_ntb_xlat_reg atom_sec_xlat; | |
81 | static const struct intel_ntb_reg xeon_reg; | |
82 | static const struct intel_ntb_alt_reg xeon_pri_reg; | |
83 | static const struct intel_ntb_alt_reg xeon_sec_reg; | |
84 | static const struct intel_ntb_alt_reg xeon_b2b_reg; | |
85 | static const struct intel_ntb_xlat_reg xeon_pri_xlat; | |
86 | static const struct intel_ntb_xlat_reg xeon_sec_xlat; | |
87 | static struct intel_b2b_addr xeon_b2b_usd_addr; | |
88 | static struct intel_b2b_addr xeon_b2b_dsd_addr; | |
e26a5843 AH |
89 | static const struct ntb_dev_ops intel_ntb_ops; |
90 | ||
91 | static const struct file_operations intel_ntb_debugfs_info; | |
1517a3f2 JM |
92 | static struct dentry *debugfs_dir; |
93 | ||
42fefc86 AH |
94 | static int b2b_mw_idx = -1; |
95 | module_param(b2b_mw_idx, int, 0644); | |
96 | MODULE_PARM_DESC(b2b_mw_idx, "Use this mw idx to access the peer ntb. A " | |
97 | "value of zero or positive starts from first mw idx, and a " | |
98 | "negative value starts from last mw idx. Both sides MUST " | |
99 | "set the same value here!"); | |
100 | ||
101 | static unsigned int b2b_mw_share; | |
102 | module_param(b2b_mw_share, uint, 0644); | |
103 | MODULE_PARM_DESC(b2b_mw_share, "If the b2b mw is large enough, configure the " | |
104 | "ntb so that the peer ntb only occupies the first half of " | |
105 | "the mw, so the second half can still be used as a mw. Both " | |
106 | "sides MUST set the same value here!"); | |
107 | ||
2f887b9a DJ |
108 | module_param_named(xeon_b2b_usd_bar2_addr64, |
109 | xeon_b2b_usd_addr.bar2_addr64, ullong, 0644); | |
110 | MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, | |
111 | "XEON B2B USD BAR 2 64-bit address"); | |
112 | ||
113 | module_param_named(xeon_b2b_usd_bar4_addr64, | |
114 | xeon_b2b_usd_addr.bar4_addr64, ullong, 0644); | |
115 | MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, | |
116 | "XEON B2B USD BAR 4 64-bit address"); | |
117 | ||
118 | module_param_named(xeon_b2b_usd_bar4_addr32, | |
119 | xeon_b2b_usd_addr.bar4_addr32, ullong, 0644); | |
120 | MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, | |
121 | "XEON B2B USD split-BAR 4 32-bit address"); | |
122 | ||
123 | module_param_named(xeon_b2b_usd_bar5_addr32, | |
124 | xeon_b2b_usd_addr.bar5_addr32, ullong, 0644); | |
125 | MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, | |
126 | "XEON B2B USD split-BAR 5 32-bit address"); | |
127 | ||
128 | module_param_named(xeon_b2b_dsd_bar2_addr64, | |
129 | xeon_b2b_dsd_addr.bar2_addr64, ullong, 0644); | |
130 | MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, | |
131 | "XEON B2B DSD BAR 2 64-bit address"); | |
132 | ||
133 | module_param_named(xeon_b2b_dsd_bar4_addr64, | |
134 | xeon_b2b_dsd_addr.bar4_addr64, ullong, 0644); | |
135 | MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, | |
136 | "XEON B2B DSD BAR 4 64-bit address"); | |
137 | ||
138 | module_param_named(xeon_b2b_dsd_bar4_addr32, | |
139 | xeon_b2b_dsd_addr.bar4_addr32, ullong, 0644); | |
140 | MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, | |
141 | "XEON B2B DSD split-BAR 4 32-bit address"); | |
142 | ||
143 | module_param_named(xeon_b2b_dsd_bar5_addr32, | |
144 | xeon_b2b_dsd_addr.bar5_addr32, ullong, 0644); | |
145 | MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, | |
146 | "XEON B2B DSD split-BAR 5 32-bit address"); | |
42fefc86 | 147 | |
e26a5843 AH |
148 | #ifndef ioread64 |
149 | #ifdef readq | |
150 | #define ioread64 readq | |
151 | #else | |
152 | #define ioread64 _ioread64 | |
153 | static inline u64 _ioread64(void __iomem *mmio) | |
b775e85b | 154 | { |
e26a5843 | 155 | u64 low, high; |
b775e85b | 156 | |
e26a5843 AH |
157 | low = ioread32(mmio); |
158 | high = ioread32(mmio + sizeof(u32)); | |
159 | return low | (high << 32); | |
160 | } | |
161 | #endif | |
162 | #endif | |
163 | ||
164 | #ifndef iowrite64 | |
165 | #ifdef writeq | |
166 | #define iowrite64 writeq | |
167 | #else | |
168 | #define iowrite64 _iowrite64 | |
169 | static inline void _iowrite64(u64 val, void __iomem *mmio) | |
170 | { | |
171 | iowrite32(val, mmio); | |
172 | iowrite32(val >> 32, mmio + sizeof(u32)); | |
b775e85b | 173 | } |
e26a5843 AH |
174 | #endif |
175 | #endif | |
b775e85b | 176 | |
2f887b9a | 177 | static inline int pdev_is_atom(struct pci_dev *pdev) |
b775e85b | 178 | { |
e26a5843 | 179 | switch (pdev->device) { |
b775e85b DJ |
180 | case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD: |
181 | return 1; | |
b775e85b | 182 | } |
b775e85b DJ |
183 | return 0; |
184 | } | |
185 | ||
2f887b9a | 186 | static inline int pdev_is_xeon(struct pci_dev *pdev) |
069684e8 | 187 | { |
e26a5843 | 188 | switch (pdev->device) { |
069684e8 DJ |
189 | case PCI_DEVICE_ID_INTEL_NTB_SS_JSF: |
190 | case PCI_DEVICE_ID_INTEL_NTB_SS_SNB: | |
191 | case PCI_DEVICE_ID_INTEL_NTB_SS_IVT: | |
192 | case PCI_DEVICE_ID_INTEL_NTB_SS_HSX: | |
193 | case PCI_DEVICE_ID_INTEL_NTB_PS_JSF: | |
194 | case PCI_DEVICE_ID_INTEL_NTB_PS_SNB: | |
195 | case PCI_DEVICE_ID_INTEL_NTB_PS_IVT: | |
196 | case PCI_DEVICE_ID_INTEL_NTB_PS_HSX: | |
197 | case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF: | |
198 | case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB: | |
199 | case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT: | |
200 | case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX: | |
e26a5843 | 201 | return 1; |
069684e8 | 202 | } |
e26a5843 | 203 | return 0; |
069684e8 DJ |
204 | } |
205 | ||
e26a5843 | 206 | static inline void ndev_reset_unsafe_flags(struct intel_ntb_dev *ndev) |
fce8a7bb | 207 | { |
e26a5843 AH |
208 | ndev->unsafe_flags = 0; |
209 | ndev->unsafe_flags_ignore = 0; | |
210 | ||
211 | /* Only B2B has a workaround to avoid SDOORBELL */ | |
212 | if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) | |
213 | if (!ntb_topo_is_b2b(ndev->ntb.topo)) | |
214 | ndev->unsafe_flags |= NTB_UNSAFE_DB; | |
215 | ||
216 | /* No low level workaround to avoid SB01BASE */ | |
217 | if (ndev->hwerr_flags & NTB_HWERR_SB01BASE_LOCKUP) { | |
218 | ndev->unsafe_flags |= NTB_UNSAFE_DB; | |
219 | ndev->unsafe_flags |= NTB_UNSAFE_SPAD; | |
220 | } | |
fce8a7bb JM |
221 | } |
222 | ||
e26a5843 AH |
223 | static inline int ndev_is_unsafe(struct intel_ntb_dev *ndev, |
224 | unsigned long flag) | |
fce8a7bb | 225 | { |
e26a5843 | 226 | return !!(flag & ndev->unsafe_flags & ~ndev->unsafe_flags_ignore); |
fce8a7bb JM |
227 | } |
228 | ||
e26a5843 AH |
229 | static inline int ndev_ignore_unsafe(struct intel_ntb_dev *ndev, |
230 | unsigned long flag) | |
e8aeb60c | 231 | { |
e26a5843 AH |
232 | flag &= ndev->unsafe_flags; |
233 | ndev->unsafe_flags_ignore |= flag; | |
e8aeb60c | 234 | |
e26a5843 | 235 | return !!flag; |
e8aeb60c JM |
236 | } |
237 | ||
e26a5843 | 238 | static int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx) |
fce8a7bb | 239 | { |
e26a5843 | 240 | if (idx < 0 || idx > ndev->mw_count) |
fce8a7bb | 241 | return -EINVAL; |
e26a5843 AH |
242 | return ndev->reg->mw_bar[idx]; |
243 | } | |
fce8a7bb | 244 | |
e26a5843 AH |
245 | static inline int ndev_db_addr(struct intel_ntb_dev *ndev, |
246 | phys_addr_t *db_addr, resource_size_t *db_size, | |
247 | phys_addr_t reg_addr, unsigned long reg) | |
248 | { | |
fd839bf8 DJ |
249 | if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB)) |
250 | pr_warn_once("%s: NTB unsafe doorbell access", __func__); | |
e8aeb60c | 251 | |
e26a5843 AH |
252 | if (db_addr) { |
253 | *db_addr = reg_addr + reg; | |
254 | dev_dbg(ndev_dev(ndev), "Peer db addr %llx\n", *db_addr); | |
255 | } | |
fce8a7bb | 256 | |
e26a5843 AH |
257 | if (db_size) { |
258 | *db_size = ndev->reg->db_size; | |
259 | dev_dbg(ndev_dev(ndev), "Peer db size %llx\n", *db_size); | |
260 | } | |
fce8a7bb JM |
261 | |
262 | return 0; | |
263 | } | |
264 | ||
e26a5843 AH |
265 | static inline u64 ndev_db_read(struct intel_ntb_dev *ndev, |
266 | void __iomem *mmio) | |
fce8a7bb | 267 | { |
fd839bf8 DJ |
268 | if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB)) |
269 | pr_warn_once("%s: NTB unsafe doorbell access", __func__); | |
fce8a7bb | 270 | |
e26a5843 AH |
271 | return ndev->reg->db_ioread(mmio); |
272 | } | |
273 | ||
274 | static inline int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits, | |
275 | void __iomem *mmio) | |
276 | { | |
fd839bf8 DJ |
277 | if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB)) |
278 | pr_warn_once("%s: NTB unsafe doorbell access", __func__); | |
fce8a7bb | 279 | |
e26a5843 AH |
280 | if (db_bits & ~ndev->db_valid_mask) |
281 | return -EINVAL; | |
fce8a7bb | 282 | |
e26a5843 | 283 | ndev->reg->db_iowrite(db_bits, mmio); |
e8aeb60c | 284 | |
e26a5843 | 285 | return 0; |
fce8a7bb JM |
286 | } |
287 | ||
e26a5843 AH |
288 | static inline int ndev_db_set_mask(struct intel_ntb_dev *ndev, u64 db_bits, |
289 | void __iomem *mmio) | |
fce8a7bb | 290 | { |
e26a5843 | 291 | unsigned long irqflags; |
fce8a7bb | 292 | |
fd839bf8 DJ |
293 | if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB)) |
294 | pr_warn_once("%s: NTB unsafe doorbell access", __func__); | |
e26a5843 AH |
295 | |
296 | if (db_bits & ~ndev->db_valid_mask) | |
297 | return -EINVAL; | |
fce8a7bb | 298 | |
e26a5843 AH |
299 | spin_lock_irqsave(&ndev->db_mask_lock, irqflags); |
300 | { | |
301 | ndev->db_mask |= db_bits; | |
302 | ndev->reg->db_iowrite(ndev->db_mask, mmio); | |
303 | } | |
304 | spin_unlock_irqrestore(&ndev->db_mask_lock, irqflags); | |
fce8a7bb | 305 | |
e26a5843 | 306 | return 0; |
fce8a7bb JM |
307 | } |
308 | ||
e26a5843 AH |
309 | static inline int ndev_db_clear_mask(struct intel_ntb_dev *ndev, u64 db_bits, |
310 | void __iomem *mmio) | |
fce8a7bb | 311 | { |
e26a5843 | 312 | unsigned long irqflags; |
fce8a7bb | 313 | |
fd839bf8 DJ |
314 | if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB)) |
315 | pr_warn_once("%s: NTB unsafe doorbell access", __func__); | |
e26a5843 AH |
316 | |
317 | if (db_bits & ~ndev->db_valid_mask) | |
318 | return -EINVAL; | |
fce8a7bb | 319 | |
e26a5843 AH |
320 | spin_lock_irqsave(&ndev->db_mask_lock, irqflags); |
321 | { | |
322 | ndev->db_mask &= ~db_bits; | |
323 | ndev->reg->db_iowrite(ndev->db_mask, mmio); | |
324 | } | |
325 | spin_unlock_irqrestore(&ndev->db_mask_lock, irqflags); | |
fce8a7bb | 326 | |
e26a5843 | 327 | return 0; |
fce8a7bb JM |
328 | } |
329 | ||
e26a5843 | 330 | static inline int ndev_vec_mask(struct intel_ntb_dev *ndev, int db_vector) |
fce8a7bb | 331 | { |
e26a5843 | 332 | u64 shift, mask; |
fce8a7bb | 333 | |
e26a5843 AH |
334 | shift = ndev->db_vec_shift; |
335 | mask = BIT_ULL(shift) - 1; | |
fce8a7bb | 336 | |
e26a5843 | 337 | return mask << (shift * db_vector); |
fce8a7bb JM |
338 | } |
339 | ||
e26a5843 AH |
340 | static inline int ndev_spad_addr(struct intel_ntb_dev *ndev, int idx, |
341 | phys_addr_t *spad_addr, phys_addr_t reg_addr, | |
342 | unsigned long reg) | |
fce8a7bb | 343 | { |
fd839bf8 DJ |
344 | if (ndev_is_unsafe(ndev, NTB_UNSAFE_SPAD)) |
345 | pr_warn_once("%s: NTB unsafe scratchpad access", __func__); | |
e26a5843 AH |
346 | |
347 | if (idx < 0 || idx >= ndev->spad_count) | |
fce8a7bb JM |
348 | return -EINVAL; |
349 | ||
e26a5843 AH |
350 | if (spad_addr) { |
351 | *spad_addr = reg_addr + reg + (idx << 2); | |
352 | dev_dbg(ndev_dev(ndev), "Peer spad addr %llx\n", *spad_addr); | |
353 | } | |
fce8a7bb JM |
354 | |
355 | return 0; | |
356 | } | |
357 | ||
e26a5843 AH |
358 | static inline u32 ndev_spad_read(struct intel_ntb_dev *ndev, int idx, |
359 | void __iomem *mmio) | |
fce8a7bb | 360 | { |
fd839bf8 DJ |
361 | if (ndev_is_unsafe(ndev, NTB_UNSAFE_SPAD)) |
362 | pr_warn_once("%s: NTB unsafe scratchpad access", __func__); | |
fce8a7bb | 363 | |
e26a5843 AH |
364 | if (idx < 0 || idx >= ndev->spad_count) |
365 | return 0; | |
fce8a7bb | 366 | |
e26a5843 | 367 | return ioread32(mmio + (idx << 2)); |
fce8a7bb JM |
368 | } |
369 | ||
e26a5843 AH |
370 | static inline int ndev_spad_write(struct intel_ntb_dev *ndev, int idx, u32 val, |
371 | void __iomem *mmio) | |
fce8a7bb | 372 | { |
fd839bf8 DJ |
373 | if (ndev_is_unsafe(ndev, NTB_UNSAFE_SPAD)) |
374 | pr_warn_once("%s: NTB unsafe scratchpad access", __func__); | |
e26a5843 AH |
375 | |
376 | if (idx < 0 || idx >= ndev->spad_count) | |
fce8a7bb JM |
377 | return -EINVAL; |
378 | ||
e26a5843 | 379 | iowrite32(val, mmio + (idx << 2)); |
fce8a7bb JM |
380 | |
381 | return 0; | |
382 | } | |
383 | ||
e26a5843 | 384 | static irqreturn_t ndev_interrupt(struct intel_ntb_dev *ndev, int vec) |
282a2fee | 385 | { |
e26a5843 AH |
386 | u64 vec_mask; |
387 | ||
388 | vec_mask = ndev_vec_mask(ndev, vec); | |
389 | ||
390 | dev_dbg(ndev_dev(ndev), "vec %d vec_mask %llx\n", vec, vec_mask); | |
282a2fee | 391 | |
e26a5843 AH |
392 | ndev->last_ts = jiffies; |
393 | ||
394 | if (vec_mask & ndev->db_link_mask) { | |
395 | if (ndev->reg->poll_link(ndev)) | |
396 | ntb_link_event(&ndev->ntb); | |
397 | } | |
398 | ||
399 | if (vec_mask & ndev->db_valid_mask) | |
400 | ntb_db_event(&ndev->ntb, vec); | |
401 | ||
402 | return IRQ_HANDLED; | |
282a2fee JM |
403 | } |
404 | ||
e26a5843 | 405 | static irqreturn_t ndev_vec_isr(int irq, void *dev) |
fce8a7bb | 406 | { |
e26a5843 | 407 | struct intel_ntb_vec *nvec = dev; |
fce8a7bb | 408 | |
e26a5843 | 409 | return ndev_interrupt(nvec->ndev, nvec->num); |
fce8a7bb JM |
410 | } |
411 | ||
e26a5843 | 412 | static irqreturn_t ndev_irq_isr(int irq, void *dev) |
fce8a7bb | 413 | { |
e26a5843 | 414 | struct intel_ntb_dev *ndev = dev; |
fce8a7bb | 415 | |
e26a5843 | 416 | return ndev_interrupt(ndev, irq - ndev_pdev(ndev)->irq); |
fce8a7bb JM |
417 | } |
418 | ||
e26a5843 AH |
419 | static int ndev_init_isr(struct intel_ntb_dev *ndev, |
420 | int msix_min, int msix_max, | |
421 | int msix_shift, int total_shift) | |
fce8a7bb | 422 | { |
e26a5843 | 423 | struct pci_dev *pdev; |
0e041fb5 | 424 | int rc, i, msix_count, node; |
fce8a7bb | 425 | |
e26a5843 | 426 | pdev = ndev_pdev(ndev); |
fce8a7bb | 427 | |
0e041fb5 AH |
428 | node = dev_to_node(&pdev->dev); |
429 | ||
e26a5843 AH |
430 | /* Mask all doorbell interrupts */ |
431 | ndev->db_mask = ndev->db_valid_mask; | |
432 | ndev->reg->db_iowrite(ndev->db_mask, | |
433 | ndev->self_mmio + | |
434 | ndev->self_reg->db_mask); | |
fce8a7bb | 435 | |
e26a5843 AH |
436 | /* Try to set up msix irq */ |
437 | ||
0e041fb5 AH |
438 | ndev->vec = kzalloc_node(msix_max * sizeof(*ndev->vec), |
439 | GFP_KERNEL, node); | |
e26a5843 AH |
440 | if (!ndev->vec) |
441 | goto err_msix_vec_alloc; | |
442 | ||
0e041fb5 AH |
443 | ndev->msix = kzalloc_node(msix_max * sizeof(*ndev->msix), |
444 | GFP_KERNEL, node); | |
e26a5843 AH |
445 | if (!ndev->msix) |
446 | goto err_msix_alloc; | |
447 | ||
448 | for (i = 0; i < msix_max; ++i) | |
449 | ndev->msix[i].entry = i; | |
450 | ||
451 | msix_count = pci_enable_msix_range(pdev, ndev->msix, | |
452 | msix_min, msix_max); | |
453 | if (msix_count < 0) | |
454 | goto err_msix_enable; | |
455 | ||
456 | for (i = 0; i < msix_count; ++i) { | |
457 | ndev->vec[i].ndev = ndev; | |
458 | ndev->vec[i].num = i; | |
459 | rc = request_irq(ndev->msix[i].vector, ndev_vec_isr, 0, | |
460 | "ndev_vec_isr", &ndev->vec[i]); | |
461 | if (rc) | |
462 | goto err_msix_request; | |
fce8a7bb | 463 | } |
fce8a7bb | 464 | |
e26a5843 AH |
465 | dev_dbg(ndev_dev(ndev), "Using msix interrupts\n"); |
466 | ndev->db_vec_count = msix_count; | |
467 | ndev->db_vec_shift = msix_shift; | |
468 | return 0; | |
fce8a7bb | 469 | |
e26a5843 AH |
470 | err_msix_request: |
471 | while (i-- > 0) | |
472 | free_irq(ndev->msix[i].vector, ndev); | |
473 | pci_disable_msix(pdev); | |
474 | err_msix_enable: | |
475 | kfree(ndev->msix); | |
476 | err_msix_alloc: | |
477 | kfree(ndev->vec); | |
478 | err_msix_vec_alloc: | |
479 | ndev->msix = NULL; | |
480 | ndev->vec = NULL; | |
fce8a7bb | 481 | |
e26a5843 | 482 | /* Try to set up msi irq */ |
113bf1c9 | 483 | |
e26a5843 AH |
484 | rc = pci_enable_msi(pdev); |
485 | if (rc) | |
486 | goto err_msi_enable; | |
113bf1c9 | 487 | |
e26a5843 AH |
488 | rc = request_irq(pdev->irq, ndev_irq_isr, 0, |
489 | "ndev_irq_isr", ndev); | |
490 | if (rc) | |
491 | goto err_msi_request; | |
113bf1c9 | 492 | |
e26a5843 AH |
493 | dev_dbg(ndev_dev(ndev), "Using msi interrupts\n"); |
494 | ndev->db_vec_count = 1; | |
495 | ndev->db_vec_shift = total_shift; | |
496 | return 0; | |
113bf1c9 | 497 | |
e26a5843 AH |
498 | err_msi_request: |
499 | pci_disable_msi(pdev); | |
500 | err_msi_enable: | |
113bf1c9 | 501 | |
e26a5843 | 502 | /* Try to set up intx irq */ |
113bf1c9 | 503 | |
e26a5843 | 504 | pci_intx(pdev, 1); |
113bf1c9 | 505 | |
e26a5843 AH |
506 | rc = request_irq(pdev->irq, ndev_irq_isr, IRQF_SHARED, |
507 | "ndev_irq_isr", ndev); | |
508 | if (rc) | |
509 | goto err_intx_request; | |
510 | ||
511 | dev_dbg(ndev_dev(ndev), "Using intx interrupts\n"); | |
512 | ndev->db_vec_count = 1; | |
513 | ndev->db_vec_shift = total_shift; | |
514 | return 0; | |
515 | ||
516 | err_intx_request: | |
517 | return rc; | |
113bf1c9 JM |
518 | } |
519 | ||
e26a5843 | 520 | static void ndev_deinit_isr(struct intel_ntb_dev *ndev) |
fce8a7bb | 521 | { |
e26a5843 AH |
522 | struct pci_dev *pdev; |
523 | int i; | |
fce8a7bb | 524 | |
e26a5843 | 525 | pdev = ndev_pdev(ndev); |
fce8a7bb | 526 | |
e26a5843 AH |
527 | /* Mask all doorbell interrupts */ |
528 | ndev->db_mask = ndev->db_valid_mask; | |
529 | ndev->reg->db_iowrite(ndev->db_mask, | |
530 | ndev->self_mmio + | |
531 | ndev->self_reg->db_mask); | |
113bf1c9 | 532 | |
e26a5843 AH |
533 | if (ndev->msix) { |
534 | i = ndev->db_vec_count; | |
535 | while (i--) | |
536 | free_irq(ndev->msix[i].vector, &ndev->vec[i]); | |
537 | pci_disable_msix(pdev); | |
538 | kfree(ndev->msix); | |
539 | kfree(ndev->vec); | |
fce8a7bb | 540 | } else { |
e26a5843 AH |
541 | free_irq(pdev->irq, ndev); |
542 | if (pci_dev_msi_enabled(pdev)) | |
543 | pci_disable_msi(pdev); | |
fce8a7bb | 544 | } |
fce8a7bb JM |
545 | } |
546 | ||
e26a5843 AH |
547 | static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf, |
548 | size_t count, loff_t *offp) | |
fce8a7bb | 549 | { |
e26a5843 AH |
550 | struct intel_ntb_dev *ndev; |
551 | void __iomem *mmio; | |
552 | char *buf; | |
553 | size_t buf_size; | |
554 | ssize_t ret, off; | |
555 | union { u64 v64; u32 v32; u16 v16; } u; | |
fce8a7bb | 556 | |
e26a5843 AH |
557 | ndev = filp->private_data; |
558 | mmio = ndev->self_mmio; | |
fce8a7bb | 559 | |
e26a5843 | 560 | buf_size = min(count, 0x800ul); |
fce8a7bb | 561 | |
e26a5843 AH |
562 | buf = kmalloc(buf_size, GFP_KERNEL); |
563 | if (!buf) | |
564 | return -ENOMEM; | |
fce8a7bb | 565 | |
e26a5843 | 566 | off = 0; |
fce8a7bb | 567 | |
e26a5843 AH |
568 | off += scnprintf(buf + off, buf_size - off, |
569 | "NTB Device Information:\n"); | |
fce8a7bb | 570 | |
e26a5843 AH |
571 | off += scnprintf(buf + off, buf_size - off, |
572 | "Connection Topology -\t%s\n", | |
573 | ntb_topo_string(ndev->ntb.topo)); | |
fce8a7bb | 574 | |
e26a5843 AH |
575 | off += scnprintf(buf + off, buf_size - off, |
576 | "B2B Offset -\t\t%#lx\n", ndev->b2b_off); | |
577 | off += scnprintf(buf + off, buf_size - off, | |
578 | "B2B MW Idx -\t\t%d\n", ndev->b2b_idx); | |
579 | off += scnprintf(buf + off, buf_size - off, | |
580 | "BAR4 Split -\t\t%s\n", | |
581 | ndev->bar4_split ? "yes" : "no"); | |
113bf1c9 | 582 | |
e26a5843 AH |
583 | off += scnprintf(buf + off, buf_size - off, |
584 | "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl); | |
585 | off += scnprintf(buf + off, buf_size - off, | |
586 | "LNK STA -\t\t%#06x\n", ndev->lnk_sta); | |
587 | ||
588 | if (!ndev->reg->link_is_up(ndev)) { | |
589 | off += scnprintf(buf + off, buf_size - off, | |
590 | "Link Status -\t\tDown\n"); | |
591 | } else { | |
592 | off += scnprintf(buf + off, buf_size - off, | |
593 | "Link Status -\t\tUp\n"); | |
594 | off += scnprintf(buf + off, buf_size - off, | |
595 | "Link Speed -\t\tPCI-E Gen %u\n", | |
596 | NTB_LNK_STA_SPEED(ndev->lnk_sta)); | |
597 | off += scnprintf(buf + off, buf_size - off, | |
598 | "Link Width -\t\tx%u\n", | |
599 | NTB_LNK_STA_WIDTH(ndev->lnk_sta)); | |
113bf1c9 JM |
600 | } |
601 | ||
e26a5843 AH |
602 | off += scnprintf(buf + off, buf_size - off, |
603 | "Memory Window Count -\t%u\n", ndev->mw_count); | |
604 | off += scnprintf(buf + off, buf_size - off, | |
605 | "Scratchpad Count -\t%u\n", ndev->spad_count); | |
606 | off += scnprintf(buf + off, buf_size - off, | |
607 | "Doorbell Count -\t%u\n", ndev->db_count); | |
608 | off += scnprintf(buf + off, buf_size - off, | |
609 | "Doorbell Vector Count -\t%u\n", ndev->db_vec_count); | |
610 | off += scnprintf(buf + off, buf_size - off, | |
611 | "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift); | |
612 | ||
613 | off += scnprintf(buf + off, buf_size - off, | |
614 | "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask); | |
615 | off += scnprintf(buf + off, buf_size - off, | |
616 | "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask); | |
617 | off += scnprintf(buf + off, buf_size - off, | |
618 | "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask); | |
619 | ||
620 | u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask); | |
621 | off += scnprintf(buf + off, buf_size - off, | |
622 | "Doorbell Mask -\t\t%#llx\n", u.v64); | |
623 | ||
624 | u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_bell); | |
625 | off += scnprintf(buf + off, buf_size - off, | |
626 | "Doorbell Bell -\t\t%#llx\n", u.v64); | |
627 | ||
628 | off += scnprintf(buf + off, buf_size - off, | |
629 | "\nNTB Incoming XLAT:\n"); | |
630 | ||
631 | u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 2)); | |
632 | off += scnprintf(buf + off, buf_size - off, | |
633 | "XLAT23 -\t\t%#018llx\n", u.v64); | |
634 | ||
635 | u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4)); | |
636 | off += scnprintf(buf + off, buf_size - off, | |
637 | "XLAT45 -\t\t%#018llx\n", u.v64); | |
638 | ||
639 | u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 2)); | |
640 | off += scnprintf(buf + off, buf_size - off, | |
641 | "LMT23 -\t\t\t%#018llx\n", u.v64); | |
642 | ||
643 | u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4)); | |
644 | off += scnprintf(buf + off, buf_size - off, | |
645 | "LMT45 -\t\t\t%#018llx\n", u.v64); | |
646 | ||
2f887b9a | 647 | if (pdev_is_xeon(ndev->ntb.pdev)) { |
e26a5843 AH |
648 | if (ntb_topo_is_b2b(ndev->ntb.topo)) { |
649 | off += scnprintf(buf + off, buf_size - off, | |
650 | "\nNTB Outgoing B2B XLAT:\n"); | |
651 | ||
2f887b9a | 652 | u.v64 = ioread64(mmio + XEON_PBAR23XLAT_OFFSET); |
e26a5843 AH |
653 | off += scnprintf(buf + off, buf_size - off, |
654 | "B2B XLAT23 -\t\t%#018llx\n", u.v64); | |
655 | ||
2f887b9a | 656 | u.v64 = ioread64(mmio + XEON_PBAR45XLAT_OFFSET); |
e26a5843 AH |
657 | off += scnprintf(buf + off, buf_size - off, |
658 | "B2B XLAT45 -\t\t%#018llx\n", u.v64); | |
659 | ||
2f887b9a | 660 | u.v64 = ioread64(mmio + XEON_PBAR23LMT_OFFSET); |
e26a5843 AH |
661 | off += scnprintf(buf + off, buf_size - off, |
662 | "B2B LMT23 -\t\t%#018llx\n", u.v64); | |
663 | ||
2f887b9a | 664 | u.v64 = ioread64(mmio + XEON_PBAR45LMT_OFFSET); |
e26a5843 AH |
665 | off += scnprintf(buf + off, buf_size - off, |
666 | "B2B LMT45 -\t\t%#018llx\n", u.v64); | |
667 | ||
668 | off += scnprintf(buf + off, buf_size - off, | |
669 | "\nNTB Secondary BAR:\n"); | |
670 | ||
2f887b9a | 671 | u.v64 = ioread64(mmio + XEON_SBAR0BASE_OFFSET); |
e26a5843 AH |
672 | off += scnprintf(buf + off, buf_size - off, |
673 | "SBAR01 -\t\t%#018llx\n", u.v64); | |
674 | ||
2f887b9a | 675 | u.v64 = ioread64(mmio + XEON_SBAR23BASE_OFFSET); |
e26a5843 AH |
676 | off += scnprintf(buf + off, buf_size - off, |
677 | "SBAR23 -\t\t%#018llx\n", u.v64); | |
678 | ||
2f887b9a | 679 | u.v64 = ioread64(mmio + XEON_SBAR45BASE_OFFSET); |
e26a5843 AH |
680 | off += scnprintf(buf + off, buf_size - off, |
681 | "SBAR45 -\t\t%#018llx\n", u.v64); | |
682 | } | |
683 | ||
684 | off += scnprintf(buf + off, buf_size - off, | |
2f887b9a | 685 | "\nXEON NTB Statistics:\n"); |
e26a5843 | 686 | |
2f887b9a | 687 | u.v16 = ioread16(mmio + XEON_USMEMMISS_OFFSET); |
e26a5843 AH |
688 | off += scnprintf(buf + off, buf_size - off, |
689 | "Upstream Memory Miss -\t%u\n", u.v16); | |
690 | ||
691 | off += scnprintf(buf + off, buf_size - off, | |
2f887b9a | 692 | "\nXEON NTB Hardware Errors:\n"); |
e26a5843 AH |
693 | |
694 | if (!pci_read_config_word(ndev->ntb.pdev, | |
2f887b9a | 695 | XEON_DEVSTS_OFFSET, &u.v16)) |
e26a5843 AH |
696 | off += scnprintf(buf + off, buf_size - off, |
697 | "DEVSTS -\t\t%#06x\n", u.v16); | |
698 | ||
699 | if (!pci_read_config_word(ndev->ntb.pdev, | |
2f887b9a | 700 | XEON_LINK_STATUS_OFFSET, &u.v16)) |
e26a5843 AH |
701 | off += scnprintf(buf + off, buf_size - off, |
702 | "LNKSTS -\t\t%#06x\n", u.v16); | |
113bf1c9 | 703 | |
e26a5843 | 704 | if (!pci_read_config_dword(ndev->ntb.pdev, |
2f887b9a | 705 | XEON_UNCERRSTS_OFFSET, &u.v32)) |
e26a5843 AH |
706 | off += scnprintf(buf + off, buf_size - off, |
707 | "UNCERRSTS -\t\t%#06x\n", u.v32); | |
708 | ||
709 | if (!pci_read_config_dword(ndev->ntb.pdev, | |
2f887b9a | 710 | XEON_CORERRSTS_OFFSET, &u.v32)) |
e26a5843 AH |
711 | off += scnprintf(buf + off, buf_size - off, |
712 | "CORERRSTS -\t\t%#06x\n", u.v32); | |
713 | } | |
714 | ||
715 | ret = simple_read_from_buffer(ubuf, count, offp, buf, off); | |
716 | kfree(buf); | |
717 | return ret; | |
113bf1c9 JM |
718 | } |
719 | ||
e26a5843 | 720 | static void ndev_init_debugfs(struct intel_ntb_dev *ndev) |
fce8a7bb | 721 | { |
e26a5843 AH |
722 | if (!debugfs_dir) { |
723 | ndev->debugfs_dir = NULL; | |
724 | ndev->debugfs_info = NULL; | |
725 | } else { | |
726 | ndev->debugfs_dir = | |
727 | debugfs_create_dir(ndev_name(ndev), debugfs_dir); | |
728 | if (!ndev->debugfs_dir) | |
729 | ndev->debugfs_info = NULL; | |
730 | else | |
731 | ndev->debugfs_info = | |
732 | debugfs_create_file("info", S_IRUSR, | |
733 | ndev->debugfs_dir, ndev, | |
734 | &intel_ntb_debugfs_info); | |
fce8a7bb | 735 | } |
e26a5843 | 736 | } |
fce8a7bb | 737 | |
e26a5843 AH |
738 | static void ndev_deinit_debugfs(struct intel_ntb_dev *ndev) |
739 | { | |
740 | debugfs_remove_recursive(ndev->debugfs_dir); | |
fce8a7bb JM |
741 | } |
742 | ||
e26a5843 | 743 | static int intel_ntb_mw_count(struct ntb_dev *ntb) |
fce8a7bb | 744 | { |
e26a5843 AH |
745 | return ntb_ndev(ntb)->mw_count; |
746 | } | |
ed6c24ed | 747 | |
e26a5843 AH |
748 | static int intel_ntb_mw_get_range(struct ntb_dev *ntb, int idx, |
749 | phys_addr_t *base, | |
750 | resource_size_t *size, | |
751 | resource_size_t *align, | |
752 | resource_size_t *align_size) | |
753 | { | |
754 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); | |
755 | int bar; | |
948d3a65 | 756 | |
e26a5843 AH |
757 | if (idx >= ndev->b2b_idx && !ndev->b2b_off) |
758 | idx += 1; | |
ab760a0c | 759 | |
e26a5843 AH |
760 | bar = ndev_mw_to_bar(ndev, idx); |
761 | if (bar < 0) | |
762 | return bar; | |
ed6c24ed | 763 | |
e26a5843 AH |
764 | if (base) |
765 | *base = pci_resource_start(ndev->ntb.pdev, bar) + | |
766 | (idx == ndev->b2b_idx ? ndev->b2b_off : 0); | |
069684e8 | 767 | |
e26a5843 AH |
768 | if (size) |
769 | *size = pci_resource_len(ndev->ntb.pdev, bar) - | |
770 | (idx == ndev->b2b_idx ? ndev->b2b_off : 0); | |
fce8a7bb | 771 | |
e26a5843 AH |
772 | if (align) |
773 | *align = pci_resource_len(ndev->ntb.pdev, bar); | |
ed6c24ed | 774 | |
e26a5843 AH |
775 | if (align_size) |
776 | *align_size = 1; | |
fce8a7bb JM |
777 | |
778 | return 0; | |
779 | } | |
780 | ||
e26a5843 AH |
781 | static int intel_ntb_mw_set_trans(struct ntb_dev *ntb, int idx, |
782 | dma_addr_t addr, resource_size_t size) | |
fce8a7bb | 783 | { |
e26a5843 AH |
784 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); |
785 | unsigned long base_reg, xlat_reg, limit_reg; | |
786 | resource_size_t bar_size, mw_size; | |
787 | void __iomem *mmio; | |
788 | u64 base, limit, reg_val; | |
789 | int bar; | |
fce8a7bb | 790 | |
e26a5843 AH |
791 | if (idx >= ndev->b2b_idx && !ndev->b2b_off) |
792 | idx += 1; | |
fce8a7bb | 793 | |
e26a5843 AH |
794 | bar = ndev_mw_to_bar(ndev, idx); |
795 | if (bar < 0) | |
796 | return bar; | |
fce8a7bb | 797 | |
e26a5843 AH |
798 | bar_size = pci_resource_len(ndev->ntb.pdev, bar); |
799 | ||
800 | if (idx == ndev->b2b_idx) | |
801 | mw_size = bar_size - ndev->b2b_off; | |
802 | else | |
803 | mw_size = bar_size; | |
804 | ||
805 | /* hardware requires that addr is aligned to bar size */ | |
806 | if (addr & (bar_size - 1)) | |
fce8a7bb | 807 | return -EINVAL; |
e26a5843 AH |
808 | |
809 | /* make sure the range fits in the usable mw size */ | |
810 | if (size > mw_size) | |
811 | return -EINVAL; | |
812 | ||
813 | mmio = ndev->self_mmio; | |
814 | base_reg = bar0_off(ndev->xlat_reg->bar0_base, bar); | |
815 | xlat_reg = bar2_off(ndev->xlat_reg->bar2_xlat, bar); | |
816 | limit_reg = bar2_off(ndev->xlat_reg->bar2_limit, bar); | |
817 | ||
818 | if (bar < 4 || !ndev->bar4_split) { | |
819 | base = ioread64(mmio + base_reg); | |
820 | ||
821 | /* Set the limit if supported, if size is not mw_size */ | |
822 | if (limit_reg && size != mw_size) | |
823 | limit = base + size; | |
824 | else | |
825 | limit = 0; | |
826 | ||
827 | /* set and verify setting the translation address */ | |
828 | iowrite64(addr, mmio + xlat_reg); | |
829 | reg_val = ioread64(mmio + xlat_reg); | |
830 | if (reg_val != addr) { | |
831 | iowrite64(0, mmio + xlat_reg); | |
832 | return -EIO; | |
833 | } | |
834 | ||
835 | /* set and verify setting the limit */ | |
836 | iowrite64(limit, mmio + limit_reg); | |
837 | reg_val = ioread64(mmio + limit_reg); | |
838 | if (reg_val != limit) { | |
839 | iowrite64(base, mmio + limit_reg); | |
840 | iowrite64(0, mmio + xlat_reg); | |
841 | return -EIO; | |
842 | } | |
843 | } else { | |
844 | /* split bar addr range must all be 32 bit */ | |
845 | if (addr & (~0ull << 32)) | |
846 | return -EINVAL; | |
847 | if ((addr + size) & (~0ull << 32)) | |
848 | return -EINVAL; | |
849 | ||
850 | base = ioread32(mmio + base_reg); | |
851 | ||
852 | /* Set the limit if supported, if size is not mw_size */ | |
853 | if (limit_reg && size != mw_size) | |
854 | limit = base + size; | |
855 | else | |
856 | limit = 0; | |
857 | ||
858 | /* set and verify setting the translation address */ | |
859 | iowrite32(addr, mmio + xlat_reg); | |
860 | reg_val = ioread32(mmio + xlat_reg); | |
861 | if (reg_val != addr) { | |
862 | iowrite32(0, mmio + xlat_reg); | |
863 | return -EIO; | |
864 | } | |
865 | ||
866 | /* set and verify setting the limit */ | |
867 | iowrite32(limit, mmio + limit_reg); | |
868 | reg_val = ioread32(mmio + limit_reg); | |
869 | if (reg_val != limit) { | |
870 | iowrite32(base, mmio + limit_reg); | |
871 | iowrite32(0, mmio + xlat_reg); | |
872 | return -EIO; | |
873 | } | |
fce8a7bb JM |
874 | } |
875 | ||
e26a5843 AH |
876 | return 0; |
877 | } | |
fce8a7bb | 878 | |
e26a5843 AH |
879 | static int intel_ntb_link_is_up(struct ntb_dev *ntb, |
880 | enum ntb_speed *speed, | |
881 | enum ntb_width *width) | |
882 | { | |
883 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); | |
fce8a7bb | 884 | |
e26a5843 AH |
885 | if (ndev->reg->link_is_up(ndev)) { |
886 | if (speed) | |
887 | *speed = NTB_LNK_STA_SPEED(ndev->lnk_sta); | |
888 | if (width) | |
889 | *width = NTB_LNK_STA_WIDTH(ndev->lnk_sta); | |
890 | return 1; | |
891 | } else { | |
892 | /* TODO MAYBE: is it possible to observe the link speed and | |
893 | * width while link is training? */ | |
894 | if (speed) | |
895 | *speed = NTB_SPEED_NONE; | |
896 | if (width) | |
897 | *width = NTB_WIDTH_NONE; | |
898 | return 0; | |
899 | } | |
900 | } | |
901 | ||
902 | static int intel_ntb_link_enable(struct ntb_dev *ntb, | |
903 | enum ntb_speed max_speed, | |
904 | enum ntb_width max_width) | |
905 | { | |
906 | struct intel_ntb_dev *ndev; | |
907 | u32 ntb_ctl; | |
908 | ||
909 | ndev = container_of(ntb, struct intel_ntb_dev, ntb); | |
910 | ||
911 | if (ndev->ntb.topo == NTB_TOPO_SEC) | |
912 | return -EINVAL; | |
913 | ||
914 | dev_dbg(ndev_dev(ndev), | |
915 | "Enabling link with max_speed %d max_width %d\n", | |
916 | max_speed, max_width); | |
917 | if (max_speed != NTB_SPEED_AUTO) | |
918 | dev_dbg(ndev_dev(ndev), "ignoring max_speed %d\n", max_speed); | |
919 | if (max_width != NTB_WIDTH_AUTO) | |
920 | dev_dbg(ndev_dev(ndev), "ignoring max_width %d\n", max_width); | |
921 | ||
922 | ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); | |
923 | ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK); | |
924 | ntb_ctl |= NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP; | |
925 | ntb_ctl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP; | |
926 | if (ndev->bar4_split) | |
927 | ntb_ctl |= NTB_CTL_P2S_BAR5_SNOOP | NTB_CTL_S2P_BAR5_SNOOP; | |
928 | iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); | |
fce8a7bb JM |
929 | |
930 | return 0; | |
931 | } | |
932 | ||
e26a5843 | 933 | static int intel_ntb_link_disable(struct ntb_dev *ntb) |
fce8a7bb | 934 | { |
e26a5843 AH |
935 | struct intel_ntb_dev *ndev; |
936 | u32 ntb_cntl; | |
fce8a7bb | 937 | |
e26a5843 | 938 | ndev = container_of(ntb, struct intel_ntb_dev, ntb); |
fce8a7bb | 939 | |
e26a5843 AH |
940 | if (ndev->ntb.topo == NTB_TOPO_SEC) |
941 | return -EINVAL; | |
3b12a0d1 | 942 | |
e26a5843 AH |
943 | dev_dbg(ndev_dev(ndev), "Disabling link\n"); |
944 | ||
945 | /* Bring NTB link down */ | |
946 | ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); | |
947 | ntb_cntl &= ~(NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP); | |
948 | ntb_cntl &= ~(NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP); | |
949 | if (ndev->bar4_split) | |
950 | ntb_cntl &= ~(NTB_CTL_P2S_BAR5_SNOOP | NTB_CTL_S2P_BAR5_SNOOP); | |
951 | ntb_cntl |= NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK; | |
952 | iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl); | |
fce8a7bb | 953 | |
3b12a0d1 | 954 | return 0; |
fce8a7bb JM |
955 | } |
956 | ||
e26a5843 | 957 | static int intel_ntb_db_is_unsafe(struct ntb_dev *ntb) |
fce8a7bb | 958 | { |
e26a5843 | 959 | return ndev_ignore_unsafe(ntb_ndev(ntb), NTB_UNSAFE_DB); |
fce8a7bb JM |
960 | } |
961 | ||
e26a5843 | 962 | static u64 intel_ntb_db_valid_mask(struct ntb_dev *ntb) |
fce8a7bb | 963 | { |
e26a5843 AH |
964 | return ntb_ndev(ntb)->db_valid_mask; |
965 | } | |
fce8a7bb | 966 | |
e26a5843 AH |
967 | static int intel_ntb_db_vector_count(struct ntb_dev *ntb) |
968 | { | |
969 | struct intel_ntb_dev *ndev; | |
fce8a7bb | 970 | |
e26a5843 | 971 | ndev = container_of(ntb, struct intel_ntb_dev, ntb); |
e8aeb60c | 972 | |
e26a5843 AH |
973 | return ndev->db_vec_count; |
974 | } | |
fce8a7bb | 975 | |
e26a5843 AH |
976 | static u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector) |
977 | { | |
978 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); | |
fce8a7bb | 979 | |
e26a5843 AH |
980 | if (db_vector < 0 || db_vector > ndev->db_vec_count) |
981 | return 0; | |
fce8a7bb | 982 | |
e26a5843 | 983 | return ndev->db_valid_mask & ndev_vec_mask(ndev, db_vector); |
fce8a7bb JM |
984 | } |
985 | ||
e26a5843 | 986 | static u64 intel_ntb_db_read(struct ntb_dev *ntb) |
fce8a7bb | 987 | { |
e26a5843 | 988 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); |
fce8a7bb | 989 | |
e26a5843 AH |
990 | return ndev_db_read(ndev, |
991 | ndev->self_mmio + | |
992 | ndev->self_reg->db_bell); | |
993 | } | |
fce8a7bb | 994 | |
e26a5843 AH |
995 | static int intel_ntb_db_clear(struct ntb_dev *ntb, u64 db_bits) |
996 | { | |
997 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); | |
e8aeb60c | 998 | |
e26a5843 AH |
999 | return ndev_db_write(ndev, db_bits, |
1000 | ndev->self_mmio + | |
1001 | ndev->self_reg->db_bell); | |
1002 | } | |
fce8a7bb | 1003 | |
e26a5843 AH |
1004 | static int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits) |
1005 | { | |
1006 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); | |
fce8a7bb | 1007 | |
e26a5843 AH |
1008 | return ndev_db_set_mask(ndev, db_bits, |
1009 | ndev->self_mmio + | |
1010 | ndev->self_reg->db_mask); | |
fce8a7bb JM |
1011 | } |
1012 | ||
e26a5843 | 1013 | static int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits) |
fce8a7bb | 1014 | { |
e26a5843 | 1015 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); |
fce8a7bb | 1016 | |
e26a5843 AH |
1017 | return ndev_db_clear_mask(ndev, db_bits, |
1018 | ndev->self_mmio + | |
1019 | ndev->self_reg->db_mask); | |
1020 | } | |
fce8a7bb | 1021 | |
e26a5843 AH |
1022 | static int intel_ntb_peer_db_addr(struct ntb_dev *ntb, |
1023 | phys_addr_t *db_addr, | |
1024 | resource_size_t *db_size) | |
1025 | { | |
1026 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); | |
fce8a7bb | 1027 | |
e26a5843 AH |
1028 | return ndev_db_addr(ndev, db_addr, db_size, ndev->peer_addr, |
1029 | ndev->peer_reg->db_bell); | |
fce8a7bb JM |
1030 | } |
1031 | ||
e26a5843 | 1032 | static int intel_ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits) |
fce8a7bb | 1033 | { |
e26a5843 | 1034 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); |
fce8a7bb | 1035 | |
e26a5843 AH |
1036 | return ndev_db_write(ndev, db_bits, |
1037 | ndev->peer_mmio + | |
1038 | ndev->peer_reg->db_bell); | |
1039 | } | |
fce8a7bb | 1040 | |
e26a5843 AH |
1041 | static int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb) |
1042 | { | |
1043 | return ndev_ignore_unsafe(ntb_ndev(ntb), NTB_UNSAFE_SPAD); | |
1044 | } | |
fce8a7bb | 1045 | |
e26a5843 AH |
1046 | static int intel_ntb_spad_count(struct ntb_dev *ntb) |
1047 | { | |
1048 | struct intel_ntb_dev *ndev; | |
fce8a7bb | 1049 | |
e26a5843 | 1050 | ndev = container_of(ntb, struct intel_ntb_dev, ntb); |
fce8a7bb | 1051 | |
e26a5843 AH |
1052 | return ndev->spad_count; |
1053 | } | |
fce8a7bb | 1054 | |
e26a5843 AH |
1055 | static u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx) |
1056 | { | |
1057 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); | |
fce8a7bb | 1058 | |
e26a5843 AH |
1059 | return ndev_spad_read(ndev, idx, |
1060 | ndev->self_mmio + | |
1061 | ndev->self_reg->spad); | |
fce8a7bb JM |
1062 | } |
1063 | ||
e26a5843 AH |
1064 | static int intel_ntb_spad_write(struct ntb_dev *ntb, |
1065 | int idx, u32 val) | |
53a788a7 | 1066 | { |
e26a5843 | 1067 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); |
53a788a7 | 1068 | |
e26a5843 AH |
1069 | return ndev_spad_write(ndev, idx, val, |
1070 | ndev->self_mmio + | |
1071 | ndev->self_reg->spad); | |
1072 | } | |
53a788a7 | 1073 | |
e26a5843 AH |
1074 | static int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int idx, |
1075 | phys_addr_t *spad_addr) | |
1076 | { | |
1077 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); | |
53a788a7 | 1078 | |
e26a5843 AH |
1079 | return ndev_spad_addr(ndev, idx, spad_addr, ndev->peer_addr, |
1080 | ndev->peer_reg->spad); | |
1081 | } | |
53a788a7 | 1082 | |
e26a5843 AH |
1083 | static u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int idx) |
1084 | { | |
1085 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); | |
53a788a7 | 1086 | |
e26a5843 AH |
1087 | return ndev_spad_read(ndev, idx, |
1088 | ndev->peer_mmio + | |
1089 | ndev->peer_reg->spad); | |
1090 | } | |
53a788a7 | 1091 | |
e26a5843 AH |
1092 | static int intel_ntb_peer_spad_write(struct ntb_dev *ntb, |
1093 | int idx, u32 val) | |
1094 | { | |
1095 | struct intel_ntb_dev *ndev = ntb_ndev(ntb); | |
53a788a7 | 1096 | |
e26a5843 AH |
1097 | return ndev_spad_write(ndev, idx, val, |
1098 | ndev->peer_mmio + | |
1099 | ndev->peer_reg->spad); | |
1100 | } | |
53a788a7 | 1101 | |
2f887b9a | 1102 | /* ATOM */ |
53a788a7 | 1103 | |
2f887b9a | 1104 | static u64 atom_db_ioread(void __iomem *mmio) |
e26a5843 AH |
1105 | { |
1106 | return ioread64(mmio); | |
1107 | } | |
1108 | ||
2f887b9a | 1109 | static void atom_db_iowrite(u64 bits, void __iomem *mmio) |
e26a5843 AH |
1110 | { |
1111 | iowrite64(bits, mmio); | |
53a788a7 AG |
1112 | } |
1113 | ||
2f887b9a | 1114 | static int atom_poll_link(struct intel_ntb_dev *ndev) |
fce8a7bb | 1115 | { |
e26a5843 | 1116 | u32 ntb_ctl; |
53a788a7 | 1117 | |
2f887b9a | 1118 | ntb_ctl = ioread32(ndev->self_mmio + ATOM_NTBCNTL_OFFSET); |
53a788a7 | 1119 | |
e26a5843 AH |
1120 | if (ntb_ctl == ndev->ntb_ctl) |
1121 | return 0; | |
53a788a7 | 1122 | |
e26a5843 | 1123 | ndev->ntb_ctl = ntb_ctl; |
53a788a7 | 1124 | |
2f887b9a | 1125 | ndev->lnk_sta = ioread32(ndev->self_mmio + ATOM_LINK_STATUS_OFFSET); |
53a788a7 | 1126 | |
e26a5843 AH |
1127 | return 1; |
1128 | } | |
53a788a7 | 1129 | |
2f887b9a | 1130 | static int atom_link_is_up(struct intel_ntb_dev *ndev) |
e26a5843 | 1131 | { |
2f887b9a | 1132 | return ATOM_NTB_CTL_ACTIVE(ndev->ntb_ctl); |
e26a5843 | 1133 | } |
53a788a7 | 1134 | |
2f887b9a | 1135 | static int atom_link_is_err(struct intel_ntb_dev *ndev) |
e26a5843 | 1136 | { |
2f887b9a DJ |
1137 | if (ioread32(ndev->self_mmio + ATOM_LTSSMSTATEJMP_OFFSET) |
1138 | & ATOM_LTSSMSTATEJMP_FORCEDETECT) | |
e26a5843 | 1139 | return 1; |
53a788a7 | 1140 | |
2f887b9a DJ |
1141 | if (ioread32(ndev->self_mmio + ATOM_IBSTERRRCRVSTS0_OFFSET) |
1142 | & ATOM_IBIST_ERR_OFLOW) | |
e26a5843 AH |
1143 | return 1; |
1144 | ||
1145 | return 0; | |
53a788a7 AG |
1146 | } |
1147 | ||
2f887b9a | 1148 | static inline enum ntb_topo atom_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd) |
53a788a7 | 1149 | { |
2f887b9a DJ |
1150 | switch (ppd & ATOM_PPD_TOPO_MASK) { |
1151 | case ATOM_PPD_TOPO_B2B_USD: | |
e26a5843 AH |
1152 | dev_dbg(ndev_dev(ndev), "PPD %d B2B USD\n", ppd); |
1153 | return NTB_TOPO_B2B_USD; | |
1154 | ||
2f887b9a | 1155 | case ATOM_PPD_TOPO_B2B_DSD: |
e26a5843 AH |
1156 | dev_dbg(ndev_dev(ndev), "PPD %d B2B DSD\n", ppd); |
1157 | return NTB_TOPO_B2B_DSD; | |
1158 | ||
2f887b9a DJ |
1159 | case ATOM_PPD_TOPO_PRI_USD: |
1160 | case ATOM_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */ | |
1161 | case ATOM_PPD_TOPO_SEC_USD: | |
1162 | case ATOM_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */ | |
e26a5843 AH |
1163 | dev_dbg(ndev_dev(ndev), "PPD %d non B2B disabled\n", ppd); |
1164 | return NTB_TOPO_NONE; | |
1165 | } | |
fce8a7bb | 1166 | |
e26a5843 AH |
1167 | dev_dbg(ndev_dev(ndev), "PPD %d invalid\n", ppd); |
1168 | return NTB_TOPO_NONE; | |
1169 | } | |
1170 | ||
2f887b9a | 1171 | static void atom_link_hb(struct work_struct *work) |
e26a5843 AH |
1172 | { |
1173 | struct intel_ntb_dev *ndev = hb_ndev(work); | |
1174 | unsigned long poll_ts; | |
1175 | void __iomem *mmio; | |
1176 | u32 status32; | |
1177 | ||
2f887b9a | 1178 | poll_ts = ndev->last_ts + ATOM_LINK_HB_TIMEOUT; |
e26a5843 AH |
1179 | |
1180 | /* Delay polling the link status if an interrupt was received, | |
1181 | * unless the cached link status says the link is down. | |
1182 | */ | |
2f887b9a | 1183 | if (time_after(poll_ts, jiffies) && atom_link_is_up(ndev)) { |
e26a5843 AH |
1184 | schedule_delayed_work(&ndev->hb_timer, poll_ts - jiffies); |
1185 | return; | |
fce8a7bb JM |
1186 | } |
1187 | ||
2f887b9a | 1188 | if (atom_poll_link(ndev)) |
e26a5843 AH |
1189 | ntb_link_event(&ndev->ntb); |
1190 | ||
2f887b9a DJ |
1191 | if (atom_link_is_up(ndev) || !atom_link_is_err(ndev)) { |
1192 | schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_HB_TIMEOUT); | |
e26a5843 | 1193 | return; |
fce8a7bb JM |
1194 | } |
1195 | ||
e26a5843 | 1196 | /* Link is down with error: recover the link! */ |
fce8a7bb | 1197 | |
e26a5843 | 1198 | mmio = ndev->self_mmio; |
fce8a7bb | 1199 | |
e26a5843 | 1200 | /* Driver resets the NTB ModPhy lanes - magic! */ |
2f887b9a DJ |
1201 | iowrite8(0xe0, mmio + ATOM_MODPHY_PCSREG6); |
1202 | iowrite8(0x40, mmio + ATOM_MODPHY_PCSREG4); | |
1203 | iowrite8(0x60, mmio + ATOM_MODPHY_PCSREG4); | |
1204 | iowrite8(0x60, mmio + ATOM_MODPHY_PCSREG6); | |
fce8a7bb | 1205 | |
e26a5843 AH |
1206 | /* Driver waits 100ms to allow the NTB ModPhy to settle */ |
1207 | msleep(100); | |
1208 | ||
1209 | /* Clear AER Errors, write to clear */ | |
2f887b9a | 1210 | status32 = ioread32(mmio + ATOM_ERRCORSTS_OFFSET); |
e26a5843 AH |
1211 | dev_dbg(ndev_dev(ndev), "ERRCORSTS = %x\n", status32); |
1212 | status32 &= PCI_ERR_COR_REP_ROLL; | |
2f887b9a | 1213 | iowrite32(status32, mmio + ATOM_ERRCORSTS_OFFSET); |
e26a5843 AH |
1214 | |
1215 | /* Clear unexpected electrical idle event in LTSSM, write to clear */ | |
2f887b9a | 1216 | status32 = ioread32(mmio + ATOM_LTSSMERRSTS0_OFFSET); |
e26a5843 | 1217 | dev_dbg(ndev_dev(ndev), "LTSSMERRSTS0 = %x\n", status32); |
2f887b9a DJ |
1218 | status32 |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; |
1219 | iowrite32(status32, mmio + ATOM_LTSSMERRSTS0_OFFSET); | |
e26a5843 AH |
1220 | |
1221 | /* Clear DeSkew Buffer error, write to clear */ | |
2f887b9a | 1222 | status32 = ioread32(mmio + ATOM_DESKEWSTS_OFFSET); |
e26a5843 | 1223 | dev_dbg(ndev_dev(ndev), "DESKEWSTS = %x\n", status32); |
2f887b9a DJ |
1224 | status32 |= ATOM_DESKEWSTS_DBERR; |
1225 | iowrite32(status32, mmio + ATOM_DESKEWSTS_OFFSET); | |
e26a5843 | 1226 | |
2f887b9a | 1227 | status32 = ioread32(mmio + ATOM_IBSTERRRCRVSTS0_OFFSET); |
e26a5843 | 1228 | dev_dbg(ndev_dev(ndev), "IBSTERRRCRVSTS0 = %x\n", status32); |
2f887b9a DJ |
1229 | status32 &= ATOM_IBIST_ERR_OFLOW; |
1230 | iowrite32(status32, mmio + ATOM_IBSTERRRCRVSTS0_OFFSET); | |
e26a5843 AH |
1231 | |
1232 | /* Releases the NTB state machine to allow the link to retrain */ | |
2f887b9a | 1233 | status32 = ioread32(mmio + ATOM_LTSSMSTATEJMP_OFFSET); |
e26a5843 | 1234 | dev_dbg(ndev_dev(ndev), "LTSSMSTATEJMP = %x\n", status32); |
2f887b9a DJ |
1235 | status32 &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; |
1236 | iowrite32(status32, mmio + ATOM_LTSSMSTATEJMP_OFFSET); | |
e26a5843 AH |
1237 | |
1238 | /* There is a potential race between the 2 NTB devices recovering at the | |
1239 | * same time. If the times are the same, the link will not recover and | |
1240 | * the driver will be stuck in this loop forever. Add a random interval | |
1241 | * to the recovery time to prevent this race. | |
1242 | */ | |
2f887b9a DJ |
1243 | schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_RECOVERY_TIME |
1244 | + prandom_u32() % ATOM_LINK_RECOVERY_TIME); | |
fce8a7bb JM |
1245 | } |
1246 | ||
2f887b9a | 1247 | static int atom_init_isr(struct intel_ntb_dev *ndev) |
fce8a7bb | 1248 | { |
fce8a7bb JM |
1249 | int rc; |
1250 | ||
2f887b9a DJ |
1251 | rc = ndev_init_isr(ndev, 1, ATOM_DB_MSIX_VECTOR_COUNT, |
1252 | ATOM_DB_MSIX_VECTOR_SHIFT, ATOM_DB_TOTAL_SHIFT); | |
fce8a7bb JM |
1253 | if (rc) |
1254 | return rc; | |
1255 | ||
2f887b9a | 1256 | /* ATOM doesn't have link status interrupt, poll on that platform */ |
e26a5843 | 1257 | ndev->last_ts = jiffies; |
2f887b9a DJ |
1258 | INIT_DELAYED_WORK(&ndev->hb_timer, atom_link_hb); |
1259 | schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_HB_TIMEOUT); | |
fce8a7bb JM |
1260 | |
1261 | return 0; | |
1262 | } | |
1263 | ||
2f887b9a | 1264 | static void atom_deinit_isr(struct intel_ntb_dev *ndev) |
fce8a7bb | 1265 | { |
e26a5843 AH |
1266 | cancel_delayed_work_sync(&ndev->hb_timer); |
1267 | ndev_deinit_isr(ndev); | |
1268 | } | |
fce8a7bb | 1269 | |
2f887b9a | 1270 | static int atom_init_ntb(struct intel_ntb_dev *ndev) |
e26a5843 | 1271 | { |
2f887b9a DJ |
1272 | ndev->mw_count = ATOM_MW_COUNT; |
1273 | ndev->spad_count = ATOM_SPAD_COUNT; | |
1274 | ndev->db_count = ATOM_DB_COUNT; | |
fce8a7bb | 1275 | |
e26a5843 AH |
1276 | switch (ndev->ntb.topo) { |
1277 | case NTB_TOPO_B2B_USD: | |
1278 | case NTB_TOPO_B2B_DSD: | |
2f887b9a DJ |
1279 | ndev->self_reg = &atom_pri_reg; |
1280 | ndev->peer_reg = &atom_b2b_reg; | |
1281 | ndev->xlat_reg = &atom_sec_xlat; | |
e26a5843 AH |
1282 | |
1283 | /* Enable Bus Master and Memory Space on the secondary side */ | |
1284 | iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, | |
2f887b9a | 1285 | ndev->self_mmio + ATOM_SPCICMD_OFFSET); |
e26a5843 AH |
1286 | |
1287 | break; | |
1288 | ||
1289 | default: | |
1290 | return -EINVAL; | |
1291 | } | |
1292 | ||
1293 | ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; | |
fce8a7bb JM |
1294 | |
1295 | return 0; | |
1296 | } | |
1297 | ||
2f887b9a | 1298 | static int atom_init_dev(struct intel_ntb_dev *ndev) |
fce8a7bb | 1299 | { |
e26a5843 | 1300 | u32 ppd; |
fce8a7bb JM |
1301 | int rc; |
1302 | ||
2f887b9a | 1303 | rc = pci_read_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET, &ppd); |
e26a5843 AH |
1304 | if (rc) |
1305 | return -EIO; | |
fce8a7bb | 1306 | |
2f887b9a | 1307 | ndev->ntb.topo = atom_ppd_topo(ndev, ppd); |
e26a5843 AH |
1308 | if (ndev->ntb.topo == NTB_TOPO_NONE) |
1309 | return -EINVAL; | |
fce8a7bb | 1310 | |
2f887b9a | 1311 | rc = atom_init_ntb(ndev); |
e26a5843 AH |
1312 | if (rc) |
1313 | return rc; | |
fce8a7bb | 1314 | |
2f887b9a | 1315 | rc = atom_init_isr(ndev); |
e26a5843 | 1316 | if (rc) |
fce8a7bb | 1317 | return rc; |
e26a5843 AH |
1318 | |
1319 | if (ndev->ntb.topo != NTB_TOPO_SEC) { | |
1320 | /* Initiate PCI-E link training */ | |
2f887b9a DJ |
1321 | rc = pci_write_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET, |
1322 | ppd | ATOM_PPD_INIT_LINK); | |
e26a5843 AH |
1323 | if (rc) |
1324 | return rc; | |
fce8a7bb JM |
1325 | } |
1326 | ||
fce8a7bb JM |
1327 | return 0; |
1328 | } | |
1329 | ||
2f887b9a | 1330 | static void atom_deinit_dev(struct intel_ntb_dev *ndev) |
fce8a7bb | 1331 | { |
2f887b9a | 1332 | atom_deinit_isr(ndev); |
e26a5843 | 1333 | } |
fce8a7bb | 1334 | |
2f887b9a | 1335 | /* XEON */ |
fce8a7bb | 1336 | |
2f887b9a | 1337 | static u64 xeon_db_ioread(void __iomem *mmio) |
e26a5843 AH |
1338 | { |
1339 | return (u64)ioread16(mmio); | |
1340 | } | |
fce8a7bb | 1341 | |
2f887b9a | 1342 | static void xeon_db_iowrite(u64 bits, void __iomem *mmio) |
e26a5843 AH |
1343 | { |
1344 | iowrite16((u16)bits, mmio); | |
1345 | } | |
fce8a7bb | 1346 | |
2f887b9a | 1347 | static int xeon_poll_link(struct intel_ntb_dev *ndev) |
e26a5843 AH |
1348 | { |
1349 | u16 reg_val; | |
1350 | int rc; | |
1351 | ||
1352 | ndev->reg->db_iowrite(ndev->db_link_mask, | |
1353 | ndev->self_mmio + | |
1354 | ndev->self_reg->db_bell); | |
1355 | ||
1356 | rc = pci_read_config_word(ndev->ntb.pdev, | |
2f887b9a | 1357 | XEON_LINK_STATUS_OFFSET, ®_val); |
e26a5843 AH |
1358 | if (rc) |
1359 | return 0; | |
1360 | ||
1361 | if (reg_val == ndev->lnk_sta) | |
1362 | return 0; | |
1363 | ||
1364 | ndev->lnk_sta = reg_val; | |
1365 | ||
1366 | return 1; | |
fce8a7bb JM |
1367 | } |
1368 | ||
2f887b9a | 1369 | static int xeon_link_is_up(struct intel_ntb_dev *ndev) |
fce8a7bb | 1370 | { |
5ae0beb6 DJ |
1371 | if (ndev->ntb.topo == NTB_TOPO_SEC) |
1372 | return 1; | |
1373 | ||
e26a5843 AH |
1374 | return NTB_LNK_STA_ACTIVE(ndev->lnk_sta); |
1375 | } | |
fce8a7bb | 1376 | |
2f887b9a | 1377 | static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd) |
e26a5843 | 1378 | { |
2f887b9a DJ |
1379 | switch (ppd & XEON_PPD_TOPO_MASK) { |
1380 | case XEON_PPD_TOPO_B2B_USD: | |
e26a5843 AH |
1381 | return NTB_TOPO_B2B_USD; |
1382 | ||
2f887b9a | 1383 | case XEON_PPD_TOPO_B2B_DSD: |
e26a5843 AH |
1384 | return NTB_TOPO_B2B_DSD; |
1385 | ||
2f887b9a DJ |
1386 | case XEON_PPD_TOPO_PRI_USD: |
1387 | case XEON_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */ | |
e26a5843 | 1388 | return NTB_TOPO_PRI; |
fce8a7bb | 1389 | |
2f887b9a DJ |
1390 | case XEON_PPD_TOPO_SEC_USD: |
1391 | case XEON_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */ | |
e26a5843 | 1392 | return NTB_TOPO_SEC; |
fce8a7bb JM |
1393 | } |
1394 | ||
e26a5843 | 1395 | return NTB_TOPO_NONE; |
fce8a7bb JM |
1396 | } |
1397 | ||
2f887b9a | 1398 | static inline int xeon_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd) |
fce8a7bb | 1399 | { |
2f887b9a | 1400 | if (ppd & XEON_PPD_SPLIT_BAR_MASK) { |
e26a5843 AH |
1401 | dev_dbg(ndev_dev(ndev), "PPD %d split bar\n", ppd); |
1402 | return 1; | |
1403 | } | |
1404 | return 0; | |
1405 | } | |
fce8a7bb | 1406 | |
2f887b9a | 1407 | static int xeon_init_isr(struct intel_ntb_dev *ndev) |
e26a5843 | 1408 | { |
2f887b9a DJ |
1409 | return ndev_init_isr(ndev, XEON_DB_MSIX_VECTOR_COUNT, |
1410 | XEON_DB_MSIX_VECTOR_COUNT, | |
1411 | XEON_DB_MSIX_VECTOR_SHIFT, | |
1412 | XEON_DB_TOTAL_SHIFT); | |
e26a5843 | 1413 | } |
fce8a7bb | 1414 | |
2f887b9a | 1415 | static void xeon_deinit_isr(struct intel_ntb_dev *ndev) |
e26a5843 AH |
1416 | { |
1417 | ndev_deinit_isr(ndev); | |
fce8a7bb JM |
1418 | } |
1419 | ||
2f887b9a DJ |
1420 | static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev, |
1421 | const struct intel_b2b_addr *addr, | |
1422 | const struct intel_b2b_addr *peer_addr) | |
6465d02e | 1423 | { |
e26a5843 AH |
1424 | struct pci_dev *pdev; |
1425 | void __iomem *mmio; | |
1426 | resource_size_t bar_size; | |
1427 | phys_addr_t bar_addr; | |
1428 | int b2b_bar; | |
1429 | u8 bar_sz; | |
1430 | ||
1431 | pdev = ndev_pdev(ndev); | |
1432 | mmio = ndev->self_mmio; | |
1433 | ||
1434 | if (ndev->b2b_idx >= ndev->mw_count) { | |
1435 | dev_dbg(ndev_dev(ndev), "not using b2b mw\n"); | |
1436 | b2b_bar = 0; | |
1437 | ndev->b2b_off = 0; | |
1438 | } else { | |
1439 | b2b_bar = ndev_mw_to_bar(ndev, ndev->b2b_idx); | |
1440 | if (b2b_bar < 0) | |
1441 | return -EIO; | |
6465d02e | 1442 | |
e26a5843 | 1443 | dev_dbg(ndev_dev(ndev), "using b2b mw bar %d\n", b2b_bar); |
6465d02e | 1444 | |
e26a5843 | 1445 | bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar); |
6465d02e | 1446 | |
e26a5843 | 1447 | dev_dbg(ndev_dev(ndev), "b2b bar size %#llx\n", bar_size); |
6465d02e | 1448 | |
2f887b9a | 1449 | if (b2b_mw_share && XEON_B2B_MIN_SIZE <= bar_size >> 1) { |
e26a5843 AH |
1450 | dev_dbg(ndev_dev(ndev), |
1451 | "b2b using first half of bar\n"); | |
1452 | ndev->b2b_off = bar_size >> 1; | |
2f887b9a | 1453 | } else if (XEON_B2B_MIN_SIZE <= bar_size) { |
e26a5843 AH |
1454 | dev_dbg(ndev_dev(ndev), |
1455 | "b2b using whole bar\n"); | |
1456 | ndev->b2b_off = 0; | |
1457 | --ndev->mw_count; | |
1458 | } else { | |
1459 | dev_dbg(ndev_dev(ndev), | |
1460 | "b2b bar size is too small\n"); | |
1461 | return -EIO; | |
1462 | } | |
6465d02e JM |
1463 | } |
1464 | ||
e26a5843 AH |
1465 | /* Reset the secondary bar sizes to match the primary bar sizes, |
1466 | * except disable or halve the size of the b2b secondary bar. | |
1467 | * | |
1468 | * Note: code for each specific bar size register, because the register | |
1469 | * offsets are not in a consistent order (bar5sz comes after ppd, odd). | |
1470 | */ | |
2f887b9a | 1471 | pci_read_config_byte(pdev, XEON_PBAR23SZ_OFFSET, &bar_sz); |
e26a5843 AH |
1472 | dev_dbg(ndev_dev(ndev), "PBAR23SZ %#x\n", bar_sz); |
1473 | if (b2b_bar == 2) { | |
1474 | if (ndev->b2b_off) | |
1475 | bar_sz -= 1; | |
1476 | else | |
1477 | bar_sz = 0; | |
1478 | } | |
2f887b9a DJ |
1479 | pci_write_config_byte(pdev, XEON_SBAR23SZ_OFFSET, bar_sz); |
1480 | pci_read_config_byte(pdev, XEON_SBAR23SZ_OFFSET, &bar_sz); | |
e26a5843 AH |
1481 | dev_dbg(ndev_dev(ndev), "SBAR23SZ %#x\n", bar_sz); |
1482 | ||
1483 | if (!ndev->bar4_split) { | |
2f887b9a | 1484 | pci_read_config_byte(pdev, XEON_PBAR45SZ_OFFSET, &bar_sz); |
e26a5843 AH |
1485 | dev_dbg(ndev_dev(ndev), "PBAR45SZ %#x\n", bar_sz); |
1486 | if (b2b_bar == 4) { | |
1487 | if (ndev->b2b_off) | |
1488 | bar_sz -= 1; | |
1489 | else | |
1490 | bar_sz = 0; | |
1491 | } | |
2f887b9a DJ |
1492 | pci_write_config_byte(pdev, XEON_SBAR45SZ_OFFSET, bar_sz); |
1493 | pci_read_config_byte(pdev, XEON_SBAR45SZ_OFFSET, &bar_sz); | |
e26a5843 AH |
1494 | dev_dbg(ndev_dev(ndev), "SBAR45SZ %#x\n", bar_sz); |
1495 | } else { | |
2f887b9a | 1496 | pci_read_config_byte(pdev, XEON_PBAR4SZ_OFFSET, &bar_sz); |
e26a5843 AH |
1497 | dev_dbg(ndev_dev(ndev), "PBAR4SZ %#x\n", bar_sz); |
1498 | if (b2b_bar == 4) { | |
1499 | if (ndev->b2b_off) | |
1500 | bar_sz -= 1; | |
1501 | else | |
1502 | bar_sz = 0; | |
1503 | } | |
2f887b9a DJ |
1504 | pci_write_config_byte(pdev, XEON_SBAR4SZ_OFFSET, bar_sz); |
1505 | pci_read_config_byte(pdev, XEON_SBAR4SZ_OFFSET, &bar_sz); | |
e26a5843 AH |
1506 | dev_dbg(ndev_dev(ndev), "SBAR4SZ %#x\n", bar_sz); |
1507 | ||
2f887b9a | 1508 | pci_read_config_byte(pdev, XEON_PBAR5SZ_OFFSET, &bar_sz); |
e26a5843 AH |
1509 | dev_dbg(ndev_dev(ndev), "PBAR5SZ %#x\n", bar_sz); |
1510 | if (b2b_bar == 5) { | |
1511 | if (ndev->b2b_off) | |
1512 | bar_sz -= 1; | |
1513 | else | |
1514 | bar_sz = 0; | |
1515 | } | |
2f887b9a DJ |
1516 | pci_write_config_byte(pdev, XEON_SBAR5SZ_OFFSET, bar_sz); |
1517 | pci_read_config_byte(pdev, XEON_SBAR5SZ_OFFSET, &bar_sz); | |
e26a5843 AH |
1518 | dev_dbg(ndev_dev(ndev), "SBAR5SZ %#x\n", bar_sz); |
1519 | } | |
6465d02e | 1520 | |
e26a5843 AH |
1521 | /* SBAR01 hit by first part of the b2b bar */ |
1522 | if (b2b_bar == 0) | |
1523 | bar_addr = addr->bar0_addr; | |
1524 | else if (b2b_bar == 2) | |
1525 | bar_addr = addr->bar2_addr64; | |
1526 | else if (b2b_bar == 4 && !ndev->bar4_split) | |
1527 | bar_addr = addr->bar4_addr64; | |
1528 | else if (b2b_bar == 4) | |
1529 | bar_addr = addr->bar4_addr32; | |
1530 | else if (b2b_bar == 5) | |
1531 | bar_addr = addr->bar5_addr32; | |
1532 | else | |
1533 | return -EIO; | |
6465d02e | 1534 | |
e26a5843 | 1535 | dev_dbg(ndev_dev(ndev), "SBAR01 %#018llx\n", bar_addr); |
2f887b9a | 1536 | iowrite64(bar_addr, mmio + XEON_SBAR0BASE_OFFSET); |
6465d02e | 1537 | |
e26a5843 AH |
1538 | /* Other SBAR are normally hit by the PBAR xlat, except for b2b bar. |
1539 | * The b2b bar is either disabled above, or configured half-size, and | |
1540 | * it starts at the PBAR xlat + offset. | |
1541 | */ | |
1517a3f2 | 1542 | |
e26a5843 | 1543 | bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); |
2f887b9a DJ |
1544 | iowrite64(bar_addr, mmio + XEON_SBAR23BASE_OFFSET); |
1545 | bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET); | |
e26a5843 AH |
1546 | dev_dbg(ndev_dev(ndev), "SBAR23 %#018llx\n", bar_addr); |
1547 | ||
1548 | if (!ndev->bar4_split) { | |
1549 | bar_addr = addr->bar4_addr64 + | |
1550 | (b2b_bar == 4 ? ndev->b2b_off : 0); | |
2f887b9a DJ |
1551 | iowrite64(bar_addr, mmio + XEON_SBAR45BASE_OFFSET); |
1552 | bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET); | |
e26a5843 AH |
1553 | dev_dbg(ndev_dev(ndev), "SBAR45 %#018llx\n", bar_addr); |
1554 | } else { | |
1555 | bar_addr = addr->bar4_addr32 + | |
1556 | (b2b_bar == 4 ? ndev->b2b_off : 0); | |
2f887b9a DJ |
1557 | iowrite32(bar_addr, mmio + XEON_SBAR4BASE_OFFSET); |
1558 | bar_addr = ioread32(mmio + XEON_SBAR4BASE_OFFSET); | |
e26a5843 AH |
1559 | dev_dbg(ndev_dev(ndev), "SBAR4 %#010llx\n", bar_addr); |
1560 | ||
1561 | bar_addr = addr->bar5_addr32 + | |
1562 | (b2b_bar == 5 ? ndev->b2b_off : 0); | |
2f887b9a DJ |
1563 | iowrite32(bar_addr, mmio + XEON_SBAR5BASE_OFFSET); |
1564 | bar_addr = ioread32(mmio + XEON_SBAR5BASE_OFFSET); | |
e26a5843 AH |
1565 | dev_dbg(ndev_dev(ndev), "SBAR5 %#010llx\n", bar_addr); |
1566 | } | |
1517a3f2 | 1567 | |
e26a5843 | 1568 | /* setup incoming bar limits == base addrs (zero length windows) */ |
1517a3f2 | 1569 | |
e26a5843 | 1570 | bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0); |
2f887b9a DJ |
1571 | iowrite64(bar_addr, mmio + XEON_SBAR23LMT_OFFSET); |
1572 | bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET); | |
e26a5843 | 1573 | dev_dbg(ndev_dev(ndev), "SBAR23LMT %#018llx\n", bar_addr); |
1517a3f2 | 1574 | |
e26a5843 AH |
1575 | if (!ndev->bar4_split) { |
1576 | bar_addr = addr->bar4_addr64 + | |
1577 | (b2b_bar == 4 ? ndev->b2b_off : 0); | |
2f887b9a DJ |
1578 | iowrite64(bar_addr, mmio + XEON_SBAR45LMT_OFFSET); |
1579 | bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET); | |
e26a5843 AH |
1580 | dev_dbg(ndev_dev(ndev), "SBAR45LMT %#018llx\n", bar_addr); |
1581 | } else { | |
1582 | bar_addr = addr->bar4_addr32 + | |
1583 | (b2b_bar == 4 ? ndev->b2b_off : 0); | |
2f887b9a DJ |
1584 | iowrite32(bar_addr, mmio + XEON_SBAR4LMT_OFFSET); |
1585 | bar_addr = ioread32(mmio + XEON_SBAR4LMT_OFFSET); | |
e26a5843 AH |
1586 | dev_dbg(ndev_dev(ndev), "SBAR4LMT %#010llx\n", bar_addr); |
1587 | ||
1588 | bar_addr = addr->bar5_addr32 + | |
1589 | (b2b_bar == 5 ? ndev->b2b_off : 0); | |
2f887b9a DJ |
1590 | iowrite32(bar_addr, mmio + XEON_SBAR5LMT_OFFSET); |
1591 | bar_addr = ioread32(mmio + XEON_SBAR5LMT_OFFSET); | |
e26a5843 | 1592 | dev_dbg(ndev_dev(ndev), "SBAR5LMT %#05llx\n", bar_addr); |
1517a3f2 | 1593 | } |
1517a3f2 | 1594 | |
e26a5843 | 1595 | /* zero incoming translation addrs */ |
2f887b9a | 1596 | iowrite64(0, mmio + XEON_SBAR23XLAT_OFFSET); |
78958433 | 1597 | |
e26a5843 | 1598 | if (!ndev->bar4_split) { |
2f887b9a | 1599 | iowrite64(0, mmio + XEON_SBAR45XLAT_OFFSET); |
e26a5843 | 1600 | } else { |
2f887b9a DJ |
1601 | iowrite32(0, mmio + XEON_SBAR4XLAT_OFFSET); |
1602 | iowrite32(0, mmio + XEON_SBAR5XLAT_OFFSET); | |
e26a5843 | 1603 | } |
ab760a0c | 1604 | |
e26a5843 | 1605 | /* zero outgoing translation limits (whole bar size windows) */ |
2f887b9a | 1606 | iowrite64(0, mmio + XEON_PBAR23LMT_OFFSET); |
e26a5843 | 1607 | if (!ndev->bar4_split) { |
2f887b9a | 1608 | iowrite64(0, mmio + XEON_PBAR45LMT_OFFSET); |
e26a5843 | 1609 | } else { |
2f887b9a DJ |
1610 | iowrite32(0, mmio + XEON_PBAR4LMT_OFFSET); |
1611 | iowrite32(0, mmio + XEON_PBAR5LMT_OFFSET); | |
78958433 | 1612 | } |
9fec60c4 | 1613 | |
e26a5843 AH |
1614 | /* set outgoing translation offsets */ |
1615 | bar_addr = peer_addr->bar2_addr64; | |
2f887b9a DJ |
1616 | iowrite64(bar_addr, mmio + XEON_PBAR23XLAT_OFFSET); |
1617 | bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET); | |
e26a5843 AH |
1618 | dev_dbg(ndev_dev(ndev), "PBAR23XLAT %#018llx\n", bar_addr); |
1619 | ||
1620 | if (!ndev->bar4_split) { | |
1621 | bar_addr = peer_addr->bar4_addr64; | |
2f887b9a DJ |
1622 | iowrite64(bar_addr, mmio + XEON_PBAR45XLAT_OFFSET); |
1623 | bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET); | |
e26a5843 AH |
1624 | dev_dbg(ndev_dev(ndev), "PBAR45XLAT %#018llx\n", bar_addr); |
1625 | } else { | |
1626 | bar_addr = peer_addr->bar4_addr32; | |
2f887b9a DJ |
1627 | iowrite32(bar_addr, mmio + XEON_PBAR4XLAT_OFFSET); |
1628 | bar_addr = ioread32(mmio + XEON_PBAR4XLAT_OFFSET); | |
e26a5843 AH |
1629 | dev_dbg(ndev_dev(ndev), "PBAR4XLAT %#010llx\n", bar_addr); |
1630 | ||
1631 | bar_addr = peer_addr->bar5_addr32; | |
2f887b9a DJ |
1632 | iowrite32(bar_addr, mmio + XEON_PBAR5XLAT_OFFSET); |
1633 | bar_addr = ioread32(mmio + XEON_PBAR5XLAT_OFFSET); | |
e26a5843 AH |
1634 | dev_dbg(ndev_dev(ndev), "PBAR5XLAT %#010llx\n", bar_addr); |
1635 | } | |
9fec60c4 | 1636 | |
e26a5843 AH |
1637 | /* set the translation offset for b2b registers */ |
1638 | if (b2b_bar == 0) | |
1639 | bar_addr = peer_addr->bar0_addr; | |
1640 | else if (b2b_bar == 2) | |
1641 | bar_addr = peer_addr->bar2_addr64; | |
1642 | else if (b2b_bar == 4 && !ndev->bar4_split) | |
1643 | bar_addr = peer_addr->bar4_addr64; | |
1644 | else if (b2b_bar == 4) | |
1645 | bar_addr = peer_addr->bar4_addr32; | |
1646 | else if (b2b_bar == 5) | |
1647 | bar_addr = peer_addr->bar5_addr32; | |
1648 | else | |
1649 | return -EIO; | |
1650 | ||
1651 | /* B2B_XLAT_OFFSET is 64bit, but can only take 32bit writes */ | |
1652 | dev_dbg(ndev_dev(ndev), "B2BXLAT %#018llx\n", bar_addr); | |
2f887b9a DJ |
1653 | iowrite32(bar_addr, mmio + XEON_B2B_XLAT_OFFSETL); |
1654 | iowrite32(bar_addr >> 32, mmio + XEON_B2B_XLAT_OFFSETU); | |
e26a5843 AH |
1655 | |
1656 | if (b2b_bar) { | |
1657 | /* map peer ntb mmio config space registers */ | |
1658 | ndev->peer_mmio = pci_iomap(pdev, b2b_bar, | |
2f887b9a | 1659 | XEON_B2B_MIN_SIZE); |
e26a5843 AH |
1660 | if (!ndev->peer_mmio) |
1661 | return -EIO; | |
9fec60c4 JM |
1662 | } |
1663 | ||
e26a5843 | 1664 | return 0; |
9fec60c4 JM |
1665 | } |
1666 | ||
2f887b9a | 1667 | static int xeon_init_ntb(struct intel_ntb_dev *ndev) |
ab760a0c | 1668 | { |
e26a5843 | 1669 | int rc; |
5ae0beb6 | 1670 | u32 ntb_ctl; |
e26a5843 AH |
1671 | |
1672 | if (ndev->bar4_split) | |
1673 | ndev->mw_count = HSX_SPLIT_BAR_MW_COUNT; | |
ab760a0c | 1674 | else |
2f887b9a | 1675 | ndev->mw_count = XEON_MW_COUNT; |
ab760a0c | 1676 | |
2f887b9a DJ |
1677 | ndev->spad_count = XEON_SPAD_COUNT; |
1678 | ndev->db_count = XEON_DB_COUNT; | |
1679 | ndev->db_link_mask = XEON_DB_LINK_BIT; | |
1db97f25 | 1680 | |
e26a5843 AH |
1681 | switch (ndev->ntb.topo) { |
1682 | case NTB_TOPO_PRI: | |
1683 | if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { | |
1684 | dev_err(ndev_dev(ndev), "NTB Primary config disabled\n"); | |
1685 | return -EINVAL; | |
1686 | } | |
5ae0beb6 DJ |
1687 | |
1688 | /* enable link to allow secondary side device to appear */ | |
1689 | ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); | |
1690 | ntb_ctl &= ~NTB_CTL_DISABLE; | |
1691 | iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); | |
1692 | ||
e26a5843 AH |
1693 | /* use half the spads for the peer */ |
1694 | ndev->spad_count >>= 1; | |
2f887b9a DJ |
1695 | ndev->self_reg = &xeon_pri_reg; |
1696 | ndev->peer_reg = &xeon_sec_reg; | |
1697 | ndev->xlat_reg = &xeon_sec_xlat; | |
e26a5843 | 1698 | break; |
1db97f25 | 1699 | |
e26a5843 AH |
1700 | case NTB_TOPO_SEC: |
1701 | if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { | |
1702 | dev_err(ndev_dev(ndev), "NTB Secondary config disabled\n"); | |
1703 | return -EINVAL; | |
1704 | } | |
1705 | /* use half the spads for the peer */ | |
1706 | ndev->spad_count >>= 1; | |
2f887b9a DJ |
1707 | ndev->self_reg = &xeon_sec_reg; |
1708 | ndev->peer_reg = &xeon_pri_reg; | |
1709 | ndev->xlat_reg = &xeon_pri_xlat; | |
e26a5843 | 1710 | break; |
1db97f25 | 1711 | |
e26a5843 AH |
1712 | case NTB_TOPO_B2B_USD: |
1713 | case NTB_TOPO_B2B_DSD: | |
2f887b9a DJ |
1714 | ndev->self_reg = &xeon_pri_reg; |
1715 | ndev->peer_reg = &xeon_b2b_reg; | |
1716 | ndev->xlat_reg = &xeon_sec_xlat; | |
1db97f25 | 1717 | |
e26a5843 | 1718 | if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) { |
2f887b9a | 1719 | ndev->peer_reg = &xeon_pri_reg; |
ab760a0c | 1720 | |
e26a5843 AH |
1721 | if (b2b_mw_idx < 0) |
1722 | ndev->b2b_idx = b2b_mw_idx + ndev->mw_count; | |
1723 | else | |
1724 | ndev->b2b_idx = b2b_mw_idx; | |
ab760a0c | 1725 | |
e26a5843 AH |
1726 | dev_dbg(ndev_dev(ndev), |
1727 | "setting up b2b mw idx %d means %d\n", | |
1728 | b2b_mw_idx, ndev->b2b_idx); | |
1729 | ||
1730 | } else if (ndev->hwerr_flags & NTB_HWERR_B2BDOORBELL_BIT14) { | |
1731 | dev_warn(ndev_dev(ndev), "Reduce doorbell count by 1\n"); | |
1732 | ndev->db_count -= 1; | |
1733 | } | |
1734 | ||
1735 | if (ndev->ntb.topo == NTB_TOPO_B2B_USD) { | |
2f887b9a DJ |
1736 | rc = xeon_setup_b2b_mw(ndev, |
1737 | &xeon_b2b_dsd_addr, | |
1738 | &xeon_b2b_usd_addr); | |
e26a5843 | 1739 | } else { |
2f887b9a DJ |
1740 | rc = xeon_setup_b2b_mw(ndev, |
1741 | &xeon_b2b_usd_addr, | |
1742 | &xeon_b2b_dsd_addr); | |
e26a5843 AH |
1743 | } |
1744 | if (rc) | |
1745 | return rc; | |
1746 | ||
1747 | /* Enable Bus Master and Memory Space on the secondary side */ | |
1748 | iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, | |
2f887b9a | 1749 | ndev->self_mmio + XEON_SPCICMD_OFFSET); |
ab760a0c | 1750 | |
1db97f25 | 1751 | break; |
e26a5843 | 1752 | |
1db97f25 | 1753 | default: |
e26a5843 | 1754 | return -EINVAL; |
1db97f25 DJ |
1755 | } |
1756 | ||
e26a5843 AH |
1757 | ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; |
1758 | ||
1759 | ndev->reg->db_iowrite(ndev->db_valid_mask, | |
1760 | ndev->self_mmio + | |
1761 | ndev->self_reg->db_mask); | |
ab760a0c | 1762 | |
1db97f25 DJ |
1763 | return 0; |
1764 | } | |
1765 | ||
2f887b9a | 1766 | static int xeon_init_dev(struct intel_ntb_dev *ndev) |
1db97f25 | 1767 | { |
e26a5843 AH |
1768 | struct pci_dev *pdev; |
1769 | u8 ppd; | |
1770 | int rc, mem; | |
1771 | ||
dd5d4d8e DJ |
1772 | pdev = ndev_pdev(ndev); |
1773 | ||
1774 | switch (pdev->device) { | |
e26a5843 AH |
1775 | /* There is a Xeon hardware errata related to writes to SDOORBELL or |
1776 | * B2BDOORBELL in conjunction with inbound access to NTB MMIO Space, | |
1777 | * which may hang the system. To workaround this use the second memory | |
1778 | * window to access the interrupt and scratch pad registers on the | |
1779 | * remote system. | |
1780 | */ | |
dd5d4d8e DJ |
1781 | case PCI_DEVICE_ID_INTEL_NTB_SS_JSF: |
1782 | case PCI_DEVICE_ID_INTEL_NTB_PS_JSF: | |
1783 | case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF: | |
1784 | case PCI_DEVICE_ID_INTEL_NTB_SS_SNB: | |
1785 | case PCI_DEVICE_ID_INTEL_NTB_PS_SNB: | |
1786 | case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB: | |
1787 | case PCI_DEVICE_ID_INTEL_NTB_SS_IVT: | |
1788 | case PCI_DEVICE_ID_INTEL_NTB_PS_IVT: | |
1789 | case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT: | |
1790 | case PCI_DEVICE_ID_INTEL_NTB_SS_HSX: | |
1791 | case PCI_DEVICE_ID_INTEL_NTB_PS_HSX: | |
1792 | case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX: | |
1793 | ndev->hwerr_flags |= NTB_HWERR_SDOORBELL_LOCKUP; | |
1794 | break; | |
1795 | } | |
1db97f25 | 1796 | |
dd5d4d8e | 1797 | switch (pdev->device) { |
e26a5843 AH |
1798 | /* There is a hardware errata related to accessing any register in |
1799 | * SB01BASE in the presence of bidirectional traffic crossing the NTB. | |
1800 | */ | |
dd5d4d8e DJ |
1801 | case PCI_DEVICE_ID_INTEL_NTB_SS_IVT: |
1802 | case PCI_DEVICE_ID_INTEL_NTB_PS_IVT: | |
1803 | case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT: | |
1804 | case PCI_DEVICE_ID_INTEL_NTB_SS_HSX: | |
1805 | case PCI_DEVICE_ID_INTEL_NTB_PS_HSX: | |
1806 | case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX: | |
1807 | ndev->hwerr_flags |= NTB_HWERR_SB01BASE_LOCKUP; | |
1808 | break; | |
1809 | } | |
e26a5843 | 1810 | |
dd5d4d8e | 1811 | switch (pdev->device) { |
e26a5843 AH |
1812 | /* HW Errata on bit 14 of b2bdoorbell register. Writes will not be |
1813 | * mirrored to the remote system. Shrink the number of bits by one, | |
1814 | * since bit 14 is the last bit. | |
1815 | */ | |
dd5d4d8e DJ |
1816 | case PCI_DEVICE_ID_INTEL_NTB_SS_JSF: |
1817 | case PCI_DEVICE_ID_INTEL_NTB_PS_JSF: | |
1818 | case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF: | |
1819 | case PCI_DEVICE_ID_INTEL_NTB_SS_SNB: | |
1820 | case PCI_DEVICE_ID_INTEL_NTB_PS_SNB: | |
1821 | case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB: | |
1822 | case PCI_DEVICE_ID_INTEL_NTB_SS_IVT: | |
1823 | case PCI_DEVICE_ID_INTEL_NTB_PS_IVT: | |
1824 | case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT: | |
1825 | case PCI_DEVICE_ID_INTEL_NTB_SS_HSX: | |
1826 | case PCI_DEVICE_ID_INTEL_NTB_PS_HSX: | |
1827 | case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX: | |
1828 | ndev->hwerr_flags |= NTB_HWERR_B2BDOORBELL_BIT14; | |
1829 | break; | |
1830 | } | |
1db97f25 | 1831 | |
2f887b9a | 1832 | ndev->reg = &xeon_reg; |
e26a5843 | 1833 | |
2f887b9a | 1834 | rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd); |
1db97f25 | 1835 | if (rc) |
e26a5843 | 1836 | return -EIO; |
1db97f25 | 1837 | |
2f887b9a | 1838 | ndev->ntb.topo = xeon_ppd_topo(ndev, ppd); |
e26a5843 AH |
1839 | dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd, |
1840 | ntb_topo_string(ndev->ntb.topo)); | |
1841 | if (ndev->ntb.topo == NTB_TOPO_NONE) | |
1db97f25 | 1842 | return -EINVAL; |
e26a5843 AH |
1843 | |
1844 | if (ndev->ntb.topo != NTB_TOPO_SEC) { | |
2f887b9a | 1845 | ndev->bar4_split = xeon_ppd_bar4_split(ndev, ppd); |
e26a5843 AH |
1846 | dev_dbg(ndev_dev(ndev), "ppd %#x bar4_split %d\n", |
1847 | ppd, ndev->bar4_split); | |
1848 | } else { | |
1849 | /* This is a way for transparent BAR to figure out if we are | |
1850 | * doing split BAR or not. There is no way for the hw on the | |
1851 | * transparent side to know and set the PPD. | |
1852 | */ | |
1853 | mem = pci_select_bars(pdev, IORESOURCE_MEM); | |
1854 | ndev->bar4_split = hweight32(mem) == | |
1855 | HSX_SPLIT_BAR_MW_COUNT + 1; | |
1856 | dev_dbg(ndev_dev(ndev), "mem %#x bar4_split %d\n", | |
1857 | mem, ndev->bar4_split); | |
1db97f25 DJ |
1858 | } |
1859 | ||
2f887b9a | 1860 | rc = xeon_init_ntb(ndev); |
e26a5843 AH |
1861 | if (rc) |
1862 | return rc; | |
1db97f25 | 1863 | |
2f887b9a | 1864 | return xeon_init_isr(ndev); |
e26a5843 AH |
1865 | } |
1866 | ||
2f887b9a | 1867 | static void xeon_deinit_dev(struct intel_ntb_dev *ndev) |
e26a5843 | 1868 | { |
2f887b9a | 1869 | xeon_deinit_isr(ndev); |
1db97f25 DJ |
1870 | } |
1871 | ||
e26a5843 | 1872 | static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev) |
1db97f25 DJ |
1873 | { |
1874 | int rc; | |
1875 | ||
e26a5843 AH |
1876 | pci_set_drvdata(pdev, ndev); |
1877 | ||
1878 | rc = pci_enable_device(pdev); | |
1879 | if (rc) | |
1880 | goto err_pci_enable; | |
1881 | ||
1882 | rc = pci_request_regions(pdev, NTB_NAME); | |
1883 | if (rc) | |
1884 | goto err_pci_regions; | |
1885 | ||
1886 | pci_set_master(pdev); | |
1887 | ||
1888 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
1889 | if (rc) { | |
1890 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1891 | if (rc) | |
1892 | goto err_dma_mask; | |
1893 | dev_warn(ndev_dev(ndev), "Cannot DMA highmem\n"); | |
1894 | } | |
1db97f25 | 1895 | |
e26a5843 AH |
1896 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
1897 | if (rc) { | |
1898 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1899 | if (rc) | |
1900 | goto err_dma_mask; | |
1901 | dev_warn(ndev_dev(ndev), "Cannot DMA consistent highmem\n"); | |
1902 | } | |
1903 | ||
1904 | ndev->self_mmio = pci_iomap(pdev, 0, 0); | |
1905 | if (!ndev->self_mmio) { | |
1906 | rc = -EIO; | |
1907 | goto err_mmio; | |
1908 | } | |
1909 | ndev->peer_mmio = ndev->self_mmio; | |
1db97f25 DJ |
1910 | |
1911 | return 0; | |
e26a5843 AH |
1912 | |
1913 | err_mmio: | |
1914 | err_dma_mask: | |
1915 | pci_clear_master(pdev); | |
1916 | pci_release_regions(pdev); | |
1917 | err_pci_regions: | |
1918 | pci_disable_device(pdev); | |
1919 | err_pci_enable: | |
1920 | pci_set_drvdata(pdev, NULL); | |
1921 | return rc; | |
1db97f25 DJ |
1922 | } |
1923 | ||
e26a5843 | 1924 | static void intel_ntb_deinit_pci(struct intel_ntb_dev *ndev) |
fce8a7bb | 1925 | { |
e26a5843 | 1926 | struct pci_dev *pdev = ndev_pdev(ndev); |
fce8a7bb | 1927 | |
e26a5843 AH |
1928 | if (ndev->peer_mmio && ndev->peer_mmio != ndev->self_mmio) |
1929 | pci_iounmap(pdev, ndev->peer_mmio); | |
1930 | pci_iounmap(pdev, ndev->self_mmio); | |
fce8a7bb | 1931 | |
e26a5843 AH |
1932 | pci_clear_master(pdev); |
1933 | pci_release_regions(pdev); | |
1934 | pci_disable_device(pdev); | |
1935 | pci_set_drvdata(pdev, NULL); | |
1936 | } | |
069684e8 | 1937 | |
e26a5843 AH |
1938 | static inline void ndev_init_struct(struct intel_ntb_dev *ndev, |
1939 | struct pci_dev *pdev) | |
1940 | { | |
1941 | ndev->ntb.pdev = pdev; | |
1942 | ndev->ntb.topo = NTB_TOPO_NONE; | |
1943 | ndev->ntb.ops = &intel_ntb_ops; | |
069684e8 | 1944 | |
e26a5843 AH |
1945 | ndev->b2b_off = 0; |
1946 | ndev->b2b_idx = INT_MAX; | |
fce8a7bb | 1947 | |
e26a5843 | 1948 | ndev->bar4_split = 0; |
fce8a7bb | 1949 | |
e26a5843 AH |
1950 | ndev->mw_count = 0; |
1951 | ndev->spad_count = 0; | |
1952 | ndev->db_count = 0; | |
1953 | ndev->db_vec_count = 0; | |
1954 | ndev->db_vec_shift = 0; | |
fce8a7bb | 1955 | |
e26a5843 AH |
1956 | ndev->ntb_ctl = 0; |
1957 | ndev->lnk_sta = 0; | |
1db97f25 | 1958 | |
e26a5843 AH |
1959 | ndev->db_valid_mask = 0; |
1960 | ndev->db_link_mask = 0; | |
1961 | ndev->db_mask = 0; | |
ab760a0c | 1962 | |
e26a5843 AH |
1963 | spin_lock_init(&ndev->db_mask_lock); |
1964 | } | |
ab760a0c | 1965 | |
e26a5843 AH |
1966 | static int intel_ntb_pci_probe(struct pci_dev *pdev, |
1967 | const struct pci_device_id *id) | |
1968 | { | |
1969 | struct intel_ntb_dev *ndev; | |
0e041fb5 AH |
1970 | int rc, node; |
1971 | ||
1972 | node = dev_to_node(&pdev->dev); | |
fce8a7bb | 1973 | |
2f887b9a | 1974 | if (pdev_is_atom(pdev)) { |
0e041fb5 | 1975 | ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); |
e26a5843 AH |
1976 | if (!ndev) { |
1977 | rc = -ENOMEM; | |
1978 | goto err_ndev; | |
1979 | } | |
fce8a7bb | 1980 | |
e26a5843 | 1981 | ndev_init_struct(ndev, pdev); |
ab760a0c | 1982 | |
e26a5843 AH |
1983 | rc = intel_ntb_init_pci(ndev, pdev); |
1984 | if (rc) | |
1985 | goto err_init_pci; | |
1986 | ||
2f887b9a | 1987 | rc = atom_init_dev(ndev); |
e26a5843 AH |
1988 | if (rc) |
1989 | goto err_init_dev; | |
ab760a0c | 1990 | |
2f887b9a | 1991 | } else if (pdev_is_xeon(pdev)) { |
0e041fb5 | 1992 | ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node); |
e26a5843 AH |
1993 | if (!ndev) { |
1994 | rc = -ENOMEM; | |
1995 | goto err_ndev; | |
fce8a7bb | 1996 | } |
fce8a7bb | 1997 | |
e26a5843 | 1998 | ndev_init_struct(ndev, pdev); |
fce8a7bb | 1999 | |
e26a5843 AH |
2000 | rc = intel_ntb_init_pci(ndev, pdev); |
2001 | if (rc) | |
2002 | goto err_init_pci; | |
fce8a7bb | 2003 | |
2f887b9a | 2004 | rc = xeon_init_dev(ndev); |
fce8a7bb | 2005 | if (rc) |
e26a5843 | 2006 | goto err_init_dev; |
fce8a7bb | 2007 | |
e26a5843 AH |
2008 | } else { |
2009 | rc = -EINVAL; | |
2010 | goto err_ndev; | |
fce8a7bb JM |
2011 | } |
2012 | ||
e26a5843 | 2013 | ndev_reset_unsafe_flags(ndev); |
fce8a7bb | 2014 | |
e26a5843 | 2015 | ndev->reg->poll_link(ndev); |
fce8a7bb | 2016 | |
e26a5843 | 2017 | ndev_init_debugfs(ndev); |
fce8a7bb | 2018 | |
e26a5843 | 2019 | rc = ntb_register_device(&ndev->ntb); |
fce8a7bb | 2020 | if (rc) |
e26a5843 | 2021 | goto err_register; |
fce8a7bb | 2022 | |
7eb38781 DJ |
2023 | dev_info(&pdev->dev, "NTB device registered.\n"); |
2024 | ||
fce8a7bb JM |
2025 | return 0; |
2026 | ||
e26a5843 AH |
2027 | err_register: |
2028 | ndev_deinit_debugfs(ndev); | |
2f887b9a DJ |
2029 | if (pdev_is_atom(pdev)) |
2030 | atom_deinit_dev(ndev); | |
2031 | else if (pdev_is_xeon(pdev)) | |
2032 | xeon_deinit_dev(ndev); | |
e26a5843 AH |
2033 | err_init_dev: |
2034 | intel_ntb_deinit_pci(ndev); | |
2035 | err_init_pci: | |
fce8a7bb | 2036 | kfree(ndev); |
e26a5843 | 2037 | err_ndev: |
fce8a7bb JM |
2038 | return rc; |
2039 | } | |
2040 | ||
e26a5843 | 2041 | static void intel_ntb_pci_remove(struct pci_dev *pdev) |
fce8a7bb | 2042 | { |
e26a5843 AH |
2043 | struct intel_ntb_dev *ndev = pci_get_drvdata(pdev); |
2044 | ||
2045 | ntb_unregister_device(&ndev->ntb); | |
2046 | ndev_deinit_debugfs(ndev); | |
2f887b9a DJ |
2047 | if (pdev_is_atom(pdev)) |
2048 | atom_deinit_dev(ndev); | |
2049 | else if (pdev_is_xeon(pdev)) | |
2050 | xeon_deinit_dev(ndev); | |
e26a5843 AH |
2051 | intel_ntb_deinit_pci(ndev); |
2052 | kfree(ndev); | |
2053 | } | |
fce8a7bb | 2054 | |
2f887b9a DJ |
2055 | static const struct intel_ntb_reg atom_reg = { |
2056 | .poll_link = atom_poll_link, | |
2057 | .link_is_up = atom_link_is_up, | |
2058 | .db_ioread = atom_db_ioread, | |
2059 | .db_iowrite = atom_db_iowrite, | |
e26a5843 | 2060 | .db_size = sizeof(u64), |
2f887b9a | 2061 | .ntb_ctl = ATOM_NTBCNTL_OFFSET, |
e26a5843 AH |
2062 | .mw_bar = {2, 4}, |
2063 | }; | |
fce8a7bb | 2064 | |
2f887b9a DJ |
2065 | static const struct intel_ntb_alt_reg atom_pri_reg = { |
2066 | .db_bell = ATOM_PDOORBELL_OFFSET, | |
2067 | .db_mask = ATOM_PDBMSK_OFFSET, | |
2068 | .spad = ATOM_SPAD_OFFSET, | |
e26a5843 | 2069 | }; |
fce8a7bb | 2070 | |
2f887b9a DJ |
2071 | static const struct intel_ntb_alt_reg atom_b2b_reg = { |
2072 | .db_bell = ATOM_B2B_DOORBELL_OFFSET, | |
2073 | .spad = ATOM_B2B_SPAD_OFFSET, | |
e26a5843 | 2074 | }; |
fce8a7bb | 2075 | |
2f887b9a DJ |
2076 | static const struct intel_ntb_xlat_reg atom_sec_xlat = { |
2077 | /* FIXME : .bar0_base = ATOM_SBAR0BASE_OFFSET, */ | |
2078 | /* FIXME : .bar2_limit = ATOM_SBAR2LMT_OFFSET, */ | |
2079 | .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, | |
e26a5843 | 2080 | }; |
ab760a0c | 2081 | |
2f887b9a DJ |
2082 | static const struct intel_ntb_reg xeon_reg = { |
2083 | .poll_link = xeon_poll_link, | |
2084 | .link_is_up = xeon_link_is_up, | |
2085 | .db_ioread = xeon_db_ioread, | |
2086 | .db_iowrite = xeon_db_iowrite, | |
e26a5843 | 2087 | .db_size = sizeof(u32), |
2f887b9a | 2088 | .ntb_ctl = XEON_NTBCNTL_OFFSET, |
e26a5843 AH |
2089 | .mw_bar = {2, 4, 5}, |
2090 | }; | |
fce8a7bb | 2091 | |
2f887b9a DJ |
2092 | static const struct intel_ntb_alt_reg xeon_pri_reg = { |
2093 | .db_bell = XEON_PDOORBELL_OFFSET, | |
2094 | .db_mask = XEON_PDBMSK_OFFSET, | |
2095 | .spad = XEON_SPAD_OFFSET, | |
e26a5843 AH |
2096 | }; |
2097 | ||
2f887b9a DJ |
2098 | static const struct intel_ntb_alt_reg xeon_sec_reg = { |
2099 | .db_bell = XEON_SDOORBELL_OFFSET, | |
2100 | .db_mask = XEON_SDBMSK_OFFSET, | |
e26a5843 | 2101 | /* second half of the scratchpads */ |
2f887b9a | 2102 | .spad = XEON_SPAD_OFFSET + (XEON_SPAD_COUNT << 1), |
e26a5843 | 2103 | }; |
fce8a7bb | 2104 | |
2f887b9a DJ |
2105 | static const struct intel_ntb_alt_reg xeon_b2b_reg = { |
2106 | .db_bell = XEON_B2B_DOORBELL_OFFSET, | |
2107 | .spad = XEON_B2B_SPAD_OFFSET, | |
e26a5843 AH |
2108 | }; |
2109 | ||
2f887b9a | 2110 | static const struct intel_ntb_xlat_reg xeon_pri_xlat = { |
e26a5843 AH |
2111 | /* Note: no primary .bar0_base visible to the secondary side. |
2112 | * | |
2113 | * The secondary side cannot get the base address stored in primary | |
2114 | * bars. The base address is necessary to set the limit register to | |
2115 | * any value other than zero, or unlimited. | |
2116 | * | |
2117 | * WITHOUT THE BASE ADDRESS, THE SECONDARY SIDE CANNOT DISABLE the | |
2118 | * window by setting the limit equal to base, nor can it limit the size | |
2119 | * of the memory window by setting the limit to base + size. | |
2120 | */ | |
2f887b9a DJ |
2121 | .bar2_limit = XEON_PBAR23LMT_OFFSET, |
2122 | .bar2_xlat = XEON_PBAR23XLAT_OFFSET, | |
e26a5843 AH |
2123 | }; |
2124 | ||
2f887b9a DJ |
2125 | static const struct intel_ntb_xlat_reg xeon_sec_xlat = { |
2126 | .bar0_base = XEON_SBAR0BASE_OFFSET, | |
2127 | .bar2_limit = XEON_SBAR23LMT_OFFSET, | |
2128 | .bar2_xlat = XEON_SBAR23XLAT_OFFSET, | |
e26a5843 AH |
2129 | }; |
2130 | ||
2f887b9a DJ |
2131 | static struct intel_b2b_addr xeon_b2b_usd_addr = { |
2132 | .bar2_addr64 = XEON_B2B_BAR2_USD_ADDR64, | |
2133 | .bar4_addr64 = XEON_B2B_BAR4_USD_ADDR64, | |
2134 | .bar4_addr32 = XEON_B2B_BAR4_USD_ADDR32, | |
2135 | .bar5_addr32 = XEON_B2B_BAR5_USD_ADDR32, | |
e26a5843 AH |
2136 | }; |
2137 | ||
2f887b9a DJ |
2138 | static struct intel_b2b_addr xeon_b2b_dsd_addr = { |
2139 | .bar2_addr64 = XEON_B2B_BAR2_DSD_ADDR64, | |
2140 | .bar4_addr64 = XEON_B2B_BAR4_DSD_ADDR64, | |
2141 | .bar4_addr32 = XEON_B2B_BAR4_DSD_ADDR32, | |
2142 | .bar5_addr32 = XEON_B2B_BAR5_DSD_ADDR32, | |
e26a5843 AH |
2143 | }; |
2144 | ||
2145 | /* operations for primary side of local ntb */ | |
2146 | static const struct ntb_dev_ops intel_ntb_ops = { | |
2147 | .mw_count = intel_ntb_mw_count, | |
2148 | .mw_get_range = intel_ntb_mw_get_range, | |
2149 | .mw_set_trans = intel_ntb_mw_set_trans, | |
2150 | .link_is_up = intel_ntb_link_is_up, | |
2151 | .link_enable = intel_ntb_link_enable, | |
2152 | .link_disable = intel_ntb_link_disable, | |
2153 | .db_is_unsafe = intel_ntb_db_is_unsafe, | |
2154 | .db_valid_mask = intel_ntb_db_valid_mask, | |
2155 | .db_vector_count = intel_ntb_db_vector_count, | |
2156 | .db_vector_mask = intel_ntb_db_vector_mask, | |
2157 | .db_read = intel_ntb_db_read, | |
2158 | .db_clear = intel_ntb_db_clear, | |
2159 | .db_set_mask = intel_ntb_db_set_mask, | |
2160 | .db_clear_mask = intel_ntb_db_clear_mask, | |
2161 | .peer_db_addr = intel_ntb_peer_db_addr, | |
2162 | .peer_db_set = intel_ntb_peer_db_set, | |
2163 | .spad_is_unsafe = intel_ntb_spad_is_unsafe, | |
2164 | .spad_count = intel_ntb_spad_count, | |
2165 | .spad_read = intel_ntb_spad_read, | |
2166 | .spad_write = intel_ntb_spad_write, | |
2167 | .peer_spad_addr = intel_ntb_peer_spad_addr, | |
2168 | .peer_spad_read = intel_ntb_peer_spad_read, | |
2169 | .peer_spad_write = intel_ntb_peer_spad_write, | |
2170 | }; | |
2171 | ||
2172 | static const struct file_operations intel_ntb_debugfs_info = { | |
2173 | .owner = THIS_MODULE, | |
2174 | .open = simple_open, | |
2175 | .read = ndev_debugfs_read, | |
2176 | }; | |
2177 | ||
2178 | static const struct pci_device_id intel_ntb_pci_tbl[] = { | |
2179 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)}, | |
2180 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)}, | |
2181 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)}, | |
2182 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)}, | |
2183 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)}, | |
2184 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)}, | |
2185 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)}, | |
2186 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)}, | |
2187 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)}, | |
2188 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)}, | |
2189 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)}, | |
2190 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)}, | |
2191 | {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)}, | |
2192 | {0} | |
2193 | }; | |
2194 | MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl); | |
2195 | ||
2196 | static struct pci_driver intel_ntb_pci_driver = { | |
fce8a7bb | 2197 | .name = KBUILD_MODNAME, |
e26a5843 AH |
2198 | .id_table = intel_ntb_pci_tbl, |
2199 | .probe = intel_ntb_pci_probe, | |
2200 | .remove = intel_ntb_pci_remove, | |
fce8a7bb | 2201 | }; |
6465d02e | 2202 | |
e26a5843 AH |
2203 | static int __init intel_ntb_pci_driver_init(void) |
2204 | { | |
7eb38781 DJ |
2205 | pr_info("%s %s\n", NTB_DESC, NTB_VER); |
2206 | ||
e26a5843 AH |
2207 | if (debugfs_initialized()) |
2208 | debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); | |
2209 | ||
2210 | return pci_register_driver(&intel_ntb_pci_driver); | |
2211 | } | |
2212 | module_init(intel_ntb_pci_driver_init); | |
2213 | ||
2214 | static void __exit intel_ntb_pci_driver_exit(void) | |
2215 | { | |
2216 | pci_unregister_driver(&intel_ntb_pci_driver); | |
2217 | ||
2218 | debugfs_remove_recursive(debugfs_dir); | |
2219 | } | |
2220 | module_exit(intel_ntb_pci_driver_exit); | |
2221 |