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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-2.6-block.git] / drivers / net / yellowfin.c
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1da177e4
LT		 1/* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
2/*
3 Written 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
03a8c661 22 [link no longer provides useful info -jgarzik]
1da177e4 23
1da177e4
LT		 24*/
25
acbbf1f1
JP		 26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
1da177e4 28#define DRV_NAME "yellowfin"
d5b20697
AG		 29#define DRV_VERSION "2.1"
30#define DRV_RELDATE "Sep 11, 2006"
1da177e4 31
1da177e4
LT		 32/* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37static int max_interrupt_work = 20;
38static int mtu;
39#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40/* System-wide count of bogus-rx frames. */
41static int bogus_rx;
42static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44#elif defined(YF_NEW) /* A future perfect board :->. */
45static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46static int fifo_cfg = 0x0028;
47#else
f71e1309
AV		 48static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
1da177e4
LT		 50#endif
51
52/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53 Setting to > 1514 effectively disables this feature. */
54static int rx_copybreak;
55
56/* Used to pass the media type, etc.
57 No media types are currently defined. These exist for driver
58 interoperability.
59*/
60#define MAX_UNITS 8 /* More are supported, limit only on options */
61static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
63
64/* Do ugly workaround for GX server chipset errata. */
65static int gx_fix;
66
67/* Operational parameters that are set at compile time. */
68
69/* Keep the ring sizes a power of two for efficiency.
70 Making the Tx ring too long decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73#define TX_RING_SIZE 16
74#define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75#define RX_RING_SIZE 64
76#define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77#define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
78#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
79
80/* Operational parameters that usually are not changed. */
81/* Time in jiffies before concluding the transmitter is hung. */
82#define TX_TIMEOUT (2*HZ)
83#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85#define yellowfin_debug debug
86
87#include <linux/module.h>
88#include <linux/kernel.h>
89#include <linux/string.h>
90#include <linux/timer.h>
91#include <linux/errno.h>
92#include <linux/ioport.h>
1da177e4
LT		 93#include <linux/interrupt.h>
94#include <linux/pci.h>
95#include <linux/init.h>
96#include <linux/mii.h>
97#include <linux/netdevice.h>
98#include <linux/etherdevice.h>
99#include <linux/skbuff.h>
100#include <linux/ethtool.h>
101#include <linux/crc32.h>
102#include <linux/bitops.h>
103#include <asm/uaccess.h>
104#include <asm/processor.h> /* Processor type for cache alignment. */
105#include <asm/unaligned.h>
106#include <asm/io.h>
107
108/* These identify the driver base version and may not be removed. */
7285484a
SH		 109static const char version[] __devinitconst =
110 KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
ad361c98 111 " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
1da177e4
LT		 112
113MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
114MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
115MODULE_LICENSE("GPL");
116
117module_param(max_interrupt_work, int, 0);
118module_param(mtu, int, 0);
119module_param(debug, int, 0);
120module_param(rx_copybreak, int, 0);
121module_param_array(options, int, NULL, 0);
122module_param_array(full_duplex, int, NULL, 0);
123module_param(gx_fix, int, 0);
124MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
125MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
126MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
127MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
128MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
129MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
130MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
131
132/*
133 Theory of Operation
134
135I. Board Compatibility
136
137This device driver is designed for the Packet Engines "Yellowfin" Gigabit
6aa20a22 138Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
1da177e4
LT		 139Symbios 53C885E dual function chip.
140
141II. Board-specific settings
142
143PCI bus devices are configured by the system at boot time, so no jumpers
144need to be set on the board. The system BIOS preferably should assign the
145PCI INTA signal to an otherwise unused system IRQ line.
146Note: Kernel versions earlier than 1.3.73 do not support shared PCI
147interrupt lines.
148
149III. Driver operation
150
151IIIa. Ring buffers
152
153The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
154This is a descriptor list scheme similar to that used by the EEPro100 and
155Tulip. This driver uses two statically allocated fixed-size descriptor lists
156formed into rings by a branch from the final descriptor to the beginning of
157the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
158
159The driver allocates full frame size skbuffs for the Rx ring buffers at
160open() time and passes the skb->data field to the Yellowfin as receive data
161buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
162a fresh skbuff is allocated and the frame is copied to the new skbuff.
163When the incoming frame is larger, the skbuff is passed directly up the
164protocol stack and replaced by a newly allocated skbuff.
165
166The RX_COPYBREAK value is chosen to trade-off the memory wasted by
167using a full-sized skbuff for small frames vs. the copying costs of larger
168frames. For small frames the copying cost is negligible (esp. considering
169that we are pre-loading the cache with immediately useful header
170information). For large frames the copying cost is non-trivial, and the
171larger copy might flush the cache of useful data.
172
173IIIC. Synchronization
174
175The driver runs as two independent, single-threaded flows of control. One
176is the send-packet routine, which enforces single-threaded use by the
177dev->tbusy flag. The other thread is the interrupt handler, which is single
178threaded by the hardware and other software.
179
180The send packet thread has partial control over the Tx ring and 'dev->tbusy'
181flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
182queue slot is empty, it clears the tbusy flag when finished otherwise it sets
183the 'yp->tx_full' flag.
184
185The interrupt handler has exclusive control over the Rx ring and records stats
186from the Tx ring. After reaping the stats, it marks the Tx queue entry as
187empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
188clears both the tx_full and tbusy flags.
189
190IV. Notes
191
192Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
193Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
194and an AlphaStation to verifty the Alpha port!
195
196IVb. References
197
198Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
199Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
200 Data Manual v3.0
201http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
202http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
203
204IVc. Errata
205
206See Packet Engines confidential appendix (prototype chips only).
207*/
208
6aa20a22 209
1da177e4 210
1da177e4
LT		 211enum capability_flags {
212 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
213 HasMACAddrBug=32, /* Only on early revs. */
214 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
215};
c3d8e682 216
1da177e4 217/* The PCI I/O space extent. */
c3d8e682
JG		 218enum {
219 YELLOWFIN_SIZE = 0x100,
220};
1da177e4
LT		 221
222struct pci_id_info {
223 const char *name;
224 struct match_info {
225 int pci, pci_mask, subsystem, subsystem_mask;
226 int revision, revision_mask; /* Only 8 bits. */
227 } id;
1da177e4
LT		 228 int drv_flags; /* Driver use, intended as capability flags. */
229};
230
f71e1309 231static const struct pci_id_info pci_id_tbl[] = {
1da177e4 232 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
1da177e4
LT		 233 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
234 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
c3d8e682 235 HasMII | DontUseEeprom },
1f1bd5fc 236 { }
1da177e4
LT		 237};
238
a3aa1884 239static DEFINE_PCI_DEVICE_TABLE(yellowfin_pci_tbl) = {
1da177e4
LT		 240 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
241 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
1f1bd5fc 242 { }
1da177e4
LT		 243};
244MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
245
246
247/* Offsets to the Yellowfin registers. Various sizes and alignments. */
248enum yellowfin_offsets {
249 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
250 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
251 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
252 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
253 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
254 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
255 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
256 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
257 MII_Status=0xAE,
258 RxDepth=0xB8, FlowCtrl=0xBC,
259 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
260 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
261 EEFeature=0xF5,
262};
263
264/* The Yellowfin Rx and Tx buffer descriptors.
265 Elements are written as 32 bit for endian portability. */
266struct yellowfin_desc {
e5a31421
AV		 267 __le32 dbdma_cmd;
268 __le32 addr;
269 __le32 branch_addr;
270 __le32 result_status;
1da177e4
LT		 271};
272
273struct tx_status_words {
274#ifdef __BIG_ENDIAN
275 u16 tx_errs;
276 u16 tx_cnt;
277 u16 paused;
278 u16 total_tx_cnt;
279#else /* Little endian chips. */
280 u16 tx_cnt;
281 u16 tx_errs;
282 u16 total_tx_cnt;
283 u16 paused;
284#endif /* __BIG_ENDIAN */
285};
286
287/* Bits in yellowfin_desc.cmd */
288enum desc_cmd_bits {
289 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
290 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
291 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
292 BRANCH_IFTRUE=0x040000,
293};
294
295/* Bits in yellowfin_desc.status */
296enum desc_status_bits { RX_EOP=0x0040, };
297
298/* Bits in the interrupt status/mask registers. */
299enum intr_status_bits {
300 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
301 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
302 IntrEarlyRx=0x100, IntrWakeup=0x200, };
303
304#define PRIV_ALIGN 31 /* Required alignment mask */
305#define MII_CNT 4
306struct yellowfin_private {
307 /* Descriptor rings first for alignment.
308 Tx requires a second descriptor for status. */
309 struct yellowfin_desc *rx_ring;
310 struct yellowfin_desc *tx_ring;
311 struct sk_buff* rx_skbuff[RX_RING_SIZE];
312 struct sk_buff* tx_skbuff[TX_RING_SIZE];
313 dma_addr_t rx_ring_dma;
314 dma_addr_t tx_ring_dma;
315
316 struct tx_status_words *tx_status;
317 dma_addr_t tx_status_dma;
318
319 struct timer_list timer; /* Media selection timer. */
1da177e4
LT		 320 /* Frequently used and paired value: keep adjacent for cache effect. */
321 int chip_id, drv_flags;
322 struct pci_dev *pci_dev;
323 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
324 unsigned int rx_buf_sz; /* Based on MTU+slack. */
325 struct tx_status_words *tx_tail_desc;
326 unsigned int cur_tx, dirty_tx;
327 int tx_threshold;
328 unsigned int tx_full:1; /* The Tx queue is full. */
329 unsigned int full_duplex:1; /* Full-duplex operation requested. */
330 unsigned int duplex_lock:1;
331 unsigned int medialock:1; /* Do not sense media. */
332 unsigned int default_port:4; /* Last dev->if_port value. */
333 /* MII transceiver section. */
334 int mii_cnt; /* MII device addresses. */
335 u16 advertising; /* NWay media advertisement */
336 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
337 spinlock_t lock;
338 void __iomem *base;
339};
340
341static int read_eeprom(void __iomem *ioaddr, int location);
342static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
343static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
344static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
345static int yellowfin_open(struct net_device *dev);
346static void yellowfin_timer(unsigned long data);
347static void yellowfin_tx_timeout(struct net_device *dev);
e7a5965a 348static int yellowfin_init_ring(struct net_device *dev);
61357325
SH		 349static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
350 struct net_device *dev);
7d12e780 351static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
1da177e4
LT		 352static int yellowfin_rx(struct net_device *dev);
353static void yellowfin_error(struct net_device *dev, int intr_status);
354static int yellowfin_close(struct net_device *dev);
1da177e4 355static void set_rx_mode(struct net_device *dev);
7282d491 356static const struct ethtool_ops ethtool_ops;
1da177e4 357
bfd82c35
SH		 358static const struct net_device_ops netdev_ops = {
359 .ndo_open = yellowfin_open,
360 .ndo_stop = yellowfin_close,
361 .ndo_start_xmit = yellowfin_start_xmit,
362 .ndo_set_multicast_list = set_rx_mode,
363 .ndo_change_mtu = eth_change_mtu,
364 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 365 .ndo_set_mac_address = eth_mac_addr,
bfd82c35
SH		 366 .ndo_do_ioctl = netdev_ioctl,
367 .ndo_tx_timeout = yellowfin_tx_timeout,
368};
1da177e4
LT		 369
370static int __devinit yellowfin_init_one(struct pci_dev *pdev,
371 const struct pci_device_id *ent)
372{
373 struct net_device *dev;
374 struct yellowfin_private *np;
375 int irq;
376 int chip_idx = ent->driver_data;
377 static int find_cnt;
378 void __iomem *ioaddr;
379 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
380 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
381 void *ring_space;
382 dma_addr_t ring_dma;
383#ifdef USE_IO_OPS
384 int bar = 0;
385#else
386 int bar = 1;
387#endif
6aa20a22 388
1da177e4
LT		 389/* when built into the kernel, we only print version if device is found */
390#ifndef MODULE
391 static int printed_version;
392 if (!printed_version++)
393 printk(version);
394#endif
395
396 i = pci_enable_device(pdev);
397 if (i) return i;
398
399 dev = alloc_etherdev(sizeof(*np));
400 if (!dev) {
acbbf1f1 401 pr_err("cannot allocate ethernet device\n");
1da177e4
LT		 402 return -ENOMEM;
403 }
1da177e4
LT		 404 SET_NETDEV_DEV(dev, &pdev->dev);
405
406 np = netdev_priv(dev);
407
408 if (pci_request_regions(pdev, DRV_NAME))
409 goto err_out_free_netdev;
410
411 pci_set_master (pdev);
412
413 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
414 if (!ioaddr)
415 goto err_out_free_res;
416
417 irq = pdev->irq;
418
419 if (drv_flags & DontUseEeprom)
420 for (i = 0; i < 6; i++)
421 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
422 else {
423 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
424 for (i = 0; i < 6; i++)
425 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
426 }
427
428 /* Reset the chip. */
429 iowrite32(0x80000000, ioaddr + DMACtrl);
430
431 dev->base_addr = (unsigned long)ioaddr;
432 dev->irq = irq;
433
434 pci_set_drvdata(pdev, dev);
435 spin_lock_init(&np->lock);
436
437 np->pci_dev = pdev;
438 np->chip_id = chip_idx;
439 np->drv_flags = drv_flags;
440 np->base = ioaddr;
441
442 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
443 if (!ring_space)
444 goto err_out_cleardev;
445 np->tx_ring = (struct yellowfin_desc *)ring_space;
446 np->tx_ring_dma = ring_dma;
447
448 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
449 if (!ring_space)
450 goto err_out_unmap_tx;
451 np->rx_ring = (struct yellowfin_desc *)ring_space;
452 np->rx_ring_dma = ring_dma;
453
454 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
455 if (!ring_space)
456 goto err_out_unmap_rx;
457 np->tx_status = (struct tx_status_words *)ring_space;
458 np->tx_status_dma = ring_dma;
459
460 if (dev->mem_start)
461 option = dev->mem_start;
462
463 /* The lower four bits are the media type. */
464 if (option > 0) {
465 if (option & 0x200)
466 np->full_duplex = 1;
467 np->default_port = option & 15;
468 if (np->default_port)
469 np->medialock = 1;
470 }
471 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
472 np->full_duplex = 1;
473
474 if (np->full_duplex)
475 np->duplex_lock = 1;
476
477 /* The Yellowfin-specific entries in the device structure. */
bfd82c35 478 dev->netdev_ops = &netdev_ops;
1da177e4 479 SET_ETHTOOL_OPS(dev, &ethtool_ops);
1da177e4
LT		 480 dev->watchdog_timeo = TX_TIMEOUT;
481
482 if (mtu)
483 dev->mtu = mtu;
484
485 i = register_netdev(dev);
486 if (i)
487 goto err_out_unmap_status;
488
acbbf1f1
JP		 489 netdev_info(dev, "%s type %8x at %p, %pM, IRQ %d\n",
490 pci_id_tbl[chip_idx].name,
491 ioread32(ioaddr + ChipRev), ioaddr,
492 dev->dev_addr, irq);
1da177e4
LT		 493
494 if (np->drv_flags & HasMII) {
495 int phy, phy_idx = 0;
496 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
497 int mii_status = mdio_read(ioaddr, phy, 1);
498 if (mii_status != 0xffff && mii_status != 0x0000) {
499 np->phys[phy_idx++] = phy;
500 np->advertising = mdio_read(ioaddr, phy, 4);
acbbf1f1
JP		 501 netdev_info(dev, "MII PHY found at address %d, status 0x%04x advertising %04x\n",
502 phy, mii_status, np->advertising);
1da177e4
LT		 503 }
504 }
505 np->mii_cnt = phy_idx;
506 }
507
508 find_cnt++;
6aa20a22 509
1da177e4
LT		 510 return 0;
511
512err_out_unmap_status:
6aa20a22 513 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1da177e4
LT		 514 np->tx_status_dma);
515err_out_unmap_rx:
516 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
517err_out_unmap_tx:
518 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
519err_out_cleardev:
520 pci_set_drvdata(pdev, NULL);
521 pci_iounmap(pdev, ioaddr);
522err_out_free_res:
523 pci_release_regions(pdev);
524err_out_free_netdev:
525 free_netdev (dev);
526 return -ENODEV;
527}
528
529static int __devinit read_eeprom(void __iomem *ioaddr, int location)
530{
531 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
532
533 iowrite8(location, ioaddr + EEAddr);
534 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
535 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
536 ;
537 return ioread8(ioaddr + EERead);
538}
539
540/* MII Managemen Data I/O accesses.
541 These routines assume the MDIO controller is idle, and do not exit until
542 the command is finished. */
543
544static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
545{
546 int i;
547
548 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
549 iowrite16(1, ioaddr + MII_Cmd);
550 for (i = 10000; i >= 0; i--)
551 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
552 break;
553 return ioread16(ioaddr + MII_Rd_Data);
554}
555
556static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
557{
558 int i;
559
560 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
561 iowrite16(value, ioaddr + MII_Wr_Data);
562
563 /* Wait for the command to finish. */
564 for (i = 10000; i >= 0; i--)
565 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
566 break;
567 return;
568}
569
6aa20a22 570
1da177e4
LT		 571static int yellowfin_open(struct net_device *dev)
572{
573 struct yellowfin_private *yp = netdev_priv(dev);
574 void __iomem *ioaddr = yp->base;
e7a5965a 575 int i, ret;
1da177e4
LT		 576
577 /* Reset the chip. */
578 iowrite32(0x80000000, ioaddr + DMACtrl);
579
a0607fd3 580 ret = request_irq(dev->irq, yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
e7a5965a
RK		 581 if (ret)
582 return ret;
1da177e4
LT		 583
584 if (yellowfin_debug > 1)
acbbf1f1
JP		 585 netdev_printk(KERN_DEBUG, dev, "%s() irq %d\n",
586 __func__, dev->irq);
1da177e4 587
e7a5965a
RK		 588 ret = yellowfin_init_ring(dev);
589 if (ret) {
590 free_irq(dev->irq, dev);
591 return ret;
592 }
1da177e4
LT		 593
594 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
595 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
596
597 for (i = 0; i < 6; i++)
598 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
599
600 /* Set up various condition 'select' registers.
601 There are no options here. */
602 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
603 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
604 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
605 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
606 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
607 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
608
609 /* Initialize other registers: with so many this eventually this will
610 converted to an offset/value list. */
611 iowrite32(dma_ctrl, ioaddr + DMACtrl);
612 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
613 /* Enable automatic generation of flow control frames, period 0xffff. */
614 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
615
616 yp->tx_threshold = 32;
617 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
618
619 if (dev->if_port == 0)
620 dev->if_port = yp->default_port;
621
622 netif_start_queue(dev);
623
624 /* Setting the Rx mode will start the Rx process. */
625 if (yp->drv_flags & IsGigabit) {
626 /* We are always in full-duplex mode with gigabit! */
627 yp->full_duplex = 1;
628 iowrite16(0x01CF, ioaddr + Cnfg);
629 } else {
630 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
631 iowrite16(0x1018, ioaddr + FrameGap1);
632 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
633 }
634 set_rx_mode(dev);
635
636 /* Enable interrupts by setting the interrupt mask. */
637 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
638 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
639 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
640 iowrite32(0x80008000, ioaddr + TxCtrl);
641
642 if (yellowfin_debug > 2) {
acbbf1f1 643 netdev_printk(KERN_DEBUG, dev, "Done %s()\n", __func__);
1da177e4
LT		 644 }
645
646 /* Set the timer to check for link beat. */
647 init_timer(&yp->timer);
648 yp->timer.expires = jiffies + 3*HZ;
649 yp->timer.data = (unsigned long)dev;
650 yp->timer.function = &yellowfin_timer; /* timer handler */
651 add_timer(&yp->timer);
652
653 return 0;
654}
655
656static void yellowfin_timer(unsigned long data)
657{
658 struct net_device *dev = (struct net_device *)data;
659 struct yellowfin_private *yp = netdev_priv(dev);
660 void __iomem *ioaddr = yp->base;
661 int next_tick = 60*HZ;
662
663 if (yellowfin_debug > 3) {
acbbf1f1
JP		 664 netdev_printk(KERN_DEBUG, dev, "Yellowfin timer tick, status %08x\n",
665 ioread16(ioaddr + IntrStatus));
1da177e4
LT		 666 }
667
668 if (yp->mii_cnt) {
669 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
670 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
671 int negotiated = lpa & yp->advertising;
672 if (yellowfin_debug > 1)
acbbf1f1
JP		 673 netdev_printk(KERN_DEBUG, dev, "MII #%d status register is %04x, link partner capability %04x\n",
674 yp->phys[0], bmsr, lpa);
1da177e4
LT		 675
676 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
6aa20a22 677
1da177e4
LT		 678 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
679
680 if (bmsr & BMSR_LSTATUS)
681 next_tick = 60*HZ;
682 else
683 next_tick = 3*HZ;
684 }
685
686 yp->timer.expires = jiffies + next_tick;
687 add_timer(&yp->timer);
688}
689
690static void yellowfin_tx_timeout(struct net_device *dev)
691{
692 struct yellowfin_private *yp = netdev_priv(dev);
693 void __iomem *ioaddr = yp->base;
694
acbbf1f1
JP		 695 netdev_warn(dev, "Yellowfin transmit timed out at %d/%d Tx status %04x, Rx status %04x, resetting...\n",
696 yp->cur_tx, yp->dirty_tx,
697 ioread32(ioaddr + TxStatus),
698 ioread32(ioaddr + RxStatus));
1da177e4
LT		 699
700 /* Note: these should be KERN_DEBUG. */
701 if (yellowfin_debug) {
702 int i;
acbbf1f1 703 pr_warning(" Rx ring %p: ", yp->rx_ring);
1da177e4 704 for (i = 0; i < RX_RING_SIZE; i++)
acbbf1f1
JP		 705 pr_cont(" %08x", yp->rx_ring[i].result_status);
706 pr_cont("\n");
707 pr_warning(" Tx ring %p: ", yp->tx_ring);
1da177e4 708 for (i = 0; i < TX_RING_SIZE; i++)
acbbf1f1 709 pr_cont(" %04x /%08x",
ad361c98
JP		 710 yp->tx_status[i].tx_errs,
711 yp->tx_ring[i].result_status);
acbbf1f1 712 pr_cont("\n");
1da177e4
LT		 713 }
714
715 /* If the hardware is found to hang regularly, we will update the code
716 to reinitialize the chip here. */
717 dev->if_port = 0;
718
719 /* Wake the potentially-idle transmit channel. */
720 iowrite32(0x10001000, yp->base + TxCtrl);
721 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
722 netif_wake_queue (dev); /* Typical path */
723
cdd0db05 724 dev->trans_start = jiffies; /* prevent tx timeout */
09f75cd7 725 dev->stats.tx_errors++;
1da177e4
LT		 726}
727
728/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
e7a5965a 729static int yellowfin_init_ring(struct net_device *dev)
1da177e4
LT		 730{
731 struct yellowfin_private *yp = netdev_priv(dev);
e7a5965a 732 int i, j;
1da177e4
LT		 733
734 yp->tx_full = 0;
735 yp->cur_rx = yp->cur_tx = 0;
736 yp->dirty_tx = 0;
737
738 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
739
740 for (i = 0; i < RX_RING_SIZE; i++) {
741 yp->rx_ring[i].dbdma_cmd =
742 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
743 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
744 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
745 }
746
747 for (i = 0; i < RX_RING_SIZE; i++) {
748 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
749 yp->rx_skbuff[i] = skb;
750 if (skb == NULL)
751 break;
752 skb->dev = dev; /* Mark as being used by this device. */
753 skb_reserve(skb, 2); /* 16 byte align the IP header. */
754 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
689be439 755 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4 756 }
e7a5965a
RK		 757 if (i != RX_RING_SIZE) {
758 for (j = 0; j < i; j++)
759 dev_kfree_skb(yp->rx_skbuff[j]);
760 return -ENOMEM;
761 }
1da177e4
LT		 762 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
763 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
764
765#define NO_TXSTATS
766#ifdef NO_TXSTATS
767 /* In this mode the Tx ring needs only a single descriptor. */
768 for (i = 0; i < TX_RING_SIZE; i++) {
769 yp->tx_skbuff[i] = NULL;
770 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
771 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
772 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
773 }
774 /* Wrap ring */
775 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
776#else
777{
1da177e4
LT		 778 /* Tx ring needs a pair of descriptors, the second for the status. */
779 for (i = 0; i < TX_RING_SIZE; i++) {
780 j = 2*i;
781 yp->tx_skbuff[i] = 0;
782 /* Branch on Tx error. */
783 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
784 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
80950f8b 785 (j+1)*sizeof(struct yellowfin_desc));
1da177e4
LT		 786 j++;
787 if (yp->flags & FullTxStatus) {
788 yp->tx_ring[j].dbdma_cmd =
789 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
790 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
791 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
80950f8b 792 i*sizeof(struct tx_status_words));
1da177e4
LT		 793 } else {
794 /* Symbios chips write only tx_errs word. */
795 yp->tx_ring[j].dbdma_cmd =
796 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
797 yp->tx_ring[j].request_cnt = 2;
798 /* Om pade ummmmm... */
799 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
800 i*sizeof(struct tx_status_words) +
6aa20a22 801 &(yp->tx_status[0].tx_errs) -
1da177e4
LT		 802 &(yp->tx_status[0]));
803 }
6aa20a22 804 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
1da177e4
LT		 805 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
806 }
807 /* Wrap ring */
808 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
809}
810#endif
811 yp->tx_tail_desc = &yp->tx_status[0];
e7a5965a 812 return 0;
1da177e4
LT		 813}
814
61357325
SH		 815static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
816 struct net_device *dev)
1da177e4
LT		 817{
818 struct yellowfin_private *yp = netdev_priv(dev);
819 unsigned entry;
820 int len = skb->len;
821
822 netif_stop_queue (dev);
823
824 /* Note: Ordering is important here, set the field with the
825 "ownership" bit last, and only then increment cur_tx. */
826
827 /* Calculate the next Tx descriptor entry. */
828 entry = yp->cur_tx % TX_RING_SIZE;
829
830 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
831 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
832 /* Fix GX chipset errata. */
833 if (cacheline_end > 24 || cacheline_end == 0) {
834 len = skb->len + 32 - cacheline_end + 1;
5b057c6b
HX		 835 if (skb_padto(skb, len)) {
836 yp->tx_skbuff[entry] = NULL;
837 netif_wake_queue(dev);
6ed10654 838 return NETDEV_TX_OK;
5b057c6b 839 }
1da177e4
LT		 840 }
841 }
842 yp->tx_skbuff[entry] = skb;
843
844#ifdef NO_TXSTATS
6aa20a22 845 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1da177e4
LT		 846 skb->data, len, PCI_DMA_TODEVICE));
847 yp->tx_ring[entry].result_status = 0;
848 if (entry >= TX_RING_SIZE-1) {
849 /* New stop command. */
850 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
851 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
852 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
853 } else {
854 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
855 yp->tx_ring[entry].dbdma_cmd =
856 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
857 }
858 yp->cur_tx++;
859#else
860 yp->tx_ring[entry<<1].request_cnt = len;
6aa20a22 861 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1da177e4 862 skb->data, len, PCI_DMA_TODEVICE));
6aa20a22 863 /* The input_last (status-write) command is constant, but we must
1da177e4
LT		 864 rewrite the subsequent 'stop' command. */
865
866 yp->cur_tx++;
867 {
868 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
869 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
870 }
871 /* Final step -- overwrite the old 'stop' command. */
872
873 yp->tx_ring[entry<<1].dbdma_cmd =
874 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
875 CMD_TX_PKT | BRANCH_IFTRUE) | len);
876#endif
877
878 /* Non-x86 Todo: explicitly flush cache lines here. */
879
880 /* Wake the potentially-idle transmit channel. */
881 iowrite32(0x10001000, yp->base + TxCtrl);
882
883 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
884 netif_start_queue (dev); /* Typical path */
885 else
886 yp->tx_full = 1;
1da177e4
LT		 887
888 if (yellowfin_debug > 4) {
acbbf1f1
JP		 889 netdev_printk(KERN_DEBUG, dev, "Yellowfin transmit frame #%d queued in slot %d\n",
890 yp->cur_tx, entry);
1da177e4 891 }
6ed10654 892 return NETDEV_TX_OK;
1da177e4
LT		 893}
894
895/* The interrupt handler does all of the Rx thread work and cleans up
896 after the Tx thread. */
7d12e780 897static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
1da177e4
LT		 898{
899 struct net_device *dev = dev_instance;
900 struct yellowfin_private *yp;
901 void __iomem *ioaddr;
902 int boguscnt = max_interrupt_work;
903 unsigned int handled = 0;
904
1da177e4
LT		 905 yp = netdev_priv(dev);
906 ioaddr = yp->base;
6aa20a22 907
1da177e4
LT		 908 spin_lock (&yp->lock);
909
910 do {
911 u16 intr_status = ioread16(ioaddr + IntrClear);
912
913 if (yellowfin_debug > 4)
acbbf1f1
JP		 914 netdev_printk(KERN_DEBUG, dev, "Yellowfin interrupt, status %04x\n",
915 intr_status);
1da177e4
LT		 916
917 if (intr_status == 0)
918 break;
919 handled = 1;
920
921 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
922 yellowfin_rx(dev);
923 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
924 }
925
926#ifdef NO_TXSTATS
927 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
928 int entry = yp->dirty_tx % TX_RING_SIZE;
929 struct sk_buff *skb;
930
931 if (yp->tx_ring[entry].result_status == 0)
932 break;
933 skb = yp->tx_skbuff[entry];
09f75cd7
JG		 934 dev->stats.tx_packets++;
935 dev->stats.tx_bytes += skb->len;
1da177e4 936 /* Free the original skb. */
e5a31421 937 pci_unmap_single(yp->pci_dev, le32_to_cpu(yp->tx_ring[entry].addr),
1da177e4
LT		 938 skb->len, PCI_DMA_TODEVICE);
939 dev_kfree_skb_irq(skb);
940 yp->tx_skbuff[entry] = NULL;
941 }
8e95a202
JP		 942 if (yp->tx_full &&
943 yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
1da177e4
LT		 944 /* The ring is no longer full, clear tbusy. */
945 yp->tx_full = 0;
946 netif_wake_queue(dev);
947 }
948#else
949 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
950 unsigned dirty_tx = yp->dirty_tx;
951
952 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
953 dirty_tx++) {
954 /* Todo: optimize this. */
955 int entry = dirty_tx % TX_RING_SIZE;
956 u16 tx_errs = yp->tx_status[entry].tx_errs;
957 struct sk_buff *skb;
958
959#ifndef final_version
960 if (yellowfin_debug > 5)
acbbf1f1
JP		 961 netdev_printk(KERN_DEBUG, dev, "Tx queue %d check, Tx status %04x %04x %04x %04x\n",
962 entry,
963 yp->tx_status[entry].tx_cnt,
964 yp->tx_status[entry].tx_errs,
965 yp->tx_status[entry].total_tx_cnt,
966 yp->tx_status[entry].paused);
1da177e4
LT		 967#endif
968 if (tx_errs == 0)
969 break; /* It still hasn't been Txed */
970 skb = yp->tx_skbuff[entry];
971 if (tx_errs & 0xF810) {
972 /* There was an major error, log it. */
973#ifndef final_version
974 if (yellowfin_debug > 1)
acbbf1f1
JP		 975 netdev_printk(KERN_DEBUG, dev, "Transmit error, Tx status %04x\n",
976 tx_errs);
1da177e4 977#endif
09f75cd7
JG		 978 dev->stats.tx_errors++;
979 if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;
980 if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;
981 if (tx_errs & 0x2000) dev->stats.tx_window_errors++;
982 if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;
1da177e4
LT		 983 } else {
984#ifndef final_version
985 if (yellowfin_debug > 4)
acbbf1f1
JP		 986 netdev_printk(KERN_DEBUG, dev, "Normal transmit, Tx status %04x\n",
987 tx_errs);
1da177e4 988#endif
09f75cd7
JG		 989 dev->stats.tx_bytes += skb->len;
990 dev->stats.collisions += tx_errs & 15;
991 dev->stats.tx_packets++;
1da177e4
LT		 992 }
993 /* Free the original skb. */
6aa20a22
JG		 994 pci_unmap_single(yp->pci_dev,
995 yp->tx_ring[entry<<1].addr, skb->len,
1da177e4
LT		 996 PCI_DMA_TODEVICE);
997 dev_kfree_skb_irq(skb);
998 yp->tx_skbuff[entry] = 0;
999 /* Mark status as empty. */
1000 yp->tx_status[entry].tx_errs = 0;
1001 }
1002
1003#ifndef final_version
1004 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
acbbf1f1
JP		 1005 netdev_err(dev, "Out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1006 dirty_tx, yp->cur_tx, yp->tx_full);
1da177e4
LT		 1007 dirty_tx += TX_RING_SIZE;
1008 }
1009#endif
1010
8e95a202
JP		 1011 if (yp->tx_full &&
1012 yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1da177e4
LT		 1013 /* The ring is no longer full, clear tbusy. */
1014 yp->tx_full = 0;
1015 netif_wake_queue(dev);
1016 }
1017
1018 yp->dirty_tx = dirty_tx;
1019 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1020 }
1021#endif
1022
1023 /* Log errors and other uncommon events. */
1024 if (intr_status & 0x2ee) /* Abnormal error summary. */
1025 yellowfin_error(dev, intr_status);
1026
1027 if (--boguscnt < 0) {
acbbf1f1
JP		 1028 netdev_warn(dev, "Too much work at interrupt, status=%#04x\n",
1029 intr_status);
1da177e4
LT		 1030 break;
1031 }
1032 } while (1);
1033
1034 if (yellowfin_debug > 3)
acbbf1f1
JP		 1035 netdev_printk(KERN_DEBUG, dev, "exiting interrupt, status=%#04x\n",
1036 ioread16(ioaddr + IntrStatus));
1da177e4
LT		 1037
1038 spin_unlock (&yp->lock);
1039 return IRQ_RETVAL(handled);
1040}
1041
1042/* This routine is logically part of the interrupt handler, but separated
1043 for clarity and better register allocation. */
1044static int yellowfin_rx(struct net_device *dev)
1045{
1046 struct yellowfin_private *yp = netdev_priv(dev);
1047 int entry = yp->cur_rx % RX_RING_SIZE;
1048 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1049
1050 if (yellowfin_debug > 4) {
acbbf1f1 1051 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %08x\n",
1da177e4 1052 entry, yp->rx_ring[entry].result_status);
acbbf1f1 1053 printk(KERN_DEBUG " #%d desc. %08x %08x %08x\n",
1da177e4
LT		 1054 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1055 yp->rx_ring[entry].result_status);
1056 }
1057
1058 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1059 while (1) {
1060 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1061 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1062 s16 frame_status;
1063 u16 desc_status;
1064 int data_size;
1065 u8 *buf_addr;
1066
1067 if(!desc->result_status)
1068 break;
e5a31421 1069 pci_dma_sync_single_for_cpu(yp->pci_dev, le32_to_cpu(desc->addr),
1da177e4
LT		 1070 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1071 desc_status = le32_to_cpu(desc->result_status) >> 16;
689be439 1072 buf_addr = rx_skb->data;
6aa20a22 1073 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1da177e4 1074 le32_to_cpu(desc->result_status)) & 0xffff;
6caf52a4 1075 frame_status = get_unaligned_le16(&(buf_addr[data_size - 2]));
1da177e4 1076 if (yellowfin_debug > 4)
acbbf1f1
JP		 1077 printk(KERN_DEBUG " %s() status was %04x\n",
1078 __func__, frame_status);
1da177e4
LT		 1079 if (--boguscnt < 0)
1080 break;
1081 if ( ! (desc_status & RX_EOP)) {
1082 if (data_size != 0)
acbbf1f1
JP		 1083 netdev_warn(dev, "Oversized Ethernet frame spanned multiple buffers, status %04x, data_size %d!\n",
1084 desc_status, data_size);
09f75cd7 1085 dev->stats.rx_length_errors++;
1da177e4
LT		 1086 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1087 /* There was a error. */
1088 if (yellowfin_debug > 3)
acbbf1f1
JP		 1089 printk(KERN_DEBUG " %s() Rx error was %04x\n",
1090 __func__, frame_status);
09f75cd7
JG		 1091 dev->stats.rx_errors++;
1092 if (frame_status & 0x0060) dev->stats.rx_length_errors++;
1093 if (frame_status & 0x0008) dev->stats.rx_frame_errors++;
1094 if (frame_status & 0x0010) dev->stats.rx_crc_errors++;
1095 if (frame_status < 0) dev->stats.rx_dropped++;
1da177e4
LT		 1096 } else if ( !(yp->drv_flags & IsGigabit) &&
1097 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1098 u8 status1 = buf_addr[data_size-2];
1099 u8 status2 = buf_addr[data_size-1];
09f75cd7
JG		 1100 dev->stats.rx_errors++;
1101 if (status1 & 0xC0) dev->stats.rx_length_errors++;
1102 if (status2 & 0x03) dev->stats.rx_frame_errors++;
1103 if (status2 & 0x04) dev->stats.rx_crc_errors++;
1104 if (status2 & 0x80) dev->stats.rx_dropped++;
1da177e4
LT		 1105#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1106 } else if ((yp->flags & HasMACAddrBug) &&
1107 memcmp(le32_to_cpu(yp->rx_ring_dma +
1108 entry*sizeof(struct yellowfin_desc)),
6aa20a22 1109 dev->dev_addr, 6) != 0 &&
1da177e4
LT		 1110 memcmp(le32_to_cpu(yp->rx_ring_dma +
1111 entry*sizeof(struct yellowfin_desc)),
1112 "\377\377\377\377\377\377", 6) != 0) {
e174961c 1113 if (bogus_rx++ == 0)
acbbf1f1
JP		 1114 netdev_warn(dev, "Bad frame to %pM\n",
1115 buf_addr);
1da177e4
LT		 1116#endif
1117 } else {
1118 struct sk_buff *skb;
1119 int pkt_len = data_size -
1120 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1121 /* To verify: Yellowfin Length should omit the CRC! */
1122
1123#ifndef final_version
1124 if (yellowfin_debug > 4)
acbbf1f1
JP		 1125 printk(KERN_DEBUG " %s() normal Rx pkt length %d of %d, bogus_cnt %d\n",
1126 __func__, pkt_len, data_size, boguscnt);
1da177e4
LT		 1127#endif
1128 /* Check if the packet is long enough to just pass up the skbuff
1129 without copying to a properly sized skbuff. */
1130 if (pkt_len > rx_copybreak) {
1131 skb_put(skb = rx_skb, pkt_len);
6aa20a22 1132 pci_unmap_single(yp->pci_dev,
e5a31421 1133 le32_to_cpu(yp->rx_ring[entry].addr),
6aa20a22 1134 yp->rx_buf_sz,
1da177e4
LT		 1135 PCI_DMA_FROMDEVICE);
1136 yp->rx_skbuff[entry] = NULL;
1137 } else {
1138 skb = dev_alloc_skb(pkt_len + 2);
1139 if (skb == NULL)
1140 break;
1da177e4 1141 skb_reserve(skb, 2); /* 16 byte align the IP header */
8c7b7faa 1142 skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1da177e4 1143 skb_put(skb, pkt_len);
e5a31421
AV		 1144 pci_dma_sync_single_for_device(yp->pci_dev,
1145 le32_to_cpu(desc->addr),
1146 yp->rx_buf_sz,
1147 PCI_DMA_FROMDEVICE);
1da177e4
LT		 1148 }
1149 skb->protocol = eth_type_trans(skb, dev);
1150 netif_rx(skb);
09f75cd7
JG		 1151 dev->stats.rx_packets++;
1152 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 1153 }
1154 entry = (++yp->cur_rx) % RX_RING_SIZE;
1155 }
1156
1157 /* Refill the Rx ring buffers. */
1158 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1159 entry = yp->dirty_rx % RX_RING_SIZE;
1160 if (yp->rx_skbuff[entry] == NULL) {
1161 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1162 if (skb == NULL)
1163 break; /* Better luck next round. */
1164 yp->rx_skbuff[entry] = skb;
1165 skb->dev = dev; /* Mark as being used by this device. */
1166 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1167 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
689be439 1168 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1169 }
1170 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1171 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1172 if (entry != 0)
1173 yp->rx_ring[entry - 1].dbdma_cmd =
1174 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1175 else
1176 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1177 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1178 | yp->rx_buf_sz);
1179 }
1180
1181 return 0;
1182}
1183
1184static void yellowfin_error(struct net_device *dev, int intr_status)
1185{
acbbf1f1 1186 netdev_err(dev, "Something Wicked happened! %04x\n", intr_status);
1da177e4
LT		 1187 /* Hmmmmm, it's not clear what to do here. */
1188 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
09f75cd7 1189 dev->stats.tx_errors++;
1da177e4 1190 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
09f75cd7 1191 dev->stats.rx_errors++;
1da177e4
LT		 1192}
1193
1194static int yellowfin_close(struct net_device *dev)
1195{
1196 struct yellowfin_private *yp = netdev_priv(dev);
1197 void __iomem *ioaddr = yp->base;
1198 int i;
1199
1200 netif_stop_queue (dev);
1201
1202 if (yellowfin_debug > 1) {
acbbf1f1
JP		 1203 netdev_printk(KERN_DEBUG, dev, "Shutting down ethercard, status was Tx %04x Rx %04x Int %02x\n",
1204 ioread16(ioaddr + TxStatus),
1205 ioread16(ioaddr + RxStatus),
1206 ioread16(ioaddr + IntrStatus));
1207 netdev_printk(KERN_DEBUG, dev, "Queue pointers were Tx %d / %d, Rx %d / %d\n",
1208 yp->cur_tx, yp->dirty_tx,
1209 yp->cur_rx, yp->dirty_rx);
1da177e4
LT		 1210 }
1211
1212 /* Disable interrupts by clearing the interrupt mask. */
1213 iowrite16(0x0000, ioaddr + IntrEnb);
1214
1215 /* Stop the chip's Tx and Rx processes. */
1216 iowrite32(0x80000000, ioaddr + RxCtrl);
1217 iowrite32(0x80000000, ioaddr + TxCtrl);
1218
1219 del_timer(&yp->timer);
1220
1221#if defined(__i386__)
1222 if (yellowfin_debug > 2) {
acbbf1f1 1223 printk(KERN_DEBUG " Tx ring at %08llx:\n",
1da177e4
LT		 1224 (unsigned long long)yp->tx_ring_dma);
1225 for (i = 0; i < TX_RING_SIZE*2; i++)
acbbf1f1 1226 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x %08x\n",
1da177e4
LT		 1227 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1228 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1229 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1230 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1231 for (i = 0; i < TX_RING_SIZE; i++)
acbbf1f1 1232 printk(KERN_DEBUG " #%d status %04x %04x %04x %04x\n",
1da177e4
LT		 1233 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1234 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1235
acbbf1f1 1236 printk(KERN_DEBUG " Rx ring %08llx:\n",
1da177e4
LT		 1237 (unsigned long long)yp->rx_ring_dma);
1238 for (i = 0; i < RX_RING_SIZE; i++) {
acbbf1f1 1239 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x\n",
1da177e4
LT		 1240 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1241 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1242 yp->rx_ring[i].result_status);
1243 if (yellowfin_debug > 6) {
1244 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1245 int j;
acbbf1f1
JP		 1246
1247 printk(KERN_DEBUG);
1da177e4 1248 for (j = 0; j < 0x50; j++)
acbbf1f1
JP		 1249 pr_cont(" %04x",
1250 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1251 pr_cont("\n");
1da177e4
LT		 1252 }
1253 }
1254 }
1255 }
1256#endif /* __i386__ debugging only */
1257
1258 free_irq(dev->irq, dev);
1259
1260 /* Free all the skbuffs in the Rx queue. */
1261 for (i = 0; i < RX_RING_SIZE; i++) {
1262 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
e5a31421 1263 yp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1da177e4
LT		 1264 if (yp->rx_skbuff[i]) {
1265 dev_kfree_skb(yp->rx_skbuff[i]);
1266 }
1267 yp->rx_skbuff[i] = NULL;
1268 }
1269 for (i = 0; i < TX_RING_SIZE; i++) {
1270 if (yp->tx_skbuff[i])
1271 dev_kfree_skb(yp->tx_skbuff[i]);
1272 yp->tx_skbuff[i] = NULL;
1273 }
1274
1275#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1276 if (yellowfin_debug > 0) {
acbbf1f1
JP		 1277 netdev_printk(KERN_DEBUG, dev, "Received %d frames that we should not have\n",
1278 bogus_rx);
1da177e4
LT		 1279 }
1280#endif
1281
1282 return 0;
1283}
1284
1da177e4
LT		 1285/* Set or clear the multicast filter for this adaptor. */
1286
1287static void set_rx_mode(struct net_device *dev)
1288{
1289 struct yellowfin_private *yp = netdev_priv(dev);
1290 void __iomem *ioaddr = yp->base;
1291 u16 cfg_value = ioread16(ioaddr + Cnfg);
1292
1293 /* Stop the Rx process to change any value. */
1294 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1295 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4 1296 iowrite16(0x000F, ioaddr + AddrMode);
4cd24eaf
JP		 1297 } else if ((netdev_mc_count(dev) > 64) ||
1298 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 1299 /* Too many to filter well, or accept all multicasts. */
1300 iowrite16(0x000B, ioaddr + AddrMode);
4cd24eaf 1301 } else if (!netdev_mc_empty(dev)) { /* Must use the multicast hash table. */
1da177e4
LT		 1302 struct dev_mc_list *mclist;
1303 u16 hash_table[4];
1304 int i;
567ec874 1305
1da177e4 1306 memset(hash_table, 0, sizeof(hash_table));
567ec874 1307 netdev_for_each_mc_addr(mclist, dev) {
1da177e4
LT		 1308 unsigned int bit;
1309
1310 /* Due to a bug in the early chip versions, multiple filter
1311 slots must be set for each address. */
1312 if (yp->drv_flags & HasMulticastBug) {
1313 bit = (ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f;
1314 hash_table[bit >> 4] |= (1 << bit);
1315 bit = (ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f;
1316 hash_table[bit >> 4] |= (1 << bit);
1317 bit = (ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f;
1318 hash_table[bit >> 4] |= (1 << bit);
1319 }
1320 bit = (ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f;
1321 hash_table[bit >> 4] |= (1 << bit);
1322 }
1323 /* Copy the hash table to the chip. */
1324 for (i = 0; i < 4; i++)
1325 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1326 iowrite16(0x0003, ioaddr + AddrMode);
1327 } else { /* Normal, unicast/broadcast-only mode. */
1328 iowrite16(0x0001, ioaddr + AddrMode);
1329 }
1330 /* Restart the Rx process. */
1331 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1332}
1333
1334static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1335{
1336 struct yellowfin_private *np = netdev_priv(dev);
1337 strcpy(info->driver, DRV_NAME);
1338 strcpy(info->version, DRV_VERSION);
1339 strcpy(info->bus_info, pci_name(np->pci_dev));
1340}
1341
7282d491 1342static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 1343 .get_drvinfo = yellowfin_get_drvinfo
1344};
1345
1346static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1347{
1348 struct yellowfin_private *np = netdev_priv(dev);
1349 void __iomem *ioaddr = np->base;
1350 struct mii_ioctl_data *data = if_mii(rq);
1351
1352 switch(cmd) {
1353 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1354 data->phy_id = np->phys[0] & 0x1f;
1355 /* Fall Through */
1356
1357 case SIOCGMIIREG: /* Read MII PHY register. */
1358 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1359 return 0;
1360
1361 case SIOCSMIIREG: /* Write MII PHY register. */
1da177e4
LT		 1362 if (data->phy_id == np->phys[0]) {
1363 u16 value = data->val_in;
1364 switch (data->reg_num) {
1365 case 0:
1366 /* Check for autonegotiation on or reset. */
1367 np->medialock = (value & 0x9000) ? 0 : 1;
1368 if (np->medialock)
1369 np->full_duplex = (value & 0x0100) ? 1 : 0;
1370 break;
1371 case 4: np->advertising = value; break;
1372 }
1373 /* Perhaps check_duplex(dev), depending on chip semantics. */
1374 }
1375 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1376 return 0;
1377 default:
1378 return -EOPNOTSUPP;
1379 }
1380}
1381
1382
1383static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1384{
1385 struct net_device *dev = pci_get_drvdata(pdev);
1386 struct yellowfin_private *np;
1387
5d9428de 1388 BUG_ON(!dev);
1da177e4
LT		 1389 np = netdev_priv(dev);
1390
6aa20a22 1391 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1da177e4
LT		 1392 np->tx_status_dma);
1393 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1394 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1395 unregister_netdev (dev);
1396
1397 pci_iounmap(pdev, np->base);
1398
1399 pci_release_regions (pdev);
1400
1401 free_netdev (dev);
1402 pci_set_drvdata(pdev, NULL);
1403}
1404
1405
1406static struct pci_driver yellowfin_driver = {
1407 .name = DRV_NAME,
1408 .id_table = yellowfin_pci_tbl,
1409 .probe = yellowfin_init_one,
1410 .remove = __devexit_p(yellowfin_remove_one),
1411};
1412
1413
1414static int __init yellowfin_init (void)
1415{
1416/* when a module, this is printed whether or not devices are found in probe */
1417#ifdef MODULE
1418 printk(version);
1419#endif
29917620 1420 return pci_register_driver(&yellowfin_driver);
1da177e4
LT		 1421}
1422
1423
1424static void __exit yellowfin_cleanup (void)
1425{
1426 pci_unregister_driver (&yellowfin_driver);
1427}
1428
1429
1430module_init(yellowfin_init);
1431module_exit(yellowfin_cleanup);
Linux 6.x block layer and io_uring tree(s)