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[linux-block.git] / drivers / net / wireless / rtl818x / rtl8187_dev.c
CommitLineData
605bebe2
MW		 1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
3461fc12
LF		 10 * The driver was extended to the RTL8187B in 2008 by:
11 * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
12 * Hin-Tak Leung <htl10@users.sourceforge.net>
13 * Larry Finger <Larry.Finger@lwfinger.net>
14 *
0aec00ae
JL		 15 * Magic delays and register offsets below are taken from the original
16 * r8187 driver sources. Thanks to Realtek for their support!
605bebe2
MW		 17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/init.h>
24#include <linux/usb.h>
25#include <linux/delay.h>
26#include <linux/etherdevice.h>
27#include <linux/eeprom_93cx6.h>
28#include <net/mac80211.h>
29
30#include "rtl8187.h"
31#include "rtl8187_rtl8225.h"
32
33MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
3461fc12
LF		 35MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
36MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
37MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
f8a08c34 38MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
605bebe2
MW		 39MODULE_LICENSE("GPL");
40
41static struct usb_device_id rtl8187_table[] __devinitdata = {
7c7e6af3
AM		 42 /* Asus */
43 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
eaca90da
FF		 44 /* Belkin */
45 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
605bebe2 46 /* Realtek */
f8a08c34
HTL		 47 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
48 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
49 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
746db510 50 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
046ee5d2
LF		 51 /* Surecom */
52 {USB_DEVICE(0x0769, 0x11F2), .driver_info = DEVICE_RTL8187},
53 /* Logitech */
54 {USB_DEVICE(0x0789, 0x010C), .driver_info = DEVICE_RTL8187},
605bebe2 55 /* Netgear */
f8a08c34
HTL		 56 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
57 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
fcd7cc14 58 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
c3cf60a9 59 /* HP */
f8a08c34 60 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
9934550d 61 /* Sitecom */
f8a08c34 62 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
f3c76918 63 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
046ee5d2
LF		 64 /* Sphairon Access Systems GmbH */
65 {USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187},
66 /* Dick Smith Electronics */
67 {USB_DEVICE(0x1371, 0x9401), .driver_info = DEVICE_RTL8187},
8f7c41d4
IK		 68 /* Abocom */
69 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
046ee5d2
LF		 70 /* Qcom */
71 {USB_DEVICE(0x18E8, 0x6232), .driver_info = DEVICE_RTL8187},
72 /* AirLive */
73 {USB_DEVICE(0x1b75, 0x8187), .driver_info = DEVICE_RTL8187},
605bebe2
MW		 74 {}
75};
76
77MODULE_DEVICE_TABLE(usb, rtl8187_table);
78
8318d78a
JB		 79static const struct ieee80211_rate rtl818x_rates[] = {
80 { .bitrate = 10, .hw_value = 0, },
81 { .bitrate = 20, .hw_value = 1, },
82 { .bitrate = 55, .hw_value = 2, },
83 { .bitrate = 110, .hw_value = 3, },
84 { .bitrate = 60, .hw_value = 4, },
85 { .bitrate = 90, .hw_value = 5, },
86 { .bitrate = 120, .hw_value = 6, },
87 { .bitrate = 180, .hw_value = 7, },
88 { .bitrate = 240, .hw_value = 8, },
89 { .bitrate = 360, .hw_value = 9, },
90 { .bitrate = 480, .hw_value = 10, },
91 { .bitrate = 540, .hw_value = 11, },
92};
93
94static const struct ieee80211_channel rtl818x_channels[] = {
95 { .center_freq = 2412 },
96 { .center_freq = 2417 },
97 { .center_freq = 2422 },
98 { .center_freq = 2427 },
99 { .center_freq = 2432 },
100 { .center_freq = 2437 },
101 { .center_freq = 2442 },
102 { .center_freq = 2447 },
103 { .center_freq = 2452 },
104 { .center_freq = 2457 },
105 { .center_freq = 2462 },
106 { .center_freq = 2467 },
107 { .center_freq = 2472 },
108 { .center_freq = 2484 },
109};
110
4150c572
JB		 111static void rtl8187_iowrite_async_cb(struct urb *urb)
112{
113 kfree(urb->context);
4150c572
JB		 114}
115
116static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
117 void *data, u16 len)
118{
119 struct usb_ctrlrequest *dr;
120 struct urb *urb;
121 struct rtl8187_async_write_data {
122 u8 data[4];
123 struct usb_ctrlrequest dr;
124 } *buf;
ea8ee240 125 int rc;
4150c572
JB		 126
127 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
128 if (!buf)
129 return;
130
131 urb = usb_alloc_urb(0, GFP_ATOMIC);
132 if (!urb) {
133 kfree(buf);
134 return;
135 }
136
137 dr = &buf->dr;
138
139 dr->bRequestType = RTL8187_REQT_WRITE;
140 dr->bRequest = RTL8187_REQ_SET_REG;
141 dr->wValue = addr;
142 dr->wIndex = 0;
143 dr->wLength = cpu_to_le16(len);
144
145 memcpy(buf, data, len);
146
147 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
148 (unsigned char *)dr, buf, len,
149 rtl8187_iowrite_async_cb, buf);
c1db52b9 150 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 151 rc = usb_submit_urb(urb, GFP_ATOMIC);
152 if (rc < 0) {
153 kfree(buf);
c1db52b9 154 usb_unanchor_urb(urb);
ea8ee240 155 }
c1db52b9 156 usb_free_urb(urb);
4150c572
JB		 157}
158
159static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
160 __le32 *addr, u32 val)
161{
162 __le32 buf = cpu_to_le32(val);
163
164 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
165 &buf, sizeof(buf));
166}
167
605bebe2
MW		 168void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
169{
170 struct rtl8187_priv *priv = dev->priv;
171
172 data <<= 8;
173 data |= addr | 0x80;
174
175 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
176 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
177 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
178 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
605bebe2
MW		 179}
180
181static void rtl8187_tx_cb(struct urb *urb)
182{
605bebe2 183 struct sk_buff *skb = (struct sk_buff *)urb->context;
e039fa4a 184 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e6a9854b 185 struct ieee80211_hw *hw = info->rate_driver_data[0];
6f7853f3 186 struct rtl8187_priv *priv = hw->priv;
605bebe2 187
6f7853f3
HTL		 188 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
189 sizeof(struct rtl8187_tx_hdr));
e6a9854b 190 ieee80211_tx_info_clear_status(info);
3517afde
HRK		 191
192 if (!urb->status &&
193 !(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
194 priv->is_rtl8187b) {
195 skb_queue_tail(&priv->b_tx_status.queue, skb);
196
197 /* queue is "full", discard last items */
198 while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
199 struct sk_buff *old_skb;
200
201 dev_dbg(&priv->udev->dev,
202 "transmit status queue full\n");
203
204 old_skb = skb_dequeue(&priv->b_tx_status.queue);
205 ieee80211_tx_status_irqsafe(hw, old_skb);
206 }
207 } else {
208 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) && !urb->status)
209 info->flags |= IEEE80211_TX_STAT_ACK;
210 ieee80211_tx_status_irqsafe(hw, skb);
211 }
605bebe2
MW		 212}
213
e039fa4a 214static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
605bebe2
MW		 215{
216 struct rtl8187_priv *priv = dev->priv;
e039fa4a 217 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
6f7853f3
HTL		 218 unsigned int ep;
219 void *buf;
605bebe2 220 struct urb *urb;
98798f48
MW		 221 __le16 rts_dur = 0;
222 u32 flags;
ea8ee240 223 int rc;
605bebe2
MW		 224
225 urb = usb_alloc_urb(0, GFP_ATOMIC);
226 if (!urb) {
227 kfree_skb(skb);
d6e2be98 228 return NETDEV_TX_OK;
605bebe2
MW		 229 }
230
98798f48 231 flags = skb->len;
38e3b0d8 232 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
aa68cbfb 233
e039fa4a 234 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
8b7b1e05 235 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
38e3b0d8 236 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
e6a9854b 237 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 238 flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 239 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
32bfd35d 240 rts_dur = ieee80211_rts_duration(dev, priv->vif,
e039fa4a 241 skb->len, info);
e6a9854b 242 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 243 flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 244 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 245 }
98798f48 246
6f7853f3
HTL		 247 if (!priv->is_rtl8187b) {
248 struct rtl8187_tx_hdr *hdr =
249 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
250 hdr->flags = cpu_to_le32(flags);
251 hdr->len = 0;
252 hdr->rts_duration = rts_dur;
d9a1f486 253 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 254 buf = hdr;
255
256 ep = 2;
257 } else {
258 /* fc needs to be calculated before skb_push() */
259 unsigned int epmap[4] = { 6, 7, 5, 4 };
260 struct ieee80211_hdr *tx_hdr =
261 (struct ieee80211_hdr *)(skb->data);
262 u16 fc = le16_to_cpu(tx_hdr->frame_control);
263
264 struct rtl8187b_tx_hdr *hdr =
265 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
266 struct ieee80211_rate *txrate =
267 ieee80211_get_tx_rate(dev, info);
268 memset(hdr, 0, sizeof(*hdr));
269 hdr->flags = cpu_to_le32(flags);
270 hdr->rts_duration = rts_dur;
d9a1f486 271 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 272 hdr->tx_duration =
273 ieee80211_generic_frame_duration(dev, priv->vif,
274 skb->len, txrate);
275 buf = hdr;
276
277 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
278 ep = 12;
279 else
280 ep = epmap[skb_get_queue_mapping(skb)];
281 }
605bebe2 282
e6a9854b
JB		 283 info->rate_driver_data[0] = dev;
284 info->rate_driver_data[1] = urb;
6f7853f3
HTL		 285
286 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
287 buf, skb->len, rtl8187_tx_cb, skb);
2fcbab04 288 urb->transfer_flags |= URB_ZERO_PACKET;
c1db52b9 289 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 290 rc = usb_submit_urb(urb, GFP_ATOMIC);
291 if (rc < 0) {
c1db52b9 292 usb_unanchor_urb(urb);
ea8ee240
ON		 293 kfree_skb(skb);
294 }
c1db52b9 295 usb_free_urb(urb);
605bebe2 296
d6e2be98 297 return NETDEV_TX_OK;
605bebe2
MW		 298}
299
300static void rtl8187_rx_cb(struct urb *urb)
301{
302 struct sk_buff *skb = (struct sk_buff *)urb->context;
303 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
304 struct ieee80211_hw *dev = info->dev;
305 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 306 struct ieee80211_rx_status rx_status = { 0 };
307 int rate, signal;
4150c572 308 u32 flags;
0ccd58fc 309 u32 quality;
d8588227 310 unsigned long f;
605bebe2 311
d8588227 312 spin_lock_irqsave(&priv->rx_queue.lock, f);
605bebe2
MW		 313 if (skb->next)
314 __skb_unlink(skb, &priv->rx_queue);
315 else {
d8588227 316 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
605bebe2
MW		 317 return;
318 }
d8588227 319 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
c1db52b9 320 skb_put(skb, urb->actual_length);
605bebe2
MW		 321
322 if (unlikely(urb->status)) {
605bebe2
MW		 323 dev_kfree_skb_irq(skb);
324 return;
325 }
326
6f7853f3
HTL		 327 if (!priv->is_rtl8187b) {
328 struct rtl8187_rx_hdr *hdr =
329 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
330 flags = le32_to_cpu(hdr->flags);
a7db74f4
LF		 331 /* As with the RTL8187B below, the AGC is used to calculate
332 * signal strength and quality. In this case, the scaling
333 * constants are derived from the output of p54usb.
334 */
335 quality = 130 - ((41 * hdr->agc) >> 6);
336 signal = -4 - ((27 * hdr->agc) >> 6);
6f7853f3 337 rx_status.antenna = (hdr->signal >> 7) & 1;
6f7853f3 338 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3
HTL		 339 } else {
340 struct rtl8187b_rx_hdr *hdr =
341 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
0ccd58fc
LF		 342 /* The Realtek datasheet for the RTL8187B shows that the RX
343 * header contains the following quantities: signal quality,
344 * RSSI, AGC, the received power in dB, and the measured SNR.
345 * In testing, none of these quantities show qualitative
346 * agreement with AP signal strength, except for the AGC,
347 * which is inversely proportional to the strength of the
348 * signal. In the following, the quality and signal strength
349 * are derived from the AGC. The arbitrary scaling constants
350 * are chosen to make the results close to the values obtained
351 * for a BCM4312 using b43 as the driver. The noise is ignored
352 * for now.
353 */
6f7853f3 354 flags = le32_to_cpu(hdr->flags);
0ccd58fc 355 quality = 170 - hdr->agc;
0ccd58fc 356 signal = 14 - hdr->agc / 2;
0ccd58fc 357 rx_status.antenna = (hdr->rssi >> 7) & 1;
6f7853f3 358 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3 359 }
605bebe2 360
a7db74f4
LF		 361 if (quality > 100)
362 quality = 100;
363 rx_status.qual = quality;
364 priv->quality = quality;
365 rx_status.signal = signal;
366 priv->signal = signal;
367 rate = (flags >> 20) & 0xF;
6f7853f3 368 skb_trim(skb, flags & 0x0FFF);
8318d78a
JB		 369 rx_status.rate_idx = rate;
370 rx_status.freq = dev->conf.channel->center_freq;
371 rx_status.band = dev->conf.channel->band;
03bffc13 372 rx_status.flag |= RX_FLAG_TSFT;
38e3b0d8 373 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
4150c572 374 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
605bebe2
MW		 375 ieee80211_rx_irqsafe(dev, skb, &rx_status);
376
377 skb = dev_alloc_skb(RTL8187_MAX_RX);
378 if (unlikely(!skb)) {
605bebe2
MW		 379 /* TODO check rx queue length and refill *somewhere* */
380 return;
381 }
382
383 info = (struct rtl8187_rx_info *)skb->cb;
384 info->urb = urb;
385 info->dev = dev;
386 urb->transfer_buffer = skb_tail_pointer(skb);
387 urb->context = skb;
388 skb_queue_tail(&priv->rx_queue, skb);
389
c1db52b9
LF		 390 usb_anchor_urb(urb, &priv->anchored);
391 if (usb_submit_urb(urb, GFP_ATOMIC)) {
392 usb_unanchor_urb(urb);
393 skb_unlink(skb, &priv->rx_queue);
394 dev_kfree_skb_irq(skb);
395 }
605bebe2
MW		 396}
397
398static int rtl8187_init_urbs(struct ieee80211_hw *dev)
399{
400 struct rtl8187_priv *priv = dev->priv;
c1db52b9 401 struct urb *entry = NULL;
605bebe2
MW		 402 struct sk_buff *skb;
403 struct rtl8187_rx_info *info;
c1db52b9 404 int ret = 0;
605bebe2
MW		 405
406 while (skb_queue_len(&priv->rx_queue) < 8) {
407 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
c1db52b9
LF		 408 if (!skb) {
409 ret = -ENOMEM;
410 goto err;
411 }
605bebe2
MW		 412 entry = usb_alloc_urb(0, GFP_KERNEL);
413 if (!entry) {
c1db52b9
LF		 414 ret = -ENOMEM;
415 goto err;
605bebe2
MW		 416 }
417 usb_fill_bulk_urb(entry, priv->udev,
6f7853f3
HTL		 418 usb_rcvbulkpipe(priv->udev,
419 priv->is_rtl8187b ? 3 : 1),
605bebe2
MW		 420 skb_tail_pointer(skb),
421 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
422 info = (struct rtl8187_rx_info *)skb->cb;
423 info->urb = entry;
424 info->dev = dev;
425 skb_queue_tail(&priv->rx_queue, skb);
c1db52b9
LF		 426 usb_anchor_urb(entry, &priv->anchored);
427 ret = usb_submit_urb(entry, GFP_KERNEL);
428 if (ret) {
429 skb_unlink(skb, &priv->rx_queue);
430 usb_unanchor_urb(entry);
431 goto err;
432 }
433 usb_free_urb(entry);
605bebe2 434 }
c1db52b9 435 return ret;
605bebe2 436
c1db52b9
LF		 437err:
438 usb_free_urb(entry);
439 kfree_skb(skb);
440 usb_kill_anchored_urbs(&priv->anchored);
441 return ret;
605bebe2
MW		 442}
443
3517afde
HRK		 444static void rtl8187b_status_cb(struct urb *urb)
445{
446 struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
447 struct rtl8187_priv *priv = hw->priv;
448 u64 val;
449 unsigned int cmd_type;
450
c1db52b9 451 if (unlikely(urb->status))
3517afde 452 return;
3517afde
HRK		 453
454 /*
455 * Read from status buffer:
456 *
457 * bits [30:31] = cmd type:
458 * - 0 indicates tx beacon interrupt
459 * - 1 indicates tx close descriptor
460 *
461 * In the case of tx beacon interrupt:
462 * [0:9] = Last Beacon CW
463 * [10:29] = reserved
464 * [30:31] = 00b
465 * [32:63] = Last Beacon TSF
466 *
467 * If it's tx close descriptor:
468 * [0:7] = Packet Retry Count
469 * [8:14] = RTS Retry Count
470 * [15] = TOK
471 * [16:27] = Sequence No
472 * [28] = LS
473 * [29] = FS
474 * [30:31] = 01b
475 * [32:47] = unused (reserved?)
476 * [48:63] = MAC Used Time
477 */
478 val = le64_to_cpu(priv->b_tx_status.buf);
479
480 cmd_type = (val >> 30) & 0x3;
481 if (cmd_type == 1) {
482 unsigned int pkt_rc, seq_no;
483 bool tok;
484 struct sk_buff *skb;
485 struct ieee80211_hdr *ieee80211hdr;
486 unsigned long flags;
487
488 pkt_rc = val & 0xFF;
489 tok = val & (1 << 15);
490 seq_no = (val >> 16) & 0xFFF;
491
492 spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
493 skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
494 ieee80211hdr = (struct ieee80211_hdr *)skb->data;
495
496 /*
497 * While testing, it was discovered that the seq_no
498 * doesn't actually contains the sequence number.
499 * Instead of returning just the 12 bits of sequence
500 * number, hardware is returning entire sequence control
501 * (fragment number plus sequence number) in a 12 bit
502 * only field overflowing after some time. As a
503 * workaround, just consider the lower bits, and expect
504 * it's unlikely we wrongly ack some sent data
505 */
506 if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
507 & 0xFFF) == seq_no)
508 break;
509 }
510 if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
511 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
512
513 __skb_unlink(skb, &priv->b_tx_status.queue);
514 if (tok)
515 info->flags |= IEEE80211_TX_STAT_ACK;
1548c86a 516 info->status.rates[0].count = pkt_rc + 1;
3517afde
HRK		 517
518 ieee80211_tx_status_irqsafe(hw, skb);
519 }
520 spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
521 }
522
c1db52b9
LF		 523 usb_anchor_urb(urb, &priv->anchored);
524 if (usb_submit_urb(urb, GFP_ATOMIC))
525 usb_unanchor_urb(urb);
3517afde
HRK		 526}
527
528static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
529{
530 struct rtl8187_priv *priv = dev->priv;
531 struct urb *entry;
c1db52b9 532 int ret = 0;
3517afde
HRK		 533
534 entry = usb_alloc_urb(0, GFP_KERNEL);
535 if (!entry)
536 return -ENOMEM;
3517afde
HRK		 537
538 usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
539 &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
540 rtl8187b_status_cb, dev);
541
c1db52b9
LF		 542 usb_anchor_urb(entry, &priv->anchored);
543 ret = usb_submit_urb(entry, GFP_KERNEL);
544 if (ret)
545 usb_unanchor_urb(entry);
546 usb_free_urb(entry);
3517afde 547
c1db52b9 548 return ret;
3517afde
HRK		 549}
550
f8a08c34 551static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
605bebe2
MW		 552{
553 struct rtl8187_priv *priv = dev->priv;
554 u8 reg;
555 int i;
556
605bebe2
MW		 557 reg = rtl818x_ioread8(priv, &priv->map->CMD);
558 reg &= (1 << 1);
559 reg |= RTL818X_CMD_RESET;
560 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
561
562 i = 10;
563 do {
564 msleep(2);
565 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
566 RTL818X_CMD_RESET))
567 break;
568 } while (--i);
569
570 if (!i) {
571 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
572 return -ETIMEDOUT;
573 }
574
575 /* reload registers from eeprom */
576 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
577
578 i = 10;
579 do {
580 msleep(4);
581 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
582 RTL818X_EEPROM_CMD_CONFIG))
583 break;
584 } while (--i);
585
586 if (!i) {
587 printk(KERN_ERR "%s: eeprom reset timeout!\n",
588 wiphy_name(dev->wiphy));
589 return -ETIMEDOUT;
590 }
591
f8a08c34
HTL		 592 return 0;
593}
594
595static int rtl8187_init_hw(struct ieee80211_hw *dev)
596{
597 struct rtl8187_priv *priv = dev->priv;
598 u8 reg;
599 int res;
600
601 /* reset */
602 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
603 RTL818X_EEPROM_CMD_CONFIG);
604 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
605 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
606 RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 607 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
608 RTL8187_RTL8225_ANAPARAM_ON);
609 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
610 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 611 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
612 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
613 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
614 RTL818X_EEPROM_CMD_NORMAL);
615
616 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
617
618 msleep(200);
619 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
620 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
621 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
622 msleep(200);
623
624 res = rtl8187_cmd_reset(dev);
625 if (res)
626 return res;
627
605bebe2
MW		 628 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
629 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
f8a08c34
HTL		 630 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
631 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 632 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
633 RTL8187_RTL8225_ANAPARAM_ON);
634 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
635 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 636 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
637 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
605bebe2
MW		 638 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
639
640 /* setup card */
641 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
642 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
643
644 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
645 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
646 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
647
648 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
605bebe2
MW		 649
650 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
651 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
652 reg &= 0x3F;
653 reg |= 0x80;
654 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
655
656 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
657
658 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
659 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
660 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
661
662 // TODO: set RESP_RATE and BRSR properly
663 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
664 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
665
666 /* host_usb_init */
667 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
668 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
669 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
670 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
671 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
672 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
673 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
674 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
675 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
676 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
677 msleep(100);
678
679 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
680 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
681 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
f8a08c34
HTL		 682 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
683 RTL818X_EEPROM_CMD_CONFIG);
605bebe2 684 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
f8a08c34
HTL		 685 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
686 RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 687 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
688 msleep(100);
689
f6532111 690 priv->rf->init(dev);
605bebe2
MW		 691
692 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
f6532111
MW		 693 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
694 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 695 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
696 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
697 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
f6532111 698 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 699
700 return 0;
701}
702
f8a08c34
HTL		 703static const u8 rtl8187b_reg_table[][3] = {
704 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
705 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
706 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
707 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
708
709 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
710 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
711 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
712 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
713 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
714 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
715
716 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
717 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
718 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
719 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
720 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
721 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
722 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
723 {0x73, 0x9A, 2},
724
725 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
726 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
727 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
728 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
729 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0},
730
731 {0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0},
732 {0x8E, 0x08, 0}, {0x8F, 0x00, 0}
733};
734
735static int rtl8187b_init_hw(struct ieee80211_hw *dev)
736{
737 struct rtl8187_priv *priv = dev->priv;
738 int res, i;
739 u8 reg;
740
741 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
742 RTL818X_EEPROM_CMD_CONFIG);
743
744 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
745 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
746 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
4ece16a1
HRK		 747 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
748 RTL8187B_RTL8225_ANAPARAM2_ON);
749 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
750 RTL8187B_RTL8225_ANAPARAM_ON);
751 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
752 RTL8187B_RTL8225_ANAPARAM3_ON);
f8a08c34
HTL		 753
754 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
755 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
756 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
757 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
758
759 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
760 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
761 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
762
763 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
764 RTL818X_EEPROM_CMD_NORMAL);
765
766 res = rtl8187_cmd_reset(dev);
767 if (res)
768 return res;
769
770 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
771 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
772 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
773 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
774 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
775 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
776 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
777 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
778
779 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
780 reg = rtl818x_ioread8(priv, &priv->map->RATE_FALLBACK);
781 reg |= RTL818X_RATE_FALLBACK_ENABLE;
782 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, reg);
783
784 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
785 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
786 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
787
788 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
789 RTL818X_EEPROM_CMD_CONFIG);
790 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
791 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
792 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
793 RTL818X_EEPROM_CMD_NORMAL);
794
795 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
796 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
797 rtl818x_iowrite8_idx(priv,
798 (u8 *)(uintptr_t)
799 (rtl8187b_reg_table[i][0] | 0xFF00),
800 rtl8187b_reg_table[i][1],
801 rtl8187b_reg_table[i][2]);
802 }
803
804 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
805 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
806
807 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
808 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
809 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
810
811 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
812
813 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
814
815 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
816 RTL818X_EEPROM_CMD_CONFIG);
817 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
818 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
819 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
820 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
821 RTL818X_EEPROM_CMD_NORMAL);
822
823 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
824 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
825 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
2f20596b 826 msleep(100);
f8a08c34
HTL		 827
828 priv->rf->init(dev);
829
830 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
831 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
832 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
833
834 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
835 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
836 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
837 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
838 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
839 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
840 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
841
842 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
843 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
844 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
845 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
846 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
847 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
848 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
849 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
850 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
851 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
852 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
853 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
854 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
855
856 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
857
858 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
859
b4572a92
HRK		 860 priv->slot_time = 0x9;
861 priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
862 priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
863 priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
864 priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
865 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
866
f8a08c34
HTL		 867 return 0;
868}
869
4150c572 870static int rtl8187_start(struct ieee80211_hw *dev)
605bebe2
MW		 871{
872 struct rtl8187_priv *priv = dev->priv;
873 u32 reg;
874 int ret;
875
f8a08c34
HTL		 876 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
877 rtl8187b_init_hw(dev);
605bebe2
MW		 878 if (ret)
879 return ret;
880
7dcdd073 881 mutex_lock(&priv->conf_mutex);
c1db52b9
LF		 882
883 init_usb_anchor(&priv->anchored);
884
f8a08c34
HTL		 885 if (priv->is_rtl8187b) {
886 reg = RTL818X_RX_CONF_MGMT |
887 RTL818X_RX_CONF_DATA |
888 RTL818X_RX_CONF_BROADCAST |
889 RTL818X_RX_CONF_NICMAC |
890 RTL818X_RX_CONF_BSSID |
891 (7 << 13 /* RX FIFO threshold NONE */) |
892 (7 << 10 /* MAX RX DMA */) |
893 RTL818X_RX_CONF_RX_AUTORESETPHY |
894 RTL818X_RX_CONF_ONLYERLPKT |
895 RTL818X_RX_CONF_MULTICAST;
896 priv->rx_conf = reg;
897 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
898
899 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
900 RTL818X_TX_CONF_HW_SEQNUM |
901 RTL818X_TX_CONF_DISREQQSIZE |
902 (7 << 8 /* short retry limit */) |
903 (7 << 0 /* long retry limit */) |
904 (7 << 21 /* MAX TX DMA */));
905 rtl8187_init_urbs(dev);
3517afde 906 rtl8187b_init_status_urb(dev);
7dcdd073 907 mutex_unlock(&priv->conf_mutex);
f8a08c34
HTL		 908 return 0;
909 }
910
605bebe2
MW		 911 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
912
2fe14263
MW		 913 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
914 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
915
605bebe2
MW		 916 rtl8187_init_urbs(dev);
917
918 reg = RTL818X_RX_CONF_ONLYERLPKT |
919 RTL818X_RX_CONF_RX_AUTORESETPHY |
920 RTL818X_RX_CONF_BSSID |
921 RTL818X_RX_CONF_MGMT |
605bebe2
MW		 922 RTL818X_RX_CONF_DATA |
923 (7 << 13 /* RX FIFO threshold NONE */) |
924 (7 << 10 /* MAX RX DMA */) |
925 RTL818X_RX_CONF_BROADCAST |
605bebe2 926 RTL818X_RX_CONF_NICMAC;
605bebe2 927
4150c572 928 priv->rx_conf = reg;
605bebe2
MW		 929 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
930
931 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
932 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
933 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
934 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
935
936 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
937 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
938 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
939 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
940 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
941
942 reg = RTL818X_TX_CONF_CW_MIN |
943 (7 << 21 /* MAX TX DMA */) |
944 RTL818X_TX_CONF_NO_ICV;
945 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
946
947 reg = rtl818x_ioread8(priv, &priv->map->CMD);
948 reg |= RTL818X_CMD_TX_ENABLE;
949 reg |= RTL818X_CMD_RX_ENABLE;
950 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
7dcdd073 951 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 952
953 return 0;
954}
955
4150c572 956static void rtl8187_stop(struct ieee80211_hw *dev)
605bebe2
MW		 957{
958 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 959 struct sk_buff *skb;
960 u32 reg;
961
7dcdd073 962 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 963 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
964
965 reg = rtl818x_ioread8(priv, &priv->map->CMD);
966 reg &= ~RTL818X_CMD_TX_ENABLE;
967 reg &= ~RTL818X_CMD_RX_ENABLE;
968 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
969
f6532111 970 priv->rf->stop(dev);
605bebe2
MW		 971
972 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
973 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
974 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
975 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
976
3517afde
HRK		 977 while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
978 dev_kfree_skb_any(skb);
c1db52b9
LF		 979
980 usb_kill_anchored_urbs(&priv->anchored);
7dcdd073 981 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 982}
983
984static int rtl8187_add_interface(struct ieee80211_hw *dev,
985 struct ieee80211_if_init_conf *conf)
986{
987 struct rtl8187_priv *priv = dev->priv;
4150c572 988 int i;
605bebe2 989
05c914fe 990 if (priv->mode != NL80211_IFTYPE_MONITOR)
4150c572 991 return -EOPNOTSUPP;
605bebe2
MW		 992
993 switch (conf->type) {
05c914fe 994 case NL80211_IFTYPE_STATION:
605bebe2
MW		 995 priv->mode = conf->type;
996 break;
997 default:
998 return -EOPNOTSUPP;
999 }
1000
7dcdd073 1001 mutex_lock(&priv->conf_mutex);
aa979a6a
HRK		 1002 priv->vif = conf->vif;
1003
4150c572
JB		 1004 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1005 for (i = 0; i < ETH_ALEN; i++)
1006 rtl818x_iowrite8(priv, &priv->map->MAC[i],
1007 ((u8 *)conf->mac_addr)[i]);
1008 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
605bebe2 1009
7dcdd073 1010 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1011 return 0;
1012}
1013
1014static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1015 struct ieee80211_if_init_conf *conf)
1016{
1017 struct rtl8187_priv *priv = dev->priv;
7dcdd073 1018 mutex_lock(&priv->conf_mutex);
05c914fe 1019 priv->mode = NL80211_IFTYPE_MONITOR;
aa979a6a 1020 priv->vif = NULL;
7dcdd073 1021 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1022}
1023
e8975581 1024static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
605bebe2
MW		 1025{
1026 struct rtl8187_priv *priv = dev->priv;
e8975581 1027 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 1028 u32 reg;
1029
7dcdd073 1030 mutex_lock(&priv->conf_mutex);
f6532111
MW		 1031 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1032 /* Enable TX loopback on MAC level to avoid TX during channel
1033 * changes, as this has be seen to causes problems and the
1034 * card will stop work until next reset
1035 */
1036 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1037 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
f6532111
MW		 1038 priv->rf->set_chan(dev, conf);
1039 msleep(10);
1040 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
605bebe2 1041
605bebe2
MW		 1042 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1043 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1044 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1045 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
7dcdd073 1046 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1047 return 0;
1048}
1049
32bfd35d
JB		 1050static int rtl8187_config_interface(struct ieee80211_hw *dev,
1051 struct ieee80211_vif *vif,
605bebe2
MW		 1052 struct ieee80211_if_conf *conf)
1053{
1054 struct rtl8187_priv *priv = dev->priv;
1055 int i;
6f7853f3 1056 u8 reg;
605bebe2 1057
7dcdd073 1058 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 1059 for (i = 0; i < ETH_ALEN; i++)
1060 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
1061
6f7853f3
HTL		 1062 if (is_valid_ether_addr(conf->bssid)) {
1063 reg = RTL818X_MSR_INFRA;
1064 if (priv->is_rtl8187b)
1065 reg |= RTL818X_MSR_ENEDCA;
1066 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1067 } else {
1068 reg = RTL818X_MSR_NO_LINK;
1069 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1070 }
605bebe2 1071
7dcdd073 1072 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1073 return 0;
1074}
1075
b4572a92
HRK		 1076/*
1077 * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1078 * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1079 */
1080static __le32 *rtl8187b_ac_addr[4] = {
1081 (__le32 *) 0xFFF0, /* AC_VO */
1082 (__le32 *) 0xFFF4, /* AC_VI */
1083 (__le32 *) 0xFFFC, /* AC_BK */
1084 (__le32 *) 0xFFF8, /* AC_BE */
1085};
1086
1087#define SIFS_TIME 0xa
1088
f8288317
HRK		 1089static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1090 bool use_short_preamble)
64761077 1091{
f8288317 1092 if (priv->is_rtl8187b) {
b4572a92 1093 u8 difs, eifs;
f8288317 1094 u16 ack_timeout;
b4572a92 1095 int queue;
f8288317
HRK		 1096
1097 if (use_short_slot) {
b4572a92 1098 priv->slot_time = 0x9;
f8288317
HRK		 1099 difs = 0x1c;
1100 eifs = 0x53;
1101 } else {
b4572a92 1102 priv->slot_time = 0x14;
f8288317
HRK		 1103 difs = 0x32;
1104 eifs = 0x5b;
1105 }
54ac218a 1106 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
b4572a92 1107 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
f8288317
HRK		 1108 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1109
1110 /*
1111 * BRSR+1 on 8187B is in fact EIFS register
1112 * Value in units of 4 us
1113 */
1114 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1115
1116 /*
1117 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1118 * register. In units of 4 us like eifs register
1119 * ack_timeout = ack duration + plcp + difs + preamble
1120 */
1121 ack_timeout = 112 + 48 + difs;
1122 if (use_short_preamble)
1123 ack_timeout += 72;
1124 else
1125 ack_timeout += 144;
1126 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1127 DIV_ROUND_UP(ack_timeout, 4));
b4572a92
HRK		 1128
1129 for (queue = 0; queue < 4; queue++)
1130 rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1131 priv->aifsn[queue] * priv->slot_time +
1132 SIFS_TIME);
f8288317 1133 } else {
64761077
HRK		 1134 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1135 if (use_short_slot) {
1136 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1137 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1138 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
64761077
HRK		 1139 } else {
1140 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1141 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1142 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
64761077
HRK		 1143 }
1144 }
1145}
1146
1147static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1148 struct ieee80211_vif *vif,
1149 struct ieee80211_bss_conf *info,
1150 u32 changed)
1151{
1152 struct rtl8187_priv *priv = dev->priv;
1153
f8288317
HRK		 1154 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1155 rtl8187_conf_erp(priv, info->use_short_slot,
1156 info->use_short_preamble);
64761077
HRK		 1157}
1158
4150c572
JB		 1159static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1160 unsigned int changed_flags,
1161 unsigned int *total_flags,
2fe14263 1162 int mc_count, struct dev_addr_list *mclist)
4150c572
JB		 1163{
1164 struct rtl8187_priv *priv = dev->priv;
1165
4150c572
JB		 1166 if (changed_flags & FIF_FCSFAIL)
1167 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1168 if (changed_flags & FIF_CONTROL)
1169 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1170 if (changed_flags & FIF_OTHER_BSS)
1171 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
2fe14263 1172 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
4150c572 1173 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
2fe14263
MW		 1174 else
1175 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1176
1177 *total_flags = 0;
4150c572 1178
4150c572
JB		 1179 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1180 *total_flags |= FIF_FCSFAIL;
1181 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1182 *total_flags |= FIF_CONTROL;
1183 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1184 *total_flags |= FIF_OTHER_BSS;
2fe14263
MW		 1185 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1186 *total_flags |= FIF_ALLMULTI;
4150c572
JB		 1187
1188 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1189}
1190
b4572a92
HRK		 1191static int rtl8187_conf_tx(struct ieee80211_hw *dev, u16 queue,
1192 const struct ieee80211_tx_queue_params *params)
1193{
1194 struct rtl8187_priv *priv = dev->priv;
1195 u8 cw_min, cw_max;
1196
1197 if (queue > 3)
1198 return -EINVAL;
1199
1200 cw_min = fls(params->cw_min);
1201 cw_max = fls(params->cw_max);
1202
1203 if (priv->is_rtl8187b) {
1204 priv->aifsn[queue] = params->aifs;
1205
1206 /*
1207 * This is the structure of AC_*_PARAM registers in 8187B:
1208 * - TXOP limit field, bit offset = 16
1209 * - ECWmax, bit offset = 12
1210 * - ECWmin, bit offset = 8
1211 * - AIFS, bit offset = 0
1212 */
1213 rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1214 (params->txop << 16) | (cw_max << 12) |
1215 (cw_min << 8) | (params->aifs *
1216 priv->slot_time + SIFS_TIME));
1217 } else {
1218 if (queue != 0)
1219 return -EINVAL;
1220
1221 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1222 cw_min | (cw_max << 4));
1223 }
1224 return 0;
1225}
1226
605bebe2
MW		 1227static const struct ieee80211_ops rtl8187_ops = {
1228 .tx = rtl8187_tx,
4150c572 1229 .start = rtl8187_start,
605bebe2
MW		 1230 .stop = rtl8187_stop,
1231 .add_interface = rtl8187_add_interface,
1232 .remove_interface = rtl8187_remove_interface,
1233 .config = rtl8187_config,
1234 .config_interface = rtl8187_config_interface,
64761077 1235 .bss_info_changed = rtl8187_bss_info_changed,
4150c572 1236 .configure_filter = rtl8187_configure_filter,
b4572a92 1237 .conf_tx = rtl8187_conf_tx
605bebe2
MW		 1238};
1239
1240static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1241{
1242 struct ieee80211_hw *dev = eeprom->data;
1243 struct rtl8187_priv *priv = dev->priv;
1244 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1245
1246 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1247 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1248 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1249 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1250}
1251
1252static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1253{
1254 struct ieee80211_hw *dev = eeprom->data;
1255 struct rtl8187_priv *priv = dev->priv;
1256 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1257
1258 if (eeprom->reg_data_in)
1259 reg |= RTL818X_EEPROM_CMD_WRITE;
1260 if (eeprom->reg_data_out)
1261 reg |= RTL818X_EEPROM_CMD_READ;
1262 if (eeprom->reg_data_clock)
1263 reg |= RTL818X_EEPROM_CMD_CK;
1264 if (eeprom->reg_chip_select)
1265 reg |= RTL818X_EEPROM_CMD_CS;
1266
1267 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1268 udelay(10);
1269}
1270
1271static int __devinit rtl8187_probe(struct usb_interface *intf,
1272 const struct usb_device_id *id)
1273{
1274 struct usb_device *udev = interface_to_usbdev(intf);
1275 struct ieee80211_hw *dev;
1276 struct rtl8187_priv *priv;
1277 struct eeprom_93cx6 eeprom;
1278 struct ieee80211_channel *channel;
6f7853f3 1279 const char *chip_name;
605bebe2
MW		 1280 u16 txpwr, reg;
1281 int err, i;
1282
1283 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1284 if (!dev) {
1285 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1286 return -ENOMEM;
1287 }
1288
1289 priv = dev->priv;
0e25b4ef 1290 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
605bebe2
MW		 1291
1292 SET_IEEE80211_DEV(dev, &intf->dev);
1293 usb_set_intfdata(intf, dev);
1294 priv->udev = udev;
1295
1296 usb_get_dev(udev);
1297
1298 skb_queue_head_init(&priv->rx_queue);
8318d78a
JB		 1299
1300 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1301 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1302
605bebe2
MW		 1303 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1304 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1305 priv->map = (struct rtl818x_csr *)0xFF00;
8318d78a
JB		 1306
1307 priv->band.band = IEEE80211_BAND_2GHZ;
1308 priv->band.channels = priv->channels;
1309 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1310 priv->band.bitrates = priv->rates;
1311 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1312 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1313
1314
05c914fe 1315 priv->mode = NL80211_IFTYPE_MONITOR;
605bebe2 1316 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
a7db74f4 1317 IEEE80211_HW_SIGNAL_DBM |
0ccd58fc 1318 IEEE80211_HW_RX_INCLUDES_FCS;
605bebe2 1319
605bebe2
MW		 1320 eeprom.data = dev;
1321 eeprom.register_read = rtl8187_eeprom_register_read;
1322 eeprom.register_write = rtl8187_eeprom_register_write;
1323 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1324 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1325 else
1326 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1327
1328 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1329 udelay(10);
1330
1331 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1332 (__le16 __force *)dev->wiphy->perm_addr, 3);
1333 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
1334 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1335 "generated MAC address\n");
1336 random_ether_addr(dev->wiphy->perm_addr);
1337 }
1338
1339 channel = priv->channels;
1340 for (i = 0; i < 3; i++) {
1341 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1342 &txpwr);
8318d78a
JB		 1343 (*channel++).hw_value = txpwr & 0xFF;
1344 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 1345 }
1346 for (i = 0; i < 2; i++) {
1347 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1348 &txpwr);
8318d78a
JB		 1349 (*channel++).hw_value = txpwr & 0xFF;
1350 (*channel++).hw_value = txpwr >> 8;
605bebe2 1351 }
605bebe2
MW		 1352
1353 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1354 &priv->txpwr_base);
1355
f6532111
MW		 1356 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1357 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 1358 /* 0 means asic B-cut, we should use SW 3 wire
1359 * bit-by-bit banging for radio. 1 means we can use
1360 * USB specific request to write radio registers */
1361 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
f6532111 1362 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 1363 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1364
6f7853f3
HTL		 1365 if (!priv->is_rtl8187b) {
1366 u32 reg32;
1367 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1368 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1369 switch (reg32) {
0e25b4ef
LF		 1370 case RTL818X_TX_CONF_R8187vD_B:
1371 /* Some RTL8187B devices have a USB ID of 0x8187
1372 * detect them here */
1373 chip_name = "RTL8187BvB(early)";
1374 priv->is_rtl8187b = 1;
1375 priv->hw_rev = RTL8187BvB;
1376 break;
1377 case RTL818X_TX_CONF_R8187vD:
6f7853f3
HTL		 1378 chip_name = "RTL8187vD";
1379 break;
1380 default:
1381 chip_name = "RTL8187vB (default)";
1382 }
1383 } else {
6f7853f3
HTL		 1384 /*
1385 * Force USB request to write radio registers for 8187B, Realtek
1386 * only uses it in their sources
1387 */
1388 /*if (priv->asic_rev == 0) {
1389 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1390 "requests to write to radio registers\n");
1391 priv->asic_rev = 1;
1392 }*/
1393 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1394 case RTL818X_R8187B_B:
1395 chip_name = "RTL8187BvB";
1396 priv->hw_rev = RTL8187BvB;
1397 break;
1398 case RTL818X_R8187B_D:
1399 chip_name = "RTL8187BvD";
1400 priv->hw_rev = RTL8187BvD;
1401 break;
1402 case RTL818X_R8187B_E:
1403 chip_name = "RTL8187BvE";
1404 priv->hw_rev = RTL8187BvE;
1405 break;
1406 default:
1407 chip_name = "RTL8187BvB (default)";
1408 priv->hw_rev = RTL8187BvB;
1409 }
1410 }
1411
0e25b4ef
LF		 1412 if (!priv->is_rtl8187b) {
1413 for (i = 0; i < 2; i++) {
1414 eeprom_93cx6_read(&eeprom,
1415 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1416 &txpwr);
1417 (*channel++).hw_value = txpwr & 0xFF;
1418 (*channel++).hw_value = txpwr >> 8;
1419 }
1420 } else {
1421 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1422 &txpwr);
1423 (*channel++).hw_value = txpwr & 0xFF;
1424
1425 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1426 (*channel++).hw_value = txpwr & 0xFF;
1427
1428 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1429 (*channel++).hw_value = txpwr & 0xFF;
1430 (*channel++).hw_value = txpwr >> 8;
1431 }
1432
a7db74f4 1433 if (priv->is_rtl8187b)
c8f96974 1434 printk(KERN_WARNING "rtl8187: 8187B chip detected.\n");
0ccd58fc 1435
94778280
JB		 1436 /*
1437 * XXX: Once this driver supports anything that requires
1438 * beacons it must implement IEEE80211_TX_CTL_ASSIGN_SEQ.
1439 */
f59ac048
LR		 1440 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1441
0e25b4ef
LF		 1442 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1443 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1444 " info!\n");
1445
f6532111 1446 priv->rf = rtl8187_detect_rf(dev);
0e25b4ef
LF		 1447 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1448 sizeof(struct rtl8187_tx_hdr) :
1449 sizeof(struct rtl8187b_tx_hdr);
1450 if (!priv->is_rtl8187b)
1451 dev->queues = 1;
1452 else
1453 dev->queues = 4;
605bebe2
MW		 1454
1455 err = ieee80211_register_hw(dev);
1456 if (err) {
1457 printk(KERN_ERR "rtl8187: Cannot register device\n");
1458 goto err_free_dev;
1459 }
7dcdd073 1460 mutex_init(&priv->conf_mutex);
3517afde 1461 skb_queue_head_init(&priv->b_tx_status.queue);
605bebe2 1462
e174961c
JB		 1463 printk(KERN_INFO "%s: hwaddr %pM, %s V%d + %s\n",
1464 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
6f7853f3 1465 chip_name, priv->asic_rev, priv->rf->name);
605bebe2
MW		 1466
1467 return 0;
1468
1469 err_free_dev:
1470 ieee80211_free_hw(dev);
1471 usb_set_intfdata(intf, NULL);
1472 usb_put_dev(udev);
1473 return err;
1474}
1475
1476static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1477{
1478 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1479 struct rtl8187_priv *priv;
1480
1481 if (!dev)
1482 return;
1483
1484 ieee80211_unregister_hw(dev);
1485
1486 priv = dev->priv;
d6e2be98 1487 usb_reset_device(priv->udev);
605bebe2
MW		 1488 usb_put_dev(interface_to_usbdev(intf));
1489 ieee80211_free_hw(dev);
1490}
1491
1492static struct usb_driver rtl8187_driver = {
1493 .name = KBUILD_MODNAME,
1494 .id_table = rtl8187_table,
1495 .probe = rtl8187_probe,
500c1197 1496 .disconnect = __devexit_p(rtl8187_disconnect),
605bebe2
MW		 1497};
1498
1499static int __init rtl8187_init(void)
1500{
1501 return usb_register(&rtl8187_driver);
1502}
1503
1504static void __exit rtl8187_exit(void)
1505{
1506 usb_deregister(&rtl8187_driver);
1507}
1508
1509module_init(rtl8187_init);
1510module_exit(rtl8187_exit);
Linux 6.x block layer and io_uring tree(s)