rt2x00: Properly clean up beacon skbs.
[linux-2.6-block.git] / drivers / net / wireless / rt2x00 / rt2x00pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00pci
23 Abstract: rt2x00 generic pci device routines.
24 */
25
95ea3627
ID
26#include <linux/dma-mapping.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30
31#include "rt2x00.h"
32#include "rt2x00pci.h"
33
95ea3627
ID
34/*
35 * TX data handlers.
36 */
6db3786a 37int rt2x00pci_write_tx_data(struct queue_entry *entry)
95ea3627 38{
b8be63ff 39 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
181d6902 40 struct skb_frame_desc *skbdesc;
95ea3627
ID
41 u32 word;
42
b8be63ff 43 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 44
6db3786a
ID
45 /*
46 * This should not happen, we already checked the entry
47 * was ours. When the hardware disagrees there has been
48 * a queue corruption!
49 */
50 if (unlikely(rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) ||
51 rt2x00_get_field32(word, TXD_ENTRY_VALID))) {
52 ERROR(entry->queue->rt2x00dev,
53 "Corrupt queue %d, accessing entry which is not ours.\n"
95ea3627 54 "Please file bug report to %s.\n",
e58c6aca 55 entry->queue->qid, DRV_PROJECT);
95ea3627
ID
56 return -EINVAL;
57 }
58
08992f7f
ID
59 /*
60 * Fill in skb descriptor
61 */
6db3786a 62 skbdesc = get_skb_frame_desc(entry->skb);
e039fa4a 63 memset(skbdesc, 0, sizeof(*skbdesc));
b8be63ff 64 skbdesc->desc = entry_priv->desc;
6db3786a 65 skbdesc->desc_len = entry->queue->desc_size;
181d6902
ID
66 skbdesc->entry = entry;
67
6db3786a 68 memcpy(entry_priv->data, entry->skb->data, entry->skb->len);
95ea3627 69
95ea3627
ID
70 return 0;
71}
72EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data);
73
74/*
3957ccb5 75 * TX/RX data handlers.
95ea3627
ID
76 */
77void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
78{
181d6902
ID
79 struct data_queue *queue = rt2x00dev->rx;
80 struct queue_entry *entry;
b8be63ff 81 struct queue_entry_priv_pci *entry_priv;
181d6902
ID
82 struct skb_frame_desc *skbdesc;
83 struct rxdone_entry_desc rxdesc;
4150c572 84 u32 word;
95ea3627
ID
85
86 while (1) {
181d6902 87 entry = rt2x00queue_get_entry(queue, Q_INDEX);
b8be63ff
ID
88 entry_priv = entry->priv_data;
89 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 90
4150c572 91 if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC))
95ea3627
ID
92 break;
93
181d6902
ID
94 memset(&rxdesc, 0, sizeof(rxdesc));
95 rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
95ea3627
ID
96
97 /*
239c249d 98 * Allocate the sk_buffer and copy all data into it.
95ea3627 99 */
239c249d 100 entry->skb = rt2x00queue_alloc_rxskb(queue);
181d6902 101 if (!entry->skb)
95ea3627
ID
102 return;
103
239c249d
GW
104 memcpy(entry->skb->data, entry_priv->data, rxdesc.size);
105 skb_trim(entry->skb, rxdesc.size);
95ea3627 106
08992f7f
ID
107 /*
108 * Fill in skb descriptor
109 */
181d6902
ID
110 skbdesc = get_skb_frame_desc(entry->skb);
111 memset(skbdesc, 0, sizeof(*skbdesc));
b8be63ff 112 skbdesc->desc = entry_priv->desc;
181d6902 113 skbdesc->desc_len = queue->desc_size;
08992f7f
ID
114 skbdesc->entry = entry;
115
95ea3627
ID
116 /*
117 * Send the frame to rt2x00lib for further processing.
118 */
181d6902 119 rt2x00lib_rxdone(entry, &rxdesc);
95ea3627 120
181d6902 121 if (test_bit(DEVICE_ENABLED_RADIO, &queue->rt2x00dev->flags)) {
4150c572 122 rt2x00_set_field32(&word, RXD_ENTRY_OWNER_NIC, 1);
b8be63ff 123 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID
124 }
125
181d6902 126 rt2x00queue_index_inc(queue, Q_INDEX);
95ea3627
ID
127 }
128}
129EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
130
181d6902
ID
131void rt2x00pci_txdone(struct rt2x00_dev *rt2x00dev, struct queue_entry *entry,
132 struct txdone_entry_desc *txdesc)
3957ccb5 133{
b8be63ff 134 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
e039fa4a 135 enum data_queue_qid qid = skb_get_queue_mapping(entry->skb);
3957ccb5
ID
136 u32 word;
137
181d6902 138 rt2x00lib_txdone(entry, txdesc);
3957ccb5
ID
139
140 /*
141 * Make this entry available for reuse.
142 */
143 entry->flags = 0;
144
b8be63ff 145 rt2x00_desc_read(entry_priv->desc, 0, &word);
3957ccb5
ID
146 rt2x00_set_field32(&word, TXD_ENTRY_OWNER_NIC, 0);
147 rt2x00_set_field32(&word, TXD_ENTRY_VALID, 0);
b8be63ff 148 rt2x00_desc_write(entry_priv->desc, 0, word);
3957ccb5 149
6db3786a 150 __clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
181d6902 151 rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
3957ccb5
ID
152
153 /*
b869767b
ID
154 * If the data queue was below the threshold before the txdone
155 * handler we must make sure the packet queue in the mac80211 stack
3957ccb5
ID
156 * is reenabled when the txdone handler has finished.
157 */
b869767b 158 if (!rt2x00queue_threshold(entry->queue))
e039fa4a 159 ieee80211_wake_queue(rt2x00dev->hw, qid);
3957ccb5
ID
160
161}
162EXPORT_SYMBOL_GPL(rt2x00pci_txdone);
163
95ea3627
ID
164/*
165 * Device initialization handlers.
166 */
9c9dd2c9
ID
167#define desc_size(__queue) \
168({ \
169 ((__queue)->limit * (__queue)->desc_size);\
95ea3627
ID
170})
171
9c9dd2c9
ID
172#define data_size(__queue) \
173({ \
174 ((__queue)->limit * (__queue)->data_size);\
95ea3627
ID
175})
176
9c9dd2c9
ID
177#define dma_size(__queue) \
178({ \
179 data_size(__queue) + desc_size(__queue);\
95ea3627
ID
180})
181
9c9dd2c9
ID
182#define desc_offset(__queue, __base, __i) \
183({ \
184 (__base) + data_size(__queue) + \
185 ((__i) * (__queue)->desc_size); \
186})
187
188#define data_offset(__queue, __base, __i) \
189({ \
190 (__base) + \
191 ((__i) * (__queue)->data_size); \
181d6902
ID
192})
193
194static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
195 struct data_queue *queue)
95ea3627 196{
181d6902 197 struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
b8be63ff 198 struct queue_entry_priv_pci *entry_priv;
30b3a23c
ID
199 void *addr;
200 dma_addr_t dma;
95ea3627
ID
201 unsigned int i;
202
203 /*
204 * Allocate DMA memory for descriptor and buffer.
205 */
30b3a23c
ID
206 addr = pci_alloc_consistent(pci_dev, dma_size(queue), &dma);
207 if (!addr)
95ea3627
ID
208 return -ENOMEM;
209
30b3a23c 210 memset(addr, 0, dma_size(queue));
9c9dd2c9 211
95ea3627 212 /*
181d6902 213 * Initialize all queue entries to contain valid addresses.
95ea3627 214 */
181d6902 215 for (i = 0; i < queue->limit; i++) {
b8be63ff
ID
216 entry_priv = queue->entries[i].priv_data;
217 entry_priv->desc = desc_offset(queue, addr, i);
218 entry_priv->desc_dma = desc_offset(queue, dma, i);
219 entry_priv->data = data_offset(queue, addr, i);
220 entry_priv->data_dma = data_offset(queue, dma, i);
95ea3627
ID
221 }
222
223 return 0;
224}
225
181d6902
ID
226static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
227 struct data_queue *queue)
95ea3627 228{
181d6902 229 struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
b8be63ff
ID
230 struct queue_entry_priv_pci *entry_priv =
231 queue->entries[0].priv_data;
181d6902 232
b8be63ff 233 if (entry_priv->data)
181d6902 234 pci_free_consistent(pci_dev, dma_size(queue),
b8be63ff
ID
235 entry_priv->data, entry_priv->data_dma);
236 entry_priv->data = NULL;
95ea3627
ID
237}
238
239int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
240{
241 struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
181d6902 242 struct data_queue *queue;
95ea3627
ID
243 int status;
244
245 /*
246 * Allocate DMA
247 */
181d6902
ID
248 queue_for_each(rt2x00dev, queue) {
249 status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);
95ea3627
ID
250 if (status)
251 goto exit;
252 }
253
254 /*
255 * Register interrupt handler.
256 */
257 status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler,
258 IRQF_SHARED, pci_name(pci_dev), rt2x00dev);
259 if (status) {
260 ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
261 pci_dev->irq, status);
b30cdfc5 262 goto exit;
95ea3627
ID
263 }
264
265 return 0;
266
267exit:
b30cdfc5
ID
268 queue_for_each(rt2x00dev, queue)
269 rt2x00pci_free_queue_dma(rt2x00dev, queue);
95ea3627
ID
270
271 return status;
272}
273EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
274
275void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
276{
181d6902 277 struct data_queue *queue;
95ea3627
ID
278
279 /*
280 * Free irq line.
281 */
282 free_irq(rt2x00dev_pci(rt2x00dev)->irq, rt2x00dev);
283
284 /*
285 * Free DMA
286 */
181d6902
ID
287 queue_for_each(rt2x00dev, queue)
288 rt2x00pci_free_queue_dma(rt2x00dev, queue);
95ea3627
ID
289}
290EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
291
292/*
293 * PCI driver handlers.
294 */
295static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
296{
297 kfree(rt2x00dev->rf);
298 rt2x00dev->rf = NULL;
299
300 kfree(rt2x00dev->eeprom);
301 rt2x00dev->eeprom = NULL;
302
21795094
ID
303 if (rt2x00dev->csr.base) {
304 iounmap(rt2x00dev->csr.base);
305 rt2x00dev->csr.base = NULL;
95ea3627
ID
306 }
307}
308
309static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
310{
311 struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
312
21795094 313 rt2x00dev->csr.base = ioremap(pci_resource_start(pci_dev, 0),
95ea3627 314 pci_resource_len(pci_dev, 0));
21795094 315 if (!rt2x00dev->csr.base)
95ea3627
ID
316 goto exit;
317
318 rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
319 if (!rt2x00dev->eeprom)
320 goto exit;
321
322 rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
323 if (!rt2x00dev->rf)
324 goto exit;
325
326 return 0;
327
328exit:
329 ERROR_PROBE("Failed to allocate registers.\n");
330
331 rt2x00pci_free_reg(rt2x00dev);
332
333 return -ENOMEM;
334}
335
336int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
337{
338 struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_data;
339 struct ieee80211_hw *hw;
340 struct rt2x00_dev *rt2x00dev;
341 int retval;
342
343 retval = pci_request_regions(pci_dev, pci_name(pci_dev));
344 if (retval) {
345 ERROR_PROBE("PCI request regions failed.\n");
346 return retval;
347 }
348
349 retval = pci_enable_device(pci_dev);
350 if (retval) {
351 ERROR_PROBE("Enable device failed.\n");
352 goto exit_release_regions;
353 }
354
355 pci_set_master(pci_dev);
356
357 if (pci_set_mwi(pci_dev))
358 ERROR_PROBE("MWI not available.\n");
359
051c256f 360 if (pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
95ea3627
ID
361 ERROR_PROBE("PCI DMA not supported.\n");
362 retval = -EIO;
363 goto exit_disable_device;
364 }
365
366 hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
367 if (!hw) {
368 ERROR_PROBE("Failed to allocate hardware.\n");
369 retval = -ENOMEM;
370 goto exit_disable_device;
371 }
372
373 pci_set_drvdata(pci_dev, hw);
374
375 rt2x00dev = hw->priv;
376 rt2x00dev->dev = pci_dev;
377 rt2x00dev->ops = ops;
378 rt2x00dev->hw = hw;
379
380 retval = rt2x00pci_alloc_reg(rt2x00dev);
381 if (retval)
382 goto exit_free_device;
383
384 retval = rt2x00lib_probe_dev(rt2x00dev);
385 if (retval)
386 goto exit_free_reg;
387
388 return 0;
389
390exit_free_reg:
391 rt2x00pci_free_reg(rt2x00dev);
392
393exit_free_device:
394 ieee80211_free_hw(hw);
395
396exit_disable_device:
397 if (retval != -EBUSY)
398 pci_disable_device(pci_dev);
399
400exit_release_regions:
401 pci_release_regions(pci_dev);
402
403 pci_set_drvdata(pci_dev, NULL);
404
405 return retval;
406}
407EXPORT_SYMBOL_GPL(rt2x00pci_probe);
408
409void rt2x00pci_remove(struct pci_dev *pci_dev)
410{
411 struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
412 struct rt2x00_dev *rt2x00dev = hw->priv;
413
414 /*
415 * Free all allocated data.
416 */
417 rt2x00lib_remove_dev(rt2x00dev);
418 rt2x00pci_free_reg(rt2x00dev);
419 ieee80211_free_hw(hw);
420
421 /*
422 * Free the PCI device data.
423 */
424 pci_set_drvdata(pci_dev, NULL);
425 pci_disable_device(pci_dev);
426 pci_release_regions(pci_dev);
427}
428EXPORT_SYMBOL_GPL(rt2x00pci_remove);
429
430#ifdef CONFIG_PM
431int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
432{
433 struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
434 struct rt2x00_dev *rt2x00dev = hw->priv;
435 int retval;
436
437 retval = rt2x00lib_suspend(rt2x00dev, state);
438 if (retval)
439 return retval;
440
441 rt2x00pci_free_reg(rt2x00dev);
442
443 pci_save_state(pci_dev);
444 pci_disable_device(pci_dev);
445 return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
446}
447EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
448
449int rt2x00pci_resume(struct pci_dev *pci_dev)
450{
451 struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
452 struct rt2x00_dev *rt2x00dev = hw->priv;
453 int retval;
454
455 if (pci_set_power_state(pci_dev, PCI_D0) ||
456 pci_enable_device(pci_dev) ||
457 pci_restore_state(pci_dev)) {
458 ERROR(rt2x00dev, "Failed to resume device.\n");
459 return -EIO;
460 }
461
462 retval = rt2x00pci_alloc_reg(rt2x00dev);
463 if (retval)
464 return retval;
465
466 retval = rt2x00lib_resume(rt2x00dev);
467 if (retval)
468 goto exit_free_reg;
469
470 return 0;
471
472exit_free_reg:
473 rt2x00pci_free_reg(rt2x00dev);
474
475 return retval;
476}
477EXPORT_SYMBOL_GPL(rt2x00pci_resume);
478#endif /* CONFIG_PM */
479
480/*
481 * rt2x00pci module information.
482 */
483MODULE_AUTHOR(DRV_PROJECT);
484MODULE_VERSION(DRV_VERSION);
181d6902 485MODULE_DESCRIPTION("rt2x00 pci library");
95ea3627 486MODULE_LICENSE("GPL");