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Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / net / wireless / realtek / rtw88 / rtw8822c.c
CommitLineData
e3037485
YHC		 1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#include "main.h"
4136214f 6#include "coex.h"
e3037485
YHC		 7#include "fw.h"
8#include "tx.h"
9#include "rx.h"
10#include "phy.h"
11#include "rtw8822c.h"
12#include "rtw8822c_table.h"
13#include "mac.h"
14#include "reg.h"
15#include "debug.h"
5227c2ee 16#include "util.h"
0bd95573 17#include "bf.h"
e3037485
YHC		 18
19static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
20 u8 rx_path, bool is_tx2_path);
21
22static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse,
23 struct rtw8822c_efuse *map)
24{
25 ether_addr_copy(efuse->addr, map->e.mac_addr);
26}
27
28static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
29{
30 struct rtw_efuse *efuse = &rtwdev->efuse;
31 struct rtw8822c_efuse *map;
32 int i;
33
34 map = (struct rtw8822c_efuse *)log_map;
35
36 efuse->rfe_option = map->rfe_option;
4136214f 37 efuse->rf_board_option = map->rf_board_option;
e3037485
YHC		 38 efuse->crystal_cap = map->xtal_k;
39 efuse->channel_plan = map->channel_plan;
40 efuse->country_code[0] = map->country_code[0];
41 efuse->country_code[1] = map->country_code[1];
42 efuse->bt_setting = map->rf_bt_setting;
43 efuse->regd = map->rf_board_option & 0x7;
c97ee3e0
TEH		 44 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal;
45 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal;
46 efuse->thermal_meter_k =
47 (map->path_a_thermal + map->path_b_thermal) >> 1;
48 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf;
e3037485
YHC		 49
50 for (i = 0; i < 4; i++)
51 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
52
53 switch (rtw_hci_type(rtwdev)) {
54 case RTW_HCI_TYPE_PCIE:
55 rtw8822ce_efuse_parsing(efuse, map);
56 break;
57 default:
58 /* unsupported now */
59 return -ENOTSUPP;
60 }
61
62 return 0;
63}
64
65static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre)
66{
67 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
68 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
69 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
70 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
71
72 if (pre)
73 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
74 else
75 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
76}
77
78static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev,
79 struct rtw_backup_info *backup,
80 struct rtw_backup_info *backup_rf)
81{
82 u32 path, i;
83 u32 val;
84 u32 reg;
85 u32 rf_addr[DACK_RF_8822C] = {0x8f};
86 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110,
87 0x1c3c, 0x1c24, 0x1d70, 0x9b4,
88 0x1a00, 0x1a14, 0x1d58, 0x1c38,
89 0x1e24, 0x1e28, 0x1860, 0x4160};
90
91 for (i = 0; i < DACK_REG_8822C; i++) {
92 backup[i].len = 4;
93 backup[i].reg = addrs[i];
94 backup[i].val = rtw_read32(rtwdev, addrs[i]);
95 }
96
97 for (path = 0; path < DACK_PATH_8822C; path++) {
98 for (i = 0; i < DACK_RF_8822C; i++) {
99 reg = rf_addr[i];
100 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
101 backup_rf[path * i + i].reg = reg;
102 backup_rf[path * i + i].val = val;
103 }
104 }
105}
106
107static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev,
108 struct rtw_backup_info *backup,
109 struct rtw_backup_info *backup_rf)
110{
111 u32 path, i;
112 u32 val;
113 u32 reg;
114
115 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C);
116
117 for (path = 0; path < DACK_PATH_8822C; path++) {
118 for (i = 0; i < DACK_RF_8822C; i++) {
119 val = backup_rf[path * i + i].val;
120 reg = backup_rf[path * i + i].reg;
121 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
122 }
123 }
124}
125
126static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value,
127 u32 *min, u32 *max)
128{
129 if (value >= 0x200) {
130 if (*min >= 0x200) {
131 if (*min > value)
132 *min = value;
133 } else {
134 *min = value;
135 }
136 if (*max >= 0x200) {
137 if (*max < value)
138 *max = value;
139 }
140 } else {
141 if (*min < 0x200) {
142 if (*min > value)
143 *min = value;
144 }
145
146 if (*max >= 0x200) {
147 *max = value;
148 } else {
149 if (*max < value)
150 *max = value;
151 }
152 }
153}
154
155static void swap_u32(u32 *v1, u32 *v2)
156{
157 u32 tmp;
158
159 tmp = *v1;
160 *v1 = *v2;
161 *v2 = tmp;
162}
163
164static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2)
165{
166 if (*v1 >= 0x200 && *v2 >= 0x200) {
167 if (*v1 > *v2)
168 swap_u32(v1, v2);
169 } else if (*v1 < 0x200 && *v2 < 0x200) {
170 if (*v1 > *v2)
171 swap_u32(v1, v2);
172 } else if (*v1 < 0x200 && *v2 >= 0x200) {
173 swap_u32(v1, v2);
174 }
175}
176
177static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
178{
179 u32 i, j;
180
181 for (i = 0; i < DACK_SN_8822C - 1; i++) {
182 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
183 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]);
184 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]);
185 }
186 }
187}
188
189static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
190{
191 u32 p, m, t, i;
192
193 m = 0;
194 p = 0;
195 for (i = 10; i < DACK_SN_8822C - 10; i++) {
196 if (vec[i] > 0x200)
197 m = (0x400 - vec[i]) + m;
198 else
199 p = vec[i] + p;
200 }
201
202 if (p > m) {
203 t = p - m;
204 t = t / (DACK_SN_8822C - 20);
205 } else {
206 t = m - p;
207 t = t / (DACK_SN_8822C - 20);
208 if (t != 0x0)
209 t = 0x400 - t;
210 }
211
212 *val = t;
213}
214
a11cddd4 215static u32 rtw8822c_get_path_write_addr(u8 path)
e3037485
YHC		 216{
217 u32 base_addr;
218
219 switch (path) {
220 case RF_PATH_A:
221 base_addr = 0x1800;
222 break;
223 case RF_PATH_B:
224 base_addr = 0x4100;
225 break;
226 default:
227 WARN_ON(1);
228 return -1;
229 }
230
231 return base_addr;
232}
233
a11cddd4
YHC		 234static u32 rtw8822c_get_path_read_addr(u8 path)
235{
236 u32 base_addr;
237
238 switch (path) {
239 case RF_PATH_A:
240 base_addr = 0x2800;
241 break;
242 case RF_PATH_B:
243 base_addr = 0x4500;
244 break;
245 default:
246 WARN_ON(1);
247 return -1;
248 }
249
250 return base_addr;
251}
252
e3037485
YHC		 253static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value)
254{
255 bool ret = true;
256
257 if ((value >= 0x200 && (0x400 - value) > 0x64) ||
258 (value < 0x200 && value > 0x64)) {
259 ret = false;
260 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n");
261 }
262
263 return ret;
264}
265
266static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
267{
268 u32 temp;
269 int i = 0, cnt = 0;
270
271 while (i < DACK_SN_8822C && cnt < 10000) {
272 cnt++;
273 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
274 iv[i] = (temp & 0x3ff000) >> 12;
275 qv[i] = temp & 0x3ff;
276
277 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) &&
278 rtw8822c_dac_iq_check(rtwdev, qv[i]))
279 i++;
280 }
281}
282
283static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev,
284 u32 *iv, u32 *qv,
285 u32 *i_value, u32 *q_value)
286{
287 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0;
288 u32 i_delta, q_delta;
289 u32 temp;
290 int i, cnt = 0;
291
292 do {
293 i_min = iv[0];
294 i_max = iv[0];
295 q_min = qv[0];
296 q_max = qv[0];
297 for (i = 0; i < DACK_SN_8822C; i++) {
298 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max);
299 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max);
300 }
301
302 if (i_max < 0x200 && i_min < 0x200)
303 i_delta = i_max - i_min;
304 else if (i_max >= 0x200 && i_min >= 0x200)
305 i_delta = i_max - i_min;
306 else
307 i_delta = i_max + (0x400 - i_min);
308
309 if (q_max < 0x200 && q_min < 0x200)
310 q_delta = q_max - q_min;
311 else if (q_max >= 0x200 && q_min >= 0x200)
312 q_delta = q_max - q_min;
313 else
314 q_delta = q_max + (0x400 - q_min);
315
316 rtw_dbg(rtwdev, RTW_DBG_RFK,
317 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n",
318 i_min, i_max, i_delta);
319 rtw_dbg(rtwdev, RTW_DBG_RFK,
320 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n",
321 q_min, q_max, q_delta);
322
323 rtw8822c_dac_iq_sort(rtwdev, iv, qv);
324
325 if (i_delta > 5 || q_delta > 5) {
326 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
327 iv[0] = (temp & 0x3ff000) >> 12;
328 qv[0] = temp & 0x3ff;
329 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
330 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
331 qv[DACK_SN_8822C - 1] = temp & 0x3ff;
332 } else {
333 break;
334 }
335 } while (cnt++ < 100);
336
337 rtw8822c_dac_iq_offset(rtwdev, iv, i_value);
338 rtw8822c_dac_iq_offset(rtwdev, qv, q_value);
339}
340
341static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev,
342 u32 *i_value, u32 *q_value)
343{
344 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C];
345 u32 rf_a, rf_b;
346
e3037485
YHC		 347 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
348 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
349
350 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
351 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
352
353 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv);
354 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value);
355}
356
357static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev)
358{
359 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
360 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
361 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
362 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
363 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
364 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
365 rtw_write32(rtwdev, 0x1b00, 0x00000008);
366 rtw_write8(rtwdev, 0x1bcc, 0x3f);
367 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
368 rtw_write8(rtwdev, 0x1bcc, 0x3f);
369 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
370 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
371}
372
373static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev,
374 u8 path, u32 *adc_ic, u32 *adc_qc)
375{
a11cddd4 376 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
e3037485
YHC		 377 u32 ic = 0, qc = 0, temp = 0;
378 u32 base_addr;
379 u32 path_sel;
380 int i;
381
382 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
383
a11cddd4 384 base_addr = rtw8822c_get_path_write_addr(path);
e3037485
YHC		 385 switch (path) {
386 case RF_PATH_A:
387 path_sel = 0xa0000;
388 break;
389 case RF_PATH_B:
390 path_sel = 0x80000;
391 break;
392 default:
393 WARN_ON(1);
394 return;
395 }
396
397 /* ADCK step1 */
398 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
399 if (path == RF_PATH_B)
400 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
401 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
402 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
403 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
404 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
405 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
406 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
407 for (i = 0; i < 10; i++) {
408 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i);
409 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
410 rtw_write32(rtwdev, 0x1c24, 0x00010002);
411 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
412 rtw_dbg(rtwdev, RTW_DBG_RFK,
413 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc);
414
415 /* compensation value */
416 if (ic != 0x0) {
417 ic = 0x400 - ic;
418 *adc_ic = ic;
419 }
420 if (qc != 0x0) {
421 qc = 0x400 - qc;
422 *adc_qc = qc;
423 }
424 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
425 rtw_write32(rtwdev, base_addr + 0x68, temp);
a11cddd4 426 dm_info->dack_adck[path] = temp;
e3037485
YHC		 427 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
428 base_addr + 0x68, temp);
429 /* check ADC DC offset */
430 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
431 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
432 rtw_dbg(rtwdev, RTW_DBG_RFK,
433 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc);
434 if (ic >= 0x200)
435 ic = 0x400 - ic;
436 if (qc >= 0x200)
437 qc = 0x400 - qc;
438 if (ic < 5 && qc < 5)
439 break;
440 }
441
442 /* ADCK step2 */
443 rtw_write32(rtwdev, 0x1c3c, 0x00000003);
444 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
445 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
446
447 /* release pull low switch on IQ path */
448 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
449}
450
451static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
452{
a11cddd4 453 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
e3037485 454 u32 base_addr;
a11cddd4 455 u32 read_addr;
e3037485 456
a11cddd4
YHC		 457 base_addr = rtw8822c_get_path_write_addr(path);
458 read_addr = rtw8822c_get_path_read_addr(path);
e3037485 459
a11cddd4 460 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
e3037485
YHC		 461 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
462 if (path == RF_PATH_A) {
463 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
464 rtw_write32(rtwdev, 0x1c38, 0xffffffff);
465 }
466 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
467 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
468 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
469 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
470 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
471 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
472 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
473 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
474 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
475 mdelay(2);
476 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
477 mdelay(2);
478 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
479 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
480 mdelay(1);
481 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
e3037485
YHC		 482 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
483 mdelay(20);
a11cddd4
YHC		 484 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
485 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
486 rtw_err(rtwdev, "failed to wait for dack ready\n");
e3037485 487 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
a11cddd4 488 mdelay(1);
e3037485
YHC		 489 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
490 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
491 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
492 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
493 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
494}
495
496static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev,
497 u8 path, u32 *ic_out, u32 *qc_out)
498{
499 u32 base_addr;
500 u32 ic, qc, ic_in, qc_in;
501
a11cddd4 502 base_addr = rtw8822c_get_path_write_addr(path);
e3037485
YHC		 503 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
504 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
505 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
506 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
507
508 rtw_write32(rtwdev, 0x1b00, 0x00000008);
509 rtw_write8(rtwdev, 0x1bcc, 0x03f);
510 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
511 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
512 rtw_write32(rtwdev, 0x1c3c, 0x00088103);
513
514 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in);
515 ic = ic_in;
516 qc = qc_in;
517
518 /* compensation value */
519 if (ic != 0x0)
520 ic = 0x400 - ic;
521 if (qc != 0x0)
522 qc = 0x400 - qc;
523 if (ic < 0x300) {
524 ic = ic * 2 * 6 / 5;
525 ic = ic + 0x80;
526 } else {
527 ic = (0x400 - ic) * 2 * 6 / 5;
528 ic = 0x7f - ic;
529 }
530 if (qc < 0x300) {
531 qc = qc * 2 * 6 / 5;
532 qc = qc + 0x80;
533 } else {
534 qc = (0x400 - qc) * 2 * 6 / 5;
535 qc = 0x7f - qc;
536 }
537
538 *ic_out = ic;
539 *qc_out = qc;
540
541 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
542 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
543}
544
545static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
546 u32 adc_ic, u32 adc_qc,
547 u32 *ic_in, u32 *qc_in,
548 u32 *i_out, u32 *q_out)
549{
550 u32 base_addr;
a11cddd4 551 u32 read_addr;
e3037485
YHC		 552 u32 ic, qc;
553 u32 temp;
554
a11cddd4
YHC		 555 base_addr = rtw8822c_get_path_write_addr(path);
556 read_addr = rtw8822c_get_path_read_addr(path);
e3037485
YHC		 557 ic = *ic_in;
558 qc = *qc_in;
559
560 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
561 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
562 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
563 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
564 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
565 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
566 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
567 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
568 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
569 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
570 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
571 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
572 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
573 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
574 mdelay(2);
575 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
576 mdelay(2);
577 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
578 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
579 mdelay(1);
580 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
e3037485
YHC		 581 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
582 mdelay(20);
a11cddd4
YHC		 583 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
584 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
585 rtw_err(rtwdev, "failed to write IQ vector to hardware\n");
e3037485 586 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
a11cddd4 587 mdelay(1);
e3037485
YHC		 588 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
589 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
590
591 /* check DAC DC offset */
592 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10);
593 rtw_write32(rtwdev, base_addr + 0x68, temp);
594 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
595 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
596 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
597 if (ic >= 0x10)
598 ic = ic - 0x10;
599 else
600 ic = 0x400 - (0x10 - ic);
601
602 if (qc >= 0x10)
603 qc = qc - 0x10;
604 else
605 qc = 0x400 - (0x10 - qc);
606
607 *i_out = ic;
608 *q_out = qc;
609
610 if (ic >= 0x200)
611 ic = 0x400 - ic;
612 if (qc >= 0x200)
613 qc = 0x400 - qc;
614
615 *ic_in = ic;
616 *qc_in = qc;
617
618 rtw_dbg(rtwdev, RTW_DBG_RFK,
619 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out);
620}
621
622static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
623{
a11cddd4 624 u32 base_addr = rtw8822c_get_path_write_addr(path);
e3037485
YHC		 625
626 rtw_write32(rtwdev, base_addr + 0x68, 0x0);
627 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
628 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
629 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
630}
631
a11cddd4
YHC		 632static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev,
633 u8 path, u8 vec, u32 w_addr, u32 r_addr)
634{
635 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
636 u16 val;
637 u32 i;
638
639 if (WARN_ON(vec >= 2))
640 return;
641
642 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
643 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
644 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
645 dm_info->dack_msbk[path][vec][i] = val;
646 }
647}
648
649static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path)
650{
651 u32 w_off = 0x1c;
652 u32 r_off = 0x2c;
653 u32 w_addr, r_addr;
654
655 if (WARN_ON(path >= 2))
656 return;
657
658 /* backup I vector */
659 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0;
660 r_addr = rtw8822c_get_path_read_addr(path) + 0x10;
661 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
662
663 /* backup Q vector */
664 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
665 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off;
666 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr);
667}
668
669static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev)
670{
671 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
672 u8 val;
673
674 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
675 dm_info->dack_dck[RF_PATH_A][0][0] = val;
676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
677 dm_info->dack_dck[RF_PATH_A][0][1] = val;
678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
679 dm_info->dack_dck[RF_PATH_A][1][0] = val;
680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
681 dm_info->dack_dck[RF_PATH_A][1][1] = val;
682
683 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
684 dm_info->dack_dck[RF_PATH_B][0][0] = val;
685 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
686 dm_info->dack_dck[RF_PATH_B][1][0] = val;
687 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
688 dm_info->dack_dck[RF_PATH_B][0][1] = val;
689 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
690 dm_info->dack_dck[RF_PATH_B][1][1] = val;
691}
692
693static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev)
694{
695 u32 temp[3];
696
697 temp[0] = rtw_read32(rtwdev, 0x1860);
698 temp[1] = rtw_read32(rtwdev, 0x4160);
699 temp[2] = rtw_read32(rtwdev, 0x9b4);
700
701 /* set clock */
702 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
703
704 /* backup path-A I/Q */
705 rtw_write32_clr(rtwdev, 0x1830, BIT(30));
706 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
707 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A);
708
709 /* backup path-B I/Q */
710 rtw_write32_clr(rtwdev, 0x4130, BIT(30));
711 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
712 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B);
713
714 rtw8822c_dac_cal_backup_dck(rtwdev);
715 rtw_write32_set(rtwdev, 0x1830, BIT(30));
716 rtw_write32_set(rtwdev, 0x4130, BIT(30));
717
718 rtw_write32(rtwdev, 0x1860, temp[0]);
719 rtw_write32(rtwdev, 0x4160, temp[1]);
720 rtw_write32(rtwdev, 0x9b4, temp[2]);
721}
722
723static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev)
724{
725 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
726 u8 val;
727
728 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19));
729 val = dm_info->dack_dck[RF_PATH_A][0][0];
730 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
731 val = dm_info->dack_dck[RF_PATH_A][0][1];
732 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
733
734 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19));
735 val = dm_info->dack_dck[RF_PATH_A][1][0];
736 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
737 val = dm_info->dack_dck[RF_PATH_A][1][1];
738 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
739
740 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19));
741 val = dm_info->dack_dck[RF_PATH_B][0][0];
742 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
743 val = dm_info->dack_dck[RF_PATH_B][0][1];
744 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
745
746 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19));
747 val = dm_info->dack_dck[RF_PATH_B][1][0];
748 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
749 val = dm_info->dack_dck[RF_PATH_B][1][1];
750 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
751}
752
753static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev)
754{
755 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
756
757 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
758 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
759 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
760 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
761
762 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
763 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
764 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
765 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
766
767 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
768 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
769 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
770 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
771
772 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
773 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
774 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
775 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
776
777 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
778 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
779 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
780 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
781
782 rtw8822c_dac_cal_restore_dck(rtwdev);
783
784 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
785 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
786 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
787 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
788
789 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
790 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
791
792 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
793 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
794 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
795 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
796
797 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
798 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
799 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
800 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
801
802 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
803 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
804}
805
806static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev,
807 u32 target_addr, u32 toggle_addr)
808{
809 u32 cnt = 0;
810
811 do {
812 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
813 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
814
815 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
816 return true;
817
818 } while (cnt++ < 100);
819
820 return false;
821}
822
823static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path)
824{
825 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
826 u32 w_off = 0x1c;
827 u32 r_off = 0x2c;
828 u32 w_i, r_i, w_q, r_q;
829 u32 value;
830 u32 i;
831
832 w_i = rtw8822c_get_path_write_addr(path) + 0xb0;
833 r_i = rtw8822c_get_path_read_addr(path) + 0x08;
834 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
835 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off;
836
837 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
838 return false;
839
840 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
841 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
842 value = dm_info->dack_msbk[path][0][i];
843 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
844 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
845 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
846 }
847
848 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
849
850 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
851 return false;
852
853 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
854 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
855 value = dm_info->dack_msbk[path][1][i];
856 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
857 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
858 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
859 }
860 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
861
862 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
863 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
864 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
865 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
866
867 return true;
868}
869
870static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
871{
872 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A))
873 return false;
874
875 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B))
876 return false;
877
878 return true;
879}
880
881static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
882{
883 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
884 u32 temp[3];
885
886 /* sample the first element for both path's IQ vector */
887 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 &&
888 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 &&
889 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 &&
890 dm_info->dack_msbk[RF_PATH_B][1][0] == 0)
891 return false;
892
893 temp[0] = rtw_read32(rtwdev, 0x1860);
894 temp[1] = rtw_read32(rtwdev, 0x4160);
895 temp[2] = rtw_read32(rtwdev, 0x9b4);
896
897 rtw8822c_dac_cal_restore_prepare(rtwdev);
898 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
899 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
900 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
901 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
902 return false;
903
904 if (!__rtw8822c_dac_cal_restore(rtwdev)) {
905 rtw_err(rtwdev, "failed to restore dack vectors\n");
906 return false;
907 }
908
909 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
910 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
911 rtw_write32(rtwdev, 0x1860, temp[0]);
912 rtw_write32(rtwdev, 0x4160, temp[1]);
913 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
914 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
915 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
916 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
917 rtw_write32(rtwdev, 0x9b4, temp[2]);
918
919 return true;
920}
921
e3037485
YHC		 922static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev)
923{
924 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C];
925 struct rtw_backup_info backup[DACK_REG_8822C];
926 u32 ic = 0, qc = 0, i;
927 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;
928 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;
929 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;
930
a11cddd4
YHC		 931 if (rtw8822c_dac_cal_restore(rtwdev))
932 return;
933
934 /* not able to restore, do it */
935
e3037485
YHC		 936 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf);
937
938 rtw8822c_dac_bb_setting(rtwdev);
939
940 /* path-A */
941 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a);
942 for (i = 0; i < 10; i++) {
943 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A);
944 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc);
945 ic_a = ic;
946 qc_a = qc;
947
948 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a,
949 &ic, &qc, &i_a, &q_a);
950
951 if (ic < 5 && qc < 5)
952 break;
953 }
954 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A);
955
956 /* path-B */
957 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b);
958 for (i = 0; i < 10; i++) {
959 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B);
960 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc);
961 ic_b = ic;
962 qc_b = qc;
963
964 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b,
965 &ic, &qc, &i_b, &q_b);
966
967 if (ic < 5 && qc < 5)
968 break;
969 }
970 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B);
971
972 rtw_write32(rtwdev, 0x1b00, 0x00000008);
973 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
974 rtw_write8(rtwdev, 0x1bcc, 0x0);
975 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
976 rtw_write8(rtwdev, 0x1bcc, 0x0);
977
978 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf);
979
a11cddd4
YHC		 980 /* backup results to restore, saving a lot of time */
981 rtw8822c_dac_cal_backup(rtwdev);
982
e3037485
YHC		 983 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
984 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
985 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
986 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
987}
988
989static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev)
990{
991 u8 x2k_busy;
992
993 mdelay(1);
994 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
995 if (x2k_busy == 1) {
996 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
997 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
998 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
999 mdelay(1);
1000 }
1001}
1002
1003static void rtw8822c_rf_init(struct rtw_dev *rtwdev)
1004{
1005 rtw8822c_rf_dac_cal(rtwdev);
1006 rtw8822c_rf_x2_check(rtwdev);
1007}
1008
a969cf42 1009static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev)
c97ee3e0
TEH		 1010{
1011 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1012 u8 path;
1013
1014 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) {
1015 dm_info->delta_power_index[path] = 0;
1016 ewma_thermal_init(&dm_info->avg_thermal[path]);
1017 dm_info->thermal_avg[path] = 0xff;
1018 }
1019
1020 dm_info->pwr_trk_triggered = false;
1021 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
1022}
1023
e3037485
YHC		 1024static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
1025{
1026 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1027 struct rtw_hal *hal = &rtwdev->hal;
1028 u8 crystal_cap;
1029 u8 cck_gi_u_bnd_msb = 0;
1030 u8 cck_gi_u_bnd_lsb = 0;
1031 u8 cck_gi_l_bnd_msb = 0;
1032 u8 cck_gi_l_bnd_lsb = 0;
1033 bool is_tx2_path;
1034
1035 /* power on BB/RF domain */
1036 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
1037 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
1038 rtw_write8_set(rtwdev, REG_RF_CTRL,
1039 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
1040 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
1041
5227c2ee
TEH		 1042 /* disable low rate DPD */
1043 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1044
e3037485
YHC		 1045 /* pre init before header files config */
1046 rtw8822c_header_file_init(rtwdev, true);
1047
1048 rtw_phy_load_tables(rtwdev);
1049
1050 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1051 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
1052 crystal_cap | (crystal_cap << 7));
1053
1054 /* post init after header files config */
1055 rtw8822c_header_file_init(rtwdev, false);
1056
1057 is_tx2_path = false;
1058 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
1059 is_tx2_path);
1060 rtw_phy_init(rtwdev);
1061
1062 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
1063 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
1064 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
1065 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
1066
1067 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb));
1068 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb));
1069
1070 rtw8822c_rf_init(rtwdev);
c97ee3e0 1071 rtw8822c_pwrtrack_init(rtwdev);
0bd95573
TEH		 1072
1073 rtw_bf_phy_init(rtwdev);
e3037485
YHC		 1074}
1075
1076#define WLAN_TXQ_RPT_EN 0x1F
1077#define WLAN_SLOT_TIME 0x09
1078#define WLAN_PIFS_TIME 0x1C
1079#define WLAN_SIFS_CCK_CONT_TX 0x0A
1080#define WLAN_SIFS_OFDM_CONT_TX 0x0E
1081#define WLAN_SIFS_CCK_TRX 0x0A
1082#define WLAN_SIFS_OFDM_TRX 0x10
1083#define WLAN_NAV_MAX 0xC8
1084#define WLAN_RDG_NAV 0x05
1085#define WLAN_TXOP_NAV 0x1B
1086#define WLAN_CCK_RX_TSF 0x30
1087#define WLAN_OFDM_RX_TSF 0x30
1088#define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
1089#define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
1090#define WLAN_DRV_EARLY_INT 0x04
1091#define WLAN_BCN_CTRL_CLT0 0x10
1092#define WLAN_BCN_DMA_TIME 0x02
1093#define WLAN_BCN_MAX_ERR 0xFF
1094#define WLAN_SIFS_CCK_DUR_TUNE 0x0A
1095#define WLAN_SIFS_OFDM_DUR_TUNE 0x10
1096#define WLAN_SIFS_CCK_CTX 0x0A
1097#define WLAN_SIFS_CCK_IRX 0x0A
1098#define WLAN_SIFS_OFDM_CTX 0x0E
1099#define WLAN_SIFS_OFDM_IRX 0x0E
1100#define WLAN_EIFS_DUR_TUNE 0x40
1101#define WLAN_EDCA_VO_PARAM 0x002FA226
1102#define WLAN_EDCA_VI_PARAM 0x005EA328
1103#define WLAN_EDCA_BE_PARAM 0x005EA42B
1104#define WLAN_EDCA_BK_PARAM 0x0000A44F
1105
1106#define WLAN_RX_FILTER0 0xFFFFFFFF
1107#define WLAN_RX_FILTER2 0xFFFF
1108#define WLAN_RCR_CFG 0xE400220E
1109#define WLAN_RXPKT_MAX_SZ 12288
1110#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
1111
1112#define WLAN_AMPDU_MAX_TIME 0x70
1113#define WLAN_RTS_LEN_TH 0xFF
1114#define WLAN_RTS_TX_TIME_TH 0x08
46ebb174
YHC		 1115#define WLAN_MAX_AGG_PKT_LIMIT 0x3f
1116#define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f
e3037485
YHC		 1117#define WLAN_PRE_TXCNT_TIME_TH 0x1E0
1118#define FAST_EDCA_VO_TH 0x06
1119#define FAST_EDCA_VI_TH 0x06
1120#define FAST_EDCA_BE_TH 0x06
1121#define FAST_EDCA_BK_TH 0x06
1122#define WLAN_BAR_RETRY_LIMIT 0x01
1123#define WLAN_BAR_ACK_TYPE 0x05
1124#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
1125#define WLAN_RESP_TXRATE 0x84
1126#define WLAN_ACK_TO 0x21
1127#define WLAN_ACK_TO_CCK 0x6A
1128#define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000
1129#define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504
1130#define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504
1131#define WLAN_DATA_RATE_FB_RATE0 0xFE01F010
1132#define WLAN_DATA_RATE_FB_RATE0_H 0x40000000
1133#define WLAN_RTS_RATE_FB_RATE1 0x003FF010
1134#define WLAN_RTS_RATE_FB_RATE1_H 0x40000000
1135#define WLAN_RTS_RATE_FB_RATE4 0x0600F010
1136#define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0
1137#define WLAN_RTS_RATE_FB_RATE5 0x0600F015
1138#define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0
27c65bfc 1139#define WLAN_MULTI_ADDR 0xFFFFFFFF
e3037485
YHC		 1140
1141#define WLAN_TX_FUNC_CFG1 0x30
1142#define WLAN_TX_FUNC_CFG2 0x30
1143#define WLAN_MAC_OPT_NORM_FUNC1 0x98
1144#define WLAN_MAC_OPT_LB_FUNC1 0x80
1145#define WLAN_MAC_OPT_FUNC2 0x30810041
bc61ae96 1146#define WLAN_MAC_INT_MIG_CFG 0x33330000
e3037485
YHC		 1147
1148#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
1149 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
1150 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
1151 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
1152
1153#define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \
1154 (WLAN_SIFS_OFDM_DUR_TUNE << 8))
1155
1156#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
1157 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
1158
1159#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
1160#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
1161
1162#define MAC_CLK_SPEED 80 /* 80M */
1163#define EFUSE_PCB_INFO_OFFSET 0xCA
1164
1165static int rtw8822c_mac_init(struct rtw_dev *rtwdev)
1166{
1167 u8 value8;
1168 u16 value16;
1169 u32 value32;
1170 u16 pre_txcnt;
1171
1172 /* txq control */
1173 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL);
1174 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2));
1175 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8);
1176 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
1177 /* sifs control */
1178 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE);
1179 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
1180 rtw_write16(rtwdev, REG_RESP_SIFS_CCK,
1181 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8);
1182 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM,
1183 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8);
1184 /* rate fallback control */
1185 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4);
1186 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8);
1187 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8);
1188 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0);
1189 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H);
1190 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1);
1191 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H);
1192 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4);
1193 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H);
1194 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5);
1195 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H);
1196 /* protocol configuration */
1197 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
1198 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
1199 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
1200 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
1201 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
1202 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
1203 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
1204 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
1205 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
1206 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
1207 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
1208 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
1209 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
1210 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
1211 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
1212 /* close BA parser */
1213 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN);
1214 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC);
1215
1216 /* EDCA configuration */
1217 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM);
1218 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM);
1219 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM);
1220 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM);
1221 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
1222 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
1223 rtw_write8_set(rtwdev, REG_RD_CTRL + 1,
1224 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE |
1225 BIT_DIS_STBC_CFE) >> 8);
1226
1227 /* MAC clock configuration */
1228 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL);
1229 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
1230 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
1231
1232 rtw_write8_set(rtwdev, REG_MISC_CTRL,
1233 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA);
1234 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
1235 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
1236 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
1237 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
1238 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
1239 /* Set beacon cotnrol - enable TSF and other related functions */
1240 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1241 /* Set send beacon related registers */
1242 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
1243 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
1244 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0);
1245 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
1246 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR);
1247
1248 /* WMAC configuration */
27c65bfc
TEH		 1249 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR);
1250 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR);
e3037485
YHC		 1251 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE);
1252 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO);
1253 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
1254 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE);
1255 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX);
1256 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE);
1257 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
1258 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
1259 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
1260 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
1261 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
1262 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
1263 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN);
1264 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
1265 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1);
1266
1267 /* init low power */
1268 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
1269 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) |
1270 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16;
1271 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16);
1272 value16 = 0;
1273 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1);
1274 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN
1275 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN
1276 | BIT_RXPSF_OFDMRST;
1277 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
1278 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
1279 /* rx ignore configuration */
1280 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL);
1281 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST |
1282 BIT_RXPSF_CONT_ERRCHKEN);
1283 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07);
1284 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
1285
bc61ae96
TSL		 1286 /* Interrupt migration configuration */
1287 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG);
1288
e3037485
YHC		 1289 return 0;
1290}
1291
1292static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1293{
1294#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
1295#define RF18_BAND_2G (0)
1296#define RF18_BAND_5G (BIT(16) | BIT(8))
1297#define RF18_CHANNEL_MASK (MASKBYTE0)
1298#define RF18_RFSI_MASK (BIT(18) | BIT(17))
1299#define RF18_RFSI_GE_CH80 (BIT(17))
1300#define RF18_RFSI_GT_CH140 (BIT(18))
1301#define RF18_BW_MASK (BIT(13) | BIT(12))
1302#define RF18_BW_20M (BIT(13) | BIT(12))
1303#define RF18_BW_40M (BIT(13))
1304#define RF18_BW_80M (BIT(12))
1305
1306 u32 rf_reg18 = 0;
1307 u32 rf_rxbb = 0;
1308
1309 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
1310
1311 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
1312 RF18_BW_MASK);
1313
8575b534 1314 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G);
e3037485 1315 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
8575b534 1316 if (IS_CH_5G_BAND_4(channel))
e3037485 1317 rf_reg18 |= RF18_RFSI_GT_CH140;
8575b534 1318 else if (IS_CH_5G_BAND_3(channel))
e3037485
YHC		 1319 rf_reg18 |= RF18_RFSI_GE_CH80;
1320
1321 switch (bw) {
1322 case RTW_CHANNEL_WIDTH_5:
1323 case RTW_CHANNEL_WIDTH_10:
1324 case RTW_CHANNEL_WIDTH_20:
1325 default:
1326 rf_reg18 |= RF18_BW_20M;
1327 rf_rxbb = 0x18;
1328 break;
1329 case RTW_CHANNEL_WIDTH_40:
1330 /* RF bandwidth */
1331 rf_reg18 |= RF18_BW_40M;
1332 rf_rxbb = 0x10;
1333 break;
1334 case RTW_CHANNEL_WIDTH_80:
1335 rf_reg18 |= RF18_BW_80M;
1336 rf_rxbb = 0x8;
1337 break;
1338 }
1339
1340 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
1341 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
1342 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
1343 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
1344
1345 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
1346 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
1347 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
1348 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
1349
1350 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18);
1351 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18);
1352}
1353
1354static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev)
1355{
1356 u32 igi;
1357
1358 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
1359 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
1360 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
1361 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
1362 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
1363}
1364
1365static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1366 u8 primary_ch_idx)
1367{
8575b534 1368 if (IS_CH_2G_BAND(channel)) {
e3037485
YHC		 1369 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1370 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1371 rtw_write32_set(rtwdev, REG_TXF4, BIT(20));
1372 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1373 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1374 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
1375
f859e71f
CHL		 1376 switch (bw) {
1377 case RTW_CHANNEL_WIDTH_20:
1378 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
1379 0x5);
1380 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
1381 0x5);
1382 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1383 0x6);
1384 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1385 0x6);
1386 break;
1387 case RTW_CHANNEL_WIDTH_40:
1388 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
1389 0x4);
1390 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
1391 0x4);
1392 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1393 0x0);
1394 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1395 0x0);
1396 break;
1397 }
e3037485
YHC		 1398 if (channel == 13 || channel == 14)
1399 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
1400 else if (channel == 11 || channel == 12)
1401 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
1402 else
1403 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
1404 if (channel == 14) {
1405 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
1406 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1407 0x4962c931);
1408 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
1409 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
1410 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
1411 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
1412 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1413 0xff012455);
1414 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
1415 } else {
1416 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
1417 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1418 0x3e18fec8);
1419 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
1420 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
1421 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
1422 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD,
1423 0x00faf0de);
1424 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1425 0x00122344);
1426 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD,
1427 0x0fffffff);
1428 }
1429 if (channel == 13)
1430 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1431 else
1432 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
8575b534 1433 } else if (IS_CH_5G_BAND(channel)) {
e3037485
YHC		 1434 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1435 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1436 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1437 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20));
1438 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x0);
1439 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
1440 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
8575b534 1441 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) {
f859e71f
CHL		 1442 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1443 0x1);
1444 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1445 0x1);
8575b534 1446 } else if (IS_CH_5G_BAND_3(channel)) {
f859e71f
CHL		 1447 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1448 0x2);
1449 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1450 0x2);
8575b534 1451 } else if (IS_CH_5G_BAND_4(channel)) {
f859e71f
CHL		 1452 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1453 0x3);
1454 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1455 0x3);
e3037485
YHC		 1456 }
1457
1458 if (channel >= 36 && channel <= 51)
1459 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
1460 else if (channel >= 52 && channel <= 55)
1461 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
1462 else if (channel >= 56 && channel <= 111)
1463 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
1464 else if (channel >= 112 && channel <= 119)
1465 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
1466 else if (channel >= 120 && channel <= 172)
1467 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
1468 else if (channel >= 173 && channel <= 177)
1469 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
1470 }
1471
1472 switch (bw) {
1473 case RTW_CHANNEL_WIDTH_20:
1474 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
1475 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1476 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
1477 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
1478 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
f859e71f
CHL		 1479 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1480 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1481 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
e3037485
YHC		 1482 break;
1483 case RTW_CHANNEL_WIDTH_40:
1484 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4),
1485 (primary_ch_idx == 1 ? 1 : 0));
1486 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
1487 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1488 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1489 (primary_ch_idx | (primary_ch_idx << 4)));
f859e71f
CHL		 1490 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
1491 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1492 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
e3037485
YHC		 1493 break;
1494 case RTW_CHANNEL_WIDTH_80:
1495 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
1496 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1497 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1498 (primary_ch_idx | (primary_ch_idx << 4)));
f859e71f
CHL		 1499 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
1500 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
e3037485
YHC		 1501 break;
1502 case RTW_CHANNEL_WIDTH_5:
1503 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1504 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1505 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
1506 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
1507 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
f859e71f
CHL		 1508 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1509 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1510 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
e3037485
YHC		 1511 break;
1512 case RTW_CHANNEL_WIDTH_10:
1513 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1514 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1515 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
1516 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
1517 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
f859e71f
CHL		 1518 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1519 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1520 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
e3037485
YHC		 1521 break;
1522 }
1523}
1524
1525static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1526 u8 primary_chan_idx)
1527{
1528 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
1529 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
1530 rtw8822c_set_channel_rf(rtwdev, channel, bw);
1531 rtw8822c_toggle_igi(rtwdev);
1532}
1533
1534static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1535{
1536 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
1537 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
1538 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
1539 } else if (rx_path == BB_PATH_AB) {
1540 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
1541 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
1542 }
1543
1544 if (rx_path == BB_PATH_A)
1545 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
1546 else if (rx_path == BB_PATH_B)
1547 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
1548 else if (rx_path == BB_PATH_AB)
1549 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
1550}
1551
1552static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1553{
1554 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
1555 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
1556 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
1557 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
1558 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
1559 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
1560 } else if (rx_path == BB_PATH_AB) {
1561 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
1562 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
1563 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
1564 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
1565 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
1566 }
1567
1568 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
1569 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
1570}
1571
1572static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1573{
1574 rtw8822c_config_cck_rx_path(rtwdev, rx_path);
1575 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path);
1576}
1577
1578static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1579 bool is_tx2_path)
1580{
1581 if (tx_path == BB_PATH_A) {
1582 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1583 } else if (tx_path == BB_PATH_B) {
1584 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
1585 } else {
1586 if (is_tx2_path)
1587 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
1588 else
1589 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1590 }
1591}
1592
1593static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1594 bool is_tx2_path)
1595{
1596 if (tx_path == BB_PATH_A) {
1597 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
1598 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1599 } else if (tx_path == BB_PATH_B) {
1600 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
1601 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1602 } else {
1603 if (is_tx2_path) {
1604 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
1605 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
1606 } else {
1607 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
1608 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
1609 }
1610 }
1611}
1612
1613static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1614 bool is_tx2_path)
1615{
1616 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path);
1617 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path);
1618}
1619
1620static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
1621 u8 rx_path, bool is_tx2_path)
1622{
1623 if ((tx_path | rx_path) & BB_PATH_A)
1624 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
1625 else
1626 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
1627 if ((tx_path | rx_path) & BB_PATH_B)
1628 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
1629 else
1630 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
1631
1632 rtw8822c_config_rx_path(rtwdev, rx_path);
1633 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path);
1634
1635 rtw8822c_toggle_igi(rtwdev);
1636}
1637
1638static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
1639 struct rtw_rx_pkt_stat *pkt_stat)
1640{
1641 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1642 u8 l_bnd, u_bnd;
1643 u8 gain_a, gain_b;
1644 s8 rx_power[RTW_RF_PATH_MAX];
1645 s8 min_rx_power = -120;
082a36dc
TSL		 1646 u8 rssi;
1647 int path;
e3037485
YHC		 1648
1649 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status);
1650 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status);
1651 l_bnd = dm_info->cck_gi_l_bnd;
1652 u_bnd = dm_info->cck_gi_u_bnd;
1653 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status);
1654 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status);
1655 if (gain_a < l_bnd)
1656 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1;
1657 else if (gain_a > u_bnd)
1658 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1;
1659 if (gain_b < l_bnd)
e9afa2dc 1660 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1;
e3037485 1661 else if (gain_b > u_bnd)
e9afa2dc 1662 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1;
e3037485
YHC		 1663
1664 rx_power[RF_PATH_A] -= 110;
1665 rx_power[RF_PATH_B] -= 110;
1666
98ab76ef
YHC		 1667 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A];
1668 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B];
1669
082a36dc
TSL		 1670 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
1671 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
1672 dm_info->rssi[path] = rssi;
1673 }
1674
e3037485
YHC		 1675 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
1676 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
1677 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
1678 min_rx_power);
1679}
1680
1681static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
1682 struct rtw_rx_pkt_stat *pkt_stat)
1683{
082a36dc 1684 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
e3037485
YHC		 1685 u8 rxsc, bw;
1686 s8 min_rx_power = -120;
082a36dc
TSL		 1687 s8 rx_evm;
1688 u8 evm_dbm = 0;
1689 u8 rssi;
1690 int path;
e3037485
YHC		 1691
1692 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
1693 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
1694 else
1695 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
1696
1697 if (rxsc >= 9 && rxsc <= 12)
1698 bw = RTW_CHANNEL_WIDTH_40;
1699 else if (rxsc >= 13)
1700 bw = RTW_CHANNEL_WIDTH_80;
1701 else
1702 bw = RTW_CHANNEL_WIDTH_20;
1703
1704 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
1705 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
1706 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
1707 pkt_stat->bw = bw;
1708 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
1709 pkt_stat->rx_power[RF_PATH_B],
1710 min_rx_power);
082a36dc
TSL		 1711
1712 dm_info->curr_rx_rate = pkt_stat->rate;
1713
1714 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
1715 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
1716
1717 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
1718 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
1719
1720 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
1721 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
1722
1723 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
1724 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
1725 dm_info->rssi[path] = rssi;
1726 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
1727 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
1728
1729 rx_evm = pkt_stat->rx_evm[path];
1730
1731 if (rx_evm < 0) {
1732 if (rx_evm == S8_MIN)
1733 evm_dbm = 0;
1734 else
1735 evm_dbm = ((u8)-rx_evm >> 1);
1736 }
1737 dm_info->rx_evm_dbm[path] = evm_dbm;
1738 }
e3037485
YHC		 1739}
1740
1741static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1742 struct rtw_rx_pkt_stat *pkt_stat)
1743{
1744 u8 page;
1745
1746 page = *phy_status & 0xf;
1747
1748 switch (page) {
1749 case 0:
1750 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
1751 break;
1752 case 1:
1753 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
1754 break;
1755 default:
1756 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
1757 return;
1758 }
1759}
1760
1761static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
1762 struct rtw_rx_pkt_stat *pkt_stat,
1763 struct ieee80211_rx_status *rx_status)
1764{
1765 struct ieee80211_hdr *hdr;
1766 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
1767 u8 *phy_status = NULL;
1768
1769 memset(pkt_stat, 0, sizeof(*pkt_stat));
1770
1771 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
1772 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
1773 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
0649ff58
PKS		 1774 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
1775 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
e3037485
YHC		 1776 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
1777 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
1778 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
1779 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
1780 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
1781 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
1782 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
1783 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
1784
1785 /* drv_info_sz is in unit of 8-bytes */
1786 pkt_stat->drv_info_sz *= 8;
1787
1788 /* c2h cmd pkt's rx/phy status is not interested */
1789 if (pkt_stat->is_c2h)
1790 return;
1791
1792 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
1793 pkt_stat->drv_info_sz);
1794 if (pkt_stat->phy_status) {
1795 phy_status = rx_desc + desc_sz + pkt_stat->shift;
1796 query_phy_status(rtwdev, phy_status, pkt_stat);
1797 }
1798
1799 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
1800}
1801
1802static void
1803rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck,
1804 u8 *tx_pwr_ref_ofdm)
1805{
1806 struct rtw_hal *hal = &rtwdev->hal;
1807 u32 txref_cck[2] = {0x18a0, 0x41a0};
1808 u32 txref_ofdm[2] = {0x18e8, 0x41e8};
1809 u8 path;
1810
1811 for (path = 0; path < hal->rf_path_num; path++) {
1812 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1813 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
1814 tx_pwr_ref_cck[path]);
1815 }
1816 for (path = 0; path < hal->rf_path_num; path++) {
1817 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1818 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
1819 tx_pwr_ref_ofdm[path]);
1820 }
1821}
1822
1823static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate,
1824 s8 *diff_idx)
1825{
1826 u32 offset_txagc = 0x3a00;
1827 u8 rate_idx = rate & 0xfc;
1828 u8 pwr_idx[4];
1829 u32 phy_pwr_idx;
1830 int i;
1831
1832 for (i = 0; i < 4; i++)
1833 pwr_idx[i] = diff_idx[i] & 0x7f;
1834
1835 phy_pwr_idx = pwr_idx[0] |
1836 (pwr_idx[1] << 8) |
1837 (pwr_idx[2] << 16) |
1838 (pwr_idx[3] << 24);
1839
1840 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
1841 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD,
1842 phy_pwr_idx);
1843}
1844
1845static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev)
1846{
1847 struct rtw_hal *hal = &rtwdev->hal;
1848 u8 rs, rate, j;
1849 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M],
1850 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]};
1851 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7],
1852 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]};
1853 s8 diff_a, diff_b;
1854 u8 pwr_a, pwr_b;
1855 s8 diff_idx[4];
1856
1857 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm);
1858 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
1859 for (j = 0; j < rtw_rate_size[rs]; j++) {
1860 rate = rtw_rate_section[rs][j];
1861 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate];
1862 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate];
1863 if (rs == 0) {
1864 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0];
1865 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1];
1866 } else {
1867 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0];
1868 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1];
1869 }
1870 diff_idx[rate % 4] = min(diff_a, diff_b);
1871 if (rate % 4 == 3)
1872 rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
1873 diff_idx);
1874 }
1875 }
1876}
1877
1878static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
1879{
1880 u8 ldo_pwr;
1881
1882 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC);
1883 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON;
1884 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr);
1885}
1886
1887static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
1888{
1889 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1890 u32 cck_enable;
1891 u32 cck_fa_cnt;
4136214f 1892 u32 crc32_cnt;
082a36dc 1893 u32 cca32_cnt;
e3037485 1894 u32 ofdm_fa_cnt;
e1cc056c
YHC		 1895 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5;
1896 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail,
1897 fast_fsync, crc8_fail_vhta, mcs_fail_vht;
e3037485
YHC		 1898
1899 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN;
1900 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT);
e1cc056c
YHC		 1901
1902 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1);
1903 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2);
1904 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3);
1905 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4);
1906 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5);
1907
1908 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1);
1909 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2);
1910 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2);
1911 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3);
1912 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4);
1913 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4);
1914 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5);
1915 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5);
1916
1917 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta +
1918 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail;
e3037485
YHC		 1919
1920 dm_info->cck_fa_cnt = cck_fa_cnt;
1921 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1922 dm_info->total_fa_cnt = ofdm_fa_cnt;
1923 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
1924
4136214f
YHC		 1925 crc32_cnt = rtw_read32(rtwdev, 0x2c04);
1926 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
1927 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1928 crc32_cnt = rtw_read32(rtwdev, 0x2c14);
1929 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
1930 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1931 crc32_cnt = rtw_read32(rtwdev, 0x2c10);
1932 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
1933 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1934 crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
1935 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
1936 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1937
082a36dc
TSL		 1938 cca32_cnt = rtw_read32(rtwdev, 0x2c08);
1939 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
1940 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
1941 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
1942 if (cck_enable)
1943 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
1944
e3037485
YHC		 1945 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
1946 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
1947 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
1948 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2);
e0274466
YHC		 1949
1950 /* disable rx clk gating to reset counters */
1951 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
e3037485
YHC		 1952 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
1953 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
e0274466 1954 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
e3037485
YHC		 1955}
1956
1957static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
1958{
1ac3294b
YHC		 1959 struct rtw_iqk_para para = {0};
1960 u8 iqk_chk;
1961 int counter;
1962
1963 para.clear = 1;
1964 rtw_fw_do_iqk(rtwdev, &para);
1965
1966 for (counter = 0; counter < 300; counter++) {
1967 iqk_chk = rtw_read8(rtwdev, REG_RPT_CIP);
1968 if (iqk_chk == 0xaa)
1969 break;
1970 msleep(20);
1971 }
1972 rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
1973
1974 rtw_dbg(rtwdev, RTW_DBG_RFK, "iqk counter=%d\n", counter);
e3037485
YHC		 1975}
1976
4136214f
YHC		 1977/* for coex */
1978static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
1979{
1980 /* enable TBTT nterrupt */
1981 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1982
1983 /* BT report packet sample rate */
1984 /* 0x790[5:0]=0x5 */
1985 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
1986
1987 /* enable BT counter statistics */
1988 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
1989
1990 /* enable PTA (3-wire function form BT side) */
1991 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
1992 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
1993
1994 /* enable PTA (tx/rx signal form WiFi side) */
1995 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
1996 /* wl tx signal to PTA not case EDCCA */
1997 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
1998 /* GNT_BT=1 while select both */
1999 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
2000 /* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */
2001 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
2002
2003 /* to avoid RF parameter error */
2004 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000);
2005}
2006
2007static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
2008{
2009 struct rtw_coex *coex = &rtwdev->coex;
2010 struct rtw_coex_stat *coex_stat = &coex->stat;
2011 struct rtw_efuse *efuse = &rtwdev->efuse;
2012 u32 rf_0x1;
2013
2014 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode)
2015 return;
2016
2017 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode;
2018
2019 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
2020 rf_0x1 = 0x40021;
2021 else
2022 rf_0x1 = 0x40000;
2023
2024 /* BT at S1 for Shared-Ant */
2025 if (efuse->share_ant)
2026 rf_0x1 |= BIT(13);
2027
2028 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
2029
2030 /* WL-S0 2G RF TRX cannot be masked by GNT_BT
2031 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type
2032 * disable:0x1860[3] = 1, enable:0x1860[3] = 0
2033 *
2034 * enable "DAC off if GNT_WL = 0" for non-shared-antenna
2035 * disable 0x1c30[22] = 0,
2036 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1
2037 *
2038 * disable WL-S1 BB chage RF mode if GNT_BT
2039 * since RF TRx mask can do it
2040 */
2041 rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1);
2042 rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0);
2043 rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1);
2044 rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1);
2045
2046 /* disable WL-S0 BB chage RF mode if wifi is at 5G,
2047 * or antenna path is separated
2048 */
2049 if (coex_stat->wl_coex_mode == COEX_WLINK_5G ||
2050 coex->under_5g || !efuse->share_ant) {
2051 if (coex_stat->kt_ver >= 3) {
2052 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
2053 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1);
2054 } else {
2055 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1);
2056 }
2057 } else {
2058 /* shared-antenna */
2059 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
2060 if (coex_stat->kt_ver >= 3)
2061 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0);
2062 }
2063}
2064
2065static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
2066{
2067 rtw_write8_mask(rtwdev, 0x66, BIT(4), 0);
2068 rtw_write8_mask(rtwdev, 0x67, BIT(0), 0);
2069 rtw_write8_mask(rtwdev, 0x42, BIT(3), 0);
2070 rtw_write8_mask(rtwdev, 0x65, BIT(7), 0);
2071 rtw_write8_mask(rtwdev, 0x73, BIT(3), 0);
2072}
2073
2074static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
2075{
2076 struct rtw_coex *coex = &rtwdev->coex;
2077 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
2078 struct rtw_efuse *efuse = &rtwdev->efuse;
2079
2080 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
2081 coex_rfe->ant_switch_polarity = 0;
2082 coex_rfe->ant_switch_exist = false;
2083 coex_rfe->ant_switch_with_bt = false;
2084 coex_rfe->ant_switch_diversity = false;
2085
2086 if (efuse->share_ant)
2087 coex_rfe->wlg_at_btg = true;
2088 else
2089 coex_rfe->wlg_at_btg = false;
2090
2091 /* disable LTE coex in wifi side */
2092 rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0);
2093 rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff);
2094 rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff);
2095}
2096
2097static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
2098{
2099 struct rtw_coex *coex = &rtwdev->coex;
2100 struct rtw_coex_dm *coex_dm = &coex->dm;
2101
2102 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
2103 return;
2104
2105 coex_dm->cur_wl_pwr_lvl = wl_pwr;
2106}
2107
2108static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
2109{
2110 struct rtw_coex *coex = &rtwdev->coex;
2111 struct rtw_coex_dm *coex_dm = &coex->dm;
2112
2113 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
2114 return;
2115
2116 coex_dm->cur_wl_rx_low_gain_en = low_gain;
2117
2118 if (coex_dm->cur_wl_rx_low_gain_en) {
2119 /* set Rx filter corner RCK offset */
2120 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22);
2121 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36);
2122 rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22);
2123 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36);
2124 } else {
2125 /* set Rx filter corner RCK offset */
2126 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20);
2127 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0);
2128 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0);
2129 }
2130}
2131
0bd95573
TEH		 2132static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev,
2133 struct rtw_vif *vif,
2134 struct rtw_bfee *bfee)
2135{
2136 u8 csi_rsc = 0;
2137 u32 tmp6dc;
2138
2139 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
2140
2141 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
2142 BIT_WMAC_USE_NDPARATE |
2143 (csi_rsc << 13);
2144 if (vif->net_type == RTW_NET_AP_MODE)
2145 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12));
2146 else
2147 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12));
2148
2149 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550);
2150}
2151
2152static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev,
2153 struct rtw_vif *vif,
2154 struct rtw_bfee *bfee, bool enable)
2155{
2156 if (enable)
2157 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee);
2158 else
2159 rtw_bf_remove_bfee_su(rtwdev, bfee);
2160}
2161
2162static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
2163 struct rtw_vif *vif,
2164 struct rtw_bfee *bfee, bool enable)
2165{
2166 if (enable)
2167 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
2168 else
2169 rtw_bf_remove_bfee_mu(rtwdev, bfee);
2170}
2171
2172static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
2173 struct rtw_bfee *bfee, bool enable)
2174{
2175 if (bfee->role == RTW_BFEE_SU)
2176 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
2177 else if (bfee->role == RTW_BFEE_MU)
2178 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
2179 else
2180 rtw_warn(rtwdev, "wrong bfee role\n");
2181}
2182
5227c2ee
TEH		 2183struct dpk_cfg_pair {
2184 u32 addr;
2185 u32 bitmask;
2186 u32 data;
2187};
2188
2189void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
2190 const struct rtw_table *tbl)
2191{
2192 const struct dpk_cfg_pair *p = tbl->data;
2193 const struct dpk_cfg_pair *end = p + tbl->size / 3;
2194
2195 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3);
2196
2197 for (; p < end; p++)
2198 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data);
2199}
2200
2201static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k)
2202{
2203 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2204
2205 if (is_before_k) {
2206 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
2207 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
2208 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1);
2209 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77);
2210 } else {
2211 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD,
2212 dpk_info->gnt_value);
2213 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
2214 }
2215}
2216
2217static void
2218rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num,
2219 struct rtw_backup_info *bckp)
2220{
2221 rtw_restore_reg(rtwdev, bckp, reg_num);
2222 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2223 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4);
2224}
2225
2226static void
2227rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg,
2228 u32 reg_num, struct rtw_backup_info *bckp)
2229{
2230 u32 i;
2231
2232 for (i = 0; i < reg_num; i++) {
2233 bckp[i].len = 4;
2234 bckp[i].reg = reg[i];
2235 bckp[i].val = rtw_read32(rtwdev, reg[i]);
2236 }
2237}
2238
2239static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev,
2240 u32 *rf_reg,
2241 u32 rf_reg_bak[][2])
2242{
2243 u32 i;
2244
2245 for (i = 0; i < DPK_RF_REG_NUM; i++) {
2246 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A,
2247 rf_reg[i], RFREG_MASK);
2248 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B,
2249 rf_reg[i], RFREG_MASK);
2250 }
2251}
2252
2253static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev,
2254 u32 *rf_reg,
2255 u32 rf_reg_bak[][2])
2256{
2257 u32 i;
2258
2259 for (i = 0; i < DPK_RF_REG_NUM; i++) {
2260 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK,
2261 rf_reg_bak[i][RF_PATH_A]);
2262 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK,
2263 rf_reg_bak[i][RF_PATH_B]);
2264 }
2265}
2266
2267static void rtw8822c_dpk_information(struct rtw_dev *rtwdev)
2268{
2269 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2270 u32 reg;
2271 u8 band_shift;
2272
2273 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
2274
2275 band_shift = FIELD_GET(BIT(16), reg);
2276 dpk_info->dpk_band = 1 << band_shift;
2277 dpk_info->dpk_ch = FIELD_GET(0xff, reg);
2278 dpk_info->dpk_bw = FIELD_GET(0x3000, reg);
2279}
2280
2281static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path)
2282{
2283 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
2284 udelay(5);
2285 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
2286 usleep_range(600, 610);
2287 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
2288}
2289
2290static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
2291{
2292 u16 dc_i, dc_q;
2293 u8 corr_val, corr_idx;
2294
2295 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
2296 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
2297 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
2298
2299 if (dc_i & BIT(11))
2300 dc_i = 0x1000 - dc_i;
2301 if (dc_q & BIT(11))
2302 dc_q = 0x1000 - dc_q;
2303
2304 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2305 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
2306 corr_val = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
2307
2308 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65)
2309 return 1;
2310 else
2311 return 0;
2312
2313}
2314
2315static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev)
2316{
2317 u8 reg_a, reg_b;
2318 u16 count = 0;
2319
2320 rtw_write8(rtwdev, 0x522, 0xff);
2321 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2);
2322
2323 do {
2324 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000);
2325 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
2326 udelay(2);
2327 count++;
2328 } while ((reg_a == 2 || reg_b == 2) && count < 2500);
2329}
2330
2331static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev)
2332{
2333 rtw8822c_dpk_tx_pause(rtwdev);
2334 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl);
2335}
2336
2337static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk)
2338{
2339 if (is_do_dpk)
2340 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl);
2341 else
2342 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl);
2343}
2344
2345static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev)
2346{
2347 u8 path;
2348
2349 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
2350 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
2351 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
2352 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
2353 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
2354 else
2355 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
2356 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
2357 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
2358 }
2359 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2360 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b);
2361 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347);
2362}
2363
2364static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path)
2365{
2366 u32 ori_txbb;
2367
2368 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
2369 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK);
2370
2371 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
2372 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
2373 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0);
2374 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);
2375
2376 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
2377 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1);
2378 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
2379 } else {
2380 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
2381 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
2382 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
2383 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
2384 }
2385
2386 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
2387 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
2388 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
2389
2390 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80)
2391 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
2392 else
2393 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
2394
2395 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
2396
2397 usleep_range(100, 110);
2398
2399 return ori_txbb & 0x1f;
2400}
2401
2402static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path)
2403{
2404 u16 cmd;
2405 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
2406
2407 switch (action) {
2408 case RTW_DPK_GAIN_LOSS:
2409 cmd = 0x14 + path;
2410 break;
2411 case RTW_DPK_DO_DPK:
2412 cmd = 0x16 + path + bw;
2413 break;
2414 case RTW_DPK_DPK_ON:
2415 cmd = 0x1a + path;
2416 break;
2417 case RTW_DPK_DAGC:
2418 cmd = 0x1c + path + bw;
2419 break;
2420 default:
2421 return 0;
2422 }
2423
2424 return (cmd << 8) | 0x48;
2425}
2426
2427static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action)
2428{
2429 u16 dpk_cmd;
2430 u8 result = 0;
2431
2432 rtw8822c_dpk_set_gnt_wl(rtwdev, true);
2433
2434 if (action == RTW_DPK_CAL_PWR) {
2435 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1);
2436 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0);
2437 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
2438 msleep(10);
2439 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
2440 result = 1;
2441 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
2442 }
2443 } else {
2444 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2445 0x8 | (path << 1));
2446 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
2447
2448 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path);
2449 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd);
2450 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1);
2451 msleep(10);
2452 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
2453 result = 1;
2454 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
2455 }
2456 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2457 0x8 | (path << 1));
2458 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
2459 }
2460
2461 rtw8822c_dpk_set_gnt_wl(rtwdev, false);
2462
2463 rtw_write8(rtwdev, 0x1b10, 0x0);
2464
2465 return result;
2466}
2467
2468static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path)
2469{
2470 u16 dgain;
2471
2472 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2473 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0);
2474
2475 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
2476
2477 return dgain;
2478}
2479
2480static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path)
2481{
2482 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
2483 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
2484 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
2485 udelay(15);
2486
2487 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
2488}
2489
2490static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path)
2491{
2492 u32 i_val, q_val;
2493
2494 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
2495 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
2496 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001);
2497 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
2498 rtw_write32(rtwdev, 0x1b4c, 0x00080000);
2499
2500 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD);
2501 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD);
2502
2503 if (i_val & BIT(15))
2504 i_val = 0x10000 - i_val;
2505 if (q_val & BIT(15))
2506 q_val = 0x10000 - q_val;
2507
2508 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
2509
2510 return i_val * i_val + q_val * q_val;
2511}
2512
2513static u32 rtw8822c_psd_log2base(u32 val)
2514{
2515 u32 tmp, val_integerd_b, tindex;
2516 u32 result, val_fractiond_b;
2517 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174,
2518 151, 132, 115, 100, 86, 74, 62, 51,
2519 42, 32, 23, 15, 7, 0};
2520
2521 if (val == 0)
2522 return 0;
2523
2524 val_integerd_b = __fls(val) + 1;
2525
2526 tmp = (val * 100) / (1 << val_integerd_b);
2527 tindex = tmp / 5;
2528
2529 if (tindex >= ARRAY_SIZE(table_fraction))
2530 tindex = ARRAY_SIZE(table_fraction) - 1;
2531
2532 val_fractiond_b = table_fraction[tindex];
2533
2534 result = val_integerd_b * 100 - val_fractiond_b;
2535
2536 return result;
2537}
2538
2539static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path)
2540{
2541 u8 result;
2542
2543 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2544 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1);
2545 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000);
2546
2547 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
2548
2549 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
2550
2551 return result;
2552}
2553
2554static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path,
2555 u8 limited_pga)
2556{
2557 u8 result = 0;
2558 u16 dgain;
2559
2560 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
2561 dgain = rtw8822c_dpk_dgain_read(rtwdev, path);
2562
2563 if (dgain > 1535 && !limited_pga)
2564 return RTW_DPK_GAIN_LESS;
2565 else if (dgain < 768 && !limited_pga)
2566 return RTW_DPK_GAIN_LARGE;
2567 else
2568 return result;
2569}
2570
2571static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path)
2572{
2573 u32 loss, loss_db;
2574
2575 loss = rtw8822c_dpk_pas_read(rtwdev, path);
2576 if (loss < 0x4000000)
2577 return RTW_DPK_GL_LESS;
2578 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870;
2579
2580 if (loss_db > 1000)
2581 return RTW_DPK_GL_LARGE;
2582 else if (loss_db < 250)
2583 return RTW_DPK_GL_LESS;
2584 else
2585 return RTW_DPK_AGC_OUT;
2586}
2587
2588struct rtw8822c_dpk_data {
2589 u8 txbb;
2590 u8 pga;
2591 u8 limited_pga;
2592 u8 agc_cnt;
2593 bool loss_only;
2594 bool gain_only;
2595 u8 path;
2596};
2597
2598static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev,
2599 struct rtw8822c_dpk_data *data)
2600{
2601 u8 state;
2602
2603 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN,
2604 BIT_GAIN_TXBB);
2605 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC,
2606 BIT_RXAGC);
2607
2608 if (data->loss_only) {
2609 state = RTW_DPK_LOSS_CHECK;
2610 goto check_end;
2611 }
2612
2613 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path,
2614 data->limited_pga);
2615 if (state == RTW_DPK_GAIN_CHECK && data->gain_only)
2616 state = RTW_DPK_AGC_OUT;
2617 else if (state == RTW_DPK_GAIN_CHECK)
2618 state = RTW_DPK_LOSS_CHECK;
2619
2620check_end:
2621 data->agc_cnt++;
2622 if (data->agc_cnt >= 6)
2623 state = RTW_DPK_AGC_OUT;
2624
2625 return state;
2626}
2627
2628static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev,
2629 struct rtw8822c_dpk_data *data)
2630{
2631 u8 pga = data->pga;
2632
2633 if (pga > 0xe)
2634 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
2635 else if (pga > 0xb && pga < 0xf)
2636 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
2637 else if (pga < 0xc)
2638 data->limited_pga = 1;
2639
2640 return RTW_DPK_GAIN_CHECK;
2641}
2642
2643static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev,
2644 struct rtw8822c_dpk_data *data)
2645{
2646 u8 pga = data->pga;
2647
2648 if (pga < 0xc)
2649 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
2650 else if (pga > 0xb && pga < 0xf)
2651 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
2652 else if (pga > 0xe)
2653 data->limited_pga = 1;
2654
2655 return RTW_DPK_GAIN_CHECK;
2656}
2657
2658static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev,
2659 struct rtw8822c_dpk_data *data, u8 is_large)
2660{
2661 u8 txbb_bound[] = {0x1f, 0};
2662
2663 if (data->txbb == txbb_bound[is_large])
2664 return RTW_DPK_AGC_OUT;
2665
2666 if (is_large == 1)
2667 data->txbb -= 2;
2668 else
2669 data->txbb += 3;
2670
2671 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb);
2672 data->limited_pga = 0;
2673
2674 return RTW_DPK_GAIN_CHECK;
2675}
2676
2677static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev,
2678 struct rtw8822c_dpk_data *data)
2679{
2680 return rtw8822c_gl_state(rtwdev, data, 1);
2681}
2682
2683static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev,
2684 struct rtw8822c_dpk_data *data)
2685{
2686 return rtw8822c_gl_state(rtwdev, data, 0);
2687}
2688
2689static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev,
2690 struct rtw8822c_dpk_data *data)
2691{
2692 u8 path = data->path;
2693 u8 state;
2694
2695 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS);
2696 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path);
2697
2698 return state;
2699}
2700
2701static u8 (*dpk_state[])(struct rtw_dev *rtwdev,
2702 struct rtw8822c_dpk_data *data) = {
2703 rtw8822c_gain_check_state, rtw8822c_gain_large_state,
2704 rtw8822c_gain_less_state, rtw8822c_gl_large_state,
2705 rtw8822c_gl_less_state, rtw8822c_loss_check_state };
2706
2707static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path,
2708 bool gain_only, bool loss_only)
2709{
2710 struct rtw8822c_dpk_data data = {0};
2711 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data);
2712 u8 state = RTW_DPK_GAIN_CHECK;
2713
2714 data.loss_only = loss_only;
2715 data.gain_only = gain_only;
2716 data.path = path;
2717
2718 for (;;) {
2719 func = dpk_state[state];
2720 state = func(rtwdev, &data);
2721 if (state == RTW_DPK_AGC_OUT)
2722 break;
2723 }
2724
2725 return data.txbb;
2726}
2727
2728static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev,
2729 u16 coef_i, u16 coef_q)
2730{
2731 if (coef_i == 0x1000 || coef_i == 0x0fff ||
2732 coef_q == 0x1000 || coef_q == 0x0fff)
0d32f5d9
YHC		 2733 return true;
2734
2735 return false;
5227c2ee
TEH		 2736}
2737
2738static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev)
2739{
2740 u32 reg = 0;
2741 u16 coef_i = 0, coef_q = 0;
2742
2743 reg = rtw_read32(rtwdev, REG_STAT_RPT);
2744
2745 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff;
2746 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
2747
2748 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1;
2749
2750 reg = (coef_i << 16) | coef_q;
2751
2752 return reg;
2753}
2754
2755static const u32 rtw8822c_dpk_get_coef_tbl[] = {
2756 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0,
2757 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0,
2758 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0,
2759 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0,
2760};
2761
2762static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path)
2763{
2764 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2765 int i;
2766
2767 for (i = 0; i < 20; i++) {
2768 rtw_write32(rtwdev, REG_RXSRAM_CTL,
2769 rtw8822c_dpk_get_coef_tbl[i]);
2770 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev);
2771 }
2772}
2773
2774static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path)
2775{
2776 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
2777
2778 if (path == RF_PATH_A) {
2779 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0);
2780 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080);
2781 } else if (path == RF_PATH_B) {
2782 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1);
2783 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080);
2784 }
2785
2786 rtw8822c_dpk_coef_tbl_apply(rtwdev, path);
2787}
2788
2789static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path)
2790{
2791 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2792 u8 addr, result = 1;
2793 u16 coef_i, coef_q;
2794
2795 for (addr = 0; addr < 20; addr++) {
2796 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]);
2797 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]);
2798
2799 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) {
2800 result = 0;
2801 break;
2802 }
2803 }
2804 return result;
2805}
2806
2807static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result)
2808{
2809 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2810 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64};
2811 u32 coef;
2812 u8 addr;
2813
2814 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
2815 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2816
2817 for (addr = 0; addr < 20; addr++) {
2818 if (result == 0) {
2819 if (addr == 3)
2820 coef = 0x04001fff;
2821 else
2822 coef = 0x00001fff;
2823 } else {
2824 coef = dpk_info->coef[path][addr];
2825 }
2826 rtw_write32(rtwdev, reg[path] + addr * 4, coef);
2827 }
2828}
2829
2830static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc,
2831 u8 path, u8 result)
2832{
2833 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2834
2835 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2836
2837 if (result)
2838 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6));
2839 else
2840 rtw_write8(rtwdev, REG_DPD_AGC, 0x00);
2841
2842 dpk_info->result[path] = result;
2843 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
2844
2845 rtw8822c_dpk_coef_write(rtwdev, path, result);
2846}
2847
2848static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path)
2849{
2850 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2851 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2;
2852
2853 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path);
2854 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC);
2855
2856 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
2857 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
2858 rtw8822c_dpk_dgain_read(rtwdev, path);
2859
2860 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) {
2861 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
2862 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
2863 rtw8822c_dpk_dc_corr_check(rtwdev, path);
2864 }
2865
2866 t1 = rtw8822c_dpk_thermal_read(rtwdev, path);
2867 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true);
2868 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path);
2869
2870 if (tx_bb < tx_agc_search)
2871 tx_bb = 0;
2872 else
2873 tx_bb = tx_bb - tx_agc_search;
2874
2875 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb);
2876
2877 tx_agc = ori_txagc - (ori_txbb - tx_bb);
2878
2879 t2 = rtw8822c_dpk_thermal_read(rtwdev, path);
2880
2881 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1);
2882
2883 return tx_agc;
2884}
2885
2886static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path)
2887{
2888 u8 result;
2889
2890 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK);
2891
2892 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2893
2894 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26));
2895
2896 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14);
2897
2898 rtw8822c_dpk_get_coef(rtwdev, path);
2899
2900 return result;
2901}
2902
2903static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path)
2904{
2905 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2906 u32 tmp_gs = 0;
2907
2908 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2909 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0);
2910 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
2911 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
2912 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1);
2913 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2914 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf);
2915
2916 if (path == RF_PATH_A) {
2917 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
2918 0x1066680);
2919 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1);
2920 } else {
2921 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
2922 0x1066680);
2923 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1);
2924 }
2925
2926 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) {
2927 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310);
2928 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310);
2929 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db);
2930 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db);
2931 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
2932 rtw_write32(rtwdev, REG_DPD_CTL15,
2933 0x05020000 | (BIT(path) << 28));
2934 } else {
2935 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c);
2936 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c);
2937 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14);
2938 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14);
2939 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
2940 rtw_write32(rtwdev, REG_DPD_CTL15,
2941 0x05020008 | (BIT(path) << 28));
2942 }
2943
2944 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path);
2945
2946 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR);
2947
2948 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0);
2949 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2950 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
2951 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0);
2952 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2953
2954 if (path == RF_PATH_A)
2955 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b);
2956 else
2957 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b);
2958
2959 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
2960
2961 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN);
2962 tmp_gs = (tmp_gs * 910) >> 10;
2963 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10);
2964
2965 if (path == RF_PATH_A)
2966 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs);
2967 else
2968 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs);
2969
2970 dpk_info->dpk_gs[path] = tmp_gs;
2971}
2972
1f592108 2973static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev)
5227c2ee
TEH		 2974{
2975 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2976 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58};
2977 u32 i_scaling;
2978 u8 path;
2979
2980 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
2981 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2982 rtw_write32(rtwdev, REG_NCTL0, 0x00001148);
2983 rtw_write32(rtwdev, REG_NCTL0, 0x00001149);
2984
2985 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55);
2986
2987 rtw_write8(rtwdev, 0x1b10, 0x0);
2988 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
2989
2990 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
2991 i_scaling = 0x16c00 / dpk_info->dpk_gs[path];
2992
2993 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD,
2994 i_scaling);
2995 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
2996 GENMASK(31, 28), 0x9);
2997 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
2998 GENMASK(31, 28), 0x1);
2999 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3000 GENMASK(31, 28), 0x0);
3001 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path],
3002 BIT(14), 0x0);
3003 }
3004}
3005
3006static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path)
3007{
3008 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3009
3010 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
3011
3012 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3013 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3014
3015 if (test_bit(path, dpk_info->dpk_path_ok))
3016 rtw8822c_dpk_cal_gs(rtwdev, path);
3017}
3018
3019static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail,
3020 u32 dpk_txagc, u8 path)
3021{
3022 bool result;
3023
3024 if (!is_fail) {
3025 if (rtw8822c_dpk_coef_read(rtwdev, path))
3026 result = true;
3027 else
3028 result = false;
3029 } else {
3030 result = false;
3031 }
3032
3033 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result);
3034
3035 return result;
3036}
3037
3038static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev)
3039{
3040 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3041 u8 path;
3042
3043 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3044 clear_bit(path, dpk_info->dpk_path_ok);
3045 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3046 0x8 | (path << 1));
3047 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0);
3048
3049 dpk_info->dpk_txagc[path] = 0;
3050 dpk_info->result[path] = 0;
3051 dpk_info->dpk_gs[path] = 0x5b;
3052 dpk_info->pre_pwsf[path] = 0;
3053 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev,
3054 path);
3055 }
3056}
3057
3058static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path)
3059{
3060 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3061 u32 dpk_txagc;
3062 u8 dpk_fail;
3063
3064 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path);
3065
3066 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path);
3067
3068 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path);
3069
3070 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path))
3071 rtw_err(rtwdev, "failed to do dpk calibration\n");
3072
3073 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path);
3074
3075 if (dpk_info->result[path])
3076 set_bit(path, dpk_info->dpk_path_ok);
3077}
3078
3079static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev)
3080{
3081 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A);
3082 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B);
3083 rtw8822c_dpk_on(rtwdev, RF_PATH_A);
3084 rtw8822c_dpk_on(rtwdev, RF_PATH_B);
3085 rtw8822c_dpk_cal_coef1(rtwdev);
3086}
3087
3088static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev)
3089{
3090 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3091 u32 mask = BIT(15) | BIT(14);
3092
3093 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3094
3095 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN,
3096 dpk_info->is_dpk_pwr_on);
3097 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN,
3098 dpk_info->is_dpk_pwr_on);
3099
3100 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) {
3101 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0);
3102 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]);
3103 }
3104 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) {
3105 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0);
3106 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]);
3107 }
3108}
3109
3110static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev)
3111{
3112 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3113 u8 path;
3114
3115 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) &&
3116 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) &&
3117 dpk_info->dpk_ch == 0)
3118 return;
3119
3120 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3121 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3122 0x8 | (path << 1));
3123 if (dpk_info->dpk_band == RTW_BAND_2G)
3124 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
3125 else
3126 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
3127
3128 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
3129
3130 rtw8822c_dpk_coef_write(rtwdev, path,
3131 test_bit(path, dpk_info->dpk_path_ok));
3132
3133 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
3134
3135 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3136
3137 if (path == RF_PATH_A)
3138 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
3139 dpk_info->dpk_gs[path]);
3140 else
3141 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
3142 dpk_info->dpk_gs[path]);
3143 }
3144 rtw8822c_dpk_cal_coef1(rtwdev);
3145}
3146
3147static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev)
3148{
3149 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3150 u8 channel;
3151
3152 dpk_info->is_reload = false;
3153
3154 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff);
3155
3156 if (channel == dpk_info->dpk_ch) {
3157 rtw_dbg(rtwdev, RTW_DBG_RFK,
3158 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch);
3159 rtw8822c_dpk_reload_data(rtwdev);
3160 dpk_info->is_reload = true;
3161 }
3162
3163 return dpk_info->is_reload;
3164}
3165
3166static void rtw8822c_do_dpk(struct rtw_dev *rtwdev)
3167{
3168 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3169 struct rtw_backup_info bckp[DPK_BB_REG_NUM];
3170 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM];
3171 u32 bb_reg[DPK_BB_REG_NUM] = {
3172 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864,
3173 0x4164, 0x180c, 0x410c, 0x186c, 0x416c,
3174 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4};
3175 u32 rf_reg[DPK_RF_REG_NUM] = {
3176 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde};
3177 u8 path;
3178
3179 if (!dpk_info->is_dpk_pwr_on) {
3180 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n");
3181 return;
3182 } else if (rtw8822c_dpk_reload(rtwdev)) {
3183 return;
3184 }
3185
3186 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++)
3187 ewma_thermal_init(&dpk_info->avg_thermal[path]);
3188
3189 rtw8822c_dpk_information(rtwdev);
3190
3191 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp);
3192 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup);
3193
3194 rtw8822c_dpk_mac_bb_setting(rtwdev);
3195 rtw8822c_dpk_afe_setting(rtwdev, true);
3196 rtw8822c_dpk_pre_setting(rtwdev);
3197 rtw8822c_dpk_result_reset(rtwdev);
3198 rtw8822c_dpk_path_select(rtwdev);
3199 rtw8822c_dpk_afe_setting(rtwdev, false);
3200 rtw8822c_dpk_enable_disable(rtwdev);
3201
3202 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup);
3203 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
3204 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3205 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp);
3206}
3207
f27b886d
YHC		 3208static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev)
3209{
3210 rtw8822c_do_iqk(rtwdev);
3211 rtw8822c_do_dpk(rtwdev);
3212}
3213
1f592108 3214static void rtw8822c_dpk_track(struct rtw_dev *rtwdev)
5227c2ee
TEH		 3215{
3216 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3217 u8 path;
3218 u8 thermal_value[DPK_RF_PATH_NUM] = {0};
3219 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM];
3220
3221 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0)
3222 return;
3223
3224 for (path = 0; path < DPK_RF_PATH_NUM; path++) {
3225 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path);
3226 ewma_thermal_add(&dpk_info->avg_thermal[path],
3227 thermal_value[path]);
3228 thermal_value[path] =
3229 ewma_thermal_read(&dpk_info->avg_thermal[path]);
3230 delta_dpk[path] = dpk_info->thermal_dpk[path] -
3231 thermal_value[path];
3232 offset[path] = delta_dpk[path] -
3233 dpk_info->thermal_dpk_delta[path];
3234 offset[path] &= 0x7f;
3235
3236 if (offset[path] != dpk_info->pre_pwsf[path]) {
3237 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3238 0x8 | (path << 1));
3239 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),
3240 offset[path]);
3241 dpk_info->pre_pwsf[path] = offset[path];
3242 }
3243 }
3244}
3245
479c4ee9
TEH		 3246static const struct rtw_phy_cck_pd_reg
3247rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = {
3248 {
3249 {0x1ac8, 0x00ff, 0x1ad0, 0x01f},
3250 {0x1ac8, 0xff00, 0x1ad0, 0x3e0}
3251 },
3252 {
3253 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000},
3254 {0x1acc, 0xff00, 0x1ad0, 0x3E000000}
3255 },
3256};
3257
3258#define RTW_CCK_PD_MAX 255
3259#define RTW_CCK_CS_MAX 31
3260#define RTW_CCK_CS_ERR1 27
3261#define RTW_CCK_CS_ERR2 29
3262static void
3263rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev,
3264 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx)
3265{
3266 u32 pd, cs;
3267
3268 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX))
3269 return;
3270
3271 pd = rtw_read32_mask(rtwdev,
3272 rtw8822c_cck_pd_reg[bw][nrx].reg_pd,
3273 rtw8822c_cck_pd_reg[bw][nrx].mask_pd);
3274 cs = rtw_read32_mask(rtwdev,
3275 rtw8822c_cck_pd_reg[bw][nrx].reg_cs,
3276 rtw8822c_cck_pd_reg[bw][nrx].mask_cs);
3277 pd += pd_diff;
3278 cs += cs_diff;
3279 if (pd > RTW_CCK_PD_MAX)
3280 pd = RTW_CCK_PD_MAX;
3281 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2)
3282 cs++;
3283 else if (cs > RTW_CCK_CS_MAX)
3284 cs = RTW_CCK_CS_MAX;
3285 rtw_write32_mask(rtwdev,
3286 rtw8822c_cck_pd_reg[bw][nrx].reg_pd,
3287 rtw8822c_cck_pd_reg[bw][nrx].mask_pd,
3288 pd);
3289 rtw_write32_mask(rtwdev,
3290 rtw8822c_cck_pd_reg[bw][nrx].reg_cs,
3291 rtw8822c_cck_pd_reg[bw][nrx].mask_cs,
3292 cs);
3293}
3294
3295static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
3296{
3297 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
18a0696e
TEH		 3298 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8};
3299 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4};
479c4ee9
TEH		 3300 u8 cur_lvl;
3301 u8 nrx, bw;
3302
3303 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
3304 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
3305
3306 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl)
3307 return;
3308
3309 cur_lvl = dm_info->cck_pd_lv[bw][nrx];
3310
3311 /* update cck pd info */
3312 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
3313
3314 rtw8822c_phy_cck_pd_set_reg(rtwdev,
3315 pd_lvl[new_lvl] - pd_lvl[cur_lvl],
3316 cs_lvl[new_lvl] - cs_lvl[cur_lvl],
3317 bw, nrx);
3318 dm_info->cck_pd_lv[bw][nrx] = new_lvl;
3319}
3320
c97ee3e0
TEH		 3321#define PWR_TRACK_MASK 0x7f
3322static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path)
3323{
3324 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3325
3326 switch (rf_path) {
3327 case RF_PATH_A:
3328 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK,
3329 dm_info->delta_power_index[rf_path]);
3330 break;
3331 case RF_PATH_B:
3332 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK,
3333 dm_info->delta_power_index[rf_path]);
3334 break;
3335 default:
3336 break;
3337 }
3338}
3339
3340static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev,
3341 struct rtw_swing_table *swing_table,
3342 u8 path)
3343{
3344 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3345 u8 thermal_value, delta;
3346
3347 if (rtwdev->efuse.thermal_meter[path] == 0xff)
3348 return;
3349
3350 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e);
3351
3352 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path);
3353
3354 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path);
3355
3356 dm_info->delta_power_index[path] =
3357 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path,
3358 delta);
3359
3360 rtw8822c_pwrtrack_set(rtwdev, path);
3361}
3362
3363static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev)
3364{
3365 struct rtw_swing_table swing_table;
3366 u8 i;
3367
3368 rtw_phy_config_swing_table(rtwdev, &swing_table);
3369
3370 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
3371 rtw8822c_pwr_track_path(rtwdev, &swing_table, i);
3372
3373 if (rtw_phy_pwrtrack_need_iqk(rtwdev))
3374 rtw8822c_do_iqk(rtwdev);
3375}
3376
3377static void rtw8822c_pwr_track(struct rtw_dev *rtwdev)
3378{
3379 struct rtw_efuse *efuse = &rtwdev->efuse;
3380 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3381
3382 if (efuse->power_track_type != 0)
3383 return;
3384
3385 if (!dm_info->pwr_trk_triggered) {
3386 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
3387 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00);
3388 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
3389
3390 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
3391 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00);
3392 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
3393
3394 dm_info->pwr_trk_triggered = true;
3395 return;
3396 }
3397
3398 __rtw8822c_pwr_track(rtwdev);
3399 dm_info->pwr_trk_triggered = false;
3400}
3401
e3037485
YHC		 3402static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = {
3403 {0x0086,
3404 RTW_PWR_CUT_ALL_MSK,
3405 RTW_PWR_INTF_SDIO_MSK,
3406 RTW_PWR_ADDR_SDIO,
3407 RTW_PWR_CMD_WRITE, BIT(0), 0},
3408 {0x0086,
3409 RTW_PWR_CUT_ALL_MSK,
3410 RTW_PWR_INTF_SDIO_MSK,
3411 RTW_PWR_ADDR_SDIO,
3412 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
3413 {0x002E,
3414 RTW_PWR_CUT_ALL_MSK,
3415 RTW_PWR_INTF_ALL_MSK,
3416 RTW_PWR_ADDR_MAC,
3417 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3418 {0x002D,
3419 RTW_PWR_CUT_ALL_MSK,
3420 RTW_PWR_INTF_ALL_MSK,
3421 RTW_PWR_ADDR_MAC,
3422 RTW_PWR_CMD_WRITE, BIT(0), 0},
3423 {0x007F,
3424 RTW_PWR_CUT_ALL_MSK,
3425 RTW_PWR_INTF_ALL_MSK,
3426 RTW_PWR_ADDR_MAC,
3427 RTW_PWR_CMD_WRITE, BIT(7), 0},
3428 {0x004A,
3429 RTW_PWR_CUT_ALL_MSK,
3430 RTW_PWR_INTF_USB_MSK,
3431 RTW_PWR_ADDR_MAC,
3432 RTW_PWR_CMD_WRITE, BIT(0), 0},
3433 {0x0005,
3434 RTW_PWR_CUT_ALL_MSK,
3435 RTW_PWR_INTF_ALL_MSK,
3436 RTW_PWR_ADDR_MAC,
3437 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
3438 {0xFFFF,
3439 RTW_PWR_CUT_ALL_MSK,
3440 RTW_PWR_INTF_ALL_MSK,
3441 0,
3442 RTW_PWR_CMD_END, 0, 0},
3443};
3444
3445static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = {
3446 {0x0000,
3447 RTW_PWR_CUT_ALL_MSK,
3448 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3449 RTW_PWR_ADDR_MAC,
3450 RTW_PWR_CMD_WRITE, BIT(5), 0},
3451 {0x0005,
3452 RTW_PWR_CUT_ALL_MSK,
3453 RTW_PWR_INTF_ALL_MSK,
3454 RTW_PWR_ADDR_MAC,
3455 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
3456 {0x0075,
3457 RTW_PWR_CUT_ALL_MSK,
3458 RTW_PWR_INTF_PCI_MSK,
3459 RTW_PWR_ADDR_MAC,
3460 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3461 {0x0006,
3462 RTW_PWR_CUT_ALL_MSK,
3463 RTW_PWR_INTF_ALL_MSK,
3464 RTW_PWR_ADDR_MAC,
3465 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
3466 {0x0075,
3467 RTW_PWR_CUT_ALL_MSK,
3468 RTW_PWR_INTF_PCI_MSK,
3469 RTW_PWR_ADDR_MAC,
3470 RTW_PWR_CMD_WRITE, BIT(0), 0},
3471 {0xFF1A,
3472 RTW_PWR_CUT_ALL_MSK,
3473 RTW_PWR_INTF_USB_MSK,
3474 RTW_PWR_ADDR_MAC,
3475 RTW_PWR_CMD_WRITE, 0xFF, 0},
3476 {0x002E,
3477 RTW_PWR_CUT_ALL_MSK,
3478 RTW_PWR_INTF_ALL_MSK,
3479 RTW_PWR_ADDR_MAC,
3480 RTW_PWR_CMD_WRITE, BIT(3), 0},
3481 {0x0006,
3482 RTW_PWR_CUT_ALL_MSK,
3483 RTW_PWR_INTF_ALL_MSK,
3484 RTW_PWR_ADDR_MAC,
3485 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3486 {0x0005,
3487 RTW_PWR_CUT_ALL_MSK,
3488 RTW_PWR_INTF_ALL_MSK,
3489 RTW_PWR_ADDR_MAC,
3490 RTW_PWR_CMD_WRITE, BIT(7), 0},
3491 {0x0005,
3492 RTW_PWR_CUT_ALL_MSK,
3493 RTW_PWR_INTF_ALL_MSK,
3494 RTW_PWR_ADDR_MAC,
3495 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
3496 {0x0005,
3497 RTW_PWR_CUT_ALL_MSK,
3498 RTW_PWR_INTF_ALL_MSK,
3499 RTW_PWR_ADDR_MAC,
3500 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3501 {0x0005,
3502 RTW_PWR_CUT_ALL_MSK,
3503 RTW_PWR_INTF_ALL_MSK,
3504 RTW_PWR_ADDR_MAC,
3505 RTW_PWR_CMD_POLLING, BIT(0), 0},
3506 {0x0074,
3507 RTW_PWR_CUT_ALL_MSK,
3508 RTW_PWR_INTF_PCI_MSK,
3509 RTW_PWR_ADDR_MAC,
3510 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
3511 {0x0071,
3512 RTW_PWR_CUT_ALL_MSK,
3513 RTW_PWR_INTF_PCI_MSK,
3514 RTW_PWR_ADDR_MAC,
3515 RTW_PWR_CMD_WRITE, BIT(4), 0},
3516 {0x0062,
3517 RTW_PWR_CUT_ALL_MSK,
3518 RTW_PWR_INTF_PCI_MSK,
3519 RTW_PWR_ADDR_MAC,
3520 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
3521 (BIT(7) | BIT(6) | BIT(5))},
3522 {0x0061,
3523 RTW_PWR_CUT_ALL_MSK,
3524 RTW_PWR_INTF_PCI_MSK,
3525 RTW_PWR_ADDR_MAC,
3526 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
3527 {0x001F,
3528 RTW_PWR_CUT_ALL_MSK,
3529 RTW_PWR_INTF_ALL_MSK,
3530 RTW_PWR_ADDR_MAC,
3531 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},
3532 {0x00EF,
3533 RTW_PWR_CUT_ALL_MSK,
3534 RTW_PWR_INTF_ALL_MSK,
3535 RTW_PWR_ADDR_MAC,
3536 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},
3537 {0x1045,
3538 RTW_PWR_CUT_ALL_MSK,
3539 RTW_PWR_INTF_ALL_MSK,
3540 RTW_PWR_ADDR_MAC,
3541 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
3542 {0x0010,
3543 RTW_PWR_CUT_ALL_MSK,
3544 RTW_PWR_INTF_ALL_MSK,
3545 RTW_PWR_ADDR_MAC,
3546 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3547 {0xFFFF,
3548 RTW_PWR_CUT_ALL_MSK,
3549 RTW_PWR_INTF_ALL_MSK,
3550 0,
3551 RTW_PWR_CMD_END, 0, 0},
3552};
3553
3554static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = {
3555 {0x0093,
3556 RTW_PWR_CUT_ALL_MSK,
3557 RTW_PWR_INTF_ALL_MSK,
3558 RTW_PWR_ADDR_MAC,
3559 RTW_PWR_CMD_WRITE, BIT(3), 0},
3560 {0x001F,
3561 RTW_PWR_CUT_ALL_MSK,
3562 RTW_PWR_INTF_ALL_MSK,
3563 RTW_PWR_ADDR_MAC,
3564 RTW_PWR_CMD_WRITE, 0xFF, 0},
3565 {0x00EF,
3566 RTW_PWR_CUT_ALL_MSK,
3567 RTW_PWR_INTF_ALL_MSK,
3568 RTW_PWR_ADDR_MAC,
3569 RTW_PWR_CMD_WRITE, 0xFF, 0},
3570 {0x1045,
3571 RTW_PWR_CUT_ALL_MSK,
3572 RTW_PWR_INTF_ALL_MSK,
3573 RTW_PWR_ADDR_MAC,
3574 RTW_PWR_CMD_WRITE, BIT(4), 0},
3575 {0xFF1A,
3576 RTW_PWR_CUT_ALL_MSK,
3577 RTW_PWR_INTF_USB_MSK,
3578 RTW_PWR_ADDR_MAC,
3579 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
3580 {0x0049,
3581 RTW_PWR_CUT_ALL_MSK,
3582 RTW_PWR_INTF_ALL_MSK,
3583 RTW_PWR_ADDR_MAC,
3584 RTW_PWR_CMD_WRITE, BIT(1), 0},
3585 {0x0006,
3586 RTW_PWR_CUT_ALL_MSK,
3587 RTW_PWR_INTF_ALL_MSK,
3588 RTW_PWR_ADDR_MAC,
3589 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3590 {0x0002,
3591 RTW_PWR_CUT_ALL_MSK,
3592 RTW_PWR_INTF_ALL_MSK,
3593 RTW_PWR_ADDR_MAC,
3594 RTW_PWR_CMD_WRITE, BIT(1), 0},
3595 {0x0005,
3596 RTW_PWR_CUT_ALL_MSK,
3597 RTW_PWR_INTF_ALL_MSK,
3598 RTW_PWR_ADDR_MAC,
3599 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
3600 {0x0005,
3601 RTW_PWR_CUT_ALL_MSK,
3602 RTW_PWR_INTF_ALL_MSK,
3603 RTW_PWR_ADDR_MAC,
3604 RTW_PWR_CMD_POLLING, BIT(1), 0},
3605 {0x0000,
3606 RTW_PWR_CUT_ALL_MSK,
3607 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3608 RTW_PWR_ADDR_MAC,
3609 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
3610 {0xFFFF,
3611 RTW_PWR_CUT_ALL_MSK,
3612 RTW_PWR_INTF_ALL_MSK,
3613 0,
3614 RTW_PWR_CMD_END, 0, 0},
3615};
3616
3617static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = {
3618 {0x0005,
3619 RTW_PWR_CUT_ALL_MSK,
3620 RTW_PWR_INTF_SDIO_MSK,
3621 RTW_PWR_ADDR_MAC,
3622 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
3623 {0x0007,
3624 RTW_PWR_CUT_ALL_MSK,
3625 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3626 RTW_PWR_ADDR_MAC,
3627 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
3628 {0x0067,
3629 RTW_PWR_CUT_ALL_MSK,
3630 RTW_PWR_INTF_ALL_MSK,
3631 RTW_PWR_ADDR_MAC,
3632 RTW_PWR_CMD_WRITE, BIT(5), 0},
3633 {0x004A,
3634 RTW_PWR_CUT_ALL_MSK,
3635 RTW_PWR_INTF_USB_MSK,
3636 RTW_PWR_ADDR_MAC,
3637 RTW_PWR_CMD_WRITE, BIT(0), 0},
3638 {0x0081,
3639 RTW_PWR_CUT_ALL_MSK,
3640 RTW_PWR_INTF_ALL_MSK,
3641 RTW_PWR_ADDR_MAC,
3642 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
3643 {0x0090,
3644 RTW_PWR_CUT_ALL_MSK,
3645 RTW_PWR_INTF_ALL_MSK,
3646 RTW_PWR_ADDR_MAC,
3647 RTW_PWR_CMD_WRITE, BIT(1), 0},
dfcd0f58
CYL		 3648 {0x0092,
3649 RTW_PWR_CUT_ALL_MSK,
3650 RTW_PWR_INTF_PCI_MSK,
3651 RTW_PWR_ADDR_MAC,
3652 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
3653 {0x0093,
3654 RTW_PWR_CUT_ALL_MSK,
3655 RTW_PWR_INTF_PCI_MSK,
3656 RTW_PWR_ADDR_MAC,
3657 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
e3037485
YHC		 3658 {0x0005,
3659 RTW_PWR_CUT_ALL_MSK,
3660 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3661 RTW_PWR_ADDR_MAC,
3662 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
3663 {0x0005,
3664 RTW_PWR_CUT_ALL_MSK,
3665 RTW_PWR_INTF_PCI_MSK,
3666 RTW_PWR_ADDR_MAC,
3667 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3668 {0x0086,
3669 RTW_PWR_CUT_ALL_MSK,
3670 RTW_PWR_INTF_SDIO_MSK,
3671 RTW_PWR_ADDR_SDIO,
3672 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3673 {0xFFFF,
3674 RTW_PWR_CUT_ALL_MSK,
3675 RTW_PWR_INTF_ALL_MSK,
3676 0,
3677 RTW_PWR_CMD_END, 0, 0},
3678};
3679
3680static struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = {
3681 trans_carddis_to_cardemu_8822c,
3682 trans_cardemu_to_act_8822c,
3683 NULL
3684};
3685
3686static struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = {
3687 trans_act_to_cardemu_8822c,
3688 trans_cardemu_to_carddis_8822c,
3689 NULL
3690};
3691
3692static struct rtw_intf_phy_para usb2_param_8822c[] = {
3693 {0xFFFF, 0x00,
3694 RTW_IP_SEL_PHY,
3695 RTW_INTF_PHY_CUT_ALL,
3696 RTW_INTF_PHY_PLATFORM_ALL},
3697};
3698
3699static struct rtw_intf_phy_para usb3_param_8822c[] = {
3700 {0xFFFF, 0x0000,
3701 RTW_IP_SEL_PHY,
3702 RTW_INTF_PHY_CUT_ALL,
3703 RTW_INTF_PHY_PLATFORM_ALL},
3704};
3705
3706static struct rtw_intf_phy_para pcie_gen1_param_8822c[] = {
3707 {0xFFFF, 0x0000,
3708 RTW_IP_SEL_PHY,
3709 RTW_INTF_PHY_CUT_ALL,
3710 RTW_INTF_PHY_PLATFORM_ALL},
3711};
3712
3713static struct rtw_intf_phy_para pcie_gen2_param_8822c[] = {
3714 {0xFFFF, 0x0000,
3715 RTW_IP_SEL_PHY,
3716 RTW_INTF_PHY_CUT_ALL,
3717 RTW_INTF_PHY_PLATFORM_ALL},
3718};
3719
3720static struct rtw_intf_phy_para_table phy_para_table_8822c = {
3721 .usb2_para = usb2_param_8822c,
3722 .usb3_para = usb3_param_8822c,
3723 .gen1_para = pcie_gen1_param_8822c,
3724 .gen2_para = pcie_gen2_param_8822c,
3725 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c),
3726 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c),
3727 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c),
3728 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c),
3729};
3730
3731static const struct rtw_rfe_def rtw8822c_rfe_defs[] = {
3732 [0] = RTW_DEF_RFE(8822c, 0, 0),
3733 [1] = RTW_DEF_RFE(8822c, 0, 0),
3734 [2] = RTW_DEF_RFE(8822c, 0, 0),
3735};
3736
3737static struct rtw_hw_reg rtw8822c_dig[] = {
3738 [0] = { .addr = 0x1d70, .mask = 0x7f },
3739 [1] = { .addr = 0x1d70, .mask = 0x7f00 },
3740};
3741
3742static struct rtw_page_table page_table_8822c[] = {
3743 {64, 64, 64, 64, 1},
3744 {64, 64, 64, 64, 1},
3745 {64, 64, 0, 0, 1},
3746 {64, 64, 64, 0, 1},
3747 {64, 64, 64, 64, 1},
3748};
3749
3750static struct rtw_rqpn rqpn_table_8822c[] = {
3751 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3752 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3753 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3754 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3755 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3756 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3757 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3758 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
3759 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
3760 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3761 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3762 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
3763 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3764 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3765 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3766};
3767
3768static struct rtw_chip_ops rtw8822c_ops = {
3769 .phy_set_param = rtw8822c_phy_set_param,
3770 .read_efuse = rtw8822c_read_efuse,
3771 .query_rx_desc = rtw8822c_query_rx_desc,
3772 .set_channel = rtw8822c_set_channel,
3773 .mac_init = rtw8822c_mac_init,
3774 .read_rf = rtw_phy_read_rf,
3775 .write_rf = rtw_phy_write_rf_reg_mix,
3776 .set_tx_power_index = rtw8822c_set_tx_power_index,
3777 .cfg_ldo25 = rtw8822c_cfg_ldo25,
3778 .false_alarm_statistics = rtw8822c_false_alarm_statistics,
5227c2ee 3779 .dpk_track = rtw8822c_dpk_track,
f27b886d 3780 .phy_calibration = rtw8822c_phy_calibration,
479c4ee9 3781 .cck_pd_set = rtw8822c_phy_cck_pd_set,
c97ee3e0 3782 .pwr_track = rtw8822c_pwr_track,
0bd95573
TEH		 3783 .config_bfee = rtw8822c_bf_config_bfee,
3784 .set_gid_table = rtw_bf_set_gid_table,
3785 .cfg_csi_rate = rtw_bf_cfg_csi_rate,
4136214f
YHC		 3786
3787 .coex_set_init = rtw8822c_coex_cfg_init,
3788 .coex_set_ant_switch = NULL,
3789 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix,
3790 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug,
3791 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type,
3792 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power,
3793 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain,
3794};
3795
3796/* Shared-Antenna Coex Table */
3797static const struct coex_table_para table_sant_8822c[] = {
3798 {0xffffffff, 0xffffffff}, /* case-0 */
3799 {0x55555555, 0x55555555},
3800 {0x66555555, 0x66555555},
3801 {0xaaaaaaaa, 0xaaaaaaaa},
3802 {0x5a5a5a5a, 0x5a5a5a5a},
3803 {0xfafafafa, 0xfafafafa}, /* case-5 */
3804 {0x6a5a6a5a, 0xaaaaaaaa},
3805 {0x6a5a56aa, 0x6a5a56aa},
3806 {0x6a5a5a5a, 0x6a5a5a5a},
3807 {0x66555555, 0x5a5a5a5a},
3808 {0x66555555, 0x6a5a5a5a}, /* case-10 */
3809 {0x66555555, 0xfafafafa},
3810 {0x66555555, 0x6a5a5aaa},
3811 {0x66555555, 0x5aaa5aaa},
3812 {0x66555555, 0xaaaa5aaa},
3813 {0x66555555, 0xaaaaaaaa}, /* case-15 */
3814 {0xffff55ff, 0xfafafafa},
3815 {0xffff55ff, 0x6afa5afa},
3816 {0xaaffffaa, 0xfafafafa},
3817 {0xaa5555aa, 0x5a5a5a5a},
3818 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
3819 {0xaa5555aa, 0xaaaaaaaa},
3820 {0xffffffff, 0x5a5a5a5a},
3821 {0xffffffff, 0x6a5a5a5a},
3822 {0xffffffff, 0x55555555},
3823 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
3824 {0x55555555, 0x5a5a5a5a},
3825 {0x55555555, 0xaaaaaaaa},
3826 {0x55555555, 0x6a5a6a5a},
3827 {0x66556655, 0x66556655}
3828};
3829
3830/* Non-Shared-Antenna Coex Table */
3831static const struct coex_table_para table_nsant_8822c[] = {
3832 {0xffffffff, 0xffffffff}, /* case-100 */
3833 {0x55555555, 0x55555555},
3834 {0x66555555, 0x66555555},
3835 {0xaaaaaaaa, 0xaaaaaaaa},
3836 {0x5a5a5a5a, 0x5a5a5a5a},
3837 {0xfafafafa, 0xfafafafa}, /* case-105 */
3838 {0x5afa5afa, 0x5afa5afa},
3839 {0x55555555, 0xfafafafa},
3840 {0x66555555, 0xfafafafa},
3841 {0x66555555, 0x5a5a5a5a},
3842 {0x66555555, 0x6a5a5a5a}, /* case-110 */
3843 {0x66555555, 0xaaaaaaaa},
3844 {0xffff55ff, 0xfafafafa},
3845 {0xffff55ff, 0x5afa5afa},
3846 {0xffff55ff, 0xaaaaaaaa},
3847 {0xaaffffaa, 0xfafafafa}, /* case-115 */
3848 {0xaaffffaa, 0x5afa5afa},
3849 {0xaaffffaa, 0xaaaaaaaa},
3850 {0xffffffff, 0xfafafafa},
3851 {0xffffffff, 0x5afa5afa},
3852 {0xffffffff, 0xaaaaaaaa},/* case-120 */
3853 {0x55ff55ff, 0x5afa5afa},
3854 {0x55ff55ff, 0xaaaaaaaa},
3855 {0x55ff55ff, 0x55ff55ff}
3856};
3857
3858/* Shared-Antenna TDMA */
3859static const struct coex_tdma_para tdma_sant_8822c[] = {
3860 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
3861 { {0x61, 0x45, 0x03, 0x11, 0x11} },
3862 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
3863 { {0x61, 0x30, 0x03, 0x11, 0x11} },
3864 { {0x61, 0x20, 0x03, 0x11, 0x11} },
3865 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
3866 { {0x61, 0x45, 0x03, 0x11, 0x10} },
3867 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
3868 { {0x61, 0x30, 0x03, 0x11, 0x10} },
3869 { {0x61, 0x20, 0x03, 0x11, 0x10} },
3870 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
3871 { {0x61, 0x08, 0x03, 0x11, 0x14} },
3872 { {0x61, 0x08, 0x03, 0x10, 0x14} },
3873 { {0x51, 0x08, 0x03, 0x10, 0x54} },
3874 { {0x51, 0x08, 0x03, 0x10, 0x55} },
3875 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
3876 { {0x51, 0x45, 0x03, 0x10, 0x10} },
3877 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
3878 { {0x51, 0x30, 0x03, 0x10, 0x50} },
3879 { {0x51, 0x20, 0x03, 0x10, 0x50} },
3880 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
3881 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
3882 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
3883 { {0x55, 0x08, 0x03, 0x10, 0x54} },
3884 { {0x65, 0x10, 0x03, 0x11, 0x11} },
3885 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
3886 { {0x51, 0x08, 0x03, 0x10, 0x50} }
e3037485
YHC		 3887};
3888
4136214f
YHC		 3889/* Non-Shared-Antenna TDMA */
3890static const struct coex_tdma_para tdma_nsant_8822c[] = {
3891 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
3892 { {0x61, 0x45, 0x03, 0x11, 0x11} },
3893 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
3894 { {0x61, 0x30, 0x03, 0x11, 0x11} },
3895 { {0x61, 0x20, 0x03, 0x11, 0x11} },
3896 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
3897 { {0x61, 0x45, 0x03, 0x11, 0x10} },
3898 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
3899 { {0x61, 0x30, 0x03, 0x11, 0x10} },
3900 { {0x61, 0x20, 0x03, 0x11, 0x10} },
3901 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
3902 { {0x61, 0x08, 0x03, 0x11, 0x14} },
3903 { {0x61, 0x08, 0x03, 0x10, 0x14} },
3904 { {0x51, 0x08, 0x03, 0x10, 0x54} },
3905 { {0x51, 0x08, 0x03, 0x10, 0x55} },
3906 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
3907 { {0x51, 0x45, 0x03, 0x10, 0x50} },
3908 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
3909 { {0x51, 0x30, 0x03, 0x10, 0x50} },
3910 { {0x51, 0x20, 0x03, 0x10, 0x50} },
3911 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */
3912};
3913
3914/* rssi in percentage % (dbm = % - 100) */
3915static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30};
3916static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25};
3917static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };
3918
3919/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
3920static const struct coex_rf_para rf_para_tx_8822c[] = {
3921 {0, 0, false, 7}, /* for normal */
3922 {0, 16, false, 7}, /* for WL-CPT */
3923 {8, 17, true, 4},
3924 {7, 18, true, 4},
3925 {6, 19, true, 4},
3926 {5, 20, true, 4}
3927};
3928
3929static const struct coex_rf_para rf_para_rx_8822c[] = {
3930 {0, 0, false, 7}, /* for normal */
3931 {0, 16, false, 7}, /* for WL-CPT */
3932 {3, 24, true, 5},
3933 {2, 26, true, 5},
3934 {1, 27, true, 5},
3935 {0, 28, true, 5}
3936};
3937
3938static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c));
3939
c97ee3e0
TEH		 3940static const u8
3941rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
3942 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
3943 11, 12, 13, 14, 15, 16, 18, 19, 20, 21,
3944 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 },
3945 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
3946 11, 12, 13, 14, 15, 16, 18, 19, 20, 21,
3947 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 },
3948 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
3949 11, 12, 13, 14, 15, 16, 18, 19, 20, 21,
3950 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 },
3951};
3952
3953static const u8
3954rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
3955 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
3956 10, 10, 11, 12, 13, 14, 15, 16, 17, 18,
3957 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 },
3958 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
3959 10, 10, 11, 12, 13, 14, 15, 16, 17, 18,
3960 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 },
3961 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
3962 10, 10, 11, 12, 13, 14, 15, 16, 17, 18,
3963 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 },
3964};
3965
3966static const u8
3967rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
3968 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
3969 11, 13, 14, 15, 16, 17, 18, 19, 20, 21,
3970 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 },
3971 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
3972 11, 13, 14, 15, 16, 17, 18, 19, 20, 21,
3973 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 },
3974 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
3975 11, 13, 14, 15, 16, 17, 18, 19, 20, 21,
3976 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 },
3977};
3978
3979static const u8
3980rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
3981 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
3982 10, 11, 12, 13, 14, 15, 16, 17, 18, 20,
3983 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 },
3984 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
3985 10, 11, 12, 13, 14, 15, 16, 17, 18, 20,
3986 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 },
3987 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
3988 10, 11, 12, 13, 14, 15, 16, 17, 18, 20,
3989 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 },
3990};
3991
3992static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = {
3993 0, 1, 2, 3, 4, 4, 5, 6, 7, 8,
3994 9, 9, 10, 11, 12, 13, 14, 15, 15, 16,
3995 17, 18, 19, 20, 20, 21, 22, 23, 24, 25
3996};
3997
3998static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = {
3999 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4000 10, 11, 12, 13, 14, 14, 15, 16, 17, 18,
4001 19, 20, 21, 22, 23, 24, 25, 26, 27, 28
4002};
4003
4004static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = {
4005 0, 1, 2, 2, 3, 4, 4, 5, 6, 6,
4006 7, 8, 8, 9, 9, 10, 11, 11, 12, 13,
4007 13, 14, 15, 15, 16, 17, 17, 18, 19, 19
4008};
4009
4010static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = {
4011 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4012 10, 11, 11, 12, 13, 14, 15, 16, 17, 18,
4013 19, 20, 21, 22, 23, 24, 25, 25, 26, 27
4014};
4015
4016static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = {
4017 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
4018 9, 10, 11, 11, 12, 13, 14, 15, 16, 17,
4019 17, 18, 19, 20, 21, 22, 23, 23, 24, 25
4020};
4021
4022static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = {
4023 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4024 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
4025 20, 21, 22, 23, 24, 25, 26, 27, 28, 29
4026};
4027
4028static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = {
4029 0, 1, 2, 3, 3, 4, 5, 6, 6, 7,
4030 8, 9, 9, 10, 11, 12, 12, 13, 14, 15,
4031 15, 16, 17, 18, 18, 19, 20, 21, 21, 22
4032};
4033
4034static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = {
4035 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
4036 9, 10, 11, 11, 12, 13, 14, 15, 16, 17,
4037 18, 18, 19, 20, 21, 22, 23, 24, 24, 25
4038};
4039
4040static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = {
4041 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1],
4042 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2],
4043 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3],
4044 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1],
4045 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2],
4046 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3],
4047 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1],
4048 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2],
4049 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3],
4050 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1],
4051 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2],
4052 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3],
4053 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n,
4054 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p,
4055 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n,
4056 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p,
4057 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n,
4058 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p,
4059 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n,
4060 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p,
4061};
4062
e3037485
YHC		 4063struct rtw_chip_info rtw8822c_hw_spec = {
4064 .ops = &rtw8822c_ops,
4065 .id = RTW_CHIP_TYPE_8822C,
4066 .fw_name = "rtw88/rtw8822c_fw.bin",
4067 .tx_pkt_desc_sz = 48,
4068 .tx_buf_desc_sz = 16,
4069 .rx_pkt_desc_sz = 24,
4070 .rx_buf_desc_sz = 8,
4071 .phy_efuse_size = 512,
4072 .log_efuse_size = 768,
4073 .ptct_efuse_size = 124,
4074 .txff_size = 262144,
4075 .rxff_size = 24576,
4076 .txgi_factor = 2,
4077 .is_pwr_by_rate_dec = false,
4078 .max_power_index = 0x7f,
4079 .csi_buf_pg_num = 50,
4080 .band = RTW_BAND_2G | RTW_BAND_5G,
4081 .page_size = 128,
4082 .dig_min = 0x20,
4083 .ht_supported = true,
4084 .vht_supported = true,
04b786e0 4085 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG),
e3037485
YHC		 4086 .sys_func_en = 0xD8,
4087 .pwr_on_seq = card_enable_flow_8822c,
4088 .pwr_off_seq = card_disable_flow_8822c,
4089 .page_table = page_table_8822c,
4090 .rqpn_table = rqpn_table_8822c,
4091 .intf_table = &phy_para_table_8822c,
4092 .dig = rtw8822c_dig,
4093 .rf_base_addr = {0x3c00, 0x4c00},
4094 .rf_sipi_addr = {0x1808, 0x4108},
4095 .mac_tbl = &rtw8822c_mac_tbl,
4096 .agc_tbl = &rtw8822c_agc_tbl,
4097 .bb_tbl = &rtw8822c_bb_tbl,
4098 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl,
4099 .rf_tbl = {&rtw8822c_rf_a_tbl, &rtw8822c_rf_b_tbl},
4100 .rfe_defs = rtw8822c_rfe_defs,
4101 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs),
5227c2ee
TEH		 4102 .en_dis_dpd = true,
4103 .dpd_ratemask = DIS_DPD_RATEALL,
c97ee3e0
TEH		 4104 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl,
4105 .iqk_threshold = 8,
0bd95573
TEH		 4106 .bfer_su_max_num = 2,
4107 .bfer_mu_max_num = 1,
4136214f
YHC		 4108
4109 .coex_para_ver = 0x19062706,
4110 .bt_desired_ver = 0x6,
4111 .scbd_support = true,
4112 .new_scbd10_def = true,
4113 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
4114 .bt_rssi_type = COEX_BTRSSI_DBM,
4115 .ant_isolation = 15,
4116 .rssi_tolerance = 2,
4117 .wl_rssi_step = wl_rssi_step_8822c,
4118 .bt_rssi_step = bt_rssi_step_8822c,
4119 .table_sant_num = ARRAY_SIZE(table_sant_8822c),
4120 .table_sant = table_sant_8822c,
4121 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c),
4122 .table_nsant = table_nsant_8822c,
4123 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c),
4124 .tdma_sant = tdma_sant_8822c,
4125 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c),
4126 .tdma_nsant = tdma_nsant_8822c,
4127 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c),
4128 .wl_rf_para_tx = rf_para_tx_8822c,
4129 .wl_rf_para_rx = rf_para_rx_8822c,
4130 .bt_afh_span_bw20 = 0x24,
4131 .bt_afh_span_bw40 = 0x36,
4132 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c),
4133 .afh_5g = afh_5g_8822c,
e3037485
YHC		 4134};
4135EXPORT_SYMBOL(rtw8822c_hw_spec);
4136
4137MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin");
Linux 6.x block layer and io_uring tree(s)