[linux-2.6-block.git] / drivers / net / wireless / realtek / rtw88 / reg.h

/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2018-2019  Realtek Corporation
 */

#ifndef __RTW_REG_DEF_H__
#define __RTW_REG_DEF_H__

#define REG_SYS_FUNC_EN		0x0002
#define BIT_FEN_CPUEN		BIT(2)
#define BIT_FEN_BB_GLB_RST	BIT(1)
#define BIT_FEN_BB_RSTB		BIT(0)
#define REG_SYS_PW_CTRL		0x0004
#define REG_SYS_CLK_CTRL	0x0008
#define BIT_CPU_CLK_EN		BIT(14)

#define REG_RSV_CTRL		0x001C
#define DISABLE_PI		0x3
#define ENABLE_PI		0x2
#define BITS_RFC_DIRECT		(BIT(31) | BIT(30))
#define BIT_WLMCU_IOIF		BIT(0)
#define REG_RF_CTRL		0x001F
#define BIT_RF_SDM_RSTB		BIT(2)
#define BIT_RF_RSTB		BIT(1)
#define BIT_RF_EN		BIT(0)

#define REG_AFE_CTRL1		0x0024
#define BIT_MAC_CLK_SEL		(BIT(20) | BIT(21))
#define REG_EFUSE_CTRL		0x0030
#define BIT_EF_FLAG		BIT(31)
#define BIT_SHIFT_EF_ADDR	8
#define BIT_MASK_EF_ADDR	0x3ff
#define BIT_MASK_EF_DATA	0xff
#define BITS_EF_ADDR		(BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)

#define REG_LDO_EFUSE_CTRL	0x0034
#define BIT_MASK_EFUSE_BANK_SEL	(BIT(8) | BIT(9))

#define REG_GPIO_MUXCFG		0x0040
#define BIT_FSPI_EN		BIT(19)
#define BIT_BT_AOD_GPIO3	BIT(9)
#define BIT_BT_PTA_EN		BIT(5)
#define BIT_WLRFE_4_5_EN	BIT(2)

#define REG_LED_CFG		0x004C
#define BIT_LNAON_SEL_EN	BIT(26)
#define BIT_PAPE_SEL_EN		BIT(25)
#define BIT_DPDT_WL_SEL		BIT(24)
#define BIT_DPDT_SEL_EN		BIT(23)
#define REG_PAD_CTRL1		0x0064
#define BIT_PAPE_WLBT_SEL	BIT(29)
#define BIT_LNAON_WLBT_SEL	BIT(28)
#define BIT_BTGP_JTAG_EN	BIT(24)
#define BIT_BTGP_SPI_EN		BIT(20)
#define BIT_LED1DIS		BIT(15)
#define BIT_SW_DPDT_SEL_DATA	BIT(0)
#define REG_WL_BT_PWR_CTRL	0x0068
#define BIT_BT_FUNC_EN		BIT(18)
#define BIT_BT_DIG_CLK_EN	BIT(8)
#define REG_SYS_SDIO_CTRL	0x0070
#define BIT_DBG_GNT_WL_BT	BIT(27)
#define BIT_LTE_MUX_CTRL_PATH	BIT(26)
#define REG_HCI_OPT_CTRL	0x0074

#define REG_MCUFW_CTRL		0x0080
#define BIT_ANA_PORT_EN		BIT(22)
#define BIT_MAC_PORT_EN		BIT(21)
#define BIT_BOOT_FSPI_EN	BIT(20)
#define BIT_FW_INIT_RDY		BIT(15)
#define BIT_FW_DW_RDY		BIT(14)
#define BIT_RPWM_TOGGLE		BIT(7)
#define BIT_DMEM_CHKSUM_OK	BIT(6)
#define BIT_DMEM_DW_OK		BIT(5)
#define BIT_IMEM_CHKSUM_OK	BIT(4)
#define BIT_IMEM_DW_OK		BIT(3)
#define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2)
#define BIT_MCUFWDL_EN		BIT(0)
#define BIT_CHECK_SUM_OK	(BIT(4) | BIT(6))
#define FW_READY		(BIT_FW_INIT_RDY | BIT_FW_DW_RDY |             \
				 BIT_IMEM_DW_OK | BIT_DMEM_DW_OK |             \
				 BIT_CHECK_SUM_OK)
#define FW_READY_MASK		0xffff

#define REG_WLRF1		0x00EC
#define REG_WIFI_BT_INFO	0x00AA
#define BIT_BT_INT_EN		BIT(15)
#define REG_SYS_CFG1		0x00F0
#define	BIT_RTL_ID		BIT(23)
#define BIT_RF_TYPE_ID		BIT(27)
#define BIT_SHIFT_VENDOR_ID	16
#define BIT_MASK_VENDOR_ID	0xf
#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
#define BITS_VENDOR_ID		(BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)
#define BIT_CLEAR_VENDOR_ID(x)	((x) & (~BITS_VENDOR_ID))
#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
#define BIT_SHIFT_CHIP_VER	12
#define BIT_MASK_CHIP_VER	0xf
#define BIT_CHIP_VER(x)	 (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
#define BITS_CHIP_VER		(BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)
#define BIT_CLEAR_CHIP_VER(x)	((x) & (~BITS_CHIP_VER))
#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
#define REG_SYS_STATUS1		0x00F4
#define REG_SYS_STATUS2		0x00F8
#define REG_SYS_CFG2		0x00FC
#define REG_WLRF1		0x00EC
#define BIT_WLRF1_BBRF_EN	(BIT(24) | BIT(25) | BIT(26))
#define REG_CR			0x0100
#define BIT_32K_CAL_TMR_EN	BIT(10)
#define BIT_MAC_SEC_EN		BIT(9)
#define BIT_ENSWBCN		BIT(8)
#define BIT_MACRXEN		BIT(7)
#define BIT_MACTXEN		BIT(6)
#define BIT_SCHEDULE_EN		BIT(5)
#define BIT_PROTOCOL_EN		BIT(4)
#define BIT_RXDMA_EN		BIT(3)
#define BIT_TXDMA_EN		BIT(2)
#define BIT_HCI_RXDMA_EN	BIT(1)
#define BIT_HCI_TXDMA_EN	BIT(0)
#define MAC_TRX_ENABLE	(BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
			BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
			BIT_MACTXEN | BIT_MACRXEN)
#define BIT_SHIFT_TXDMA_VOQ_MAP	4
#define BIT_MASK_TXDMA_VOQ_MAP	0x3
#define BIT_TXDMA_VOQ_MAP(x)                                                   \
	(((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
#define BIT_SHIFT_TXDMA_VIQ_MAP	6
#define BIT_MASK_TXDMA_VIQ_MAP	0x3
#define BIT_TXDMA_VIQ_MAP(x)                                                   \
	(((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
#define REG_TXDMA_PQ_MAP	0x010C
#define BIT_SHIFT_TXDMA_BEQ_MAP	8
#define BIT_MASK_TXDMA_BEQ_MAP	0x3
#define BIT_TXDMA_BEQ_MAP(x)                                                   \
	(((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
#define BIT_SHIFT_TXDMA_BKQ_MAP	10
#define BIT_MASK_TXDMA_BKQ_MAP	0x3
#define BIT_TXDMA_BKQ_MAP(x)                                                   \
	(((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
#define BIT_SHIFT_TXDMA_MGQ_MAP	12
#define BIT_MASK_TXDMA_MGQ_MAP	0x3
#define BIT_TXDMA_MGQ_MAP(x)                                                   \
	(((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
#define BIT_SHIFT_TXDMA_HIQ_MAP	14
#define BIT_MASK_TXDMA_HIQ_MAP	0x3
#define BIT_TXDMA_HIQ_MAP(x)                                                   \
	(((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
#define BIT_SHIFT_TXSC_40M	4
#define BIT_MASK_TXSC_40M	0xf
#define BIT_TXSC_40M(x)							       \
	(((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
#define BIT_SHIFT_TXSC_20M	0
#define BIT_MASK_TXSC_20M	0xf
#define BIT_TXSC_20M(x)							       \
	(((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
#define BIT_SHIFT_MAC_CLK_SEL	20
#define MAC_CLK_HW_DEF_80M	0
#define MAC_CLK_HW_DEF_40M	1
#define MAC_CLK_HW_DEF_20M	2
#define MAC_CLK_SPEED		80

#define REG_CR			0x0100
#define REG_TRXFF_BNDY		0x0114
#define REG_RXFF_BNDY		0x011C
#define REG_PKTBUF_DBG_CTRL	0x0140
#define REG_C2HEVT		0x01A0
#define REG_HMETFR		0x01CC
#define REG_HMEBOX0		0x01D0
#define REG_HMEBOX1		0x01D4
#define REG_HMEBOX2		0x01D8
#define REG_HMEBOX3		0x01DC
#define REG_HMEBOX0_EX		0x01F0
#define REG_HMEBOX1_EX		0x01F4
#define REG_HMEBOX2_EX		0x01F8
#define REG_HMEBOX3_EX		0x01FC

#define REG_FIFOPAGE_CTRL_2	0x0204
#define BIT_BCN_VALID_V1	BIT(15)
#define BIT_MASK_BCN_HEAD_1_V1	0xfff
#define REG_AUTO_LLT_V1		0x0208
#define BIT_AUTO_INIT_LLT_V1	BIT(0)
#define REG_TXDMA_OFFSET_CHK	0x020C
#define REG_TXDMA_STATUS	0x0210
#define BTI_PAGE_OVF		BIT(2)
#define REG_RQPN_CTRL_1		0x0228
#define REG_RQPN_CTRL_2		0x022C
#define BIT_LD_RQPN		BIT(31)
#define REG_FIFOPAGE_INFO_1	0x0230
#define REG_FIFOPAGE_INFO_2	0x0234
#define REG_FIFOPAGE_INFO_3	0x0238
#define REG_FIFOPAGE_INFO_4	0x023C
#define REG_FIFOPAGE_INFO_5	0x0240
#define REG_H2C_HEAD		0x0244
#define REG_H2C_TAIL		0x0248
#define REG_H2C_READ_ADDR	0x024C
#define REG_H2C_INFO		0x0254

#define REG_INT_MIG		0x0304

#define REG_FWHW_TXQ_CTRL	0x0420
#define BIT_EN_BCNQ_DL		BIT(22)
#define BIT_EN_WR_FREE_TAIL	BIT(20)
#define REG_BCNQ_BDNY_V1	0x0424
#define REG_LIFETIME_EN		0x0426
#define BIT_BA_PARSER_EN	BIT(5)
#define REG_SPEC_SIFS		0x0428
#define REG_RETRY_LIMIT		0x042a
#define REG_DARFRC		0x0430
#define REG_DARFRCH		0x0434
#define REG_RARFRCH		0x043C
#define REG_ARFR0		0x0444
#define REG_ARFRH0		0x0448
#define REG_ARFR1_V1		0x044C
#define REG_ARFRH1_V1		0x0450
#define REG_CCK_CHECK		0x0454
#define BIT_CHECK_CCK_EN	BIT(7)
#define REG_AMPDU_MAX_TIME_V1	0x0455
#define REG_BCNQ1_BDNY_V1	0x0456
#define REG_TX_HANG_CTRL	0x045E
#define BIT_EN_GNT_BT_AWAKE	BIT(3)
#define BIT_EN_EOF_V1		BIT(2)
#define REG_DATA_SC		0x0483
#define REG_ARFR4		0x049C
#define BIT_WL_RFK		BIT(0)
#define REG_ARFRH4		0x04A0
#define REG_ARFR5		0x04A4
#define REG_ARFRH5		0x04A8
#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
#define BIT_PRE_TX_CMD		BIT(6)
#define REG_QUEUE_CTRL		0x04C6
#define BIT_PTA_WL_TX_EN	BIT(4)
#define BIT_PTA_EDCCA_EN	BIT(5)
#define REG_PROT_MODE_CTRL	0x04C8
#define REG_BAR_MODE_CTRL	0x04CC
#define REG_PRECNT_CTRL		0x04E5
#define BIT_BTCCA_CTRL		(BIT(0) | BIT(1))
#define BIT_EN_PRECNT		BIT(11)
#define REG_DUMMY_PAGE4_V1	0x04FC

#define REG_EDCA_VO_PARAM	0x0500
#define REG_EDCA_VI_PARAM	0x0504
#define REG_EDCA_BE_PARAM	0x0508
#define REG_EDCA_BK_PARAM	0x050C
#define BIT_MASK_TXOP_LMT	GENMASK(26, 16)
#define BIT_MASK_CWMAX		GENMASK(15, 12)
#define BIT_MASK_CWMIN		GENMASK(11, 8)
#define BIT_MASK_AIFS		GENMASK(7, 0)
#define REG_PIFS		0x0512
#define REG_SIFS		0x0514
#define BIT_SHIFT_SIFS_OFDM_CTX	8
#define BIT_SHIFT_SIFS_CCK_TRX	16
#define BIT_SHIFT_SIFS_OFDM_TRX	24
#define REG_SLOT		0x051B
#define REG_TX_PTCL_CTRL	0x0520
#define BIT_SIFS_BK_EN		BIT(12)
#define REG_TXPAUSE		0x0522
#define REG_RD_CTRL		0x0524
#define BIT_DIS_TXOP_CFE	BIT(10)
#define BIT_DIS_LSIG_CFE	BIT(9)
#define BIT_DIS_STBC_CFE	BIT(8)
#define REG_TBTT_PROHIBIT	0x0540
#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
#define REG_RD_NAV_NXT		0x0544
#define REG_BCN_CTRL		0x0550
#define BIT_DIS_TSF_UDT		BIT(4)
#define BIT_EN_BCN_FUNCTION	BIT(3)
#define REG_BCN_CTRL_CLINT0	0x0551
#define REG_DRVERLYINT		0x0558
#define REG_BCNDMATIM		0x0559
#define REG_USTIME_TSF		0x055C
#define REG_BCN_MAX_ERR		0x055D
#define REG_RXTSF_OFFSET_CCK	0x055E
#define REG_MISC_CTRL		0x0577
#define BIT_EN_FREE_CNT		BIT(3)
#define BIT_DIS_SECOND_CCA	(BIT(0) | BIT(1))
#define REG_TIMER0_SRC_SEL	0x05B4
#define BIT_TSFT_SEL_TIMER0	(BIT(4) | BIT(5) | BIT(6))

#define REG_TCR			0x0604
#define BIT_PWRMGT_HWDATA_EN	BIT(7)
#define REG_RCR			0x0608
#define BIT_APP_FCS		BIT(31)
#define BIT_APP_MIC		BIT(30)
#define BIT_APP_ICV		BIT(29)
#define BIT_APP_PHYSTS		BIT(28)
#define BIT_APP_BASSN		BIT(27)
#define BIT_VHT_DACK		BIT(26)
#define BIT_TCPOFLD_EN		BIT(25)
#define BIT_ENMBID		BIT(24)
#define BIT_LSIGEN		BIT(23)
#define BIT_MFBEN		BIT(22)
#define BIT_DISCHKPPDLLEN	BIT(21)
#define BIT_PKTCTL_DLEN		BIT(20)
#define BIT_TIM_PARSER_EN	BIT(18)
#define BIT_BC_MD_EN		BIT(17)
#define BIT_UC_MD_EN		BIT(16)
#define BIT_RXSK_PERPKT		BIT(15)
#define BIT_HTC_LOC_CTRL	BIT(14)
#define BIT_RPFM_CAM_ENABLE	BIT(12)
#define BIT_TA_BCN		BIT(11)
#define BIT_DISDECMYPKT		BIT(10)
#define BIT_AICV		BIT(9)
#define BIT_ACRC32		BIT(8)
#define BIT_CBSSID_BCN		BIT(7)
#define BIT_CBSSID_DATA		BIT(6)
#define BIT_APWRMGT		BIT(5)
#define BIT_ADD3		BIT(4)
#define BIT_AB			BIT(3)
#define BIT_AM			BIT(2)
#define BIT_APM			BIT(1)
#define BIT_AAP			BIT(0)
#define REG_RX_PKT_LIMIT	0x060C
#define REG_RX_DRVINFO_SZ	0x060F
#define BIT_APP_PHYSTS		BIT(28)
#define REG_MAR			0x0620
#define REG_USTIME_EDCA		0x0638
#define REG_ACKTO_CCK		0x0639
#define REG_RESP_SIFS_CCK	0x063C
#define REG_RESP_SIFS_OFDM	0x063E
#define REG_ACKTO		0x0640
#define REG_EIFS		0x0642
#define REG_NAV_CTRL		0x0650
#define REG_WMAC_TRXPTCL_CTL	0x0668
#define BIT_RFMOD		(BIT(7) | BIT(8))
#define BIT_RFMOD_80M		BIT(8)
#define BIT_RFMOD_40M		BIT(7)
#define REG_WMAC_TRXPTCL_CTL_H	0x066C
#define REG_RXFLTMAP0		0x06A0
#define REG_RXFLTMAP1		0x06A2
#define REG_RXFLTMAP2		0x06A4
#define REG_RXFLTMAP4		0x068A
#define REG_BT_COEX_TABLE0	0x06C0
#define REG_BT_COEX_TABLE1	0x06C4
#define REG_BT_COEX_BRK_TABLE	0x06C8
#define REG_BT_COEX_TABLE_H	0x06CC
#define REG_BT_COEX_TABLE_H1	0x06CD
#define REG_BT_COEX_TABLE_H2	0x06CE
#define REG_BT_COEX_TABLE_H3	0x06CF
#define REG_BBPSF_CTRL		0x06DC

#define REG_BT_COEX_V2		0x0763
#define BIT_GNT_BT_POLARITY	BIT(4)
#define BIT_LTE_COEX_EN		BIT(7)
#define REG_BT_STAT_CTRL	0x0778
#define REG_BT_TDMA_TIME	0x0790
#define REG_WMAC_OPTION_FUNCTION 0x07D0
#define REG_WMAC_OPTION_FUNCTION_1 0x07D4

#define REG_RX_GAIN_EN		0x081c

#define REG_RFE_CTRL_E		0x0974

#define REG_DIS_DPD		0x0a70
#define DIS_DPD_MASK		GENMASK(9, 0)
#define DIS_DPD_RATE6M		BIT(0)
#define DIS_DPD_RATE9M		BIT(1)
#define DIS_DPD_RATEMCS0	BIT(2)
#define DIS_DPD_RATEMCS1	BIT(3)
#define DIS_DPD_RATEMCS8	BIT(4)
#define DIS_DPD_RATEMCS9	BIT(5)
#define DIS_DPD_RATEVHT1SS_MCS0	BIT(6)
#define DIS_DPD_RATEVHT1SS_MCS1	BIT(7)
#define DIS_DPD_RATEVHT2SS_MCS0	BIT(8)
#define DIS_DPD_RATEVHT2SS_MCS1	BIT(9)
#define DIS_DPD_RATEALL		GENMASK(9, 0)

#define REG_RFE_CTRL8		0x0cb4
#define BIT_MASK_RFE_SEL89	GENMASK(7, 0)
#define REG_RFE_INV8		0x0cbd
#define BIT_MASK_RFE_INV89	GENMASK(1, 0)
#define REG_RFE_INV16		0x0cbe
#define BIT_RFE_BUF_EN		BIT(3)

#define REG_ANAPAR_XTAL_0	0x1040
#define REG_CPU_DMEM_CON	0x1080
#define BIT_WL_PLATFORM_RST	BIT(16)
#define BIT_WL_SECURITY_CLK	BIT(15)
#define BIT_DDMA_EN		BIT(8)

#define REG_H2C_PKT_READADDR	0x10D0
#define REG_H2C_PKT_WRITEADDR	0x10D4
#define REG_FW_DBG7		0x10FC
#define FW_KEY_MASK		0xffffff00

#define REG_CR_EXT		0x1100

#define REG_DDMA_CH0SA		0x1200
#define REG_DDMA_CH0DA		0x1204
#define REG_DDMA_CH0CTRL	0x1208
#define BIT_DDMACH0_OWN		BIT(31)
#define BIT_DDMACH0_CHKSUM_EN	BIT(29)
#define BIT_DDMACH0_CHKSUM_STS	BIT(27)
#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)
#define BIT_DDMACH0_CHKSUM_CONT	BIT(24)
#define BIT_MASK_DDMACH0_DLEN	0x3ffff

#define REG_H2CQ_CSR		0x1330
#define BIT_H2CQ_FULL		BIT(31)
#define REG_FAST_EDCA_VOVI_SETTING 0x1448
#define REG_FAST_EDCA_BEBK_SETTING 0x144C

#define REG_RXPSF_CTRL		0x1610
#define BIT_RXGCK_FIFOTHR_EN	BIT(28)

#define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26
#define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3
#define BIT_RXGCK_VHT_FIFOTHR(x)                                               \
	(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
#define BITS_RXGCK_VHT_FIFOTHR                                                 \
	(BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)

#define BIT_SHIFT_RXGCK_HT_FIFOTHR 24
#define BIT_MASK_RXGCK_HT_FIFOTHR 0x3
#define BIT_RXGCK_HT_FIFOTHR(x)                                                \
	(((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)
#define BITS_RXGCK_HT_FIFOTHR                                                  \
	(BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)

#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22
#define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3
#define BIT_RXGCK_OFDM_FIFOTHR(x)                                              \
	(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
#define BITS_RXGCK_OFDM_FIFOTHR                                                \
	(BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)

#define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20
#define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3
#define BIT_RXGCK_CCK_FIFOTHR(x)                                               \
	(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
#define BITS_RXGCK_CCK_FIFOTHR                                                 \
	(BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)

#define BIT_RXGCK_OFDMCCA_EN BIT(16)

#define BIT_SHIFT_RXPSF_PKTLENTHR 13
#define BIT_MASK_RXPSF_PKTLENTHR 0x7
#define BIT_RXPSF_PKTLENTHR(x)                                                 \
	(((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)
#define BITS_RXPSF_PKTLENTHR                                                   \
	(BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)
#define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR))
#define BIT_SET_RXPSF_PKTLENTHR(x, v)                                          \
	(BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))

#define BIT_RXPSF_CTRLEN	BIT(12)
#define BIT_RXPSF_VHTCHKEN	BIT(11)
#define BIT_RXPSF_HTCHKEN	BIT(10)
#define BIT_RXPSF_OFDMCHKEN	BIT(9)
#define BIT_RXPSF_CCKCHKEN	BIT(8)
#define BIT_RXPSF_OFDMRST	BIT(7)
#define BIT_RXPSF_CCKRST	BIT(6)
#define BIT_RXPSF_MHCHKEN	BIT(5)
#define BIT_RXPSF_CONT_ERRCHKEN	BIT(4)
#define BIT_RXPSF_ALL_ERRCHKEN	BIT(3)

#define BIT_SHIFT_RXPSF_ERRTHR 0
#define BIT_MASK_RXPSF_ERRTHR 0x7
#define BIT_RXPSF_ERRTHR(x)                                                    \
	(((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)
#define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)
#define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR))
#define BIT_GET_RXPSF_ERRTHR(x)                                                \
	(((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)
#define BIT_SET_RXPSF_ERRTHR(x, v)                                             \
	(BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))

#define REG_RXPSF_TYPE_CTRL	0x1614
#define REG_GENERAL_OPTION	0x1664
#define BIT_DUMMY_FCS_READY_MASK_EN BIT(9)

#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1		0x1700
#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1	0x1704
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1	0x1708
#define LTECOEX_READY		BIT(29)
#define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1
#define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
#define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1

#define REG_IGN_GNT_BT1	0x1860

#define REG_RFESEL_CTRL	0x1990

#define REG_NOMASK_TXBT	0x1ca7
#define REG_ANAPAR	0x1c30
#define BIT_ANAPAR_BTPS	BIT(22)
#define REG_RSTB_SEL	0x1c38

#define REG_IGN_GNTBT4	0x4160

#define RF_MODOPT	0x01
#define RF_DTXLOK	0x08
#define RF_CFGCH	0x18
#define RF_RCK		0x1d
#define RF_LUTWA	0x33
#define RF_LUTWD1	0x3e
#define RF_LUTWD0	0x3f
#define RF_T_METER	0x42
#define RF_XTALX2	0xb8
#define RF_MALSEL	0xbe
#define RF_RCKD		0xde
#define RF_LUTDBG	0xdf
#define RF_LUTWE2	0xee
#define RF_LUTWE	0xef

#define LTE_COEX_CTRL	0x38
#define LTE_WL_TRX_CTRL	0xa0
#define LTE_BT_TRX_CTRL	0xa4

#endif
Commit	Line	Data
e3037485 YHC	1	/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
	2	/* Copyright(c) 2018-2019 Realtek Corporation
	3	*/
	4
	5	#ifndef __RTW_REG_DEF_H__
	6	#define __RTW_REG_DEF_H__
	7
	8	#define REG_SYS_FUNC_EN 0x0002
	9	#define BIT_FEN_CPUEN BIT(2)
	10	#define BIT_FEN_BB_GLB_RST BIT(1)
	11	#define BIT_FEN_BB_RSTB BIT(0)
	12	#define REG_SYS_PW_CTRL 0x0004
	13	#define REG_SYS_CLK_CTRL 0x0008
	14	#define BIT_CPU_CLK_EN BIT(14)
	15
	16	#define REG_RSV_CTRL 0x001C
	17	#define DISABLE_PI 0x3
	18	#define ENABLE_PI 0x2
	19	#define BITS_RFC_DIRECT (BIT(31) \| BIT(30))
	20	#define BIT_WLMCU_IOIF BIT(0)
	21	#define REG_RF_CTRL 0x001F
	22	#define BIT_RF_SDM_RSTB BIT(2)
	23	#define BIT_RF_RSTB BIT(1)
	24	#define BIT_RF_EN BIT(0)
	25
	26	#define REG_AFE_CTRL1 0x0024
	27	#define BIT_MAC_CLK_SEL (BIT(20) \| BIT(21))
	28	#define REG_EFUSE_CTRL 0x0030
	29	#define BIT_EF_FLAG BIT(31)
	30	#define BIT_SHIFT_EF_ADDR 8
	31	#define BIT_MASK_EF_ADDR 0x3ff
	32	#define BIT_MASK_EF_DATA 0xff
	33	#define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
	34
	35	#define REG_LDO_EFUSE_CTRL 0x0034
	36	#define BIT_MASK_EFUSE_BANK_SEL (BIT(8) \| BIT(9))
	37
	38	#define REG_GPIO_MUXCFG 0x0040
	39	#define BIT_FSPI_EN BIT(19)
4136214f YHC	40	#define BIT_BT_AOD_GPIO3 BIT(9)
4136214f YHC	41	#define BIT_BT_PTA_EN BIT(5)
e3037485 YHC	42	#define BIT_WLRFE_4_5_EN BIT(2)
	43
	44	#define REG_LED_CFG 0x004C
	45	#define BIT_LNAON_SEL_EN BIT(26)
	46	#define BIT_PAPE_SEL_EN BIT(25)
4136214f YHC	47	#define BIT_DPDT_WL_SEL BIT(24)
4136214f YHC	48	#define BIT_DPDT_SEL_EN BIT(23)
e3037485 YHC	49	#define REG_PAD_CTRL1 0x0064
	50	#define BIT_PAPE_WLBT_SEL BIT(29)
	51	#define BIT_LNAON_WLBT_SEL BIT(28)
4136214f YHC	52	#define BIT_BTGP_JTAG_EN BIT(24)
	53	#define BIT_BTGP_SPI_EN BIT(20)
	54	#define BIT_LED1DIS BIT(15)
	55	#define BIT_SW_DPDT_SEL_DATA BIT(0)
e3037485 YHC	56	#define REG_WL_BT_PWR_CTRL 0x0068
	57	#define BIT_BT_FUNC_EN BIT(18)
	58	#define BIT_BT_DIG_CLK_EN BIT(8)
4136214f YHC	59	#define REG_SYS_SDIO_CTRL 0x0070
	60	#define BIT_DBG_GNT_WL_BT BIT(27)
	61	#define BIT_LTE_MUX_CTRL_PATH BIT(26)
e3037485 YHC	62	#define REG_HCI_OPT_CTRL 0x0074
	63
	64	#define REG_MCUFW_CTRL 0x0080
	65	#define BIT_ANA_PORT_EN BIT(22)
	66	#define BIT_MAC_PORT_EN BIT(21)
	67	#define BIT_BOOT_FSPI_EN BIT(20)
	68	#define BIT_FW_INIT_RDY BIT(15)
	69	#define BIT_FW_DW_RDY BIT(14)
	70	#define BIT_RPWM_TOGGLE BIT(7)
	71	#define BIT_DMEM_CHKSUM_OK BIT(6)
	72	#define BIT_DMEM_DW_OK BIT(5)
	73	#define BIT_IMEM_CHKSUM_OK BIT(4)
	74	#define BIT_IMEM_DW_OK BIT(3)
	75	#define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2)
	76	#define BIT_MCUFWDL_EN BIT(0)
	77	#define BIT_CHECK_SUM_OK (BIT(4) \| BIT(6))
	78	#define FW_READY (BIT_FW_INIT_RDY \| BIT_FW_DW_RDY \| \
	79	BIT_IMEM_DW_OK \| BIT_DMEM_DW_OK \| \
	80	BIT_CHECK_SUM_OK)
	81	#define FW_READY_MASK 0xffff
	82
	83	#define REG_WLRF1 0x00EC
4136214f YHC	84	#define REG_WIFI_BT_INFO 0x00AA
4136214f YHC	85	#define BIT_BT_INT_EN BIT(15)
e3037485 YHC	86	#define REG_SYS_CFG1 0x00F0
	87	#define BIT_RTL_ID BIT(23)
	88	#define BIT_RF_TYPE_ID BIT(27)
	89	#define BIT_SHIFT_VENDOR_ID 16
	90	#define BIT_MASK_VENDOR_ID 0xf
	91	#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
	92	#define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)
	93	#define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID))
	94	#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
	95	#define BIT_SHIFT_CHIP_VER 12
	96	#define BIT_MASK_CHIP_VER 0xf
	97	#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
	98	#define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)
	99	#define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER))
	100	#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
	101	#define REG_SYS_STATUS1 0x00F4
	102	#define REG_SYS_STATUS2 0x00F8
	103	#define REG_SYS_CFG2 0x00FC
	104	#define REG_WLRF1 0x00EC
	105	#define BIT_WLRF1_BBRF_EN (BIT(24) \| BIT(25) \| BIT(26))
	106	#define REG_CR 0x0100
	107	#define BIT_32K_CAL_TMR_EN BIT(10)
	108	#define BIT_MAC_SEC_EN BIT(9)
	109	#define BIT_ENSWBCN BIT(8)
	110	#define BIT_MACRXEN BIT(7)
	111	#define BIT_MACTXEN BIT(6)
	112	#define BIT_SCHEDULE_EN BIT(5)
	113	#define BIT_PROTOCOL_EN BIT(4)
	114	#define BIT_RXDMA_EN BIT(3)
	115	#define BIT_TXDMA_EN BIT(2)
	116	#define BIT_HCI_RXDMA_EN BIT(1)
	117	#define BIT_HCI_TXDMA_EN BIT(0)
	118	#define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN \| BIT_HCI_RXDMA_EN \| BIT_TXDMA_EN \| \
	119	BIT_RXDMA_EN \| BIT_PROTOCOL_EN \| BIT_SCHEDULE_EN \| \
	120	BIT_MACTXEN \| BIT_MACRXEN)
	121	#define BIT_SHIFT_TXDMA_VOQ_MAP 4
	122	#define BIT_MASK_TXDMA_VOQ_MAP 0x3
	123	#define BIT_TXDMA_VOQ_MAP(x) \
	124	(((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
	125	#define BIT_SHIFT_TXDMA_VIQ_MAP 6
	126	#define BIT_MASK_TXDMA_VIQ_MAP 0x3
	127	#define BIT_TXDMA_VIQ_MAP(x) \
	128	(((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
	129	#define REG_TXDMA_PQ_MAP 0x010C
	130	#define BIT_SHIFT_TXDMA_BEQ_MAP 8
	131	#define BIT_MASK_TXDMA_BEQ_MAP 0x3
	132	#define BIT_TXDMA_BEQ_MAP(x) \
	133	(((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
	134	#define BIT_SHIFT_TXDMA_BKQ_MAP 10
	135	#define BIT_MASK_TXDMA_BKQ_MAP 0x3
	136	#define BIT_TXDMA_BKQ_MAP(x) \
	137	(((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
	138	#define BIT_SHIFT_TXDMA_MGQ_MAP 12
	139	#define BIT_MASK_TXDMA_MGQ_MAP 0x3
	140	#define BIT_TXDMA_MGQ_MAP(x) \
	141	(((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
	142	#define BIT_SHIFT_TXDMA_HIQ_MAP 14
	143	#define BIT_MASK_TXDMA_HIQ_MAP 0x3
	144	#define BIT_TXDMA_HIQ_MAP(x) \
	145	(((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
	146	#define BIT_SHIFT_TXSC_40M 4
	147	#define BIT_MASK_TXSC_40M 0xf
	148	#define BIT_TXSC_40M(x) \
	149	(((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
150	#define BIT_SHIFT_TXSC_20M 0
151	#define BIT_MASK_TXSC_20M 0xf
152	#define BIT_TXSC_20M(x) \
153	(((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
154	#define BIT_SHIFT_MAC_CLK_SEL 20
155	#define MAC_CLK_HW_DEF_80M 0
156	#define MAC_CLK_HW_DEF_40M 1
157	#define MAC_CLK_HW_DEF_20M 2
158	#define MAC_CLK_SPEED 80
159
160	#define REG_CR 0x0100
161	#define REG_TRXFF_BNDY 0x0114
162	#define REG_RXFF_BNDY 0x011C
163	#define REG_PKTBUF_DBG_CTRL 0x0140
164	#define REG_C2HEVT 0x01A0
165	#define REG_HMETFR 0x01CC
166	#define REG_HMEBOX0 0x01D0
167	#define REG_HMEBOX1 0x01D4
168	#define REG_HMEBOX2 0x01D8
169	#define REG_HMEBOX3 0x01DC
170	#define REG_HMEBOX0_EX 0x01F0
171	#define REG_HMEBOX1_EX 0x01F4
172	#define REG_HMEBOX2_EX 0x01F8
173	#define REG_HMEBOX3_EX 0x01FC
174
175	#define REG_FIFOPAGE_CTRL_2 0x0204
176	#define BIT_BCN_VALID_V1 BIT(15)
177	#define BIT_MASK_BCN_HEAD_1_V1 0xfff
178	#define REG_AUTO_LLT_V1 0x0208
179	#define BIT_AUTO_INIT_LLT_V1 BIT(0)
180	#define REG_TXDMA_OFFSET_CHK 0x020C
181	#define REG_TXDMA_STATUS 0x0210
182	#define BTI_PAGE_OVF BIT(2)
183	#define REG_RQPN_CTRL_1 0x0228
184	#define REG_RQPN_CTRL_2 0x022C
185	#define BIT_LD_RQPN BIT(31)
186	#define REG_FIFOPAGE_INFO_1 0x0230
187	#define REG_FIFOPAGE_INFO_2 0x0234
188	#define REG_FIFOPAGE_INFO_3 0x0238
189	#define REG_FIFOPAGE_INFO_4 0x023C
190	#define REG_FIFOPAGE_INFO_5 0x0240
191	#define REG_H2C_HEAD 0x0244
192	#define REG_H2C_TAIL 0x0248
193	#define REG_H2C_READ_ADDR 0x024C
194	#define REG_H2C_INFO 0x0254
195
bc61ae96 TSL	196	#define REG_INT_MIG 0x0304
bc61ae96 TSL	197
e3037485 YHC	198	#define REG_FWHW_TXQ_CTRL 0x0420
	199	#define BIT_EN_BCNQ_DL BIT(22)
	200	#define BIT_EN_WR_FREE_TAIL BIT(20)
	201	#define REG_BCNQ_BDNY_V1 0x0424
	202	#define REG_LIFETIME_EN 0x0426
	203	#define BIT_BA_PARSER_EN BIT(5)
	204	#define REG_SPEC_SIFS 0x0428
4136214f	205	#define REG_RETRY_LIMIT 0x042a
e3037485 YHC	206	#define REG_DARFRC 0x0430
	207	#define REG_DARFRCH 0x0434
	208	#define REG_RARFRCH 0x043C
	209	#define REG_ARFR0 0x0444
	210	#define REG_ARFRH0 0x0448
	211	#define REG_ARFR1_V1 0x044C
	212	#define REG_ARFRH1_V1 0x0450
	213	#define REG_CCK_CHECK 0x0454
	214	#define BIT_CHECK_CCK_EN BIT(7)
	215	#define REG_AMPDU_MAX_TIME_V1 0x0455
	216	#define REG_BCNQ1_BDNY_V1 0x0456
	217	#define REG_TX_HANG_CTRL 0x045E
4136214f	218	#define BIT_EN_GNT_BT_AWAKE BIT(3)
e3037485 YHC	219	#define BIT_EN_EOF_V1 BIT(2)
	220	#define REG_DATA_SC 0x0483
	221	#define REG_ARFR4 0x049C
4136214f	222	#define BIT_WL_RFK BIT(0)
e3037485 YHC	223	#define REG_ARFRH4 0x04A0
	224	#define REG_ARFR5 0x04A4
	225	#define REG_ARFRH5 0x04A8
	226	#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
	227	#define BIT_PRE_TX_CMD BIT(6)
4136214f YHC	228	#define REG_QUEUE_CTRL 0x04C6
	229	#define BIT_PTA_WL_TX_EN BIT(4)
	230	#define BIT_PTA_EDCCA_EN BIT(5)
e3037485 YHC	231	#define REG_PROT_MODE_CTRL 0x04C8
	232	#define REG_BAR_MODE_CTRL 0x04CC
	233	#define REG_PRECNT_CTRL 0x04E5
4136214f	234	#define BIT_BTCCA_CTRL (BIT(0) \| BIT(1))
e3037485	235	#define BIT_EN_PRECNT BIT(11)
4136214f	236	#define REG_DUMMY_PAGE4_V1 0x04FC
e3037485 YHC	237
	238	#define REG_EDCA_VO_PARAM 0x0500
	239	#define REG_EDCA_VI_PARAM 0x0504
	240	#define REG_EDCA_BE_PARAM 0x0508
	241	#define REG_EDCA_BK_PARAM 0x050C
bf06c7ec YHC	242	#define BIT_MASK_TXOP_LMT GENMASK(26, 16)
	243	#define BIT_MASK_CWMAX GENMASK(15, 12)
	244	#define BIT_MASK_CWMIN GENMASK(11, 8)
	245	#define BIT_MASK_AIFS GENMASK(7, 0)
e3037485 YHC	246	#define REG_PIFS 0x0512
	247	#define REG_SIFS 0x0514
	248	#define BIT_SHIFT_SIFS_OFDM_CTX 8
	249	#define BIT_SHIFT_SIFS_CCK_TRX 16
	250	#define BIT_SHIFT_SIFS_OFDM_TRX 24
	251	#define REG_SLOT 0x051B
	252	#define REG_TX_PTCL_CTRL 0x0520
	253	#define BIT_SIFS_BK_EN BIT(12)
	254	#define REG_TXPAUSE 0x0522
	255	#define REG_RD_CTRL 0x0524
	256	#define BIT_DIS_TXOP_CFE BIT(10)
	257	#define BIT_DIS_LSIG_CFE BIT(9)
	258	#define BIT_DIS_STBC_CFE BIT(8)
	259	#define REG_TBTT_PROHIBIT 0x0540
	260	#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
	261	#define REG_RD_NAV_NXT 0x0544
	262	#define REG_BCN_CTRL 0x0550
	263	#define BIT_DIS_TSF_UDT BIT(4)
	264	#define BIT_EN_BCN_FUNCTION BIT(3)
	265	#define REG_BCN_CTRL_CLINT0 0x0551
	266	#define REG_DRVERLYINT 0x0558
	267	#define REG_BCNDMATIM 0x0559
	268	#define REG_USTIME_TSF 0x055C
	269	#define REG_BCN_MAX_ERR 0x055D
	270	#define REG_RXTSF_OFFSET_CCK 0x055E
	271	#define REG_MISC_CTRL 0x0577
	272	#define BIT_EN_FREE_CNT BIT(3)
	273	#define BIT_DIS_SECOND_CCA (BIT(0) \| BIT(1))
	274	#define REG_TIMER0_SRC_SEL 0x05B4
	275	#define BIT_TSFT_SEL_TIMER0 (BIT(4) \| BIT(5) \| BIT(6))
	276
	277	#define REG_TCR 0x0604
3a2dd6b7	278	#define BIT_PWRMGT_HWDATA_EN BIT(7)
e3037485 YHC	279	#define REG_RCR 0x0608
	280	#define BIT_APP_FCS BIT(31)
	281	#define BIT_APP_MIC BIT(30)
	282	#define BIT_APP_ICV BIT(29)
	283	#define BIT_APP_PHYSTS BIT(28)
	284	#define BIT_APP_BASSN BIT(27)
	285	#define BIT_VHT_DACK BIT(26)
	286	#define BIT_TCPOFLD_EN BIT(25)
	287	#define BIT_ENMBID BIT(24)
	288	#define BIT_LSIGEN BIT(23)
	289	#define BIT_MFBEN BIT(22)
	290	#define BIT_DISCHKPPDLLEN BIT(21)
	291	#define BIT_PKTCTL_DLEN BIT(20)
	292	#define BIT_TIM_PARSER_EN BIT(18)
	293	#define BIT_BC_MD_EN BIT(17)
	294	#define BIT_UC_MD_EN BIT(16)
	295	#define BIT_RXSK_PERPKT BIT(15)
	296	#define BIT_HTC_LOC_CTRL BIT(14)
	297	#define BIT_RPFM_CAM_ENABLE BIT(12)
	298	#define BIT_TA_BCN BIT(11)
	299	#define BIT_DISDECMYPKT BIT(10)
	300	#define BIT_AICV BIT(9)
	301	#define BIT_ACRC32 BIT(8)
	302	#define BIT_CBSSID_BCN BIT(7)
	303	#define BIT_CBSSID_DATA BIT(6)
	304	#define BIT_APWRMGT BIT(5)
	305	#define BIT_ADD3 BIT(4)
	306	#define BIT_AB BIT(3)
	307	#define BIT_AM BIT(2)
	308	#define BIT_APM BIT(1)
	309	#define BIT_AAP BIT(0)
	310	#define REG_RX_PKT_LIMIT 0x060C
	311	#define REG_RX_DRVINFO_SZ 0x060F
	312	#define BIT_APP_PHYSTS BIT(28)
27c65bfc	313	#define REG_MAR 0x0620
e3037485 YHC	314	#define REG_USTIME_EDCA 0x0638
	315	#define REG_ACKTO_CCK 0x0639
	316	#define REG_RESP_SIFS_CCK 0x063C
	317	#define REG_RESP_SIFS_OFDM 0x063E
	318	#define REG_ACKTO 0x0640
	319	#define REG_EIFS 0x0642
	320	#define REG_NAV_CTRL 0x0650
	321	#define REG_WMAC_TRXPTCL_CTL 0x0668
	322	#define BIT_RFMOD (BIT(7) \| BIT(8))
	323	#define BIT_RFMOD_80M BIT(8)
	324	#define BIT_RFMOD_40M BIT(7)
	325	#define REG_WMAC_TRXPTCL_CTL_H 0x066C
	326	#define REG_RXFLTMAP0 0x06A0
	327	#define REG_RXFLTMAP1 0x06A2
	328	#define REG_RXFLTMAP2 0x06A4
0bd95573	329	#define REG_RXFLTMAP4 0x068A
4136214f YHC	330	#define REG_BT_COEX_TABLE0 0x06C0
	331	#define REG_BT_COEX_TABLE1 0x06C4
	332	#define REG_BT_COEX_BRK_TABLE 0x06C8
	333	#define REG_BT_COEX_TABLE_H 0x06CC
	334	#define REG_BT_COEX_TABLE_H1 0x06CD
	335	#define REG_BT_COEX_TABLE_H2 0x06CE
	336	#define REG_BT_COEX_TABLE_H3 0x06CF
e3037485 YHC	337	#define REG_BBPSF_CTRL 0x06DC
e3037485 YHC	338
4136214f YHC	339	#define REG_BT_COEX_V2 0x0763
	340	#define BIT_GNT_BT_POLARITY BIT(4)
	341	#define BIT_LTE_COEX_EN BIT(7)
	342	#define REG_BT_STAT_CTRL 0x0778
	343	#define REG_BT_TDMA_TIME 0x0790
e3037485 YHC	344	#define REG_WMAC_OPTION_FUNCTION 0x07D0
	345	#define REG_WMAC_OPTION_FUNCTION_1 0x07D4
	346
4136214f YHC	347	#define REG_RX_GAIN_EN 0x081c
	348
	349	#define REG_RFE_CTRL_E 0x0974
	350
5227c2ee TEH	351	#define REG_DIS_DPD 0x0a70
	352	#define DIS_DPD_MASK GENMASK(9, 0)
	353	#define DIS_DPD_RATE6M BIT(0)
	354	#define DIS_DPD_RATE9M BIT(1)
	355	#define DIS_DPD_RATEMCS0 BIT(2)
	356	#define DIS_DPD_RATEMCS1 BIT(3)
	357	#define DIS_DPD_RATEMCS8 BIT(4)
	358	#define DIS_DPD_RATEMCS9 BIT(5)
	359	#define DIS_DPD_RATEVHT1SS_MCS0 BIT(6)
	360	#define DIS_DPD_RATEVHT1SS_MCS1 BIT(7)
	361	#define DIS_DPD_RATEVHT2SS_MCS0 BIT(8)
	362	#define DIS_DPD_RATEVHT2SS_MCS1 BIT(9)
	363	#define DIS_DPD_RATEALL GENMASK(9, 0)
	364
4136214f YHC	365	#define REG_RFE_CTRL8 0x0cb4
	366	#define BIT_MASK_RFE_SEL89 GENMASK(7, 0)
	367	#define REG_RFE_INV8 0x0cbd
	368	#define BIT_MASK_RFE_INV89 GENMASK(1, 0)
	369	#define REG_RFE_INV16 0x0cbe
	370	#define BIT_RFE_BUF_EN BIT(3)
	371
e3037485 YHC	372	#define REG_ANAPAR_XTAL_0 0x1040
	373	#define REG_CPU_DMEM_CON 0x1080
	374	#define BIT_WL_PLATFORM_RST BIT(16)
	375	#define BIT_WL_SECURITY_CLK BIT(15)
	376	#define BIT_DDMA_EN BIT(8)
	377
	378	#define REG_H2C_PKT_READADDR 0x10D0
	379	#define REG_H2C_PKT_WRITEADDR 0x10D4
	380	#define REG_FW_DBG7 0x10FC
	381	#define FW_KEY_MASK 0xffffff00
	382
	383	#define REG_CR_EXT 0x1100
	384
	385	#define REG_DDMA_CH0SA 0x1200
	386	#define REG_DDMA_CH0DA 0x1204
	387	#define REG_DDMA_CH0CTRL 0x1208
	388	#define BIT_DDMACH0_OWN BIT(31)
	389	#define BIT_DDMACH0_CHKSUM_EN BIT(29)
	390	#define BIT_DDMACH0_CHKSUM_STS BIT(27)
	391	#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)
	392	#define BIT_DDMACH0_CHKSUM_CONT BIT(24)
	393	#define BIT_MASK_DDMACH0_DLEN 0x3ffff
	394
	395	#define REG_H2CQ_CSR 0x1330
	396	#define BIT_H2CQ_FULL BIT(31)
	397	#define REG_FAST_EDCA_VOVI_SETTING 0x1448
	398	#define REG_FAST_EDCA_BEBK_SETTING 0x144C
	399
	400	#define REG_RXPSF_CTRL 0x1610
	401	#define BIT_RXGCK_FIFOTHR_EN BIT(28)
	402
	403	#define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26
	404	#define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3
	405	#define BIT_RXGCK_VHT_FIFOTHR(x) \
	406	(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
	407	#define BITS_RXGCK_VHT_FIFOTHR \
	408	(BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
	409
	410	#define BIT_SHIFT_RXGCK_HT_FIFOTHR 24
	411	#define BIT_MASK_RXGCK_HT_FIFOTHR 0x3
	412	#define BIT_RXGCK_HT_FIFOTHR(x) \
	413	(((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)
	414	#define BITS_RXGCK_HT_FIFOTHR \
	415	(BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)
	416
	417	#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22
	418	#define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3
	419	#define BIT_RXGCK_OFDM_FIFOTHR(x) \
	420	(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
	421	#define BITS_RXGCK_OFDM_FIFOTHR \
	422	(BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
	423
	424	#define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20
	425	#define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3
	426	#define BIT_RXGCK_CCK_FIFOTHR(x) \
	427	(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
	428	#define BITS_RXGCK_CCK_FIFOTHR \
	429	(BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
	430
	431	#define BIT_RXGCK_OFDMCCA_EN BIT(16)
	432
	433	#define BIT_SHIFT_RXPSF_PKTLENTHR 13
	434	#define BIT_MASK_RXPSF_PKTLENTHR 0x7
	435	#define BIT_RXPSF_PKTLENTHR(x) \
436	(((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)
437	#define BITS_RXPSF_PKTLENTHR \
438	(BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)
439	#define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR))
440	#define BIT_SET_RXPSF_PKTLENTHR(x, v) \
441	(BIT_CLEAR_RXPSF_PKTLENTHR(x) \| BIT_RXPSF_PKTLENTHR(v))
442
443	#define BIT_RXPSF_CTRLEN BIT(12)
444	#define BIT_RXPSF_VHTCHKEN BIT(11)
445	#define BIT_RXPSF_HTCHKEN BIT(10)
446	#define BIT_RXPSF_OFDMCHKEN BIT(9)
447	#define BIT_RXPSF_CCKCHKEN BIT(8)
448	#define BIT_RXPSF_OFDMRST BIT(7)
449	#define BIT_RXPSF_CCKRST BIT(6)
450	#define BIT_RXPSF_MHCHKEN BIT(5)
451	#define BIT_RXPSF_CONT_ERRCHKEN BIT(4)
452	#define BIT_RXPSF_ALL_ERRCHKEN BIT(3)
453
454	#define BIT_SHIFT_RXPSF_ERRTHR 0
455	#define BIT_MASK_RXPSF_ERRTHR 0x7
456	#define BIT_RXPSF_ERRTHR(x) \
457	(((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)
458	#define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)
459	#define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR))
460	#define BIT_GET_RXPSF_ERRTHR(x) \
461	(((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)
462	#define BIT_SET_RXPSF_ERRTHR(x, v) \
463	(BIT_CLEAR_RXPSF_ERRTHR(x) \| BIT_RXPSF_ERRTHR(v))
464
465	#define REG_RXPSF_TYPE_CTRL 0x1614
466	#define REG_GENERAL_OPTION 0x1664
467	#define BIT_DUMMY_FCS_READY_MASK_EN BIT(9)
468
469	#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700
470	#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704
471	#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708
472	#define LTECOEX_READY BIT(29)
473	#define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1
474	#define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
475	#define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1
476
4136214f YHC	477	#define REG_IGN_GNT_BT1 0x1860
	478
	479	#define REG_RFESEL_CTRL 0x1990
	480
	481	#define REG_NOMASK_TXBT 0x1ca7
	482	#define REG_ANAPAR 0x1c30
	483	#define BIT_ANAPAR_BTPS BIT(22)
	484	#define REG_RSTB_SEL 0x1c38
	485
	486	#define REG_IGN_GNTBT4 0x4160
	487
	488	#define RF_MODOPT 0x01
e3037485 YHC	489	#define RF_DTXLOK 0x08
e3037485 YHC	490	#define RF_CFGCH 0x18
4136214f	491	#define RF_RCK 0x1d
e3037485 YHC	492	#define RF_LUTWA 0x33
	493	#define RF_LUTWD1 0x3e
	494	#define RF_LUTWD0 0x3f
5227c2ee	495	#define RF_T_METER 0x42
e3037485 YHC	496	#define RF_XTALX2 0xb8
e3037485 YHC	497	#define RF_MALSEL 0xbe
4136214f	498	#define RF_RCKD 0xde
e3037485 YHC	499	#define RF_LUTDBG 0xdf
	500	#define RF_LUTWE2 0xee
	501	#define RF_LUTWE 0xef
	502
4136214f YHC	503	#define LTE_COEX_CTRL 0x38
	504	#define LTE_WL_TRX_CTRL 0xa0
	505	#define LTE_BT_TRX_CTRL 0xa4
	506
e3037485	507	#endif