[linux-2.6-block.git] / drivers / net / wireless / ralink / rt2x00 / rt2800pci.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
	Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
	Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
	Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
	Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
	Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
	Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
	Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
	Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
	<http://rt2x00.serialmonkey.com>

 */

/*
	Module: rt2800pci
	Abstract: rt2800pci device specific routines.
	Supported chipsets: RT2800E & RT2800ED.
 */

#include <linux/delay.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/eeprom_93cx6.h>

#include "rt2x00.h"
#include "rt2x00mmio.h"
#include "rt2x00pci.h"
#include "rt2800lib.h"
#include "rt2800mmio.h"
#include "rt2800.h"
#include "rt2800pci.h"

/*
 * Allow hardware encryption to be disabled.
 */
static bool modparam_nohwcrypt = false;
module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444);
MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");

static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
{
	return modparam_nohwcrypt;
}

static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
{
	unsigned int i;
	u32 reg;

	/*
	 * SOC devices don't support MCU requests.
	 */
	if (rt2x00_is_soc(rt2x00dev))
		return;

	for (i = 0; i < 200; i++) {
		reg = rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID);

		if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
		    (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
		    (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
		    (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
			break;

		udelay(REGISTER_BUSY_DELAY);
	}

	if (i == 200)
		rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");

	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
}

static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
{
	struct rt2x00_dev *rt2x00dev = eeprom->data;
	u32 reg;

	reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);

	eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
	eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
	eeprom->reg_data_clock =
	    !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
	eeprom->reg_chip_select =
	    !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
}

static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
{
	struct rt2x00_dev *rt2x00dev = eeprom->data;
	u32 reg = 0;

	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
			   !!eeprom->reg_data_clock);
	rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
			   !!eeprom->reg_chip_select);

	rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
}

static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
{
	struct eeprom_93cx6 eeprom;
	u32 reg;

	reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);

	eeprom.data = rt2x00dev;
	eeprom.register_read = rt2800pci_eepromregister_read;
	eeprom.register_write = rt2800pci_eepromregister_write;
	switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
	{
	case 0:
		eeprom.width = PCI_EEPROM_WIDTH_93C46;
		break;
	case 1:
		eeprom.width = PCI_EEPROM_WIDTH_93C66;
		break;
	default:
		eeprom.width = PCI_EEPROM_WIDTH_93C86;
		break;
	}
	eeprom.reg_data_in = 0;
	eeprom.reg_data_out = 0;
	eeprom.reg_data_clock = 0;
	eeprom.reg_chip_select = 0;

	eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
			       EEPROM_SIZE / sizeof(u16));

	return 0;
}

static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
{
	return rt2800_efuse_detect(rt2x00dev);
}

static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
{
	return rt2800_read_eeprom_efuse(rt2x00dev);
}

/*
 * Firmware functions
 */
static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
{
	/*
	 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
	 */
	if (rt2x00_rt(rt2x00dev, RT3290))
		return FIRMWARE_RT3290;
	else
		return FIRMWARE_RT2860;
}

static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
				    const u8 *data, const size_t len)
{
	u32 reg;

	/*
	 * enable Host program ram write selection
	 */
	reg = 0;
	rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);

	/*
	 * Write firmware to device.
	 */
	rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
				       data, len);

	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);

	rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);

	return 0;
}

/*
 * Device state switch handlers.
 */
static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
{
	int retval;

	retval = rt2800mmio_enable_radio(rt2x00dev);
	if (retval)
		return retval;

	/* After resume MCU_BOOT_SIGNAL will trash these. */
	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);

	rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
	rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);

	rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
	rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);

	return retval;
}

static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
			       enum dev_state state)
{
	if (state == STATE_AWAKE) {
		rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
				   0, 0x02);
		rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
	} else if (state == STATE_SLEEP) {
		rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
					  0xffffffff);
		rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
					  0xffffffff);
		rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
				   0xff, 0x01);
	}

	return 0;
}

static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
				      enum dev_state state)
{
	int retval = 0;

	switch (state) {
	case STATE_RADIO_ON:
		retval = rt2800pci_enable_radio(rt2x00dev);
		break;
	case STATE_RADIO_OFF:
		/*
		 * After the radio has been disabled, the device should
		 * be put to sleep for powersaving.
		 */
		rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
		break;
	case STATE_RADIO_IRQ_ON:
	case STATE_RADIO_IRQ_OFF:
		rt2800mmio_toggle_irq(rt2x00dev, state);
		break;
	case STATE_DEEP_SLEEP:
	case STATE_SLEEP:
	case STATE_STANDBY:
	case STATE_AWAKE:
		retval = rt2800pci_set_state(rt2x00dev, state);
		break;
	default:
		retval = -ENOTSUPP;
		break;
	}

	if (unlikely(retval))
		rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
			   state, retval);

	return retval;
}

/*
 * Device probe functions.
 */
static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
{
	int retval;

	if (rt2800pci_efuse_detect(rt2x00dev))
		retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
	else
		retval = rt2800pci_read_eeprom_pci(rt2x00dev);

	return retval;
}

static const struct ieee80211_ops rt2800pci_mac80211_ops = {
	.tx			= rt2x00mac_tx,
	.start			= rt2x00mac_start,
	.stop			= rt2x00mac_stop,
	.add_interface		= rt2x00mac_add_interface,
	.remove_interface	= rt2x00mac_remove_interface,
	.config			= rt2x00mac_config,
	.configure_filter	= rt2x00mac_configure_filter,
	.set_key		= rt2x00mac_set_key,
	.sw_scan_start		= rt2x00mac_sw_scan_start,
	.sw_scan_complete	= rt2x00mac_sw_scan_complete,
	.get_stats		= rt2x00mac_get_stats,
	.get_key_seq		= rt2800_get_key_seq,
	.set_rts_threshold	= rt2800_set_rts_threshold,
	.sta_add		= rt2800_sta_add,
	.sta_remove		= rt2800_sta_remove,
	.bss_info_changed	= rt2x00mac_bss_info_changed,
	.conf_tx		= rt2800_conf_tx,
	.get_tsf		= rt2800_get_tsf,
	.rfkill_poll		= rt2x00mac_rfkill_poll,
	.ampdu_action		= rt2800_ampdu_action,
	.flush			= rt2x00mac_flush,
	.get_survey		= rt2800_get_survey,
	.get_ringparam		= rt2x00mac_get_ringparam,
	.tx_frames_pending	= rt2x00mac_tx_frames_pending,
};

static const struct rt2800_ops rt2800pci_rt2800_ops = {
	.register_read		= rt2x00mmio_register_read,
	.register_read_lock	= rt2x00mmio_register_read, /* same for PCI */
	.register_write		= rt2x00mmio_register_write,
	.register_write_lock	= rt2x00mmio_register_write, /* same for PCI */
	.register_multiread	= rt2x00mmio_register_multiread,
	.register_multiwrite	= rt2x00mmio_register_multiwrite,
	.regbusy_read		= rt2x00mmio_regbusy_read,
	.read_eeprom		= rt2800pci_read_eeprom,
	.hwcrypt_disabled	= rt2800pci_hwcrypt_disabled,
	.drv_write_firmware	= rt2800pci_write_firmware,
	.drv_init_registers	= rt2800mmio_init_registers,
	.drv_get_txwi		= rt2800mmio_get_txwi,
};

static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
	.irq_handler		= rt2800mmio_interrupt,
	.txstatus_tasklet	= rt2800mmio_txstatus_tasklet,
	.pretbtt_tasklet	= rt2800mmio_pretbtt_tasklet,
	.tbtt_tasklet		= rt2800mmio_tbtt_tasklet,
	.rxdone_tasklet		= rt2800mmio_rxdone_tasklet,
	.autowake_tasklet	= rt2800mmio_autowake_tasklet,
	.probe_hw		= rt2800mmio_probe_hw,
	.get_firmware_name	= rt2800pci_get_firmware_name,
	.check_firmware		= rt2800_check_firmware,
	.load_firmware		= rt2800_load_firmware,
	.initialize		= rt2x00mmio_initialize,
	.uninitialize		= rt2x00mmio_uninitialize,
	.get_entry_state	= rt2800mmio_get_entry_state,
	.clear_entry		= rt2800mmio_clear_entry,
	.set_device_state	= rt2800pci_set_device_state,
	.rfkill_poll		= rt2800_rfkill_poll,
	.link_stats		= rt2800_link_stats,
	.reset_tuner		= rt2800_reset_tuner,
	.link_tuner		= rt2800_link_tuner,
	.gain_calibration	= rt2800_gain_calibration,
	.vco_calibration	= rt2800_vco_calibration,
	.start_queue		= rt2800mmio_start_queue,
	.kick_queue		= rt2800mmio_kick_queue,
	.stop_queue		= rt2800mmio_stop_queue,
	.flush_queue		= rt2800mmio_flush_queue,
	.write_tx_desc		= rt2800mmio_write_tx_desc,
	.write_tx_data		= rt2800_write_tx_data,
	.write_beacon		= rt2800_write_beacon,
	.clear_beacon		= rt2800_clear_beacon,
	.fill_rxdone		= rt2800mmio_fill_rxdone,
	.config_shared_key	= rt2800_config_shared_key,
	.config_pairwise_key	= rt2800_config_pairwise_key,
	.config_filter		= rt2800_config_filter,
	.config_intf		= rt2800_config_intf,
	.config_erp		= rt2800_config_erp,
	.config_ant		= rt2800_config_ant,
	.config			= rt2800_config,
};

static const struct rt2x00_ops rt2800pci_ops = {
	.name			= KBUILD_MODNAME,
	.drv_data_size		= sizeof(struct rt2800_drv_data),
	.max_ap_intf		= 8,
	.eeprom_size		= EEPROM_SIZE,
	.rf_size		= RF_SIZE,
	.tx_queues		= NUM_TX_QUEUES,
	.queue_init		= rt2800mmio_queue_init,
	.lib			= &rt2800pci_rt2x00_ops,
	.drv			= &rt2800pci_rt2800_ops,
	.hw			= &rt2800pci_mac80211_ops,
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
	.debugfs		= &rt2800_rt2x00debug,
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
};

/*
 * RT2800pci module information.
 */
static const struct pci_device_id rt2800pci_device_table[] = {
	{ PCI_DEVICE(0x1814, 0x0601) },
	{ PCI_DEVICE(0x1814, 0x0681) },
	{ PCI_DEVICE(0x1814, 0x0701) },
	{ PCI_DEVICE(0x1814, 0x0781) },
	{ PCI_DEVICE(0x1814, 0x3090) },
	{ PCI_DEVICE(0x1814, 0x3091) },
	{ PCI_DEVICE(0x1814, 0x3092) },
	{ PCI_DEVICE(0x1432, 0x7708) },
	{ PCI_DEVICE(0x1432, 0x7727) },
	{ PCI_DEVICE(0x1432, 0x7728) },
	{ PCI_DEVICE(0x1432, 0x7738) },
	{ PCI_DEVICE(0x1432, 0x7748) },
	{ PCI_DEVICE(0x1432, 0x7758) },
	{ PCI_DEVICE(0x1432, 0x7768) },
	{ PCI_DEVICE(0x1462, 0x891a) },
	{ PCI_DEVICE(0x1a3b, 0x1059) },
#ifdef CONFIG_RT2800PCI_RT3290
	{ PCI_DEVICE(0x1814, 0x3290) },
#endif
#ifdef CONFIG_RT2800PCI_RT33XX
	{ PCI_DEVICE(0x1814, 0x3390) },
#endif
#ifdef CONFIG_RT2800PCI_RT35XX
	{ PCI_DEVICE(0x1432, 0x7711) },
	{ PCI_DEVICE(0x1432, 0x7722) },
	{ PCI_DEVICE(0x1814, 0x3060) },
	{ PCI_DEVICE(0x1814, 0x3062) },
	{ PCI_DEVICE(0x1814, 0x3562) },
	{ PCI_DEVICE(0x1814, 0x3592) },
	{ PCI_DEVICE(0x1814, 0x3593) },
	{ PCI_DEVICE(0x1814, 0x359f) },
#endif
#ifdef CONFIG_RT2800PCI_RT53XX
	{ PCI_DEVICE(0x1814, 0x5360) },
	{ PCI_DEVICE(0x1814, 0x5362) },
	{ PCI_DEVICE(0x1814, 0x5390) },
	{ PCI_DEVICE(0x1814, 0x5392) },
	{ PCI_DEVICE(0x1814, 0x539a) },
	{ PCI_DEVICE(0x1814, 0x539b) },
	{ PCI_DEVICE(0x1814, 0x539f) },
#endif
	{ 0, }
};

MODULE_AUTHOR(DRV_PROJECT);
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
MODULE_FIRMWARE(FIRMWARE_RT2860);
MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
MODULE_LICENSE("GPL");

static int rt2800pci_probe(struct pci_dev *pci_dev,
			   const struct pci_device_id *id)
{
	return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
}

static struct pci_driver rt2800pci_driver = {
	.name		= KBUILD_MODNAME,
	.id_table	= rt2800pci_device_table,
	.probe		= rt2800pci_probe,
	.remove		= rt2x00pci_remove,
	.suspend	= rt2x00pci_suspend,
	.resume		= rt2x00pci_resume,
};

module_pci_driver(rt2800pci_driver);
Commit	Line	Data
1ccea77e	1	// SPDX-License-Identifier: GPL-2.0-or-later
a9b3a9f7	2	/*
96481b20	3	Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 GW	4	Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
	5	Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
	6	Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
	7	Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
	8	Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
	9	Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
	10	Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
a9b3a9f7 ID	11	<http://rt2x00.serialmonkey.com>
a9b3a9f7 ID	12
a9b3a9f7 ID	13	*/
	14
	15	/*
	16	Module: rt2800pci
	17	Abstract: rt2800pci device specific routines.
	18	Supported chipsets: RT2800E & RT2800ED.
	19	*/
	20
a9b3a9f7 ID	21	#include <linux/delay.h>
	22	#include <linux/etherdevice.h>
	23	#include <linux/init.h>
	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/pci.h>
a9b3a9f7 ID	27	#include <linux/eeprom_93cx6.h>
	28
	29	#include "rt2x00.h"
69a2bac8	30	#include "rt2x00mmio.h"
a9b3a9f7	31	#include "rt2x00pci.h"
7ef5cc92	32	#include "rt2800lib.h"
0bc202b3	33	#include "rt2800mmio.h"
b54f78a8	34	#include "rt2800.h"
a9b3a9f7 ID	35	#include "rt2800pci.h"
a9b3a9f7 ID	36
a9b3a9f7 ID	37	/*
	38	* Allow hardware encryption to be disabled.
	39	*/
eb939922	40	static bool modparam_nohwcrypt = false;
2ef00c53	41	module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444);
a9b3a9f7 ID	42	MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
a9b3a9f7 ID	43
ad417a53 GW	44	static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
	45	{
	46	return modparam_nohwcrypt;
	47	}
	48
a9b3a9f7 ID	49	static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
	50	{
	51	unsigned int i;
	52	u32 reg;
	53
f18d4463 LC	54	/*
	55	* SOC devices don't support MCU requests.
	56	*/
	57	if (rt2x00_is_soc(rt2x00dev))
	58	return;
	59
a9b3a9f7	60	for (i = 0; i < 200; i++) {
3954b4e3	61	reg = rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID);
a9b3a9f7 ID	62
	63	if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) \|\|
	64	(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) \|\|
	65	(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) \|\|
	66	(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
	67	break;
	68
	69	udelay(REGISTER_BUSY_DELAY);
	70	}
	71
	72	if (i == 200)
ec9c4989	73	rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
a9b3a9f7	74
b9570b66 GJ	75	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
b9570b66 GJ	76	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
a9b3a9f7 ID	77	}
a9b3a9f7 ID	78
a9b3a9f7 ID	79	static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
	80	{
	81	struct rt2x00_dev *rt2x00dev = eeprom->data;
	82	u32 reg;
	83
3954b4e3	84	reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
a9b3a9f7 ID	85
	86	eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
	87	eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
	88	eeprom->reg_data_clock =
	89	!!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
	90	eeprom->reg_chip_select =
	91	!!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
	92	}
	93
	94	static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
	95	{
	96	struct rt2x00_dev *rt2x00dev = eeprom->data;
	97	u32 reg = 0;
	98
	99	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
	100	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
	101	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
	102	!!eeprom->reg_data_clock);
	103	rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
	104	!!eeprom->reg_chip_select);
	105
b9570b66	106	rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
a9b3a9f7 ID	107	}
a9b3a9f7 ID	108
a02308e9	109	static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
a9b3a9f7 ID	110	{
	111	struct eeprom_93cx6 eeprom;
	112	u32 reg;
	113
3954b4e3	114	reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
a9b3a9f7 ID	115
	116	eeprom.data = rt2x00dev;
	117	eeprom.register_read = rt2800pci_eepromregister_read;
	118	eeprom.register_write = rt2800pci_eepromregister_write;
20f8b139 GW	119	switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
	120	{
	121	case 0:
	122	eeprom.width = PCI_EEPROM_WIDTH_93C46;
	123	break;
	124	case 1:
	125	eeprom.width = PCI_EEPROM_WIDTH_93C66;
	126	break;
	127	default:
	128	eeprom.width = PCI_EEPROM_WIDTH_93C86;
	129	break;
	130	}
a9b3a9f7 ID	131	eeprom.reg_data_in = 0;
	132	eeprom.reg_data_out = 0;
	133	eeprom.reg_data_clock = 0;
	134	eeprom.reg_chip_select = 0;
	135
	136	eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
	137	EEPROM_SIZE / sizeof(u16));
a02308e9 GJ	138
a02308e9 GJ	139	return 0;
a9b3a9f7 ID	140	}
a9b3a9f7 ID	141
a6598682 GW	142	static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
a6598682 GW	143	{
30e84034	144	return rt2800_efuse_detect(rt2x00dev);
a9b3a9f7 ID	145	}
a9b3a9f7 ID	146
a02308e9	147	static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
a9b3a9f7	148	{
a02308e9	149	return rt2800_read_eeprom_efuse(rt2x00dev);
a9b3a9f7	150	}
a9b3a9f7	151
a9b3a9f7 ID	152	/*
	153	* Firmware functions
	154	*/
	155	static char rt2800pci_get_firmware_name(struct rt2x00_dev rt2x00dev)
	156	{
a89534ed WH	157	/*
	158	* Chip rt3290 use specific 4KB firmware named rt3290.bin.
	159	*/
	160	if (rt2x00_rt(rt2x00dev, RT3290))
	161	return FIRMWARE_RT3290;
	162	else
	163	return FIRMWARE_RT2860;
a9b3a9f7 ID	164	}
a9b3a9f7 ID	165
f31c9a8c	166	static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
a9b3a9f7 ID	167	const u8 *data, const size_t len)
a9b3a9f7 ID	168	{
a9b3a9f7 ID	169	u32 reg;
a9b3a9f7 ID	170
a9b3a9f7 ID	171	/*
	172	* enable Host program ram write selection
	173	*/
	174	reg = 0;
	175	rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
b9570b66	176	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
a9b3a9f7 ID	177
	178	/*
	179	* Write firmware to device.
	180	*/
b9570b66 GJ	181	rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
b9570b66 GJ	182	data, len);
a9b3a9f7	183
b9570b66 GJ	184	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
b9570b66 GJ	185	rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
a9b3a9f7	186
b9570b66 GJ	187	rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
b9570b66 GJ	188	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
a9b3a9f7 ID	189
	190	return 0;
	191	}
	192
a9b3a9f7 ID	193	/*
	194	* Device state switch handlers.
	195	*/
1e7d3035 GJ	196	static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
	197	{
	198	int retval;
	199
	200	retval = rt2800mmio_enable_radio(rt2x00dev);
e8b461c3 JK	201	if (retval)
	202	return retval;
	203
	204	/* After resume MCU_BOOT_SIGNAL will trash these. */
b9570b66 GJ	205	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
b9570b66 GJ	206	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
e8b461c3 JK	207
	208	rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
	209	rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
	210
	211	rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
	212	rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
	213
	214	return retval;
a9b3a9f7 ID	215	}
a9b3a9f7 ID	216
a9b3a9f7 ID	217	static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
	218	enum dev_state state)
	219	{
a9b3a9f7	220	if (state == STATE_AWAKE) {
09a3311c JK	221	rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
	222	0, 0x02);
	223	rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
7f6e144f	224	} else if (state == STATE_SLEEP) {
b9570b66 GJ	225	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
	226	0xffffffff);
	227	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
	228	0xffffffff);
09a3311c JK	229	rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
09a3311c JK	230	0xff, 0x01);
a9b3a9f7 ID	231	}
	232
	233	return 0;
	234	}
	235
	236	static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
	237	enum dev_state state)
	238	{
	239	int retval = 0;
	240
	241	switch (state) {
	242	case STATE_RADIO_ON:
a9b3a9f7 ID	243	retval = rt2800pci_enable_radio(rt2x00dev);
	244	break;
	245	case STATE_RADIO_OFF:
	246	/*
	247	* After the radio has been disabled, the device should
	248	* be put to sleep for powersaving.
	249	*/
a9b3a9f7 ID	250	rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
a9b3a9f7 ID	251	break;
a9b3a9f7 ID	252	case STATE_RADIO_IRQ_ON:
a9b3a9f7 ID	253	case STATE_RADIO_IRQ_OFF:
b5cfde3f	254	rt2800mmio_toggle_irq(rt2x00dev, state);
a9b3a9f7 ID	255	break;
	256	case STATE_DEEP_SLEEP:
	257	case STATE_SLEEP:
	258	case STATE_STANDBY:
	259	case STATE_AWAKE:
	260	retval = rt2800pci_set_state(rt2x00dev, state);
	261	break;
	262	default:
	263	retval = -ENOTSUPP;
	264	break;
	265	}
	266
	267	if (unlikely(retval))
ec9c4989 JP	268	rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
ec9c4989 JP	269	state, retval);
a9b3a9f7 ID	270
	271	return retval;
	272	}
	273
a9b3a9f7 ID	274	/*
	275	* Device probe functions.
	276	*/
a02308e9	277	static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
7ab71325	278	{
a02308e9 GJ	279	int retval;
a02308e9 GJ	280
68597ea8	281	if (rt2800pci_efuse_detect(rt2x00dev))
a02308e9	282	retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
cea90e55	283	else
a02308e9 GJ	284	retval = rt2800pci_read_eeprom_pci(rt2x00dev);
	285
	286	return retval;
a9b3a9f7 ID	287	}
a9b3a9f7 ID	288
e783619e HS	289	static const struct ieee80211_ops rt2800pci_mac80211_ops = {
	290	.tx = rt2x00mac_tx,
	291	.start = rt2x00mac_start,
	292	.stop = rt2x00mac_stop,
	293	.add_interface = rt2x00mac_add_interface,
	294	.remove_interface = rt2x00mac_remove_interface,
	295	.config = rt2x00mac_config,
	296	.configure_filter = rt2x00mac_configure_filter,
e783619e HS	297	.set_key = rt2x00mac_set_key,
	298	.sw_scan_start = rt2x00mac_sw_scan_start,
	299	.sw_scan_complete = rt2x00mac_sw_scan_complete,
	300	.get_stats = rt2x00mac_get_stats,
9352c19f	301	.get_key_seq = rt2800_get_key_seq,
e783619e	302	.set_rts_threshold = rt2800_set_rts_threshold,
9c87758c SG	303	.sta_add = rt2800_sta_add,
9c87758c SG	304	.sta_remove = rt2800_sta_remove,
e783619e HS	305	.bss_info_changed = rt2x00mac_bss_info_changed,
	306	.conf_tx = rt2800_conf_tx,
	307	.get_tsf = rt2800_get_tsf,
	308	.rfkill_poll = rt2x00mac_rfkill_poll,
	309	.ampdu_action = rt2800_ampdu_action,
f44df18c	310	.flush = rt2x00mac_flush,
977206d7	311	.get_survey = rt2800_get_survey,
e7dee444	312	.get_ringparam = rt2x00mac_get_ringparam,
5f0dd296	313	.tx_frames_pending = rt2x00mac_tx_frames_pending,
e783619e HS	314	};
e783619e HS	315
e796643e	316	static const struct rt2800_ops rt2800pci_rt2800_ops = {
3954b4e3 AB	317	.register_read = rt2x00mmio_register_read,
3954b4e3 AB	318	.register_read_lock = rt2x00mmio_register_read, /* same for PCI */
b9570b66 GJ	319	.register_write = rt2x00mmio_register_write,
	320	.register_write_lock = rt2x00mmio_register_write, /* same for PCI */
	321	.register_multiread = rt2x00mmio_register_multiread,
	322	.register_multiwrite = rt2x00mmio_register_multiwrite,
	323	.regbusy_read = rt2x00mmio_regbusy_read,
ad417a53 GW	324	.read_eeprom = rt2800pci_read_eeprom,
ad417a53 GW	325	.hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
e796643e	326	.drv_write_firmware = rt2800pci_write_firmware,
7573afdf	327	.drv_init_registers = rt2800mmio_init_registers,
45c67550	328	.drv_get_txwi = rt2800mmio_get_txwi,
e796643e ID	329	};
e796643e ID	330
a9b3a9f7	331	static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
b5cfde3f GJ	332	.irq_handler = rt2800mmio_interrupt,
	333	.txstatus_tasklet = rt2800mmio_txstatus_tasklet,
	334	.pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
	335	.tbtt_tasklet = rt2800mmio_tbtt_tasklet,
	336	.rxdone_tasklet = rt2800mmio_rxdone_tasklet,
	337	.autowake_tasklet = rt2800mmio_autowake_tasklet,
e5ceab9d	338	.probe_hw = rt2800mmio_probe_hw,
a9b3a9f7	339	.get_firmware_name = rt2800pci_get_firmware_name,
f31c9a8c ID	340	.check_firmware = rt2800_check_firmware,
f31c9a8c ID	341	.load_firmware = rt2800_load_firmware,
b9570b66 GJ	342	.initialize = rt2x00mmio_initialize,
b9570b66 GJ	343	.uninitialize = rt2x00mmio_uninitialize,
7573afdf GJ	344	.get_entry_state = rt2800mmio_get_entry_state,
7573afdf GJ	345	.clear_entry = rt2800mmio_clear_entry,
a9b3a9f7	346	.set_device_state = rt2800pci_set_device_state,
f4450616 BZ	347	.rfkill_poll = rt2800_rfkill_poll,
	348	.link_stats = rt2800_link_stats,
	349	.reset_tuner = rt2800_reset_tuner,
	350	.link_tuner = rt2800_link_tuner,
9e33a355	351	.gain_calibration = rt2800_gain_calibration,
2e9c43dd	352	.vco_calibration = rt2800_vco_calibration,
51e62469 GJ	353	.start_queue = rt2800mmio_start_queue,
	354	.kick_queue = rt2800mmio_kick_queue,
	355	.stop_queue = rt2800mmio_stop_queue,
02405644	356	.flush_queue = rt2800mmio_flush_queue,
45c67550	357	.write_tx_desc = rt2800mmio_write_tx_desc,
0c5879bc	358	.write_tx_data = rt2800_write_tx_data,
f0194b2d	359	.write_beacon = rt2800_write_beacon,
69cf36a4	360	.clear_beacon = rt2800_clear_beacon,
d10b7547	361	.fill_rxdone = rt2800mmio_fill_rxdone,
f4450616 BZ	362	.config_shared_key = rt2800_config_shared_key,
	363	.config_pairwise_key = rt2800_config_pairwise_key,
	364	.config_filter = rt2800_config_filter,
	365	.config_intf = rt2800_config_intf,
	366	.config_erp = rt2800_config_erp,
	367	.config_ant = rt2800_config_ant,
	368	.config = rt2800_config,
a9b3a9f7 ID	369	};
a9b3a9f7 ID	370
a9b3a9f7	371	static const struct rt2x00_ops rt2800pci_ops = {
04d0362e	372	.name = KBUILD_MODNAME,
3a1c0128	373	.drv_data_size = sizeof(struct rt2800_drv_data),
04d0362e GW	374	.max_ap_intf = 8,
	375	.eeprom_size = EEPROM_SIZE,
	376	.rf_size = RF_SIZE,
	377	.tx_queues = NUM_TX_QUEUES,
51e62469	378	.queue_init = rt2800mmio_queue_init,
04d0362e	379	.lib = &rt2800pci_rt2x00_ops,
e796643e	380	.drv = &rt2800pci_rt2800_ops,
e783619e	381	.hw = &rt2800pci_mac80211_ops,
a9b3a9f7	382	#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e	383	.debugfs = &rt2800_rt2x00debug,
a9b3a9f7 ID	384	#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
	385	};
	386
	387	/*
	388	* RT2800pci module information.
	389	*/
9baa3c34	390	static const struct pci_device_id rt2800pci_device_table[] = {
e01ae27f GW	391	{ PCI_DEVICE(0x1814, 0x0601) },
	392	{ PCI_DEVICE(0x1814, 0x0681) },
	393	{ PCI_DEVICE(0x1814, 0x0701) },
	394	{ PCI_DEVICE(0x1814, 0x0781) },
	395	{ PCI_DEVICE(0x1814, 0x3090) },
	396	{ PCI_DEVICE(0x1814, 0x3091) },
	397	{ PCI_DEVICE(0x1814, 0x3092) },
	398	{ PCI_DEVICE(0x1432, 0x7708) },
	399	{ PCI_DEVICE(0x1432, 0x7727) },
	400	{ PCI_DEVICE(0x1432, 0x7728) },
	401	{ PCI_DEVICE(0x1432, 0x7738) },
	402	{ PCI_DEVICE(0x1432, 0x7748) },
	403	{ PCI_DEVICE(0x1432, 0x7758) },
	404	{ PCI_DEVICE(0x1432, 0x7768) },
	405	{ PCI_DEVICE(0x1462, 0x891a) },
	406	{ PCI_DEVICE(0x1a3b, 0x1059) },
a89534ed WH	407	#ifdef CONFIG_RT2800PCI_RT3290
	408	{ PCI_DEVICE(0x1814, 0x3290) },
	409	#endif
f93bc9b3	410	#ifdef CONFIG_RT2800PCI_RT33XX
e01ae27f	411	{ PCI_DEVICE(0x1814, 0x3390) },
f93bc9b3	412	#endif
de1ebdce	413	#ifdef CONFIG_RT2800PCI_RT35XX
e01ae27f GW	414	{ PCI_DEVICE(0x1432, 0x7711) },
	415	{ PCI_DEVICE(0x1432, 0x7722) },
	416	{ PCI_DEVICE(0x1814, 0x3060) },
	417	{ PCI_DEVICE(0x1814, 0x3062) },
	418	{ PCI_DEVICE(0x1814, 0x3562) },
	419	{ PCI_DEVICE(0x1814, 0x3592) },
	420	{ PCI_DEVICE(0x1814, 0x3593) },
c4806014	421	{ PCI_DEVICE(0x1814, 0x359f) },
60687ba7 RST	422	#endif
60687ba7 RST	423	#ifdef CONFIG_RT2800PCI_RT53XX
ccf91bd6	424	{ PCI_DEVICE(0x1814, 0x5360) },
f57d7b6c	425	{ PCI_DEVICE(0x1814, 0x5362) },
e01ae27f	426	{ PCI_DEVICE(0x1814, 0x5390) },
f57d7b6c	427	{ PCI_DEVICE(0x1814, 0x5392) },
5126d97e	428	{ PCI_DEVICE(0x1814, 0x539a) },
2aed6915	429	{ PCI_DEVICE(0x1814, 0x539b) },
71e0b38c	430	{ PCI_DEVICE(0x1814, 0x539f) },
de1ebdce	431	#endif
a9b3a9f7 ID	432	{ 0, }
	433	};
	434
	435	MODULE_AUTHOR(DRV_PROJECT);
	436	MODULE_VERSION(DRV_VERSION);
	437	MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
	438	MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
a9b3a9f7 ID	439	MODULE_FIRMWARE(FIRMWARE_RT2860);
a9b3a9f7 ID	440	MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
a9b3a9f7 ID	441	MODULE_LICENSE("GPL");
a9b3a9f7 ID	442
e01ae27f GW	443	static int rt2800pci_probe(struct pci_dev *pci_dev,
	444	const struct pci_device_id *id)
	445	{
	446	return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
	447	}
	448
a9b3a9f7 ID	449	static struct pci_driver rt2800pci_driver = {
	450	.name = KBUILD_MODNAME,
	451	.id_table = rt2800pci_device_table,
e01ae27f	452	.probe = rt2800pci_probe,
69202359	453	.remove = rt2x00pci_remove,
a9b3a9f7 ID	454	.suspend = rt2x00pci_suspend,
	455	.resume = rt2x00pci_resume,
	456	};
fe7ef7c6	457
a1b13b9a	458	module_pci_driver(rt2800pci_driver);