[linux-2.6-block.git] / drivers / net / wireless / p54 / p54pci.c


/*
 * Linux device driver for PCI based Prism54
 *
 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
 * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
 *
 * Based on the islsm (softmac prism54) driver, which is:
 * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/firmware.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/completion.h>
#include <net/mac80211.h>

#include "p54.h"
#include "p54pci.h"

MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
MODULE_DESCRIPTION("Prism54 PCI wireless driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("prism54pci");

static struct pci_device_id p54p_table[] __devinitdata = {
	/* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3890) },
	/* 3COM 3CRWE154G72 Wireless LAN adapter */
	{ PCI_DEVICE(0x10b7, 0x6001) },
	/* Intersil PRISM Indigo Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3877) },
	/* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
	{ PCI_DEVICE(0x1260, 0x3886) },
	{ },
};

MODULE_DEVICE_TABLE(pci, p54p_table);

static int p54p_upload_firmware(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	const struct firmware *fw_entry = NULL;
	__le32 reg;
	int err;
	__le32 *data;
	u32 remains, left, device_addr;

	P54P_WRITE(int_enable, cpu_to_le32(0));
	P54P_READ(int_enable);
	udelay(10);

	reg = P54P_READ(ctrl_stat);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
	P54P_WRITE(ctrl_stat, reg);
	P54P_READ(ctrl_stat);
	udelay(10);

	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();

	err = request_firmware(&fw_entry, "isl3886", &priv->pdev->dev);
	if (err) {
		printk(KERN_ERR "%s (p54pci): cannot find firmware "
		       "(isl3886)\n", pci_name(priv->pdev));
		return err;
	}

	err = p54_parse_firmware(dev, fw_entry);
	if (err) {
		release_firmware(fw_entry);
		return err;
	}

	data = (__le32 *) fw_entry->data;
	remains = fw_entry->size;
	device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
	while (remains) {
		u32 i = 0;
		left = min((u32)0x1000, remains);
		P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
		P54P_READ(int_enable);

		device_addr += 0x1000;
		while (i < left) {
			P54P_WRITE(direct_mem_win[i], *data++);
			i += sizeof(u32);
		}

		remains -= left;
		P54P_READ(int_enable);
	}

	release_firmware(fw_entry);

	reg = P54P_READ(ctrl_stat);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
	P54P_WRITE(ctrl_stat, reg);
	P54P_READ(ctrl_stat);
	udelay(10);

	reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	P54P_WRITE(ctrl_stat, reg);
	wmb();
	udelay(10);

	/* wait for the firmware to boot properly */
	mdelay(100);

	return 0;
}

static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **rx_buf)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	u32 limit, idx, i;

	idx = le32_to_cpu(ring_control->host_idx[ring_index]);
	limit = idx;
	limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
	limit = ring_limit - limit;

	i = idx % ring_limit;
	while (limit-- > 1) {
		struct p54p_desc *desc = &ring[i];

		if (!desc->host_addr) {
			struct sk_buff *skb;
			dma_addr_t mapping;
			skb = dev_alloc_skb(priv->common.rx_mtu + 32);
			if (!skb)
				break;

			mapping = pci_map_single(priv->pdev,
						 skb_tail_pointer(skb),
						 priv->common.rx_mtu + 32,
						 PCI_DMA_FROMDEVICE);
			desc->host_addr = cpu_to_le32(mapping);
			desc->device_addr = 0;	// FIXME: necessary?
			desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
			desc->flags = 0;
			rx_buf[i] = skb;
		}

		i++;
		idx++;
		i %= ring_limit;
	}

	wmb();
	ring_control->host_idx[ring_index] = cpu_to_le32(idx);
}

static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	struct sk_buff **rx_buf)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	u32 idx, i;

	i = (*index) % ring_limit;
	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
	idx %= ring_limit;
	while (i != idx) {
		u16 len;
		struct sk_buff *skb;
		desc = &ring[i];
		len = le16_to_cpu(desc->len);
		skb = rx_buf[i];

		if (!skb) {
			i++;
			i %= ring_limit;
			continue;
		}
		skb_put(skb, len);

		if (p54_rx(dev, skb)) {
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
			rx_buf[i] = NULL;
			desc->host_addr = 0;
		} else {
			skb_trim(skb, 0);
			desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
		}

		i++;
		i %= ring_limit;
	}

	p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
}

/* caller must hold priv->lock */
static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	void **tx_buf)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	struct p54p_desc *desc;
	u32 idx, i;

	i = (*index) % ring_limit;
	(*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
	idx %= ring_limit;

	while (i != idx) {
		desc = &ring[i];
		kfree(tx_buf[i]);
		tx_buf[i] = NULL;

		pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
				 le16_to_cpu(desc->len), PCI_DMA_TODEVICE);

		desc->host_addr = 0;
		desc->device_addr = 0;
		desc->len = 0;
		desc->flags = 0;

		i++;
		i %= ring_limit;
	}
}

static void p54p_rx_tasklet(unsigned long dev_id)
{
	struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;

	p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
		ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);

	p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
		ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);

	wmb();
	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
}

static irqreturn_t p54p_interrupt(int irq, void *dev_id)
{
	struct ieee80211_hw *dev = dev_id;
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	__le32 reg;

	spin_lock(&priv->lock);
	reg = P54P_READ(int_ident);
	if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
		spin_unlock(&priv->lock);
		return IRQ_HANDLED;
	}

	P54P_WRITE(int_ack, reg);

	reg &= P54P_READ(int_enable);

	if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
		p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
				   3, ring_control->tx_mgmt,
				   ARRAY_SIZE(ring_control->tx_mgmt),
				   priv->tx_buf_mgmt);

		p54p_check_tx_ring(dev, &priv->tx_idx_data,
				   1, ring_control->tx_data,
				   ARRAY_SIZE(ring_control->tx_data),
				   priv->tx_buf_data);

		tasklet_schedule(&priv->rx_tasklet);

	} else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
		complete(&priv->boot_comp);

	spin_unlock(&priv->lock);

	return reg ? IRQ_HANDLED : IRQ_NONE;
}

static void p54p_tx(struct ieee80211_hw *dev, struct p54_control_hdr *data,
		    size_t len, int free_on_tx)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	unsigned long flags;
	struct p54p_desc *desc;
	dma_addr_t mapping;
	u32 device_idx, idx, i;

	spin_lock_irqsave(&priv->lock, flags);

	device_idx = le32_to_cpu(ring_control->device_idx[1]);
	idx = le32_to_cpu(ring_control->host_idx[1]);
	i = idx % ARRAY_SIZE(ring_control->tx_data);

	mapping = pci_map_single(priv->pdev, data, len, PCI_DMA_TODEVICE);
	desc = &ring_control->tx_data[i];
	desc->host_addr = cpu_to_le32(mapping);
	desc->device_addr = data->req_id;
	desc->len = cpu_to_le16(len);
	desc->flags = 0;

	wmb();
	ring_control->host_idx[1] = cpu_to_le32(idx + 1);

	if (free_on_tx)
		priv->tx_buf_data[i] = data;

	spin_unlock_irqrestore(&priv->lock, flags);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	P54P_READ(dev_int);

	/* FIXME: unlikely to happen because the device usually runs out of
	   memory before we fill the ring up, but we can make it impossible */
	if (idx - device_idx > ARRAY_SIZE(ring_control->tx_data) - 2)
		printk(KERN_INFO "%s: tx overflow.\n", wiphy_name(dev->wiphy));
}

static void p54p_stop(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	struct p54p_ring_control *ring_control = priv->ring_control;
	unsigned int i;
	struct p54p_desc *desc;

	tasklet_kill(&priv->rx_tasklet);

	P54P_WRITE(int_enable, cpu_to_le32(0));
	P54P_READ(int_enable);
	udelay(10);

	free_irq(priv->pdev->irq, dev);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));

	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
		desc = &ring_control->rx_data[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
		kfree_skb(priv->rx_buf_data[i]);
		priv->rx_buf_data[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
		desc = &ring_control->rx_mgmt[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 priv->common.rx_mtu + 32,
					 PCI_DMA_FROMDEVICE);
		kfree_skb(priv->rx_buf_mgmt[i]);
		priv->rx_buf_mgmt[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
		desc = &ring_control->tx_data[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 le16_to_cpu(desc->len),
					 PCI_DMA_TODEVICE);

		kfree(priv->tx_buf_data[i]);
		priv->tx_buf_data[i] = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
		desc = &ring_control->tx_mgmt[i];
		if (desc->host_addr)
			pci_unmap_single(priv->pdev,
					 le32_to_cpu(desc->host_addr),
					 le16_to_cpu(desc->len),
					 PCI_DMA_TODEVICE);

		kfree(priv->tx_buf_mgmt[i]);
		priv->tx_buf_mgmt[i] = NULL;
	}

	memset(ring_control, 0, sizeof(*ring_control));
}

static int p54p_open(struct ieee80211_hw *dev)
{
	struct p54p_priv *priv = dev->priv;
	int err;

	init_completion(&priv->boot_comp);
	err = request_irq(priv->pdev->irq, &p54p_interrupt,
			  IRQF_SHARED, "p54pci", dev);
	if (err) {
		printk(KERN_ERR "%s: failed to register IRQ handler\n",
		       wiphy_name(dev->wiphy));
		return err;
	}

	memset(priv->ring_control, 0, sizeof(*priv->ring_control));
	err = p54p_upload_firmware(dev);
	if (err) {
		free_irq(priv->pdev->irq, dev);
		return err;
	}
	priv->rx_idx_data = priv->tx_idx_data = 0;
	priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;

	p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
		ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);

	p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
		ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);

	P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
	P54P_READ(ring_control_base);
	wmb();
	udelay(10);

	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
	P54P_READ(int_enable);
	wmb();
	udelay(10);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
	P54P_READ(dev_int);

	if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
		printk(KERN_ERR "%s: Cannot boot firmware!\n",
		       wiphy_name(dev->wiphy));
		p54p_stop(dev);
		return -ETIMEDOUT;
	}

	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
	P54P_READ(int_enable);
	wmb();
	udelay(10);

	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	P54P_READ(dev_int);
	wmb();
	udelay(10);

	return 0;
}

static int __devinit p54p_probe(struct pci_dev *pdev,
				const struct pci_device_id *id)
{
	struct p54p_priv *priv;
	struct ieee80211_hw *dev;
	unsigned long mem_addr, mem_len;
	int err;
	DECLARE_MAC_BUF(mac);

	err = pci_enable_device(pdev);
	if (err) {
		printk(KERN_ERR "%s (p54pci): Cannot enable new PCI device\n",
		       pci_name(pdev));
		return err;
	}

	mem_addr = pci_resource_start(pdev, 0);
	mem_len = pci_resource_len(pdev, 0);
	if (mem_len < sizeof(struct p54p_csr)) {
		printk(KERN_ERR "%s (p54pci): Too short PCI resources\n",
		       pci_name(pdev));
		pci_disable_device(pdev);
		return err;
	}

	err = pci_request_regions(pdev, "p54pci");
	if (err) {
		printk(KERN_ERR "%s (p54pci): Cannot obtain PCI resources\n",
		       pci_name(pdev));
		return err;
	}

	if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
	    pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
		printk(KERN_ERR "%s (p54pci): No suitable DMA available\n",
		       pci_name(pdev));
		goto err_free_reg;
	}

	pci_set_master(pdev);
	pci_try_set_mwi(pdev);

	pci_write_config_byte(pdev, 0x40, 0);
	pci_write_config_byte(pdev, 0x41, 0);

	dev = p54_init_common(sizeof(*priv));
	if (!dev) {
		printk(KERN_ERR "%s (p54pci): ieee80211 alloc failed\n",
		       pci_name(pdev));
		err = -ENOMEM;
		goto err_free_reg;
	}

	priv = dev->priv;
	priv->pdev = pdev;

	SET_IEEE80211_DEV(dev, &pdev->dev);
	pci_set_drvdata(pdev, dev);

	priv->map = ioremap(mem_addr, mem_len);
	if (!priv->map) {
		printk(KERN_ERR "%s (p54pci): Cannot map device memory\n",
		       pci_name(pdev));
		err = -EINVAL;	// TODO: use a better error code?
		goto err_free_dev;
	}

	priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
						  &priv->ring_control_dma);
	if (!priv->ring_control) {
		printk(KERN_ERR "%s (p54pci): Cannot allocate rings\n",
		       pci_name(pdev));
		err = -ENOMEM;
		goto err_iounmap;
	}
	priv->common.open = p54p_open;
	priv->common.stop = p54p_stop;
	priv->common.tx = p54p_tx;

	spin_lock_init(&priv->lock);
	tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);

	err = p54p_open(dev);
	if (err)
		goto err_free_common;
	err = p54_read_eeprom(dev);
	p54p_stop(dev);
	if (err)
		goto err_free_common;

	err = ieee80211_register_hw(dev);
	if (err) {
		printk(KERN_ERR "%s (p54pci): Cannot register netdevice\n",
		       pci_name(pdev));
		goto err_free_common;
	}

	return 0;

 err_free_common:
	p54_free_common(dev);
	pci_free_consistent(pdev, sizeof(*priv->ring_control),
			    priv->ring_control, priv->ring_control_dma);

 err_iounmap:
	iounmap(priv->map);

 err_free_dev:
	pci_set_drvdata(pdev, NULL);
	ieee80211_free_hw(dev);

 err_free_reg:
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	return err;
}

static void __devexit p54p_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv;

	if (!dev)
		return;

	ieee80211_unregister_hw(dev);
	priv = dev->priv;
	pci_free_consistent(pdev, sizeof(*priv->ring_control),
			    priv->ring_control, priv->ring_control_dma);
	p54_free_common(dev);
	iounmap(priv->map);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	ieee80211_free_hw(dev);
}

#ifdef CONFIG_PM
static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv = dev->priv;

	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
		ieee80211_stop_queues(dev);
		p54p_stop(dev);
	}

	pci_save_state(pdev);
	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	return 0;
}

static int p54p_resume(struct pci_dev *pdev)
{
	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	struct p54p_priv *priv = dev->priv;

	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);

	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
		p54p_open(dev);
		ieee80211_wake_queues(dev);
	}

	return 0;
}
#endif /* CONFIG_PM */

static struct pci_driver p54p_driver = {
	.name		= "p54pci",
	.id_table	= p54p_table,
	.probe		= p54p_probe,
	.remove		= __devexit_p(p54p_remove),
#ifdef CONFIG_PM
	.suspend	= p54p_suspend,
	.resume		= p54p_resume,
#endif /* CONFIG_PM */
};

static int __init p54p_init(void)
{
	return pci_register_driver(&p54p_driver);
}

static void __exit p54p_exit(void)
{
	pci_unregister_driver(&p54p_driver);
}

module_init(p54p_init);
module_exit(p54p_exit);
Commit	Line	Data
eff1a59c MW	1
	2	/*
	3	* Linux device driver for PCI based Prism54
	4	*
	5	* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
7262d593	6	* Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
eff1a59c MW	7	*
	8	* Based on the islsm (softmac prism54) driver, which is:
	9	* Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/pci.h>
	18	#include <linux/firmware.h>
	19	#include <linux/etherdevice.h>
	20	#include <linux/delay.h>
	21	#include <linux/completion.h>
	22	#include <net/mac80211.h>
	23
	24	#include "p54.h"
	25	#include "p54pci.h"
	26
	27	MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
	28	MODULE_DESCRIPTION("Prism54 PCI wireless driver");
	29	MODULE_LICENSE("GPL");
	30	MODULE_ALIAS("prism54pci");
	31
	32	static struct pci_device_id p54p_table[] __devinitdata = {
	33	/* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
	34	{ PCI_DEVICE(0x1260, 0x3890) },
	35	/* 3COM 3CRWE154G72 Wireless LAN adapter */
	36	{ PCI_DEVICE(0x10b7, 0x6001) },
	37	/* Intersil PRISM Indigo Wireless LAN adapter */
	38	{ PCI_DEVICE(0x1260, 0x3877) },
	39	/* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
	40	{ PCI_DEVICE(0x1260, 0x3886) },
90f4dd0f	41	{ },
eff1a59c MW	42	};
	43
	44	MODULE_DEVICE_TABLE(pci, p54p_table);
	45
	46	static int p54p_upload_firmware(struct ieee80211_hw *dev)
	47	{
	48	struct p54p_priv *priv = dev->priv;
	49	const struct firmware *fw_entry = NULL;
	50	__le32 reg;
	51	int err;
8160c031	52	__le32 *data;
eff1a59c MW	53	u32 remains, left, device_addr;
eff1a59c MW	54
8160c031	55	P54P_WRITE(int_enable, cpu_to_le32(0));
eff1a59c MW	56	P54P_READ(int_enable);
	57	udelay(10);
	58
	59	reg = P54P_READ(ctrl_stat);
	60	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	61	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
	62	P54P_WRITE(ctrl_stat, reg);
	63	P54P_READ(ctrl_stat);
	64	udelay(10);
	65
	66	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	67	P54P_WRITE(ctrl_stat, reg);
	68	wmb();
	69	udelay(10);
	70
	71	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	72	P54P_WRITE(ctrl_stat, reg);
	73	wmb();
	74
eff1a59c MW	75	err = request_firmware(&fw_entry, "isl3886", &priv->pdev->dev);
eff1a59c MW	76	if (err) {
32ddf071	77	printk(KERN_ERR "%s (p54pci): cannot find firmware "
eff1a59c MW	78	"(isl3886)\n", pci_name(priv->pdev));
	79	return err;
	80	}
	81
4e416a6f CL	82	err = p54_parse_firmware(dev, fw_entry);
	83	if (err) {
	84	release_firmware(fw_entry);
	85	return err;
	86	}
eff1a59c	87
8160c031	88	data = (__le32 *) fw_entry->data;
eff1a59c MW	89	remains = fw_entry->size;
	90	device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
	91	while (remains) {
	92	u32 i = 0;
	93	left = min((u32)0x1000, remains);
	94	P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
	95	P54P_READ(int_enable);
	96
	97	device_addr += 0x1000;
	98	while (i < left) {
	99	P54P_WRITE(direct_mem_win[i], *data++);
	100	i += sizeof(u32);
	101	}
	102
	103	remains -= left;
	104	P54P_READ(int_enable);
	105	}
	106
	107	release_firmware(fw_entry);
	108
	109	reg = P54P_READ(ctrl_stat);
	110	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
	111	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	112	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
	113	P54P_WRITE(ctrl_stat, reg);
	114	P54P_READ(ctrl_stat);
	115	udelay(10);
	116
	117	reg \|= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
	118	P54P_WRITE(ctrl_stat, reg);
	119	wmb();
	120	udelay(10);
	121
	122	reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
	123	P54P_WRITE(ctrl_stat, reg);
	124	wmb();
	125	udelay(10);
	126
7cb77072	127	/* wait for the firmware to boot properly */
eff1a59c	128	mdelay(100);
eff1a59c	129
7cb77072	130	return 0;
eff1a59c MW	131	}
eff1a59c MW	132
7262d593 CL	133	static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
	134	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	135	struct sk_buff **rx_buf)
eff1a59c MW	136	{
eff1a59c MW	137	struct p54p_priv *priv = dev->priv;
eb76bf29	138	struct p54p_ring_control *ring_control = priv->ring_control;
7262d593	139	u32 limit, idx, i;
eff1a59c	140
7262d593 CL	141	idx = le32_to_cpu(ring_control->host_idx[ring_index]);
	142	limit = idx;
	143	limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
	144	limit = ring_limit - limit;
eff1a59c	145
7262d593	146	i = idx % ring_limit;
eff1a59c	147	while (limit-- > 1) {
7262d593	148	struct p54p_desc *desc = &ring[i];
eff1a59c MW	149
	150	if (!desc->host_addr) {
	151	struct sk_buff *skb;
	152	dma_addr_t mapping;
4e416a6f	153	skb = dev_alloc_skb(priv->common.rx_mtu + 32);
eff1a59c MW	154	if (!skb)
	155	break;
	156
	157	mapping = pci_map_single(priv->pdev,
	158	skb_tail_pointer(skb),
4e416a6f	159	priv->common.rx_mtu + 32,
eff1a59c MW	160	PCI_DMA_FROMDEVICE);
	161	desc->host_addr = cpu_to_le32(mapping);
	162	desc->device_addr = 0; // FIXME: necessary?
4e416a6f	163	desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
eff1a59c	164	desc->flags = 0;
7262d593	165	rx_buf[i] = skb;
eff1a59c MW	166	}
eff1a59c MW	167
7262d593	168	i++;
eff1a59c	169	idx++;
7262d593	170	i %= ring_limit;
eff1a59c MW	171	}
	172
	173	wmb();
7262d593 CL	174	ring_control->host_idx[ring_index] = cpu_to_le32(idx);
	175	}
	176
	177	static void p54p_check_rx_ring(struct ieee80211_hw dev, u32 index,
	178	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	179	struct sk_buff **rx_buf)
	180	{
	181	struct p54p_priv *priv = dev->priv;
	182	struct p54p_ring_control *ring_control = priv->ring_control;
	183	struct p54p_desc *desc;
	184	u32 idx, i;
	185
	186	i = (*index) % ring_limit;
	187	(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
	188	idx %= ring_limit;
	189	while (i != idx) {
	190	u16 len;
	191	struct sk_buff *skb;
	192	desc = &ring[i];
	193	len = le16_to_cpu(desc->len);
	194	skb = rx_buf[i];
	195
0c25970d CL	196	if (!skb) {
	197	i++;
	198	i %= ring_limit;
7262d593	199	continue;
0c25970d	200	}
7262d593 CL	201	skb_put(skb, len);
	202
	203	if (p54_rx(dev, skb)) {
	204	pci_unmap_single(priv->pdev,
	205	le32_to_cpu(desc->host_addr),
4e416a6f CL	206	priv->common.rx_mtu + 32,
4e416a6f CL	207	PCI_DMA_FROMDEVICE);
7262d593 CL	208	rx_buf[i] = NULL;
	209	desc->host_addr = 0;
	210	} else {
	211	skb_trim(skb, 0);
4e416a6f	212	desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
7262d593 CL	213	}
	214
	215	i++;
	216	i %= ring_limit;
	217	}
	218
	219	p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
	220	}
	221
	222	/* caller must hold priv->lock */
	223	static void p54p_check_tx_ring(struct ieee80211_hw dev, u32 index,
	224	int ring_index, struct p54p_desc *ring, u32 ring_limit,
	225	void **tx_buf)
	226	{
	227	struct p54p_priv *priv = dev->priv;
	228	struct p54p_ring_control *ring_control = priv->ring_control;
	229	struct p54p_desc *desc;
	230	u32 idx, i;
	231
	232	i = (*index) % ring_limit;
	233	(*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
	234	idx %= ring_limit;
	235
	236	while (i != idx) {
	237	desc = &ring[i];
	238	kfree(tx_buf[i]);
	239	tx_buf[i] = NULL;
	240
	241	pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
	242	le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
	243
	244	desc->host_addr = 0;
	245	desc->device_addr = 0;
	246	desc->len = 0;
	247	desc->flags = 0;
	248
	249	i++;
	250	i %= ring_limit;
	251	}
	252	}
	253
	254	static void p54p_rx_tasklet(unsigned long dev_id)
	255	{
	256	struct ieee80211_hw dev = (struct ieee80211_hw )dev_id;
	257	struct p54p_priv *priv = dev->priv;
	258	struct p54p_ring_control *ring_control = priv->ring_control;
	259
	260	p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
	261	ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
	262
	263	p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
	264	ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
	265
	266	wmb();
	267	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
eff1a59c MW	268	}
	269
	270	static irqreturn_t p54p_interrupt(int irq, void *dev_id)
	271	{
	272	struct ieee80211_hw *dev = dev_id;
	273	struct p54p_priv *priv = dev->priv;
eb76bf29	274	struct p54p_ring_control *ring_control = priv->ring_control;
eff1a59c MW	275	__le32 reg;
	276
	277	spin_lock(&priv->lock);
	278	reg = P54P_READ(int_ident);
8160c031	279	if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
eff1a59c MW	280	spin_unlock(&priv->lock);
	281	return IRQ_HANDLED;
	282	}
	283
	284	P54P_WRITE(int_ack, reg);
	285
	286	reg &= P54P_READ(int_enable);
	287
	288	if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
7262d593 CL	289	p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
	290	3, ring_control->tx_mgmt,
	291	ARRAY_SIZE(ring_control->tx_mgmt),
	292	priv->tx_buf_mgmt);
eff1a59c	293
7262d593 CL	294	p54p_check_tx_ring(dev, &priv->tx_idx_data,
	295	1, ring_control->tx_data,
	296	ARRAY_SIZE(ring_control->tx_data),
	297	priv->tx_buf_data);
eff1a59c	298
7262d593	299	tasklet_schedule(&priv->rx_tasklet);
eff1a59c	300
eff1a59c MW	301	} else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
	302	complete(&priv->boot_comp);
	303
	304	spin_unlock(&priv->lock);
	305
	306	return reg ? IRQ_HANDLED : IRQ_NONE;
	307	}
	308
	309	static void p54p_tx(struct ieee80211_hw dev, struct p54_control_hdr data,
	310	size_t len, int free_on_tx)
	311	{
	312	struct p54p_priv *priv = dev->priv;
eb76bf29	313	struct p54p_ring_control *ring_control = priv->ring_control;
eff1a59c MW	314	unsigned long flags;
	315	struct p54p_desc *desc;
	316	dma_addr_t mapping;
	317	u32 device_idx, idx, i;
	318
	319	spin_lock_irqsave(&priv->lock, flags);
	320
eb76bf29 DT	321	device_idx = le32_to_cpu(ring_control->device_idx[1]);
	322	idx = le32_to_cpu(ring_control->host_idx[1]);
	323	i = idx % ARRAY_SIZE(ring_control->tx_data);
eff1a59c MW	324
eff1a59c MW	325	mapping = pci_map_single(priv->pdev, data, len, PCI_DMA_TODEVICE);
eb76bf29	326	desc = &ring_control->tx_data[i];
eff1a59c MW	327	desc->host_addr = cpu_to_le32(mapping);
	328	desc->device_addr = data->req_id;
	329	desc->len = cpu_to_le16(len);
	330	desc->flags = 0;
	331
	332	wmb();
eb76bf29	333	ring_control->host_idx[1] = cpu_to_le32(idx + 1);
eff1a59c MW	334
eff1a59c MW	335	if (free_on_tx)
7262d593	336	priv->tx_buf_data[i] = data;
eff1a59c MW	337
	338	spin_unlock_irqrestore(&priv->lock, flags);
	339
	340	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	341	P54P_READ(dev_int);
	342
	343	/* FIXME: unlikely to happen because the device usually runs out of
	344	memory before we fill the ring up, but we can make it impossible */
eb76bf29	345	if (idx - device_idx > ARRAY_SIZE(ring_control->tx_data) - 2)
eff1a59c MW	346	printk(KERN_INFO "%s: tx overflow.\n", wiphy_name(dev->wiphy));
	347	}
	348
eff1a59c MW	349	static void p54p_stop(struct ieee80211_hw *dev)
	350	{
	351	struct p54p_priv *priv = dev->priv;
eb76bf29	352	struct p54p_ring_control *ring_control = priv->ring_control;
eff1a59c MW	353	unsigned int i;
	354	struct p54p_desc *desc;
	355
7262d593 CL	356	tasklet_kill(&priv->rx_tasklet);
7262d593 CL	357
8160c031	358	P54P_WRITE(int_enable, cpu_to_le32(0));
eff1a59c MW	359	P54P_READ(int_enable);
	360	udelay(10);
	361
	362	free_irq(priv->pdev->irq, dev);
	363
	364	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
	365
7262d593	366	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
eb76bf29	367	desc = &ring_control->rx_data[i];
eff1a59c	368	if (desc->host_addr)
7262d593 CL	369	pci_unmap_single(priv->pdev,
7262d593 CL	370	le32_to_cpu(desc->host_addr),
4e416a6f CL	371	priv->common.rx_mtu + 32,
4e416a6f CL	372	PCI_DMA_FROMDEVICE);
7262d593 CL	373	kfree_skb(priv->rx_buf_data[i]);
7262d593 CL	374	priv->rx_buf_data[i] = NULL;
eff1a59c MW	375	}
eff1a59c MW	376
7262d593 CL	377	for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
	378	desc = &ring_control->rx_mgmt[i];
	379	if (desc->host_addr)
	380	pci_unmap_single(priv->pdev,
	381	le32_to_cpu(desc->host_addr),
4e416a6f CL	382	priv->common.rx_mtu + 32,
4e416a6f CL	383	PCI_DMA_FROMDEVICE);
7262d593 CL	384	kfree_skb(priv->rx_buf_mgmt[i]);
	385	priv->rx_buf_mgmt[i] = NULL;
	386	}
	387
	388	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
eb76bf29	389	desc = &ring_control->tx_data[i];
eff1a59c	390	if (desc->host_addr)
7262d593 CL	391	pci_unmap_single(priv->pdev,
	392	le32_to_cpu(desc->host_addr),
	393	le16_to_cpu(desc->len),
	394	PCI_DMA_TODEVICE);
	395
	396	kfree(priv->tx_buf_data[i]);
	397	priv->tx_buf_data[i] = NULL;
	398	}
	399
	400	for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
	401	desc = &ring_control->tx_mgmt[i];
	402	if (desc->host_addr)
	403	pci_unmap_single(priv->pdev,
	404	le32_to_cpu(desc->host_addr),
	405	le16_to_cpu(desc->len),
	406	PCI_DMA_TODEVICE);
eff1a59c	407
7262d593 CL	408	kfree(priv->tx_buf_mgmt[i]);
7262d593 CL	409	priv->tx_buf_mgmt[i] = NULL;
eff1a59c MW	410	}
eff1a59c MW	411
7262d593	412	memset(ring_control, 0, sizeof(*ring_control));
eff1a59c MW	413	}
eff1a59c MW	414
35961627 CL	415	static int p54p_open(struct ieee80211_hw *dev)
	416	{
	417	struct p54p_priv *priv = dev->priv;
	418	int err;
	419
	420	init_completion(&priv->boot_comp);
	421	err = request_irq(priv->pdev->irq, &p54p_interrupt,
	422	IRQF_SHARED, "p54pci", dev);
	423	if (err) {
	424	printk(KERN_ERR "%s: failed to register IRQ handler\n",
	425	wiphy_name(dev->wiphy));
	426	return err;
	427	}
	428
	429	memset(priv->ring_control, 0, sizeof(*priv->ring_control));
	430	err = p54p_upload_firmware(dev);
	431	if (err) {
	432	free_irq(priv->pdev->irq, dev);
	433	return err;
	434	}
	435	priv->rx_idx_data = priv->tx_idx_data = 0;
	436	priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
	437
	438	p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
	439	ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
	440
	441	p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
	442	ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
	443
	444	P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
	445	P54P_READ(ring_control_base);
	446	wmb();
	447	udelay(10);
	448
	449	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
	450	P54P_READ(int_enable);
	451	wmb();
	452	udelay(10);
	453
	454	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
	455	P54P_READ(dev_int);
	456
	457	if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
	458	printk(KERN_ERR "%s: Cannot boot firmware!\n",
	459	wiphy_name(dev->wiphy));
	460	p54p_stop(dev);
	461	return -ETIMEDOUT;
	462	}
	463
	464	P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
	465	P54P_READ(int_enable);
	466	wmb();
	467	udelay(10);
	468
	469	P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
	470	P54P_READ(dev_int);
	471	wmb();
	472	udelay(10);
	473
	474	return 0;
	475	}
	476
eff1a59c MW	477	static int __devinit p54p_probe(struct pci_dev *pdev,
	478	const struct pci_device_id *id)
	479	{
	480	struct p54p_priv *priv;
	481	struct ieee80211_hw *dev;
	482	unsigned long mem_addr, mem_len;
	483	int err;
	484	DECLARE_MAC_BUF(mac);
	485
	486	err = pci_enable_device(pdev);
	487	if (err) {
32ddf071	488	printk(KERN_ERR "%s (p54pci): Cannot enable new PCI device\n",
eff1a59c MW	489	pci_name(pdev));
	490	return err;
	491	}
	492
	493	mem_addr = pci_resource_start(pdev, 0);
	494	mem_len = pci_resource_len(pdev, 0);
	495	if (mem_len < sizeof(struct p54p_csr)) {
32ddf071	496	printk(KERN_ERR "%s (p54pci): Too short PCI resources\n",
eff1a59c MW	497	pci_name(pdev));
	498	pci_disable_device(pdev);
	499	return err;
	500	}
	501
32ddf071	502	err = pci_request_regions(pdev, "p54pci");
eff1a59c	503	if (err) {
32ddf071	504	printk(KERN_ERR "%s (p54pci): Cannot obtain PCI resources\n",
eff1a59c MW	505	pci_name(pdev));
	506	return err;
	507	}
	508
	509	if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) \|\|
	510	pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
32ddf071	511	printk(KERN_ERR "%s (p54pci): No suitable DMA available\n",
eff1a59c MW	512	pci_name(pdev));
	513	goto err_free_reg;
	514	}
	515
	516	pci_set_master(pdev);
	517	pci_try_set_mwi(pdev);
	518
	519	pci_write_config_byte(pdev, 0x40, 0);
	520	pci_write_config_byte(pdev, 0x41, 0);
	521
	522	dev = p54_init_common(sizeof(*priv));
	523	if (!dev) {
32ddf071	524	printk(KERN_ERR "%s (p54pci): ieee80211 alloc failed\n",
eff1a59c MW	525	pci_name(pdev));
	526	err = -ENOMEM;
	527	goto err_free_reg;
	528	}
	529
	530	priv = dev->priv;
	531	priv->pdev = pdev;
	532
	533	SET_IEEE80211_DEV(dev, &pdev->dev);
	534	pci_set_drvdata(pdev, dev);
	535
	536	priv->map = ioremap(mem_addr, mem_len);
	537	if (!priv->map) {
32ddf071	538	printk(KERN_ERR "%s (p54pci): Cannot map device memory\n",
eff1a59c MW	539	pci_name(pdev));
	540	err = -EINVAL; // TODO: use a better error code?
	541	goto err_free_dev;
	542	}
	543
	544	priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
	545	&priv->ring_control_dma);
	546	if (!priv->ring_control) {
32ddf071	547	printk(KERN_ERR "%s (p54pci): Cannot allocate rings\n",
eff1a59c MW	548	pci_name(pdev));
	549	err = -ENOMEM;
	550	goto err_iounmap;
	551	}
eff1a59c MW	552	priv->common.open = p54p_open;
	553	priv->common.stop = p54p_stop;
	554	priv->common.tx = p54p_tx;
	555
	556	spin_lock_init(&priv->lock);
7262d593	557	tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
eff1a59c	558
35961627 CL	559	err = p54p_open(dev);
	560	if (err)
	561	goto err_free_common;
7cb77072 CL	562	err = p54_read_eeprom(dev);
	563	p54p_stop(dev);
	564	if (err)
35961627	565	goto err_free_common;
7cb77072	566
eff1a59c MW	567	err = ieee80211_register_hw(dev);
eff1a59c MW	568	if (err) {
32ddf071	569	printk(KERN_ERR "%s (p54pci): Cannot register netdevice\n",
eff1a59c MW	570	pci_name(pdev));
	571	goto err_free_common;
	572	}
	573
eff1a59c MW	574	return 0;
	575
	576	err_free_common:
	577	p54_free_common(dev);
eff1a59c MW	578	pci_free_consistent(pdev, sizeof(*priv->ring_control),
	579	priv->ring_control, priv->ring_control_dma);
	580
	581	err_iounmap:
	582	iounmap(priv->map);
	583
	584	err_free_dev:
	585	pci_set_drvdata(pdev, NULL);
	586	ieee80211_free_hw(dev);
	587
	588	err_free_reg:
	589	pci_release_regions(pdev);
	590	pci_disable_device(pdev);
	591	return err;
	592	}
	593
	594	static void __devexit p54p_remove(struct pci_dev *pdev)
	595	{
	596	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	597	struct p54p_priv *priv;
	598
	599	if (!dev)
	600	return;
	601
	602	ieee80211_unregister_hw(dev);
	603	priv = dev->priv;
	604	pci_free_consistent(pdev, sizeof(*priv->ring_control),
	605	priv->ring_control, priv->ring_control_dma);
	606	p54_free_common(dev);
	607	iounmap(priv->map);
	608	pci_release_regions(pdev);
	609	pci_disable_device(pdev);
	610	ieee80211_free_hw(dev);
	611	}
	612
	613	#ifdef CONFIG_PM
	614	static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
	615	{
	616	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	617	struct p54p_priv *priv = dev->priv;
	618
05c914fe	619	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
eff1a59c MW	620	ieee80211_stop_queues(dev);
	621	p54p_stop(dev);
	622	}
	623
	624	pci_save_state(pdev);
	625	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	626	return 0;
	627	}
	628
	629	static int p54p_resume(struct pci_dev *pdev)
	630	{
	631	struct ieee80211_hw *dev = pci_get_drvdata(pdev);
	632	struct p54p_priv *priv = dev->priv;
	633
	634	pci_set_power_state(pdev, PCI_D0);
	635	pci_restore_state(pdev);
	636
05c914fe	637	if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
eff1a59c	638	p54p_open(dev);
36d6825b	639	ieee80211_wake_queues(dev);
eff1a59c MW	640	}
	641
	642	return 0;
	643	}
	644	#endif /* CONFIG_PM */
	645
	646	static struct pci_driver p54p_driver = {
32ddf071	647	.name = "p54pci",
eff1a59c MW	648	.id_table = p54p_table,
	649	.probe = p54p_probe,
	650	.remove = __devexit_p(p54p_remove),
	651	#ifdef CONFIG_PM
	652	.suspend = p54p_suspend,
	653	.resume = p54p_resume,
	654	#endif /* CONFIG_PM */
	655	};
	656
	657	static int __init p54p_init(void)
	658	{
	659	return pci_register_driver(&p54p_driver);
	660	}
	661
	662	static void __exit p54p_exit(void)
	663	{
	664	pci_unregister_driver(&p54p_driver);
	665	}
	666
	667	module_init(p54p_init);
	668	module_exit(p54p_exit);