[linux-2.6-block.git] / drivers / net / wireless / mediatek / mt76 / mt7615 / dma.c

// SPDX-License-Identifier: ISC
/* Copyright (C) 2019 MediaTek Inc.
 *
 * Author: Ryder Lee <ryder.lee@mediatek.com>
 *         Roy Luo <royluo@google.com>
 *         Lorenzo Bianconi <lorenzo@kernel.org>
 *         Felix Fietkau <nbd@nbd.name>
 */

#include "mt7615.h"
#include "../dma.h"
#include "mac.h"

static int
mt7615_init_tx_queues(struct mt7615_dev *dev, int n_desc)
{
	struct mt76_sw_queue *q;
	struct mt76_queue *hwq;
	int err, i;

	hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
	if (!hwq)
		return -ENOMEM;

	err = mt76_queue_alloc(dev, hwq, 0, n_desc, 0, MT_TX_RING_BASE);
	if (err < 0)
		return err;

	for (i = 0; i < MT_TXQ_MCU; i++) {
		q = &dev->mt76.q_tx[i];
		INIT_LIST_HEAD(&q->swq);
		q->q = hwq;
	}

	return 0;
}

static int
mt7615_init_mcu_queue(struct mt7615_dev *dev, struct mt76_sw_queue *q,
		      int idx, int n_desc)
{
	struct mt76_queue *hwq;
	int err;

	hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
	if (!hwq)
		return -ENOMEM;

	err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE);
	if (err < 0)
		return err;

	INIT_LIST_HEAD(&q->swq);
	q->q = hwq;

	return 0;
}

void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
			 struct sk_buff *skb)
{
	struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
	__le32 *rxd = (__le32 *)skb->data;
	__le32 *end = (__le32 *)&skb->data[skb->len];
	enum rx_pkt_type type;

	type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));

	switch (type) {
	case PKT_TYPE_TXS:
		for (rxd++; rxd + 7 <= end; rxd += 7)
			mt7615_mac_add_txs(dev, rxd);
		dev_kfree_skb(skb);
		break;
	case PKT_TYPE_TXRX_NOTIFY:
		mt7615_mac_tx_free(dev, skb);
		break;
	case PKT_TYPE_RX_EVENT:
		mt7615_mcu_rx_event(dev, skb);
		break;
	case PKT_TYPE_NORMAL:
		if (!mt7615_mac_fill_rx(dev, skb)) {
			mt76_rx(&dev->mt76, q, skb);
			return;
		}
		/* fall through */
	default:
		dev_kfree_skb(skb);
		break;
	}
}

static int mt7615_poll_tx(struct napi_struct *napi, int budget)
{
	static const u8 queue_map[] = {
		MT_TXQ_MCU,
		MT_TXQ_BE
	};
	struct mt7615_dev *dev;
	int i;

	dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);

	for (i = 0; i < ARRAY_SIZE(queue_map); i++)
		mt76_queue_tx_cleanup(dev, queue_map[i], false);

	if (napi_complete_done(napi, 0))
		mt7615_irq_enable(dev, MT_INT_TX_DONE_ALL);

	for (i = 0; i < ARRAY_SIZE(queue_map); i++)
		mt76_queue_tx_cleanup(dev, queue_map[i], false);

	mt7615_mac_sta_poll(dev);

	tasklet_schedule(&dev->mt76.tx_tasklet);

	return 0;
}

int mt7615_dma_init(struct mt7615_dev *dev)
{
	int ret;

	mt76_dma_attach(&dev->mt76);

	mt76_wr(dev, MT_WPDMA_GLO_CFG,
		MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE |
		MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN |
		MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY |
		MT_WPDMA_GLO_CFG_OMIT_TX_INFO);

	mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
		       MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);

	mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
		       MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1);

	mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
		       MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3);

	mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
		       MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);

	mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);
	mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);
	mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
	mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);
	mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);
	mt76_set(dev, 0x7158, BIT(16));
	mt76_clear(dev, 0x7000, BIT(23));
	mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);

	ret = mt7615_init_tx_queues(dev, MT7615_TX_RING_SIZE);
	if (ret)
		return ret;

	ret = mt7615_init_mcu_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
				    MT7615_TXQ_MCU,
				    MT7615_TX_MCU_RING_SIZE);
	if (ret)
		return ret;

	ret = mt7615_init_mcu_queue(dev, &dev->mt76.q_tx[MT_TXQ_FWDL],
				    MT7615_TXQ_FWDL,
				    MT7615_TX_FWDL_RING_SIZE);
	if (ret)
		return ret;

	/* init rx queues */
	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
			       MT7615_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE,
			       MT_RX_RING_BASE);
	if (ret)
		return ret;

	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
			       MT7615_RX_RING_SIZE, MT_RX_BUF_SIZE,
			       MT_RX_RING_BASE);
	if (ret)
		return ret;

	mt76_wr(dev, MT_DELAY_INT_CFG, 0);

	ret = mt76_init_queues(dev);
	if (ret < 0)
		return ret;

	netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi,
			  mt7615_poll_tx, NAPI_POLL_WEIGHT);
	napi_enable(&dev->mt76.tx_napi);

	mt76_poll(dev, MT_WPDMA_GLO_CFG,
		  MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
		  MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000);

	/* start dma engine */
	mt76_set(dev, MT_WPDMA_GLO_CFG,
		 MT_WPDMA_GLO_CFG_TX_DMA_EN |
		 MT_WPDMA_GLO_CFG_RX_DMA_EN);

	/* enable interrupts for TX/RX rings */
	mt7615_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL);

	return 0;
}

void mt7615_dma_cleanup(struct mt7615_dev *dev)
{
	mt76_clear(dev, MT_WPDMA_GLO_CFG,
		   MT_WPDMA_GLO_CFG_TX_DMA_EN |
		   MT_WPDMA_GLO_CFG_RX_DMA_EN);
	mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);

	tasklet_kill(&dev->mt76.tx_tasklet);
	mt76_dma_cleanup(&dev->mt76);
}
Commit	Line	Data
04b8e659 RL	1	// SPDX-License-Identifier: ISC
	2	/* Copyright (C) 2019 MediaTek Inc.
	3	*
	4	* Author: Ryder Lee <ryder.lee@mediatek.com>
	5	* Roy Luo <royluo@google.com>
	6	* Lorenzo Bianconi <lorenzo@kernel.org>
	7	* Felix Fietkau <nbd@nbd.name>
	8	*/
	9
	10	#include "mt7615.h"
	11	#include "../dma.h"
	12	#include "mac.h"
	13
	14	static int
	15	mt7615_init_tx_queues(struct mt7615_dev *dev, int n_desc)
	16	{
	17	struct mt76_sw_queue *q;
	18	struct mt76_queue *hwq;
	19	int err, i;
	20
	21	hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
	22	if (!hwq)
	23	return -ENOMEM;
	24
	25	err = mt76_queue_alloc(dev, hwq, 0, n_desc, 0, MT_TX_RING_BASE);
	26	if (err < 0)
	27	return err;
	28
	29	for (i = 0; i < MT_TXQ_MCU; i++) {
	30	q = &dev->mt76.q_tx[i];
	31	INIT_LIST_HEAD(&q->swq);
	32	q->q = hwq;
	33	}
	34
	35	return 0;
	36	}
	37
	38	static int
	39	mt7615_init_mcu_queue(struct mt7615_dev dev, struct mt76_sw_queue q,
	40	int idx, int n_desc)
	41	{
	42	struct mt76_queue *hwq;
	43	int err;
	44
	45	hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
	46	if (!hwq)
	47	return -ENOMEM;
	48
	49	err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE);
	50	if (err < 0)
	51	return err;
	52
	53	INIT_LIST_HEAD(&q->swq);
	54	q->q = hwq;
	55
	56	return 0;
	57	}
	58
	59	void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
	60	struct sk_buff *skb)
	61	{
	62	struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
	63	__le32 rxd = (__le32 )skb->data;
	64	__le32 end = (__le32 )&skb->data[skb->len];
65	enum rx_pkt_type type;
66
67	type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
68
69	switch (type) {
70	case PKT_TYPE_TXS:
71	for (rxd++; rxd + 7 <= end; rxd += 7)
72	mt7615_mac_add_txs(dev, rxd);
73	dev_kfree_skb(skb);
74	break;
75	case PKT_TYPE_TXRX_NOTIFY:
76	mt7615_mac_tx_free(dev, skb);
77	break;
78	case PKT_TYPE_RX_EVENT:
d67a6646	79	mt7615_mcu_rx_event(dev, skb);
04b8e659 RL	80	break;
	81	case PKT_TYPE_NORMAL:
	82	if (!mt7615_mac_fill_rx(dev, skb)) {
	83	mt76_rx(&dev->mt76, q, skb);
	84	return;
	85	}
	86	/* fall through */
	87	default:
	88	dev_kfree_skb(skb);
	89	break;
	90	}
	91	}
	92
8357f0dc LB	93	static int mt7615_poll_tx(struct napi_struct *napi, int budget)
8357f0dc LB	94	{
04b8e659 RL	95	static const u8 queue_map[] = {
	96	MT_TXQ_MCU,
	97	MT_TXQ_BE
	98	};
8357f0dc	99	struct mt7615_dev *dev;
04b8e659 RL	100	int i;
04b8e659 RL	101
8357f0dc LB	102	dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
8357f0dc LB	103
04b8e659 RL	104	for (i = 0; i < ARRAY_SIZE(queue_map); i++)
	105	mt76_queue_tx_cleanup(dev, queue_map[i], false);
	106
8357f0dc LB	107	if (napi_complete_done(napi, 0))
8357f0dc LB	108	mt7615_irq_enable(dev, MT_INT_TX_DONE_ALL);
04b8e659	109
8357f0dc LB	110	for (i = 0; i < ARRAY_SIZE(queue_map); i++)
	111	mt76_queue_tx_cleanup(dev, queue_map[i], false);
	112
b2c2f029 LB	113	mt7615_mac_sta_poll(dev);
b2c2f029 LB	114
8357f0dc LB	115	tasklet_schedule(&dev->mt76.tx_tasklet);
	116
	117	return 0;
04b8e659 RL	118	}
	119
	120	int mt7615_dma_init(struct mt7615_dev *dev)
	121	{
	122	int ret;
	123
	124	mt76_dma_attach(&dev->mt76);
	125
04b8e659 RL	126	mt76_wr(dev, MT_WPDMA_GLO_CFG,
	127	MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE \|
	128	MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN \|
	129	MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY \|
	130	MT_WPDMA_GLO_CFG_OMIT_TX_INFO);
	131
	132	mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
	133	MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);
	134
	135	mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
	136	MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1);
	137
	138	mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
	139	MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3);
	140
	141	mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
	142	MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);
	143
	144	mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);
	145	mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);
	146	mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
	147	mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);
	148	mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);
	149	mt76_set(dev, 0x7158, BIT(16));
	150	mt76_clear(dev, 0x7000, BIT(23));
	151	mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
	152
	153	ret = mt7615_init_tx_queues(dev, MT7615_TX_RING_SIZE);
	154	if (ret)
	155	return ret;
	156
	157	ret = mt7615_init_mcu_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
	158	MT7615_TXQ_MCU,
	159	MT7615_TX_MCU_RING_SIZE);
	160	if (ret)
	161	return ret;
	162
	163	ret = mt7615_init_mcu_queue(dev, &dev->mt76.q_tx[MT_TXQ_FWDL],
	164	MT7615_TXQ_FWDL,
	165	MT7615_TX_FWDL_RING_SIZE);
	166	if (ret)
	167	return ret;
	168
	169	/* init rx queues */
	170	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
	171	MT7615_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE,
	172	MT_RX_RING_BASE);
	173	if (ret)
	174	return ret;
	175
	176	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
	177	MT7615_RX_RING_SIZE, MT_RX_BUF_SIZE,
	178	MT_RX_RING_BASE);
	179	if (ret)
	180	return ret;
	181
	182	mt76_wr(dev, MT_DELAY_INT_CFG, 0);
	183
	184	ret = mt76_init_queues(dev);
	185	if (ret < 0)
	186	return ret;
	187
8357f0dc LB	188	netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi,
	189	mt7615_poll_tx, NAPI_POLL_WEIGHT);
	190	napi_enable(&dev->mt76.tx_napi);
	191
04b8e659 RL	192	mt76_poll(dev, MT_WPDMA_GLO_CFG,
	193	MT_WPDMA_GLO_CFG_TX_DMA_BUSY \|
	194	MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000);
	195
	196	/* start dma engine */
	197	mt76_set(dev, MT_WPDMA_GLO_CFG,
	198	MT_WPDMA_GLO_CFG_TX_DMA_EN \|
	199	MT_WPDMA_GLO_CFG_RX_DMA_EN);
	200
	201	/* enable interrupts for TX/RX rings */
	202	mt7615_irq_enable(dev, MT_INT_RX_DONE_ALL \| MT_INT_TX_DONE_ALL);
	203
	204	return 0;
	205	}
	206
	207	void mt7615_dma_cleanup(struct mt7615_dev *dev)
	208	{
	209	mt76_clear(dev, MT_WPDMA_GLO_CFG,
	210	MT_WPDMA_GLO_CFG_TX_DMA_EN \|
	211	MT_WPDMA_GLO_CFG_RX_DMA_EN);
	212	mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
	213
	214	tasklet_kill(&dev->mt76.tx_tasklet);
	215	mt76_dma_cleanup(&dev->mt76);
	216	}