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mac80211_hwsim: Shared TX code for received frames and Beacons
[linux-2.6-block.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
CommitLineData
1053d35f
RR		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
fd4abac5 30#include <linux/etherdevice.h>
1053d35f
RR		 31#include <net/mac80211.h>
32#include "iwl-eeprom.h"
33#include "iwl-dev.h"
34#include "iwl-core.h"
35#include "iwl-sta.h"
36#include "iwl-io.h"
37#include "iwl-helpers.h"
38
30e553e3
TW		 39static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
57};
58
30e553e3 59
1053d35f
RR		 60/**
61 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
62 *
63 * Does NOT advance any TFD circular buffer read/write indexes
64 * Does NOT free the TFD itself (which is within circular buffer)
65 */
16466903 66int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
1053d35f
RR		 67{
68 struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
69 struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
70 struct pci_dev *dev = priv->pci_dev;
71 int i;
72 int counter = 0;
73 int index, is_odd;
74
75 /* Host command buffers stay mapped in memory, nothing to clean */
76 if (txq->q.id == IWL_CMD_QUEUE_NUM)
77 return 0;
78
79 /* Sanity check on number of chunks */
80 counter = IWL_GET_BITS(*bd, num_tbs);
81 if (counter > MAX_NUM_OF_TBS) {
82 IWL_ERROR("Too many chunks: %i\n", counter);
83 /* @todo issue fatal error, it is quite serious situation */
84 return 0;
85 }
86
87 /* Unmap chunks, if any.
88 * TFD info for odd chunks is different format than for even chunks. */
89 for (i = 0; i < counter; i++) {
90 index = i / 2;
91 is_odd = i & 0x1;
92
93 if (is_odd)
94 pci_unmap_single(
95 dev,
96 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
97 (IWL_GET_BITS(bd->pa[index],
98 tb2_addr_hi20) << 16),
99 IWL_GET_BITS(bd->pa[index], tb2_len),
100 PCI_DMA_TODEVICE);
101
102 else if (i > 0)
103 pci_unmap_single(dev,
104 le32_to_cpu(bd->pa[index].tb1_addr),
105 IWL_GET_BITS(bd->pa[index], tb1_len),
106 PCI_DMA_TODEVICE);
107
108 /* Free SKB, if any, for this chunk */
109 if (txq->txb[txq->q.read_ptr].skb[i]) {
110 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
111
112 dev_kfree_skb(skb);
113 txq->txb[txq->q.read_ptr].skb[i] = NULL;
114 }
115 }
116 return 0;
117}
118EXPORT_SYMBOL(iwl_hw_txq_free_tfd);
119
fd4abac5
TW		 120
121int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
122 dma_addr_t addr, u16 len)
123{
124 int index, is_odd;
125 struct iwl_tfd_frame *tfd = ptr;
126 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
127
128 /* Each TFD can point to a maximum 20 Tx buffers */
129 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
130 IWL_ERROR("Error can not send more than %d chunks\n",
131 MAX_NUM_OF_TBS);
132 return -EINVAL;
133 }
134
135 index = num_tbs / 2;
136 is_odd = num_tbs & 0x1;
137
138 if (!is_odd) {
139 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
140 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
141 iwl_get_dma_hi_address(addr));
142 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
143 } else {
144 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
145 (u32) (addr & 0xffff));
146 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
147 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
148 }
149
150 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
151
152 return 0;
153}
154EXPORT_SYMBOL(iwl_hw_txq_attach_buf_to_tfd);
155
156/**
157 * iwl_txq_update_write_ptr - Send new write index to hardware
158 */
159int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
160{
161 u32 reg = 0;
162 int ret = 0;
163 int txq_id = txq->q.id;
164
165 if (txq->need_update == 0)
166 return ret;
167
168 /* if we're trying to save power */
169 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
170 /* wake up nic if it's powered down ...
171 * uCode will wake up, and interrupt us again, so next
172 * time we'll skip this part. */
173 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
174
175 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
176 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
177 iwl_set_bit(priv, CSR_GP_CNTRL,
178 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
179 return ret;
180 }
181
182 /* restore this queue's parameters in nic hardware. */
183 ret = iwl_grab_nic_access(priv);
184 if (ret)
185 return ret;
186 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
187 txq->q.write_ptr | (txq_id << 8));
188 iwl_release_nic_access(priv);
189
190 /* else not in power-save mode, uCode will never sleep when we're
191 * trying to tx (during RFKILL, we're not trying to tx). */
192 } else
193 iwl_write32(priv, HBUS_TARG_WRPTR,
194 txq->q.write_ptr | (txq_id << 8));
195
196 txq->need_update = 0;
197
198 return ret;
199}
200EXPORT_SYMBOL(iwl_txq_update_write_ptr);
201
202
1053d35f
RR		 203/**
204 * iwl_tx_queue_free - Deallocate DMA queue.
205 * @txq: Transmit queue to deallocate.
206 *
207 * Empty queue by removing and destroying all BD's.
208 * Free all buffers.
209 * 0-fill, but do not free "txq" descriptor structure.
210 */
16466903 211static void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
1053d35f 212{
443cfd45 213 struct iwl_queue *q = &txq->q;
1053d35f
RR		 214 struct pci_dev *dev = priv->pci_dev;
215 int len;
216
217 if (q->n_bd == 0)
218 return;
219
220 /* first, empty all BD's */
221 for (; q->write_ptr != q->read_ptr;
222 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
223 iwl_hw_txq_free_tfd(priv, txq);
224
225 len = sizeof(struct iwl_cmd) * q->n_window;
226 if (q->id == IWL_CMD_QUEUE_NUM)
227 len += IWL_MAX_SCAN_SIZE;
228
229 /* De-alloc array of command/tx buffers */
230 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
231
232 /* De-alloc circular buffer of TFDs */
233 if (txq->q.n_bd)
234 pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) *
235 txq->q.n_bd, txq->bd, txq->q.dma_addr);
236
237 /* De-alloc array of per-TFD driver data */
238 kfree(txq->txb);
239 txq->txb = NULL;
240
241 /* 0-fill queue descriptor structure */
242 memset(txq, 0, sizeof(*txq));
243}
244
fd4abac5
TW		 245/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
246 * DMA services
247 *
248 * Theory of operation
249 *
250 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
251 * of buffer descriptors, each of which points to one or more data buffers for
252 * the device to read from or fill. Driver and device exchange status of each
253 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
254 * entries in each circular buffer, to protect against confusing empty and full
255 * queue states.
256 *
257 * The device reads or writes the data in the queues via the device's several
258 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
259 *
260 * For Tx queue, there are low mark and high mark limits. If, after queuing
261 * the packet for Tx, free space become < low mark, Tx queue stopped. When
262 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
263 * Tx queue resumed.
264 *
265 * See more detailed info in iwl-4965-hw.h.
266 ***************************************************/
267
268int iwl_queue_space(const struct iwl_queue *q)
269{
270 int s = q->read_ptr - q->write_ptr;
271
272 if (q->read_ptr > q->write_ptr)
273 s -= q->n_bd;
274
275 if (s <= 0)
276 s += q->n_window;
277 /* keep some reserve to not confuse empty and full situations */
278 s -= 2;
279 if (s < 0)
280 s = 0;
281 return s;
282}
283EXPORT_SYMBOL(iwl_queue_space);
284
285
1053d35f
RR		 286/**
287 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
288 */
443cfd45 289static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
1053d35f
RR		 290 int count, int slots_num, u32 id)
291{
292 q->n_bd = count;
293 q->n_window = slots_num;
294 q->id = id;
295
296 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
297 * and iwl_queue_dec_wrap are broken. */
298 BUG_ON(!is_power_of_2(count));
299
300 /* slots_num must be power-of-two size, otherwise
301 * get_cmd_index is broken. */
302 BUG_ON(!is_power_of_2(slots_num));
303
304 q->low_mark = q->n_window / 4;
305 if (q->low_mark < 4)
306 q->low_mark = 4;
307
308 q->high_mark = q->n_window / 8;
309 if (q->high_mark < 2)
310 q->high_mark = 2;
311
312 q->write_ptr = q->read_ptr = 0;
313
314 return 0;
315}
316
317/**
318 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
319 */
320static int iwl_tx_queue_alloc(struct iwl_priv *priv,
16466903 321 struct iwl_tx_queue *txq, u32 id)
1053d35f
RR		 322{
323 struct pci_dev *dev = priv->pci_dev;
324
325 /* Driver private data, only for Tx (not command) queues,
326 * not shared with device. */
327 if (id != IWL_CMD_QUEUE_NUM) {
328 txq->txb = kmalloc(sizeof(txq->txb[0]) *
329 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
330 if (!txq->txb) {
331 IWL_ERROR("kmalloc for auxiliary BD "
332 "structures failed\n");
333 goto error;
334 }
335 } else
336 txq->txb = NULL;
337
338 /* Circular buffer of transmit frame descriptors (TFDs),
339 * shared with device */
340 txq->bd = pci_alloc_consistent(dev,
341 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
342 &txq->q.dma_addr);
343
344 if (!txq->bd) {
345 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
346 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
347 goto error;
348 }
349 txq->q.id = id;
350
351 return 0;
352
353 error:
354 kfree(txq->txb);
355 txq->txb = NULL;
356
357 return -ENOMEM;
358}
359
360/*
361 * Tell nic where to find circular buffer of Tx Frame Descriptors for
362 * given Tx queue, and enable the DMA channel used for that queue.
363 *
364 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
365 * channels supported in hardware.
366 */
367static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
16466903 368 struct iwl_tx_queue *txq)
1053d35f
RR		 369{
370 int rc;
371 unsigned long flags;
372 int txq_id = txq->q.id;
373
374 spin_lock_irqsave(&priv->lock, flags);
375 rc = iwl_grab_nic_access(priv);
376 if (rc) {
377 spin_unlock_irqrestore(&priv->lock, flags);
378 return rc;
379 }
380
381 /* Circular buffer (TFD queue in DRAM) physical base address */
382 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
383 txq->q.dma_addr >> 8);
384
385 /* Enable DMA channel, using same id as for TFD queue */
386 iwl_write_direct32(
387 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
388 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
389 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
390 iwl_release_nic_access(priv);
391 spin_unlock_irqrestore(&priv->lock, flags);
392
393 return 0;
394}
395
396/**
397 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
398 */
399static int iwl_tx_queue_init(struct iwl_priv *priv,
16466903 400 struct iwl_tx_queue *txq,
1053d35f
RR		 401 int slots_num, u32 txq_id)
402{
403 struct pci_dev *dev = priv->pci_dev;
404 int len;
405 int rc = 0;
406
407 /*
408 * Alloc buffer array for commands (Tx or other types of commands).
409 * For the command queue (#4), allocate command space + one big
410 * command for scan, since scan command is very huge; the system will
411 * not have two scans at the same time, so only one is needed.
412 * For normal Tx queues (all other queues), no super-size command
413 * space is needed.
414 */
415 len = sizeof(struct iwl_cmd) * slots_num;
416 if (txq_id == IWL_CMD_QUEUE_NUM)
417 len += IWL_MAX_SCAN_SIZE;
418 txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
419 if (!txq->cmd)
420 return -ENOMEM;
421
422 /* Alloc driver data array and TFD circular buffer */
423 rc = iwl_tx_queue_alloc(priv, txq, txq_id);
424 if (rc) {
425 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
426
427 return -ENOMEM;
428 }
429 txq->need_update = 0;
430
431 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
432 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
433 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
434
435 /* Initialize queue's high/low-water marks, and head/tail indexes */
436 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
437
438 /* Tell device where to find queue */
439 iwl_hw_tx_queue_init(priv, txq);
440
441 return 0;
442}
da1bc453
TW		 443/**
444 * iwl_hw_txq_ctx_free - Free TXQ Context
445 *
446 * Destroy all TX DMA queues and structures
447 */
448void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
449{
450 int txq_id;
451
452 /* Tx queues */
453 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
454 iwl_tx_queue_free(priv, &priv->txq[txq_id]);
455
456 /* Keep-warm buffer */
457 iwl_kw_free(priv);
458}
459EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
460
1053d35f
RR		 461
462/**
463 * iwl_txq_ctx_reset - Reset TX queue context
464 * Destroys all DMA structures and initialise them again
465 *
466 * @param priv
467 * @return error code
468 */
469int iwl_txq_ctx_reset(struct iwl_priv *priv)
470{
471 int ret = 0;
472 int txq_id, slots_num;
da1bc453 473 unsigned long flags;
1053d35f
RR		 474
475 iwl_kw_free(priv);
476
477 /* Free all tx/cmd queues and keep-warm buffer */
478 iwl_hw_txq_ctx_free(priv);
479
480 /* Alloc keep-warm buffer */
481 ret = iwl_kw_alloc(priv);
482 if (ret) {
483 IWL_ERROR("Keep Warm allocation failed");
484 goto error_kw;
485 }
da1bc453
TW		 486 spin_lock_irqsave(&priv->lock, flags);
487 ret = iwl_grab_nic_access(priv);
488 if (unlikely(ret)) {
489 spin_unlock_irqrestore(&priv->lock, flags);
490 goto error_reset;
491 }
1053d35f
RR		 492
493 /* Turn off all Tx DMA fifos */
da1bc453
TW		 494 priv->cfg->ops->lib->txq_set_sched(priv, 0);
495
496 iwl_release_nic_access(priv);
497 spin_unlock_irqrestore(&priv->lock, flags);
498
1053d35f
RR		 499
500 /* Tell nic where to find the keep-warm buffer */
501 ret = iwl_kw_init(priv);
502 if (ret) {
503 IWL_ERROR("kw_init failed\n");
504 goto error_reset;
505 }
506
da1bc453 507 /* Alloc and init all Tx queues, including the command queue (#4) */
1053d35f
RR		 508 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
509 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
510 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
511 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
512 txq_id);
513 if (ret) {
514 IWL_ERROR("Tx %d queue init failed\n", txq_id);
515 goto error;
516 }
517 }
518
519 return ret;
520
521 error:
522 iwl_hw_txq_ctx_free(priv);
523 error_reset:
524 iwl_kw_free(priv);
525 error_kw:
526 return ret;
527}
da1bc453
TW		 528/**
529 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
530 */
531void iwl_txq_ctx_stop(struct iwl_priv *priv)
532{
533
534 int txq_id;
535 unsigned long flags;
536
537
538 /* Turn off all Tx DMA fifos */
539 spin_lock_irqsave(&priv->lock, flags);
540 if (iwl_grab_nic_access(priv)) {
541 spin_unlock_irqrestore(&priv->lock, flags);
542 return;
543 }
544
545 priv->cfg->ops->lib->txq_set_sched(priv, 0);
546
547 /* Stop each Tx DMA channel, and wait for it to be idle */
548 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
549 iwl_write_direct32(priv,
550 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
551 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
552 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
553 (txq_id), 200);
554 }
555 iwl_release_nic_access(priv);
556 spin_unlock_irqrestore(&priv->lock, flags);
557
558 /* Deallocate memory for all Tx queues */
559 iwl_hw_txq_ctx_free(priv);
560}
561EXPORT_SYMBOL(iwl_txq_ctx_stop);
fd4abac5
TW		 562
563/*
564 * handle build REPLY_TX command notification.
565 */
566static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
567 struct iwl_tx_cmd *tx_cmd,
e039fa4a 568 struct ieee80211_tx_info *info,
fd4abac5
TW		 569 struct ieee80211_hdr *hdr,
570 int is_unicast, u8 std_id)
571{
572 u16 fc = le16_to_cpu(hdr->frame_control);
573 __le32 tx_flags = tx_cmd->tx_flags;
574
575 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 576 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
fd4abac5
TW		 577 tx_flags |= TX_CMD_FLG_ACK_MSK;
578 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
579 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
580 if (ieee80211_is_probe_response(fc) &&
581 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
582 tx_flags |= TX_CMD_FLG_TSF_MSK;
583 } else {
584 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
585 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
586 }
587
588 if (ieee80211_is_back_request(fc))
589 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
590
591
592 tx_cmd->sta_id = std_id;
593 if (ieee80211_get_morefrag(hdr))
594 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
595
596 if (ieee80211_is_qos_data(fc)) {
597 u8 *qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
598 tx_cmd->tid_tspec = qc[0] & 0xf;
599 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
600 } else {
601 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
602 }
603
e039fa4a 604 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
fd4abac5
TW		 605 tx_flags |= TX_CMD_FLG_RTS_MSK;
606 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e039fa4a 607 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
fd4abac5
TW		 608 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
609 tx_flags |= TX_CMD_FLG_CTS_MSK;
610 }
611
612 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
613 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
614
615 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
616 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
617 if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
618 (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
619 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
620 else
621 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
622 } else {
623 tx_cmd->timeout.pm_frame_timeout = 0;
624 }
625
626 tx_cmd->driver_txop = 0;
627 tx_cmd->tx_flags = tx_flags;
628 tx_cmd->next_frame_len = 0;
629}
630
631#define RTS_HCCA_RETRY_LIMIT 3
632#define RTS_DFAULT_RETRY_LIMIT 60
633
634static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
635 struct iwl_tx_cmd *tx_cmd,
e039fa4a 636 struct ieee80211_tx_info *info,
fd4abac5
TW		 637 u16 fc, int sta_id,
638 int is_hcca)
639{
640 u8 rts_retry_limit = 0;
641 u8 data_retry_limit = 0;
642 u8 rate_plcp;
643 u16 rate_flags = 0;
2e92e6f2
JB		 644 int rate_idx;
645
e039fa4a 646 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
2e92e6f2 647 IWL_RATE_COUNT - 1);
fd4abac5
TW		 648
649 rate_plcp = iwl_rates[rate_idx].plcp;
650
651 rts_retry_limit = (is_hcca) ?
652 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
653
654 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
655 rate_flags |= RATE_MCS_CCK_MSK;
656
657
658 if (ieee80211_is_probe_response(fc)) {
659 data_retry_limit = 3;
660 if (data_retry_limit < rts_retry_limit)
661 rts_retry_limit = data_retry_limit;
662 } else
663 data_retry_limit = IWL_DEFAULT_TX_RETRY;
664
665 if (priv->data_retry_limit != -1)
666 data_retry_limit = priv->data_retry_limit;
667
668
669 if (ieee80211_is_data(fc)) {
670 tx_cmd->initial_rate_index = 0;
671 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
672 } else {
673 switch (fc & IEEE80211_FCTL_STYPE) {
674 case IEEE80211_STYPE_AUTH:
675 case IEEE80211_STYPE_DEAUTH:
676 case IEEE80211_STYPE_ASSOC_REQ:
677 case IEEE80211_STYPE_REASSOC_REQ:
678 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
679 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
680 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
681 }
682 break;
683 default:
684 break;
685 }
686
687 /* Alternate between antenna A and B for successive frames */
688 if (priv->use_ant_b_for_management_frame) {
689 priv->use_ant_b_for_management_frame = 0;
690 rate_flags |= RATE_MCS_ANT_B_MSK;
691 } else {
692 priv->use_ant_b_for_management_frame = 1;
693 rate_flags |= RATE_MCS_ANT_A_MSK;
694 }
695 }
696
697 tx_cmd->rts_retry_limit = rts_retry_limit;
698 tx_cmd->data_retry_limit = data_retry_limit;
e7d326ac 699 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
fd4abac5
TW		 700}
701
702static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
e039fa4a 703 struct ieee80211_tx_info *info,
fd4abac5
TW		 704 struct iwl_tx_cmd *tx_cmd,
705 struct sk_buff *skb_frag,
706 int sta_id)
707{
e039fa4a 708 struct ieee80211_key_conf *keyconf = info->control.hw_key;
fd4abac5 709
ccc038ab 710 switch (keyconf->alg) {
fd4abac5
TW		 711 case ALG_CCMP:
712 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
ccc038ab 713 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
e039fa4a 714 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 715 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
716 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
717 break;
718
719 case ALG_TKIP:
720 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
ccc038ab 721 ieee80211_get_tkip_key(keyconf, skb_frag,
fd4abac5
TW		 722 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
723 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
724 break;
725
726 case ALG_WEP:
fd4abac5 727 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
ccc038ab
EG		 728 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
729
730 if (keyconf->keylen == WEP_KEY_LEN_128)
731 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
732
733 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
fd4abac5
TW		 734
735 IWL_DEBUG_TX("Configuring packet for WEP encryption "
ccc038ab 736 "with key %d\n", keyconf->keyidx);
fd4abac5
TW		 737 break;
738
739 default:
ccc038ab 740 printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg);
fd4abac5
TW		 741 break;
742 }
743}
744
745static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
746{
747 /* 0 - mgmt, 1 - cnt, 2 - data */
748 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
749 priv->tx_stats[idx].cnt++;
750 priv->tx_stats[idx].bytes += len;
751}
752
753/*
754 * start REPLY_TX command process
755 */
e039fa4a 756int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
fd4abac5
TW		 757{
758 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 759 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fd4abac5
TW		 760 struct iwl_tfd_frame *tfd;
761 u32 *control_flags;
e2530083 762 int txq_id = skb_get_queue_mapping(skb);
fd4abac5
TW		 763 struct iwl_tx_queue *txq = NULL;
764 struct iwl_queue *q = NULL;
765 dma_addr_t phys_addr;
766 dma_addr_t txcmd_phys;
767 dma_addr_t scratch_phys;
768 struct iwl_cmd *out_cmd = NULL;
769 struct iwl_tx_cmd *tx_cmd;
770 u16 len, idx, len_org;
771 u16 seq_number = 0;
772 u8 id, hdr_len, unicast;
773 u8 sta_id;
774 u16 fc;
775 u8 wait_write_ptr = 0;
776 u8 tid = 0;
777 u8 *qc = NULL;
778 unsigned long flags;
779 int ret;
780
781 spin_lock_irqsave(&priv->lock, flags);
782 if (iwl_is_rfkill(priv)) {
783 IWL_DEBUG_DROP("Dropping - RF KILL\n");
784 goto drop_unlock;
785 }
786
787 if (!priv->vif) {
788 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
789 goto drop_unlock;
790 }
791
e039fa4a 792 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
2e92e6f2 793 IWL_INVALID_RATE) {
fd4abac5
TW		 794 IWL_ERROR("ERROR: No TX rate available.\n");
795 goto drop_unlock;
796 }
797
798 unicast = !is_multicast_ether_addr(hdr->addr1);
799 id = 0;
800
801 fc = le16_to_cpu(hdr->frame_control);
802
803#ifdef CONFIG_IWLWIFI_DEBUG
804 if (ieee80211_is_auth(fc))
805 IWL_DEBUG_TX("Sending AUTH frame\n");
806 else if (ieee80211_is_assoc_request(fc))
807 IWL_DEBUG_TX("Sending ASSOC frame\n");
808 else if (ieee80211_is_reassoc_request(fc))
809 IWL_DEBUG_TX("Sending REASSOC frame\n");
810#endif
811
812 /* drop all data frame if we are not associated */
813 if (((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) &&
814 (!iwl_is_associated(priv) ||
815 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) ||
816 !priv->assoc_station_added)) {
817 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
818 goto drop_unlock;
819 }
820
821 spin_unlock_irqrestore(&priv->lock, flags);
822
823 hdr_len = ieee80211_get_hdrlen(fc);
824
825 /* Find (or create) index into station table for destination station */
826 sta_id = iwl_get_sta_id(priv, hdr);
827 if (sta_id == IWL_INVALID_STATION) {
828 DECLARE_MAC_BUF(mac);
829
830 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
831 print_mac(mac, hdr->addr1));
832 goto drop;
833 }
834
835 IWL_DEBUG_TX("station Id %d\n", sta_id);
836
837 if (ieee80211_is_qos_data(fc)) {
838 qc = ieee80211_get_qos_ctrl(hdr, hdr_len);
839 tid = qc[0] & 0xf;
840 seq_number = priv->stations[sta_id].tid[tid].seq_number &
841 IEEE80211_SCTL_SEQ;
842 hdr->seq_ctrl = cpu_to_le16(seq_number) |
843 (hdr->seq_ctrl &
844 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
845 seq_number += 0x10;
fd4abac5 846 /* aggregation is on for this <sta,tid> */
e039fa4a 847 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 848 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
849 priv->stations[sta_id].tid[tid].tfds_in_queue++;
fd4abac5
TW		 850 }
851
852 /* Descriptor for chosen Tx queue */
853 txq = &priv->txq[txq_id];
854 q = &txq->q;
855
856 spin_lock_irqsave(&priv->lock, flags);
857
858 /* Set up first empty TFD within this queue's circular TFD buffer */
859 tfd = &txq->bd[q->write_ptr];
860 memset(tfd, 0, sizeof(*tfd));
861 control_flags = (u32 *) tfd;
862 idx = get_cmd_index(q, q->write_ptr, 0);
863
864 /* Set up driver data for this TFD */
865 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
866 txq->txb[q->write_ptr].skb[0] = skb;
fd4abac5
TW		 867
868 /* Set up first empty entry in queue's array of Tx/cmd buffers */
869 out_cmd = &txq->cmd[idx];
870 tx_cmd = &out_cmd->cmd.tx;
871 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
872 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
873
874 /*
875 * Set up the Tx-command (not MAC!) header.
876 * Store the chosen Tx queue and TFD index within the sequence field;
877 * after Tx, uCode's Tx response will return this value so driver can
878 * locate the frame within the tx queue and do post-tx processing.
879 */
880 out_cmd->hdr.cmd = REPLY_TX;
881 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
882 INDEX_TO_SEQ(q->write_ptr)));
883
884 /* Copy MAC header from skb into command buffer */
885 memcpy(tx_cmd->hdr, hdr, hdr_len);
886
887 /*
888 * Use the first empty entry in this queue's command buffer array
889 * to contain the Tx command and MAC header concatenated together
890 * (payload data will be in another buffer).
891 * Size of this varies, due to varying MAC header length.
892 * If end is not dword aligned, we'll have 2 extra bytes at the end
893 * of the MAC header (device reads on dword boundaries).
894 * We'll tell device about this padding later.
895 */
896 len = sizeof(struct iwl_tx_cmd) +
897 sizeof(struct iwl_cmd_header) + hdr_len;
898
899 len_org = len;
900 len = (len + 3) & ~3;
901
902 if (len_org != len)
903 len_org = 1;
904 else
905 len_org = 0;
906
907 /* Physical address of this Tx command's header (not MAC header!),
908 * within command buffer array. */
909 txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx +
910 offsetof(struct iwl_cmd, hdr);
911
912 /* Add buffer containing Tx command and MAC(!) header to TFD's
913 * first entry */
914 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
915
e039fa4a
JB		 916 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT))
917 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
fd4abac5
TW		 918
919 /* Set up TFD's 2nd entry to point directly to remainder of skb,
920 * if any (802.11 null frames have no payload). */
921 len = skb->len - hdr_len;
922 if (len) {
923 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
924 len, PCI_DMA_TODEVICE);
925 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
926 }
927
928 /* Tell NIC about any 2-byte padding after MAC header */
929 if (len_org)
930 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
931
932 /* Total # bytes to be transmitted */
933 len = (u16)skb->len;
934 tx_cmd->len = cpu_to_le16(len);
935 /* TODO need this for burst mode later on */
e039fa4a 936 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id);
fd4abac5
TW		 937
938 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 939 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
fd4abac5
TW		 940
941 iwl_update_tx_stats(priv, fc, len);
942
943 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
944 offsetof(struct iwl_tx_cmd, scratch);
945 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
946 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
947
948 if (!ieee80211_get_morefrag(hdr)) {
949 txq->need_update = 1;
950 if (qc)
951 priv->stations[sta_id].tid[tid].seq_number = seq_number;
952 } else {
953 wait_write_ptr = 1;
954 txq->need_update = 0;
955 }
956
957 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
958
959 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
960
961 /* Set up entry for this TFD in Tx byte-count array */
962 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
963
964 /* Tell device the write index *just past* this latest filled TFD */
965 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
966 ret = iwl_txq_update_write_ptr(priv, txq);
967 spin_unlock_irqrestore(&priv->lock, flags);
968
969 if (ret)
970 return ret;
971
972 if ((iwl_queue_space(q) < q->high_mark)
973 && priv->mac80211_registered) {
974 if (wait_write_ptr) {
975 spin_lock_irqsave(&priv->lock, flags);
976 txq->need_update = 1;
977 iwl_txq_update_write_ptr(priv, txq);
978 spin_unlock_irqrestore(&priv->lock, flags);
979 }
980
e2530083 981 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
fd4abac5
TW		 982 }
983
984 return 0;
985
986drop_unlock:
987 spin_unlock_irqrestore(&priv->lock, flags);
988drop:
989 return -1;
990}
991EXPORT_SYMBOL(iwl_tx_skb);
992
993/*************** HOST COMMAND QUEUE FUNCTIONS *****/
994
995/**
996 * iwl_enqueue_hcmd - enqueue a uCode command
997 * @priv: device private data point
998 * @cmd: a point to the ucode command structure
999 *
1000 * The function returns < 0 values to indicate the operation is
1001 * failed. On success, it turns the index (> 0) of command in the
1002 * command queue.
1003 */
1004int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1005{
1006 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1007 struct iwl_queue *q = &txq->q;
1008 struct iwl_tfd_frame *tfd;
1009 u32 *control_flags;
1010 struct iwl_cmd *out_cmd;
1011 u32 idx;
1012 u16 fix_size;
1013 dma_addr_t phys_addr;
1014 int ret;
1015 unsigned long flags;
1016
1017 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1018 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1019
1020 /* If any of the command structures end up being larger than
1021 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1022 * we will need to increase the size of the TFD entries */
1023 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1024 !(cmd->meta.flags & CMD_SIZE_HUGE));
1025
1026 if (iwl_is_rfkill(priv)) {
1027 IWL_DEBUG_INFO("Not sending command - RF KILL");
1028 return -EIO;
1029 }
1030
1031 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
1032 IWL_ERROR("No space for Tx\n");
1033 return -ENOSPC;
1034 }
1035
1036 spin_lock_irqsave(&priv->hcmd_lock, flags);
1037
1038 tfd = &txq->bd[q->write_ptr];
1039 memset(tfd, 0, sizeof(*tfd));
1040
1041 control_flags = (u32 *) tfd;
1042
1043 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
1044 out_cmd = &txq->cmd[idx];
1045
1046 out_cmd->hdr.cmd = cmd->id;
1047 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
1048 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1049
1050 /* At this point, the out_cmd now has all of the incoming cmd
1051 * information */
1052
1053 out_cmd->hdr.flags = 0;
1054 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1055 INDEX_TO_SEQ(q->write_ptr));
1056 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
1057 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
1058
1059 phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
1060 offsetof(struct iwl_cmd, hdr);
1061 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
1062
1063 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1064 "%d bytes at %d[%d]:%d\n",
1065 get_cmd_string(out_cmd->hdr.cmd),
1066 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1067 fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1068
1069 txq->need_update = 1;
1070
1071 /* Set up entry in queue's byte count circular buffer */
1072 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1073
1074 /* Increment and update queue's write index */
1075 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1076 ret = iwl_txq_update_write_ptr(priv, txq);
1077
1078 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1079 return ret ? ret : idx;
1080}
1081
17b88929
TW		 1082int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1083{
1084 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1085 struct iwl_queue *q = &txq->q;
1086 struct iwl_tx_info *tx_info;
1087 int nfreed = 0;
1088
1089 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1090 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1091 "is out of range [0-%d] %d %d.\n", txq_id,
1092 index, q->n_bd, q->write_ptr, q->read_ptr);
1093 return 0;
1094 }
1095
1096 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1097 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1098
1099 tx_info = &txq->txb[txq->q.read_ptr];
1100 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1101 tx_info->skb[0] = NULL;
17b88929 1102
972cf447
TW		 1103 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1104 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1105
1106 iwl_hw_txq_free_tfd(priv, txq);
17b88929
TW		 1107 nfreed++;
1108 }
1109 return nfreed;
1110}
1111EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1112
1113
1114/**
1115 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1116 *
1117 * When FW advances 'R' index, all entries between old and new 'R' index
1118 * need to be reclaimed. As result, some free space forms. If there is
1119 * enough free space (> low mark), wake the stack that feeds us.
1120 */
1121static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1122{
1123 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1124 struct iwl_queue *q = &txq->q;
1125 int nfreed = 0;
1126
1127 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1128 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1129 "is out of range [0-%d] %d %d.\n", txq_id,
1130 index, q->n_bd, q->write_ptr, q->read_ptr);
1131 return;
1132 }
1133
1134 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1135 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1136
1137 if (nfreed > 1) {
1138 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
1139 q->write_ptr, q->read_ptr);
1140 queue_work(priv->workqueue, &priv->restart);
1141 }
1142 nfreed++;
1143 }
1144}
1145
1146/**
1147 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1148 * @rxb: Rx buffer to reclaim
1149 *
1150 * If an Rx buffer has an async callback associated with it the callback
1151 * will be executed. The attached skb (if present) will only be freed
1152 * if the callback returns 1
1153 */
1154void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1155{
1156 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1157 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1158 int txq_id = SEQ_TO_QUEUE(sequence);
1159 int index = SEQ_TO_INDEX(sequence);
1160 int huge = sequence & SEQ_HUGE_FRAME;
1161 int cmd_index;
1162 struct iwl_cmd *cmd;
1163
1164 /* If a Tx command is being handled and it isn't in the actual
1165 * command queue then there a command routing bug has been introduced
1166 * in the queue management code. */
1167 if (txq_id != IWL_CMD_QUEUE_NUM)
1168 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
1169 txq_id, pkt->hdr.cmd);
1170 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
1171
1172 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1173 cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1174
1175 /* Input error checking is done when commands are added to queue. */
1176 if (cmd->meta.flags & CMD_WANT_SKB) {
1177 cmd->meta.source->u.skb = rxb->skb;
1178 rxb->skb = NULL;
1179 } else if (cmd->meta.u.callback &&
1180 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1181 rxb->skb = NULL;
1182
1183 iwl_hcmd_queue_reclaim(priv, txq_id, index);
1184
1185 if (!(cmd->meta.flags & CMD_ASYNC)) {
1186 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1187 wake_up_interruptible(&priv->wait_command_queue);
1188 }
1189}
1190EXPORT_SYMBOL(iwl_tx_cmd_complete);
1191
30e553e3
TW		 1192/*
1193 * Find first available (lowest unused) Tx Queue, mark it "active".
1194 * Called only when finding queue for aggregation.
1195 * Should never return anything < 7, because they should already
1196 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1197 */
1198static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1199{
1200 int txq_id;
1201
1202 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1203 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1204 return txq_id;
1205 return -1;
1206}
1207
1208int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1209{
1210 int sta_id;
1211 int tx_fifo;
1212 int txq_id;
1213 int ret;
1214 unsigned long flags;
1215 struct iwl_tid_data *tid_data;
1216 DECLARE_MAC_BUF(mac);
1217
1218 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1219 tx_fifo = default_tid_to_tx_fifo[tid];
1220 else
1221 return -EINVAL;
1222
1223 IWL_WARNING("%s on ra = %s tid = %d\n",
1224 __func__, print_mac(mac, ra), tid);
1225
1226 sta_id = iwl_find_station(priv, ra);
1227 if (sta_id == IWL_INVALID_STATION)
1228 return -ENXIO;
1229
1230 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1231 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
1232 return -ENXIO;
1233 }
1234
1235 txq_id = iwl_txq_ctx_activate_free(priv);
1236 if (txq_id == -1)
1237 return -ENXIO;
1238
1239 spin_lock_irqsave(&priv->sta_lock, flags);
1240 tid_data = &priv->stations[sta_id].tid[tid];
1241 *ssn = SEQ_TO_SN(tid_data->seq_number);
1242 tid_data->agg.txq_id = txq_id;
1243 spin_unlock_irqrestore(&priv->sta_lock, flags);
1244
1245 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1246 sta_id, tid, *ssn);
1247 if (ret)
1248 return ret;
1249
1250 if (tid_data->tfds_in_queue == 0) {
1251 printk(KERN_ERR "HW queue is empty\n");
1252 tid_data->agg.state = IWL_AGG_ON;
1253 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1254 } else {
1255 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1256 tid_data->tfds_in_queue);
1257 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1258 }
1259 return ret;
1260}
1261EXPORT_SYMBOL(iwl_tx_agg_start);
1262
1263int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1264{
1265 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1266 struct iwl_tid_data *tid_data;
1267 int ret, write_ptr, read_ptr;
1268 unsigned long flags;
1269 DECLARE_MAC_BUF(mac);
1270
1271 if (!ra) {
1272 IWL_ERROR("ra = NULL\n");
1273 return -EINVAL;
1274 }
1275
1276 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1277 tx_fifo_id = default_tid_to_tx_fifo[tid];
1278 else
1279 return -EINVAL;
1280
1281 sta_id = iwl_find_station(priv, ra);
1282
1283 if (sta_id == IWL_INVALID_STATION)
1284 return -ENXIO;
1285
1286 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1287 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
1288
1289 tid_data = &priv->stations[sta_id].tid[tid];
1290 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1291 txq_id = tid_data->agg.txq_id;
1292 write_ptr = priv->txq[txq_id].q.write_ptr;
1293 read_ptr = priv->txq[txq_id].q.read_ptr;
1294
1295 /* The queue is not empty */
1296 if (write_ptr != read_ptr) {
1297 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1298 priv->stations[sta_id].tid[tid].agg.state =
1299 IWL_EMPTYING_HW_QUEUE_DELBA;
1300 return 0;
1301 }
1302
1303 IWL_DEBUG_HT("HW queue is empty\n");
1304 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1305
1306 spin_lock_irqsave(&priv->lock, flags);
1307 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1308 tx_fifo_id);
1309 spin_unlock_irqrestore(&priv->lock, flags);
1310
1311 if (ret)
1312 return ret;
1313
1314 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1315
1316 return 0;
1317}
1318EXPORT_SYMBOL(iwl_tx_agg_stop);
1319
1320int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1321{
1322 struct iwl_queue *q = &priv->txq[txq_id].q;
1323 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1324 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1325
1326 switch (priv->stations[sta_id].tid[tid].agg.state) {
1327 case IWL_EMPTYING_HW_QUEUE_DELBA:
1328 /* We are reclaiming the last packet of the */
1329 /* aggregated HW queue */
1330 if (txq_id == tid_data->agg.txq_id &&
1331 q->read_ptr == q->write_ptr) {
1332 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1333 int tx_fifo = default_tid_to_tx_fifo[tid];
1334 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1335 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1336 ssn, tx_fifo);
1337 tid_data->agg.state = IWL_AGG_OFF;
1338 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1339 }
1340 break;
1341 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1342 /* We are reclaiming the last packet of the queue */
1343 if (tid_data->tfds_in_queue == 0) {
1344 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1345 tid_data->agg.state = IWL_AGG_ON;
1346 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1347 }
1348 break;
1349 }
1350 return 0;
1351}
1352EXPORT_SYMBOL(iwl_txq_check_empty);
30e553e3 1353
a332f8d6
TW		 1354#ifdef CONFIG_IWLWIF_DEBUG
1355#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1356
1357const char *iwl_get_tx_fail_reason(u32 status)
1358{
1359 switch (status & TX_STATUS_MSK) {
1360 case TX_STATUS_SUCCESS:
1361 return "SUCCESS";
1362 TX_STATUS_ENTRY(SHORT_LIMIT);
1363 TX_STATUS_ENTRY(LONG_LIMIT);
1364 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1365 TX_STATUS_ENTRY(MGMNT_ABORT);
1366 TX_STATUS_ENTRY(NEXT_FRAG);
1367 TX_STATUS_ENTRY(LIFE_EXPIRE);
1368 TX_STATUS_ENTRY(DEST_PS);
1369 TX_STATUS_ENTRY(ABORTED);
1370 TX_STATUS_ENTRY(BT_RETRY);
1371 TX_STATUS_ENTRY(STA_INVALID);
1372 TX_STATUS_ENTRY(FRAG_DROPPED);
1373 TX_STATUS_ENTRY(TID_DISABLE);
1374 TX_STATUS_ENTRY(FRAME_FLUSHED);
1375 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1376 TX_STATUS_ENTRY(TX_LOCKED);
1377 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1378 }
1379
1380 return "UNKNOWN";
1381}
1382EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1383#endif /* CONFIG_IWLWIFI_DEBUG */
Linux 6.x block layer and io_uring tree(s)