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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
1053d35f RR |
31 | #include <net/mac80211.h> |
32 | #include "iwl-eeprom.h" | |
33 | #include "iwl-dev.h" | |
34 | #include "iwl-core.h" | |
35 | #include "iwl-sta.h" | |
36 | #include "iwl-io.h" | |
37 | #include "iwl-helpers.h" | |
38 | ||
30e553e3 TW |
39 | static const u16 default_tid_to_tx_fifo[] = { |
40 | IWL_TX_FIFO_AC1, | |
41 | IWL_TX_FIFO_AC0, | |
42 | IWL_TX_FIFO_AC0, | |
43 | IWL_TX_FIFO_AC1, | |
44 | IWL_TX_FIFO_AC2, | |
45 | IWL_TX_FIFO_AC2, | |
46 | IWL_TX_FIFO_AC3, | |
47 | IWL_TX_FIFO_AC3, | |
48 | IWL_TX_FIFO_NONE, | |
49 | IWL_TX_FIFO_NONE, | |
50 | IWL_TX_FIFO_NONE, | |
51 | IWL_TX_FIFO_NONE, | |
52 | IWL_TX_FIFO_NONE, | |
53 | IWL_TX_FIFO_NONE, | |
54 | IWL_TX_FIFO_NONE, | |
55 | IWL_TX_FIFO_NONE, | |
56 | IWL_TX_FIFO_AC3 | |
57 | }; | |
58 | ||
4ddbb7d0 TW |
59 | static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv, |
60 | struct iwl_dma_ptr *ptr, size_t size) | |
61 | { | |
62 | ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma); | |
63 | if (!ptr->addr) | |
64 | return -ENOMEM; | |
65 | ptr->size = size; | |
66 | return 0; | |
67 | } | |
68 | ||
69 | static inline void iwl_free_dma_ptr(struct iwl_priv *priv, | |
70 | struct iwl_dma_ptr *ptr) | |
71 | { | |
72 | if (unlikely(!ptr->addr)) | |
73 | return; | |
74 | ||
75 | pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma); | |
76 | memset(ptr, 0, sizeof(*ptr)); | |
77 | } | |
78 | ||
fd4abac5 TW |
79 | /** |
80 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
81 | */ | |
82 | int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
83 | { | |
84 | u32 reg = 0; | |
85 | int ret = 0; | |
86 | int txq_id = txq->q.id; | |
87 | ||
88 | if (txq->need_update == 0) | |
89 | return ret; | |
90 | ||
91 | /* if we're trying to save power */ | |
92 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
93 | /* wake up nic if it's powered down ... | |
94 | * uCode will wake up, and interrupt us again, so next | |
95 | * time we'll skip this part. */ | |
96 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
97 | ||
98 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
e1623446 | 99 | IWL_DEBUG_INFO(priv, "Requesting wakeup, GP1 = 0x%x\n", reg); |
fd4abac5 TW |
100 | iwl_set_bit(priv, CSR_GP_CNTRL, |
101 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
102 | return ret; | |
103 | } | |
104 | ||
105 | /* restore this queue's parameters in nic hardware. */ | |
106 | ret = iwl_grab_nic_access(priv); | |
107 | if (ret) | |
108 | return ret; | |
109 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
110 | txq->q.write_ptr | (txq_id << 8)); | |
111 | iwl_release_nic_access(priv); | |
112 | ||
113 | /* else not in power-save mode, uCode will never sleep when we're | |
114 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
115 | } else | |
116 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
117 | txq->q.write_ptr | (txq_id << 8)); | |
118 | ||
119 | txq->need_update = 0; | |
120 | ||
121 | return ret; | |
122 | } | |
123 | EXPORT_SYMBOL(iwl_txq_update_write_ptr); | |
124 | ||
125 | ||
1053d35f RR |
126 | /** |
127 | * iwl_tx_queue_free - Deallocate DMA queue. | |
128 | * @txq: Transmit queue to deallocate. | |
129 | * | |
130 | * Empty queue by removing and destroying all BD's. | |
131 | * Free all buffers. | |
132 | * 0-fill, but do not free "txq" descriptor structure. | |
133 | */ | |
a8e74e27 | 134 | void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
1053d35f | 135 | { |
da99c4b6 | 136 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
443cfd45 | 137 | struct iwl_queue *q = &txq->q; |
1053d35f | 138 | struct pci_dev *dev = priv->pci_dev; |
961ba60a | 139 | int i, len; |
1053d35f RR |
140 | |
141 | if (q->n_bd == 0) | |
142 | return; | |
143 | ||
144 | /* first, empty all BD's */ | |
145 | for (; q->write_ptr != q->read_ptr; | |
146 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) | |
7aaa1d79 | 147 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
1053d35f RR |
148 | |
149 | len = sizeof(struct iwl_cmd) * q->n_window; | |
1053d35f RR |
150 | |
151 | /* De-alloc array of command/tx buffers */ | |
961ba60a | 152 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) |
da99c4b6 | 153 | kfree(txq->cmd[i]); |
1053d35f RR |
154 | |
155 | /* De-alloc circular buffer of TFDs */ | |
156 | if (txq->q.n_bd) | |
a8e74e27 | 157 | pci_free_consistent(dev, priv->hw_params.tfd_size * |
499b1883 | 158 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
1053d35f RR |
159 | |
160 | /* De-alloc array of per-TFD driver data */ | |
161 | kfree(txq->txb); | |
162 | txq->txb = NULL; | |
163 | ||
164 | /* 0-fill queue descriptor structure */ | |
165 | memset(txq, 0, sizeof(*txq)); | |
166 | } | |
a8e74e27 | 167 | EXPORT_SYMBOL(iwl_tx_queue_free); |
961ba60a TW |
168 | |
169 | /** | |
170 | * iwl_cmd_queue_free - Deallocate DMA queue. | |
171 | * @txq: Transmit queue to deallocate. | |
172 | * | |
173 | * Empty queue by removing and destroying all BD's. | |
174 | * Free all buffers. | |
175 | * 0-fill, but do not free "txq" descriptor structure. | |
176 | */ | |
177 | static void iwl_cmd_queue_free(struct iwl_priv *priv) | |
178 | { | |
179 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
180 | struct iwl_queue *q = &txq->q; | |
181 | struct pci_dev *dev = priv->pci_dev; | |
182 | int i, len; | |
183 | ||
184 | if (q->n_bd == 0) | |
185 | return; | |
186 | ||
187 | len = sizeof(struct iwl_cmd) * q->n_window; | |
188 | len += IWL_MAX_SCAN_SIZE; | |
189 | ||
190 | /* De-alloc array of command/tx buffers */ | |
191 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
192 | kfree(txq->cmd[i]); | |
193 | ||
194 | /* De-alloc circular buffer of TFDs */ | |
195 | if (txq->q.n_bd) | |
499b1883 TW |
196 | pci_free_consistent(dev, sizeof(struct iwl_tfd) * |
197 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
961ba60a TW |
198 | |
199 | /* 0-fill queue descriptor structure */ | |
200 | memset(txq, 0, sizeof(*txq)); | |
201 | } | |
fd4abac5 TW |
202 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
203 | * DMA services | |
204 | * | |
205 | * Theory of operation | |
206 | * | |
207 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
208 | * of buffer descriptors, each of which points to one or more data buffers for | |
209 | * the device to read from or fill. Driver and device exchange status of each | |
210 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
211 | * entries in each circular buffer, to protect against confusing empty and full | |
212 | * queue states. | |
213 | * | |
214 | * The device reads or writes the data in the queues via the device's several | |
215 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
216 | * | |
217 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
218 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
219 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
220 | * Tx queue resumed. | |
221 | * | |
222 | * See more detailed info in iwl-4965-hw.h. | |
223 | ***************************************************/ | |
224 | ||
225 | int iwl_queue_space(const struct iwl_queue *q) | |
226 | { | |
227 | int s = q->read_ptr - q->write_ptr; | |
228 | ||
229 | if (q->read_ptr > q->write_ptr) | |
230 | s -= q->n_bd; | |
231 | ||
232 | if (s <= 0) | |
233 | s += q->n_window; | |
234 | /* keep some reserve to not confuse empty and full situations */ | |
235 | s -= 2; | |
236 | if (s < 0) | |
237 | s = 0; | |
238 | return s; | |
239 | } | |
240 | EXPORT_SYMBOL(iwl_queue_space); | |
241 | ||
242 | ||
1053d35f RR |
243 | /** |
244 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
245 | */ | |
443cfd45 | 246 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
247 | int count, int slots_num, u32 id) |
248 | { | |
249 | q->n_bd = count; | |
250 | q->n_window = slots_num; | |
251 | q->id = id; | |
252 | ||
253 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
254 | * and iwl_queue_dec_wrap are broken. */ | |
255 | BUG_ON(!is_power_of_2(count)); | |
256 | ||
257 | /* slots_num must be power-of-two size, otherwise | |
258 | * get_cmd_index is broken. */ | |
259 | BUG_ON(!is_power_of_2(slots_num)); | |
260 | ||
261 | q->low_mark = q->n_window / 4; | |
262 | if (q->low_mark < 4) | |
263 | q->low_mark = 4; | |
264 | ||
265 | q->high_mark = q->n_window / 8; | |
266 | if (q->high_mark < 2) | |
267 | q->high_mark = 2; | |
268 | ||
269 | q->write_ptr = q->read_ptr = 0; | |
270 | ||
271 | return 0; | |
272 | } | |
273 | ||
274 | /** | |
275 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
276 | */ | |
277 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 278 | struct iwl_tx_queue *txq, u32 id) |
1053d35f RR |
279 | { |
280 | struct pci_dev *dev = priv->pci_dev; | |
3978e5bc | 281 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; |
1053d35f RR |
282 | |
283 | /* Driver private data, only for Tx (not command) queues, | |
284 | * not shared with device. */ | |
285 | if (id != IWL_CMD_QUEUE_NUM) { | |
286 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
287 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
288 | if (!txq->txb) { | |
15b1687c | 289 | IWL_ERR(priv, "kmalloc for auxiliary BD " |
1053d35f RR |
290 | "structures failed\n"); |
291 | goto error; | |
292 | } | |
3978e5bc | 293 | } else { |
1053d35f | 294 | txq->txb = NULL; |
3978e5bc | 295 | } |
1053d35f RR |
296 | |
297 | /* Circular buffer of transmit frame descriptors (TFDs), | |
298 | * shared with device */ | |
3978e5bc | 299 | txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr); |
1053d35f | 300 | |
499b1883 | 301 | if (!txq->tfds) { |
3978e5bc | 302 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); |
1053d35f RR |
303 | goto error; |
304 | } | |
305 | txq->q.id = id; | |
306 | ||
307 | return 0; | |
308 | ||
309 | error: | |
310 | kfree(txq->txb); | |
311 | txq->txb = NULL; | |
312 | ||
313 | return -ENOMEM; | |
314 | } | |
315 | ||
1053d35f RR |
316 | /** |
317 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
318 | */ | |
a8e74e27 SO |
319 | int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
320 | int slots_num, u32 txq_id) | |
1053d35f | 321 | { |
da99c4b6 | 322 | int i, len; |
73b7d742 | 323 | int ret; |
1053d35f RR |
324 | |
325 | /* | |
326 | * Alloc buffer array for commands (Tx or other types of commands). | |
327 | * For the command queue (#4), allocate command space + one big | |
328 | * command for scan, since scan command is very huge; the system will | |
329 | * not have two scans at the same time, so only one is needed. | |
330 | * For normal Tx queues (all other queues), no super-size command | |
331 | * space is needed. | |
332 | */ | |
da99c4b6 GG |
333 | len = sizeof(struct iwl_cmd); |
334 | for (i = 0; i <= slots_num; i++) { | |
335 | if (i == slots_num) { | |
336 | if (txq_id == IWL_CMD_QUEUE_NUM) | |
337 | len += IWL_MAX_SCAN_SIZE; | |
338 | else | |
339 | continue; | |
340 | } | |
341 | ||
49898852 | 342 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); |
da99c4b6 | 343 | if (!txq->cmd[i]) |
73b7d742 | 344 | goto err; |
da99c4b6 | 345 | } |
1053d35f RR |
346 | |
347 | /* Alloc driver data array and TFD circular buffer */ | |
73b7d742 TW |
348 | ret = iwl_tx_queue_alloc(priv, txq, txq_id); |
349 | if (ret) | |
350 | goto err; | |
1053d35f | 351 | |
1053d35f RR |
352 | txq->need_update = 0; |
353 | ||
354 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
355 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
356 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
357 | ||
358 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
359 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
360 | ||
361 | /* Tell device where to find queue */ | |
a8e74e27 | 362 | priv->cfg->ops->lib->txq_init(priv, txq); |
1053d35f RR |
363 | |
364 | return 0; | |
73b7d742 TW |
365 | err: |
366 | for (i = 0; i < slots_num; i++) { | |
367 | kfree(txq->cmd[i]); | |
368 | txq->cmd[i] = NULL; | |
369 | } | |
370 | ||
371 | if (txq_id == IWL_CMD_QUEUE_NUM) { | |
372 | kfree(txq->cmd[slots_num]); | |
373 | txq->cmd[slots_num] = NULL; | |
374 | } | |
375 | return -ENOMEM; | |
1053d35f | 376 | } |
a8e74e27 SO |
377 | EXPORT_SYMBOL(iwl_tx_queue_init); |
378 | ||
da1bc453 TW |
379 | /** |
380 | * iwl_hw_txq_ctx_free - Free TXQ Context | |
381 | * | |
382 | * Destroy all TX DMA queues and structures | |
383 | */ | |
384 | void iwl_hw_txq_ctx_free(struct iwl_priv *priv) | |
385 | { | |
386 | int txq_id; | |
387 | ||
388 | /* Tx queues */ | |
389 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
961ba60a TW |
390 | if (txq_id == IWL_CMD_QUEUE_NUM) |
391 | iwl_cmd_queue_free(priv); | |
392 | else | |
393 | iwl_tx_queue_free(priv, txq_id); | |
da1bc453 | 394 | |
4ddbb7d0 TW |
395 | iwl_free_dma_ptr(priv, &priv->kw); |
396 | ||
397 | iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); | |
da1bc453 TW |
398 | } |
399 | EXPORT_SYMBOL(iwl_hw_txq_ctx_free); | |
400 | ||
1053d35f RR |
401 | /** |
402 | * iwl_txq_ctx_reset - Reset TX queue context | |
a96a27f9 | 403 | * Destroys all DMA structures and initialize them again |
1053d35f RR |
404 | * |
405 | * @param priv | |
406 | * @return error code | |
407 | */ | |
408 | int iwl_txq_ctx_reset(struct iwl_priv *priv) | |
409 | { | |
410 | int ret = 0; | |
411 | int txq_id, slots_num; | |
da1bc453 | 412 | unsigned long flags; |
1053d35f | 413 | |
1053d35f RR |
414 | /* Free all tx/cmd queues and keep-warm buffer */ |
415 | iwl_hw_txq_ctx_free(priv); | |
416 | ||
4ddbb7d0 TW |
417 | ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls, |
418 | priv->hw_params.scd_bc_tbls_size); | |
419 | if (ret) { | |
15b1687c | 420 | IWL_ERR(priv, "Scheduler BC Table allocation failed\n"); |
4ddbb7d0 TW |
421 | goto error_bc_tbls; |
422 | } | |
1053d35f | 423 | /* Alloc keep-warm buffer */ |
4ddbb7d0 | 424 | ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE); |
1053d35f | 425 | if (ret) { |
15b1687c | 426 | IWL_ERR(priv, "Keep Warm allocation failed\n"); |
1053d35f RR |
427 | goto error_kw; |
428 | } | |
da1bc453 TW |
429 | spin_lock_irqsave(&priv->lock, flags); |
430 | ret = iwl_grab_nic_access(priv); | |
431 | if (unlikely(ret)) { | |
432 | spin_unlock_irqrestore(&priv->lock, flags); | |
433 | goto error_reset; | |
434 | } | |
1053d35f RR |
435 | |
436 | /* Turn off all Tx DMA fifos */ | |
da1bc453 TW |
437 | priv->cfg->ops->lib->txq_set_sched(priv, 0); |
438 | ||
4ddbb7d0 TW |
439 | /* Tell NIC where to find the "keep warm" buffer */ |
440 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
441 | ||
da1bc453 TW |
442 | iwl_release_nic_access(priv); |
443 | spin_unlock_irqrestore(&priv->lock, flags); | |
444 | ||
da1bc453 | 445 | /* Alloc and init all Tx queues, including the command queue (#4) */ |
1053d35f RR |
446 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
447 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | |
448 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
449 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | |
450 | txq_id); | |
451 | if (ret) { | |
15b1687c | 452 | IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); |
1053d35f RR |
453 | goto error; |
454 | } | |
455 | } | |
456 | ||
457 | return ret; | |
458 | ||
459 | error: | |
460 | iwl_hw_txq_ctx_free(priv); | |
461 | error_reset: | |
4ddbb7d0 | 462 | iwl_free_dma_ptr(priv, &priv->kw); |
1053d35f | 463 | error_kw: |
4ddbb7d0 TW |
464 | iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); |
465 | error_bc_tbls: | |
1053d35f RR |
466 | return ret; |
467 | } | |
a33c2f47 | 468 | |
da1bc453 TW |
469 | /** |
470 | * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory | |
471 | */ | |
472 | void iwl_txq_ctx_stop(struct iwl_priv *priv) | |
473 | { | |
f3f911d1 | 474 | int ch; |
da1bc453 TW |
475 | unsigned long flags; |
476 | ||
da1bc453 TW |
477 | /* Turn off all Tx DMA fifos */ |
478 | spin_lock_irqsave(&priv->lock, flags); | |
479 | if (iwl_grab_nic_access(priv)) { | |
480 | spin_unlock_irqrestore(&priv->lock, flags); | |
481 | return; | |
482 | } | |
483 | ||
484 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
485 | ||
486 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
f3f911d1 ZY |
487 | for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) { |
488 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
da1bc453 | 489 | iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, |
f3f911d1 | 490 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
f056658b | 491 | 1000); |
da1bc453 TW |
492 | } |
493 | iwl_release_nic_access(priv); | |
494 | spin_unlock_irqrestore(&priv->lock, flags); | |
495 | ||
496 | /* Deallocate memory for all Tx queues */ | |
497 | iwl_hw_txq_ctx_free(priv); | |
498 | } | |
499 | EXPORT_SYMBOL(iwl_txq_ctx_stop); | |
fd4abac5 TW |
500 | |
501 | /* | |
502 | * handle build REPLY_TX command notification. | |
503 | */ | |
504 | static void iwl_tx_cmd_build_basic(struct iwl_priv *priv, | |
505 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 506 | struct ieee80211_tx_info *info, |
fd4abac5 | 507 | struct ieee80211_hdr *hdr, |
0e7690f1 | 508 | u8 std_id) |
fd4abac5 | 509 | { |
fd7c8a40 | 510 | __le16 fc = hdr->frame_control; |
fd4abac5 TW |
511 | __le32 tx_flags = tx_cmd->tx_flags; |
512 | ||
513 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
e039fa4a | 514 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
fd4abac5 | 515 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 516 | if (ieee80211_is_mgmt(fc)) |
fd4abac5 | 517 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 518 | if (ieee80211_is_probe_resp(fc) && |
fd4abac5 TW |
519 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
520 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
521 | } else { | |
522 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
523 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
524 | } | |
525 | ||
fd7c8a40 | 526 | if (ieee80211_is_back_req(fc)) |
fd4abac5 TW |
527 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; |
528 | ||
529 | ||
530 | tx_cmd->sta_id = std_id; | |
8b7b1e05 | 531 | if (ieee80211_has_morefrags(fc)) |
fd4abac5 TW |
532 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
533 | ||
fd7c8a40 HH |
534 | if (ieee80211_is_data_qos(fc)) { |
535 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
fd4abac5 TW |
536 | tx_cmd->tid_tspec = qc[0] & 0xf; |
537 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
538 | } else { | |
539 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
540 | } | |
541 | ||
a326a5d0 | 542 | priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags); |
fd4abac5 TW |
543 | |
544 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
545 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
546 | ||
547 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
548 | if (ieee80211_is_mgmt(fc)) { |
549 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
fd4abac5 TW |
550 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
551 | else | |
552 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
553 | } else { | |
554 | tx_cmd->timeout.pm_frame_timeout = 0; | |
555 | } | |
556 | ||
557 | tx_cmd->driver_txop = 0; | |
558 | tx_cmd->tx_flags = tx_flags; | |
559 | tx_cmd->next_frame_len = 0; | |
560 | } | |
561 | ||
562 | #define RTS_HCCA_RETRY_LIMIT 3 | |
563 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
564 | ||
565 | static void iwl_tx_cmd_build_rate(struct iwl_priv *priv, | |
566 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 567 | struct ieee80211_tx_info *info, |
fd7c8a40 | 568 | __le16 fc, int sta_id, |
fd4abac5 TW |
569 | int is_hcca) |
570 | { | |
76eff18b TW |
571 | u32 rate_flags = 0; |
572 | int rate_idx; | |
fd4abac5 TW |
573 | u8 rts_retry_limit = 0; |
574 | u8 data_retry_limit = 0; | |
575 | u8 rate_plcp; | |
2e92e6f2 | 576 | |
e039fa4a | 577 | rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff, |
2e92e6f2 | 578 | IWL_RATE_COUNT - 1); |
fd4abac5 TW |
579 | |
580 | rate_plcp = iwl_rates[rate_idx].plcp; | |
581 | ||
582 | rts_retry_limit = (is_hcca) ? | |
583 | RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT; | |
584 | ||
585 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) | |
586 | rate_flags |= RATE_MCS_CCK_MSK; | |
587 | ||
588 | ||
fd7c8a40 | 589 | if (ieee80211_is_probe_resp(fc)) { |
fd4abac5 TW |
590 | data_retry_limit = 3; |
591 | if (data_retry_limit < rts_retry_limit) | |
592 | rts_retry_limit = data_retry_limit; | |
593 | } else | |
594 | data_retry_limit = IWL_DEFAULT_TX_RETRY; | |
595 | ||
596 | if (priv->data_retry_limit != -1) | |
597 | data_retry_limit = priv->data_retry_limit; | |
598 | ||
599 | ||
600 | if (ieee80211_is_data(fc)) { | |
601 | tx_cmd->initial_rate_index = 0; | |
602 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
603 | } else { | |
fd7c8a40 HH |
604 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { |
605 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
606 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
607 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
608 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
fd4abac5 TW |
609 | if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) { |
610 | tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
611 | tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK; | |
612 | } | |
613 | break; | |
614 | default: | |
615 | break; | |
616 | } | |
617 | ||
76eff18b TW |
618 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant); |
619 | rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant); | |
fd4abac5 TW |
620 | } |
621 | ||
622 | tx_cmd->rts_retry_limit = rts_retry_limit; | |
623 | tx_cmd->data_retry_limit = data_retry_limit; | |
e7d326ac | 624 | tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags); |
fd4abac5 TW |
625 | } |
626 | ||
627 | static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv, | |
e039fa4a | 628 | struct ieee80211_tx_info *info, |
fd4abac5 TW |
629 | struct iwl_tx_cmd *tx_cmd, |
630 | struct sk_buff *skb_frag, | |
631 | int sta_id) | |
632 | { | |
e039fa4a | 633 | struct ieee80211_key_conf *keyconf = info->control.hw_key; |
fd4abac5 | 634 | |
ccc038ab | 635 | switch (keyconf->alg) { |
fd4abac5 TW |
636 | case ALG_CCMP: |
637 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; | |
ccc038ab | 638 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); |
e039fa4a | 639 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 | 640 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; |
e1623446 | 641 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
fd4abac5 TW |
642 | break; |
643 | ||
644 | case ALG_TKIP: | |
645 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; | |
ccc038ab | 646 | ieee80211_get_tkip_key(keyconf, skb_frag, |
fd4abac5 | 647 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); |
e1623446 | 648 | IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n"); |
fd4abac5 TW |
649 | break; |
650 | ||
651 | case ALG_WEP: | |
fd4abac5 | 652 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
ccc038ab EG |
653 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); |
654 | ||
655 | if (keyconf->keylen == WEP_KEY_LEN_128) | |
656 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
657 | ||
658 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); | |
fd4abac5 | 659 | |
e1623446 | 660 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
ccc038ab | 661 | "with key %d\n", keyconf->keyidx); |
fd4abac5 TW |
662 | break; |
663 | ||
664 | default: | |
978785a3 | 665 | IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg); |
fd4abac5 TW |
666 | break; |
667 | } | |
668 | } | |
669 | ||
670 | static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len) | |
671 | { | |
672 | /* 0 - mgmt, 1 - cnt, 2 - data */ | |
673 | int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2; | |
674 | priv->tx_stats[idx].cnt++; | |
675 | priv->tx_stats[idx].bytes += len; | |
676 | } | |
677 | ||
678 | /* | |
679 | * start REPLY_TX command process | |
680 | */ | |
e039fa4a | 681 | int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
fd4abac5 TW |
682 | { |
683 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 684 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
f3674227 TW |
685 | struct iwl_tx_queue *txq; |
686 | struct iwl_queue *q; | |
687 | struct iwl_cmd *out_cmd; | |
688 | struct iwl_tx_cmd *tx_cmd; | |
689 | int swq_id, txq_id; | |
fd4abac5 TW |
690 | dma_addr_t phys_addr; |
691 | dma_addr_t txcmd_phys; | |
692 | dma_addr_t scratch_phys; | |
b88b15df | 693 | u16 len, len_org; |
fd4abac5 | 694 | u16 seq_number = 0; |
fd7c8a40 | 695 | __le16 fc; |
0e7690f1 | 696 | u8 hdr_len; |
f3674227 | 697 | u8 sta_id; |
fd4abac5 TW |
698 | u8 wait_write_ptr = 0; |
699 | u8 tid = 0; | |
700 | u8 *qc = NULL; | |
701 | unsigned long flags; | |
702 | int ret; | |
703 | ||
704 | spin_lock_irqsave(&priv->lock, flags); | |
705 | if (iwl_is_rfkill(priv)) { | |
e1623446 | 706 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
fd4abac5 TW |
707 | goto drop_unlock; |
708 | } | |
709 | ||
e039fa4a | 710 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == |
2e92e6f2 | 711 | IWL_INVALID_RATE) { |
15b1687c | 712 | IWL_ERR(priv, "ERROR: No TX rate available.\n"); |
fd4abac5 TW |
713 | goto drop_unlock; |
714 | } | |
715 | ||
fd7c8a40 | 716 | fc = hdr->frame_control; |
fd4abac5 TW |
717 | |
718 | #ifdef CONFIG_IWLWIFI_DEBUG | |
719 | if (ieee80211_is_auth(fc)) | |
e1623446 | 720 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 721 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 722 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 723 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 724 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
fd4abac5 TW |
725 | #endif |
726 | ||
727 | /* drop all data frame if we are not associated */ | |
fd7c8a40 | 728 | if (ieee80211_is_data(fc) && |
05c914fe | 729 | (priv->iw_mode != NL80211_IFTYPE_MONITOR || |
d10c4ec8 SG |
730 | !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */ |
731 | (!iwl_is_associated(priv) || | |
05c914fe | 732 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) || |
d10c4ec8 | 733 | !priv->assoc_station_added)) { |
e1623446 | 734 | IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n"); |
fd4abac5 TW |
735 | goto drop_unlock; |
736 | } | |
737 | ||
738 | spin_unlock_irqrestore(&priv->lock, flags); | |
739 | ||
7294ec95 | 740 | hdr_len = ieee80211_hdrlen(fc); |
fd4abac5 TW |
741 | |
742 | /* Find (or create) index into station table for destination station */ | |
743 | sta_id = iwl_get_sta_id(priv, hdr); | |
744 | if (sta_id == IWL_INVALID_STATION) { | |
e1623446 | 745 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 746 | hdr->addr1); |
fd4abac5 TW |
747 | goto drop; |
748 | } | |
749 | ||
e1623446 | 750 | IWL_DEBUG_TX(priv, "station Id %d\n", sta_id); |
fd4abac5 | 751 | |
f3674227 TW |
752 | swq_id = skb_get_queue_mapping(skb); |
753 | txq_id = swq_id; | |
fd7c8a40 HH |
754 | if (ieee80211_is_data_qos(fc)) { |
755 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 756 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
f3674227 TW |
757 | seq_number = priv->stations[sta_id].tid[tid].seq_number; |
758 | seq_number &= IEEE80211_SCTL_SEQ; | |
759 | hdr->seq_ctrl = hdr->seq_ctrl & | |
c1b4aa3f | 760 | cpu_to_le16(IEEE80211_SCTL_FRAG); |
f3674227 | 761 | hdr->seq_ctrl |= cpu_to_le16(seq_number); |
fd4abac5 | 762 | seq_number += 0x10; |
fd4abac5 | 763 | /* aggregation is on for this <sta,tid> */ |
e039fa4a | 764 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 TW |
765 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
766 | priv->stations[sta_id].tid[tid].tfds_in_queue++; | |
fd4abac5 TW |
767 | } |
768 | ||
fd4abac5 TW |
769 | txq = &priv->txq[txq_id]; |
770 | q = &txq->q; | |
3fd07a1e | 771 | txq->swq_id = swq_id; |
fd4abac5 TW |
772 | |
773 | spin_lock_irqsave(&priv->lock, flags); | |
774 | ||
fd4abac5 TW |
775 | /* Set up driver data for this TFD */ |
776 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
777 | txq->txb[q->write_ptr].skb[0] = skb; | |
fd4abac5 TW |
778 | |
779 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
b88b15df | 780 | out_cmd = txq->cmd[q->write_ptr]; |
fd4abac5 TW |
781 | tx_cmd = &out_cmd->cmd.tx; |
782 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
783 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | |
784 | ||
785 | /* | |
786 | * Set up the Tx-command (not MAC!) header. | |
787 | * Store the chosen Tx queue and TFD index within the sequence field; | |
788 | * after Tx, uCode's Tx response will return this value so driver can | |
789 | * locate the frame within the tx queue and do post-tx processing. | |
790 | */ | |
791 | out_cmd->hdr.cmd = REPLY_TX; | |
792 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
793 | INDEX_TO_SEQ(q->write_ptr))); | |
794 | ||
795 | /* Copy MAC header from skb into command buffer */ | |
796 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
797 | ||
798 | /* | |
799 | * Use the first empty entry in this queue's command buffer array | |
800 | * to contain the Tx command and MAC header concatenated together | |
801 | * (payload data will be in another buffer). | |
802 | * Size of this varies, due to varying MAC header length. | |
803 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
804 | * of the MAC header (device reads on dword boundaries). | |
805 | * We'll tell device about this padding later. | |
806 | */ | |
807 | len = sizeof(struct iwl_tx_cmd) + | |
808 | sizeof(struct iwl_cmd_header) + hdr_len; | |
809 | ||
810 | len_org = len; | |
811 | len = (len + 3) & ~3; | |
812 | ||
813 | if (len_org != len) | |
814 | len_org = 1; | |
815 | else | |
816 | len_org = 0; | |
817 | ||
818 | /* Physical address of this Tx command's header (not MAC header!), | |
819 | * within command buffer array. */ | |
499b1883 TW |
820 | txcmd_phys = pci_map_single(priv->pci_dev, |
821 | out_cmd, sizeof(struct iwl_cmd), | |
822 | PCI_DMA_TODEVICE); | |
823 | pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys); | |
824 | pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd)); | |
fd4abac5 TW |
825 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
826 | * first entry */ | |
499b1883 | 827 | txcmd_phys += offsetof(struct iwl_cmd, hdr); |
7aaa1d79 SO |
828 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
829 | txcmd_phys, len, 1, 0); | |
fd4abac5 | 830 | |
d0f09804 | 831 | if (info->control.hw_key) |
e039fa4a | 832 | iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); |
fd4abac5 TW |
833 | |
834 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
835 | * if any (802.11 null frames have no payload). */ | |
836 | len = skb->len - hdr_len; | |
837 | if (len) { | |
838 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
839 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
840 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
841 | phys_addr, len, | |
842 | 0, 0); | |
fd4abac5 TW |
843 | } |
844 | ||
845 | /* Tell NIC about any 2-byte padding after MAC header */ | |
846 | if (len_org) | |
847 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
848 | ||
849 | /* Total # bytes to be transmitted */ | |
850 | len = (u16)skb->len; | |
851 | tx_cmd->len = cpu_to_le16(len); | |
852 | /* TODO need this for burst mode later on */ | |
0e7690f1 | 853 | iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id); |
fd4abac5 TW |
854 | |
855 | /* set is_hcca to 0; it probably will never be implemented */ | |
e039fa4a | 856 | iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0); |
fd4abac5 | 857 | |
fd7c8a40 | 858 | iwl_update_tx_stats(priv, le16_to_cpu(fc), len); |
fd4abac5 TW |
859 | |
860 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
861 | offsetof(struct iwl_tx_cmd, scratch); | |
862 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
499b1883 | 863 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); |
fd4abac5 | 864 | |
8b7b1e05 | 865 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
fd4abac5 TW |
866 | txq->need_update = 1; |
867 | if (qc) | |
868 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
869 | } else { | |
870 | wait_write_ptr = 1; | |
871 | txq->need_update = 0; | |
872 | } | |
873 | ||
874 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); | |
875 | ||
876 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
877 | ||
878 | /* Set up entry for this TFD in Tx byte-count array */ | |
879 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len); | |
880 | ||
881 | /* Tell device the write index *just past* this latest filled TFD */ | |
882 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
883 | ret = iwl_txq_update_write_ptr(priv, txq); | |
884 | spin_unlock_irqrestore(&priv->lock, flags); | |
885 | ||
886 | if (ret) | |
887 | return ret; | |
888 | ||
143b09ef | 889 | if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) { |
fd4abac5 TW |
890 | if (wait_write_ptr) { |
891 | spin_lock_irqsave(&priv->lock, flags); | |
892 | txq->need_update = 1; | |
893 | iwl_txq_update_write_ptr(priv, txq); | |
894 | spin_unlock_irqrestore(&priv->lock, flags); | |
143b09ef | 895 | } else { |
3fd07a1e | 896 | ieee80211_stop_queue(priv->hw, txq->swq_id); |
fd4abac5 | 897 | } |
fd4abac5 TW |
898 | } |
899 | ||
900 | return 0; | |
901 | ||
902 | drop_unlock: | |
903 | spin_unlock_irqrestore(&priv->lock, flags); | |
904 | drop: | |
905 | return -1; | |
906 | } | |
907 | EXPORT_SYMBOL(iwl_tx_skb); | |
908 | ||
909 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
910 | ||
911 | /** | |
912 | * iwl_enqueue_hcmd - enqueue a uCode command | |
913 | * @priv: device private data point | |
914 | * @cmd: a point to the ucode command structure | |
915 | * | |
916 | * The function returns < 0 values to indicate the operation is | |
917 | * failed. On success, it turns the index (> 0) of command in the | |
918 | * command queue. | |
919 | */ | |
920 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
921 | { | |
922 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
923 | struct iwl_queue *q = &txq->q; | |
fd4abac5 | 924 | struct iwl_cmd *out_cmd; |
fd4abac5 | 925 | dma_addr_t phys_addr; |
fd4abac5 | 926 | unsigned long flags; |
f3674227 TW |
927 | int len, ret; |
928 | u32 idx; | |
929 | u16 fix_size; | |
fd4abac5 TW |
930 | |
931 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
932 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
933 | ||
934 | /* If any of the command structures end up being larger than | |
935 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
936 | * we will need to increase the size of the TFD entries */ | |
937 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
938 | !(cmd->meta.flags & CMD_SIZE_HUGE)); | |
939 | ||
940 | if (iwl_is_rfkill(priv)) { | |
e1623446 | 941 | IWL_DEBUG_INFO(priv, "Not sending command - RF KILL"); |
fd4abac5 TW |
942 | return -EIO; |
943 | } | |
944 | ||
945 | if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) { | |
15b1687c | 946 | IWL_ERR(priv, "No space for Tx\n"); |
fd4abac5 TW |
947 | return -ENOSPC; |
948 | } | |
949 | ||
950 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
951 | ||
fd4abac5 | 952 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
da99c4b6 | 953 | out_cmd = txq->cmd[idx]; |
fd4abac5 TW |
954 | |
955 | out_cmd->hdr.cmd = cmd->id; | |
956 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | |
957 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
958 | ||
959 | /* At this point, the out_cmd now has all of the incoming cmd | |
960 | * information */ | |
961 | ||
962 | out_cmd->hdr.flags = 0; | |
963 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
964 | INDEX_TO_SEQ(q->write_ptr)); | |
965 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) | |
9734cb23 | 966 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
da99c4b6 GG |
967 | len = (idx == TFD_CMD_SLOTS) ? |
968 | IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd); | |
499b1883 TW |
969 | |
970 | phys_addr = pci_map_single(priv->pci_dev, out_cmd, | |
971 | len, PCI_DMA_TODEVICE); | |
972 | pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr); | |
973 | pci_unmap_len_set(&out_cmd->meta, len, len); | |
da99c4b6 | 974 | phys_addr += offsetof(struct iwl_cmd, hdr); |
499b1883 | 975 | |
7aaa1d79 | 976 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
518099a8 SO |
977 | phys_addr, fix_size, 1, |
978 | U32_PAD(cmd->len)); | |
fd4abac5 | 979 | |
ded2ae7c EK |
980 | #ifdef CONFIG_IWLWIFI_DEBUG |
981 | switch (out_cmd->hdr.cmd) { | |
982 | case REPLY_TX_LINK_QUALITY_CMD: | |
983 | case SENSITIVITY_CMD: | |
e1623446 | 984 | IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
985 | "%d bytes at %d[%d]:%d\n", |
986 | get_cmd_string(out_cmd->hdr.cmd), | |
987 | out_cmd->hdr.cmd, | |
988 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
989 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
990 | break; | |
991 | default: | |
e1623446 | 992 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
993 | "%d bytes at %d[%d]:%d\n", |
994 | get_cmd_string(out_cmd->hdr.cmd), | |
995 | out_cmd->hdr.cmd, | |
996 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
997 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
998 | } | |
999 | #endif | |
fd4abac5 TW |
1000 | txq->need_update = 1; |
1001 | ||
518099a8 SO |
1002 | if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl) |
1003 | /* Set up entry in queue's byte count circular buffer */ | |
1004 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); | |
fd4abac5 TW |
1005 | |
1006 | /* Increment and update queue's write index */ | |
1007 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1008 | ret = iwl_txq_update_write_ptr(priv, txq); | |
1009 | ||
1010 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
1011 | return ret ? ret : idx; | |
1012 | } | |
1013 | ||
17b88929 TW |
1014 | int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) |
1015 | { | |
1016 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1017 | struct iwl_queue *q = &txq->q; | |
1018 | struct iwl_tx_info *tx_info; | |
1019 | int nfreed = 0; | |
1020 | ||
1021 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
15b1687c | 1022 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 TW |
1023 | "is out of range [0-%d] %d %d.\n", txq_id, |
1024 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1025 | return 0; | |
1026 | } | |
1027 | ||
499b1883 TW |
1028 | for (index = iwl_queue_inc_wrap(index, q->n_bd); |
1029 | q->read_ptr != index; | |
1030 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 TW |
1031 | |
1032 | tx_info = &txq->txb[txq->q.read_ptr]; | |
1033 | ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]); | |
1034 | tx_info->skb[0] = NULL; | |
17b88929 | 1035 | |
972cf447 TW |
1036 | if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl) |
1037 | priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq); | |
1038 | ||
7aaa1d79 | 1039 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
17b88929 TW |
1040 | nfreed++; |
1041 | } | |
1042 | return nfreed; | |
1043 | } | |
1044 | EXPORT_SYMBOL(iwl_tx_queue_reclaim); | |
1045 | ||
1046 | ||
1047 | /** | |
1048 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
1049 | * | |
1050 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1051 | * need to be reclaimed. As result, some free space forms. If there is | |
1052 | * enough free space (> low mark), wake the stack that feeds us. | |
1053 | */ | |
499b1883 TW |
1054 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, |
1055 | int idx, int cmd_idx) | |
17b88929 TW |
1056 | { |
1057 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1058 | struct iwl_queue *q = &txq->q; | |
1059 | int nfreed = 0; | |
1060 | ||
499b1883 | 1061 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
15b1687c | 1062 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 | 1063 | "is out of range [0-%d] %d %d.\n", txq_id, |
499b1883 | 1064 | idx, q->n_bd, q->write_ptr, q->read_ptr); |
17b88929 TW |
1065 | return; |
1066 | } | |
1067 | ||
499b1883 TW |
1068 | pci_unmap_single(priv->pci_dev, |
1069 | pci_unmap_addr(&txq->cmd[cmd_idx]->meta, mapping), | |
1070 | pci_unmap_len(&txq->cmd[cmd_idx]->meta, len), | |
1071 | PCI_DMA_TODEVICE); | |
1072 | ||
1073 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; | |
1074 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 1075 | |
499b1883 | 1076 | if (nfreed++ > 0) { |
15b1687c | 1077 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 TW |
1078 | q->write_ptr, q->read_ptr); |
1079 | queue_work(priv->workqueue, &priv->restart); | |
1080 | } | |
da99c4b6 | 1081 | |
17b88929 TW |
1082 | } |
1083 | } | |
1084 | ||
1085 | /** | |
1086 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
1087 | * @rxb: Rx buffer to reclaim | |
1088 | * | |
1089 | * If an Rx buffer has an async callback associated with it the callback | |
1090 | * will be executed. The attached skb (if present) will only be freed | |
1091 | * if the callback returns 1 | |
1092 | */ | |
1093 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
1094 | { | |
1095 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1096 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
1097 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1098 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1099 | int cmd_index; |
9734cb23 | 1100 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
17b88929 TW |
1101 | struct iwl_cmd *cmd; |
1102 | ||
1103 | /* If a Tx command is being handled and it isn't in the actual | |
1104 | * command queue then there a command routing bug has been introduced | |
1105 | * in the queue management code. */ | |
55d6a3cd | 1106 | if (WARN(txq_id != IWL_CMD_QUEUE_NUM, |
01ef9323 WT |
1107 | "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n", |
1108 | txq_id, sequence, | |
1109 | priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr, | |
1110 | priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) { | |
1111 | iwl_print_hex_dump(priv, IWL_DL_INFO , rxb, 32); | |
55d6a3cd | 1112 | return; |
01ef9323 | 1113 | } |
17b88929 TW |
1114 | |
1115 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | |
da99c4b6 | 1116 | cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; |
17b88929 TW |
1117 | |
1118 | /* Input error checking is done when commands are added to queue. */ | |
1119 | if (cmd->meta.flags & CMD_WANT_SKB) { | |
1120 | cmd->meta.source->u.skb = rxb->skb; | |
1121 | rxb->skb = NULL; | |
1122 | } else if (cmd->meta.u.callback && | |
1123 | !cmd->meta.u.callback(priv, cmd, rxb->skb)) | |
1124 | rxb->skb = NULL; | |
1125 | ||
499b1883 | 1126 | iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index); |
17b88929 TW |
1127 | |
1128 | if (!(cmd->meta.flags & CMD_ASYNC)) { | |
1129 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
1130 | wake_up_interruptible(&priv->wait_command_queue); | |
1131 | } | |
1132 | } | |
1133 | EXPORT_SYMBOL(iwl_tx_cmd_complete); | |
1134 | ||
30e553e3 TW |
1135 | /* |
1136 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
1137 | * Called only when finding queue for aggregation. | |
1138 | * Should never return anything < 7, because they should already | |
1139 | * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6). | |
1140 | */ | |
1141 | static int iwl_txq_ctx_activate_free(struct iwl_priv *priv) | |
1142 | { | |
1143 | int txq_id; | |
1144 | ||
1145 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
1146 | if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk)) | |
1147 | return txq_id; | |
1148 | return -1; | |
1149 | } | |
1150 | ||
1151 | int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn) | |
1152 | { | |
1153 | int sta_id; | |
1154 | int tx_fifo; | |
1155 | int txq_id; | |
1156 | int ret; | |
1157 | unsigned long flags; | |
1158 | struct iwl_tid_data *tid_data; | |
30e553e3 TW |
1159 | |
1160 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
1161 | tx_fifo = default_tid_to_tx_fifo[tid]; | |
1162 | else | |
1163 | return -EINVAL; | |
1164 | ||
39aadf8c | 1165 | IWL_WARN(priv, "%s on ra = %pM tid = %d\n", |
e174961c | 1166 | __func__, ra, tid); |
30e553e3 TW |
1167 | |
1168 | sta_id = iwl_find_station(priv, ra); | |
1169 | if (sta_id == IWL_INVALID_STATION) | |
1170 | return -ENXIO; | |
1171 | ||
1172 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { | |
15b1687c | 1173 | IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n"); |
30e553e3 TW |
1174 | return -ENXIO; |
1175 | } | |
1176 | ||
1177 | txq_id = iwl_txq_ctx_activate_free(priv); | |
1178 | if (txq_id == -1) | |
1179 | return -ENXIO; | |
1180 | ||
1181 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1182 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1183 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
1184 | tid_data->agg.txq_id = txq_id; | |
1185 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
1186 | ||
1187 | ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo, | |
1188 | sta_id, tid, *ssn); | |
1189 | if (ret) | |
1190 | return ret; | |
1191 | ||
1192 | if (tid_data->tfds_in_queue == 0) { | |
978785a3 | 1193 | IWL_ERR(priv, "HW queue is empty\n"); |
30e553e3 TW |
1194 | tid_data->agg.state = IWL_AGG_ON; |
1195 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid); | |
1196 | } else { | |
e1623446 | 1197 | IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n", |
30e553e3 TW |
1198 | tid_data->tfds_in_queue); |
1199 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
1200 | } | |
1201 | return ret; | |
1202 | } | |
1203 | EXPORT_SYMBOL(iwl_tx_agg_start); | |
1204 | ||
1205 | int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid) | |
1206 | { | |
1207 | int tx_fifo_id, txq_id, sta_id, ssn = -1; | |
1208 | struct iwl_tid_data *tid_data; | |
1209 | int ret, write_ptr, read_ptr; | |
1210 | unsigned long flags; | |
30e553e3 TW |
1211 | |
1212 | if (!ra) { | |
15b1687c | 1213 | IWL_ERR(priv, "ra = NULL\n"); |
30e553e3 TW |
1214 | return -EINVAL; |
1215 | } | |
1216 | ||
1217 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
1218 | tx_fifo_id = default_tid_to_tx_fifo[tid]; | |
1219 | else | |
1220 | return -EINVAL; | |
1221 | ||
1222 | sta_id = iwl_find_station(priv, ra); | |
1223 | ||
1224 | if (sta_id == IWL_INVALID_STATION) | |
1225 | return -ENXIO; | |
1226 | ||
1227 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON) | |
39aadf8c | 1228 | IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n"); |
30e553e3 TW |
1229 | |
1230 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1231 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
1232 | txq_id = tid_data->agg.txq_id; | |
1233 | write_ptr = priv->txq[txq_id].q.write_ptr; | |
1234 | read_ptr = priv->txq[txq_id].q.read_ptr; | |
1235 | ||
1236 | /* The queue is not empty */ | |
1237 | if (write_ptr != read_ptr) { | |
e1623446 | 1238 | IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n"); |
30e553e3 TW |
1239 | priv->stations[sta_id].tid[tid].agg.state = |
1240 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
1241 | return 0; | |
1242 | } | |
1243 | ||
e1623446 | 1244 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); |
30e553e3 TW |
1245 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; |
1246 | ||
1247 | spin_lock_irqsave(&priv->lock, flags); | |
1248 | ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn, | |
1249 | tx_fifo_id); | |
1250 | spin_unlock_irqrestore(&priv->lock, flags); | |
1251 | ||
1252 | if (ret) | |
1253 | return ret; | |
1254 | ||
1255 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid); | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | EXPORT_SYMBOL(iwl_tx_agg_stop); | |
1260 | ||
1261 | int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id) | |
1262 | { | |
1263 | struct iwl_queue *q = &priv->txq[txq_id].q; | |
1264 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | |
1265 | struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid]; | |
1266 | ||
1267 | switch (priv->stations[sta_id].tid[tid].agg.state) { | |
1268 | case IWL_EMPTYING_HW_QUEUE_DELBA: | |
1269 | /* We are reclaiming the last packet of the */ | |
1270 | /* aggregated HW queue */ | |
3fd07a1e TW |
1271 | if ((txq_id == tid_data->agg.txq_id) && |
1272 | (q->read_ptr == q->write_ptr)) { | |
30e553e3 TW |
1273 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); |
1274 | int tx_fifo = default_tid_to_tx_fifo[tid]; | |
e1623446 | 1275 | IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n"); |
30e553e3 TW |
1276 | priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, |
1277 | ssn, tx_fifo); | |
1278 | tid_data->agg.state = IWL_AGG_OFF; | |
1279 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
1280 | } | |
1281 | break; | |
1282 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1283 | /* We are reclaiming the last packet of the queue */ | |
1284 | if (tid_data->tfds_in_queue == 0) { | |
e1623446 | 1285 | IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n"); |
30e553e3 TW |
1286 | tid_data->agg.state = IWL_AGG_ON; |
1287 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
1288 | } | |
1289 | break; | |
1290 | } | |
1291 | return 0; | |
1292 | } | |
1293 | EXPORT_SYMBOL(iwl_txq_check_empty); | |
30e553e3 | 1294 | |
653fa4a0 EG |
1295 | /** |
1296 | * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack | |
1297 | * | |
1298 | * Go through block-ack's bitmap of ACK'd frames, update driver's record of | |
1299 | * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. | |
1300 | */ | |
1301 | static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv, | |
1302 | struct iwl_ht_agg *agg, | |
1303 | struct iwl_compressed_ba_resp *ba_resp) | |
1304 | ||
1305 | { | |
1306 | int i, sh, ack; | |
1307 | u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); | |
1308 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1309 | u64 bitmap; | |
1310 | int successes = 0; | |
1311 | struct ieee80211_tx_info *info; | |
1312 | ||
1313 | if (unlikely(!agg->wait_for_ba)) { | |
15b1687c | 1314 | IWL_ERR(priv, "Received BA when not expected\n"); |
653fa4a0 EG |
1315 | return -EINVAL; |
1316 | } | |
1317 | ||
1318 | /* Mark that the expected block-ack response arrived */ | |
1319 | agg->wait_for_ba = 0; | |
e1623446 | 1320 | IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); |
653fa4a0 EG |
1321 | |
1322 | /* Calculate shift to align block-ack bits with our Tx window bits */ | |
3fd07a1e | 1323 | sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4); |
653fa4a0 EG |
1324 | if (sh < 0) /* tbw something is wrong with indices */ |
1325 | sh += 0x100; | |
1326 | ||
1327 | /* don't use 64-bit values for now */ | |
1328 | bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; | |
1329 | ||
1330 | if (agg->frame_count > (64 - sh)) { | |
e1623446 | 1331 | IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size"); |
653fa4a0 EG |
1332 | return -1; |
1333 | } | |
1334 | ||
1335 | /* check for success or failure according to the | |
1336 | * transmitted bitmap and block-ack bitmap */ | |
1337 | bitmap &= agg->bitmap; | |
1338 | ||
1339 | /* For each frame attempted in aggregation, | |
1340 | * update driver's record of tx frame's status. */ | |
1341 | for (i = 0; i < agg->frame_count ; i++) { | |
4aa41f12 | 1342 | ack = bitmap & (1ULL << i); |
653fa4a0 | 1343 | successes += !!ack; |
e1623446 | 1344 | IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n", |
c3056065 | 1345 | ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff, |
653fa4a0 EG |
1346 | agg->start_idx + i); |
1347 | } | |
1348 | ||
1349 | info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]); | |
1350 | memset(&info->status, 0, sizeof(info->status)); | |
1351 | info->flags = IEEE80211_TX_STAT_ACK; | |
1352 | info->flags |= IEEE80211_TX_STAT_AMPDU; | |
1353 | info->status.ampdu_ack_map = successes; | |
1354 | info->status.ampdu_ack_len = agg->frame_count; | |
1355 | iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info); | |
1356 | ||
e1623446 | 1357 | IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap); |
653fa4a0 EG |
1358 | |
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | /** | |
1363 | * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA | |
1364 | * | |
1365 | * Handles block-acknowledge notification from device, which reports success | |
1366 | * of frames sent via aggregation. | |
1367 | */ | |
1368 | void iwl_rx_reply_compressed_ba(struct iwl_priv *priv, | |
1369 | struct iwl_rx_mem_buffer *rxb) | |
1370 | { | |
1371 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1372 | struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; | |
653fa4a0 EG |
1373 | struct iwl_tx_queue *txq = NULL; |
1374 | struct iwl_ht_agg *agg; | |
3fd07a1e TW |
1375 | int index; |
1376 | int sta_id; | |
1377 | int tid; | |
653fa4a0 EG |
1378 | |
1379 | /* "flow" corresponds to Tx queue */ | |
1380 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1381 | ||
1382 | /* "ssn" is start of block-ack Tx window, corresponds to index | |
1383 | * (in Tx queue's circular buffer) of first TFD/frame in window */ | |
1384 | u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); | |
1385 | ||
1386 | if (scd_flow >= priv->hw_params.max_txq_num) { | |
15b1687c WT |
1387 | IWL_ERR(priv, |
1388 | "BUG_ON scd_flow is bigger than number of queues\n"); | |
653fa4a0 EG |
1389 | return; |
1390 | } | |
1391 | ||
1392 | txq = &priv->txq[scd_flow]; | |
3fd07a1e TW |
1393 | sta_id = ba_resp->sta_id; |
1394 | tid = ba_resp->tid; | |
1395 | agg = &priv->stations[sta_id].tid[tid].agg; | |
653fa4a0 EG |
1396 | |
1397 | /* Find index just before block-ack window */ | |
1398 | index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); | |
1399 | ||
1400 | /* TODO: Need to get this copy more safely - now good for debug */ | |
1401 | ||
e1623446 | 1402 | IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, " |
653fa4a0 EG |
1403 | "sta_id = %d\n", |
1404 | agg->wait_for_ba, | |
e174961c | 1405 | (u8 *) &ba_resp->sta_addr_lo32, |
653fa4a0 | 1406 | ba_resp->sta_id); |
e1623446 | 1407 | IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = " |
653fa4a0 EG |
1408 | "%d, scd_ssn = %d\n", |
1409 | ba_resp->tid, | |
1410 | ba_resp->seq_ctl, | |
1411 | (unsigned long long)le64_to_cpu(ba_resp->bitmap), | |
1412 | ba_resp->scd_flow, | |
1413 | ba_resp->scd_ssn); | |
e1623446 | 1414 | IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n", |
653fa4a0 EG |
1415 | agg->start_idx, |
1416 | (unsigned long long)agg->bitmap); | |
1417 | ||
1418 | /* Update driver's record of ACK vs. not for each frame in window */ | |
1419 | iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp); | |
1420 | ||
1421 | /* Release all TFDs before the SSN, i.e. all TFDs in front of | |
1422 | * block-ack window (we assume that they've been successfully | |
1423 | * transmitted ... if not, it's too late anyway). */ | |
1424 | if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { | |
1425 | /* calculate mac80211 ampdu sw queue to wake */ | |
653fa4a0 | 1426 | int freed = iwl_tx_queue_reclaim(priv, scd_flow, index); |
3fd07a1e TW |
1427 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
1428 | ||
1429 | if ((iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1430 | priv->mac80211_registered && | |
1431 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) | |
1432 | ieee80211_wake_queue(priv->hw, txq->swq_id); | |
1433 | ||
1434 | iwl_txq_check_empty(priv, sta_id, tid, scd_flow); | |
653fa4a0 EG |
1435 | } |
1436 | } | |
1437 | EXPORT_SYMBOL(iwl_rx_reply_compressed_ba); | |
1438 | ||
994d31f7 | 1439 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 TW |
1440 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x |
1441 | ||
1442 | const char *iwl_get_tx_fail_reason(u32 status) | |
1443 | { | |
1444 | switch (status & TX_STATUS_MSK) { | |
1445 | case TX_STATUS_SUCCESS: | |
1446 | return "SUCCESS"; | |
1447 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
1448 | TX_STATUS_ENTRY(LONG_LIMIT); | |
1449 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
1450 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
1451 | TX_STATUS_ENTRY(NEXT_FRAG); | |
1452 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
1453 | TX_STATUS_ENTRY(DEST_PS); | |
1454 | TX_STATUS_ENTRY(ABORTED); | |
1455 | TX_STATUS_ENTRY(BT_RETRY); | |
1456 | TX_STATUS_ENTRY(STA_INVALID); | |
1457 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
1458 | TX_STATUS_ENTRY(TID_DISABLE); | |
1459 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
1460 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
1461 | TX_STATUS_ENTRY(TX_LOCKED); | |
1462 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
1463 | } | |
1464 | ||
1465 | return "UNKNOWN"; | |
1466 | } | |
1467 | EXPORT_SYMBOL(iwl_get_tx_fail_reason); | |
1468 | #endif /* CONFIG_IWLWIFI_DEBUG */ |