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iwlwifi: make iwl_tx_queue->tfds void*
[linux-2.6-block.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
CommitLineData
1053d35f
RR		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
1053d35f
RR		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
1053d35f
RR		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
fd4abac5 30#include <linux/etherdevice.h>
1053d35f
RR		 31#include <net/mac80211.h>
32#include "iwl-eeprom.h"
33#include "iwl-dev.h"
34#include "iwl-core.h"
35#include "iwl-sta.h"
36#include "iwl-io.h"
37#include "iwl-helpers.h"
38
30e553e3
TW		 39static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
57};
58
4ddbb7d0
TW		 59static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
60 struct iwl_dma_ptr *ptr, size_t size)
61{
62 ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
63 if (!ptr->addr)
64 return -ENOMEM;
65 ptr->size = size;
66 return 0;
67}
68
69static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
70 struct iwl_dma_ptr *ptr)
71{
72 if (unlikely(!ptr->addr))
73 return;
74
75 pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
76 memset(ptr, 0, sizeof(*ptr));
77}
78
fd4abac5
TW		 79/**
80 * iwl_txq_update_write_ptr - Send new write index to hardware
81 */
82int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
83{
84 u32 reg = 0;
85 int ret = 0;
86 int txq_id = txq->q.id;
87
88 if (txq->need_update == 0)
89 return ret;
90
91 /* if we're trying to save power */
92 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
93 /* wake up nic if it's powered down ...
94 * uCode will wake up, and interrupt us again, so next
95 * time we'll skip this part. */
96 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
97
98 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
99 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
100 iwl_set_bit(priv, CSR_GP_CNTRL,
101 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
102 return ret;
103 }
104
105 /* restore this queue's parameters in nic hardware. */
106 ret = iwl_grab_nic_access(priv);
107 if (ret)
108 return ret;
109 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
110 txq->q.write_ptr | (txq_id << 8));
111 iwl_release_nic_access(priv);
112
113 /* else not in power-save mode, uCode will never sleep when we're
114 * trying to tx (during RFKILL, we're not trying to tx). */
115 } else
116 iwl_write32(priv, HBUS_TARG_WRPTR,
117 txq->q.write_ptr | (txq_id << 8));
118
119 txq->need_update = 0;
120
121 return ret;
122}
123EXPORT_SYMBOL(iwl_txq_update_write_ptr);
124
125
1053d35f
RR		 126/**
127 * iwl_tx_queue_free - Deallocate DMA queue.
128 * @txq: Transmit queue to deallocate.
129 *
130 * Empty queue by removing and destroying all BD's.
131 * Free all buffers.
132 * 0-fill, but do not free "txq" descriptor structure.
133 */
da99c4b6 134static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
1053d35f 135{
da99c4b6 136 struct iwl_tx_queue *txq = &priv->txq[txq_id];
443cfd45 137 struct iwl_queue *q = &txq->q;
1053d35f 138 struct pci_dev *dev = priv->pci_dev;
961ba60a 139 int i, len;
1053d35f
RR		 140
141 if (q->n_bd == 0)
142 return;
143
144 /* first, empty all BD's */
145 for (; q->write_ptr != q->read_ptr;
146 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
7aaa1d79 147 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1053d35f
RR		 148
149 len = sizeof(struct iwl_cmd) * q->n_window;
1053d35f
RR		 150
151 /* De-alloc array of command/tx buffers */
961ba60a 152 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
da99c4b6 153 kfree(txq->cmd[i]);
1053d35f
RR		 154
155 /* De-alloc circular buffer of TFDs */
156 if (txq->q.n_bd)
499b1883
TW		 157 pci_free_consistent(dev, sizeof(struct iwl_tfd) *
158 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
1053d35f
RR		 159
160 /* De-alloc array of per-TFD driver data */
161 kfree(txq->txb);
162 txq->txb = NULL;
163
164 /* 0-fill queue descriptor structure */
165 memset(txq, 0, sizeof(*txq));
166}
167
961ba60a
TW		 168
169/**
170 * iwl_cmd_queue_free - Deallocate DMA queue.
171 * @txq: Transmit queue to deallocate.
172 *
173 * Empty queue by removing and destroying all BD's.
174 * Free all buffers.
175 * 0-fill, but do not free "txq" descriptor structure.
176 */
177static void iwl_cmd_queue_free(struct iwl_priv *priv)
178{
179 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
180 struct iwl_queue *q = &txq->q;
181 struct pci_dev *dev = priv->pci_dev;
182 int i, len;
183
184 if (q->n_bd == 0)
185 return;
186
187 len = sizeof(struct iwl_cmd) * q->n_window;
188 len += IWL_MAX_SCAN_SIZE;
189
190 /* De-alloc array of command/tx buffers */
191 for (i = 0; i <= TFD_CMD_SLOTS; i++)
192 kfree(txq->cmd[i]);
193
194 /* De-alloc circular buffer of TFDs */
195 if (txq->q.n_bd)
499b1883
TW		 196 pci_free_consistent(dev, sizeof(struct iwl_tfd) *
197 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
961ba60a
TW		 198
199 /* 0-fill queue descriptor structure */
200 memset(txq, 0, sizeof(*txq));
201}
fd4abac5
TW		 202/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
203 * DMA services
204 *
205 * Theory of operation
206 *
207 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
208 * of buffer descriptors, each of which points to one or more data buffers for
209 * the device to read from or fill. Driver and device exchange status of each
210 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
211 * entries in each circular buffer, to protect against confusing empty and full
212 * queue states.
213 *
214 * The device reads or writes the data in the queues via the device's several
215 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
216 *
217 * For Tx queue, there are low mark and high mark limits. If, after queuing
218 * the packet for Tx, free space become < low mark, Tx queue stopped. When
219 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
220 * Tx queue resumed.
221 *
222 * See more detailed info in iwl-4965-hw.h.
223 ***************************************************/
224
225int iwl_queue_space(const struct iwl_queue *q)
226{
227 int s = q->read_ptr - q->write_ptr;
228
229 if (q->read_ptr > q->write_ptr)
230 s -= q->n_bd;
231
232 if (s <= 0)
233 s += q->n_window;
234 /* keep some reserve to not confuse empty and full situations */
235 s -= 2;
236 if (s < 0)
237 s = 0;
238 return s;
239}
240EXPORT_SYMBOL(iwl_queue_space);
241
242
1053d35f
RR		 243/**
244 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
245 */
443cfd45 246static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
1053d35f
RR		 247 int count, int slots_num, u32 id)
248{
249 q->n_bd = count;
250 q->n_window = slots_num;
251 q->id = id;
252
253 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
254 * and iwl_queue_dec_wrap are broken. */
255 BUG_ON(!is_power_of_2(count));
256
257 /* slots_num must be power-of-two size, otherwise
258 * get_cmd_index is broken. */
259 BUG_ON(!is_power_of_2(slots_num));
260
261 q->low_mark = q->n_window / 4;
262 if (q->low_mark < 4)
263 q->low_mark = 4;
264
265 q->high_mark = q->n_window / 8;
266 if (q->high_mark < 2)
267 q->high_mark = 2;
268
269 q->write_ptr = q->read_ptr = 0;
270
271 return 0;
272}
273
274/**
275 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
276 */
277static int iwl_tx_queue_alloc(struct iwl_priv *priv,
16466903 278 struct iwl_tx_queue *txq, u32 id)
1053d35f
RR		 279{
280 struct pci_dev *dev = priv->pci_dev;
281
282 /* Driver private data, only for Tx (not command) queues,
283 * not shared with device. */
284 if (id != IWL_CMD_QUEUE_NUM) {
285 txq->txb = kmalloc(sizeof(txq->txb[0]) *
286 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
287 if (!txq->txb) {
15b1687c 288 IWL_ERR(priv, "kmalloc for auxiliary BD "
1053d35f
RR		 289 "structures failed\n");
290 goto error;
291 }
292 } else
293 txq->txb = NULL;
294
295 /* Circular buffer of transmit frame descriptors (TFDs),
296 * shared with device */
499b1883 297 txq->tfds = pci_alloc_consistent(dev,
59606ffa 298 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
1053d35f
RR		 299 &txq->q.dma_addr);
300
499b1883 301 if (!txq->tfds) {
15b1687c 302 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
59606ffa 303 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX);
1053d35f
RR		 304 goto error;
305 }
306 txq->q.id = id;
307
308 return 0;
309
310 error:
311 kfree(txq->txb);
312 txq->txb = NULL;
313
314 return -ENOMEM;
315}
316
317/*
318 * Tell nic where to find circular buffer of Tx Frame Descriptors for
319 * given Tx queue, and enable the DMA channel used for that queue.
320 *
321 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
322 * channels supported in hardware.
323 */
324static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
16466903 325 struct iwl_tx_queue *txq)
1053d35f 326{
499b1883 327 int ret;
1053d35f
RR		 328 unsigned long flags;
329 int txq_id = txq->q.id;
330
331 spin_lock_irqsave(&priv->lock, flags);
499b1883
TW		 332 ret = iwl_grab_nic_access(priv);
333 if (ret) {
1053d35f 334 spin_unlock_irqrestore(&priv->lock, flags);
499b1883 335 return ret;
1053d35f
RR		 336 }
337
338 /* Circular buffer (TFD queue in DRAM) physical base address */
339 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
340 txq->q.dma_addr >> 8);
341
1053d35f
RR		 342 iwl_release_nic_access(priv);
343 spin_unlock_irqrestore(&priv->lock, flags);
344
345 return 0;
346}
347
348/**
349 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
350 */
73b7d742 351static int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
1053d35f
RR		 352 int slots_num, u32 txq_id)
353{
da99c4b6 354 int i, len;
73b7d742 355 int ret;
1053d35f
RR		 356
357 /*
358 * Alloc buffer array for commands (Tx or other types of commands).
359 * For the command queue (#4), allocate command space + one big
360 * command for scan, since scan command is very huge; the system will
361 * not have two scans at the same time, so only one is needed.
362 * For normal Tx queues (all other queues), no super-size command
363 * space is needed.
364 */
da99c4b6
GG		 365 len = sizeof(struct iwl_cmd);
366 for (i = 0; i <= slots_num; i++) {
367 if (i == slots_num) {
368 if (txq_id == IWL_CMD_QUEUE_NUM)
369 len += IWL_MAX_SCAN_SIZE;
370 else
371 continue;
372 }
373
49898852 374 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
da99c4b6 375 if (!txq->cmd[i])
73b7d742 376 goto err;
da99c4b6 377 }
1053d35f
RR		 378
379 /* Alloc driver data array and TFD circular buffer */
73b7d742
TW		 380 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
381 if (ret)
382 goto err;
1053d35f 383
1053d35f
RR		 384 txq->need_update = 0;
385
386 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
387 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
388 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
389
390 /* Initialize queue's high/low-water marks, and head/tail indexes */
391 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
392
393 /* Tell device where to find queue */
394 iwl_hw_tx_queue_init(priv, txq);
395
396 return 0;
73b7d742
TW		 397err:
398 for (i = 0; i < slots_num; i++) {
399 kfree(txq->cmd[i]);
400 txq->cmd[i] = NULL;
401 }
402
403 if (txq_id == IWL_CMD_QUEUE_NUM) {
404 kfree(txq->cmd[slots_num]);
405 txq->cmd[slots_num] = NULL;
406 }
407 return -ENOMEM;
1053d35f 408}
da1bc453
TW		 409/**
410 * iwl_hw_txq_ctx_free - Free TXQ Context
411 *
412 * Destroy all TX DMA queues and structures
413 */
414void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
415{
416 int txq_id;
417
418 /* Tx queues */
419 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
961ba60a
TW		 420 if (txq_id == IWL_CMD_QUEUE_NUM)
421 iwl_cmd_queue_free(priv);
422 else
423 iwl_tx_queue_free(priv, txq_id);
da1bc453 424
4ddbb7d0
TW		 425 iwl_free_dma_ptr(priv, &priv->kw);
426
427 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
da1bc453
TW		 428}
429EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
430
1053d35f
RR		 431/**
432 * iwl_txq_ctx_reset - Reset TX queue context
a96a27f9 433 * Destroys all DMA structures and initialize them again
1053d35f
RR		 434 *
435 * @param priv
436 * @return error code
437 */
438int iwl_txq_ctx_reset(struct iwl_priv *priv)
439{
440 int ret = 0;
441 int txq_id, slots_num;
da1bc453 442 unsigned long flags;
1053d35f 443
1053d35f
RR		 444 /* Free all tx/cmd queues and keep-warm buffer */
445 iwl_hw_txq_ctx_free(priv);
446
4ddbb7d0
TW		 447 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
448 priv->hw_params.scd_bc_tbls_size);
449 if (ret) {
15b1687c 450 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
4ddbb7d0
TW		 451 goto error_bc_tbls;
452 }
1053d35f 453 /* Alloc keep-warm buffer */
4ddbb7d0 454 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
1053d35f 455 if (ret) {
15b1687c 456 IWL_ERR(priv, "Keep Warm allocation failed\n");
1053d35f
RR		 457 goto error_kw;
458 }
da1bc453
TW		 459 spin_lock_irqsave(&priv->lock, flags);
460 ret = iwl_grab_nic_access(priv);
461 if (unlikely(ret)) {
462 spin_unlock_irqrestore(&priv->lock, flags);
463 goto error_reset;
464 }
1053d35f
RR		 465
466 /* Turn off all Tx DMA fifos */
da1bc453
TW		 467 priv->cfg->ops->lib->txq_set_sched(priv, 0);
468
4ddbb7d0
TW		 469 /* Tell NIC where to find the "keep warm" buffer */
470 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
471
da1bc453
TW		 472 iwl_release_nic_access(priv);
473 spin_unlock_irqrestore(&priv->lock, flags);
474
da1bc453 475 /* Alloc and init all Tx queues, including the command queue (#4) */
1053d35f
RR		 476 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
477 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
478 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
479 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
480 txq_id);
481 if (ret) {
15b1687c 482 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1053d35f
RR		 483 goto error;
484 }
485 }
486
487 return ret;
488
489 error:
490 iwl_hw_txq_ctx_free(priv);
491 error_reset:
4ddbb7d0 492 iwl_free_dma_ptr(priv, &priv->kw);
1053d35f 493 error_kw:
4ddbb7d0
TW		 494 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
495 error_bc_tbls:
1053d35f
RR		 496 return ret;
497}
a33c2f47 498
da1bc453
TW		 499/**
500 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
501 */
502void iwl_txq_ctx_stop(struct iwl_priv *priv)
503{
f3f911d1 504 int ch;
da1bc453
TW		 505 unsigned long flags;
506
da1bc453
TW		 507 /* Turn off all Tx DMA fifos */
508 spin_lock_irqsave(&priv->lock, flags);
509 if (iwl_grab_nic_access(priv)) {
510 spin_unlock_irqrestore(&priv->lock, flags);
511 return;
512 }
513
514 priv->cfg->ops->lib->txq_set_sched(priv, 0);
515
516 /* Stop each Tx DMA channel, and wait for it to be idle */
f3f911d1
ZY		 517 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
518 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
da1bc453 519 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
f3f911d1 520 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
f056658b 521 1000);
da1bc453
TW		 522 }
523 iwl_release_nic_access(priv);
524 spin_unlock_irqrestore(&priv->lock, flags);
525
526 /* Deallocate memory for all Tx queues */
527 iwl_hw_txq_ctx_free(priv);
528}
529EXPORT_SYMBOL(iwl_txq_ctx_stop);
fd4abac5
TW		 530
531/*
532 * handle build REPLY_TX command notification.
533 */
534static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
535 struct iwl_tx_cmd *tx_cmd,
e039fa4a 536 struct ieee80211_tx_info *info,
fd4abac5 537 struct ieee80211_hdr *hdr,
0e7690f1 538 u8 std_id)
fd4abac5 539{
fd7c8a40 540 __le16 fc = hdr->frame_control;
fd4abac5
TW		 541 __le32 tx_flags = tx_cmd->tx_flags;
542
543 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 544 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
fd4abac5 545 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 546 if (ieee80211_is_mgmt(fc))
fd4abac5 547 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 548 if (ieee80211_is_probe_resp(fc) &&
fd4abac5
TW		 549 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
550 tx_flags |= TX_CMD_FLG_TSF_MSK;
551 } else {
552 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
553 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
554 }
555
fd7c8a40 556 if (ieee80211_is_back_req(fc))
fd4abac5
TW		 557 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
558
559
560 tx_cmd->sta_id = std_id;
8b7b1e05 561 if (ieee80211_has_morefrags(fc))
fd4abac5
TW		 562 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
563
fd7c8a40
HH		 564 if (ieee80211_is_data_qos(fc)) {
565 u8 *qc = ieee80211_get_qos_ctl(hdr);
fd4abac5
TW		 566 tx_cmd->tid_tspec = qc[0] & 0xf;
567 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
568 } else {
569 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
570 }
571
a326a5d0 572 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
fd4abac5
TW		 573
574 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
575 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
576
577 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 578 if (ieee80211_is_mgmt(fc)) {
579 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
fd4abac5
TW		 580 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
581 else
582 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
583 } else {
584 tx_cmd->timeout.pm_frame_timeout = 0;
585 }
586
587 tx_cmd->driver_txop = 0;
588 tx_cmd->tx_flags = tx_flags;
589 tx_cmd->next_frame_len = 0;
590}
591
592#define RTS_HCCA_RETRY_LIMIT 3
593#define RTS_DFAULT_RETRY_LIMIT 60
594
595static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
596 struct iwl_tx_cmd *tx_cmd,
e039fa4a 597 struct ieee80211_tx_info *info,
fd7c8a40 598 __le16 fc, int sta_id,
fd4abac5
TW		 599 int is_hcca)
600{
76eff18b
TW		 601 u32 rate_flags = 0;
602 int rate_idx;
fd4abac5
TW		 603 u8 rts_retry_limit = 0;
604 u8 data_retry_limit = 0;
605 u8 rate_plcp;
2e92e6f2 606
e039fa4a 607 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
2e92e6f2 608 IWL_RATE_COUNT - 1);
fd4abac5
TW		 609
610 rate_plcp = iwl_rates[rate_idx].plcp;
611
612 rts_retry_limit = (is_hcca) ?
613 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
614
615 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
616 rate_flags |= RATE_MCS_CCK_MSK;
617
618
fd7c8a40 619 if (ieee80211_is_probe_resp(fc)) {
fd4abac5
TW		 620 data_retry_limit = 3;
621 if (data_retry_limit < rts_retry_limit)
622 rts_retry_limit = data_retry_limit;
623 } else
624 data_retry_limit = IWL_DEFAULT_TX_RETRY;
625
626 if (priv->data_retry_limit != -1)
627 data_retry_limit = priv->data_retry_limit;
628
629
630 if (ieee80211_is_data(fc)) {
631 tx_cmd->initial_rate_index = 0;
632 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
633 } else {
fd7c8a40
HH		 634 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
635 case cpu_to_le16(IEEE80211_STYPE_AUTH):
636 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
637 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
638 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
fd4abac5
TW		 639 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
640 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
641 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
642 }
643 break;
644 default:
645 break;
646 }
647
76eff18b
TW		 648 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
649 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
fd4abac5
TW		 650 }
651
652 tx_cmd->rts_retry_limit = rts_retry_limit;
653 tx_cmd->data_retry_limit = data_retry_limit;
e7d326ac 654 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
fd4abac5
TW		 655}
656
657static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
e039fa4a 658 struct ieee80211_tx_info *info,
fd4abac5
TW		 659 struct iwl_tx_cmd *tx_cmd,
660 struct sk_buff *skb_frag,
661 int sta_id)
662{
e039fa4a 663 struct ieee80211_key_conf *keyconf = info->control.hw_key;
fd4abac5 664
ccc038ab 665 switch (keyconf->alg) {
fd4abac5
TW		 666 case ALG_CCMP:
667 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
ccc038ab 668 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
e039fa4a 669 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5 670 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
a96a27f9 671 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
fd4abac5
TW		 672 break;
673
674 case ALG_TKIP:
675 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
ccc038ab 676 ieee80211_get_tkip_key(keyconf, skb_frag,
fd4abac5
TW		 677 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
678 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
679 break;
680
681 case ALG_WEP:
fd4abac5 682 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
ccc038ab
EG		 683 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
684
685 if (keyconf->keylen == WEP_KEY_LEN_128)
686 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
687
688 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
fd4abac5
TW		 689
690 IWL_DEBUG_TX("Configuring packet for WEP encryption "
ccc038ab 691 "with key %d\n", keyconf->keyidx);
fd4abac5
TW		 692 break;
693
694 default:
978785a3 695 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
fd4abac5
TW		 696 break;
697 }
698}
699
700static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
701{
702 /* 0 - mgmt, 1 - cnt, 2 - data */
703 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
704 priv->tx_stats[idx].cnt++;
705 priv->tx_stats[idx].bytes += len;
706}
707
708/*
709 * start REPLY_TX command process
710 */
e039fa4a 711int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
fd4abac5
TW		 712{
713 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 714 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f3674227
TW		 715 struct iwl_tx_queue *txq;
716 struct iwl_queue *q;
717 struct iwl_cmd *out_cmd;
718 struct iwl_tx_cmd *tx_cmd;
719 int swq_id, txq_id;
fd4abac5
TW		 720 dma_addr_t phys_addr;
721 dma_addr_t txcmd_phys;
722 dma_addr_t scratch_phys;
b88b15df 723 u16 len, len_org;
fd4abac5 724 u16 seq_number = 0;
fd7c8a40 725 __le16 fc;
0e7690f1 726 u8 hdr_len;
f3674227 727 u8 sta_id;
fd4abac5
TW		 728 u8 wait_write_ptr = 0;
729 u8 tid = 0;
730 u8 *qc = NULL;
731 unsigned long flags;
732 int ret;
733
734 spin_lock_irqsave(&priv->lock, flags);
735 if (iwl_is_rfkill(priv)) {
736 IWL_DEBUG_DROP("Dropping - RF KILL\n");
737 goto drop_unlock;
738 }
739
e039fa4a 740 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
2e92e6f2 741 IWL_INVALID_RATE) {
15b1687c 742 IWL_ERR(priv, "ERROR: No TX rate available.\n");
fd4abac5
TW		 743 goto drop_unlock;
744 }
745
fd7c8a40 746 fc = hdr->frame_control;
fd4abac5
TW		 747
748#ifdef CONFIG_IWLWIFI_DEBUG
749 if (ieee80211_is_auth(fc))
750 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 751 else if (ieee80211_is_assoc_req(fc))
fd4abac5 752 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 753 else if (ieee80211_is_reassoc_req(fc))
fd4abac5
TW		 754 IWL_DEBUG_TX("Sending REASSOC frame\n");
755#endif
756
757 /* drop all data frame if we are not associated */
fd7c8a40 758 if (ieee80211_is_data(fc) &&
05c914fe 759 (priv->iw_mode != NL80211_IFTYPE_MONITOR ||
d10c4ec8
SG		 760 !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */
761 (!iwl_is_associated(priv) ||
05c914fe 762 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
d10c4ec8 763 !priv->assoc_station_added)) {
fd4abac5
TW		 764 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
765 goto drop_unlock;
766 }
767
768 spin_unlock_irqrestore(&priv->lock, flags);
769
7294ec95 770 hdr_len = ieee80211_hdrlen(fc);
fd4abac5
TW		 771
772 /* Find (or create) index into station table for destination station */
773 sta_id = iwl_get_sta_id(priv, hdr);
774 if (sta_id == IWL_INVALID_STATION) {
e174961c
JB		 775 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
776 hdr->addr1);
fd4abac5
TW		 777 goto drop;
778 }
779
780 IWL_DEBUG_TX("station Id %d\n", sta_id);
781
f3674227
TW		 782 swq_id = skb_get_queue_mapping(skb);
783 txq_id = swq_id;
fd7c8a40
HH		 784 if (ieee80211_is_data_qos(fc)) {
785 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 786 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
f3674227
TW		 787 seq_number = priv->stations[sta_id].tid[tid].seq_number;
788 seq_number &= IEEE80211_SCTL_SEQ;
789 hdr->seq_ctrl = hdr->seq_ctrl &
790 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG);
791 hdr->seq_ctrl |= cpu_to_le16(seq_number);
fd4abac5 792 seq_number += 0x10;
fd4abac5 793 /* aggregation is on for this <sta,tid> */
e039fa4a 794 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 795 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
796 priv->stations[sta_id].tid[tid].tfds_in_queue++;
fd4abac5
TW		 797 }
798
fd4abac5
TW		 799 txq = &priv->txq[txq_id];
800 q = &txq->q;
3fd07a1e 801 txq->swq_id = swq_id;
fd4abac5
TW		 802
803 spin_lock_irqsave(&priv->lock, flags);
804
fd4abac5
TW		 805 /* Set up driver data for this TFD */
806 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
807 txq->txb[q->write_ptr].skb[0] = skb;
fd4abac5
TW		 808
809 /* Set up first empty entry in queue's array of Tx/cmd buffers */
b88b15df 810 out_cmd = txq->cmd[q->write_ptr];
fd4abac5
TW		 811 tx_cmd = &out_cmd->cmd.tx;
812 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
813 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
814
815 /*
816 * Set up the Tx-command (not MAC!) header.
817 * Store the chosen Tx queue and TFD index within the sequence field;
818 * after Tx, uCode's Tx response will return this value so driver can
819 * locate the frame within the tx queue and do post-tx processing.
820 */
821 out_cmd->hdr.cmd = REPLY_TX;
822 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
823 INDEX_TO_SEQ(q->write_ptr)));
824
825 /* Copy MAC header from skb into command buffer */
826 memcpy(tx_cmd->hdr, hdr, hdr_len);
827
828 /*
829 * Use the first empty entry in this queue's command buffer array
830 * to contain the Tx command and MAC header concatenated together
831 * (payload data will be in another buffer).
832 * Size of this varies, due to varying MAC header length.
833 * If end is not dword aligned, we'll have 2 extra bytes at the end
834 * of the MAC header (device reads on dword boundaries).
835 * We'll tell device about this padding later.
836 */
837 len = sizeof(struct iwl_tx_cmd) +
838 sizeof(struct iwl_cmd_header) + hdr_len;
839
840 len_org = len;
841 len = (len + 3) & ~3;
842
843 if (len_org != len)
844 len_org = 1;
845 else
846 len_org = 0;
847
848 /* Physical address of this Tx command's header (not MAC header!),
849 * within command buffer array. */
499b1883
TW		 850 txcmd_phys = pci_map_single(priv->pci_dev,
851 out_cmd, sizeof(struct iwl_cmd),
852 PCI_DMA_TODEVICE);
853 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
854 pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
fd4abac5
TW		 855 /* Add buffer containing Tx command and MAC(!) header to TFD's
856 * first entry */
499b1883 857 txcmd_phys += offsetof(struct iwl_cmd, hdr);
7aaa1d79
SO		 858 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
859 txcmd_phys, len, 1, 0);
fd4abac5 860
d0f09804 861 if (info->control.hw_key)
e039fa4a 862 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
fd4abac5
TW		 863
864 /* Set up TFD's 2nd entry to point directly to remainder of skb,
865 * if any (802.11 null frames have no payload). */
866 len = skb->len - hdr_len;
867 if (len) {
868 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
869 len, PCI_DMA_TODEVICE);
7aaa1d79
SO		 870 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
871 phys_addr, len,
872 0, 0);
fd4abac5
TW		 873 }
874
875 /* Tell NIC about any 2-byte padding after MAC header */
876 if (len_org)
877 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
878
879 /* Total # bytes to be transmitted */
880 len = (u16)skb->len;
881 tx_cmd->len = cpu_to_le16(len);
882 /* TODO need this for burst mode later on */
0e7690f1 883 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
fd4abac5
TW		 884
885 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 886 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
fd4abac5 887
fd7c8a40 888 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
fd4abac5
TW		 889
890 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
891 offsetof(struct iwl_tx_cmd, scratch);
892 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
499b1883 893 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
fd4abac5 894
8b7b1e05 895 if (!ieee80211_has_morefrags(hdr->frame_control)) {
fd4abac5
TW		 896 txq->need_update = 1;
897 if (qc)
898 priv->stations[sta_id].tid[tid].seq_number = seq_number;
899 } else {
900 wait_write_ptr = 1;
901 txq->need_update = 0;
902 }
903
904 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
905
906 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
907
908 /* Set up entry for this TFD in Tx byte-count array */
909 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
910
911 /* Tell device the write index *just past* this latest filled TFD */
912 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
913 ret = iwl_txq_update_write_ptr(priv, txq);
914 spin_unlock_irqrestore(&priv->lock, flags);
915
916 if (ret)
917 return ret;
918
143b09ef 919 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
fd4abac5
TW		 920 if (wait_write_ptr) {
921 spin_lock_irqsave(&priv->lock, flags);
922 txq->need_update = 1;
923 iwl_txq_update_write_ptr(priv, txq);
924 spin_unlock_irqrestore(&priv->lock, flags);
143b09ef 925 } else {
3fd07a1e 926 ieee80211_stop_queue(priv->hw, txq->swq_id);
fd4abac5 927 }
fd4abac5
TW		 928 }
929
930 return 0;
931
932drop_unlock:
933 spin_unlock_irqrestore(&priv->lock, flags);
934drop:
935 return -1;
936}
937EXPORT_SYMBOL(iwl_tx_skb);
938
939/*************** HOST COMMAND QUEUE FUNCTIONS *****/
940
941/**
942 * iwl_enqueue_hcmd - enqueue a uCode command
943 * @priv: device private data point
944 * @cmd: a point to the ucode command structure
945 *
946 * The function returns < 0 values to indicate the operation is
947 * failed. On success, it turns the index (> 0) of command in the
948 * command queue.
949 */
950int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
951{
952 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
953 struct iwl_queue *q = &txq->q;
fd4abac5 954 struct iwl_cmd *out_cmd;
fd4abac5 955 dma_addr_t phys_addr;
fd4abac5 956 unsigned long flags;
f3674227
TW		 957 int len, ret;
958 u32 idx;
959 u16 fix_size;
fd4abac5
TW		 960
961 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
962 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
963
964 /* If any of the command structures end up being larger than
965 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
966 * we will need to increase the size of the TFD entries */
967 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
968 !(cmd->meta.flags & CMD_SIZE_HUGE));
969
970 if (iwl_is_rfkill(priv)) {
971 IWL_DEBUG_INFO("Not sending command - RF KILL");
972 return -EIO;
973 }
974
975 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
15b1687c 976 IWL_ERR(priv, "No space for Tx\n");
fd4abac5
TW		 977 return -ENOSPC;
978 }
979
980 spin_lock_irqsave(&priv->hcmd_lock, flags);
981
fd4abac5 982 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
da99c4b6 983 out_cmd = txq->cmd[idx];
fd4abac5
TW		 984
985 out_cmd->hdr.cmd = cmd->id;
986 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
987 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
988
989 /* At this point, the out_cmd now has all of the incoming cmd
990 * information */
991
992 out_cmd->hdr.flags = 0;
993 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
994 INDEX_TO_SEQ(q->write_ptr));
995 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
9734cb23 996 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
da99c4b6
GG		 997 len = (idx == TFD_CMD_SLOTS) ?
998 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
499b1883
TW		 999
1000 phys_addr = pci_map_single(priv->pci_dev, out_cmd,
1001 len, PCI_DMA_TODEVICE);
1002 pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
1003 pci_unmap_len_set(&out_cmd->meta, len, len);
da99c4b6 1004 phys_addr += offsetof(struct iwl_cmd, hdr);
499b1883 1005
7aaa1d79 1006 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
518099a8
SO		 1007 phys_addr, fix_size, 1,
1008 U32_PAD(cmd->len));
fd4abac5 1009
ded2ae7c
EK		 1010#ifdef CONFIG_IWLWIFI_DEBUG
1011 switch (out_cmd->hdr.cmd) {
1012 case REPLY_TX_LINK_QUALITY_CMD:
1013 case SENSITIVITY_CMD:
1014 IWL_DEBUG_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
1015 "%d bytes at %d[%d]:%d\n",
1016 get_cmd_string(out_cmd->hdr.cmd),
1017 out_cmd->hdr.cmd,
1018 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1019 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1020 break;
1021 default:
1022 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1023 "%d bytes at %d[%d]:%d\n",
1024 get_cmd_string(out_cmd->hdr.cmd),
1025 out_cmd->hdr.cmd,
1026 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1027 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1028 }
1029#endif
fd4abac5
TW		 1030 txq->need_update = 1;
1031
518099a8
SO		 1032 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1033 /* Set up entry in queue's byte count circular buffer */
1034 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
fd4abac5
TW		 1035
1036 /* Increment and update queue's write index */
1037 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1038 ret = iwl_txq_update_write_ptr(priv, txq);
1039
1040 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1041 return ret ? ret : idx;
1042}
1043
17b88929
TW		 1044int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1045{
1046 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1047 struct iwl_queue *q = &txq->q;
1048 struct iwl_tx_info *tx_info;
1049 int nfreed = 0;
1050
1051 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
15b1687c 1052 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
17b88929
TW		 1053 "is out of range [0-%d] %d %d.\n", txq_id,
1054 index, q->n_bd, q->write_ptr, q->read_ptr);
1055 return 0;
1056 }
1057
499b1883
TW		 1058 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1059 q->read_ptr != index;
1060 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
17b88929
TW		 1061
1062 tx_info = &txq->txb[txq->q.read_ptr];
1063 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1064 tx_info->skb[0] = NULL;
17b88929 1065
972cf447
TW		 1066 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1067 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1068
7aaa1d79 1069 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
17b88929
TW		 1070 nfreed++;
1071 }
1072 return nfreed;
1073}
1074EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1075
1076
1077/**
1078 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1079 *
1080 * When FW advances 'R' index, all entries between old and new 'R' index
1081 * need to be reclaimed. As result, some free space forms. If there is
1082 * enough free space (> low mark), wake the stack that feeds us.
1083 */
499b1883
TW		 1084static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1085 int idx, int cmd_idx)
17b88929
TW		 1086{
1087 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1088 struct iwl_queue *q = &txq->q;
1089 int nfreed = 0;
1090
499b1883 1091 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
15b1687c 1092 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
17b88929 1093 "is out of range [0-%d] %d %d.\n", txq_id,
499b1883 1094 idx, q->n_bd, q->write_ptr, q->read_ptr);
17b88929
TW		 1095 return;
1096 }
1097
499b1883
TW		 1098 pci_unmap_single(priv->pci_dev,
1099 pci_unmap_addr(&txq->cmd[cmd_idx]->meta, mapping),
1100 pci_unmap_len(&txq->cmd[cmd_idx]->meta, len),
1101 PCI_DMA_TODEVICE);
1102
1103 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1104 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
17b88929 1105
499b1883 1106 if (nfreed++ > 0) {
15b1687c 1107 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
17b88929
TW		 1108 q->write_ptr, q->read_ptr);
1109 queue_work(priv->workqueue, &priv->restart);
1110 }
da99c4b6 1111
17b88929
TW		 1112 }
1113}
1114
1115/**
1116 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1117 * @rxb: Rx buffer to reclaim
1118 *
1119 * If an Rx buffer has an async callback associated with it the callback
1120 * will be executed. The attached skb (if present) will only be freed
1121 * if the callback returns 1
1122 */
1123void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1124{
1125 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1126 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1127 int txq_id = SEQ_TO_QUEUE(sequence);
1128 int index = SEQ_TO_INDEX(sequence);
17b88929 1129 int cmd_index;
9734cb23 1130 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
17b88929
TW		 1131 struct iwl_cmd *cmd;
1132
1133 /* If a Tx command is being handled and it isn't in the actual
1134 * command queue then there a command routing bug has been introduced
1135 * in the queue management code. */
55d6a3cd 1136 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
01ef9323
WT		 1137 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1138 txq_id, sequence,
1139 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1140 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1141 iwl_print_hex_dump(priv, IWL_DL_INFO , rxb, 32);
55d6a3cd 1142 return;
01ef9323 1143 }
17b88929
TW		 1144
1145 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
da99c4b6 1146 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
17b88929
TW		 1147
1148 /* Input error checking is done when commands are added to queue. */
1149 if (cmd->meta.flags & CMD_WANT_SKB) {
1150 cmd->meta.source->u.skb = rxb->skb;
1151 rxb->skb = NULL;
1152 } else if (cmd->meta.u.callback &&
1153 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1154 rxb->skb = NULL;
1155
499b1883 1156 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
17b88929
TW		 1157
1158 if (!(cmd->meta.flags & CMD_ASYNC)) {
1159 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1160 wake_up_interruptible(&priv->wait_command_queue);
1161 }
1162}
1163EXPORT_SYMBOL(iwl_tx_cmd_complete);
1164
30e553e3
TW		 1165/*
1166 * Find first available (lowest unused) Tx Queue, mark it "active".
1167 * Called only when finding queue for aggregation.
1168 * Should never return anything < 7, because they should already
1169 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1170 */
1171static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1172{
1173 int txq_id;
1174
1175 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1176 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1177 return txq_id;
1178 return -1;
1179}
1180
1181int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1182{
1183 int sta_id;
1184 int tx_fifo;
1185 int txq_id;
1186 int ret;
1187 unsigned long flags;
1188 struct iwl_tid_data *tid_data;
30e553e3
TW		 1189
1190 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1191 tx_fifo = default_tid_to_tx_fifo[tid];
1192 else
1193 return -EINVAL;
1194
39aadf8c 1195 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
e174961c 1196 __func__, ra, tid);
30e553e3
TW		 1197
1198 sta_id = iwl_find_station(priv, ra);
1199 if (sta_id == IWL_INVALID_STATION)
1200 return -ENXIO;
1201
1202 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
15b1687c 1203 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
30e553e3
TW		 1204 return -ENXIO;
1205 }
1206
1207 txq_id = iwl_txq_ctx_activate_free(priv);
1208 if (txq_id == -1)
1209 return -ENXIO;
1210
1211 spin_lock_irqsave(&priv->sta_lock, flags);
1212 tid_data = &priv->stations[sta_id].tid[tid];
1213 *ssn = SEQ_TO_SN(tid_data->seq_number);
1214 tid_data->agg.txq_id = txq_id;
1215 spin_unlock_irqrestore(&priv->sta_lock, flags);
1216
1217 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1218 sta_id, tid, *ssn);
1219 if (ret)
1220 return ret;
1221
1222 if (tid_data->tfds_in_queue == 0) {
978785a3 1223 IWL_ERR(priv, "HW queue is empty\n");
30e553e3
TW		 1224 tid_data->agg.state = IWL_AGG_ON;
1225 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1226 } else {
1227 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1228 tid_data->tfds_in_queue);
1229 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1230 }
1231 return ret;
1232}
1233EXPORT_SYMBOL(iwl_tx_agg_start);
1234
1235int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1236{
1237 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1238 struct iwl_tid_data *tid_data;
1239 int ret, write_ptr, read_ptr;
1240 unsigned long flags;
30e553e3
TW		 1241
1242 if (!ra) {
15b1687c 1243 IWL_ERR(priv, "ra = NULL\n");
30e553e3
TW		 1244 return -EINVAL;
1245 }
1246
1247 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1248 tx_fifo_id = default_tid_to_tx_fifo[tid];
1249 else
1250 return -EINVAL;
1251
1252 sta_id = iwl_find_station(priv, ra);
1253
1254 if (sta_id == IWL_INVALID_STATION)
1255 return -ENXIO;
1256
1257 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
39aadf8c 1258 IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n");
30e553e3
TW		 1259
1260 tid_data = &priv->stations[sta_id].tid[tid];
1261 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1262 txq_id = tid_data->agg.txq_id;
1263 write_ptr = priv->txq[txq_id].q.write_ptr;
1264 read_ptr = priv->txq[txq_id].q.read_ptr;
1265
1266 /* The queue is not empty */
1267 if (write_ptr != read_ptr) {
1268 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1269 priv->stations[sta_id].tid[tid].agg.state =
1270 IWL_EMPTYING_HW_QUEUE_DELBA;
1271 return 0;
1272 }
1273
1274 IWL_DEBUG_HT("HW queue is empty\n");
1275 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1276
1277 spin_lock_irqsave(&priv->lock, flags);
1278 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1279 tx_fifo_id);
1280 spin_unlock_irqrestore(&priv->lock, flags);
1281
1282 if (ret)
1283 return ret;
1284
1285 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1286
1287 return 0;
1288}
1289EXPORT_SYMBOL(iwl_tx_agg_stop);
1290
1291int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1292{
1293 struct iwl_queue *q = &priv->txq[txq_id].q;
1294 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1295 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1296
1297 switch (priv->stations[sta_id].tid[tid].agg.state) {
1298 case IWL_EMPTYING_HW_QUEUE_DELBA:
1299 /* We are reclaiming the last packet of the */
1300 /* aggregated HW queue */
3fd07a1e
TW		 1301 if ((txq_id == tid_data->agg.txq_id) &&
1302 (q->read_ptr == q->write_ptr)) {
30e553e3
TW		 1303 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1304 int tx_fifo = default_tid_to_tx_fifo[tid];
1305 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1306 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1307 ssn, tx_fifo);
1308 tid_data->agg.state = IWL_AGG_OFF;
1309 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1310 }
1311 break;
1312 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1313 /* We are reclaiming the last packet of the queue */
1314 if (tid_data->tfds_in_queue == 0) {
1315 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1316 tid_data->agg.state = IWL_AGG_ON;
1317 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1318 }
1319 break;
1320 }
1321 return 0;
1322}
1323EXPORT_SYMBOL(iwl_txq_check_empty);
30e553e3 1324
653fa4a0
EG		 1325/**
1326 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1327 *
1328 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1329 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1330 */
1331static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1332 struct iwl_ht_agg *agg,
1333 struct iwl_compressed_ba_resp *ba_resp)
1334
1335{
1336 int i, sh, ack;
1337 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1338 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1339 u64 bitmap;
1340 int successes = 0;
1341 struct ieee80211_tx_info *info;
1342
1343 if (unlikely(!agg->wait_for_ba)) {
15b1687c 1344 IWL_ERR(priv, "Received BA when not expected\n");
653fa4a0
EG		 1345 return -EINVAL;
1346 }
1347
1348 /* Mark that the expected block-ack response arrived */
1349 agg->wait_for_ba = 0;
1350 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1351
1352 /* Calculate shift to align block-ack bits with our Tx window bits */
3fd07a1e 1353 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
653fa4a0
EG		 1354 if (sh < 0) /* tbw something is wrong with indices */
1355 sh += 0x100;
1356
1357 /* don't use 64-bit values for now */
1358 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1359
1360 if (agg->frame_count > (64 - sh)) {
1361 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1362 return -1;
1363 }
1364
1365 /* check for success or failure according to the
1366 * transmitted bitmap and block-ack bitmap */
1367 bitmap &= agg->bitmap;
1368
1369 /* For each frame attempted in aggregation,
1370 * update driver's record of tx frame's status. */
1371 for (i = 0; i < agg->frame_count ; i++) {
4aa41f12 1372 ack = bitmap & (1ULL << i);
653fa4a0
EG		 1373 successes += !!ack;
1374 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
c3056065 1375 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
653fa4a0
EG		 1376 agg->start_idx + i);
1377 }
1378
1379 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1380 memset(&info->status, 0, sizeof(info->status));
1381 info->flags = IEEE80211_TX_STAT_ACK;
1382 info->flags |= IEEE80211_TX_STAT_AMPDU;
1383 info->status.ampdu_ack_map = successes;
1384 info->status.ampdu_ack_len = agg->frame_count;
1385 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1386
1387 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
1388
1389 return 0;
1390}
1391
1392/**
1393 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1394 *
1395 * Handles block-acknowledge notification from device, which reports success
1396 * of frames sent via aggregation.
1397 */
1398void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1399 struct iwl_rx_mem_buffer *rxb)
1400{
1401 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1402 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
653fa4a0
EG		 1403 struct iwl_tx_queue *txq = NULL;
1404 struct iwl_ht_agg *agg;
3fd07a1e
TW		 1405 int index;
1406 int sta_id;
1407 int tid;
653fa4a0
EG		 1408
1409 /* "flow" corresponds to Tx queue */
1410 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1411
1412 /* "ssn" is start of block-ack Tx window, corresponds to index
1413 * (in Tx queue's circular buffer) of first TFD/frame in window */
1414 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1415
1416 if (scd_flow >= priv->hw_params.max_txq_num) {
15b1687c
WT		 1417 IWL_ERR(priv,
1418 "BUG_ON scd_flow is bigger than number of queues\n");
653fa4a0
EG		 1419 return;
1420 }
1421
1422 txq = &priv->txq[scd_flow];
3fd07a1e
TW		 1423 sta_id = ba_resp->sta_id;
1424 tid = ba_resp->tid;
1425 agg = &priv->stations[sta_id].tid[tid].agg;
653fa4a0
EG		 1426
1427 /* Find index just before block-ack window */
1428 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1429
1430 /* TODO: Need to get this copy more safely - now good for debug */
1431
3fd07a1e 1432 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d] Received from %pM, "
653fa4a0
EG		 1433 "sta_id = %d\n",
1434 agg->wait_for_ba,
e174961c 1435 (u8 *) &ba_resp->sta_addr_lo32,
653fa4a0
EG		 1436 ba_resp->sta_id);
1437 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1438 "%d, scd_ssn = %d\n",
1439 ba_resp->tid,
1440 ba_resp->seq_ctl,
1441 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1442 ba_resp->scd_flow,
1443 ba_resp->scd_ssn);
1444 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1445 agg->start_idx,
1446 (unsigned long long)agg->bitmap);
1447
1448 /* Update driver's record of ACK vs. not for each frame in window */
1449 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1450
1451 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1452 * block-ack window (we assume that they've been successfully
1453 * transmitted ... if not, it's too late anyway). */
1454 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1455 /* calculate mac80211 ampdu sw queue to wake */
653fa4a0 1456 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
3fd07a1e
TW		 1457 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1458
1459 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1460 priv->mac80211_registered &&
1461 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1462 ieee80211_wake_queue(priv->hw, txq->swq_id);
1463
1464 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
653fa4a0
EG		 1465 }
1466}
1467EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1468
994d31f7 1469#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6
TW		 1470#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1471
1472const char *iwl_get_tx_fail_reason(u32 status)
1473{
1474 switch (status & TX_STATUS_MSK) {
1475 case TX_STATUS_SUCCESS:
1476 return "SUCCESS";
1477 TX_STATUS_ENTRY(SHORT_LIMIT);
1478 TX_STATUS_ENTRY(LONG_LIMIT);
1479 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1480 TX_STATUS_ENTRY(MGMNT_ABORT);
1481 TX_STATUS_ENTRY(NEXT_FRAG);
1482 TX_STATUS_ENTRY(LIFE_EXPIRE);
1483 TX_STATUS_ENTRY(DEST_PS);
1484 TX_STATUS_ENTRY(ABORTED);
1485 TX_STATUS_ENTRY(BT_RETRY);
1486 TX_STATUS_ENTRY(STA_INVALID);
1487 TX_STATUS_ENTRY(FRAG_DROPPED);
1488 TX_STATUS_ENTRY(TID_DISABLE);
1489 TX_STATUS_ENTRY(FRAME_FLUSHED);
1490 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1491 TX_STATUS_ENTRY(TX_LOCKED);
1492 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1493 }
1494
1495 return "UNKNOWN";
1496}
1497EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1498#endif /* CONFIG_IWLWIFI_DEBUG */
Linux 6.x block layer and io_uring tree(s)