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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
fd4abac5 | 30 | #include <linux/etherdevice.h> |
d43c36dc | 31 | #include <linux/sched.h> |
1053d35f RR |
32 | #include <net/mac80211.h> |
33 | #include "iwl-eeprom.h" | |
34 | #include "iwl-dev.h" | |
35 | #include "iwl-core.h" | |
36 | #include "iwl-sta.h" | |
37 | #include "iwl-io.h" | |
38 | #include "iwl-helpers.h" | |
39 | ||
30e553e3 TW |
40 | static const u16 default_tid_to_tx_fifo[] = { |
41 | IWL_TX_FIFO_AC1, | |
42 | IWL_TX_FIFO_AC0, | |
43 | IWL_TX_FIFO_AC0, | |
44 | IWL_TX_FIFO_AC1, | |
45 | IWL_TX_FIFO_AC2, | |
46 | IWL_TX_FIFO_AC2, | |
47 | IWL_TX_FIFO_AC3, | |
48 | IWL_TX_FIFO_AC3, | |
49 | IWL_TX_FIFO_NONE, | |
50 | IWL_TX_FIFO_NONE, | |
51 | IWL_TX_FIFO_NONE, | |
52 | IWL_TX_FIFO_NONE, | |
53 | IWL_TX_FIFO_NONE, | |
54 | IWL_TX_FIFO_NONE, | |
55 | IWL_TX_FIFO_NONE, | |
56 | IWL_TX_FIFO_NONE, | |
57 | IWL_TX_FIFO_AC3 | |
58 | }; | |
59 | ||
4ddbb7d0 TW |
60 | static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv, |
61 | struct iwl_dma_ptr *ptr, size_t size) | |
62 | { | |
f36d04ab SG |
63 | ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma, |
64 | GFP_KERNEL); | |
4ddbb7d0 TW |
65 | if (!ptr->addr) |
66 | return -ENOMEM; | |
67 | ptr->size = size; | |
68 | return 0; | |
69 | } | |
70 | ||
71 | static inline void iwl_free_dma_ptr(struct iwl_priv *priv, | |
72 | struct iwl_dma_ptr *ptr) | |
73 | { | |
74 | if (unlikely(!ptr->addr)) | |
75 | return; | |
76 | ||
f36d04ab | 77 | dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma); |
4ddbb7d0 TW |
78 | memset(ptr, 0, sizeof(*ptr)); |
79 | } | |
80 | ||
fd4abac5 TW |
81 | /** |
82 | * iwl_txq_update_write_ptr - Send new write index to hardware | |
83 | */ | |
7bfedc59 | 84 | void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
fd4abac5 TW |
85 | { |
86 | u32 reg = 0; | |
fd4abac5 TW |
87 | int txq_id = txq->q.id; |
88 | ||
89 | if (txq->need_update == 0) | |
7bfedc59 | 90 | return; |
fd4abac5 TW |
91 | |
92 | /* if we're trying to save power */ | |
93 | if (test_bit(STATUS_POWER_PMI, &priv->status)) { | |
94 | /* wake up nic if it's powered down ... | |
95 | * uCode will wake up, and interrupt us again, so next | |
96 | * time we'll skip this part. */ | |
97 | reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); | |
98 | ||
99 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
309e731a BC |
100 | IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", |
101 | txq_id, reg); | |
fd4abac5 TW |
102 | iwl_set_bit(priv, CSR_GP_CNTRL, |
103 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7bfedc59 | 104 | return; |
fd4abac5 TW |
105 | } |
106 | ||
fd4abac5 TW |
107 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
108 | txq->q.write_ptr | (txq_id << 8)); | |
fd4abac5 TW |
109 | |
110 | /* else not in power-save mode, uCode will never sleep when we're | |
111 | * trying to tx (during RFKILL, we're not trying to tx). */ | |
112 | } else | |
113 | iwl_write32(priv, HBUS_TARG_WRPTR, | |
114 | txq->q.write_ptr | (txq_id << 8)); | |
115 | ||
116 | txq->need_update = 0; | |
fd4abac5 TW |
117 | } |
118 | EXPORT_SYMBOL(iwl_txq_update_write_ptr); | |
119 | ||
120 | ||
a239a8b4 WYG |
121 | void iwl_free_tfds_in_queue(struct iwl_priv *priv, |
122 | int sta_id, int tid, int freed) | |
123 | { | |
124 | if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed) | |
125 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; | |
126 | else { | |
c8406ea8 | 127 | IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n", |
a239a8b4 WYG |
128 | priv->stations[sta_id].tid[tid].tfds_in_queue, |
129 | freed); | |
130 | priv->stations[sta_id].tid[tid].tfds_in_queue = 0; | |
131 | } | |
132 | } | |
133 | EXPORT_SYMBOL(iwl_free_tfds_in_queue); | |
134 | ||
1053d35f RR |
135 | /** |
136 | * iwl_tx_queue_free - Deallocate DMA queue. | |
137 | * @txq: Transmit queue to deallocate. | |
138 | * | |
139 | * Empty queue by removing and destroying all BD's. | |
140 | * Free all buffers. | |
141 | * 0-fill, but do not free "txq" descriptor structure. | |
142 | */ | |
a8e74e27 | 143 | void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
1053d35f | 144 | { |
da99c4b6 | 145 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
443cfd45 | 146 | struct iwl_queue *q = &txq->q; |
f36d04ab | 147 | struct device *dev = &priv->pci_dev->dev; |
71c55d90 | 148 | int i; |
1053d35f RR |
149 | |
150 | if (q->n_bd == 0) | |
151 | return; | |
152 | ||
153 | /* first, empty all BD's */ | |
154 | for (; q->write_ptr != q->read_ptr; | |
155 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) | |
7aaa1d79 | 156 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
1053d35f | 157 | |
1053d35f | 158 | /* De-alloc array of command/tx buffers */ |
961ba60a | 159 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) |
da99c4b6 | 160 | kfree(txq->cmd[i]); |
1053d35f RR |
161 | |
162 | /* De-alloc circular buffer of TFDs */ | |
163 | if (txq->q.n_bd) | |
f36d04ab SG |
164 | dma_free_coherent(dev, priv->hw_params.tfd_size * |
165 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
1053d35f RR |
166 | |
167 | /* De-alloc array of per-TFD driver data */ | |
168 | kfree(txq->txb); | |
169 | txq->txb = NULL; | |
170 | ||
c2acea8e JB |
171 | /* deallocate arrays */ |
172 | kfree(txq->cmd); | |
173 | kfree(txq->meta); | |
174 | txq->cmd = NULL; | |
175 | txq->meta = NULL; | |
176 | ||
1053d35f RR |
177 | /* 0-fill queue descriptor structure */ |
178 | memset(txq, 0, sizeof(*txq)); | |
179 | } | |
a8e74e27 | 180 | EXPORT_SYMBOL(iwl_tx_queue_free); |
961ba60a TW |
181 | |
182 | /** | |
183 | * iwl_cmd_queue_free - Deallocate DMA queue. | |
184 | * @txq: Transmit queue to deallocate. | |
185 | * | |
186 | * Empty queue by removing and destroying all BD's. | |
187 | * Free all buffers. | |
188 | * 0-fill, but do not free "txq" descriptor structure. | |
189 | */ | |
3e5d238f | 190 | void iwl_cmd_queue_free(struct iwl_priv *priv) |
961ba60a TW |
191 | { |
192 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
193 | struct iwl_queue *q = &txq->q; | |
f36d04ab | 194 | struct device *dev = &priv->pci_dev->dev; |
71c55d90 | 195 | int i; |
dd487449 | 196 | bool huge = false; |
961ba60a TW |
197 | |
198 | if (q->n_bd == 0) | |
199 | return; | |
200 | ||
dd487449 ZY |
201 | for (; q->read_ptr != q->write_ptr; |
202 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
203 | /* we have no way to tell if it is a huge cmd ATM */ | |
204 | i = get_cmd_index(q, q->read_ptr, 0); | |
205 | ||
206 | if (txq->meta[i].flags & CMD_SIZE_HUGE) { | |
207 | huge = true; | |
208 | continue; | |
209 | } | |
210 | ||
211 | pci_unmap_single(priv->pci_dev, | |
212 | pci_unmap_addr(&txq->meta[i], mapping), | |
213 | pci_unmap_len(&txq->meta[i], len), | |
214 | PCI_DMA_BIDIRECTIONAL); | |
215 | } | |
216 | if (huge) { | |
217 | i = q->n_window; | |
218 | pci_unmap_single(priv->pci_dev, | |
219 | pci_unmap_addr(&txq->meta[i], mapping), | |
220 | pci_unmap_len(&txq->meta[i], len), | |
221 | PCI_DMA_BIDIRECTIONAL); | |
222 | } | |
223 | ||
961ba60a TW |
224 | /* De-alloc array of command/tx buffers */ |
225 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
226 | kfree(txq->cmd[i]); | |
227 | ||
228 | /* De-alloc circular buffer of TFDs */ | |
229 | if (txq->q.n_bd) | |
f36d04ab SG |
230 | dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd, |
231 | txq->tfds, txq->q.dma_addr); | |
961ba60a | 232 | |
28142986 RC |
233 | /* deallocate arrays */ |
234 | kfree(txq->cmd); | |
235 | kfree(txq->meta); | |
236 | txq->cmd = NULL; | |
237 | txq->meta = NULL; | |
238 | ||
961ba60a TW |
239 | /* 0-fill queue descriptor structure */ |
240 | memset(txq, 0, sizeof(*txq)); | |
241 | } | |
3e5d238f AK |
242 | EXPORT_SYMBOL(iwl_cmd_queue_free); |
243 | ||
fd4abac5 TW |
244 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
245 | * DMA services | |
246 | * | |
247 | * Theory of operation | |
248 | * | |
249 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
250 | * of buffer descriptors, each of which points to one or more data buffers for | |
251 | * the device to read from or fill. Driver and device exchange status of each | |
252 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
253 | * entries in each circular buffer, to protect against confusing empty and full | |
254 | * queue states. | |
255 | * | |
256 | * The device reads or writes the data in the queues via the device's several | |
257 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
258 | * | |
259 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
260 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
261 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
262 | * Tx queue resumed. | |
263 | * | |
264 | * See more detailed info in iwl-4965-hw.h. | |
265 | ***************************************************/ | |
266 | ||
267 | int iwl_queue_space(const struct iwl_queue *q) | |
268 | { | |
269 | int s = q->read_ptr - q->write_ptr; | |
270 | ||
271 | if (q->read_ptr > q->write_ptr) | |
272 | s -= q->n_bd; | |
273 | ||
274 | if (s <= 0) | |
275 | s += q->n_window; | |
276 | /* keep some reserve to not confuse empty and full situations */ | |
277 | s -= 2; | |
278 | if (s < 0) | |
279 | s = 0; | |
280 | return s; | |
281 | } | |
282 | EXPORT_SYMBOL(iwl_queue_space); | |
283 | ||
284 | ||
1053d35f RR |
285 | /** |
286 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
287 | */ | |
443cfd45 | 288 | static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, |
1053d35f RR |
289 | int count, int slots_num, u32 id) |
290 | { | |
291 | q->n_bd = count; | |
292 | q->n_window = slots_num; | |
293 | q->id = id; | |
294 | ||
295 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
296 | * and iwl_queue_dec_wrap are broken. */ | |
297 | BUG_ON(!is_power_of_2(count)); | |
298 | ||
299 | /* slots_num must be power-of-two size, otherwise | |
300 | * get_cmd_index is broken. */ | |
301 | BUG_ON(!is_power_of_2(slots_num)); | |
302 | ||
303 | q->low_mark = q->n_window / 4; | |
304 | if (q->low_mark < 4) | |
305 | q->low_mark = 4; | |
306 | ||
307 | q->high_mark = q->n_window / 8; | |
308 | if (q->high_mark < 2) | |
309 | q->high_mark = 2; | |
310 | ||
311 | q->write_ptr = q->read_ptr = 0; | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | /** | |
317 | * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
318 | */ | |
319 | static int iwl_tx_queue_alloc(struct iwl_priv *priv, | |
16466903 | 320 | struct iwl_tx_queue *txq, u32 id) |
1053d35f | 321 | { |
f36d04ab | 322 | struct device *dev = &priv->pci_dev->dev; |
3978e5bc | 323 | size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; |
1053d35f RR |
324 | |
325 | /* Driver private data, only for Tx (not command) queues, | |
326 | * not shared with device. */ | |
327 | if (id != IWL_CMD_QUEUE_NUM) { | |
328 | txq->txb = kmalloc(sizeof(txq->txb[0]) * | |
329 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); | |
330 | if (!txq->txb) { | |
15b1687c | 331 | IWL_ERR(priv, "kmalloc for auxiliary BD " |
1053d35f RR |
332 | "structures failed\n"); |
333 | goto error; | |
334 | } | |
3978e5bc | 335 | } else { |
1053d35f | 336 | txq->txb = NULL; |
3978e5bc | 337 | } |
1053d35f RR |
338 | |
339 | /* Circular buffer of transmit frame descriptors (TFDs), | |
340 | * shared with device */ | |
f36d04ab SG |
341 | txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, |
342 | GFP_KERNEL); | |
499b1883 | 343 | if (!txq->tfds) { |
3978e5bc | 344 | IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); |
1053d35f RR |
345 | goto error; |
346 | } | |
347 | txq->q.id = id; | |
348 | ||
349 | return 0; | |
350 | ||
351 | error: | |
352 | kfree(txq->txb); | |
353 | txq->txb = NULL; | |
354 | ||
355 | return -ENOMEM; | |
356 | } | |
357 | ||
1053d35f RR |
358 | /** |
359 | * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue | |
360 | */ | |
a8e74e27 SO |
361 | int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq, |
362 | int slots_num, u32 txq_id) | |
1053d35f | 363 | { |
da99c4b6 | 364 | int i, len; |
73b7d742 | 365 | int ret; |
c2acea8e | 366 | int actual_slots = slots_num; |
1053d35f RR |
367 | |
368 | /* | |
369 | * Alloc buffer array for commands (Tx or other types of commands). | |
370 | * For the command queue (#4), allocate command space + one big | |
371 | * command for scan, since scan command is very huge; the system will | |
372 | * not have two scans at the same time, so only one is needed. | |
373 | * For normal Tx queues (all other queues), no super-size command | |
374 | * space is needed. | |
375 | */ | |
c2acea8e JB |
376 | if (txq_id == IWL_CMD_QUEUE_NUM) |
377 | actual_slots++; | |
378 | ||
379 | txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots, | |
380 | GFP_KERNEL); | |
381 | txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots, | |
382 | GFP_KERNEL); | |
383 | ||
384 | if (!txq->meta || !txq->cmd) | |
385 | goto out_free_arrays; | |
386 | ||
387 | len = sizeof(struct iwl_device_cmd); | |
388 | for (i = 0; i < actual_slots; i++) { | |
389 | /* only happens for cmd queue */ | |
390 | if (i == slots_num) | |
89612124 | 391 | len = IWL_MAX_CMD_SIZE; |
da99c4b6 | 392 | |
49898852 | 393 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); |
da99c4b6 | 394 | if (!txq->cmd[i]) |
73b7d742 | 395 | goto err; |
da99c4b6 | 396 | } |
1053d35f RR |
397 | |
398 | /* Alloc driver data array and TFD circular buffer */ | |
73b7d742 TW |
399 | ret = iwl_tx_queue_alloc(priv, txq, txq_id); |
400 | if (ret) | |
401 | goto err; | |
1053d35f | 402 | |
1053d35f RR |
403 | txq->need_update = 0; |
404 | ||
1a716557 JB |
405 | /* |
406 | * Aggregation TX queues will get their ID when aggregation begins; | |
407 | * they overwrite the setting done here. The command FIFO doesn't | |
408 | * need an swq_id so don't set one to catch errors, all others can | |
409 | * be set up to the identity mapping. | |
410 | */ | |
411 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
45af8195 JB |
412 | txq->swq_id = txq_id; |
413 | ||
1053d35f RR |
414 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
415 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
416 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
417 | ||
418 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
419 | iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); | |
420 | ||
421 | /* Tell device where to find queue */ | |
a8e74e27 | 422 | priv->cfg->ops->lib->txq_init(priv, txq); |
1053d35f RR |
423 | |
424 | return 0; | |
73b7d742 | 425 | err: |
c2acea8e | 426 | for (i = 0; i < actual_slots; i++) |
73b7d742 | 427 | kfree(txq->cmd[i]); |
c2acea8e JB |
428 | out_free_arrays: |
429 | kfree(txq->meta); | |
430 | kfree(txq->cmd); | |
73b7d742 | 431 | |
73b7d742 | 432 | return -ENOMEM; |
1053d35f | 433 | } |
a8e74e27 SO |
434 | EXPORT_SYMBOL(iwl_tx_queue_init); |
435 | ||
da1bc453 TW |
436 | /** |
437 | * iwl_hw_txq_ctx_free - Free TXQ Context | |
438 | * | |
439 | * Destroy all TX DMA queues and structures | |
440 | */ | |
441 | void iwl_hw_txq_ctx_free(struct iwl_priv *priv) | |
442 | { | |
443 | int txq_id; | |
444 | ||
445 | /* Tx queues */ | |
77ca7d9e | 446 | if (priv->txq) { |
88804e2b WYG |
447 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; |
448 | txq_id++) | |
449 | if (txq_id == IWL_CMD_QUEUE_NUM) | |
450 | iwl_cmd_queue_free(priv); | |
451 | else | |
452 | iwl_tx_queue_free(priv, txq_id); | |
77ca7d9e | 453 | } |
4ddbb7d0 TW |
454 | iwl_free_dma_ptr(priv, &priv->kw); |
455 | ||
456 | iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); | |
88804e2b WYG |
457 | |
458 | /* free tx queue structure */ | |
459 | iwl_free_txq_mem(priv); | |
da1bc453 TW |
460 | } |
461 | EXPORT_SYMBOL(iwl_hw_txq_ctx_free); | |
462 | ||
1053d35f RR |
463 | /** |
464 | * iwl_txq_ctx_reset - Reset TX queue context | |
a96a27f9 | 465 | * Destroys all DMA structures and initialize them again |
1053d35f RR |
466 | * |
467 | * @param priv | |
468 | * @return error code | |
469 | */ | |
470 | int iwl_txq_ctx_reset(struct iwl_priv *priv) | |
471 | { | |
472 | int ret = 0; | |
473 | int txq_id, slots_num; | |
da1bc453 | 474 | unsigned long flags; |
1053d35f | 475 | |
1053d35f RR |
476 | /* Free all tx/cmd queues and keep-warm buffer */ |
477 | iwl_hw_txq_ctx_free(priv); | |
478 | ||
4ddbb7d0 TW |
479 | ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls, |
480 | priv->hw_params.scd_bc_tbls_size); | |
481 | if (ret) { | |
15b1687c | 482 | IWL_ERR(priv, "Scheduler BC Table allocation failed\n"); |
4ddbb7d0 TW |
483 | goto error_bc_tbls; |
484 | } | |
1053d35f | 485 | /* Alloc keep-warm buffer */ |
4ddbb7d0 | 486 | ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE); |
1053d35f | 487 | if (ret) { |
15b1687c | 488 | IWL_ERR(priv, "Keep Warm allocation failed\n"); |
1053d35f RR |
489 | goto error_kw; |
490 | } | |
88804e2b WYG |
491 | |
492 | /* allocate tx queue structure */ | |
493 | ret = iwl_alloc_txq_mem(priv); | |
494 | if (ret) | |
495 | goto error; | |
496 | ||
da1bc453 | 497 | spin_lock_irqsave(&priv->lock, flags); |
1053d35f RR |
498 | |
499 | /* Turn off all Tx DMA fifos */ | |
da1bc453 TW |
500 | priv->cfg->ops->lib->txq_set_sched(priv, 0); |
501 | ||
4ddbb7d0 TW |
502 | /* Tell NIC where to find the "keep warm" buffer */ |
503 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); | |
504 | ||
da1bc453 TW |
505 | spin_unlock_irqrestore(&priv->lock, flags); |
506 | ||
da1bc453 | 507 | /* Alloc and init all Tx queues, including the command queue (#4) */ |
1053d35f RR |
508 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { |
509 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | |
510 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
511 | ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | |
512 | txq_id); | |
513 | if (ret) { | |
15b1687c | 514 | IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); |
1053d35f RR |
515 | goto error; |
516 | } | |
517 | } | |
518 | ||
519 | return ret; | |
520 | ||
521 | error: | |
522 | iwl_hw_txq_ctx_free(priv); | |
4ddbb7d0 | 523 | iwl_free_dma_ptr(priv, &priv->kw); |
1053d35f | 524 | error_kw: |
4ddbb7d0 TW |
525 | iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); |
526 | error_bc_tbls: | |
1053d35f RR |
527 | return ret; |
528 | } | |
a33c2f47 | 529 | |
da1bc453 TW |
530 | /** |
531 | * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory | |
532 | */ | |
533 | void iwl_txq_ctx_stop(struct iwl_priv *priv) | |
534 | { | |
f3f911d1 | 535 | int ch; |
da1bc453 TW |
536 | unsigned long flags; |
537 | ||
da1bc453 TW |
538 | /* Turn off all Tx DMA fifos */ |
539 | spin_lock_irqsave(&priv->lock, flags); | |
da1bc453 TW |
540 | |
541 | priv->cfg->ops->lib->txq_set_sched(priv, 0); | |
542 | ||
543 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
f3f911d1 ZY |
544 | for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) { |
545 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
da1bc453 | 546 | iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG, |
f3f911d1 | 547 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
f056658b | 548 | 1000); |
da1bc453 | 549 | } |
da1bc453 TW |
550 | spin_unlock_irqrestore(&priv->lock, flags); |
551 | ||
552 | /* Deallocate memory for all Tx queues */ | |
553 | iwl_hw_txq_ctx_free(priv); | |
554 | } | |
555 | EXPORT_SYMBOL(iwl_txq_ctx_stop); | |
fd4abac5 TW |
556 | |
557 | /* | |
558 | * handle build REPLY_TX command notification. | |
559 | */ | |
560 | static void iwl_tx_cmd_build_basic(struct iwl_priv *priv, | |
561 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 562 | struct ieee80211_tx_info *info, |
fd4abac5 | 563 | struct ieee80211_hdr *hdr, |
0e7690f1 | 564 | u8 std_id) |
fd4abac5 | 565 | { |
fd7c8a40 | 566 | __le16 fc = hdr->frame_control; |
fd4abac5 TW |
567 | __le32 tx_flags = tx_cmd->tx_flags; |
568 | ||
569 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
e039fa4a | 570 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
fd4abac5 | 571 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 572 | if (ieee80211_is_mgmt(fc)) |
fd4abac5 | 573 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 574 | if (ieee80211_is_probe_resp(fc) && |
fd4abac5 TW |
575 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
576 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
577 | } else { | |
578 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
579 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
580 | } | |
581 | ||
fd7c8a40 | 582 | if (ieee80211_is_back_req(fc)) |
fd4abac5 TW |
583 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; |
584 | ||
585 | ||
586 | tx_cmd->sta_id = std_id; | |
8b7b1e05 | 587 | if (ieee80211_has_morefrags(fc)) |
fd4abac5 TW |
588 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
589 | ||
fd7c8a40 HH |
590 | if (ieee80211_is_data_qos(fc)) { |
591 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
fd4abac5 TW |
592 | tx_cmd->tid_tspec = qc[0] & 0xf; |
593 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
594 | } else { | |
595 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
596 | } | |
597 | ||
a326a5d0 | 598 | priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags); |
fd4abac5 TW |
599 | |
600 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
601 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
602 | ||
603 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
604 | if (ieee80211_is_mgmt(fc)) { |
605 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
fd4abac5 TW |
606 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
607 | else | |
608 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
609 | } else { | |
610 | tx_cmd->timeout.pm_frame_timeout = 0; | |
611 | } | |
612 | ||
613 | tx_cmd->driver_txop = 0; | |
614 | tx_cmd->tx_flags = tx_flags; | |
615 | tx_cmd->next_frame_len = 0; | |
616 | } | |
617 | ||
618 | #define RTS_HCCA_RETRY_LIMIT 3 | |
619 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
620 | ||
621 | static void iwl_tx_cmd_build_rate(struct iwl_priv *priv, | |
622 | struct iwl_tx_cmd *tx_cmd, | |
e039fa4a | 623 | struct ieee80211_tx_info *info, |
b58ef214 | 624 | __le16 fc, int is_hcca) |
fd4abac5 | 625 | { |
b58ef214 | 626 | u32 rate_flags; |
76eff18b | 627 | int rate_idx; |
b58ef214 DH |
628 | u8 rts_retry_limit; |
629 | u8 data_retry_limit; | |
fd4abac5 | 630 | u8 rate_plcp; |
2e92e6f2 | 631 | |
b58ef214 | 632 | /* Set retry limit on DATA packets and Probe Responses*/ |
1f0436f4 | 633 | if (ieee80211_is_probe_resp(fc)) |
b58ef214 DH |
634 | data_retry_limit = 3; |
635 | else | |
636 | data_retry_limit = IWL_DEFAULT_TX_RETRY; | |
637 | tx_cmd->data_retry_limit = data_retry_limit; | |
fd4abac5 | 638 | |
b58ef214 DH |
639 | /* Set retry limit on RTS packets */ |
640 | rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT : | |
641 | RTS_DFAULT_RETRY_LIMIT; | |
642 | if (data_retry_limit < rts_retry_limit) | |
643 | rts_retry_limit = data_retry_limit; | |
644 | tx_cmd->rts_retry_limit = rts_retry_limit; | |
fd4abac5 | 645 | |
b58ef214 DH |
646 | /* DATA packets will use the uCode station table for rate/antenna |
647 | * selection */ | |
fd4abac5 TW |
648 | if (ieee80211_is_data(fc)) { |
649 | tx_cmd->initial_rate_index = 0; | |
650 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
b58ef214 DH |
651 | return; |
652 | } | |
653 | ||
654 | /** | |
655 | * If the current TX rate stored in mac80211 has the MCS bit set, it's | |
656 | * not really a TX rate. Thus, we use the lowest supported rate for | |
657 | * this band. Also use the lowest supported rate if the stored rate | |
658 | * index is invalid. | |
659 | */ | |
660 | rate_idx = info->control.rates[0].idx; | |
661 | if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS || | |
662 | (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY)) | |
663 | rate_idx = rate_lowest_index(&priv->bands[info->band], | |
664 | info->control.sta); | |
665 | /* For 5 GHZ band, remap mac80211 rate indices into driver indices */ | |
666 | if (info->band == IEEE80211_BAND_5GHZ) | |
667 | rate_idx += IWL_FIRST_OFDM_RATE; | |
668 | /* Get PLCP rate for tx_cmd->rate_n_flags */ | |
669 | rate_plcp = iwl_rates[rate_idx].plcp; | |
670 | /* Zero out flags for this packet */ | |
671 | rate_flags = 0; | |
fd4abac5 | 672 | |
b58ef214 DH |
673 | /* Set CCK flag as needed */ |
674 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) | |
675 | rate_flags |= RATE_MCS_CCK_MSK; | |
676 | ||
677 | /* Set up RTS and CTS flags for certain packets */ | |
678 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
679 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
680 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
681 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
682 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
683 | if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) { | |
684 | tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
685 | tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK; | |
686 | } | |
687 | break; | |
688 | default: | |
689 | break; | |
fd4abac5 TW |
690 | } |
691 | ||
b58ef214 DH |
692 | /* Set up antennas */ |
693 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant); | |
694 | rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant); | |
695 | ||
696 | /* Set the rate in the TX cmd */ | |
e7d326ac | 697 | tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags); |
fd4abac5 TW |
698 | } |
699 | ||
700 | static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv, | |
e039fa4a | 701 | struct ieee80211_tx_info *info, |
fd4abac5 TW |
702 | struct iwl_tx_cmd *tx_cmd, |
703 | struct sk_buff *skb_frag, | |
704 | int sta_id) | |
705 | { | |
e039fa4a | 706 | struct ieee80211_key_conf *keyconf = info->control.hw_key; |
fd4abac5 | 707 | |
ccc038ab | 708 | switch (keyconf->alg) { |
fd4abac5 TW |
709 | case ALG_CCMP: |
710 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; | |
ccc038ab | 711 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); |
e039fa4a | 712 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
fd4abac5 | 713 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; |
e1623446 | 714 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
fd4abac5 TW |
715 | break; |
716 | ||
717 | case ALG_TKIP: | |
718 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; | |
ccc038ab | 719 | ieee80211_get_tkip_key(keyconf, skb_frag, |
fd4abac5 | 720 | IEEE80211_TKIP_P2_KEY, tx_cmd->key); |
e1623446 | 721 | IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n"); |
fd4abac5 TW |
722 | break; |
723 | ||
724 | case ALG_WEP: | |
fd4abac5 | 725 | tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP | |
ccc038ab EG |
726 | (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT); |
727 | ||
728 | if (keyconf->keylen == WEP_KEY_LEN_128) | |
729 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
730 | ||
731 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); | |
fd4abac5 | 732 | |
e1623446 | 733 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
ccc038ab | 734 | "with key %d\n", keyconf->keyidx); |
fd4abac5 TW |
735 | break; |
736 | ||
737 | default: | |
978785a3 | 738 | IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg); |
fd4abac5 TW |
739 | break; |
740 | } | |
741 | } | |
742 | ||
fd4abac5 TW |
743 | /* |
744 | * start REPLY_TX command process | |
745 | */ | |
e039fa4a | 746 | int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
fd4abac5 TW |
747 | { |
748 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 749 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
6ab10ff8 JB |
750 | struct ieee80211_sta *sta = info->control.sta; |
751 | struct iwl_station_priv *sta_priv = NULL; | |
f3674227 TW |
752 | struct iwl_tx_queue *txq; |
753 | struct iwl_queue *q; | |
c2acea8e JB |
754 | struct iwl_device_cmd *out_cmd; |
755 | struct iwl_cmd_meta *out_meta; | |
f3674227 TW |
756 | struct iwl_tx_cmd *tx_cmd; |
757 | int swq_id, txq_id; | |
fd4abac5 TW |
758 | dma_addr_t phys_addr; |
759 | dma_addr_t txcmd_phys; | |
760 | dma_addr_t scratch_phys; | |
be1a71a1 | 761 | u16 len, len_org, firstlen, secondlen; |
fd4abac5 | 762 | u16 seq_number = 0; |
fd7c8a40 | 763 | __le16 fc; |
0e7690f1 | 764 | u8 hdr_len; |
f3674227 | 765 | u8 sta_id; |
fd4abac5 TW |
766 | u8 wait_write_ptr = 0; |
767 | u8 tid = 0; | |
768 | u8 *qc = NULL; | |
769 | unsigned long flags; | |
fd4abac5 TW |
770 | |
771 | spin_lock_irqsave(&priv->lock, flags); | |
772 | if (iwl_is_rfkill(priv)) { | |
e1623446 | 773 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
fd4abac5 TW |
774 | goto drop_unlock; |
775 | } | |
776 | ||
fd7c8a40 | 777 | fc = hdr->frame_control; |
fd4abac5 TW |
778 | |
779 | #ifdef CONFIG_IWLWIFI_DEBUG | |
780 | if (ieee80211_is_auth(fc)) | |
e1623446 | 781 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 782 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 783 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 784 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 785 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
fd4abac5 TW |
786 | #endif |
787 | ||
aa065263 | 788 | /* drop all non-injected data frame if we are not associated */ |
fd7c8a40 | 789 | if (ieee80211_is_data(fc) && |
aa065263 | 790 | !(info->flags & IEEE80211_TX_CTL_INJECTED) && |
d10c4ec8 | 791 | (!iwl_is_associated(priv) || |
05c914fe | 792 | ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) || |
d10c4ec8 | 793 | !priv->assoc_station_added)) { |
e1623446 | 794 | IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n"); |
fd4abac5 TW |
795 | goto drop_unlock; |
796 | } | |
797 | ||
7294ec95 | 798 | hdr_len = ieee80211_hdrlen(fc); |
fd4abac5 TW |
799 | |
800 | /* Find (or create) index into station table for destination station */ | |
aa065263 GS |
801 | if (info->flags & IEEE80211_TX_CTL_INJECTED) |
802 | sta_id = priv->hw_params.bcast_sta_id; | |
803 | else | |
804 | sta_id = iwl_get_sta_id(priv, hdr); | |
fd4abac5 | 805 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 806 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 807 | hdr->addr1); |
3995bd93 | 808 | goto drop_unlock; |
fd4abac5 TW |
809 | } |
810 | ||
e1623446 | 811 | IWL_DEBUG_TX(priv, "station Id %d\n", sta_id); |
fd4abac5 | 812 | |
6ab10ff8 JB |
813 | if (sta) |
814 | sta_priv = (void *)sta->drv_priv; | |
815 | ||
816 | if (sta_priv && sta_id != priv->hw_params.bcast_sta_id && | |
817 | sta_priv->asleep) { | |
818 | WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)); | |
819 | /* | |
820 | * This sends an asynchronous command to the device, | |
821 | * but we can rely on it being processed before the | |
822 | * next frame is processed -- and the next frame to | |
823 | * this station is the one that will consume this | |
824 | * counter. | |
825 | * For now set the counter to just 1 since we do not | |
826 | * support uAPSD yet. | |
827 | */ | |
828 | iwl_sta_modify_sleep_tx_count(priv, sta_id, 1); | |
829 | } | |
830 | ||
45af8195 | 831 | txq_id = skb_get_queue_mapping(skb); |
fd7c8a40 HH |
832 | if (ieee80211_is_data_qos(fc)) { |
833 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 834 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
e6a6cf4c RC |
835 | if (unlikely(tid >= MAX_TID_COUNT)) |
836 | goto drop_unlock; | |
f3674227 TW |
837 | seq_number = priv->stations[sta_id].tid[tid].seq_number; |
838 | seq_number &= IEEE80211_SCTL_SEQ; | |
839 | hdr->seq_ctrl = hdr->seq_ctrl & | |
c1b4aa3f | 840 | cpu_to_le16(IEEE80211_SCTL_FRAG); |
f3674227 | 841 | hdr->seq_ctrl |= cpu_to_le16(seq_number); |
fd4abac5 | 842 | seq_number += 0x10; |
fd4abac5 | 843 | /* aggregation is on for this <sta,tid> */ |
45d42700 WYG |
844 | if (info->flags & IEEE80211_TX_CTL_AMPDU && |
845 | priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) { | |
fd4abac5 | 846 | txq_id = priv->stations[sta_id].tid[tid].agg.txq_id; |
45d42700 | 847 | } |
fd4abac5 TW |
848 | } |
849 | ||
fd4abac5 | 850 | txq = &priv->txq[txq_id]; |
45af8195 | 851 | swq_id = txq->swq_id; |
fd4abac5 TW |
852 | q = &txq->q; |
853 | ||
3995bd93 JB |
854 | if (unlikely(iwl_queue_space(q) < q->high_mark)) |
855 | goto drop_unlock; | |
856 | ||
857 | if (ieee80211_is_data_qos(fc)) | |
858 | priv->stations[sta_id].tid[tid].tfds_in_queue++; | |
fd4abac5 | 859 | |
fd4abac5 TW |
860 | /* Set up driver data for this TFD */ |
861 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); | |
862 | txq->txb[q->write_ptr].skb[0] = skb; | |
fd4abac5 TW |
863 | |
864 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
b88b15df | 865 | out_cmd = txq->cmd[q->write_ptr]; |
c2acea8e | 866 | out_meta = &txq->meta[q->write_ptr]; |
fd4abac5 TW |
867 | tx_cmd = &out_cmd->cmd.tx; |
868 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
869 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | |
870 | ||
871 | /* | |
872 | * Set up the Tx-command (not MAC!) header. | |
873 | * Store the chosen Tx queue and TFD index within the sequence field; | |
874 | * after Tx, uCode's Tx response will return this value so driver can | |
875 | * locate the frame within the tx queue and do post-tx processing. | |
876 | */ | |
877 | out_cmd->hdr.cmd = REPLY_TX; | |
878 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
879 | INDEX_TO_SEQ(q->write_ptr))); | |
880 | ||
881 | /* Copy MAC header from skb into command buffer */ | |
882 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
883 | ||
df833b1d RC |
884 | |
885 | /* Total # bytes to be transmitted */ | |
886 | len = (u16)skb->len; | |
887 | tx_cmd->len = cpu_to_le16(len); | |
888 | ||
889 | if (info->control.hw_key) | |
890 | iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); | |
891 | ||
892 | /* TODO need this for burst mode later on */ | |
893 | iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id); | |
20594eb0 | 894 | iwl_dbg_log_tx_data_frame(priv, len, hdr); |
df833b1d RC |
895 | |
896 | /* set is_hcca to 0; it probably will never be implemented */ | |
b58ef214 | 897 | iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0); |
df833b1d | 898 | |
22fdf3c9 | 899 | iwl_update_stats(priv, true, fc, len); |
fd4abac5 TW |
900 | /* |
901 | * Use the first empty entry in this queue's command buffer array | |
902 | * to contain the Tx command and MAC header concatenated together | |
903 | * (payload data will be in another buffer). | |
904 | * Size of this varies, due to varying MAC header length. | |
905 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
906 | * of the MAC header (device reads on dword boundaries). | |
907 | * We'll tell device about this padding later. | |
908 | */ | |
909 | len = sizeof(struct iwl_tx_cmd) + | |
910 | sizeof(struct iwl_cmd_header) + hdr_len; | |
911 | ||
912 | len_org = len; | |
be1a71a1 | 913 | firstlen = len = (len + 3) & ~3; |
fd4abac5 TW |
914 | |
915 | if (len_org != len) | |
916 | len_org = 1; | |
917 | else | |
918 | len_org = 0; | |
919 | ||
df833b1d RC |
920 | /* Tell NIC about any 2-byte padding after MAC header */ |
921 | if (len_org) | |
922 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
923 | ||
fd4abac5 TW |
924 | /* Physical address of this Tx command's header (not MAC header!), |
925 | * within command buffer array. */ | |
499b1883 | 926 | txcmd_phys = pci_map_single(priv->pci_dev, |
df833b1d | 927 | &out_cmd->hdr, len, |
96891cee | 928 | PCI_DMA_BIDIRECTIONAL); |
c2acea8e JB |
929 | pci_unmap_addr_set(out_meta, mapping, txcmd_phys); |
930 | pci_unmap_len_set(out_meta, len, len); | |
fd4abac5 TW |
931 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
932 | * first entry */ | |
7aaa1d79 SO |
933 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
934 | txcmd_phys, len, 1, 0); | |
fd4abac5 | 935 | |
df833b1d RC |
936 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
937 | txq->need_update = 1; | |
938 | if (qc) | |
939 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | |
940 | } else { | |
941 | wait_write_ptr = 1; | |
942 | txq->need_update = 0; | |
943 | } | |
fd4abac5 TW |
944 | |
945 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
946 | * if any (802.11 null frames have no payload). */ | |
be1a71a1 | 947 | secondlen = len = skb->len - hdr_len; |
fd4abac5 TW |
948 | if (len) { |
949 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
950 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
951 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
952 | phys_addr, len, | |
953 | 0, 0); | |
fd4abac5 TW |
954 | } |
955 | ||
fd4abac5 | 956 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
df833b1d RC |
957 | offsetof(struct iwl_tx_cmd, scratch); |
958 | ||
959 | len = sizeof(struct iwl_tx_cmd) + | |
960 | sizeof(struct iwl_cmd_header) + hdr_len; | |
961 | /* take back ownership of DMA buffer to enable update */ | |
962 | pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys, | |
963 | len, PCI_DMA_BIDIRECTIONAL); | |
fd4abac5 | 964 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); |
499b1883 | 965 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); |
fd4abac5 | 966 | |
d2ee9cd2 RC |
967 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n", |
968 | le16_to_cpu(out_cmd->hdr.sequence)); | |
969 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags)); | |
3d816c77 RC |
970 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); |
971 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
fd4abac5 TW |
972 | |
973 | /* Set up entry for this TFD in Tx byte-count array */ | |
7b80ece4 RC |
974 | if (info->flags & IEEE80211_TX_CTL_AMPDU) |
975 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, | |
df833b1d RC |
976 | le16_to_cpu(tx_cmd->len)); |
977 | ||
978 | pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys, | |
979 | len, PCI_DMA_BIDIRECTIONAL); | |
fd4abac5 | 980 | |
be1a71a1 JB |
981 | trace_iwlwifi_dev_tx(priv, |
982 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], | |
983 | sizeof(struct iwl_tfd), | |
984 | &out_cmd->hdr, firstlen, | |
985 | skb->data + hdr_len, secondlen); | |
986 | ||
fd4abac5 TW |
987 | /* Tell device the write index *just past* this latest filled TFD */ |
988 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
7bfedc59 | 989 | iwl_txq_update_write_ptr(priv, txq); |
fd4abac5 TW |
990 | spin_unlock_irqrestore(&priv->lock, flags); |
991 | ||
6ab10ff8 JB |
992 | /* |
993 | * At this point the frame is "transmitted" successfully | |
994 | * and we will get a TX status notification eventually, | |
995 | * regardless of the value of ret. "ret" only indicates | |
996 | * whether or not we should update the write pointer. | |
997 | */ | |
998 | ||
999 | /* avoid atomic ops if it isn't an associated client */ | |
1000 | if (sta_priv && sta_priv->client) | |
1001 | atomic_inc(&sta_priv->pending_frames); | |
1002 | ||
143b09ef | 1003 | if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) { |
fd4abac5 TW |
1004 | if (wait_write_ptr) { |
1005 | spin_lock_irqsave(&priv->lock, flags); | |
1006 | txq->need_update = 1; | |
1007 | iwl_txq_update_write_ptr(priv, txq); | |
1008 | spin_unlock_irqrestore(&priv->lock, flags); | |
143b09ef | 1009 | } else { |
e4e72fb4 | 1010 | iwl_stop_queue(priv, txq->swq_id); |
fd4abac5 | 1011 | } |
fd4abac5 TW |
1012 | } |
1013 | ||
1014 | return 0; | |
1015 | ||
1016 | drop_unlock: | |
1017 | spin_unlock_irqrestore(&priv->lock, flags); | |
fd4abac5 TW |
1018 | return -1; |
1019 | } | |
1020 | EXPORT_SYMBOL(iwl_tx_skb); | |
1021 | ||
1022 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
1023 | ||
1024 | /** | |
1025 | * iwl_enqueue_hcmd - enqueue a uCode command | |
1026 | * @priv: device private data point | |
1027 | * @cmd: a point to the ucode command structure | |
1028 | * | |
1029 | * The function returns < 0 values to indicate the operation is | |
1030 | * failed. On success, it turns the index (> 0) of command in the | |
1031 | * command queue. | |
1032 | */ | |
1033 | int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |
1034 | { | |
1035 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; | |
1036 | struct iwl_queue *q = &txq->q; | |
c2acea8e JB |
1037 | struct iwl_device_cmd *out_cmd; |
1038 | struct iwl_cmd_meta *out_meta; | |
fd4abac5 | 1039 | dma_addr_t phys_addr; |
fd4abac5 | 1040 | unsigned long flags; |
7bfedc59 | 1041 | int len; |
f3674227 TW |
1042 | u32 idx; |
1043 | u16 fix_size; | |
fd4abac5 TW |
1044 | |
1045 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
1046 | fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr)); | |
1047 | ||
1048 | /* If any of the command structures end up being larger than | |
1049 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
89612124 AK |
1050 | * we will need to increase the size of the TFD entries |
1051 | * Also, check to see if command buffer should not exceed the size | |
1052 | * of device_cmd and max_cmd_size. */ | |
fd4abac5 | 1053 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && |
c2acea8e | 1054 | !(cmd->flags & CMD_SIZE_HUGE)); |
89612124 | 1055 | BUG_ON(fix_size > IWL_MAX_CMD_SIZE); |
fd4abac5 | 1056 | |
7812b167 | 1057 | if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) { |
f2f21b49 RC |
1058 | IWL_WARN(priv, "Not sending command - %s KILL\n", |
1059 | iwl_is_rfkill(priv) ? "RF" : "CT"); | |
fd4abac5 TW |
1060 | return -EIO; |
1061 | } | |
1062 | ||
c2acea8e | 1063 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
2d237f71 | 1064 | IWL_ERR(priv, "No space in command queue\n"); |
7812b167 WYG |
1065 | if (iwl_within_ct_kill_margin(priv)) |
1066 | iwl_tt_enter_ct_kill(priv); | |
1067 | else { | |
1068 | IWL_ERR(priv, "Restarting adapter due to queue full\n"); | |
1069 | queue_work(priv->workqueue, &priv->restart); | |
1070 | } | |
fd4abac5 TW |
1071 | return -ENOSPC; |
1072 | } | |
1073 | ||
1074 | spin_lock_irqsave(&priv->hcmd_lock, flags); | |
1075 | ||
dd487449 ZY |
1076 | /* If this is a huge cmd, mark the huge flag also on the meta.flags |
1077 | * of the _original_ cmd. This is used for DMA mapping clean up. | |
1078 | */ | |
1079 | if (cmd->flags & CMD_SIZE_HUGE) { | |
1080 | idx = get_cmd_index(q, q->write_ptr, 0); | |
1081 | txq->meta[idx].flags = CMD_SIZE_HUGE; | |
1082 | } | |
1083 | ||
c2acea8e | 1084 | idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); |
da99c4b6 | 1085 | out_cmd = txq->cmd[idx]; |
c2acea8e JB |
1086 | out_meta = &txq->meta[idx]; |
1087 | ||
8ce73f3a | 1088 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1089 | out_meta->flags = cmd->flags; |
1090 | if (cmd->flags & CMD_WANT_SKB) | |
1091 | out_meta->source = cmd; | |
1092 | if (cmd->flags & CMD_ASYNC) | |
1093 | out_meta->callback = cmd->callback; | |
fd4abac5 TW |
1094 | |
1095 | out_cmd->hdr.cmd = cmd->id; | |
fd4abac5 TW |
1096 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); |
1097 | ||
1098 | /* At this point, the out_cmd now has all of the incoming cmd | |
1099 | * information */ | |
1100 | ||
1101 | out_cmd->hdr.flags = 0; | |
1102 | out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) | | |
1103 | INDEX_TO_SEQ(q->write_ptr)); | |
c2acea8e | 1104 | if (cmd->flags & CMD_SIZE_HUGE) |
9734cb23 | 1105 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; |
c2acea8e | 1106 | len = sizeof(struct iwl_device_cmd); |
89612124 AK |
1107 | if (idx == TFD_CMD_SLOTS) |
1108 | len = IWL_MAX_CMD_SIZE; | |
fd4abac5 | 1109 | |
ded2ae7c EK |
1110 | #ifdef CONFIG_IWLWIFI_DEBUG |
1111 | switch (out_cmd->hdr.cmd) { | |
1112 | case REPLY_TX_LINK_QUALITY_CMD: | |
1113 | case SENSITIVITY_CMD: | |
e1623446 | 1114 | IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
1115 | "%d bytes at %d[%d]:%d\n", |
1116 | get_cmd_string(out_cmd->hdr.cmd), | |
1117 | out_cmd->hdr.cmd, | |
1118 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
1119 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1120 | break; | |
1121 | default: | |
e1623446 | 1122 | IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, " |
ded2ae7c EK |
1123 | "%d bytes at %d[%d]:%d\n", |
1124 | get_cmd_string(out_cmd->hdr.cmd), | |
1125 | out_cmd->hdr.cmd, | |
1126 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
1127 | q->write_ptr, idx, IWL_CMD_QUEUE_NUM); | |
1128 | } | |
1129 | #endif | |
fd4abac5 TW |
1130 | txq->need_update = 1; |
1131 | ||
518099a8 SO |
1132 | if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl) |
1133 | /* Set up entry in queue's byte count circular buffer */ | |
1134 | priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); | |
fd4abac5 | 1135 | |
df833b1d RC |
1136 | phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
1137 | fix_size, PCI_DMA_BIDIRECTIONAL); | |
c2acea8e JB |
1138 | pci_unmap_addr_set(out_meta, mapping, phys_addr); |
1139 | pci_unmap_len_set(out_meta, len, fix_size); | |
df833b1d | 1140 | |
be1a71a1 JB |
1141 | trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags); |
1142 | ||
df833b1d RC |
1143 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
1144 | phys_addr, fix_size, 1, | |
1145 | U32_PAD(cmd->len)); | |
1146 | ||
fd4abac5 TW |
1147 | /* Increment and update queue's write index */ |
1148 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
7bfedc59 | 1149 | iwl_txq_update_write_ptr(priv, txq); |
fd4abac5 TW |
1150 | |
1151 | spin_unlock_irqrestore(&priv->hcmd_lock, flags); | |
7bfedc59 | 1152 | return idx; |
fd4abac5 TW |
1153 | } |
1154 | ||
6ab10ff8 JB |
1155 | static void iwl_tx_status(struct iwl_priv *priv, struct sk_buff *skb) |
1156 | { | |
1157 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1158 | struct ieee80211_sta *sta; | |
1159 | struct iwl_station_priv *sta_priv; | |
1160 | ||
1161 | sta = ieee80211_find_sta(priv->vif, hdr->addr1); | |
1162 | if (sta) { | |
1163 | sta_priv = (void *)sta->drv_priv; | |
1164 | /* avoid atomic ops if this isn't a client */ | |
1165 | if (sta_priv->client && | |
1166 | atomic_dec_return(&sta_priv->pending_frames) == 0) | |
1167 | ieee80211_sta_block_awake(priv->hw, sta, false); | |
1168 | } | |
1169 | ||
1170 | ieee80211_tx_status_irqsafe(priv->hw, skb); | |
1171 | } | |
1172 | ||
17b88929 TW |
1173 | int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) |
1174 | { | |
1175 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1176 | struct iwl_queue *q = &txq->q; | |
1177 | struct iwl_tx_info *tx_info; | |
1178 | int nfreed = 0; | |
a120e912 | 1179 | struct ieee80211_hdr *hdr; |
17b88929 TW |
1180 | |
1181 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | |
15b1687c | 1182 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 TW |
1183 | "is out of range [0-%d] %d %d.\n", txq_id, |
1184 | index, q->n_bd, q->write_ptr, q->read_ptr); | |
1185 | return 0; | |
1186 | } | |
1187 | ||
499b1883 TW |
1188 | for (index = iwl_queue_inc_wrap(index, q->n_bd); |
1189 | q->read_ptr != index; | |
1190 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 TW |
1191 | |
1192 | tx_info = &txq->txb[txq->q.read_ptr]; | |
6ab10ff8 | 1193 | iwl_tx_status(priv, tx_info->skb[0]); |
a120e912 SG |
1194 | |
1195 | hdr = (struct ieee80211_hdr *)tx_info->skb[0]->data; | |
1196 | if (hdr && ieee80211_is_data_qos(hdr->frame_control)) | |
1197 | nfreed++; | |
17b88929 | 1198 | tx_info->skb[0] = NULL; |
17b88929 | 1199 | |
972cf447 TW |
1200 | if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl) |
1201 | priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq); | |
1202 | ||
7aaa1d79 | 1203 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
17b88929 TW |
1204 | } |
1205 | return nfreed; | |
1206 | } | |
1207 | EXPORT_SYMBOL(iwl_tx_queue_reclaim); | |
1208 | ||
1209 | ||
1210 | /** | |
1211 | * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
1212 | * | |
1213 | * When FW advances 'R' index, all entries between old and new 'R' index | |
1214 | * need to be reclaimed. As result, some free space forms. If there is | |
1215 | * enough free space (> low mark), wake the stack that feeds us. | |
1216 | */ | |
499b1883 TW |
1217 | static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, |
1218 | int idx, int cmd_idx) | |
17b88929 TW |
1219 | { |
1220 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1221 | struct iwl_queue *q = &txq->q; | |
1222 | int nfreed = 0; | |
1223 | ||
499b1883 | 1224 | if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { |
15b1687c | 1225 | IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " |
17b88929 | 1226 | "is out of range [0-%d] %d %d.\n", txq_id, |
499b1883 | 1227 | idx, q->n_bd, q->write_ptr, q->read_ptr); |
17b88929 TW |
1228 | return; |
1229 | } | |
1230 | ||
499b1883 TW |
1231 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
1232 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
17b88929 | 1233 | |
499b1883 | 1234 | if (nfreed++ > 0) { |
15b1687c | 1235 | IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx, |
17b88929 TW |
1236 | q->write_ptr, q->read_ptr); |
1237 | queue_work(priv->workqueue, &priv->restart); | |
1238 | } | |
da99c4b6 | 1239 | |
17b88929 TW |
1240 | } |
1241 | } | |
1242 | ||
1243 | /** | |
1244 | * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
1245 | * @rxb: Rx buffer to reclaim | |
1246 | * | |
1247 | * If an Rx buffer has an async callback associated with it the callback | |
1248 | * will be executed. The attached skb (if present) will only be freed | |
1249 | * if the callback returns 1 | |
1250 | */ | |
1251 | void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |
1252 | { | |
2f301227 | 1253 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1254 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1255 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1256 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1257 | int cmd_index; |
9734cb23 | 1258 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); |
c2acea8e JB |
1259 | struct iwl_device_cmd *cmd; |
1260 | struct iwl_cmd_meta *meta; | |
dd487449 | 1261 | struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM]; |
17b88929 TW |
1262 | |
1263 | /* If a Tx command is being handled and it isn't in the actual | |
1264 | * command queue then there a command routing bug has been introduced | |
1265 | * in the queue management code. */ | |
55d6a3cd | 1266 | if (WARN(txq_id != IWL_CMD_QUEUE_NUM, |
01ef9323 WT |
1267 | "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n", |
1268 | txq_id, sequence, | |
1269 | priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr, | |
1270 | priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) { | |
ec741164 | 1271 | iwl_print_hex_error(priv, pkt, 32); |
55d6a3cd | 1272 | return; |
01ef9323 | 1273 | } |
17b88929 | 1274 | |
dd487449 ZY |
1275 | /* If this is a huge cmd, clear the huge flag on the meta.flags |
1276 | * of the _original_ cmd. So that iwl_cmd_queue_free won't unmap | |
1277 | * the DMA buffer for the scan (huge) command. | |
1278 | */ | |
1279 | if (huge) { | |
1280 | cmd_index = get_cmd_index(&txq->q, index, 0); | |
1281 | txq->meta[cmd_index].flags = 0; | |
1282 | } | |
1283 | cmd_index = get_cmd_index(&txq->q, index, huge); | |
1284 | cmd = txq->cmd[cmd_index]; | |
1285 | meta = &txq->meta[cmd_index]; | |
17b88929 | 1286 | |
c33de625 RC |
1287 | pci_unmap_single(priv->pci_dev, |
1288 | pci_unmap_addr(meta, mapping), | |
1289 | pci_unmap_len(meta, len), | |
1290 | PCI_DMA_BIDIRECTIONAL); | |
1291 | ||
17b88929 | 1292 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1293 | if (meta->flags & CMD_WANT_SKB) { |
2f301227 ZY |
1294 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); |
1295 | rxb->page = NULL; | |
5696aea6 | 1296 | } else if (meta->callback) |
2f301227 | 1297 | meta->callback(priv, cmd, pkt); |
17b88929 | 1298 | |
499b1883 | 1299 | iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index); |
17b88929 | 1300 | |
c2acea8e | 1301 | if (!(meta->flags & CMD_ASYNC)) { |
17b88929 | 1302 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); |
d2dfe6df RC |
1303 | IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s \n", |
1304 | get_cmd_string(cmd->hdr.cmd)); | |
17b88929 TW |
1305 | wake_up_interruptible(&priv->wait_command_queue); |
1306 | } | |
dd487449 | 1307 | meta->flags = 0; |
17b88929 TW |
1308 | } |
1309 | EXPORT_SYMBOL(iwl_tx_cmd_complete); | |
1310 | ||
30e553e3 TW |
1311 | /* |
1312 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
1313 | * Called only when finding queue for aggregation. | |
1314 | * Should never return anything < 7, because they should already | |
1315 | * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6). | |
1316 | */ | |
1317 | static int iwl_txq_ctx_activate_free(struct iwl_priv *priv) | |
1318 | { | |
1319 | int txq_id; | |
1320 | ||
1321 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | |
1322 | if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk)) | |
1323 | return txq_id; | |
1324 | return -1; | |
1325 | } | |
1326 | ||
1327 | int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn) | |
1328 | { | |
1329 | int sta_id; | |
1330 | int tx_fifo; | |
1331 | int txq_id; | |
1332 | int ret; | |
1333 | unsigned long flags; | |
1334 | struct iwl_tid_data *tid_data; | |
30e553e3 TW |
1335 | |
1336 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
1337 | tx_fifo = default_tid_to_tx_fifo[tid]; | |
1338 | else | |
1339 | return -EINVAL; | |
1340 | ||
39aadf8c | 1341 | IWL_WARN(priv, "%s on ra = %pM tid = %d\n", |
e174961c | 1342 | __func__, ra, tid); |
30e553e3 TW |
1343 | |
1344 | sta_id = iwl_find_station(priv, ra); | |
3eb92969 WYG |
1345 | if (sta_id == IWL_INVALID_STATION) { |
1346 | IWL_ERR(priv, "Start AGG on invalid station\n"); | |
30e553e3 | 1347 | return -ENXIO; |
3eb92969 | 1348 | } |
082e708a RK |
1349 | if (unlikely(tid >= MAX_TID_COUNT)) |
1350 | return -EINVAL; | |
30e553e3 TW |
1351 | |
1352 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { | |
15b1687c | 1353 | IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n"); |
30e553e3 TW |
1354 | return -ENXIO; |
1355 | } | |
1356 | ||
1357 | txq_id = iwl_txq_ctx_activate_free(priv); | |
3eb92969 WYG |
1358 | if (txq_id == -1) { |
1359 | IWL_ERR(priv, "No free aggregation queue available\n"); | |
30e553e3 | 1360 | return -ENXIO; |
3eb92969 | 1361 | } |
30e553e3 TW |
1362 | |
1363 | spin_lock_irqsave(&priv->sta_lock, flags); | |
1364 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1365 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
1366 | tid_data->agg.txq_id = txq_id; | |
45af8195 | 1367 | priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id); |
30e553e3 TW |
1368 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
1369 | ||
1370 | ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo, | |
1371 | sta_id, tid, *ssn); | |
1372 | if (ret) | |
1373 | return ret; | |
1374 | ||
1375 | if (tid_data->tfds_in_queue == 0) { | |
3eb92969 | 1376 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); |
30e553e3 | 1377 | tid_data->agg.state = IWL_AGG_ON; |
c951ad35 | 1378 | ieee80211_start_tx_ba_cb_irqsafe(priv->vif, ra, tid); |
30e553e3 | 1379 | } else { |
e1623446 | 1380 | IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n", |
30e553e3 TW |
1381 | tid_data->tfds_in_queue); |
1382 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
1383 | } | |
1384 | return ret; | |
1385 | } | |
1386 | EXPORT_SYMBOL(iwl_tx_agg_start); | |
1387 | ||
1388 | int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid) | |
1389 | { | |
1390 | int tx_fifo_id, txq_id, sta_id, ssn = -1; | |
1391 | struct iwl_tid_data *tid_data; | |
45d42700 | 1392 | int write_ptr, read_ptr; |
30e553e3 | 1393 | unsigned long flags; |
30e553e3 TW |
1394 | |
1395 | if (!ra) { | |
15b1687c | 1396 | IWL_ERR(priv, "ra = NULL\n"); |
30e553e3 TW |
1397 | return -EINVAL; |
1398 | } | |
1399 | ||
e6a6cf4c RC |
1400 | if (unlikely(tid >= MAX_TID_COUNT)) |
1401 | return -EINVAL; | |
1402 | ||
30e553e3 TW |
1403 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) |
1404 | tx_fifo_id = default_tid_to_tx_fifo[tid]; | |
1405 | else | |
1406 | return -EINVAL; | |
1407 | ||
1408 | sta_id = iwl_find_station(priv, ra); | |
1409 | ||
a2f1cbeb WYG |
1410 | if (sta_id == IWL_INVALID_STATION) { |
1411 | IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid); | |
30e553e3 | 1412 | return -ENXIO; |
a2f1cbeb | 1413 | } |
30e553e3 | 1414 | |
827d42c9 JB |
1415 | if (priv->stations[sta_id].tid[tid].agg.state == |
1416 | IWL_EMPTYING_HW_QUEUE_ADDBA) { | |
1417 | IWL_DEBUG_HT(priv, "AGG stop before setup done\n"); | |
9b1cb21c | 1418 | ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid); |
827d42c9 JB |
1419 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; |
1420 | return 0; | |
1421 | } | |
1422 | ||
30e553e3 | 1423 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON) |
827d42c9 | 1424 | IWL_WARN(priv, "Stopping AGG while state not ON or starting\n"); |
30e553e3 TW |
1425 | |
1426 | tid_data = &priv->stations[sta_id].tid[tid]; | |
1427 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
1428 | txq_id = tid_data->agg.txq_id; | |
1429 | write_ptr = priv->txq[txq_id].q.write_ptr; | |
1430 | read_ptr = priv->txq[txq_id].q.read_ptr; | |
1431 | ||
1432 | /* The queue is not empty */ | |
1433 | if (write_ptr != read_ptr) { | |
e1623446 | 1434 | IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n"); |
30e553e3 TW |
1435 | priv->stations[sta_id].tid[tid].agg.state = |
1436 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
1437 | return 0; | |
1438 | } | |
1439 | ||
e1623446 | 1440 | IWL_DEBUG_HT(priv, "HW queue is empty\n"); |
30e553e3 TW |
1441 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; |
1442 | ||
1443 | spin_lock_irqsave(&priv->lock, flags); | |
45d42700 WYG |
1444 | /* |
1445 | * the only reason this call can fail is queue number out of range, | |
1446 | * which can happen if uCode is reloaded and all the station | |
1447 | * information are lost. if it is outside the range, there is no need | |
1448 | * to deactivate the uCode queue, just return "success" to allow | |
1449 | * mac80211 to clean up it own data. | |
1450 | */ | |
1451 | priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn, | |
30e553e3 TW |
1452 | tx_fifo_id); |
1453 | spin_unlock_irqrestore(&priv->lock, flags); | |
1454 | ||
c951ad35 | 1455 | ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid); |
30e553e3 TW |
1456 | |
1457 | return 0; | |
1458 | } | |
1459 | EXPORT_SYMBOL(iwl_tx_agg_stop); | |
1460 | ||
1461 | int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id) | |
1462 | { | |
1463 | struct iwl_queue *q = &priv->txq[txq_id].q; | |
1464 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | |
1465 | struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid]; | |
1466 | ||
1467 | switch (priv->stations[sta_id].tid[tid].agg.state) { | |
1468 | case IWL_EMPTYING_HW_QUEUE_DELBA: | |
1469 | /* We are reclaiming the last packet of the */ | |
1470 | /* aggregated HW queue */ | |
3fd07a1e TW |
1471 | if ((txq_id == tid_data->agg.txq_id) && |
1472 | (q->read_ptr == q->write_ptr)) { | |
30e553e3 TW |
1473 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); |
1474 | int tx_fifo = default_tid_to_tx_fifo[tid]; | |
e1623446 | 1475 | IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n"); |
30e553e3 TW |
1476 | priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, |
1477 | ssn, tx_fifo); | |
1478 | tid_data->agg.state = IWL_AGG_OFF; | |
c951ad35 | 1479 | ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, addr, tid); |
30e553e3 TW |
1480 | } |
1481 | break; | |
1482 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
1483 | /* We are reclaiming the last packet of the queue */ | |
1484 | if (tid_data->tfds_in_queue == 0) { | |
e1623446 | 1485 | IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n"); |
30e553e3 | 1486 | tid_data->agg.state = IWL_AGG_ON; |
c951ad35 | 1487 | ieee80211_start_tx_ba_cb_irqsafe(priv->vif, addr, tid); |
30e553e3 TW |
1488 | } |
1489 | break; | |
1490 | } | |
1491 | return 0; | |
1492 | } | |
1493 | EXPORT_SYMBOL(iwl_txq_check_empty); | |
30e553e3 | 1494 | |
653fa4a0 EG |
1495 | /** |
1496 | * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack | |
1497 | * | |
1498 | * Go through block-ack's bitmap of ACK'd frames, update driver's record of | |
1499 | * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. | |
1500 | */ | |
1501 | static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv, | |
1502 | struct iwl_ht_agg *agg, | |
1503 | struct iwl_compressed_ba_resp *ba_resp) | |
1504 | ||
1505 | { | |
1506 | int i, sh, ack; | |
1507 | u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); | |
1508 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1509 | u64 bitmap; | |
1510 | int successes = 0; | |
1511 | struct ieee80211_tx_info *info; | |
1512 | ||
1513 | if (unlikely(!agg->wait_for_ba)) { | |
15b1687c | 1514 | IWL_ERR(priv, "Received BA when not expected\n"); |
653fa4a0 EG |
1515 | return -EINVAL; |
1516 | } | |
1517 | ||
1518 | /* Mark that the expected block-ack response arrived */ | |
1519 | agg->wait_for_ba = 0; | |
e1623446 | 1520 | IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); |
653fa4a0 EG |
1521 | |
1522 | /* Calculate shift to align block-ack bits with our Tx window bits */ | |
3fd07a1e | 1523 | sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4); |
653fa4a0 EG |
1524 | if (sh < 0) /* tbw something is wrong with indices */ |
1525 | sh += 0x100; | |
1526 | ||
1527 | /* don't use 64-bit values for now */ | |
1528 | bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; | |
1529 | ||
1530 | if (agg->frame_count > (64 - sh)) { | |
e1623446 | 1531 | IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size"); |
653fa4a0 EG |
1532 | return -1; |
1533 | } | |
1534 | ||
1535 | /* check for success or failure according to the | |
1536 | * transmitted bitmap and block-ack bitmap */ | |
1537 | bitmap &= agg->bitmap; | |
1538 | ||
1539 | /* For each frame attempted in aggregation, | |
1540 | * update driver's record of tx frame's status. */ | |
1541 | for (i = 0; i < agg->frame_count ; i++) { | |
4aa41f12 | 1542 | ack = bitmap & (1ULL << i); |
653fa4a0 | 1543 | successes += !!ack; |
e1623446 | 1544 | IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n", |
c3056065 | 1545 | ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff, |
653fa4a0 EG |
1546 | agg->start_idx + i); |
1547 | } | |
1548 | ||
1549 | info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]); | |
1550 | memset(&info->status, 0, sizeof(info->status)); | |
91a55ae6 | 1551 | info->flags |= IEEE80211_TX_STAT_ACK; |
653fa4a0 EG |
1552 | info->flags |= IEEE80211_TX_STAT_AMPDU; |
1553 | info->status.ampdu_ack_map = successes; | |
1554 | info->status.ampdu_ack_len = agg->frame_count; | |
1555 | iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info); | |
1556 | ||
e1623446 | 1557 | IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap); |
653fa4a0 EG |
1558 | |
1559 | return 0; | |
1560 | } | |
1561 | ||
1562 | /** | |
1563 | * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA | |
1564 | * | |
1565 | * Handles block-acknowledge notification from device, which reports success | |
1566 | * of frames sent via aggregation. | |
1567 | */ | |
1568 | void iwl_rx_reply_compressed_ba(struct iwl_priv *priv, | |
1569 | struct iwl_rx_mem_buffer *rxb) | |
1570 | { | |
2f301227 | 1571 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
653fa4a0 | 1572 | struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; |
653fa4a0 EG |
1573 | struct iwl_tx_queue *txq = NULL; |
1574 | struct iwl_ht_agg *agg; | |
3fd07a1e TW |
1575 | int index; |
1576 | int sta_id; | |
1577 | int tid; | |
653fa4a0 EG |
1578 | |
1579 | /* "flow" corresponds to Tx queue */ | |
1580 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
1581 | ||
1582 | /* "ssn" is start of block-ack Tx window, corresponds to index | |
1583 | * (in Tx queue's circular buffer) of first TFD/frame in window */ | |
1584 | u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); | |
1585 | ||
1586 | if (scd_flow >= priv->hw_params.max_txq_num) { | |
15b1687c WT |
1587 | IWL_ERR(priv, |
1588 | "BUG_ON scd_flow is bigger than number of queues\n"); | |
653fa4a0 EG |
1589 | return; |
1590 | } | |
1591 | ||
1592 | txq = &priv->txq[scd_flow]; | |
3fd07a1e TW |
1593 | sta_id = ba_resp->sta_id; |
1594 | tid = ba_resp->tid; | |
1595 | agg = &priv->stations[sta_id].tid[tid].agg; | |
653fa4a0 EG |
1596 | |
1597 | /* Find index just before block-ack window */ | |
1598 | index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); | |
1599 | ||
1600 | /* TODO: Need to get this copy more safely - now good for debug */ | |
1601 | ||
e1623446 | 1602 | IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, " |
653fa4a0 EG |
1603 | "sta_id = %d\n", |
1604 | agg->wait_for_ba, | |
e174961c | 1605 | (u8 *) &ba_resp->sta_addr_lo32, |
653fa4a0 | 1606 | ba_resp->sta_id); |
e1623446 | 1607 | IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = " |
653fa4a0 EG |
1608 | "%d, scd_ssn = %d\n", |
1609 | ba_resp->tid, | |
1610 | ba_resp->seq_ctl, | |
1611 | (unsigned long long)le64_to_cpu(ba_resp->bitmap), | |
1612 | ba_resp->scd_flow, | |
1613 | ba_resp->scd_ssn); | |
e1623446 | 1614 | IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n", |
653fa4a0 EG |
1615 | agg->start_idx, |
1616 | (unsigned long long)agg->bitmap); | |
1617 | ||
1618 | /* Update driver's record of ACK vs. not for each frame in window */ | |
1619 | iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp); | |
1620 | ||
1621 | /* Release all TFDs before the SSN, i.e. all TFDs in front of | |
1622 | * block-ack window (we assume that they've been successfully | |
1623 | * transmitted ... if not, it's too late anyway). */ | |
1624 | if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { | |
1625 | /* calculate mac80211 ampdu sw queue to wake */ | |
653fa4a0 | 1626 | int freed = iwl_tx_queue_reclaim(priv, scd_flow, index); |
a239a8b4 | 1627 | iwl_free_tfds_in_queue(priv, sta_id, tid, freed); |
3fd07a1e TW |
1628 | |
1629 | if ((iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1630 | priv->mac80211_registered && | |
1631 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) | |
e4e72fb4 | 1632 | iwl_wake_queue(priv, txq->swq_id); |
3fd07a1e TW |
1633 | |
1634 | iwl_txq_check_empty(priv, sta_id, tid, scd_flow); | |
653fa4a0 EG |
1635 | } |
1636 | } | |
1637 | EXPORT_SYMBOL(iwl_rx_reply_compressed_ba); | |
1638 | ||
994d31f7 | 1639 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 TW |
1640 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x |
1641 | ||
1642 | const char *iwl_get_tx_fail_reason(u32 status) | |
1643 | { | |
1644 | switch (status & TX_STATUS_MSK) { | |
1645 | case TX_STATUS_SUCCESS: | |
1646 | return "SUCCESS"; | |
1647 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
1648 | TX_STATUS_ENTRY(LONG_LIMIT); | |
1649 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
1650 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
1651 | TX_STATUS_ENTRY(NEXT_FRAG); | |
1652 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
1653 | TX_STATUS_ENTRY(DEST_PS); | |
1654 | TX_STATUS_ENTRY(ABORTED); | |
1655 | TX_STATUS_ENTRY(BT_RETRY); | |
1656 | TX_STATUS_ENTRY(STA_INVALID); | |
1657 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
1658 | TX_STATUS_ENTRY(TID_DISABLE); | |
1659 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
1660 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
1661 | TX_STATUS_ENTRY(TX_LOCKED); | |
1662 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
1663 | } | |
1664 | ||
1665 | return "UNKNOWN"; | |
1666 | } | |
1667 | EXPORT_SYMBOL(iwl_get_tx_fail_reason); | |
1668 | #endif /* CONFIG_IWLWIFI_DEBUG */ |