Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / iwl-trans.h
CommitLineData
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1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
8d193ca2 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
6b35ff91 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
700b3799 11 * Copyright(c) 2018 - 2019 Intel Corporation
c85eb619
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12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
c85eb619 22 * The full GNU General Public License is included in this distribution
410dc5aa 23 * in the file called COPYING.
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24 *
25 * Contact Information:
cb2f8277 26 * Intel Linux Wireless <linuxwifi@intel.com>
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27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
51368bf7 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
8d193ca2 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
6b35ff91 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
700b3799 34 * Copyright(c) 2018 - 2019 Intel Corporation
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35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *
63 *****************************************************************************/
41c50542
EG
64#ifndef __iwl_trans_h__
65#define __iwl_trans_h__
253a634c 66
e679378d 67#include <linux/ieee80211.h>
930dfd5f 68#include <linux/mm.h> /* for page_address */
2bfb5092 69#include <linux/lockdep.h>
39bdb17e 70#include <linux/kernel.h>
a72b8b08 71
69655ebf 72#include "iwl-debug.h"
6238b008 73#include "iwl-config.h"
d962f9b1 74#include "fw/img.h"
2a988e98 75#include "iwl-op-mode.h"
d172a5ef
JB
76#include "fw/api/cmdhdr.h"
77#include "fw/api/txq.h"
f14cda6f
SS
78#include "fw/api/dbg-tlv.h"
79#include "iwl-dbg-tlv.h"
87e5666c 80
60396183
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81/**
82 * DOC: Transport layer - what is it ?
83 *
0d365ae5 84 * The transport layer is the layer that deals with the HW directly. It provides
60396183
EG
85 * an abstraction of the underlying HW to the upper layer. The transport layer
86 * doesn't provide any policy, algorithm or anything of this kind, but only
0d365ae5 87 * mechanisms to make the HW do something. It is not completely stateless but
60396183
EG
88 * close to it.
89 * We will have an implementation for each different supported bus.
90 */
91
92/**
93 * DOC: Life cycle of the transport layer
94 *
95 * The transport layer has a very precise life cycle.
96 *
97 * 1) A helper function is called during the module initialization and
98 * registers the bus driver's ops with the transport's alloc function.
99 * 2) Bus's probe calls to the transport layer's allocation functions.
100 * Of course this function is bus specific.
101 * 3) This allocation functions will spawn the upper layer which will
102 * register mac80211.
103 *
104 * 4) At some point (i.e. mac80211's start call), the op_mode will call
105 * the following sequence:
106 * start_hw
107 * start_fw
108 *
109 * 5) Then when finished (or reset):
a4082843 110 * stop_device
60396183
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111 *
112 * 6) Eventually, the free function will be called.
113 */
114
f8d7c1a1 115#define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */
0c19744c
JB
116#define FH_RSCSR_FRAME_INVALID 0x55550000
117#define FH_RSCSR_FRAME_ALIGN 0x40
fbe41127 118#define FH_RSCSR_RPA_EN BIT(25)
9d0fc5a5 119#define FH_RSCSR_RADA_EN BIT(26)
ab2e696b
SS
120#define FH_RSCSR_RXQ_POS 16
121#define FH_RSCSR_RXQ_MASK 0x3F0000
f8d7c1a1
JB
122
123struct iwl_rx_packet {
124 /*
125 * The first 4 bytes of the RX frame header contain both the RX frame
126 * size and some flags.
127 * Bit fields:
128 * 31: flag flush RB request
129 * 30: flag ignore TC (terminal counter) request
130 * 29: flag fast IRQ request
9d0fc5a5
DS
131 * 28-27: Reserved
132 * 26: RADA enabled
fbe41127 133 * 25: Offload enabled
ab2e696b
SS
134 * 24: RPF enabled
135 * 23: RSS enabled
136 * 22: Checksum enabled
137 * 21-16: RX queue
138 * 15-14: Reserved
f8d7c1a1
JB
139 * 13-00: RX frame size
140 */
141 __le32 len_n_flags;
142 struct iwl_cmd_header hdr;
143 u8 data[];
144} __packed;
522376d2 145
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JB
146static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
147{
148 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
149}
150
151static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
152{
153 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
154}
155
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156/**
157 * enum CMD_MODE - how to send the host commands ?
158 *
e89044d7 159 * @CMD_ASYNC: Return right away and don't wait for the response
a1022927
EG
160 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of
161 * the response. The caller needs to call iwl_free_resp when done.
dcbb4746
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162 * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be
163 * called after this command completes. Valid only with CMD_ASYNC.
60396183
EG
164 */
165enum CMD_MODE {
4a4ee101
JB
166 CMD_ASYNC = BIT(0),
167 CMD_WANT_SKB = BIT(1),
4f59334b 168 CMD_SEND_IN_RFKILL = BIT(2),
043fa901 169 CMD_WANT_ASYNC_CALLBACK = BIT(3),
522376d2
EG
170};
171
172#define DEF_CMD_PAYLOAD_SIZE 320
173
174/**
175 * struct iwl_device_cmd
176 *
177 * For allocation of the command and tx queues, this establishes the overall
178 * size of the largest command we send to uCode, except for commands that
179 * aren't fully copied and use other TFD space.
180 */
181struct iwl_device_cmd {
ab02165c
AE
182 union {
183 struct {
184 struct iwl_cmd_header hdr; /* uCode API */
185 u8 payload[DEF_CMD_PAYLOAD_SIZE];
186 };
187 struct {
188 struct iwl_cmd_header_wide hdr_wide;
189 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
190 sizeof(struct iwl_cmd_header_wide) +
191 sizeof(struct iwl_cmd_header)];
192 };
193 };
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194} __packed;
195
196#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
197
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198/*
199 * number of transfer buffers (fragments) per transmit frame descriptor;
200 * this is just the driver's idea, the hardware supports 20
201 */
202#define IWL_MAX_CMD_TBS_PER_TFD 2
522376d2 203
60396183 204/**
b8aed81c 205 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command
60396183 206 *
f4feb8ac 207 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's
60396183 208 * ring. The transport layer doesn't map the command's buffer to DMA, but
e89044d7 209 * rather copies it to a previously allocated DMA buffer. This flag tells
60396183 210 * the transport layer not to copy the command, but to map the existing
3e2c1592
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211 * buffer (that is passed in) instead. This saves the memcpy and allows
212 * commands that are bigger than the fixed buffer to be submitted.
213 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one.
f4feb8ac
JB
214 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this
215 * chunk internally and free it again after the command completes. This
216 * can (currently) be used only once per command.
3e2c1592 217 * Note that a TFD entry after a DUP one cannot be a normal copied one.
60396183 218 */
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219enum iwl_hcmd_dataflag {
220 IWL_HCMD_DFL_NOCOPY = BIT(0),
f4feb8ac 221 IWL_HCMD_DFL_DUP = BIT(1),
522376d2
EG
222};
223
22463857
SM
224enum iwl_error_event_table_status {
225 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0),
226 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1),
227 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2),
228};
229
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230/**
231 * struct iwl_host_cmd - Host command to the uCode
60396183 232 *
522376d2 233 * @data: array of chunks that composes the data of the host command
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JB
234 * @resp_pkt: response packet, if %CMD_WANT_SKB was set
235 * @_rx_page_order: (internally used to free response packet)
236 * @_rx_page_addr: (internally used to free response packet)
60396183 237 * @flags: can be CMD_*
e89044d7 238 * @len: array of the lengths of the chunks in data
60396183 239 * @dataflags: IWL_HCMD_DFL_*
ab02165c
AE
240 * @id: command id of the host command, for wide commands encoding the
241 * version and group as well
522376d2
EG
242 */
243struct iwl_host_cmd {
1afbfb60 244 const void *data[IWL_MAX_CMD_TBS_PER_TFD];
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JB
245 struct iwl_rx_packet *resp_pkt;
246 unsigned long _rx_page_addr;
247 u32 _rx_page_order;
247c61d6 248
522376d2 249 u32 flags;
ab02165c 250 u32 id;
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JB
251 u16 len[IWL_MAX_CMD_TBS_PER_TFD];
252 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
522376d2 253};
41c50542 254
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JB
255static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
256{
257 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
258}
259
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260struct iwl_rx_cmd_buffer {
261 struct page *_page;
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JB
262 int _offset;
263 bool _page_stolen;
d13f1862 264 u32 _rx_page_order;
ed90542b 265 unsigned int truesize;
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JB
266};
267
268static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
269{
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JB
270 return (void *)((unsigned long)page_address(r->_page) + r->_offset);
271}
272
273static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
274{
275 return r->_offset;
930dfd5f
JB
276}
277
278static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
279{
0c19744c
JB
280 r->_page_stolen = true;
281 get_page(r->_page);
282 return r->_page;
930dfd5f
JB
283}
284
d13f1862
EG
285static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
286{
287 __free_pages(r->_page, r->_rx_page_order);
288}
289
d663ee73
JB
290#define MAX_NO_RECLAIM_CMDS 6
291
ff110c8f
GG
292#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
293
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JB
294/*
295 * Maximum number of HW queues the transport layer
296 * currently supports
297 */
298#define IWL_MAX_HW_QUEUES 32
e982bc2c
SS
299#define IWL_MAX_TVQM_QUEUES 512
300
b04db9ac 301#define IWL_MAX_TID_COUNT 8
c65f4e03 302#define IWL_MGMT_TID 15
b04db9ac 303#define IWL_FRAME_LIMIT 64
56882e6c 304#define IWL_MAX_RX_HW_QUEUES 16
9eae88fa 305
ddaf5a5b
JB
306/**
307 * enum iwl_wowlan_status - WoWLAN image/device status
308 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume
309 * @IWL_D3_STATUS_RESET: device was reset while suspended
310 */
311enum iwl_d3_status {
312 IWL_D3_STATUS_ALIVE,
313 IWL_D3_STATUS_RESET,
314};
315
eb7ff77e
AN
316/**
317 * enum iwl_trans_status: transport status flags
318 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed
319 * @STATUS_DEVICE_ENABLED: APM is enabled
320 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
321 * @STATUS_INT_ENABLED: interrupts are enabled
326477e4
JB
322 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch
323 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode
eb7ff77e 324 * @STATUS_FW_ERROR: the fw is in error state
98ee7783
AN
325 * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands
326 * are sent
327 * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent
053225de 328 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation
eb7ff77e
AN
329 */
330enum iwl_trans_status {
331 STATUS_SYNC_HCMD_ACTIVE,
332 STATUS_DEVICE_ENABLED,
333 STATUS_TPOWER_PMI,
334 STATUS_INT_ENABLED,
326477e4
JB
335 STATUS_RFKILL_HW,
336 STATUS_RFKILL_OPMODE,
eb7ff77e 337 STATUS_FW_ERROR,
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AN
338 STATUS_TRANS_GOING_IDLE,
339 STATUS_TRANS_IDLE,
053225de 340 STATUS_TRANS_DEAD,
eb7ff77e
AN
341};
342
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EG
343static inline int
344iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
345{
346 switch (rb_size) {
1a4968d1
GBA
347 case IWL_AMSDU_2K:
348 return get_order(2 * 1024);
6c4fbcbc
EG
349 case IWL_AMSDU_4K:
350 return get_order(4 * 1024);
351 case IWL_AMSDU_8K:
352 return get_order(8 * 1024);
353 case IWL_AMSDU_12K:
354 return get_order(12 * 1024);
355 default:
356 WARN_ON(1);
357 return -1;
358 }
359}
360
39bdb17e
SD
361struct iwl_hcmd_names {
362 u8 cmd_id;
363 const char *const cmd_name;
364};
365
366#define HCMD_NAME(x) \
367 { .cmd_id = x, .cmd_name = #x }
368
369struct iwl_hcmd_arr {
370 const struct iwl_hcmd_names *arr;
371 int size;
372};
373
374#define HCMD_ARR(x) \
375 { .arr = x, .size = ARRAY_SIZE(x) }
376
92d743ae
MV
377/**
378 * struct iwl_trans_config - transport configuration
379 *
380 * @op_mode: pointer to the upper layer.
c6f600fc
MV
381 * @cmd_queue: the index of the command queue.
382 * Must be set before start_fw.
b04db9ac 383 * @cmd_fifo: the fifo for host commands
4cf677fd 384 * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue.
d663ee73
JB
385 * @no_reclaim_cmds: Some devices erroneously don't set the
386 * SEQ_RX_FRAME bit on some notifications, this is the
387 * list of such notifications to filter. Max length is
388 * %MAX_NO_RECLAIM_CMDS.
389 * @n_no_reclaim_cmds: # of commands in list
6c4fbcbc 390 * @rx_buf_size: RX buffer size needed for A-MSDUs
b2cf410c 391 * if unset 4k will be the RX buffer size
046db346
EG
392 * @bc_table_dword: set to true if the BC table expects the byte count to be
393 * in DWORD (as opposed to bytes)
3a736bcb 394 * @scd_set_active: should the transport configure the SCD for HCMD queue
41837ca9 395 * @sw_csum_tx: transport should compute the TCP checksum
39bdb17e
SD
396 * @command_groups: array of command groups, each member is an array of the
397 * commands in the group; for debugging only
398 * @command_groups_size: number of command groups, to avoid illegal access
21cb3222
JB
399 * @cb_data_offs: offset inside skb->cb to store transport data at, must have
400 * space for at least two pointers
92d743ae
MV
401 */
402struct iwl_trans_config {
403 struct iwl_op_mode *op_mode;
9eae88fa 404
c6f600fc 405 u8 cmd_queue;
b04db9ac 406 u8 cmd_fifo;
4cf677fd 407 unsigned int cmd_q_wdg_timeout;
d663ee73 408 const u8 *no_reclaim_cmds;
84cf0e62 409 unsigned int n_no_reclaim_cmds;
b2cf410c 410
6c4fbcbc 411 enum iwl_amsdu_size rx_buf_size;
046db346 412 bool bc_table_dword;
3a736bcb 413 bool scd_set_active;
41837ca9 414 bool sw_csum_tx;
39bdb17e
SD
415 const struct iwl_hcmd_arr *command_groups;
416 int command_groups_size;
15ffd075 417
21cb3222 418 u8 cb_data_offs;
92d743ae
MV
419};
420
48eb7b34
EG
421struct iwl_trans_dump_data {
422 u32 len;
423 u8 data[];
424};
425
87ce05a2
EG
426struct iwl_trans;
427
fea7795f
JB
428struct iwl_trans_txq_scd_cfg {
429 u8 fifo;
2a2e9d10 430 u8 sta_id;
fea7795f 431 u8 tid;
64ba8930 432 bool aggregate;
fea7795f
JB
433 int frame_limit;
434};
435
92536c96
SS
436/**
437 * struct iwl_trans_rxq_dma_data - RX queue DMA data
438 * @fr_bd_cb: DMA address of free BD cyclic buffer
439 * @fr_bd_wid: Initial write index of the free BD cyclic buffer
440 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
441 * @ur_bd_cb: DMA address of used BD cyclic buffer
442 */
443struct iwl_trans_rxq_dma_data {
444 u64 fr_bd_cb;
445 u32 fr_bd_wid;
446 u64 urbd_stts_wrptr;
447 u64 ur_bd_cb;
448};
449
41c50542
EG
450/**
451 * struct iwl_trans_ops - transport specific operations
60396183
EG
452 *
453 * All the handlers MUST be implemented
454 *
bab3cb92
EG
455 * @start_hw: starts the HW. From that point on, the HW can send interrupts.
456 * May sleep.
a4082843 457 * @op_mode_leave: Turn off the HW RF kill indication if on
60396183 458 * May sleep
cf614297 459 * @start_fw: allocates and inits all the resources for the transport
60396183
EG
460 * layer. Also kick a fw image.
461 * May sleep
adca1235
EG
462 * @fw_alive: called when the fw sends alive notification. If the fw provides
463 * the SCD base address in SRAM, then provide it here, or 0 otherwise.
60396183 464 * May sleep
a4082843 465 * @stop_device: stops the whole device (embedded CPU put to reset) and stops
bab3cb92
EG
466 * the HW. From that point on, the HW will be stopped but will still issue
467 * an interrupt if the HW RF kill switch is triggered.
8d193ca2
EH
468 * This callback must do the right thing and not crash even if %start_hw()
469 * was called but not &start_fw(). May sleep.
ddaf5a5b 470 * @d3_suspend: put the device into the correct mode for WoWLAN during
2dd4f9f7
JB
471 * suspend. This is optional, if not implemented WoWLAN will not be
472 * supported. This callback may sleep.
ddaf5a5b
JB
473 * @d3_resume: resume the device after WoWLAN, enabling the opmode to
474 * talk to the WoWLAN image to get its status. This is optional, if not
475 * implemented WoWLAN will not be supported. This callback may sleep.
f946b529
EG
476 * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted.
477 * If RFkill is asserted in the middle of a SYNC host command, it must
478 * return -ERFKILL straight away.
a1022927 479 * May sleep only if CMD_ASYNC is not set
3f73b8ca 480 * @tx: send an skb. The transport relies on the op_mode to zero the
6eb5e529
EG
481 * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all
482 * the CSUM will be taken care of (TCP CSUM and IP header in case of
483 * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP
484 * header if it is IPv4.
60396183 485 * Must be atomic
a0eaad71 486 * @reclaim: free packet until ssn. Returns a list of freed packets.
60396183 487 * Must be atomic
b04db9ac
EG
488 * @txq_enable: setup a queue. To setup an AC queue, use the
489 * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before
d4578ea8
JB
490 * this one. The op_mode must not configure the HCMD queue. The scheduler
491 * configuration may be %NULL, in which case the hardware will not be
dcfbd67b
EG
492 * configured. If true is returned, the operation mode needs to increment
493 * the sequence number of the packets routed to this queue because of a
494 * hardware scheduler bug. May sleep.
d0624be6 495 * @txq_disable: de-configure a Tx queue to send AMPDUs
b0b46192 496 * Must be atomic
42db09c1 497 * @txq_set_shared_mode: change Tx queue shared/unshared marking
d6d517b7
SS
498 * @wait_tx_queues_empty: wait until tx queues are empty. May sleep.
499 * @wait_txq_empty: wait until specific tx queue is empty. May sleep.
e0b8d405
EG
500 * @freeze_txq_timer: prevents the timer of the queue from firing until the
501 * queue is set to awake. Must be atomic.
0cd58eaa
EG
502 * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note
503 * that the transport needs to refcount the calls since this function
504 * will be called several times with block = true, and then the queues
505 * need to be unblocked only after the same number of calls with
506 * block = false.
03905495
EG
507 * @write8: write a u8 to a register at offset ofs from the BAR
508 * @write32: write a u32 to a register at offset ofs from the BAR
509 * @read32: read a u32 register at offset ofs from the BAR
6a06b6c1
EG
510 * @read_prph: read a DWORD from a periphery register
511 * @write_prph: write a DWORD to a periphery register
4fd442db 512 * @read_mem: read device's SRAM in DWORD
01387ffd
EG
513 * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory
514 * will be zeroed.
c6f600fc 515 * @configure: configure parameters required by the transport layer from
3dc420be
EG
516 * the op_mode. May be called several times before start_fw, can't be
517 * called after that.
47107e84 518 * @set_pmi: set the power pmi state
e56b04ef
LE
519 * @grab_nic_access: wake the NIC to be able to access non-HBUS regs.
520 * Sleeping is not allowed between grab_nic_access and
521 * release_nic_access.
522 * @release_nic_access: let the NIC go to sleep. The "flags" parameter
523 * must be the same one that was sent before to the grab_nic_access.
e139dc4a 524 * @set_bits_mask - set SRAM register according to value and mask.
48eb7b34
EG
525 * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last
526 * TX'ed commands and similar. The buffer will be vfree'd by the caller.
4d075007 527 * Note that the transport must fill in the proper file headers.
f7805b33
LC
528 * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup
529 * of the trans debugfs
41c50542
EG
530 */
531struct iwl_trans_ops {
532
bab3cb92 533 int (*start_hw)(struct iwl_trans *iwl_trans);
a4082843 534 void (*op_mode_leave)(struct iwl_trans *iwl_trans);
6ae02f3e
EG
535 int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw,
536 bool run_in_rfkill);
adca1235 537 void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr);
bab3cb92 538 void (*stop_device)(struct iwl_trans *trans);
41c50542 539
e5f3f215 540 int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset);
debff618 541 int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status,
23ae6128 542 bool test, bool reset);
2dd4f9f7 543
6d8f6eeb 544 int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
41c50542 545
e13c0c59 546 int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
9eae88fa
JB
547 struct iwl_device_cmd *dev_cmd, int queue);
548 void (*reclaim)(struct iwl_trans *trans, int queue, int ssn,
549 struct sk_buff_head *skbs);
550
ba7136f3
AM
551 void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr);
552
dcfbd67b 553 bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
4cf677fd
EG
554 const struct iwl_trans_txq_scd_cfg *cfg,
555 unsigned int queue_wdg_timeout);
d4578ea8
JB
556 void (*txq_disable)(struct iwl_trans *trans, int queue,
557 bool configure_scd);
2f7a3863 558 /* 22000 functions */
6b35ff91 559 int (*txq_alloc)(struct iwl_trans *trans,
1169310f 560 __le16 flags, u8 sta_id, u8 tid,
5369774c 561 int cmd_id, int size,
6b35ff91
SS
562 unsigned int queue_wdg_timeout);
563 void (*txq_free)(struct iwl_trans *trans, int queue);
92536c96
SS
564 int (*rxq_dma_data)(struct iwl_trans *trans, int queue,
565 struct iwl_trans_rxq_dma_data *data);
41c50542 566
42db09c1
LK
567 void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
568 bool shared);
569
a1a57877 570 int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm);
d6d517b7 571 int (*wait_txq_empty)(struct iwl_trans *trans, int queue);
e0b8d405
EG
572 void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs,
573 bool freeze);
0cd58eaa 574 void (*block_txq_ptrs)(struct iwl_trans *trans, bool block);
5fdda047 575
03905495
EG
576 void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
577 void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
578 u32 (*read32)(struct iwl_trans *trans, u32 ofs);
6a06b6c1
EG
579 u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
580 void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
4fd442db
EG
581 int (*read_mem)(struct iwl_trans *trans, u32 addr,
582 void *buf, int dwords);
583 int (*write_mem)(struct iwl_trans *trans, u32 addr,
bf0fd5da 584 const void *buf, int dwords);
c6f600fc
MV
585 void (*configure)(struct iwl_trans *trans,
586 const struct iwl_trans_config *trans_cfg);
47107e84 587 void (*set_pmi)(struct iwl_trans *trans, bool state);
870c2a11 588 void (*sw_reset)(struct iwl_trans *trans);
23ba9340 589 bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags);
e56b04ef
LE
590 void (*release_nic_access)(struct iwl_trans *trans,
591 unsigned long *flags);
e139dc4a
LE
592 void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
593 u32 value);
c43fe907 594 int (*suspend)(struct iwl_trans *trans);
8e551e50 595 void (*resume)(struct iwl_trans *trans);
4d075007 596
36fb9017 597 struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,
79f033f6 598 u32 dump_mask);
f7805b33 599 void (*debugfs_cleanup)(struct iwl_trans *trans);
d1967ce6 600 void (*sync_nmi)(struct iwl_trans *trans);
41c50542
EG
601};
602
69655ebf
EG
603/**
604 * enum iwl_trans_state - state of the transport layer
605 *
606 * @IWL_TRANS_NO_FW: no fw has sent an alive response
607 * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response
608 */
609enum iwl_trans_state {
610 IWL_TRANS_NO_FW = 0,
611 IWL_TRANS_FW_ALIVE = 1,
612};
613
0f8f93d6 614/**
b7282643
LC
615 * DOC: Platform power management
616 *
b7282643
LC
617 * In system-wide power management the entire platform goes into a low
618 * power state (e.g. idle or suspend to RAM) at the same time and the
619 * device is configured as a wakeup source for the entire platform.
620 * This is usually triggered by userspace activity (e.g. the user
621 * presses the suspend button or a power management daemon decides to
622 * put the platform in low power mode). The device's behavior in this
623 * mode is dictated by the wake-on-WLAN configuration.
624 *
b7282643
LC
625 * The terms used for the device's behavior are as follows:
626 *
627 * - D0: the device is fully powered and the host is awake;
628 * - D3: the device is in low power mode and only reacts to
629 * specific events (e.g. magic-packet received or scan
630 * results found);
b7282643
LC
631 *
632 * These terms reflect the power modes in the firmware and are not to
f60e2750 633 * be confused with the physical device power state.
0f8f93d6 634 */
b7282643
LC
635
636/**
637 * enum iwl_plat_pm_mode - platform power management mode
638 *
639 * This enumeration describes the device's platform power management
f60e2750 640 * behavior when in system-wide suspend (i.e WoWLAN).
b7282643
LC
641 *
642 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this
f60e2750
EG
643 * device. In system-wide suspend mode, it means that the all
644 * connections will be closed automatically by mac80211 before
645 * the platform is suspended.
b7282643 646 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).
b7282643
LC
647 */
648enum iwl_plat_pm_mode {
649 IWL_PLAT_PM_MODE_DISABLED,
650 IWL_PLAT_PM_MODE_D3,
0f8f93d6
EP
651};
652
341bd290
SM
653/**
654 * enum iwl_ini_cfg_state
655 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given
656 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded
657 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs
658 * are corrupted. The rest of the debug TLVs will still be used
659 */
660enum iwl_ini_cfg_state {
661 IWL_INI_CFG_STATE_NOT_LOADED,
662 IWL_INI_CFG_STATE_LOADED,
663 IWL_INI_CFG_STATE_CORRUPTED,
664};
665
b8a7547d
SM
666/* Max time to wait for nmi interrupt */
667#define IWL_TRANS_NMI_TIMEOUT (HZ / 4)
668
88964b2e
SS
669/**
670 * struct iwl_dram_data
671 * @physical: page phy pointer
672 * @block: pointer to the allocated block/page
673 * @size: size of the block/page
674 */
675struct iwl_dram_data {
676 dma_addr_t physical;
677 void *block;
678 int size;
679};
4cbb8e50 680
593fae3e
SM
681/**
682 * struct iwl_fw_mon - fw monitor per allocation id
683 * @num_frags: number of fragments
684 * @frags: an array of DRAM buffer fragments
685 */
686struct iwl_fw_mon {
687 u32 num_frags;
688 struct iwl_dram_data *frags;
689};
690
505a00c0
SM
691/**
692 * struct iwl_self_init_dram - dram data used by self init process
693 * @fw: lmac and umac dram data
694 * @fw_cnt: total number of items in array
695 * @paging: paging dram data
696 * @paging_cnt: total number of items in array
697 */
698struct iwl_self_init_dram {
699 struct iwl_dram_data *fw;
700 int fw_cnt;
701 struct iwl_dram_data *paging;
702 int paging_cnt;
703};
704
91c28b83
SM
705/**
706 * struct iwl_trans_debug - transport debug related data
707 *
708 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv
709 * @rec_on: true iff there is a fw debug recording currently active
710 * @dest_tlv: points to the destination TLV for debug
711 * @conf_tlv: array of pointers to configuration TLVs for debug
712 * @trigger_tlv: array of pointers to triggers TLVs for debug
713 * @lmac_error_event_table: addrs of lmacs error tables
714 * @umac_error_event_table: addr of umac error table
715 * @error_event_table_tlv_status: bitmap that indicates what error table
716 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status
341bd290
SM
717 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state
718 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state
593fae3e
SM
719 * @fw_mon_cfg: debug buffer allocation configuration
720 * @fw_mon_ini: DRAM buffer fragments per allocation id
69f0e505 721 * @fw_mon: DRAM buffer for firmware monitor
91c28b83 722 * @hw_error: equals true if hw error interrupt was received from the FW
029c25f3 723 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location
3b589d56 724 * @active_regions: active regions
677d25b2 725 * @debug_info_tlv_list: list of debug info TLVs
a9248de4 726 * @time_point: array of debug time points
60e8abd9 727 * @periodic_trig_list: periodic triggers list
cf29c5b6
SM
728 * @domains_bitmap: bitmap of active domains other than
729 * &IWL_FW_INI_DOMAIN_ALWAYS_ON
91c28b83
SM
730 */
731struct iwl_trans_debug {
732 u8 n_dest_reg;
733 bool rec_on;
734
735 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;
736 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX];
737 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv;
738
739 u32 lmac_error_event_table[2];
740 u32 umac_error_event_table;
741 unsigned int error_event_table_tlv_status;
742
341bd290
SM
743 enum iwl_ini_cfg_state internal_ini_cfg;
744 enum iwl_ini_cfg_state external_ini_cfg;
91c28b83 745
593fae3e
SM
746 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM];
747 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM];
748
69f0e505 749 struct iwl_dram_data fw_mon;
91c28b83
SM
750
751 bool hw_error;
029c25f3 752 enum iwl_fw_ini_buffer_location ini_dest;
3b589d56
SM
753
754 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID];
677d25b2 755 struct list_head debug_info_tlv_list;
a9248de4
SM
756 struct iwl_dbg_tlv_time_point_data
757 time_point[IWL_FW_INI_TIME_POINT_NUM];
60e8abd9 758 struct list_head periodic_trig_list;
cf29c5b6
SM
759
760 u32 domains_bitmap;
91c28b83
SM
761};
762
6fbfae8e
EG
763/**
764 * struct iwl_trans - transport common data
60396183 765 *
6fbfae8e 766 * @ops - pointer to iwl_trans_ops
ed277c93 767 * @op_mode - pointer to the op_mode
286ca8eb 768 * @trans_cfg: the trans-specific configuration part
035f7ff2 769 * @cfg - pointer to the configuration
6f482e37 770 * @drv - pointer to iwl_drv
eb7ff77e 771 * @status: a bit-mask of transport status flags
a42a1844 772 * @dev - pointer to struct device * that represents the device
206eea78
JB
773 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.
774 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported.
1afb0ae4 775 * @hw_rf_id a u32 with the device RF ID
0d365ae5 776 * @hw_id: a u32 with the ID of the device / sub-device.
60396183 777 * Set during transport allocation.
9ca85961 778 * @hw_id_str: a string with info about HW ID. Set during transport allocation.
f6d0e9be 779 * @pm_support: set to true in start_hw if link pm is supported
9180ac50 780 * @ltr_enabled: set to true if the LTR is enabled
5b88792c 781 * @wide_cmd_header: true when ucode supports wide command header format
56882e6c
JB
782 * @num_rx_queues: number of RX queues allocated by the transport;
783 * the transport must set this before calling iwl_drv_start()
132db31c
GBA
784 * @iml_len: the length of the image loader
785 * @iml: a pointer to the image loader itself
59c647b6
EG
786 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
787 * The user should use iwl_trans_{alloc,free}_tx_cmd.
f042c2eb
JB
788 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
789 * starting the firmware, used for tracing
790 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
791 * start of the 802.11 header in the @rx_mpdu_cmd
bcb079a1 792 * @dflt_pwr_limit: default power limit fetched from the platform (ACPI)
b7282643
LC
793 * @system_pm_mode: the system-wide power management mode in use.
794 * This mode is set dynamically, depending on the WoWLAN values
795 * configured from the userspace at runtime.
6fbfae8e 796 */
41c50542
EG
797struct iwl_trans {
798 const struct iwl_trans_ops *ops;
ed277c93 799 struct iwl_op_mode *op_mode;
286ca8eb 800 const struct iwl_cfg_trans_params *trans_cfg;
035f7ff2 801 const struct iwl_cfg *cfg;
6f482e37 802 struct iwl_drv *drv;
69655ebf 803 enum iwl_trans_state state;
eb7ff77e 804 unsigned long status;
e6bb4c9c 805
a42a1844 806 struct device *dev;
206eea78 807 u32 max_skb_frags;
08079a49 808 u32 hw_rev;
1afb0ae4 809 u32 hw_rf_id;
99673ee5 810 u32 hw_id;
9ca85961 811 char hw_id_str[52];
a42a1844 812
f042c2eb
JB
813 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
814
f6d0e9be 815 bool pm_support;
9180ac50 816 bool ltr_enabled;
97b52cfd 817
39bdb17e
SD
818 const struct iwl_hcmd_arr *command_groups;
819 int command_groups_size;
5b88792c 820 bool wide_cmd_header;
39bdb17e 821
56882e6c
JB
822 u8 num_rx_queues;
823
132db31c
GBA
824 size_t iml_len;
825 u8 *iml;
826
59c647b6
EG
827 /* The following fields are internal only */
828 struct kmem_cache *dev_cmd_pool;
3ec45882 829 char dev_cmd_pool_name[50];
59c647b6 830
9da987ac
MV
831 struct dentry *dbgfs_dir;
832
2bfb5092
JB
833#ifdef CONFIG_LOCKDEP
834 struct lockdep_map sync_cmd_lockdep_map;
835#endif
836
91c28b83 837 struct iwl_trans_debug dbg;
505a00c0 838 struct iwl_self_init_dram init_dram;
09e350f7 839
b7282643 840 enum iwl_plat_pm_mode system_pm_mode;
700b3799 841
e6bb4c9c
EG
842 /* pointer to trans specific struct */
843 /*Ensure that this pointer will always be aligned to sizeof pointer */
cbe6ab4e 844 char trans_specific[0] __aligned(sizeof(void *));
41c50542
EG
845};
846
39bdb17e
SD
847const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
848int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
849
ed277c93 850static inline void iwl_trans_configure(struct iwl_trans *trans,
92d743ae 851 const struct iwl_trans_config *trans_cfg)
ed277c93 852{
92d743ae 853 trans->op_mode = trans_cfg->op_mode;
c6f600fc
MV
854
855 trans->ops->configure(trans, trans_cfg);
39bdb17e 856 WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg));
ed277c93
EG
857}
858
bab3cb92 859static inline int iwl_trans_start_hw(struct iwl_trans *trans)
e6bb4c9c 860{
60396183
EG
861 might_sleep();
862
bab3cb92 863 return trans->ops->start_hw(trans);
e6bb4c9c
EG
864}
865
a4082843 866static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans)
cc56feb2 867{
60396183
EG
868 might_sleep();
869
a4082843
AN
870 if (trans->ops->op_mode_leave)
871 trans->ops->op_mode_leave(trans);
69655ebf 872
a4082843 873 trans->op_mode = NULL;
b4991f3f 874
69655ebf 875 trans->state = IWL_TRANS_NO_FW;
cc56feb2
EG
876}
877
adca1235 878static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 879{
60396183
EG
880 might_sleep();
881
69655ebf 882 trans->state = IWL_TRANS_FW_ALIVE;
b04db9ac 883
adca1235 884 trans->ops->fw_alive(trans, scd_addr);
ed6a3803
EG
885}
886
0692fe41 887static inline int iwl_trans_start_fw(struct iwl_trans *trans,
6ae02f3e
EG
888 const struct fw_img *fw,
889 bool run_in_rfkill)
bdfbf092 890{
cf614297
EG
891 might_sleep();
892
f042c2eb
JB
893 WARN_ON_ONCE(!trans->rx_mpdu_cmd);
894
efbf6e3b 895 clear_bit(STATUS_FW_ERROR, &trans->status);
6ae02f3e 896 return trans->ops->start_fw(trans, fw, run_in_rfkill);
bdfbf092
EG
897}
898
bab3cb92 899static inline void iwl_trans_stop_device(struct iwl_trans *trans)
bdfbf092 900{
60396183
EG
901 might_sleep();
902
bab3cb92 903 trans->ops->stop_device(trans);
69655ebf
EG
904
905 trans->state = IWL_TRANS_NO_FW;
bdfbf092
EG
906}
907
e5f3f215
HD
908static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test,
909 bool reset)
ddaf5a5b
JB
910{
911 might_sleep();
e5f3f215
HD
912 if (!trans->ops->d3_suspend)
913 return 0;
914
915 return trans->ops->d3_suspend(trans, test, reset);
ddaf5a5b
JB
916}
917
918static inline int iwl_trans_d3_resume(struct iwl_trans *trans,
debff618 919 enum iwl_d3_status *status,
23ae6128 920 bool test, bool reset)
2dd4f9f7
JB
921{
922 might_sleep();
80de4321
EP
923 if (!trans->ops->d3_resume)
924 return 0;
925
23ae6128 926 return trans->ops->d3_resume(trans, status, test, reset);
2dd4f9f7
JB
927}
928
c43fe907 929static inline int iwl_trans_suspend(struct iwl_trans *trans)
8e551e50 930{
c43fe907
EP
931 if (!trans->ops->suspend)
932 return 0;
933
934 return trans->ops->suspend(trans);
8e551e50
EP
935}
936
937static inline void iwl_trans_resume(struct iwl_trans *trans)
938{
939 if (trans->ops->resume)
940 trans->ops->resume(trans);
941}
942
48eb7b34 943static inline struct iwl_trans_dump_data *
79f033f6 944iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask)
4d075007
JB
945{
946 if (!trans->ops->dump_data)
48eb7b34 947 return NULL;
79f033f6 948 return trans->ops->dump_data(trans, dump_mask);
4d075007 949}
4d075007 950
59c647b6
EG
951static inline struct iwl_device_cmd *
952iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
953{
0ae0bb3f 954 return kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC);
59c647b6
EG
955}
956
92fe8343
EG
957int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
958
59c647b6
EG
959static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
960 struct iwl_device_cmd *dev_cmd)
961{
1ea423b0 962 kmem_cache_free(trans->dev_cmd_pool, dev_cmd);
59c647b6
EG
963}
964
e6bb4c9c 965static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
9eae88fa 966 struct iwl_device_cmd *dev_cmd, int queue)
a0eaad71 967{
3fc07953
AN
968 if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status)))
969 return -EIO;
970
e5d15cb5 971 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
3c6acb61 972 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
e5d15cb5
EP
973 return -EIO;
974 }
69655ebf 975
9eae88fa 976 return trans->ops->tx(trans, skb, dev_cmd, queue);
a0eaad71
EG
977}
978
9eae88fa
JB
979static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue,
980 int ssn, struct sk_buff_head *skbs)
48d42c42 981{
e5d15cb5 982 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
3c6acb61 983 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
e5d15cb5
EP
984 return;
985 }
69655ebf 986
9eae88fa 987 trans->ops->reclaim(trans, queue, ssn, skbs);
48d42c42
EG
988}
989
ba7136f3
AM
990static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue,
991 int ptr)
992{
993 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
994 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
995 return;
996 }
997
998 trans->ops->set_q_ptrs(trans, queue, ptr);
999}
1000
d4578ea8
JB
1001static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
1002 bool configure_scd)
288712a6 1003{
d4578ea8
JB
1004 trans->ops->txq_disable(trans, queue, configure_scd);
1005}
1006
dcfbd67b 1007static inline bool
d4578ea8 1008iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
4cf677fd
EG
1009 const struct iwl_trans_txq_scd_cfg *cfg,
1010 unsigned int queue_wdg_timeout)
d4578ea8
JB
1011{
1012 might_sleep();
1013
e5d15cb5 1014 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
d4578ea8 1015 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
dcfbd67b 1016 return false;
e5d15cb5 1017 }
d4578ea8 1018
dcfbd67b
EG
1019 return trans->ops->txq_enable(trans, queue, ssn,
1020 cfg, queue_wdg_timeout);
288712a6
EG
1021}
1022
92536c96
SS
1023static inline int
1024iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
1025 struct iwl_trans_rxq_dma_data *data)
1026{
1027 if (WARN_ON_ONCE(!trans->ops->rxq_dma_data))
1028 return -ENOTSUPP;
1029
1030 return trans->ops->rxq_dma_data(trans, queue, data);
1031}
1032
6b35ff91
SS
1033static inline void
1034iwl_trans_txq_free(struct iwl_trans *trans, int queue)
1035{
1036 if (WARN_ON_ONCE(!trans->ops->txq_free))
1037 return;
1038
1039 trans->ops->txq_free(trans, queue);
1040}
1041
1042static inline int
1043iwl_trans_txq_alloc(struct iwl_trans *trans,
1169310f 1044 __le16 flags, u8 sta_id, u8 tid,
5369774c
SS
1045 int cmd_id, int size,
1046 unsigned int wdg_timeout)
6b35ff91
SS
1047{
1048 might_sleep();
1049
1050 if (WARN_ON_ONCE(!trans->ops->txq_alloc))
1051 return -ENOTSUPP;
1052
1053 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1054 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1055 return -EIO;
1056 }
1057
1169310f
GBA
1058 return trans->ops->txq_alloc(trans, flags, sta_id, tid,
1059 cmd_id, size, wdg_timeout);
6b35ff91
SS
1060}
1061
42db09c1
LK
1062static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
1063 int queue, bool shared_mode)
1064{
1065 if (trans->ops->txq_set_shared_mode)
1066 trans->ops->txq_set_shared_mode(trans, queue, shared_mode);
1067}
1068
4beaf6c2
EG
1069static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1070 int fifo, int sta_id, int tid,
4cf677fd
EG
1071 int frame_limit, u16 ssn,
1072 unsigned int queue_wdg_timeout)
48d42c42 1073{
fea7795f
JB
1074 struct iwl_trans_txq_scd_cfg cfg = {
1075 .fifo = fifo,
1076 .sta_id = sta_id,
1077 .tid = tid,
1078 .frame_limit = frame_limit,
64ba8930 1079 .aggregate = sta_id >= 0,
fea7795f
JB
1080 };
1081
4cf677fd 1082 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
48d42c42
EG
1083}
1084
4cf677fd
EG
1085static inline
1086void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1087 unsigned int queue_wdg_timeout)
b04db9ac 1088{
d4578ea8
JB
1089 struct iwl_trans_txq_scd_cfg cfg = {
1090 .fifo = fifo,
1091 .sta_id = -1,
1092 .tid = IWL_MAX_TID_COUNT,
1093 .frame_limit = IWL_FRAME_LIMIT,
64ba8930 1094 .aggregate = false,
d4578ea8
JB
1095 };
1096
4cf677fd 1097 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
d4578ea8
JB
1098}
1099
e0b8d405
EG
1100static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1101 unsigned long txqs,
1102 bool freeze)
1103{
e5d15cb5 1104 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
e0b8d405 1105 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
e5d15cb5
EP
1106 return;
1107 }
e0b8d405
EG
1108
1109 if (trans->ops->freeze_txq_timer)
1110 trans->ops->freeze_txq_timer(trans, txqs, freeze);
1111}
1112
0cd58eaa
EG
1113static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans,
1114 bool block)
1115{
e5d15cb5 1116 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
0cd58eaa 1117 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
e5d15cb5
EP
1118 return;
1119 }
0cd58eaa
EG
1120
1121 if (trans->ops->block_txq_ptrs)
1122 trans->ops->block_txq_ptrs(trans, block);
1123}
1124
a1a57877
SS
1125static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans,
1126 u32 txqs)
5f178cd2 1127{
d6d517b7
SS
1128 if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty))
1129 return -ENOTSUPP;
1130
e5d15cb5 1131 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
3c6acb61 1132 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
e5d15cb5
EP
1133 return -EIO;
1134 }
69655ebf 1135
a1a57877 1136 return trans->ops->wait_tx_queues_empty(trans, txqs);
5f178cd2
EG
1137}
1138
d6d517b7
SS
1139static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue)
1140{
1141 if (WARN_ON_ONCE(!trans->ops->wait_txq_empty))
1142 return -ENOTSUPP;
1143
1144 if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1145 IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1146 return -EIO;
1147 }
1148
1149 return trans->ops->wait_txq_empty(trans, queue);
1150}
1151
03905495
EG
1152static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1153{
1154 trans->ops->write8(trans, ofs, val);
1155}
1156
1157static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1158{
1159 trans->ops->write32(trans, ofs, val);
1160}
1161
1162static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)
1163{
1164 return trans->ops->read32(trans, ofs);
1165}
1166
6a06b6c1
EG
1167static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
1168{
1169 return trans->ops->read_prph(trans, ofs);
1170}
1171
1172static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs,
1173 u32 val)
1174{
1175 return trans->ops->write_prph(trans, ofs, val);
1176}
1177
4fd442db
EG
1178static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1179 void *buf, int dwords)
1180{
1181 return trans->ops->read_mem(trans, addr, buf, dwords);
1182}
1183
1184#define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \
1185 do { \
1186 if (__builtin_constant_p(bufsize)) \
1187 BUILD_BUG_ON((bufsize) % sizeof(u32)); \
1188 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\
1189 } while (0)
1190
1191static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1192{
1193 u32 value;
1194
1195 if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1)))
1196 return 0xa5a5a5a5;
1197
1198 return value;
1199}
1200
1201static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1202 const void *buf, int dwords)
4fd442db
EG
1203{
1204 return trans->ops->write_mem(trans, addr, buf, dwords);
1205}
1206
1207static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1208 u32 val)
1209{
1210 return iwl_trans_write_mem(trans, addr, &val, 1);
1211}
1212
47107e84
DF
1213static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
1214{
128cb89e
AN
1215 if (trans->ops->set_pmi)
1216 trans->ops->set_pmi(trans, state);
47107e84
DF
1217}
1218
870c2a11
GBA
1219static inline void iwl_trans_sw_reset(struct iwl_trans *trans)
1220{
1221 if (trans->ops->sw_reset)
1222 trans->ops->sw_reset(trans);
1223}
1224
e139dc4a
LE
1225static inline void
1226iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
1227{
1228 trans->ops->set_bits_mask(trans, reg, mask, value);
1229}
1230
23ba9340 1231#define iwl_trans_grab_nic_access(trans, flags) \
abae2386 1232 __cond_lock(nic_access, \
23ba9340 1233 likely((trans)->ops->grab_nic_access(trans, flags)))
7a65d170 1234
abae2386 1235static inline void __releases(nic_access)
e56b04ef 1236iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags)
7a65d170 1237{
e56b04ef 1238 trans->ops->release_nic_access(trans, flags);
abae2386 1239 __release(nic_access);
7a65d170
EG
1240}
1241
2a988e98
AN
1242static inline void iwl_trans_fw_error(struct iwl_trans *trans)
1243{
1244 if (WARN_ON_ONCE(!trans->op_mode))
1245 return;
1246
1247 /* prevent double restarts due to the same erroneous FW */
1248 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status))
1249 iwl_op_mode_nic_error(trans->op_mode);
1250}
1251
068893b7
SM
1252static inline bool iwl_trans_fw_running(struct iwl_trans *trans)
1253{
1254 return trans->state == IWL_TRANS_FW_ALIVE;
1255}
1256
d1967ce6
SM
1257static inline void iwl_trans_sync_nmi(struct iwl_trans *trans)
1258{
1259 if (trans->ops->sync_nmi)
1260 trans->ops->sync_nmi(trans);
1261}
1262
a1af4c48
SM
1263static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans)
1264{
341bd290
SM
1265 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED ||
1266 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED;
a1af4c48
SM
1267}
1268
7b501d10
JB
1269/*****************************************************
1270 * transport helper functions
1271 *****************************************************/
1272struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1273 struct device *dev,
1ea423b0 1274 const struct iwl_trans_ops *ops);
7b501d10
JB
1275void iwl_trans_free(struct iwl_trans *trans);
1276
b52e7ea1 1277/*****************************************************
d1ff5253 1278* driver (transport) register/unregister functions
b52e7ea1 1279******************************************************/
36a79223
EG
1280int __must_check iwl_pci_register_driver(void);
1281void iwl_pci_unregister_driver(void);
b52e7ea1 1282
41c50542 1283#endif /* __iwl_trans_h__ */